ISL80103IR15Z-TK [RENESAS]
ISL80103IR15Z-TK;
| 型号： | ISL80103IR15Z-TK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ISL80103IR15Z-TK |
| 文件： | 总15页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
Features
• Stable with all Capacitor Types (Note 11)
• 2A and 3A Output Current Ratings
• 2.2V to 6V Input Voltage Range
The ISL80102 and ISL80103 are low voltage,
high-current, single output LDOs specified for 2A and 3A
output current, respectively. These LDOs operate from
input voltages of 2.2V to 6V and are capable of providing
output voltages of 0.8V to 5V on the adjustable V
• ±1.8% V
Accuracy Guaranteed Over Line, Load
OUT
OUT
versions. Fixed output voltage options are available in
1.5V, 1.8V, 2.5V, 3.3V and 5V. Other custom voltage
options available upon request.
and T = -40°C to +125°C
J
• Very Low 120mV Dropout Voltage at 3A (ISL80103)
• Fixed and Adjustable V
OUT
Versions
For applications that demand in-rush current less than
the current limit, an external capacitor on the soft start
pin provides adjustment. The ENABLE feature allows the
part to be placed into a low quiescent current shutdown
mode. A sub-micron BiCMOS process is utilized for this
product family to deliver the best in class analog
performance and overall value.
• Very Fast Transient Response
• Excellent 62dB PSRR
• 100µV
RMS
Output Noise
• Power-Good Output
• Adjustable In-Rush Current Limiting
• Short Circuit and Over-Temperature Protection
These CMOS LDOs will consume significantly lower
quiescent current as a function of load over bipolar LDOs,
which translates into higher efficiency and the ability to
consider packages with smaller footprints. Quiescent
current is modestly compromised to enable a leading
class fast load transient response, and hence a lower
total AC regulation band for an LDO in this category.
• Available in a 10 Ld DFN (now), 5Ld TO220 and 5Ld
TO263 (soon)
Applications*(see page 14)
• Servers
• Telecommunications and Networking
• Medical Equipment
• Instrumentation Systems
• Routers and Switchers
Typical Application
ISL80102, ISL80103
1.8V ±1.8%
2.5V ±10%
1
2
9
V
OUT
VOUT
VOUT
V
VIN
VIN
IN
C
OUT
C
10
IN
10µF
10µF
R
PG
100kΩ
ON
3
SENSE
PG
7
6
ENABLE
SS
OFF
4
PGOOD
*C
SS
GND
5
*CSS is optional, (see Note 12) on page 5.
March 22, 2010
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved
1
FN6660.1
All other trademarks mentioned are the property of their respective owners.
ISL80102, ISL80103
Block Diagram
VIN
R5
IL/10,000
M4
M5
10µA
10µA
M3
M1
POWER PMOS
IL
VOUT
+
LEVEL
SHIFT
R8
M6
-
R1
R9
R7
EN
EN
SENSE
-
500mV
+
R2
R4
EN
ADJ
PG
+
EN
-
ENABLE
SS
M7
M8
-
+
-
M2
500mV
+
V TO I
+
-
*R3
485mV
EN
GND
*R3 is open for ADJ versions.
Ordering Information
PART NUMBER
(Notes 1, 2, 4)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
V
VOLTAGE
OUT
ISL80102IRAJZ
ISL80102IR15Z
ISL80102IR18Z
ISL80102IR25Z
ISL80102IR33Z
ISL80102IR50Z
ISL80103IRAJZ
ISL80103IR15Z
ISL80103IR18Z
ISL80103IR25Z
ISL80103IR33Z
ISL80103IR50Z
NOTES:
DZJA
ADJ
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
DZMA
DZNA
DZPA
DZRA
DZSA
DZAA
DZDA
DZEA
DZFA
DZGA
DZHA
1.5V (Note 3)
1.8V
2.5V
3.3V (Note 3)
5.0V (Note 3)
ADJ
1.5V (Note 3)
1.8V
2.5V
3.3V (Note 3)
5.0V (Note 3)
1. Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. The 1.5V, 3.3V and 5V fixed output voltages will be released in the future. Please contact Intersil Marketing for more details.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on
MSL please see tech brief TB363.
FN6660.1
March 22, 2010
2
ISL80102, ISL80103
Pin Configuration
ISL80102, ISL80103
(10 LD 3X3 DFN)
TOP VIEW
V
V
V
V
1
2
3
4
5
10
9
OUT
OUT
IN
IN
SENSE/ADJ
PG
DNC
8
7
ENABLE
SS
GND
6
Pin Descriptions
PIN NUMBER PIN NAME
DESCRIPTION
1, 2
3
V
Output voltage pin.
OUT
SENSE/ADJ Remote voltage sense for internally fixed V
options. ADJ pin for externally set V .
OUT
OUT
4
PG
V
in regulation signal. Logic low defines when V
is not in regulation. Must be grounded if
OUT
OUT
not used.
5
6
GND
SS
GND pin.
External cap adjusts in-rush current.
7
ENABLE
DNC
V
independent chip enable. TTL and CMOS compatible.
IN
8
Do not connect this pin to ground or supply. Leave floating.
Input supply pin.
9, 10
V
IN
EPAD
EPAD at ground potential. Soldering it directly to GND plane is optional.
Typical Application
ISL80102, ISL80103
1.8V
2.5V ±10%
1
2
9
V
VOUT
V
OUT
IN
VIN
VIN
C
OUT
C
10
IN
VOUT
10µF
10µF
R
PG
100kΩ
R
1
10kΩ
4
PGOOD
PG
7
6
ENABLE
SS
EN
**C
OPEN DRAIN COMPATIBLE
PB
R
3
2.61kΩ
1500pF
3
ADJ
*C
SS
GND
R
4
5
1.0kΩ
*CSS is optional, (see Note 12) on page 5.
**C
PB
is optional. See “Functional Description” on page 12 for more information.
FIGURE 1. TYPICAL APPLICATION DIAGRAM
FN6660.1
March 22, 2010
3
ISL80102, ISL80103
Absolute Maximum Ratings (Note 7)
Thermal Information
V
V
relative to GND . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
θ
JA (°C/W) θJC (°C/W)
48
IN
relative to GND . . . . . . . . . . . . . . . . . -0.3V to +6.5V
OUT
10 Ld 3x3 DFN Package (Notes 5, 6)
4
PG, ENABLE, SENSE/ADJ, SS
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range. . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Relative to GND. . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Recommended Operating Conditions
(Note 10)
Junction Temperature Range (T ) . . . . . . . -40°C to +125°C
J
VIN relative to GND . . . . . . . . . . . . . . . . . . . . . 2.2V to 6V
V
range . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5V
OUT
PG, ENABLE, SENSE/ADJ, SS relative to GND . . . . . 0V to 6V
PG sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
6. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified
conditions: V = V
+ 0.4V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A
IN OUT
OUT
IN
OUT
J
LOAD
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure T = T defines established limits.
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8) TYP (Note 8) UNITS
DC CHARACTERISTICS
DC Output Voltage Accuracy
V
V
V
Options: 1.8V.
OUT
0.5
0.5
%
%
%
%
OUT
=2.2V; I
= 0A
IN
LOAD
V
Options: 1.8V.
-1.8
1.8
OUT
2.2V < V < 3.6V; 0A < I
< 3A
IN
LOAD
V
V
Options: 2.5V
OUT
IN
=V
+ 0.4V; I
LOAD
= 0A
OUT
V
V
Options: 2.5V
+ 0.4V < V < 6V; 0A < I
IN LOAD
-1.8
491
-1.8
OUT
OUT
< 3A
Feedback Pin (ADJ Version)
DC Input Line Regulation
V
2.2V < V < 6V, 0A < I
IN
< 3A
LOAD
500
0.1
0.1
509
0.4
0.8
mV
%
FB
ΔV
/ΔV
V
V
+ 0.4V < V < 3.6V, V
= 1.8V
= 2.5V
OUT
IN
OUT
OUT
IN OUT
+ 0.4V < V < 6V, V
%
IN OUT
DC Output Load Regulation
ΔV
/ΔI
0A < I
< 3A, All voltage options
< 2A, All voltage options
-0.8
-0.6
%
OUT
OUT
LOAD
LOAD
0A < I
%
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
7.5
8.5
0.4
3.3
120
81
1
9
µA
mA
mA
µA
µA
mV
mV
ADJ
I
I
I
= 0A, 2.2V < V < 6V
IN
Q
LOAD
LOAD
= 3A, 2.2V < V < 6V
IN
12
Ground Pin Current in
Shutdown
I
ENABLE Pin = 0.2V, V = 5V
IN
SHDN
ENABLE Pin = 0.2V, V = 6V
IN
16
Dropout Voltage (Note 9)
V
I
I
= 3A, V
= 2.5V, 10 LD 3x3 DFN
= 2.5V, 10 LD 3x3 DFN
185
125
DO
LOAD
LOAD
OUT
OUT
= 2A, V
FN6660.1
March 22, 2010
4
ISL80102, ISL80103
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified
conditions: V = V
+ 0.4V, V
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A
IN OUT
OUT
IN
OUT
J
LOAD
Applications must follow thermal guidelines of the package to determine worst case junction
temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C.
Pulse load techniques used by ATE to ensure T = T defines established limits.
J
A
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8) TYP (Note 8) UNITS
Output Short Circuit Current
(3A Version)
ISC
V
V
V
V
= 0V, V
+ 0.4V < V < 6V
IN
5.0
2.8
160
15
A
A
OUT
OUT
OUT
OUT
OUT
Output Short Circuit Current
(2A Version)
= 0V, V
+ 0.4V < V < 6V
IN
OUT
Thermal Shutdown
Temperature
TSD
+ 0.4V < V < 6V
IN
°C
°C
Thermal Shutdown
Hysteresis (Rising Threshold)
TSDn
+ 0.4V < V < 6V
IN
AC CHARACTERISTICS
Input Supply Ripple
Rejection
PSRR
f = 1kHz, I
LOAD
= 1A; V = 2.2V
IN
55
62
dB
f = 120Hz, I
= 1A; V = 2.2V
IN
LOAD
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz
100
µV
LOAD
RMS
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
V
2.2V < V < 6V
IN
0.3
0.8
135
150
0.95
1
V
EN(HIGH)
Hysteresis (Rising Threshold)
Enable Pin Turn-on Delay
Enable Pin Leakage Current
V
2.2V < V < 6V
IN
mV
EN(HYS)
t
C
V
= 10µF, I
= 1A
µs
EN
OUT
LOAD
= 6V, EN = 3V
µA
IN
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
Soft Start Charge Current
PG PIN CHARACTERISTICS
R
323
-4.5
Ω
PD
I
-7
-2
µA
CHG
V
V
PG Flag Threshold
PG Flag Hysteresis
75
84
4
92
%V
OUT
OUT
OUT
%
mV
µA
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
I
= 500µA
47
100
1
SINK
V
= 6V, PG = 6V
0.05
IN
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Dropout is defined by the difference in supply V and V
IN
when the supply produces a 2% drop in V
from its nominal
OUT
OUT
value.
10. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current =
lifetime average current.
11. Minimum cap of 10µF X5R/X7R on V and V
required for stability.
12. If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance
IN OUT
required on V
for application.
OUT
FN6660.1
March 22, 2010
5
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A.
OUT
J
L
1.8
1.2
0.6
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+125°C
+25°C
-40°C
-0.6
-1.2
-1.8
0
1
2
3
4
5
6
-50
-25
0
25
50
75
100 125 150
SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 3. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
FIGURE 2. ΔV
vs TEMPERATURE
OUT
1.8
9
8
7
6
5
4
3
2
1
0
1.2
0.6
+25°C
0.0
-0.6
-1.2
-1.8
-40°C
+125°C
1.0
0
0.5
1.5
2.0
2.5
3.0
2
3
4
5
6
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 5. GROUND CURRENT vs SUPPLY VOLTAGE
FIGURE 4. ΔV
vs OUTPUT CURRENT
OUT
12.0
11.5
9.1
8.9
8.7
8.5
8.3
8.1
7.9
7.7
7.5
11.0
10.5
10.0
9.5
-40°C
-40°C
+25°C
9.0
+125°C
+125°C
1.0
8.5
+25°C
2.0
8.0
7.5
0
0.5
1.5
2.0
2.5
3.0
0.8
1.4
2.6
3.2
3.8
4.4
5.0
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
FIGURE 7. GROUND CURRENT vs OUTPUT VOLTAGE
FIGURE 6. GROUND CURRENT vs OUTPUT CURRENT
FN6660.1
March 22, 2010
6
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
OUT
IN
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
11
10
9
8
7
6
5
4
3
2
V
= 5V
IN
V
= 6V
IN
1
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 9. SHUTDOWN CURRENT vs TEMPERATURE
FIGURE 8. SHUTDOWN CURRENT vs TEMPERATURE
150
140
130
120
110
100
90
80
70
60
50
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
2A
3A
40
30
20
10
1A
0
0
0.5
1.0
1.5
2.0
2.5
3.0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OUTPUT CURRENT (A)
FIGURE 10. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 11. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
V
(1V/DIV)
IN
SS (1V/DIV)
V
(1V/DIV)
OUT
PG (1V/DIV)
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
TIME (10ms/DIV)
FIGURE 13. POWER-UP (V
= 2.2V)
FIGURE 12. ENABLE THRESHOLD VOLTAGE vs
TEMPERATURE
IN
FN6660.1
March 22, 2010
7
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
EN (1V/DIV)
V
(1V/DIV)
IN
SS (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
V
(1V/DIV)
OUT
OUT
PG (1V/DIV)
PG (1V/DIV)
TIME (50µs/DIV)
TIME (10ms/DIV)
FIGURE 15. ENABLE START-UP
FIGURE 14. POWER-DOWN (V
= 2.2V)
IN
300
250
200
150
100
50
EN (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
OUT
0
PG (1V/DIV)
2.0
2.5 3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
TIME (5ms/DIV)
FIGURE 16. ENABLE SHUTDOWN
FIGURE 17. START-UP TIME vs SUPPLY VOLTAGE
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
300
250
200
150
100
50
ISL80103
ISL80102
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 18. START-UP TIME vs TEMPERATURE
FIGURE 19. CURRENT LIMIT vs TEMPERATURE
FN6660.1
March 22, 2010
8
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ISL80103
ISL80102
V
(1V/DIV)
OUT
I
(1A/DIV)
OUT
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
INPUT VOLTAGE (V)
TIME (10ms/DIV)
FIGURE 21. CURRENT LIMIT RESPONSE (ISL80102)
FIGURE 20. CURRENT LIMIT vs SUPPLY VOLTAGE
V
(1V/DIV)
OUT
V
(1V/DIV)
OUT
I
(1A/DIV)
OUT
I
(2A/DIV)
OUT
TIME (100ms/DIV)
TIME (20ms/DIV)
FIGURE 23. CURRENT LIMIT RESPONSE (ISL80103)
FIGURE 22. THERMAL CYCLING (ISL80102)
EN (1V/DIV)
V
(1V/DIV)
OUT
I
(2A/DIV)
(1V/DIV)
OUT
I
(2A/DIV)
OUT
V
OUT
TIME (1ms/DIV)
TIME (50ms/DIV)
FIGURE 25. IN-RUSH CURRENT WITH NO
SOFT-START CAPACITOR, C
FIGURE 24. THERMAL CYCLING (ISL80103)
= 1000µF
OUT
FN6660.1
March 22, 2010
9
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN OUT
= 10µF, T = +25°C, I = 0A. (Continued)
OUT
J
L
EN (1V/DIV)
EN (1V/DIV)
I
(2A/DIV)
(1V/DIV)
I
(2A/DIV)
OUT
OUT
V
(1V/DIV)
V
OUT
OUT
TIME (1ms/DIV)
TIME (1ms/DIV)
FIGURE 26. IN-RUSH WITH 22nF SOFT-START
CAPACITOR, C = 1000µF
FIGURE 27. IN-RUSH WITH 47nF SOFT-START
CAPACITOR, C = 1000µF
OUT
OUT
V
(50mV/DIV)
(2A/DIV)
OUT
V
(50mV/DIV)
(2A/DIV)
OUT
I
OUT
I
OUT
di/dt = 30A/µs
di/dt = 30A/µs
TIME (200µs/DIV)
TIME (200µs/DIV)
FIGURE 28. LOAD TRANSIENT 0A TO 3A,
FIGURE 29. LOAD TRANSIENT 0A TO 3A,
C
= 10µF CERAMIC
C
= 10µF CERAMIC + 100µF OSCON
OUT
OUT
V
(50mV/DIV)
V
(50mV/DIV)
OUT
OUT
I
(2A/DIV)
I
(2A/DIV)
OUT
OUT
di/dt = 30A/µs
di/dt = 30A/µs
TIME (200µs/DIV)
TIME (200µs/DIV)
FIGURE 30. LOAD TRANSIENT 1A TO 3A,
FIGURE 31. LOAD TRANSIENT 1A TO 3A,
= 10µF CERAMIC + 100µF OSCON
C
= 10µF CERAMIC
C
OUT
OUT
FN6660.1
March 22, 2010
10
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN OUT
= 1.8V, C = C = 10µF, T = +25°C, I = 0A. (Continued)
IN OUT J L
V
(20mV/DIV)
OUT
V
(20mV/DIV)
OUT
(2A/DIV)
I
I
(2A/DIV)
OUT
OUT
di/dt = 3A/µs
TIME (50µs/DIV)
di/dt = 3A/µs
TIME (50µs/DIV)
FIGURE 32. LOAD TRANSIENT 0A TO 3A,
= 10µF CERAMIC, No C
FIGURE 33. LOAD TRANSIENT 0A TO 3A,
= 10µF CERAMIC, C
C
(ADJ
PB
OUT
C
= 1500pF
PB
OUT
(ADJ VERSION)
VERSION)
3.2V
2.2V
80
70
60
50
40
30
20
10
0
V
(1V/DIV)
IN
1A
100mA
10k
V
(10mV/DIV)
OUT
10
100
1k
100k
1M
TIME (200µs/DIV)
FREQUENCY (Hz)
FIGURE 35. PSRR vs LOAD
FIGURE 34. LINE TRANSIENT
80
70
60
50
40
30
20
10
0
10
1
100µF
0.1
10µF
47µF
100k
I
= 100mA
L
0.01
10
100
1k
10k
100k
1M
10
100
1k
10k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 37. SPECTRAL NOISE DENSITY vs
FREQUENCY
FIGURE 36. PSRR vs C
OUT
FN6660.1
March 22, 2010
11
ISL80102, ISL80103
capacitances on V
current can be seen for a significant period of time. The
where high levels of charging
OUT
Functional Description
in-rush currents can cause V to drop below minimum
Input Voltage Requirements
IN
which could cause V
OUT
to shutdown. Figure 38 shows
Despite other output voltages offered, this family of LDOs
is optimized for a true 2.5V to 1.8V conversion where the
input supply can have a tolerance of as much as ±10%
for conditions noted in the “Electrical Specifications” table
on page 4. Minimum guaranteed input voltage is 2.2V,
however, due to the nature of an LDO, V must be some
margin higher than the output voltage plus dropout at
the maximum rated current of the application if active
the relationship between in-rush current and C with a
SS
C
of 1000µF.
OUT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
IN
filtering (PSRR) is expected from V to V
. The
IN OUT
dropout spec of this family of LDOs has been generously
specified in order to allow applications to design for a
level of efficiency that can accommodate the smaller
outline package for those applications that cannot
accommodate the profile of the TO220/263.
0
0
20
40
C
60
(nF)
80
100
Enable Operation
SS
The Enable turn-on threshold is typically 770mV with a
hysteresis of 135mV. An internal pull-up or pull-down
resistor is available upon request. As a result, this pin
FIGURE 38. IN-RUSH CURRENT vs SOFT-START
CAPACITANCE
Output Voltage Selection
must not be left floating. This pin must be tied to V if it
IN
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage. This
voltage is then fed back to the error amplifier. The output
voltage can be programmed to any level between 0.8V
is not used. A 1kΩ to 10kΩ pull-up resistor will be
required for applications that use open collector or open
drain outputs to control the Enable pin. The Enable pin
may be connected directly to V for applications that are
IN
and 5V. An external resistor divider, R and R , is used to
3
4
always on.
set the output voltage as shown in Equation 1. The
recommended value for R is 500Ω to 1kΩ. R is then
chosen according to Equation 2:
Power-Good Operation
4
3
Applications not using this feature must connect this pin
to ground. The PGOOD flag is an open-drain NMOS that
can sink up to 10mA during a fault condition. The PGOOD
pin requires an external pull-up resistor which is typically
connected to the VOUT pin. The PGOOD pin should not
R
⎛
⎜
⎝
⎞
3
(EQ. 1)
(EQ. 2)
------
V
= 0.5V ×
+ 1
⎟
OUT
R
4
⎠
V
OUT
⎛
⎝
⎞
---------------
R
= R
×
4
– 1
be pulled up to a voltage source greater than V . The
3
⎠
IN
0.5V
PGOOD fault can be caused by the output voltage going
below 84% of the nominal output voltage, or the current
limit fault, or low input voltage. The PGOOD does not
function during thermal shutdown. The PGOOD functions
in shutdown.
External Capacitor Requirements
External capacitors are required for proper operation.
Careful attention must be paid to the layout guidelines
and selection of capacitor type and value to ensure
optimal performance.
Soft-Start Operation (Optional)
OUTPUT CAPACITOR
If the current limit for in-rush current is acceptable in the
application, do not use this feature. The soft-start circuit
controls the rate at which the output voltage comes up to
regulation at power-up or LDO enable. A constant
current charges an external soft-start capacitor. The
external capacitor always gets discharged to ground pin
potential at the beginning of start-up or enabling. The
The ISL80102, ISL80103 applies state-of-the-art internal
compensation to keep selection of the output capacitor
simple for the customer. Stable operation over full
temperature, V range, V
range and load extremes
IN OUT
are guaranteed for all capacitor types and values
assuming a 10µF X5R/X7R is used for local bypass on
discharge rate is the RC time constant of R and C
See Figures 25 through 28 in the “Typical Operating
.
PD
SS
V
. This minimum capacitor must be connected to
and Ground pins of the LDO with PCB traces no
OUT
V
OUT
Performance Curves” beginning on page 10. R
is the
PD
longer than 0.5cm.
ON-resistance of the pull down MOSFET, M8. R is 300Ω
PD
Lower cost Y5V and Z5U type ceramic capacitors are
acceptable if the size of the capacitor is larger to
compensate for the significantly lower tolerance over
X5R/X7R types. Additional capacitors of any value in
Ceramic, POSCAP or Alum/Tantalum Electrolytic types
may be placed in parallel to improve PSRR at higher
typically.
The soft-start feature effectively reduces the in-rush
current at power-up or LDO enable until V
reaches
OUT
regulation. The in-rush current can be an issue for
applications that require large, external bulk
FN6660.1
March 22, 2010
12
ISL80102, ISL80103
frequencies and/or load transient AC output voltage
tolerances.
(Note 10)” on page 4. The power dissipation can be
calculated by using Equation 3:
(EQ. 3)
P
= (V – V
) × I
+ V × I
OUT IN GND
INPUT CAPACITOR
D
IN
OUT
The minimum input capacitor required for proper
operation is 10µF having a ceramic dielectric. This
The maximum allowable junction temperature, T
and the maximum expected ambient temperature,
J(MAX)
minimum capacitor must be connected to V and
IN
T
will determine the maximum allowable power
A(MAX)
dissipation as shown in Equation 4:
ground pins of the LDO with PCB traces no longer than
0.5cm.
(EQ. 4)
P
= (T
– T ) ⁄ θ
J(MAX) A JA
D(MAX)
Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable
with 10µF or larger ceramic capacitor.
Where θ is the junction-to-ambient thermal
resistance.
JA
Applications using the ADJ versions, may see improved
performance with the addition of a small ceramic
For safe operation, please make sure that power
dissipation calculated in Equation 3, P be less than the
D
capacitor C as shown in Figure 1 on page 3. The
PB
maximum allowable power dissipation P
.
D(MAX)
conditions where C may be beneficial are: (1) V
PB OUT
>
1.5V, (2) C
= 10µF, and (3) tight AC voltage
regulation band.
The DFN package uses the copper area on the PCB as a
heat-sink. The EPAD of this package must be soldered to
the copper plane (GND plane) for heat sinking. Figure 39
OUT
C
C
introduces phase lead with the product of R and
3
PB
PB
shows a curve for the θ of the DFN package for
JA
that results in increasing the bandwidth of the LDO.
different copper area sizes.
Typical R3 x C should be 4μs.
PB
46
44
42
40
38
36
34
C
not recommended for V
< 1.5V.
OUT
PB
Current Limit Protection
The ISL80102, ISL80103 family of LDOs incorporates
protection against overcurrent due to short, overload
condition applied to the output and the in-rush current
that occurs at start-up. The LDO performs as a constant
current source when the output current exceeds the
current limit threshold noted in the “Electrical
2
4
6
8
10 12 14 16 18 20 22 24
2
Specifications” table on page 4. If the short or overload
condition is removed from V
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
, then the output returns
OUT
to normal voltage mode regulation. In the event of an
overload condition, the LDO might begin to cycle on and
off due to the die temperature exceeding the thermal
fault condition. The TO220/263 package will tolerate
higher levels of power dissipation on the die which may
never thermal cycle if the heatsink of this larger package
can keep the die temperature below the specified typical
thermal shutdown temperature.
FIGURE 39. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB
WITH THERMAL VIAS θ vs EPAD-MOUNT
JA
COPPER LAND AREA ON PCB
Thermal Fault Protection
In the event the die temperature exceeds typically
+160°C, then the output of the LDO will shut down until
the die temperature can cool down to typically +145°C.
The level of power combined with the thermal impedance
of the package (+48°C/W for DFN) will determine if the
junction temperature exceeds the thermal shutdown
temperature.
Power Dissipation and Thermals
The junction temperature must not exceed the range
specified in the “Recommended Operating Conditions
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6660.1
March 22, 2010
13
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
3/4/10
FN6660.1
Corrected Features on page 1 as follows:
-Changed bullet "• 185mV Dropout @ 3A, 125mV Dropout @ 2A" to "• Very Low 120mV
Dropout at 3A"
-Changed bullet "• 65dB Typical PSRR" to "• 62dB Typical PSRR"
-Deleted 0.5% Initial VOUT Accuracy
Modified Figure 1 and placed as Typical Application on Page 1.
Moved Pinout to page 3
In "Block Diagram" on page 2, corrected resistor associated with M5 from R4 to R5
Updated Block Diagram on page 2 as follows”
- Added M8 from SS to ground.
Updated Figure 1 on page 3 as follows:
-Corrected Pin 6 from SS to IRSET
-Removed Note 12 callout "Minimum cap on VIN and VOUT required for stability." Added Note
"*CSS is optional. See Note 12 on Page 5." and “** CPB is optional. See “Functional
Description” on page 12 for more information.”
Added "The 1.5V, 3.3V and 5V fixed output voltages will be released in the future." to Note 3
on page 2.
In “Thermal Information” on page 4, updated Theta JA from 45 to 48 per ASYD
In “Soft-Start Operation (Optional)” on page 12:
-Changed "The external capacitor always gets discharged to 0V at start-up of after coming out
of a chip disable." to "The external capacitor always gets discharged to ground pin potential at
start-up or enabling."
-Changed "The soft-start function effectively limits the amount of in-rush current below the
programmed current limit during start-up or an enable sequence to avoid an overcurrent fault
condition." to "The soft-start feature effectively reduces the in-rush current at power-up or
LDO enable until VOUT reaches regulation."
-Added "See Figures 25 through 27 in the “Typical Operating Performance Curves” beginning
on page 9."
-Added “RPD is the on resistance of the pull down MOSFET, M8. RPD is 300Ohms typically.”
Added "Phase Boost Capacitor (CPB)" section on page 13.
In “Typical Operating Performance” on page 11, revised figure "PSRR vs VIN" which had 3
curves with "Spectral Noise Density vs Frequency" which has one curve.
Added "FIGURE 32. LOAD TRANSIENT 0A TO 3A, COUT = 10µF CERAMIC, NO CPB (ADJ
VERSION)" and "FIGURE 33. LOAD TRANSIENT 1A TO 3A, COUT = 10µF CERAMIC, CPB =
1500pF (ADJ VERSION)"
09/30/09
FN6660.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL80102, ISL80103
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
6
3.00
A
B
PIN #1 INDEX AREA
1
2
6
PIN 1
INDEX AREA
10 x 0.23
4
(4X)
0.10
1.60
10x 0.35
4
TOP VIEW
BOTTOM VIEW
C A B
M
0.10
(4X)
0.415
0.23
PACKAGE
OUTLINE
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
5
0.20 REF
0.05
C
1.60
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6660.1
March 22, 2010
15
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