ISL80103IRAJZ-T13 [RENESAS]
ADJUSTABLE POSITIVE LDO REGULATOR;
| 型号： | ISL80103IRAJZ-T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | ADJUSTABLE POSITIVE LDO REGULATOR 信息通信管理 光电二极管 输出元件 调节器 |
| 文件： | 总16页 (文件大小：741K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance 2A and 3A Linear Regulators
ISL80102, ISL80103
The ISL80102 and ISL80103 are low voltage, high-current, single
output LDOs specified for 2A and 3A output current, respectively.
These LDOs operate from the input voltages of 2.2V to 6V and
are capable of providing the output voltages of 0.8V to 5V on the
Features
• Stable with all capacitor types (Note 10)
• 2A and 3A output current ratings
• 2.2V to 6V input voltage range
adjustable V
versions. Fixed output voltage options are
OUT
• ±1.8% V
OUT
accuracy guaranteed over line, load and
available in 1.8V, 2.5V, 3.3V and 5V. Other custom voltage
options available upon request.
T = -40°C to +125°C
J
• Very low 120mV dropout voltage at 3A (ISL80103)
For applications that demand in-rush current less than the
current limit, an external capacitor on the soft-start pin provides
adjustment. The ENABLE feature allows the part to be placed into
a low quiescent current shutdown mode. A sub-micron BiCMOS
process is utilized for this product family to deliver the best in
class analog performance and overall value.
• Fixed and adjustable V
OUT
versions
• Very fast transient response
• Excellent 62dB PSRR
• 100µV
output noise
RMS
These CMOS (LDOs) will consume significantly lower quiescent
current as a function of load over bipolar LDOs, which translates
into higher efficiency and the ability to consider packages with
smaller footprints. The quiescent current has been modestly
compromised to enable a leading class fast load transient
response, and hence a lower total AC regulation band for an LDO
in this category.
• Power-good output
• Adjustable in-rush current limiting
• Short circuit and over-temperature protection
• Available in a 10 Ld DFN
• Servers
• Telecommunications and networking
• Medical equipment
• Instrumentation systems
• Routers and switchers
ISL80102, ISL80103
1.8V ±1.8%
2.5V ±10%
1
2
9
V
OUT
V
V
V
V
V
IN
OUT
IN
IN
C
C
10
OUT
IN
OUT
10µF
10µF
R
PG
100kΩ
ON
3
4
SENSE
PG
7
6
ENABLE
SS
OFF
PGOOD
*C
SS
GND
5
*CSS is optional, (see Note 11) on page 5.
FIGURE 1. TYPICAL APPLICATION
June 14, 2013
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009-2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
FN6660.6
ISL80102, ISL80103
Block Diagram
VIN
R5
IL/10,000
M4
10µA
10µA
M5
M3
M1
POWER PMOS
IL
VOUT
+
-
LEVEL
SHIFT
R8
R9
M6
R1
R7
EN
SENSE
-
500mV
+
EN
R2
R4
EN
ADJ
PG
+
EN
-
ENABLE
SS
M7
M8
-
+
-
M2
500mV
+
V TO I
+
-
*R3
485mV
EN
GND
*R3 is open for ADJ versions.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
V
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG
DWG. #
OUT
VOLTAGE
ISL80102IRAJZ
DZJA
DZNA
DZPA
DZAA
DZEA
DZFA
ADJ
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
-40 to +125
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
10 Ld 3x3 DFN
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
L10.3x3
ISL80102IR18Z
ISL80102IR25Z
ISL80103IRAJZ
ISL80103IR18Z
ISL80103IR25Z
ISL80102EVAL2Z
ISL80103EVAL2Z
NOTES:
1.8V
2.5V
ADJ
1.8V
2.5V
Evaluation Board
Evaluation Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80102, ISL80103. For more information on MSL please see tech brief
TB363.
FN6660.6
June 14, 2013
2
ISL80102, ISL80103
Pin Configuration
ISL80102, ISL80103
(10 LD 3x3 DFN)
TOP VIEW
V
V
V
V
1
2
3
4
5
10
9
OUT
OUT
IN
IN
SENSE/ADJ
PG
DNC
8
7
ENABLE
SS
GND
6
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
VOUT
Output voltage pin.
3
4
SENSE/ADJ Remote voltage sense for internally fixed VOUT options. ADJ pin for externally set VOUT.
PG
GND
SS
VOUT in regulation signal. Logic low defines when VOUT is not in regulation. Must be grounded if not used.
5
GND pin.
6
External cap adjusts in-rush current.
VIN independent chip enable. TTL and CMOS compatible.
Do not connect this pin to ground or supply. Leave floating.
Input supply pin.
7
ENABLE
DNC
8
9, 10
VIN
EPAD
EPAD must be connected to copper plane with as many vias as possible for proper electrical and optimal thermal
performance.
Typical Application
ISL80102, ISL80103
1.8V
2.5V ±10%
1
2
9
V
V
V
V
OUT
OUT
OUT
V
V
IN
IN
C
OUT
C
10
IN
IN
10µF
10µF
R
PG
100kΩ
R
1
10kΩ
4
PGOOD
PG
7
6
ENABLE
SS
EN
OPEN DRAIN COMPATIBLE
**C
PB
R
3
2.61kΩ
1500pF
3
ADJ
*C
SS
GND
R
4
5
1.0kΩ
*CSS is optional, (see Note 11) on page 5.
**C is optional. See “Functional Description” on page 12 for more information.
PB
FIGURE 2. TYPICAL APPLICATION DIAGRAM
FN6660.6
June 14, 2013
3
ISL80102, ISL80103
Absolute Maximum Ratings (Note 6)
Thermal Information
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
10 Ld 3x3 DFN Package (Notes 4, 5). . . . .
θ
JA (°C/W)
45
θ
JC (°C/W)
IN
OUT
4
PG, ENABLE, SENSE/ADJ, SS, Relative to GND. . . . . . . . . . . -0.3V to +6.5V
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions (Note 8)
Junction Temperature Range (T ) . . . . . . . . . . . . . . . . . . .-40°C to +125°C
J
VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V
V
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V
OUT
PG, ENABLE, SENSE/ADJ, SS Relative to GND . . . . . . . . . . . . . . . . 0V to 6V
PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. ABS max voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
7. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current.
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
V
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C = C
IN
= 10µF, T = +25°C, I
= 0A. Applications must follow thermal guidelines of the package to
IN
OUT
J
LOAD
determine worst case junction temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T = T defines
J
A
established limits.
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
0.5
(Note 8)
UNITS
DC CHARACTERISTICS
DC Output Voltage Accuracy
V
V
V
Options: 1.8V.
OUT
%
%
%
%
OUT
=2.2V; I
= 0A
IN
LOAD
V
Options: 1.8V.
-1.8
1.8
OUT
2.2V < V < 3.6V; 0A < I
< 3A
LOAD
IN
LOAD
= 0A
V
V
Options: 2.5V
0.5
OUT
=V
+ 0.4V; I
IN OUT
LOAD
V
V
Options: 2.5V
-1.8
491
-1.8
OUT
OUT
+ 0.4V < V < 6V; 0A < I
< 3A
IN
Feedback Pin (ADJ Version)
DC Input Line Regulation
V
2.2V < V < 6V, 0A < I
IN
< 3A
LOAD
500
0.1
0.1
509
0.4
0.8
mV
%
FB
ΔV /ΔV
OUT
V
+ 0.4V < V < 3.6V, V = 1.8V
IN OUT
IN
OUT
OUT
V
+ 0.4V < V < 6V, V
= 2.5V
%
IN OUT
DC Output Load Regulation
ΔV
/ΔI
0A < I
0A < I
< 3A, All voltage options
< 2A, All voltage options
-0.8
-0.6
%
OUT
OUT
LOAD
LOAD
%
Feedback Input Current
Ground Pin Current
V
= 0.5V
0.01
7.5
1
9
µA
mA
mA
µA
µA
mV
mV
A
ADJ
I
I
I
= 0A, 2.2V < V < 6V
IN
Q
LOAD
LOAD
= 3A, 2.2V < V < 6V
IN
8.5
0.4
3.3
120
81
12
Ground Pin Current in Shutdown
Dropout Voltage (Note 9)
I
ENABLE Pin = 0.2V, V = 5V
IN
SHDN
ENABLE Pin = 0.2V, V = 6V
IN
16
V
I
I
= 3A, V
= 2.5V, 10 LD 3x3 DFN
= 2.5V, 10 LD 3x3 DFN
185
125
DO
LOAD
LOAD
OUT
OUT
= 2A, V
Output Short Circuit Current
(3A Version)
ISC
V
= 0V, V
+ 0.4V < V < 6V
IN
5.0
OUT
OUT
Output Short Circuit Current
(2A Version)
V
= 0V, V
+ 0.4V < V < 6V
IN
2.8
A
OUT
OUT
FN6660.6
June 14, 2013
4
ISL80102, ISL80103
Electrical Specifications Unless otherwise noted, all parameters are established over the following specified conditions:
V
= V
OUT
+ 0.4V, V
OUT
= 1.8V, C = C
IN
= 10µF, T = +25°C, I
= 0A. Applications must follow thermal guidelines of the package to
IN
OUT
J
LOAD
determine worst case junction temperature. Please refer to “Functional Description” on page 12 and Tech Brief TB379.
Boldface limits apply over the operating temperature range, -40°C to +125°C. Pulse load techniques used by ATE to ensure T = T defines
J
A
established limits. (Continued)
MIN
MAX
PARAMETER
SYMBOL
TSD
TEST CONDITIONS
(Note 8)
TYP
160
15
(Note 8)
UNITS
°C
Thermal Shutdown Temperature
V
V
+ 0.4V < V < 6V
OUT
IN
Thermal Shutdown Hysteresis
(Rising Threshold)
TSDn
+ 0.4V < V < 6V
°C
OUT
IN
AC CHARACTERISTICS
Input Supply Ripple Rejection
PSRR
f = 1kHz, I
= 1A; V = 2.2V
IN
55
62
dB
dB
LOAD
f = 120Hz, I
= 1A; V = 2.2V
IN
LOAD
Output Noise Voltage
I
= 10mA, BW = 300Hz < f < 300kHz
100
µV
RMS
LOAD
ENABLE PIN CHARACTERISTICS
Turn-on Threshold
V
2.2V < V < 6V
IN
0.616
0.463
0.8
0.6
0.95
V
V
EN(HIGH)
Turn-off Threshold
V
2.2V < V < 6V
IN
EN(LOW)
Hysteresis
V
2.2V < V < 6V
IN
135
150
mV
EN(HYS)
Enable Pin Turn-on Delay
Enable Pin Leakage Current
SOFT-START CHARACTERISTICS
Reset Pull-Down resistance
Soft-Start Charge Current
PG PIN CHARACTERISTICS
t
C
= 10µF, I
= 1A
µs
EN
OUT
LOAD
V
= 6V, EN = 3V
1
µA
IN
R
323
-4.5
Ω
PD
I
-7
-2
µA
CHG
V
PG Flag Threshold
PG Flag Hysteresis
75
84
4
92
%V
OUT
OUT
OUT
V
%
PG Flag Low Voltage
PG Flag Leakage Current
NOTES:
I
= 500µA
47
100
1
mV
µA
SINK
V
= 6V, PG = 6V
0.05
IN
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. Dropout is defined by the difference in supply V and V when the supply produces a 2% drop in V from its nominal value.
IN OUT OUT
10. Minimum cap of 10µF X5R/X7R on V and V
IN OUT
required for stability.
11. If the current limit for in-rush current is acceptable in application, do not use this feature. Used only when large bulk capacitance required on V
application.
for
OUT
FN6660.6
June 14, 2013
5
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN
= 10µF, T = +25°C, I = 0A.
OUT J L
OUT
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.2
0.6
0
+125°C
+25°C
-40°C
-0.6
-1.2
-1.8
0
1
2
3
4
5
6
-50 -25
0
25
50
75
100
125
150
SUPPLY VOLTAGE (V)
JUNCTION TEMPERATURE (°C)
FIGURE 3. ΔV
vs TEMPERATURE
FIGURE 4. OUTPUT VOLTAGE vs SUPPLY VOLTAGE
OUT
9
1.8
8
7
6
5
4
3
2
1
0
1.2
0.6
+25°C
0.0
-0.6
-1.2
-1.8
-40°C
+125°C
0
0.5
1.0
1.5
2.0
2.5
3.0
2
3
4
5
6
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
FIGURE 5. ΔV
vs OUTPUT CURRENT
FIGURE 6. GROUND CURRENT vs SUPPLY VOLTAGE
OUT
12.0
11.5
9.1
8.9
8.7
8.5
8.3
8.1
7.9
7.7
7.5
11.0
10.5
10.0
9.5
-40°C
-40°C
+25°C
9.0
+125°C
+125°C
8.5
+25°C
2.0
8.0
7.5
0
0.5
1.0
1.5
2.0
2.5
3.0
0.8
1.4
2.6
3.2
3.8
4.4
5.0
OUTPUT CURRENT (A)
OUTPUT VOLTAGE (V)
FIGURE 8. GROUND CURRENT vs OUTPUT VOLTAGE
FIGURE 7. GROUND CURRENT vs OUTPUT CURRENT
FN6660.6
June 14, 2013
6
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
OUT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
12
11
10
9
8
7
6
5
4
3
2
V
= 5V
V
= 6V
IN
IN
1
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
FIGURE 9. SHUTDOWN CURRENT vs TEMPERATURE
FIGURE 10. SHUTDOWN CURRENT vs TEMPERATURE
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
150
140
130
120
110
100
90
80
70
60
50
2A
3A
40
30
20
10
1A
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
FIGURE 11. DROPOUT VOLTAGE vs TEMPERATURE
FIGURE 12. DROPOUT VOLTAGE vs OUTPUT CURRENT
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
V
(1V/DIV)
IN
SS (1V/DIV)
V
(1V/DIV)
OUT
PG (1V/DIV)
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
TIME (10ms/DIV)
FIGURE 13. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE
FIGURE 14. POWER-UP (V = 2.2V)
IN
FN6660.6
June 14, 2013
7
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN OUT
= 1.8V, C = C
IN
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
EN (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
IN
SS (1V/DIV)
V
(1V/DIV)
V
(1V/DIV)
OUT
OUT
PG (1V/DIV)
PG (1V/DIV)
TIME (10ms/DIV)
TIME (50µs/DIV)
FIGURE 15. POWER-DOWN (V = 2.2V)
IN
FIGURE 16. ENABLE START-UP
300
250
200
150
100
50
EN (1V/DIV)
SS (1V/DIV)
V
(1V/DIV)
OUT
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
PG (1V/DIV)
INPUT VOLTAGE (V)
TIME (5ms/DIV)
FIGURE 18. START-UP TIME vs SUPPLY VOLTAGE
FIGURE 17. ENABLE SHUTDOWN
300
250
200
150
100
50
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ISL80103
ISL80102
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 19. START-UP TIME vs TEMPERATURE
FIGURE 20. CURRENT LIMIT vs TEMPERATURE
FN6660.6
June 14, 2013
8
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN
= 1.8V, C = C
IN
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
OUT
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
ISL80103
V
(1V/DIV)
OUT
ISL80102
I
(1A/DIV)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
OUT
INPUT VOLTAGE (V)
TIME (10ms/DIV)
FIGURE 21. CURRENT LIMIT vs SUPPLY VOLTAGE
FIGURE 22. CURRENT LIMIT RESPONSE (ISL80102)
V
(1V/DIV)
OUT
V
(1V/DIV)
OUT
I
OUT
(1A/DIV)
I
(2A/DIV)
OUT
TIME (100ms/DIV)
TIME (20ms/DIV)
FIGURE 24. CURRENT LIMIT RESPONSE (ISL80103)
FIGURE 23. THERMAL CYCLING (ISL80102)
EN (1V/DIV)
V
(1V/DIV)
OUT
I
(2A/DIV)
(1V/DIV)
OUT
I
(2A/DIV)
OUT
V
OUT
TIME (1ms/DIV)
TIME (50ms/DIV)
FIGURE 26. IN-RUSH CURRENT WITH NO SOFT-START
CAPACITOR, C = 1000µF
FIGURE 25. THERMAL CYCLING (ISL80103)
OUT
FN6660.6
June 14, 2013
9
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN OUT
= 1.8V, C = C
IN
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
EN (1V/DIV)
EN (1V/DIV)
I
(2A/DIV)
(1V/DIV)
I
(2A/DIV)
(1V/DIV)
OUT
OUT
V
OUT
V
OUT
TIME (1ms/DIV)
TIME (1ms/DIV)
FIGURE 27. IN-RUSH WITH 22nF SOFT-START CAPACITOR,
= 1000µF
FIGURE 28. IN-RUSH WITH 47nF SOFT-START CAPACITOR,
= 1000µF
C
C
OUT
OUT
V
(50mV/DIV)
OUT
V
(50mV/DIV)
OUT
I
(2A/DIV)
OUT
I
(2A/DIV)
OUT
di/dt = 30A/µs
di/dt = 30A/µs
TIME (200µs/DIV)
TIME (200µs/DIV)
FIGURE 30. LOAD TRANSIENT 0A TO 3A, C
+ 100µF OSCON
= 10µF CERAMIC
OUT
FIGURE 29. LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC
OUT
V
(50mV/DIV)
OUT
V
(50mV/DIV)
OUT
I
(2A/DIV)
OUT
I
(2A/DIV)
OUT
di/dt = 30A/µs
di/dt = 30A/µs
TIME (200µs/DIV)
TIME (200µs/DIV)
FIGURE 31. LOAD TRANSIENT 1A TO 3A, C
= 10µF CERAMIC
OUT
FIGURE 32. LOAD TRANSIENT 1A TO 3A, C
+ 100µF OSCON
= 10µF CERAMIC
OUT
FN6660.6
June 14, 2013
10
ISL80102, ISL80103
Typical Operating Performance
Unless otherwise noted: V = 2.2V, V
IN OUT
= 1.8V, C = C
IN
= 10µF, T = +25°C, I = 0A. (Continued)
OUT J L
V
(20mV/DIV)
OUT
V
(20mV/DIV)
OUT
I
(2A/DIV)
I
(2A/DIV)
OUT
OUT
di/dt = 3A/µs
TIME (50µs/DIV)
di/dt = 3A/µs
TIME (50µs/DIV)
FIGURE 33. LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC,
FIGURE 34. LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC,
OUT
OUT
= 1500pF (ADJ VERSION)
NO C (ADJ VERSION)
C
PB
PB
80
70
60
50
40
30
20
10
0
3.2V
2.2V
V
(1V/DIV)
IN
1A
100mA
10k
V
(10mV/DIV)
OUT
10
100
1k
100k
1M
TIME (200µs/DIV)
FREQUENCY (Hz)
FIGURE 35. LINE TRANSIENT
FIGURE 36. PSRR vs LOAD
80
70
60
50
40
30
20
10
0
10
1
100µF
0.1
10µF
47µF
100k
I
= 100mA
L
0.01
10
100
1k
10k
100k
1M
10
100
1k
10k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 38. SPECTRAL NOISE DENSITY vs FREQUENCY
FIGURE 37. PSRR vs C
OUT
FN6660.6
June 14, 2013
11
ISL80102, ISL80103
5.0
4.5
4.0
Functional Description
Input Voltage Requirements
Despite other output voltages offered, this family of LDOs is
optimized for a true 2.5V to 1.8V conversion where the input
supply can have a tolerance of as much as ±10% for conditions
noted in the “Electrical Specifications” table on page 4. Minimum
guaranteed input voltage is 2.2V, however, due to the nature of
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
an LDO, V must be some margin higher than the output voltage
IN
plus dropout at the maximum rated current of the application if
active filtering (PSRR) is expected from V to V . The dropout
IN
OUT
spec of this family of LDOs has been generously specified in
order to allow applications to design for a level of efficiency that
can accommodate the smaller outline package.
0
20
40
60
(nF)
80
100
C
SS
FIGURE 39. IN-RUSH CURRENT vs SOFT-START CAPACITANCE
Enable Operation
The Enable turn-on threshold is typically 770mV with a hysteresis of
135mV. An internal pull-up or pull-down resistor is available upon
request. As a result, this pin must not be left floating. This pin must
Output Voltage Selection
An external resistor divider is used to scale the output voltage
relative to the internal reference voltage. This voltage is then fed
back to the error amplifier. The output voltage can be
be tied to V if it is not used. A 1kΩ to 10kΩ pull-up resistor is
IN
programmed to any level between 0.8V and 5V. An external
required for applications that use open collector or open drain
outputs to control the Enable pin. The Enable pin may be connected
resistor divider, R and R , is used to set the output voltage as
3
4
shown in Equation 1. The recommended value for R is 500Ω to
4
directly to V for applications that are always on.
IN
1kΩ. R is then chosen according to Equation 2:
3
Power-Good Operation
R
⎛
⎜
⎝
⎞
3
(EQ. 1)
(EQ. 2)
------
V
= 0.5V ×
+ 1
⎟
OUT
Applications not using this feature must connect this pin to
ground. The PGOOD flag is an open-drain NMOS that can sink up
to 10mA during a fault condition. The PGOOD pin requires an
external pull-up resistor, which is typically connected to the VOUT
pin. The PGOOD pin should not be pulled up to a voltage source
R
4
⎠
V
OUT
0.5V
⎛
⎝
⎞
------------
R
= R
×
4
– 1
3
⎠
greater than V . The PGOOD fault can be caused by the output
External Capacitor Requirements
External capacitors are required for proper operation. To ensure
optimal performance careful attention must be paid to the layout
guidelines and selection of capacitor type and value.
IN
voltage going below 84% of the nominal output voltage, or the
current limit fault, or low input voltage. The PGOOD does not
function during thermal shutdown. While the PGOOD functions in
shutdown.
OUTPUT CAPACITOR
Soft-Start Operation (Optional)
The ISL80102, ISL80103 applies state-of-the-art internal
compensation to keep selection of the output capacitor simple
If the current limit for in-rush current is acceptable in the
application, do not use this feature. The soft-start circuit controls
the rate at which the output voltage comes up to regulation at
power-up or LDO enable. A constant current charges an external
soft-start capacitor. The external capacitor always gets
for the customer. Stable operation over full temperature, V
IN
range and load extremes are guaranteed for all
range, V
OUT
capacitor types and values assuming a 10µF X5R/X7R is used
for local bypass on V . This minimum capacitor must be
OUT
and Ground pins of the LDO with PCB traces
discharged to ground pin potential at the beginning of start-up or
enabling. The discharge rate is the RC time constant of R and
connected to V
OUT
PD
no longer than 0.5cm.
C
. See Figures 26 through 29 in the “Typical Operating
SS
Lower cost Y5V and Z5U type ceramic capacitors are acceptable
if the size of the capacitor is larger to compensate for the
significantly lower tolerance over X5R/X7R types. Additional
capacitors of any value in Ceramic, POSCAP or Alum/Tantalum
Electrolytic types may be placed in parallel to improve PSRR at
higher frequencies and/or load transient AC output voltage
tolerances.
Performance Curves” beginning on page 6. R is the
PD
ON-resistance of the pull down MOSFET, M8. R is 300Ω
PD
typically.
The soft-start feature effectively reduces the in-rush current at
power-up or LDO enable until V
reaches regulation. The
OUT
in-rush current can be an issue for applications that require large,
external bulk capacitances on V where high levels of charging
OUT
current can be seen for a significant period of time. The in-rush
currents can cause V to drop below minimum which could
INPUT CAPACITOR
IN
to shutdown. Figure 39 shows the relationship
The minimum input capacitor required for proper operation is
10µF having a ceramic dielectric. This minimum capacitor must
cause V
OUT
between in-rush current and C with a C
of 1000µF.
SS
OUT
be connected to V and ground pins of the LDO with PCB traces
IN
no longer than 0.5cm.
FN6660.6
June 14, 2013
12
ISL80102, ISL80103
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
A(MAX)
maximum allowable power dissipation as shown in Equation 4:
and the
will determine the
Phase Boost Capacitor (Optional)
The ISL80102 and ISL80103 are designed to be stable with
10µF or larger ceramic capacitor.
J(MAX)
(EQ. 4)
P
= (T
– T ) ⁄ θ
J(MAX) A JA
D(MAX)
Applications using the ADJ versions, may see improved
performance with the addition of a small ceramic capacitor C
PB
Where θ is the junction-to-ambient thermal resistance.
JA
as shown in Figure 2 on page 3. The conditions where C may
PB
be beneficial are: (1) V
OUT
AC voltage regulation band.
>1.5V, (2) C = 10µF, and (3) tight
OUT
For safe operation, please make sure that power dissipation
calculated in Equation 3, P be less than the maximum
D
allowable power dissipation P
.
D(MAX)
C
introduces phase lead with the product of R and C that
PB
3
PB
results in increasing the bandwidth of the LDO. Typical R3 x C
should be 4μs.
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
PB
(GND plane) for heat sinking. Figure 40 shows a curve for the θ
of the DFN package for different copper area sizes.
JA
C
not recommended for V < 1.5V.
OUT
PB
Current Limit Protection
46
44
42
40
38
36
34
The ISL80102, ISL80103 family of LDOs incorporates protection
against overcurrent due to short, overload condition applied to
the output and the in-rush current that occurs at start-up. The
LDO performs as a constant current source when the output
current exceeds the current limit threshold noted in the
“Electrical Specifications” table on page 4. If the short or
overload condition is removed from V , then the output returns
OUT
to normal voltage mode regulation. In the event of an overload
condition, the LDO might begin to cycle on and off due to the die
temperature exceeding the thermal fault condition. The
TO220/TO263 package will tolerate higher levels of power
dissipation on the die which may never thermal cycle if the
heatsink of this larger package can keep the die temperature
below the specified typical thermal shutdown temperature.
2
4
6
8
10
12
14
16
18
20
2
22
24
EPAD-MOUNT COPPER LAND AREA ON PCB, mm
FIGURE 40. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
THERMAL VIAS θ vs EPAD-MOUNT COPPER LAND
AREA ON PCB
JA
Power Dissipation and Thermals
Thermal Fault Protection
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions (Note 8)” on page 4.
The power dissipation can be calculated by using Equation 3:
In the event the die temperature exceeds typically +160°C, then
the output of the LDO will shut down until the die temperature
can cool down to typically +145°C. The level of power combined
with the thermal impedance of the package (+48°C/W for DFN)
will determine if the junction temperature exceeds the thermal
shutdown temperature.
P
= (V – V
) × I
+ V × I
OUT IN GND
(EQ. 3)
D
IN
OUT
FN6660.6
June 14, 2013
13
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
May 23, 2013
FN6660.6 Pin Descriptions on page page 3, updated EPAD section From: EPAD at ground potential. Soldering it directly to
GND plane is optional. To: EPAD must be connected to copper plane with as many vias as possible for proper
electrical and optimal thermal performance.
Removed obsolete part numbers: ISL80102IR33Z, ISL80102IR50Z, ISL80103IR33Z, ISL80103IR50Z from
ordering information table on page 2.
Added evaluation boards to ordering information table on page 2: ISL80103IR50Z and ISL80103EVAL2Z.
Features on page 1: Removed 5 Ld TO220 and 5 Ld TO263.
Input Voltage Requirements on page 12: Removed the sentence “those applications that cannot accommodate
the profile of the TO220/TO263”.
June 14, 2012
FN6660.5 In “Thermal Information” on page 4, corrected θ from 48 to 45.
JA
February 14, 2012
FN6660.4 Increased “VEN(HIGH)” minimum limit from 0.4V to 0.616 and added the “VEN(LOW)” spec for clarity on page 5.
December 14, 2011 FN6660.3 Increased “Turn-on Threshold” minimum limit on page 5 from 0.3V to 0.4V.
Updated “Package Outline Drawing” on page 16 as follows:
Removed package outline and included center to center distance between lands on recommended land pattern.
Removed Note 4 "Dimension b applies to the metallized terminal and is measured between 0.18mm and 0.30mm
from the terminal tip." since it is not applicable to this package. Renumbered notes accordingly.
March 4, 2011
March 4, 2010
FN6660.2 Converted to new template
On page 1 - first paragraph, changed "Fixed output voltage options are available in 1.5V, 1.8V, 2.5V, 3.3V and 5V"
to "Fixed output voltage options are available in 1.8V, 2.5V, 3.3V and 5V"
In “Ordering Information” table on page 2, removed ISL80102IR15Z and ISL80103IR15Z.
In Note 3 on page 2, below the “Ordering Information” table , removed '1.5V', so it reads “The 3.3V and 5V fixed
output voltages will be released in the future. Please contact Intersil Marketing for more details.”
FN6660.1 Corrected Features on page 1 as follows:
-Changed bullet "• 185mV Dropout @ 3A, 125mV Dropout @ 2A" to "• Very Low 120mV Dropout at 3A"
-Changed bullet "• 65dB Typical PSRR" to "• 62dB Typical PSRR"
-Deleted 0.5% Initial VOUT Accuracy
Modified Figure 1 and placed as “TYPICAL APPLICATION” on page 1.
Moved Pinout to page 3
In “Block Diagram” on page 2, corrected resistor associated with M5 from R4 to R5
Updated “Block Diagram” on page 2 as follows”
- Added M8 from SS to ground.
Updated Figure 1 on page 1 as follows:
-Corrected Pin 6 from SS to IRSET
-Removed Note 11 callout "Minimum cap on VIN and VOUT required for stability." Added Note "*CSS is optional.
See Note 12 on Page 5." and “** CPB is optional. See “Functional Description” on page 12 for more information.”
Added "The 1.5V, 3.3V and 5V fixed output voltages will be released in the future." to Note 3 on page 2.
In “Thermal Information” on page 4, updated Theta JA from 45 to 48.
In “Soft-Start Operation (Optional)” on page 12:
-Changed "The external capacitor always gets discharged to 0V at start-up of after coming out of a chip disable.
"The external capacitor always gets discharged to ground pin potential at start-up or enabling."
-Changed "The soft-start function effectively limits the amount of in-rush current below the programmed current
limit during start-up or an enable sequence to avoid an overcurrent fault condition." to "The soft-start feature
effectively reduces the in-rush current at power-up or LDO enable until VOUT reaches regulation."
-Added "See Figures 25 through 27 in the “Typical Operating Performance Curves” beginning on page 6."
-Added “RPD is the on resistance of the pull-down MOSFET, M8. RPD is 300Ω typically.”
FN6660.6
June 14, 2013
14
ISL80102, ISL80103
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev. (Continued)
DATE
REVISION
CHANGE
March 4, 2010
FN6660.1 Added “Phase Boost Capacitor (Optional)” on page 13.
(CONTINUED)
In “Typical Operating Performance” on page 11, revised figure "PSRR vs VIN" which had 3 curves with “SPECTRAL
NOISE DENSITY vs FREQUENCY” which has one curve.
Added "Figure 33. “LOAD TRANSIENT 0A TO 3A, C
= 10µF CERAMIC, NO CPB (ADJ VERSION)” and "Figure 34.
OUT
= 10µF CERAMIC, CPB = 1500pF (ADJ VERSION)”
“LOAD TRANSIENT 0A TO 3A, C
OUT
September 30, 2009 FN6660.0 Initial Release.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/product_tree
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6660.6
June 14, 2013
15
ISL80102, ISL80103
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 7, 10/11
5
3.00
A
B
PIN #1 INDEX AREA
1
2
5
PIN 1
INDEX AREA
10 x 0.23
(4X)
0.10
1.60
10x 0.35
TOP VIEW
BOTTOM VIEW
A B
C
M
0.10
(4X)
0.415
0.23
0.35
SEE DETAIL "X"
0.10
(10 x 0.55)
(10x 0.23)
C
C
BASE PLANE
0.20
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
4
0.20 REF
0.05
C
1.60
2.85 TYP
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
4.
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
5.
FN6660.6
June 14, 2013
16
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