ISL8026A [RENESAS]
Compact Synchronous Buck Regulators;
| 型号： | ISL8026A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Compact Synchronous Buck Regulators |
| 文件： | 总23页 (文件大小：1411K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL8026, ISL8026A
Compact Synchronous Buck Regulators
FN8736
Rev 2.00
October 28, 2016
The ISL8026, ISL8026A are highly efficient, monolithic,
synchronous step-down DC/DC converters that can deliver 6A of
continuous output current from a 2.5V to 5.5V input supply. The
devices use current mode control architecture to deliver a very low
duty cycle operation at high frequency with fast transient
response and excellent loop stability.
Features
• 2.5V to 5.5V input voltage range
• Very low ON-resistance FETs - P-channel 36mΩ and
N-channel 13mΩ typical values
• High efficiency synchronous buck regulator with up to 95%
efficiency
The ISL8026, ISL8026A integrate a very low ON-resistance
P-channel (36mΩ) high-side FET and N-channel (13mΩ)
low-side FET to maximize efficiency and minimize external
component count. The 100% duty-cycle operation allows less
than 180mV dropout voltage at 6A output current. The
operation frequency of the Pulse-width Modulator (PWM) is
adjustable from 500kHz to 4MHz. The default switching
frequency, which is set by connecting the FS pin high, is 1MHz
for the ISL8026 and 2MHz for the ISL8026A.
• 1.0% reference accuracy over load/line/temperature (-40°C
to +85°C)
• 1.5% reference accuracy over load/line/temperature (-40°C
to +125°C)
• Internal soft-start: 1ms or adjustable
• Soft-stop output discharge during disable
• Adjustable frequency from 500kHz to 4MHz - default at
1MHz (ISL8026) or 2MHz (ISL8026A)
The ISL8026, ISL8026A can be configured for discontinuous or
forced continuous operation at light load. Forced continuous
operation reduces noise and RF interference, while
discontinuous mode provides higher efficiency by reducing
switching losses at light loads.
• External synchronization up to 4MHz
• Over-temperature, overcurrent, overvoltage and negative
overcurrent protection
Fault protection is provided by internal hiccup mode current
limiting during short-circuit and overcurrent conditions. Other
protection, such as overvoltage and over-temperature, are also
integrated into the device. A power-good output voltage
monitor indicates when the output is in regulation.
Applications
• DC/DC POL modules
• μC/µP, FPGA and DSP power
• Video processor/SOC power
• Li-ion battery powered devices
• Routers and switchers
• Portable instruments
The ISL8026, ISL8026A offer a 1ms Power-Good (PG) timer at
power-up. When in shutdown, the ISL8026, ISL8026A
discharge the output capacitor through an internal soft-stop
switch. Other features include internal fixed or adjustable
soft-start and internal/external compensation.
• Test and measurement systems
• Industrial PCs
The ISL8026, ISL8026A are offered in a space saving 16 Ld
3x3 Pb-free TQFN package with an exposed pad for improved
thermal performance and 0.8mm maximum height. The
Related Literature
• UG033, “ISL8026xEVAL3Z Evaluation Board User Guide”
2
complete converter occupies less than 142mm .
L1
100
+1.8V/6A
VOUT
GND
1.0μH
2 x 22μF
C2
3.3V
PFM
90
80
70
60
50
40
OUT
+2.5V …+5.5V
C1
2 x 22μF
1
2
PGND
PGND
VIN
VIN
ISL8026
R2
200kꢀꢁ
C3*
22pF
GND
R1
100kꢀꢁ
VIN
3.3V
PWM
OUT
R3
100kꢀꢁ
PGND/
SGND
3
4
PG
PG
SYNC
FB
*C3 IS OPTIONAL. IT IS
RECOMMENDED TO PUT A
PLACEHOLDER FOR IT AND CHECK
LOOP ANALYSIS BEFORE USE.
V
O
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
------------
R
= R
– 1
(EQ. 1)
2
3
VFB
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION (INTERNAL
COMPENSATION OPTION)
FIGURE 2. EFFICIENCY vs LOAD 1MHz 5V
IN
FN8736 Rev 2.00
October 28, 2016
Page 1 of 23
ISL8026, ISL8026A
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SKIP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Frequency Adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Negative Current Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soft Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power MOSFETs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
100% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
FN8736 Rev 2.00
October 28, 2016
Page 2 of 23
ISL8026, ISL8026A
Pin Configuration
ISL8026, ISL8026A
(16 LD TQFN)
TOP VIEW
16
14
15
13
VIN
PGND
PGND
1
2
3
4
12
11
10
9
VIN
PG
EPAD
PGND/SGND
FB
SYNC
8
7
6
5
Pin Descriptions
PIN NUMBER
SYMBOL
DESCRIPTION
1, 2, 16
VIN
Input supply voltage. Place a minimum of two 22µF ceramic capacitors from VIN to PGND as close as possible to the IC
for decoupling.
3
4
PG
Power-good is an open-drain output. Use a 10kΩ to 100kΩ pull-up resistor connected between VIN and PG. At power-up or
EN HI, PG rising edge is delayed by 1ms once the output voltage reaches regulation.
SYNC
Mode Selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM
mode. Connect to an external function generator for synchronization with the positive edge trigger. There is an internal
1MΩ pull-down resistor to prevent an undefined logic state in case the SYNC pin is floating.
5
6
EN
FS
Regulator enable pin. Enable the output when driven high. Shut down the chip and discharge output capacitor when driven
low.
This pin sets the oscillator switching frequency using a resistor, R , from the FS pin to GND. The frequency of operation
FS
may be programmed between 500kHz to 4MHz. The default frequency is 1MHz (ISL8026), 2MHz (ISL8026A) if FS is
connected to VIN.
7
SS
SS is used to adjust the soft-start time. Connect to SGND for internal 1ms rise time. Connect a capacitor from SS to SGND to
adjust the soft-start time. Do not use more than 33nF per IC.
8, 9
COMP, FB The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The output
voltage is set by an external resistor divider connected to FB. With a properly selected divider, the output voltage can be
set to any voltage between the power rail (reduced by converter losses) and the 0.6V reference.
COMP is the output of the amplifier if COMP is not tied to VIN. Otherwise, COMP is disconnected through a MOSFET for
internal compensation. Must connect COMP to VIN in internal compensation mode to meet a typical application.
Additional external networks across COMP and SGND might be required to improve the loop compensation of the amplifier
operation.
In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the regulator output voltage.
10
PGND/SGND Power/signal ground
11, 12
PGND
Power ground
13, 14, 15
PHASE
Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω resistor when the
device is disabled. See “Block Diagram” on page 5 for more detail.
Exposed Pad
-
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias as possible
under the pad connecting to the SGND plane for optimal thermal performance.
FN8736 Rev 2.00
October 28, 2016
Page 3 of 23
ISL8026, ISL8026A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
OPERATION FREQUENCY
(MHz)
TEMP. RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
ISL8026IRTAJZ
026A
26AA
026F
026AF
1
2
1
2
-40 to +85
-40 to +85
-40 to +125
-40 to +125
16 Ld 3x3 TQFN
L16.3x3D
L16.3x3D
L16.3x3D
L16.3x3D
ISL8026AIRTAJZ
ISL8026FRTAJZ
ISL8026AFRTAJZ
ISL8026EVAL3Z
ISL8026AEVAL3Z
NOTES:
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
16 Ld 3x3 TQFN
Evaluation board for ISL8026
Evaluation board for ISL8026A
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8026, ISL8026A. For more information on MSL please see techbrief
TB363.
TABLE 1. SUMMARY OF KEY DIFFERENCES
PART
NUMBER
I
(MAX)
f
RANGE
V
RANGE
(V)
V
OUT
RANGE
(V)
PART SIZE
(mm)
OUT
(A)
SW
(MHz)
IN
ISL8026
6
Programmable 0.5MHz to 4MHz
Programmable 1MHz to 4MHz
2.5 to 5.5
0.6 to 5.5
3x3
ISL8026A
TABLE 2. ISL8026 COMPONENT SELECTION
V
0.8V
1.2V
2 x 22µF
2 x 22µF
22pF
1.5V
2 x 22µF
2 x 22µF
22pF
1.8V
2 x 22µF
2 x 22µF
22pF
2.5V
3.3V
3.6V
OUT
C
C
C
2 x 22µF
4 x 22µF
22pF
2 x 22µF
2 x 22µF
22pF
2 x 22µF
2 x 22µF
22pF
2 x 22µF
2 x 22µF
22pF
1
2
3
1
L
0.47~1µH
33kΩ
0.47~1µH
100kΩ
0.47~1µH
150kΩ
0.68~1.5µH
200kΩ
0.68~1.5µH
316kΩ
1~2.2µH
450kΩ
100kΩ
1~2.2µH
500kΩ
R
R
2
3
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
100kΩ
TABLE 3. ISL8026A COMPONENT SELECTION
V
0.8V
22µF
1.2V
22µF
1.5V
22µF
1.8V
22µF
2.5V
22µF
3.3V
22µF
3.6V
22µF
OUT
C
C
C
1
2
3
1
3 x 22µF
22pF
2 x 22µF
22pF
2 x 22µF
22pF
2 x 22µF
22pF
2 x 22µF
22pF
2 x 22µF
22pF
2 x 22µF
22pF
L
0.22~0.47µH 0.22~0.47µH
0.22~0.47µH
150kΩ
0.33~0.68µH
200kΩ
0.33~0.68µH
316kΩ
0.47~1µH
450kΩ
100kΩ
0.47~1µH
500kΩ
100kΩ
R
R
33kΩ
100kΩ
100kΩ
2
3
100kΩ
100kΩ
100kΩ
100kΩ
FN8736 Rev 2.00
October 28, 2016
Page 4 of 23
ISL8026, ISL8026A
Block Diagram
COMP
55pF
FS
SYNC
SS
SOFT-
START
SHUTDOWN
SHUTDOWN
100kΩ
+
+
VIN
EN
OSCILLATOR
VREF
3pF
BANDGAP
+
EAMP
COMP
-
P
-
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
PHASE
PGND
LS
DRIVER
N
+
FB
SLOPE
COMP
0.8V
6kΩ
+
-
CSA
-
+
-
OV
+
OCP
-
0.85*VREF
ISET
THRESHOLD
+
UV
+
SKIP
-
PG
1ms
DELAY
NEG CURRENT
SENSING
SGND
ZERO-CROSS
SENSING
-
SCP
+
0.5V
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
FN8736 Rev 2.00
October 28, 2016
Page 5 of 23
ISL8026, ISL8026A
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.8V (DC) or 7V (20ms)
EN, FS, PG, SYNC, VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
PHASE . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
COMP, SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Ratings
Thermal Resistance
16 LD TQFN Package (Notes 4, 5) . . . . . . .
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
47
(°C/W)
6.5
JA
JC
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 3kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 2kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Latch-Up (Tested per JESD-78A; Class 2, Level A) . . . . . 100mA at +85°C
Recommended Operating Conditions
V
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V to 5.5V
IN
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 6A
Ambient Temperature Range (Industrial) . . . . . . . . . . . . . .-40°C to +85°C
Ambient Temperature Range (Full-Range Industrial) . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. , “case temperature” location is at the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions
and are measured at the following conditions: V = 3.6V, EN = V , unless otherwise noted. Typical values are at T = +25°C. Unless otherwise noted,
IN
IN
A
Boldface limits apply across the operating temperature range, -40°C to +125°C
MIN
MAX
PARAMETER
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6)
UNIT
INPUT SUPPLY
Undervoltage Lockout Threshold
V
V
Rising, no load
Falling, no load
2.3
2.25
50
50
9
2.5
V
IN
UVLO
2.10
V
Quiescent Supply Current
I
SYNC = GND, no load at the output
µA
µA
mA
mA
µA
VIN
SYNC = GND, no load at the output and no switching
62
16
23
8
SYNC = V , f = 1MHz, no load at the output (ISL8026)
IN SW
SYNC = V , f = 2MHz, no load at the output (ISL8026A)
IN SW
16
5
Shutdown Supply Current
OUTPUT REGULATION
Reference Voltage
I
SYNC = GND, V = 5.5V, EN = low
IN
SD
V
-40°C < T < +85°C
0.594 0.600 0.606
V
V
REF
J
-40°C < T < +125°C
J
0.591 0.600 0.606
VFB Bias Current
I
VFB = 0.75V
0.1
0.2
1
µA
%/V
ms
µA
VFB
Line Regulation
V
= V + 0.5V to 5.5V (minimal 2.5V)
O
IN
SS = SGND
= 0.1V
Soft-Start Ramp Time Cycle
Soft-Start Charging Current
OVERCURRENT PROTECTION
Current Limit Blanking Time
ISS
V
1.45
1.85
2.25
SS
t
17
Clock
OCON
pulses
Overcurrent and Auto Restart Period
Positive Peak Current Limit
Peak Skip Limit
t
8
9
SS cycle
OCOFF
I
6A application
7.5
1
11
A
A
PLIMIT
I
6A application (See “Application Information” on page 19
for more detail)
1.3
1.8
SKIP
Zero Cross Threshold
Negative Current Limit
-300
-4.5
300
-1.5
mA
A
I
-3.0
NLIMIT
FN8736 Rev 2.00
October 28, 2016
Page 6 of 23
ISL8026, ISL8026A
Electrical Specifications Unless otherwise noted, all parameter limits are established across the recommended operating conditions
and are measured at the following conditions: V = 3.6V, EN = V , unless otherwise noted. Typical values are at T = +25°C. Unless otherwise noted,
IN
IN
A
Boldface limits apply across the operating temperature range, -40°C to +125°C (Continued)
MIN
MAX
PARAMETER
COMPENSATION
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6)
UNIT
Error Amplifier Transconductance
Internal compensation
60
µA/V
µA/V
External compensation
120
Transresistance
Rt
6A application (test at 3.6V)
-40°C < T < +85°C
0.119 0.140 0.166
0.110 0.140 0.170
Ω
Ω
J
6A application (test at 3.6V)
-40°C < T < +125°C
J
PHASE
P-Channel MOSFET ON-Resistance
V
V
V
V
= 5V, I = 200mA
36
52
63
89
30
36
mΩ
mΩ
mΩ
mΩ
%
IN
IN
IN
IN
O
= 2.7V, I = 200mA
O
N-Channel MOSFET ON-Resistance
= 5V, I = 200mA
13
O
= 2.7V, I = 200mA
17
O
PHASE Maximum Duty Cycle
PHASE Minimum On-Time
OSCILLATOR
100
SYNC = High
140
ns
Nominal Switching Frequency
f
f
f
f
f
f
= V , ISL8026A. -40°C < T < +85°C
IN
1600 2000 2400
1550 2000 2450
kHz
kHz
kHz
kHz
kHz
V
SW
SW
SW
SW
SW
SW
J
= V , ISL8026A. -40°C < T < +125°C
IN
J
= V , ISL8026
IN
780
1000 1200
490
with RS = 402kΩ
with RS = 42.2kΩ
4200
SYNC Logic LOW to HIGH Transition Range
SYNC Hysteresis
0.70
0.75
0.15
3.6
0.80
5
V
SYNC Logic Input Leakage Current
PG
V
= 3.6V
µA
IN
Output Low Voltage
0.3
2
V
ms
µA
V
Delay Time (Rising Edge)
PG Pin Leakage Current
OVP PG Rising Threshold
UVP PG Rising Threshold
UVP PG Hysteresis
Time from V
OUT
reached regulation
0.5
80
1
PG = V
0.01
0.80
85
0.10
IN
90
%
30
mV
µs
PGOOD Delay Time (Falling Edge)
EN
7.5
Logic Input Low
0.4
1
V
Logic Input High
0.9
V
EN Logic Input Leakage Current
Thermal Shutdown
Pulled up to 3.6V
0.1
150
25
µA
°C
°C
Temperature Rising
Temperature Falling
Thermal Shutdown Hysteresis
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN8736 Rev 2.00
October 28, 2016
Page 7 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test.
IN
100
1
2
OUT
100
90
80
90
80
70
60
50
40
0.8V
0.9V
OUT
OUT
1.2V
0.9V
OUT
0.8V
OUT
1.2V
OUT
1.5V
OUT
70
1.5V
OUT
OUT
2.5V
OUT
1.8V
1.8V
OUT
OUT
2.5V
OUT
60
50
40
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 V PWM)
IN
FIGURE 5. EFFICIENCY vs LOAD (1MHz 3.3 V PFM)
IN
100
100
90
80
70
60
50
40
90
80
70
60
50
40
3.3V
OUT
3.3V
OUT
1.8V
OUT
2.5V
OUT
2.5V
OUT
1.8V
OUT
1.5V
1.2V
OUT
1.2V
OUT
1.5V
OUT
OUT
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5V PWM)
IN
FIGURE 7. EFFICIENCY vs LOAD (1MHz 5V PFM)
IN
100
90
80
70
60
50
40
100
90
80
70
60
50
40
0.8V
OUT
0.8V
OUT
0.9V
OUT
0.9V
OUT
1.2V
OUT
1.2V
OUT
1.5V
1.5V
OUT
OUT
2.5V
1.8V
OUT
2.5V
1.8V
OUT
OUT
OUT
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 9. EFFICIENCY vs LOAD (2MHz 3.3V PFM)
IN
FIGURE 8. EFFICIENCY vs LOAD (2MHz 3.3V PWM)
IN
FN8736 Rev 2.00
October 28, 2016
Page 8 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test. (Continued)
IN
100
1
2
OUT
100
90
80
90
80
70
60
50
40
3.3V
OUT
3.3V
OUT
2.5V
70
60
50
40
2.5V
1.8V
OUT 1.8V
OUT
OUT
1.5V
OUT
1.5V
0.9V
0.9V
OUT
OUT
1.2V
OUT
1.2V
OUT
OUT
OUT
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 10. EFFICIENCY vs LOAD (2MHz 5V PWM)
IN
FIGURE 11. EFFICIENCY vs LOAD (2MHz 5V PFM)
IN
0.816
0.813
0.810
0.807
0.804
0.801
0.798
0.795
0.792
0.789
0.915
0.912
0.909
0.906
0.903
0.900
0.897
0.894
0.891
5V PFM
IN
5V PFM
IN
3.3V PFM
IN
3.3V PFM
IN
5V PWM
IN
5V PWM
IN
3.3V PWM
IN
3.3V PWM
IN
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 12. V
REGULATION vs LOAD (1MHz, V
= 0.8V)
FIGURE 13. V
REGULATION vs LOAD (1MHz, V
= 0.9V)
OUT
OUT
OUT
OUT
1.525
1.520
1.515
1.510
1.505
1.500
1.495
1.219
1.214
1.209
1.204
1.199
1.194
3.3V PFM
IN
3.3V PFM
IN
5V PFM
IN
5V PFM
IN
5V PWM
IN
3.3V PWM
IN
1.189
1.184
1.179
5V PWM
IN
3.3V PWM
IN
1.490
1.485
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 14. V
OUT
REGULATION vs LOAD (1MHz, V
= 1.2V)
FIGURE 15. V
REGULATION vs LOAD (1MHz, V
= 1.5V)
OUT
OUT
OUT
FN8736 Rev 2.00
October 28, 2016
Page 9 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I = 0A to 6A. Resistor load is used in the test. (Continued)
OUT
IN
1.825
1
2
2.510
1.820
1.815
1.810
1.805
1.800
1.795
1.790
1.785
2.505
3.3V PFM
IN
3.3V PFM
IN
2.500
2.495
2.490
2.485
2.480
2.475
2.470
5V PFM
IN
5V PFM
IN
5V PWM
IN
5V PWM
IN
3.3V PWM
IN
3.3V PWM
IN
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 16. V
OUT
REGULATION vs LOAD (1MHz, V
= 1.8V)
FIGURE 17. V
OUT
REGULATION vs LOAD (1MHz, V = 2.5V)
OUT
OUT
3.341
3.333
3.325
3.317
3.309
3.301
5V PFM
IN
5V PWM
IN
3.293
3.285
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
OUTPUT LOAD (A)
FIGURE 18. V
OUT
REGULATION vs LOAD (1MHz, V
= 3.3V)
OUT
FN8736 Rev 2.00
October 28, 2016
Page 10 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test. (Continued)
IN
1
2
OUT
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
5V/DIV
V
1V/DIV
5V/DIV
OUT
OUT
V
V
EN
EN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 19. START-UP AT NO LOAD (PFM)
FIGURE 20. START-UP AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
V
1V/DIV
OUT
OUT
V
5V/DIV
V
5V/DIV
EN
EN
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 21. SHUTDOWN AT NO LOAD (PFM)
FIGURE 22. SHUTDOWN AT NO LOAD (PWM)
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
5V/DIV
OUT
V
V
1V/DIV
OUT
V
EN
5V/DIV
EN
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 24. SHUTDOWN AT 6A LOAD (PWM)
FIGURE 23. START-UP AT 6A LOAD (PWM)
FN8736 Rev 2.00
October 28, 2016
Page 11 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test. (Continued)
IN
1
2
OUT
I
2A/DIV
I
2A/DIV
OUT
OUT
V
1V/DIV
OUT
V
1V/DIV
OUT
V
5V/DIV
V
5V/DIV
EN
EN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
200µs/DIV
FIGURE 26. SHUTDOWN AT 6A LOAD (PFM)
FIGURE 25. START-UP AT 6A LOAD (PFM)
V
5V/DIV
1V/DIV
EN
V
5V/DIV
1V/DIV
EN
V
OUT
V
OUT
I
2A/DIV
L
I
2A/DIV
L
PG 5V/DIV
PG 5V/DIV
1ms/DIV
50µs/DIV
FIGURE 28. SHUTDOWN AT 3A LOAD (PWM)
FIGURE 27. START-UP AT 3A LOAD (PWM)
V
V
5V/DIV
V
5V/DIV
EN
EN
V
1V/DIV
1V/DIV
OUT
OUT
I
2A/DIV
I
2A/DIV
L
L
PG 5V/DIV
PG 5V/DIV
1ms/DIV
50µs/DIV
FIGURE 30. SHUTDOWN AT 3A LOAD (PFM)
FIGURE 29. START-UP AT 3A LOAD (PFM)
FN8736 Rev 2.00
October 28, 2016
Page 12 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test. (Continued)
IN
1
2
OUT
I
2A/DIV
OUT
I
2A/DIV
OUT
V
1V/DIV
5V/DIV
OUT
V
1V/DIV
5V/DIV
OUT
V
V
IN
IN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 31. START-UP V AT 6A LOAD (PFM)
IN
FIGURE 32. START-UP V AT 6A LOAD (PWM)
IN
I
2A/DIV
1V/DIV
OUT
I
2A/DIV
1V/DIV
OUT
V
OUT
V
OUT
V
5V/DIV
V
5V/DIV
IN
IN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 33. SHUTDOWN V AT 6A LOAD (PFM)
IN
FIGURE 34. SHUTDOWN V AT 6A LOAD (PWM)
IN
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
5V/DIV
OUT
V
1V/DIV
5V/DIV
OUT
V
IN
V
IN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 35. START-UP VIN AT NO LOAD (PFM)
FIGURE 36. START-UP VIN AT NO LOAD (PWM)
FN8736 Rev 2.00
October 28, 2016
Page 13 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test. (Continued)
IN
1
2
OUT
PHASE 5V/DIV
PHASE 5V/DIV
V
1V/DIV
5V/DIV
V
1V/DIV
5V/DIV
OUT
OUT
V
V
IN
IN
PG 5V/DIV
PG 5V/DIV
2ms/DIV
2ms/DIV
FIGURE 38. SHUTDOWN VIN AT NO LOAD (PWM)
FIGURE 37. SHUTDOWN VIN AT NO LOAD (PFM)
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
10ns/DIV
FIGURE 39. JITTER AT NO LOAD PWM
FIGURE 40. JITTER AT FULL LOAD PWM
PHASE 5V/DIV
PHASE 5V/DIV
V
RIPPLE 20mV/DIV
OUT
V
RIPPLE 20mV/DIV
OUT
IL 1A/DIV
IL 1A/DIV
20ms/DIV
500ns/DIV
FIGURE 42. STEADY STATE AT NO LOAD PFM
FIGURE 41. STEADY STATE AT NO LOAD PWM
FN8736 Rev 2.00
October 28, 2016
Page 14 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I
= 0A to 6A. Resistor load is used in the test. (Continued)
IN
1
2
OUT
PHASE 5V/DIV
PHASE 5V/DIV
I
1A/DIV
L
I
2A/DIV
L
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT
OUT
500ns/DIV
500ns/DIV
FIGURE 44. STEADY STATE AT 3A PFM
FIGURE 43. STEADY STATE AT 6A PWM
V
RIPPLE 100mV/DIV
V
RIPPLE 50mV/DIV
OUT
OUT
I
2A/DIV
I 2A/DIV
L
L
200µs/DIV
200µs/DIV
FIGURE 45. LOAD TRANSIENT (PWM)
FIGURE 46. LOAD TRANSIENT (PFM)
PHASE 5V/DIV
V
1V/DIV
5A/DIV
OUT
V
1V/DIV
5A/DIV
OUT
I
L
I
L
PG 5V/DIV
PG 5V/DIV
20µs/DIV
5µs/DIV
FIGURE 48. OVERCURRENT PROTECTION
FIGURE 47. OUTPUT SHORT-CIRCUIT
FN8736 Rev 2.00
October 28, 2016
Page 15 of 23
ISL8026, ISL8026A
Typical Operating Performance Unless otherwise noted, operating conditions are: T = +25°C, V = 5V, EN = V
,
A
IN
IN
SYNC = V , L = 1.0µH, C = 22µF, C = 2 x 22µF, I = 0A to 6A. Resistor load is used in the test. (Continued)
OUT
IN
1
2
PHASE 5V/DIV
PHASE1 5V/DIV
BACK TO PFM AT 360mA
600mA MODE TRANSITION,
COMPLETELY ENTER TO PWM AT 640mA
V
RIPPLE 20mV/DIV
OUT1
V
RIPPLE 20mV/DIV
OUT1
I
500mA/DIV
I
500mA/DIV
L
L
1µs/DIV
1µs/DIV
FIGURE 49. PFM TO PWM TRANSITION
FIGURE 50. PWM TO PFM TRANSITION
PHASE 5V/DIV
V
1V/DIV
OUT
V
2V/DIV
2A/DIV
OUT
I
L
PG 2V/DIV
PG 5V/DIV
2ms/DIV
20µs/DIV
FIGURE 51. OVERVOLTAGE PROTECTION
FIGURE 52. OVER-TEMPERATURE PROTECTION
FN8736 Rev 2.00
October 28, 2016
Page 16 of 23
ISL8026, ISL8026A
with the 55pF and 100kΩ RC network. The maximum EAMP
voltage output is precisely clamped to 1.6V.
Theory of Operation
The ISL8026, ISL8026A are step-down switching regulators
optimized for battery-powered applications. The regulators operate
at a 1MHz or 2MHz fixed default switching frequency for high
efficiency and allow smaller form factor when FS is connected to
VIN. By connecting a resistor from FS to SGND, the operational
frequency adjustable range is 500kHz to 4MHz. At light load, the
regulator reduces the switching frequency, unless forced to the fixed
frequency, to minimize the switching loss and to maximize the
battery life. The quiescent current when the output is not loaded is
typically only 50µA. The supply current is typically only 5µA when
the regulator is shut down.
V
EAMP
V
CSA
DUTY
CYCLE
I
L
V
OUT
PWM Control Scheme
Pulling the SYNC pin HI (>0.8V) forces the converter into PWM
mode, regardless of output current. The ISL8026, ISL8026A
employs the current-mode Pulse-width Modulation (PWM) control
scheme for fast transient response and pulse-by-pulse current
limiting. Figure 3 on page 5 shows the functional block diagram.
The current loop consists of the oscillator, the PWM comparator,
current sensing circuit and the slope compensation for the current
loop stability. The slope compensation is 440mV/Ts, which changes
with frequency. The gain for the current sensing circuit is typically
140mV/A. The control reference for the current loops comes from
the Error Amplifier's (EAMP) output.
FIGURE 53. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNC pin LOW (<0.4V) forces the converter into PFM
mode. The ISL8026, ISL8026A enters a pulse-skipping mode at
light load to minimize the switching loss by reducing the
switching frequency. Figure 54 illustrates the skip mode
operation. A zero-cross sensing circuit shown in Figure 3 on
page 5 monitors the N-FET current for zero crossing. When 16
consecutive cycles are detected, the regulator enters the Skip
mode. During the sixteen detecting cycles, the current in the
inductor is allowed to become negative. The counter is reset to
zero when the current in any cycle does not cross zero.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp up. When the
sum of the current amplifier, CSA, and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-channel MOSFET. The N-FET stays on until
the end of the PWM cycle. Figure 53 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the slope compensation ramp and the Current-Sense
Amplifier’s (CSA) output.
Once the skip mode is entered, the pulse modulation starts being
controlled by the Skip comparator shown in Figure 3 on page 5.
Each pulse cycle is still synchronized by the PWM clock. The
P-FET is turned on at the clock's rising edge and turned off when
the output is higher than 1.2% of the nominal regulation or when
its current reaches the peak skip current limit value. Then, the
inductor current is discharged to 0A and stays at zero (the
internal clock is disabled) and the output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal voltage,
the P-FET will be turned on again at the rising edge of the internal
clock as it repeats the previous operations.
The output voltage is regulated by controlling the V
EAMP
voltage
to the current loop. The bandgap circuit outputs a 0.6V reference
voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the
start-up and will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage error signal
to a current output. The voltage loop is internally compensated
The regulator resumes normal PWM mode operation when the
output voltage drops 2.5% below the nominal voltage.
PWM
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
I
L
LOAD CURRENT
0
NOMINAL +1.2%
V
OUT
NOMINAL -2.5%
NOMINAL
FIGURE 54. SKIP MODE OPERATION WAVEFORMS
FN8736 Rev 2.00
October 28, 2016
Page 17 of 23
ISL8026, ISL8026A
Frequency Adjust
Soft Start-Up
The frequency of operation is fixed at 1MHz for ISL8026, 2MHz for
ISL8026A when FS is tied to VIN. Adjustable frequency ranges from
500kHz to 4MHz via a simple resistor connecting FS to SGND,
according to Equation 2:
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the
error amplifier. This voltage ramp limits the inductor current as
well as the output voltage speed, so that the output voltage rises
in a controlled fashion. When VFB is less than 0.1V at the
beginning of the soft-start, the switching frequency is reduced to
200kHz, so that the output can start-up smoothly at light load
condition. During soft-start, the IC operates in the Skip mode to
support prebiased output condition.
3
220 10
------------------------------
(EQ. 2)
R
k =
– 14
FS
f
kHz
OSC
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
Tie SS to SGND for internal soft-start, which is approximately
1ms. Connect a capacitor from SS to SGND to adjust the
soft-start time. This capacitor, along with an internal 1.85µA
output with the OCP comparator, as shown in Figure 3 on page 5.
The current sensing circuit has a gain of 140mV/A, from the P-FET
current to the CSA output. When the CSA output reaches the
threshold, the OCP comparator is tripled to turn off the P-FET
immediately. The overcurrent function protects the switching
converter from a shorted output by monitoring the current flowing
through the upper MOSFET.
current source sets the soft-start interval of the converter, t as
SS,
shown by Equation 3.
(EQ. 3)
C
F = 3.1 t s
SS
SS
C
must be less than 33nF to insure proper soft-start reset after
SS
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. Upon detection of the initial
overcurrent condition, the overcurrent fault counter is set to 1. If,
on the subsequent cycle, another overcurrent condition is
detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the regulator will be shut down
under an overcurrent fault condition. An overcurrent fault
condition will result in the regulator attempting to restart in a
hiccup mode within the delay of eight soft-start periods. At the
fault condition.
Enable
The Enable (EN) input allows the user to control the turning on or off
of the regulator for purposes such as power-up sequencing. When
the regulator is enabled, there is typically a 600µs delay for waking
up the bandgap reference and then the soft start-up begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN UVLO is
set, the outputs discharge to GND through an internal 100Ω
switch.
th
end of the 8 soft-start wait period, the fault counters are reset
and soft-start is attempted again. If the overcurrent condition
goes away during the delay of 8 soft-start periods, the output will
resume back into regulation after hiccup mode expires.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-FET is typically 36mΩ and the
ON-resistance for the N-FET is typically 13mΩ.
Negative Current Protection
Similar to overcurrent, the negative current protection is realized
by monitoring the current across the low-side N-FET, as shown in
Figure 3 on page 5. When the valley point of the inductor current
reaches -3A for 4 consecutive cycles, both P-FET and N-FET are
turned off. The 100Ω in parallel to the N-FET will activate
discharging the output into regulation. The control will begin to
switch when output is within regulation. The regulator will be in
PFM for 20µs before switching to PWM, if necessary.
100% Duty Cycle
The ISL8026, ISL8026A features a 100% duty cycle operation to
maximize the battery life. When the battery voltage drops to a
level that the ISL8026, ISL8026A can no longer maintain the
regulation at the output, the regulator completely turns on the
P-FET. The maximum dropout voltage under the 100% duty cycle
operation is the product of the load current and the
ON-resistance of the P-FET.
PG
PG is an open-drain output of a window comparator that
continuously monitors the buck regulator output voltage. PG is
actively held low when EN is low and during the buck regulator
soft-start period. After 1ms delay of the soft-start period, PG
becomes high impedance as long as the output voltage is within the
nominal regulation voltage set by VFB. When VFB drops 15% below
or raises 0.8V above the nominal regulation voltage, the ISL8026,
ISL8026A pulls PG low. Any fault condition forces PG low until the
fault condition is cleared by attempts to soft-start. For logic level
Thermal Shutdown
The ISL8026, ISL8026A has built-in thermal protection. When the
internal temperature reaches +150°C, the regulator is completely
shut down. As the temperature drops to +125°C, the ISL8026,
ISL8026A resumes operation by stepping through the soft-start.
output voltages, connect an external pull-up resistor, R , between
1
PG and VIN. A 100kΩ resistor works well in most applications.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
FN8736 Rev 2.00
October 28, 2016
Page 18 of 23
ISL8026, ISL8026A
The ISL8026, ISL8026A uses an internal compensation network
and the output capacitor value is dependent on the output
voltage. The ceramic capacitor is recommended to be X5R or
X7R. The recommended X5R or X7R minimum output capacitor
values are shown in Table 3 on page 4.
Power Derating Characteristics
To prevent the regulator from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 4:
(EQ. 4)
T
= PD
JA
In Table 3, the minimum output capacitor value is given for the
different output voltages to ensure that the whole converter
system is stable. Additional output capacitance should be added
for better performance in applications where high load transient
or low output ripple is required. It is recommended to check the
system level performance along with the simulation model.
RISE
Where PD is the power dissipated by the regulator and θ is the
JA
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, T , is given by
Equation 5:
J
(EQ. 5)
T
= T + T
RISE
Output Voltage Selection
J
A
The output voltage of the regulator can be programmed via an
external resistor divider that is used to scale the output voltage,
relative to the internal reference voltage, and feed it back to the
inverting input of the error amplifier (refer to Figure 1 on page 1).
Where T is the ambient temperature. For the TQFN package, the
A
θ
is 47 (°C/W).
JA
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
The output voltage programming resistor, R , will depend on the
2
value chosen for the feedback resistor and the desired output
6
voltage of the regulator. The value for the feedback resistor, R ,
3
is typically between 10kΩ and 100kΩ, as shown in Equation 7.
5
3.3V
V
O
VFB
-----------
– 1
(EQ. 7)
R
= R
3
1.8V
2
4
3
0.8V
If the output voltage desired is 0.6V, then R is left unpopulated
3
and R is shorted. There is a leakage current from V to PHASE.
2
IN
It is recommended to preload the output with 10µA minimum.
2
1
For better performance, add 22pF in parallel with R (200kΩ).
2
Check loop analysis before use in application.
V
= 5V, ZERO LFM
IN
Input Capacitor Selection
0
50
60
70
80
90
100
110
120
130
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and provide a filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
TEMPERATURE (°C)
FIGURE 55. DERATING CURVE vs TEMPERATURE
Application Information
Output Inductor and Capacitor Selection
Loop Compensation Design
To consider steady state and transient operations, the ISL8026
typically uses a 1.0µH output inductor and the ISL8026A uses a
0.68µH output inductor. The higher or lower inductor value can
be used to optimize the total converter system performance. For
example, for a higher output voltage 3.3V application, in order to
decrease the inductor current ripple and output voltage ripple,
the output inductor value can be increased. It is recommended to
set the ripple inductor current approximately 30% of the
When COMP is not connected to VIN, the COMP pin is active for
external loop compensation. The ISL8026, ISL8026A uses
constant frequency peak current mode control architecture to
achieve a fast loop transient response. An accurate current
sensing pilot device in parallel with the upper MOSFET is used for
peak current control signal and overcurrent protection. The
inductor is not considered as a state variable since its peak
current is constant and the system becomes a single order
system. It is much easier to design a type II compensator to
stabilize the loop than to implement voltage mode control. Peak
current mode control has an inherent input voltage feed-forward
function to achieve good line regulation. Figure 56 on page 20
shows the small signal model of the synchronous buck regulator.
maximum output current for optimized performance. The
inductor ripple current can be expressed, as shown in Equation 6:
V
O
---------
V
1 –
O
V
IN
--------------------------------------
(EQ. 6)
I =
L f
S
The inductor’s saturation current rating needs to be at least
larger than the peak current. The ISL8026, ISL8026A protects
the typical peak current 9A. The saturation current needs to be
over 10A for maximum output current application.
FN8736 Rev 2.00
October 28, 2016
Page 19 of 23
ISL8026, ISL8026A
The compensator design procedure is as follows:
^
^
^
L
R
LP
i
i
P
L
v
in
o
The loop gain at crossover frequency of f has a unity gain.
c
^
V d
in
Therefore, the compensator resistance R is determined by
^
^
1:D
6
I d
V
L
in
Equation 9.
Rc
Co
+
Rt
2f V C R
o o t
Ro
3
c
(EQ. 9)
---------------------------------
= 12.210 f V C
c o o
R
=
6
GM V
FB
T(S)
i
Where GM is the sum of the transconductance, g , of the voltage
m
^
d
K
error amplifier in each phase. Compensator capacitor C is then
6
Fm
given by Equation 10.
R C
V C
o o
I R
o 6
R C
o
o
1
c
o
(EQ. 10)
T (S)
-------------- --------------
= ,C = max(--------------,---------------)
C
=
+
v
He(S)
6
7
R
R
f R
s 6
6
6
^
v
comp
-Av(S)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 10. An optional zero can boost the phase margin. CZ2
FIGURE 56. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
is a zero due to R and C .
2
3
Vo
Put compensator zero 2 to 5 times f .
c
1
R
R
C
3
(EQ. 11)
---------------
C =
2
3
3
f R
c
2
V
FB
V
-
COMP
Example: V = 5V, V = 1.8V, I = 6A, f = 1MHz, R = 200kΩ,
IN sw
R = 100kΩ, C = 2x22µF/3mΩ, L = 1µH, f = 100kHz, then
compensator resistance R :
GM
O
O
2
V
REF
+
3
o
c
6
R
6
3
(EQ. 12)
C
R
= 12.210 100kHz 1.8V 44F = 97.6k
7
6
C
6
1.8V 44F
6A 97.6k
(EQ. 13)
(EQ. 14)
-------------------------------
= 135pF
C
C
=
6
7
3m 44F
1
= max(--------------------------------,-------------------------------------------------) = (1pF, 3.3pF)
97.6k 1MHz97.6k
FIGURE 57. TYPE II COMPENSATOR
It is also acceptable to use the closest standard values for C and
6
Figure 57 shows the type II compensator and its transfer function
is expressed as shown in Equation 8:
C . There is approximately 3pF parasitic capacitance from V
7
COMP
to GND. Therefore, C is optional. Use C = 150pF and C = OPEN.
7
6
7
S
S
------------
------------
1 +
1 +
ˆ
GM R
v
1
comp
3
cz1
cz2
(EQ. 15)
---------------- -------------------------------------------------------- --------------------------------------------------------------
-----------------------------------------------
= 16pF
A S=
=
C
=
3
v
ˆ
C + C R + R
S
S
100kHz 200k
v
6
7
2
3
FB
-------------
-------------
S 1 +
1 +
cp1
cp2
Use C = 15pF. Note that C may increase the loop bandwidth
(EQ. 8)
3
3
from previous estimated value. Figure 58 on page 21 shows the
simulated voltage loop gain. It is shown that it has a 150kHz loop
bandwidth with a 42° phase margin and 10dB gain margin. It
may be more desirable to achieve an increased phase margin.
Where,
C
+ C
R + R
2
C R R
3 2 3
1
1
6
7
3
--------------
--------------
----------------------
----------------------
=
,
=
=
cp2
=
cz1
cz2
cp1
R C
R C
R C C
6
6
2
3
6
6
7
This can be accomplished by lowering R by 20% to 30%.
6
Compensator design goal:
High DC gain
Choose loop bandwidth f less than 100kHz
c
Gain margin: >10dB
Phase margin: >40°
FN8736 Rev 2.00
October 28, 2016
Page 20 of 23
ISL8026, ISL8026A
60
45
30
15
0
PCB Layout Recommendation
The PCB layout is a very important converter design step to make
sure the designed converter works well. For the ISL8026,
ISL8026A, the power loop is composed of the output inductor L’s,
the output capacitor (C
), the PHASE pins and the PGND pin. It
OUT
is necessary to make the power loop as small as possible and
the connecting traces among them should be direct, short and
wide. The switching node of the converter, the PHASE pins and
the traces connected to the node are very noisy, so keep the
voltage feedback trace away from these noisy traces. The input
capacitor should be placed as close as possible to the VIN pin.
The ground of input and output capacitors should be connected
as close as possible. The heat of the IC is mainly dissipated
through the thermal pad. Maximizing the copper area connected
to the thermal pad is preferable. In addition, a solid ground plane
is helpful for better EMI performance. It is recommended to add
at least 5 vias ground connection within the pad for the best
thermal relief.
-15
-30
100
1k
10k
100k
1M
FREQUENCY (Hz)
180
150
120
90
60
30
0
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 58. SIMULATED LOOP GAIN
FN8736 Rev 2.00
October 28, 2016
Page 21 of 23
ISL8026, ISL8026A
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to web to make sure you have the latest revision.
DATE
REVISION
CHANGE
2
2
October 28, 2016
FN8736.2 On page 1, last paragraph - converted - 0.22in to 142mm .
Added “1.5% reference accuracy over load/line/temperature (-40°C to +125°C)” to Features section on page 1.
Updated Ordering Information table on page 4:
Added 2 parts - ISL8026FRTAJZ and ISL8026AFRTAJZ
Removed “-T” from bulk parts and added Tape and Reel unit options to Note 1.
Updated Recommended Operating Conditions: Added full-range industrial temperature range
Electrical Spec table updates:
Reference Voltage added temp -40°C < T < +85°C and added row for -40°C < Tj < +125°C
J
Transresistance - Added temp -40°C < T < +85°C and added row for temperature -40°C < T < +125°C
J
J
Nominal Switching Frequency - added temperature -40°C < Tj < +85°C and added row for temperature
-40°C < T < +125°C
J
June 26, 2015
FN8736.1 Updated the 4th Features bullet by changing from 1.2% to 1% and adding temperature range.
Updated Applications bullets. on page 1.
Added Related Literature section.
Added evaluation boards to Ordering Information table on page 4.
In “Electrical Specifications” on page 6, updated min/max specs for Reference Voltage parameter (min)
from”0.593” to “0.594” and (max) from “0.607” to “0.606”.
Updated Equation 9 and Equations 12 through 14 on page 20.
Updated example I information from “5A” to “6A” on page 20.
O
May 13, 2015
FN8736.0 Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2015-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8736 Rev 2.00
October 28, 2016
Page 22 of 23
ISL8026, ISL8026A
For the most recent package outline drawing, see L16.3x3D.
Package Outline Drawing
L16.3x3D
16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 3/10
4X 1.50
3.00
6
A
12X 0.50
PIN #1
INDEX AREA
B
13
16
6
PIN 1
INDEX AREA
12
1
1.60 SQ
4
9
(4X)
0.15
0.10 M C A B
16X 0.23±0.05
8
5
16X 0.40±0.10
BOTTOM VIEW
TOP VIEW
4
SEE DETAIL “X”
0.10 C
C
0.75 ±0.05
0.08 C
SIDE VIEW
(12X 0.50)
(2.80 TYP) ( 1.60)
(16X 0.23)
5
0 . 2 REF
C
(16X 0.60)
0 . 02 NOM.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.25mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
JEDEC reference drawing: MO-220 WEED.
7.
FN8736 Rev 2.00
October 28, 2016
Page 23 of 23
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明