ISL80510IRAJZ [RENESAS]
High Performance 1A LDO;
| 型号： | ISL80510IRAJZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | High Performance 1A LDO |
| 文件： | 总13页 (文件大小：961K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL80505
High Performance 500mA LDO
FN8770
Rev 1.00
November 10, 2016
The ISL80505 is a single output Low Dropout voltage regulator
(LDO) capable of sourcing up to 500mA output current. This
LDO operates from input voltages of 1.8V to 6V. The output
voltage of ISL80505 can be programmed from 0.8V to 5.5V.
Features
• ±1.8% V
accuracy guaranteed over line, load, and
OUT
T = -40°C to +125°C
J
• Very low 45mV dropout voltage at V
= 2.5V
OUT
A submicron BiCMOS process is utilized for this product family
to deliver the best in class analog performance and overall
value. This CMOS LDO consumes significantly lower quiescent
current as a function of load compared to bipolar LDOs, which
translates into higher efficiency and packages with smaller
footprints.
• Stable with a 4.7µF output ceramic capacitor
• Very fast transient response
• Programmable output soft-start time
• Excellent PSRR over wide frequency range
• Current limit protection
State-of-the-art internal compensation achieves a very fast
load transient response and excellent PSRR. The ISL80505
• Thermal shutdown function
provides an output accuracy of ±1.8% V
accuracy over all
OUT
• Available in an 8 Ld DFN package
• Pb-free (RoHS compliant)
load, line and temperature variations (T = -40°C to +125°C).
J
An external capacitor on the soft-start pin provides an
adjustable soft starting of the output voltage ramp to control
the inrush current. The ENABLE feature allows the part to be
placed into a low quiescent current shutdown mode.
Applications
• Noise sensitive instrumentation systems
• Post regulation of switched mode power supplies
• Industrial systems
Table 1 shows the differences between the ISL80505 and
others in its family.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
• Medical equipment
PART NUMBER INPUT VOLTAGE RANGE MAX OUTPUT CURRENT
• Telecommunications and networking equipment
• Servers
ISL80510
ISL80505
2.2V to 6V
1.8V to 6V
1.0A
0.5A
• Hard disk drives (HD/HDD)
Related Literature
• For a full list of related documents, visit our website
- ISL80505 product page
80
I
= 0.1A
OUT
70
60
50
40
30
20
10
0
I
= 0.3A
ISL80505
EPAD
OUT
V
V
IN
V
V
V
V
OUT
C
IN
IN
OUT
1
2
8
OUT
C
IN
R
1
OUT
7
6
FB
SS
C
PB
(OPTIONAL)
3
4
I
= 0.5A
OUT
ENABLE
GND
V
V
= 2.3V
= 1.8V
= 10µF
= 2.7nF
PB
= 10kΩ
IN
C
SS
5
OUT
C
C
R
R
R
OUT
2
1
2
= 3.83kΩ
100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 1. TYPICAL APPLICATION CIRCUIT
FIGURE 2. PSRR
FN8770 Rev 1.00
November 10, 2016
Page 1 of 13
ISL80505
Block Diagram
VIN
REFERENCE
+
SOFT-START
FET DRIVER
WITH CURRENT
LIMIT
EA
CONTROL
LOGIC
THERMAL
SENSOR
ENABLE
SS
VOUT
FB
GND
FIGURE 3. BLOCK DIAGRAM
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG
DWG. #
ISL80505IRAJZ
0505
Evaluation Board
-40 to +125
8 Ld 3x3 DFN
L8.3X3J
ISL80510EVAL1Z
NOTES:
1. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit tape and reel options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see device information page for ISL80505. For more information on MSL see Technical Brief TB363.
FN8770 Rev 1.00
November 10, 2016
Page 2 of 13
ISL80505
Pin Configuration
ISL80505
(8 LD 3x3 DFN)
TOP VIEW
V
V
V
V
1
2
OUT
OUT
FB
8
IN
7
6
IN
EPAD
SS
3
4
GND
5
ENABLE
Pin Descriptions
PIN NUMBER
PIN NAME
DESCRIPTION
1, 2
V
Regulated output voltage. A minimum 4.7µF X5R/X7R output capacitor is required for stability. See “External
Capacitor Requirements” on page 10 for more details.
OUT
3
4
FB
GND
This pin is the input to the control loop error amplifier and is used to set the output voltage of the LDO.
Ground
5
ENABLE
SS
V
independent chip enable. TTL and CMOS compatible.
IN
6
External capacitor on this pin adjusts start-up ramp and controls inrush current.
7, 8
V
Input supply; A minimum of 4.7µF X5R/X7R input capacitor is required for proper operation. See “External
Capacitor Requirements” on page 10 for more details.
IN
-
EPAD
EPAD at ground potential. It is recommended to solder the EPAD to the ground plane.
FN8770 Rev 1.00
November 10, 2016
Page 3 of 13
ISL80505
Absolute Maximum Ratings
Thermal Information
V
V
Relative to GND (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Relative to GND (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Thermal Resistance (Typical)
8 Ld DFN Package (Notes 5, 6). . . . . . . . . .
JA (°C/W)
48
JC (°C/W)
IN
OUT
7
ENABLE, FB, SS Relative to GND (Note 4) . . . . . . . . . . . . . . . -0.3V to +6.5V
ESD Rating
Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22 A115C) . . . . . . . . . . . . . . . . . 250V
Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Notes 7, 8)
Junction Temperature Range (T ) . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
J
V
V
Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.8V to 6V
IN
Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .800mV to 5.5V
OUT
ENABLE, FB, SS Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 6V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
4. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%.
5. is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
7. Electromigration specification defined as lifetime average junction temperature of +110°C where maximum rated DC current = lifetime average
current.
8. The recommended operating condition for V relative to GND is 1.8V to 6V for a junction temperature range of 0°C to +125°C. The recommended
IN
operating condition for V relative to GND is 2.2V to 6V for a junction temperature range of -40°C to +125°C.
IN
Electrical Specifications Unless otherwise noted, 1.8V < V < 6V, V
= 0.5V, T = +25°C. Applications must follow thermal
J
guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 10 and Tech Brief TB379.
IN
OUT
Boldface limits apply across the operating temperature range, -40°C to +125°C.
MIN
MAX
PARAMETER
DC CHARACTERISTICS
Input Voltage
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
UNIT
V
0°C < T < +125°C
1.8
2.2
6.0
6.0
509
1
V
V
IN
J
-40°C < T < +125°C
J
Feedback Pin Voltage
Feedback Input Current
Line Regulation
V
1.8V < V < 6V; 0A < I
IN LOAD
< 500mA
491
500
mV
µA
%
FB
V
V
= 0.5V
0.01
FB
IN
(V
OUT(LOW LINE) -
= 1.8V to 6V; I
= 100mA
-0.9
-0.7
0.9
LOAD
V
V
)/
OUT(HIGH LINE)
OUT(LOW LINE)
Load Regulation
(V
V
V
= 2.2V; I = 0A to 500mA
LOAD
0.7
%
OUT(NO LOAD) -
)/
IN
OUT(FULL LOAD)
V
OUT(NO LOAD)
Ground Pin Current
I
I
I
= 0A, 1.8V < V < 6V
IN
2.2
2.8
0.2
45
4.6
5.7
12
mA
mA
µA
mV
A
Q
LOAD
LOAD
= 500mA, 1.8V < V < 6V
IN
Ground Pin Current in Shutdown
Dropout Voltage (Note 10)
I
ENABLE pin = 0V, V = 6V
IN
SHDN
V
I
= 500mA, V = 2.5V
OUT
90
DO
LOAD
Output Short-Circuit Current
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
OCP
TSD
V
= 0V
0.75
1.2
160
30
1.5
OUT
°C
°C
TSDn
FN8770 Rev 1.00
November 10, 2016
Page 4 of 13
ISL80505
Electrical Specifications Unless otherwise noted, 1.8V < V < 6V, V
= 0.5V, T = +25°C. Applications must follow thermal
J
guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 10 and Tech Brief TB379.
IN
OUT
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
MIN
MAX
PARAMETER
AC CHARACTERISTICS
SYMBOL
PSRR
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
UNIT
Input Supply Ripple Rejection
f = 1kHz, I
LOAD
= 500mA; V = 2.2V;
IN
57
60
79
dB
dB
V
= 1.8V
OUT
f = 120Hz, I
= 500mA; V = 2.2V;
IN
LOAD
= 1.8V
V
V
OUT
Output Noise Voltage
= 2.2V; V
= 1.8V; I
LOAD
= 500mA,
µV
RMS
IN
OUT
BW = 100Hz < f < 100kHz
ENABLE PIN CHARACTERISTICS
Turn-On Threshold
0.5
10
0.8
80
1
V
Hysteresis
200
mV
µs
ENABLE Pin Turn-On Delay
ENABLE Pin Leakage Current
SOFT-START CHARACTERISTICS
SS Pin Currents (Note 11)
C
= 4.7µF, I
= 500mA
= 6V, ENABLE = 3V
100
OUT
LOAD
V
1
µA
IN
I
V
= 3.5V, ENABLE = 0V, SS = 1V
0.5
1
1.3
mA
µA
PD
IN
I
-3.3
-2
-0.8
CHG
NOTES:
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Dropout is defined as the difference in supply V and V
IN OUT
when the output is below its nominal regulation.
11. I is the internal pull-down current that discharges the external SS capacitor on disable. I
is the current from the SS pin that charges the external
PD
CHG
SS capacitor during start-up.
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I
J
= 0A.
LOAD
90
60
50
40
30
20
10
0
V
= 2.5V
OUT
I
= 250mA
OUT
80
70
60
50
40
30
20
10
0
+85°C
+125°C
+125°C
+85°C
-40°C
+25°C
+25°C
0°C
0°C
-40°C
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
OUTPUT CURRENT (A)
1.80 2.17 2.54 2.91 3.28 3.65 4.02 4.39 4.76 5.13 5.50
OUTPUT VOLTAGE (V)
FIGURE 4. DROPOUT vs OUTPUT CURRENT
FIGURE 5. DROPOUT vs OUTPUT VOLTAGE
FN8770 Rev 1.00
November 10, 2016
Page 5 of 13
ISL80505
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I
J
= 0A. (Continued)
LOAD
120
100
80
60
40
20
0
90
80
70
60
50
40
30
20
10
0
I
= 500mA
V
= 2.5V
OUT
OUT
I
= 500mA
+125°C
OUT
+85°C
I
= 250mA
OUT
+25°C
0°C
-40°C
1.80 2.17 2.54 2.91 3.28 3.65 4.02 4.39 4.76 5.13 5.50
-40 -25 -10
5
20
35
50
65
80
95 110 125
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 6. DROPOUT vs OUTPUT VOLTAGE
FIGURE 7. DROPOUT vs TEMPERATURE
3.0
3.0
2.5
2.0
1.5
1.0
0.5
0
+125°C
2.5
2.0
1.5
1.0
0.5
0
+85°C
+125°C
+25°C
+25°C
-40°C
0.2
-40°C
+85°C
0
0.1
0.1
0.2
0.3
0.3
0.4
0.4
0.5
0.5
1.8 2.2
2.6
3.1
3.5
3.9
4.3
4.7
5.2
5.6
6.0
OUTPUT CURRENT (A)
INPUT VOLTAGE (V)
FIGURE 8. GROUND CURRENT vs OUTPUT CURRENT
FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
= 0A
OUT
V
= 6V
IN
V
= 5V
IN
V
= 1.8V
IN
V
= 3V
65
IN
-40 -25 -10 5.0 20
35
50
65
80
95 110 125
-40 -25 -10
5
20
35
50
80
95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. GROUND CURRENT vs TEMPERATURE
FIGURE 11. SHUTDOWN CURRENT vs TEMPERATURE
FN8770 Rev 1.00
November 10, 2016
Page 6 of 13
ISL80505
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I
J
= 0A. (Continued)
LOAD
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
RISING THRESHOLD, FALLING THRESHOLD, -40°C
V
= 2.2V
IN
-40°C
RISING THRESHOLD, +25°C
EN RISING THRESHOLD
RISING THRESHOLD, +85°C
NG
SHO
°C
LLI
RE
FA
TH
+85
EN FALLING THRESHOLD
LD,
FALLING
THRESHOLD,
+25°C
RISING
THRESHOLD,
+125°C
FALLING
THRESHOLD, +125°C
-40 -25 -10 5.0 20
35
50
65
80
95 110 125
1.8 2.2
2.6
3.1
3.5
3.9
4.3
4.7
5.2 5.6
6.0
TEMPERATURE (°C)
INPUT VOLTAGE (V)
FIGURE 12. EN THRESHOLDS vs TEMPERATURE
FIGURE 13. EN THRESHOLDS vs INPUT VOLTAGE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.854
1.836
1.818
1.800
1.782
1.764
1.746
+125°C
+85°C
T = +85°C
T = +25°C
T = -40°C
T = +125°C
+25°C
-40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
INPUT VOLTAGE (V)
0.0
0.1
0.2
0.3
0.4
0.5
OUTPUT CURRENT (A)
FIGURE 14. OUTPUT VOLTAGE vs INPUT VOLTAGE
FIGURE 15. OUTPUT VOLTAGE vs OUTPUT CURRENT
1.854
1.836
1.818
1.800
1.782
1.764
1.746
1.854
1.836
1.818
1.800
1.782
1.764
1.746
T = +85°C
Series5
I
= 0A
OUT
T = +125°C
T = -40°C
I
= 500mA
OUT
2.2 2.6
3.0
3.3 3.7
4.1 4.5
4.9
5.2
5.6 6.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
INPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 17. OUTPUT VOLTAGE vs INPUT VOLTAGE
FIGURE 16. OUTPUT VOLTAGE vs TEMPERATURE
FN8770 Rev 1.00
November 10, 2016
Page 7 of 13
ISL80505
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I
J
= 0A. (Continued)
LOAD
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 6V
R
= 3.6Ω
IN
LOAD
EN (2V/DIV)
V
= 2.2V
IN
V
= 1.8V
IN
SS (500mV/DIV)
V
(500mV/DIV)
OUT
I
(500mA/DIV)
LOAD
-40 -25 -10
5
20
35
50
65
80
95 110 125
2ms/DIV
TEMPERATURE (°C)
FIGURE 19. ENABLE START-UP (C = 10nF)
SS
FIGURE 18. CURRENT LIMIT vs TEMPERATURE
C
= 10µF, C
= 10nF
PB
C
= 4.7µF
OUT
OUT
V
(AC- COUPLED, 20mV/DIV)
V
(AC- COUPLED, 50mV/DIV)
OUT
OUT
10mA <-> 500mA AT 2A/µs
10mA <-> 500mA AT 2A/µs
I
(200mA/DIV)
LOAD
I
(200mA/DIV)
LOAD
200µs/DIV
200µs/DIV
FIGURE 20. LOAD TRANSIENT RESPONSE
FIGURE 21. LOAD TRANSIENT RESPONSE
C
= 4.7µF, I = 10mA
LOAD
C
= 10µF, C
= 10nF, I = 10mA
LOAD
OUT
OUT
PB
V
(AC- COUPLED, 10mV/DIV)
OUT
V
(AC- COUPLED, 10mV/DIV)
OUT
2.2V <-> 6V AT 1V/µs
V
(2V/DIV)
2.2V <-> 6V AT 1V/µs
IN
V
(2V/DIV)
IN
200µs/DIV
200µs/DIV
FIGURE 23. LINE TRANSIENT RESPONSE
FIGURE 22. LINE TRANSIENT RESPONSE
FN8770 Rev 1.00
November 10, 2016
Page 8 of 13
ISL80505
Typical Operating Performance Unless otherwise noted: V = 2.2V, V = 1.8V, C = C = 10µF,
IN
OUT
IN
OUT
T = +25°C, I
J
= 0A. (Continued)
LOAD
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
I
= 0.1A
OUT
I
= 0.1A
I
OUT
I
= 0.2A
OUT
= 0.2A
OUT
I
= 0.5A
OUT
I
= 0.5A
I
= 0.4A
OUT
OUT
I
= 0.4A
I
OUT
I
= 0.3A
OUT
= 0.3A
OUT
V
C
= 2.3V
= 10nF
10
C
IN
= 10nF
PB
PB
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 25. PSRR vs FREQUENCY
FIGURE 24. PSRR vs FREQUENCY
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
I
= 0.2A
OUT
I
= 0.1A
I
OUT
I
= 0.1A
OUT
= 0.2A
OUT
I
= 0.5A
I
= 0.5A
OUT
OUT
I
= 0.3A
OUT
I
OUT
= 0.4A
I
= 0.4A
I
OUT
= 0.3A
OUT
C
= 47µF
OUT
C
= 4.7µF
OUT
100
1k
10k
FREQUENCY (Hz)
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
1M
FIGURE 26. PSRR vs FREQUENCY (C
= 4.7µF)
FIGURE 27. PSRR vs FREQUENCY (C
= 47µF)
OUT
OUT
10.00
1.00
0.10
0.01
I
= 500mA
OUT
100
1k
10k
FREQUENCY (Hz)
100k
FIGURE 28. OUTPUT NOISE SPECTRAL DENSITY
FN8770 Rev 1.00
November 10, 2016
Page 9 of 13
ISL80505
customer. Stable operation over full temperature, V range,
IN
Applications Information
Input Voltage Requirements
The ISL80505 is a linear voltage regulator operating from 1.8V to
6V input voltage and regulates output voltage between 0.8V to
5.5V, a maximum 500mA output current.
V
range, and load extremes are guaranteed for all capacitor
OUT
types and values assuming a minimum of 4.7µF X5R/X7R is
used for local bypass on V . This output capacitor must be
OUT
and GND pins of the LDO with PCB traces
connected to the V
OUT
no longer than 0.5cm.
There is a growing trend to use very low ESR Multilayer Ceramic
Capacitors (MLCC) because they can support fast load transients
and also bypass very high frequency noise from other sources.
However, the effective capacitance of MLCCs drops with applied
voltage, age, and temperature. X7R and X5R dielectric ceramic
capacitors are strongly recommended as they typically maintain
a capacitance range within ±20% of nominal voltage over full
operating ratings of temperature and voltage.
Due to the nature of an LDO, V must be some margin higher
IN
than V
plus dropout at the maximum rated current of the
OUT
application if active filtering (PSRR) is expected from V to V
.
IN OUT
The generous dropout specification of this family of LDOs allows
applications to design a level of efficiency.
Enable Operation
The ENABLE turn-on threshold is typically 800mV with 80mV of
hysteresis. An internal pull-up or pull-down resistor to change
these values is available upon request. As a result, this pin must
Additional capacitors of any value in ceramic, POSCAP,
alum/tantalum electrolytic types may be placed in parallel to
improve PSRR at higher frequencies and/or load transient AC
output voltage tolerances.
not be left floating and should be tied to V if not used. A 1kΩ to
IN
10kΩ pull-up resistor is required for applications that use open
collector or open-drain outputs to control the ENABLE pin. The
INPUT CAPACITOR
ENABLE pin may be connected directly to V for applications
IN
For proper operation, a minimum capacitance of 4.7µF X5R/X7R
is required at the input. This ceramic input capacitor must be
with outputs that are always on.
connected to the V and GND pins of the LDO with PCB traces no
longer than 0.5cm.
IN
Output Voltage
The output voltage can be set by an external resistor divider
network. The values of resistors R and R can be calculated by
PHASE BOOST CAPACITOR (CPB)
1
2
using Equation 1.
A small phase boost capacitor, C , can be placed across the top
PB
V
resistor, R , in the feedback resistor divider network in order to
1
OUT
---------------
R
= R
2
– 1
(EQ. 1)
1
improve the AC performances of the LDO for the applications
where the output capacitor is 10µF or larger. For 10µF output
0.5
capacitor, the recommended C value can be calculated by
using Equation 4.
Soft-Start Operation
PB
The soft-start circuit controls the rate at which the output voltage
rises up to regulation at power-up or LDO enable. This start-up
ramp time can be set by adding an external capacitor from the
SS pin to ground. An internal 2µA current source charges up the
1
(EQ. 4)
-----------------------------------
C
=
PB
2x6000xR
1
This zero increases the crossover frequency of the LDO and
provides additional phase resulting in faster load transient
response.
C
and the feedback reference voltage is clamped to the
SS
voltage across it. The start-up time is set by Equation 2.
C
x0.5
SS
(EQ. 2)
-----------------------
=
t
start
2A
Power Dissipation and Thermals
The junction temperature must not exceed the range specified in
the “Recommended Operating Conditions” on page 4. The power
dissipation can be calculated by using Equation 5:
Equation 3 determines the C required for a specific start-up
SS
inrush current, where V
is the output voltage, C
is the total
is the desired inrush
OUT
OUT
capacitance on the output and I
current.
INRUSH
(EQ. 5)
P
= V – V
I
+ V I
OUT IN GND
D
IN
OUT
V
xC
x2A
OUT
x0.5V
OUT
I
(EQ. 3)
---------------------------------------------------
=
C
SS
The maximum allowable junction temperature, T
maximum expected ambient temperature, T
A(MAX)
and the
, determine
J(MAX)
INRUSH
the maximum allowable power dissipation, as shown in
Equation 6:
The external capacitor is always discharged to ground at the
beginning of start-up or enabling.
(EQ. 6)
P
= T
– T
JMAX A JA
DMAX
External Capacitor Requirements
is the junction-to-ambient thermal resistance.
External capacitors are required for proper operation. Careful
attention must be paid to the layout guidelines and selection of
capacitor type and value to ensure optimal performance.
JA
For safe operation, ensure that the power dissipation P ,
calculated from Equation 5, is less than the maximum allowable
power dissipation P
D
.
D(MAX)
OUTPUT CAPACITOR
The ISL80505 applies state-of-the-art internal compensation to
keep the selection of the output capacitor simple for the
FN8770 Rev 1.00
November 10, 2016
Page 10 of 13
ISL80505
The DFN package uses the copper area on the PCB as a heatsink.
The EPAD of this package must be soldered to the copper plane
(GND plane) for effective heat dissipation. Figure 29 shows a
Figure 30 shows an example for 2-layer PCB layout. The bottom
layer is the ground plane.
curve for the of the DFN package for different copper area
JA
sizes.
IN
CIN
OUT
49
ISL80505
COUT
47
45
R1
EN
43
41
R2
CPB
CSS
GND
39
FIGURE 30. EXAMPLE FOR PCB LAYOUT
37
2
4
6
8
10 12 14 16 18 20 22 24
2
EPAD-MOUNT COPPER LAND AREA ON PCB (mm )
FIGURE 29. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH
General PowerPAD Design
Considerations
THERMAL VIAS vs EPAD-MOUNT COPPER LAND
JA
AREA ON PCB
The following is an example of how to use via’s to remove heat
from the IC.
Thermal Fault Protection
The power level and the thermal impedance of the package
(+48°C/W for DFN) determine when the junction temperature
exceeds the thermal shutdown temperature. In the event that the
die temperature exceeds around +160°C, the output of the LDO will
shut down until the die temperature cools down to about +130°C.
Current Limit Protection
FIGURE 31. PCB VIA PATTERN
The ISL80505 LDO incorporates protection against overcurrent due
to any short or overload condition applied to the output pin. The LDO
performs as a constant current source when the output current
exceeds the current limit threshold noted in the “Electrical
A minimum of 4 vias evenly distributed to fill the thermal pad
footprint is recommended. Keep the vias small but not so small
that their inside diameter prevents solder wicking through the
holes during reflow.
Specifications” table on page 4. If the short or overload condition is
removed from V , then the output returns to normal voltage
OUT
Connect all vias to the ground plane. It is important the vias have
a low thermal resistance for efficient heat transfer. Do not use
“thermal relief” patterns to connect the vias. It is important to
have a complete connection of the plated through-hole to each
plane.
regulation mode. In the event of an overload condition, the LDO may
begin to cycle on and off due to the die temperature exceeding
thermal fault condition and subsequently cooling down after the
power device is turned off.
PC Board Layout
The performance of this LDO depends greatly on the care taken
in designing the PC board. The following are recommendations to
achieve optimum performance.
• A minimum capacitance of 4.7µF X5R/X7R ceramic input
capacitor must be placed to the V and GND pins of the LDO
IN
with PCB traces no longer than 0.5cm.
• A minimum capacitance of 4.7µF X5R/X7R ceramic output
capacitor must be placed to the V
and GND pins of the LDO
with PCB traces no longer than 0.5cm.
OUT
• Connect the EPAD to the ground plane with low-thermal
resistance vias.
FN8770 Rev 1.00
November 10, 2016
Page 11 of 13
ISL80505
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
FN8770.1
CHANGE
November 10, 2016
Updated Related Literature section on page 1.
Updated Note 1 on page 2.
September 8, 2015
FN8770.0
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2015-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8770 Rev 1.00
November 10, 2016
Page 12 of 13
ISL80505
For the most recent package outline drawing, see L8.3x3J.
Package Outline Drawing
L8.3x3J
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1 3/15
2X 1.950
3.00
A
6X 0.65
B
5
8
(4X)
0.15
1.64 +0.10/ - 0.15
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
4
1
4
8X 0.30
0.10 M C A B
8X 0.400 ± 0.10
TOP VIEW
2.38
+0.10/ - 0.15
BOTTOM VIEW
SEE DETAIL "X"
( 2.38 )
( 1.95)
C
0.10
C
Max 1.00
0.08
C
SIDE VIEW
( 8X 0.60)
(1.64)
( 2.80 )
PIN 1
5
C
0 . 2 REF
(6x 0.65)
0 . 00 MIN.
0 . 05 MAX.
( 8 X 0.30)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
FN8770 Rev 1.00
November 10, 2016
Page 13 of 13
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