ISL81483IB [RENESAS]
LINE TRANSCEIVER, PDSO8, PLASTIC, MS-012AA, SOIC-8;
| 型号： | ISL81483IB |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | LINE TRANSCEIVER, PDSO8, PLASTIC, MS-012AA, SOIC-8 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL8487, ISL81483, ISL81487
1/8 Unit Load, 5V, Low Power, High Speed or Slew Rate Limited, RS-485/RS-422
Transceivers
FN6050
Rev 8.00
March 14, 2016
These Intersil RS-485/RS-422 devices are “fractional” unit
load (UL), BiCMOS, 5V powered, single transceivers that
Features
• Fractional Unit Load Allows up to 256 Devices on the Bus
• Specified for 10% Tolerance Supplies
meet both the RS-485 and RS-422 standards for balanced
communication. Unlike competitive devices, this Intersil
family is specified for 10% tolerance supplies (4.5V to 5.5V).
• Class 3 ESD Protection (HBM) on all Pins. . . . . . . . >7kV
• High Data Rate Version (ISL81487). . . . . . . up to 5Mbps
The ISL81483 and ISL81487 present a 1/8 unit load to the
RS-485 bus, which allows up to 256 transceivers on the
network for large node count systems (e.g., process
automation, remote meter reading systems). The 1/4 UL
ISL8487 allows up to 128 transceivers on the bus. In a
remote utility meter reading system, individual (apartments
for example) utility meter readings are routed to a
concentrator via an RS-485 network, so the high allowed
node count minimizes the number of repeaters required to
network all the meters. Data for all meters is then read out
from the concentrator via a single access port, or a wireless
link.
• Slew Rate Limited Versions for Error Free Data
Transmission (ISL8487, ISL81483) . . . . . . .up to 250kbps
• Low Current Shutdown Mode (Except ISL81487) . . 0.5A
• Low Quiescent Supply Current:
- ISL8487, ISL81483. . . . . . . . . . . . . . . . . . 145A (Max.)
- ISL81487 . . . . . . . . . . . . . . . . . . . . . . . . . 420A (Max.)
• -7V to +12V Common Mode Input Voltage Range
• Three State Rx and Tx Outputs
• 30ns Propagation Delays, 5ns Skew (ISL81487)
• Half Duplex Pinouts
Slew rate limited drivers on the ISL8487 and ISL81483
reduce EMI, and minimize reflections from improperly
terminated transmission lines, or unterminated stubs in
multidrop and multipoint applications. Data rates up to
250kbps are achievable with these devices.
• Operate from a Single +5V Supply (10% Tolerance)
• Current Limiting and Thermal Shutdown for Driver
Overload Protection
Data rates up to 5Mbps are achievable by using the
ISL81487, which features higher slew rates.
• Drop-In Replacements for: MAX487 (ISL8487); MAX1483
(ISL81483); MAX1487, LMS1487 (ISL81487)
Receiver (Rx) inputs feature a “fail-safe if open” design,
which ensures a logic high Rx output if Rx inputs are floating.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
Driver (Tx) outputs are short circuit protected, even for
voltages exceeding the power supply voltage. Additionally,
on-chip thermal shutdown circuitry disables the Tx outputs to
prevent damage if power dissipation becomes excessive.
• High Node Count Networks
• Automated Utility Meter Reading Systems
• Factory Automation
These half duplex devices multiplex the Rx inputs and Tx
outputs to allow transceivers with Rx and Tx disable
functions in 8 lead packages.
• Security Networks
• Building Environmental Control Systems
• Industrial/Process Control Networks
TABLE 1. SUMMARY OF FEATURES
RECEIVER/
DRIVER
ENABLE?
PART
NUMBER
HALF/FULL
DUPLEX
NO. OF DEVICES DATA RATE SLEW-RATE
QUIESCENT LOW POWER
PIN
ALLOWED ON BUS
(Mbps)
LIMITED?
I
(A) SHUTDOWN? COUNT
CC
120
ISL8487
Half
128
0.25
Yes
Yes
Yes
8
(No longer
available or
supported)
ISL81483
ISL81487
Half
Half
256
256
0.25
5
Yes
No
Yes
Yes
120
350
Yes
No
8
8
FN6050 Rev 8.00
March 14, 2016
Page 1 of 14
ISL8487, ISL81483, ISL81487
Pinout
Truth Tables
ISL8487, ISL81483, ISL81487 (PDIP, SOIC)
TRANSMITTING
TOP VIEW
INPUTS
OUTPUTS
RE
X
DE
1
DI
1
Z
0
1
Y
1
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
CC
R
B/Z
X
1
0
0
A/Y
0
0
X
X
High-Z
High-Z
High-Z *
D
GND
1
0
High-Z *
*Shutdown Mode for ISL8487, ISL81483 (see Note 7)
RECEIVING
INPUTS
OUTPUT
RE
0
DE
0
A-B
+0.2V
-0.2V
Inputs Open
X
RO
1
0
0
0
0
0
1
1
0
High-Z *
High-Z
1
1
X
*Shutdown Mode for ISL8487, ISL81483 (see Note 7)
Ordering Information
PART NO.
PART MARKING
TEMP. RANGE (°C)
PACKAGE
PKG. DWG. #
M8.15
ISL8487IBZ (Note) (No longer 8487IBZ
available, recommended
-40 to 85
8 Ld SOIC* (Pb-free)
replacement ISL8487EIBZ)
ISL8487IPZ (Note) (No longer 8487IPZ
available, recommended
-40 to 85
8 Ld PDIP** (Pb-free)
E8.3
replacement ISL8487EIPZ)
ISL81483IBZ (Note)
ISL81483IPZ (Note)
ISL81487IBZ (Note)
81483IBZ
81483IPZ
81487IBZ
-40 to 85
-40 to 85
-40 to 85
8 Ld SOIC* (Pb-free)
8 Ld PDIP** (Pb-free)
8 Ld SOIC* (Pb-free)
M8.15
E8.3
M8.15
*SOIC also available in Tape and Reel; Add “-T” to suffix.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish,
which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN6050 Rev 8.00
March 14, 2016
Page 2 of 14
ISL8487, ISL81483, ISL81487
Pin Descriptions
PIN
FUNCTION
RO
RE
Receiver output: If A > B by at least 0.2V, RO is high; If A < B by 0.2V or more, RO is low; RO = High if A and B are unconnected (floating).
Receiver output enable. RO is enabled when RE is low; RO is high impedance when RE is high.
Driver output enable. The driver outputs, Y and Z, are enabled by bringing DE high. They are high impedance when DE is low.
Driver input. A low on DI forces output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low.
Ground connection.
DE
DI
GND
A/Y
B/Z
RS-485/422 level, noninverting receiver input and noninverting driver output. Pin is an input (A) if DE = 0; pin is an output (Y) if DE = 1.
RS-485/422 level, inverting receiver input and inverting driver output. Pin is an input (B) if DE = 0; pin is an output (Z) if DE = 1.
System power supply input (4.5V to 5.5V).
V
CC
Typical Operating Circuits
ISL8487, ISL81483, ISL81487
+5V
+5V
+
+
0.1F
0.1F
8
8
V
V
CC
CC
RO
1
2
4
DI
R
D
RE
DE
R
T
R
T
3
2
7
6
7
6
B/Z
A/Y
DE
RE
B/Z
A/Y
3
4
DI
1
RO
R
D
GND
5
GND
5
FN6050 Rev 8.00
March 14, 2016
Page 3 of 14
ISL8487, ISL81483, ISL81487
Absolute Maximum Ratings
Thermal Information
V
to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Thermal Resistance (Typical, Note 1)
JA (°C/W)
CC
Input Voltages
8 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . .
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
170
140
DI, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (V
Input/Output Voltages
+0.5V)
CC
A/Y, B/Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +12.5V
RO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to (V
Short Circuit Duration
+0.5V)
CC
Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
ESD Rating
HBM (Per MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . >7kV
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range
ISL8XXXIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Test Conditions: V = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V
= 5V, T = 25°C,
A
CC
CC
(Note 2)
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
(°C)
MIN
TYP
MAX UNITS
DC CHARACTERISTICS
Driver Differential V
Driver Differential V
(no load)
V
V
Full
Full
Full
Full
-
2
-
V
V
V
V
V
OUT
OUT
OD1
OD2
CC
-
(with load)
R = 50 (RS-422), (Figure 1)
R = 27 (RS-485), (Figure 1)
R = 27 or 50, (Figure 1)
3
1.5
-
2.3
0.01
5
Change in Magnitude of Driver
Differential V for
V
0.2
OD
OUT
Complementary Output States
Driver Common-Mode V
V
R = 27 or 50, (Figure 1)
R = 27 or 50, (Figure 1)
Full
Full
-
-
-
3
V
V
OUT
Change in Magnitude of Driver
Common-Mode V for
OC
V
0.01
0.2
OC
OUT
Complementary Output States
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
V
DE, DI, RE
DE, DI, RE
DE, DI, RE
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
2
-
-
-
-
-
-
-
-
-
-
-
V
IH
V
-
0.8
V
IL
I
-2
2
A
A
A
A
A
A
A
V
IN1
IN2
Input Current (A/Y, B/Z), (Note 10)
(ISL81483, ISL81487)
I
I
I
DE = 0V, V
5.5V
= 4.5 to
= 0V
V
V
V
V
V
V
= 12V
= -7V
= 12V
= -7V
= 12V
= -7V
-
140
-120
180
-100
250
-100
0.2
CC
CC
CC
IN
IN
IN
IN
IN
IN
-
DE = 0V, V
-
IN2
IN2
-
Input Current (A/Y, B/Z), (Note 11)
(ISL8487 Only)
DE = 0V, V
4.5 to 5.5V
= 0V, or
-
-
Receiver Differential Threshold
Voltage
V
-7V V
12V
-0.2
TH
CM
Receiver Input Hysteresis
Receiver Output High Voltage
Receiver Output Low Voltage
V
V
= 0V
25
-
3.5
-
70
-
-
-
mV
V
TH
CM
V
I
I
= -4mA, V = 200mV
ID
Full
Full
Full
OH
O
O
V
= -4mA, V = 200mV
ID
-
0.4
1
V
OL
Three-State (high impedance)
Receiver Output Current
I
0.4V V 2.4V
-
-
A
OZR
O
FN6050 Rev 8.00
March 14, 2016
Page 4 of 14
ISL8487, ISL81483, ISL81487
Electrical Specifications Test Conditions: V = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V
= 5V, T = 25°C,
A
CC
CC
(Note 2) (Continued)
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
12V ISL81483, ISL81487
ISL8487
(°C)
Full
Full
Full
Full
Full
Full
Full
Full
MIN
TYP
MAX UNITS
Receiver Input Resistance
R
-7V V
96
48
-
-
-
k
k
A
A
A
A
A
mA
IN
CM
-
-
No-Load Supply Current, (Note 3)
I
ISL81487, DI, RE = 0V DE = V
400
350
160
120
0.5
-
500
420
200
145
8
CC
CC
or V
CC
DE = 0V
-
ISL8487, ISL81483, DI, DE = V
RE = 0V or V
-
CC
CC
DE = 0V
-
Shutdown Supply Current
Driver Short-Circuit Current,
I
(Note 7), DE = 0V, RE = V , DI = 0V or V
CC
-
SHDN
CC
I
DE = V , -7V V or V 12V, (Note 4)
35
250
OSD1
CC
Y
Z
V
= High or Low
O
Receiver Short-Circuit Current
I
0V V V
CC
Full
7
-
85
mA
OSR
O
SWITCHING CHARACTERISTICS (ISL81487)
Driver Input to Output Delay
Driver Output Skew
t
, t
PLH PHL
R
R
R
= 54, C = 100pF, (Figure 2)
Full
Full
Full
Full
Full
Full
Full
Full
25
15
-
24
2
50
10
25
70
70
70
70
150
-
ns
ns
DIFF
DIFF
DIFF
L
t
= 54, C = 100pF, (Figure 2)
L
SKEW
t , t
Driver Differential Rise or Fall Time
Driver Enable to Output High
Driver Enable to Output Low
Driver Disable from Output High
Driver Disable from Output Low
Receiver Input to Output Delay
= 54, C = 100pF, (Figure 2)
3
-
12
14
14
44
21
90
5
ns
R
F
L
t
C = 100pF, SW = GND, (Figure 3)
ns
ZH
L
t
C = 100pF, SW = V , (Figure 3)
CC
-
ns
ZL
L
t
C = 15pF, SW = GND, (Figure 3)
-
ns
HZ
L
t
C = 15pF, SW = V , (Figure 3)
-
ns
LZ
, t
L
CC
t
(Figure 4)
30
-
ns
PLH PHL
Receiver Skew | t
- t
PLH PHL
|
t
(Figure 4)
ns
SKD
Receiver Enable to Output High
Receiver Enable to Output Low
Receiver Disable from Output High
Receiver Disable from Output Low
Maximum Data Rate
t
C = 15pF, SW = GND, (Figure 5)
Full
Full
Full
Full
Full
-
9
50
50
50
50
-
ns
ZH
L
t
C = 15pF, SW = V , (Figure 5)
CC
-
9
ns
ZL
L
t
C = 15pF, SW = GND, (Figure 5)
-
9
ns
HZ
L
t
C = 15pF, SW = V , (Figure 5)
CC
-
9
ns
LZ
L
f
5
-
Mbps
MAX
SWITCHING CHARACTERISTICS (ISL8487, ISL81483)
Driver Input to Output Delay
Driver Output Skew
t
, t
PLH PHL
R
R
R
= 54, C = 100pF, (Figure 2)
Full
Full
Full
Full
Full
Full
Full
Full
25
250
-
650
160
900
1000
860
660
640
500
60
2000
800
2000
2000
2000
3000
3000
2000
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kbps
ns
DIFF
DIFF
DIFF
L
t
= 54, C = 100pF, (Figure 2)
L
SKEW
t , t
Driver Differential Rise or Fall Time
Driver Enable to Output High
Driver Enable to Output Low
Driver Disable from Output High
Driver Disable from Output Low
Receiver Input to Output Delay
= 54, C = 100pF, (Figure 2)
250
250
250
300
300
250
-
R
F
L
t
C = 100pF, SW = GND, (Figure 3, Note 5)
L
ZH
t
C = 100pF, SW = V , (Figure 3, Note 5)
CC
ZL
L
t
C = 15pF, SW = GND, (Figure 3)
HZ
L
t
C = 15pF, SW = V , (Figure 3)
LZ
, t
L
CC
t
(Figure 4)
PLH PHL
Receiver Skew | t
- t
PLH PHL
|
t
(Figure 4)
SKD
Receiver Enable to Output High
Receiver Enable to Output Low
Receiver Disable from Output High
Receiver Disable from Output Low
Maximum Data Rate
t
C = 15pF, SW = GND, (Figure 5, Note 6)
Full
Full
Full
Full
Full
Full
-
10
50
ZH
L
t
C = 15pF, SW = V , (Figure 5, Note 6)
CC
-
10
50
ZL
L
t
C = 15pF, SW = GND, (Figure 5)
-
10
50
HZ
L
t
C = 15pF, SW = V , (Figure 5)
-
10
50
LZ
L
CC
f
250
50
-
-
MAX
Time to Shutdown
t
(Note 7)
120
600
SHDN
FN6050 Rev 8.00
March 14, 2016
Page 5 of 14
ISL8487, ISL81483, ISL81487
Electrical Specifications Test Conditions: V = 4.5V to 5.5V; Unless Otherwise Specified. Typicals are at V
= 5V, T = 25°C,
A
CC
CC
(Note 2) (Continued)
TEMP
PARAMETER
SYMBOL
TEST CONDITIONS
C = 100pF, SW = GND, (Figure 3, Notes 7, 8)
(°C)
MIN
TYP
1000
MAX UNITS
Driver Enable from Shutdown to
Output High
t
Full
-
2000
2000
2500
2500
ns
ns
ns
ns
ZH(SHDN)
L
Driver Enable from Shutdown to
Output Low
t
C = 100pF, SW = V , (Figure 3, Notes 7, 8)
CC
Full
Full
Full
-
-
-
1000
800
ZL(SHDN)
L
Receiver Enable from Shutdown to
Output High
t
C = 15pF, SW = GND, (Figure 5, Notes 7, 9)
L
ZH(SHDN)
Receiver Enable from Shutdown to
Output Low
t
C = 15pF, SW = V , (Figure 5, Notes 7, 9)
CC
800
ZL(SHDN)
L
NOTES:
2. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
3. Supply current specification is valid for loaded drivers when DE = 0V.
4. Applies to peak current. See “Typical Performance Curves” for more information.
5. When testing the ISL8487 and ISL81483, keep RE = 0 to prevent the device from entering SHDN.
6. When testing the ISL8487 and ISL81483, the RE signal high time must be short enough (typically <200ns) to prevent the device from entering
SHDN.
7. The ISL8487 and ISL81483 are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 50ns, the parts are
guaranteed not to enter shutdown. If the inputs are in this state for at least 600ns, the parts are guaranteed to have entered shutdown. See
“Low-Power Shutdown Mode” section.
8. Keep RE = V , and set the DE signal low time >600ns to ensure that the device enters SHDN.
CC
9. Set the RE signal high time >600ns to ensure that the device enters SHDN.
10. Devices meeting these limits are denoted as “1/8 unit load (1/8 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus,
so there can be 256 1/8 UL devices on a bus.
11. Devices meeting these limits are denoted as “1/4 unit load (1/4 UL)” transceivers. The RS-485 standard allows up to 32 Unit Loads on the bus,
so there can be 128 1/4 UL devices on a bus.
Test Circuits and Waveforms
R
DE
V
CC
Z
Y
DI
V
D
OD
V
R
OC
FIGURE 1. DRIVER V
AND V
OD
OC
FN6050 Rev 8.00
March 14, 2016
Page 6 of 14
ISL8487, ISL81483, ISL81487
Test Circuits and Waveforms (Continued)
3V
0V
DI
1.5V
PLH
1.5V
PHL
t
t
t
V
OH
C
= 100pF
50%
50%
50%
L
OUT (Y)
DE
DI
V
V
OL
CC
Z
Y
t
R
PHL
PLH
DIFF
D
V
C
= 100pF
OH
L
OUT (Z)
50%
90%
SIGNAL
GENERATOR
V
OL
+V
OD
90%
10%
DIFF OUT (Y - Z)
10%
-V
OD
t
t
R
F
SKEW = |t
(Y or Z) - t
(Z or Y)|
PHL
PLH
FIGURE 2A. TEST CIRCUIT
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES
DE
DI
Z
Y
500
V
CC
3V
D
GND
SW
SIGNAL
GENERATOR
DE
1.5V
1.5V
HZ
NOTE 7
C
L
0V
t
, t
ZH ZH(SHDN)
NOTE 7
t
(SHDN) for ISL8487 and ISL81483 only.
OUTPUT HIGH
2.3V
V
OH
V
- 0.5V
OH
PARAMETER OUTPUT
RE
X
DI
SW
GND
C (pF)
L
OUT (Y, Z)
t
Y/Z
Y/Z
Y/Z
Y/Z
Y/Z
Y/Z
1/0
0/1
1/0
0/1
1/0
0/1
15
HZ
0V
t
X
V
15
LZ
CC
GND
t
, t
t
ZL ZL(SHDN)
LZ
t
0 (Note 5)
0 (Note 5)
1 (Note 7)
1 (Note 7)
100
100
100
100
ZH
NOTE 7
V
CC
t
V
ZL
ZH(SHDN)
CC
GND
OUT (Y, Z)
2.3V
t
V
+ 0.5V
V
OL
OL
t
V
CC
ZL(SHDN)
OUTPUT LOW
FIGURE 3A. TEST CIRCUIT
FIGURE 3B. MEASUREMENT POINTS
FIGURE 3. DRIVER ENABLE AND DISABLE TIMES
RE
3V
0V
15pF
A
B
1.5V
PLH
1.5V
PHL
+1.5V
RO
R
A
t
t
V
SIGNAL
GENERATOR
CC
50%
50%
RO
0V
FIGURE 4A. TEST CIRCUIT
FIGURE 4B. MEASUREMENT POINTS
FIGURE 4. RECEIVER PROPAGATION DELAY
FN6050 Rev 8.00
March 14, 2016
Page 7 of 14
ISL8487, ISL81483, ISL81487
Test Circuits and Waveforms (Continued)
RE
NOTE 7
3V
0V
B
1k
V
CC
RO
RE
R
1.5V
1.5V
HZ
GND
SW
SIGNAL
A
15pF
GENERATOR
t
, t
ZH ZH(SHDN)
NOTE 7
t
OUTPUT HIGH
1.5V
(SHDN) for ISL8487 and ISL81483 only.
V
OH
V
- 0.5V
OH
PARAMETER
DE
0
A
SW
RO
0V
t
+1.5V
-1.5V
+1.5V
-1.5V
+1.5V
-1.5V
GND
HZ
t
0
V
t
, t
LZ
CC
ZL ZL(SHDN)
t
LZ
NOTE 7
t
(Note 6)
(Note 6)
0
GND
V
ZH
CC
RO
t
0
V
1.5V
ZL
CC
V
+ 0.5V
V
OL
OL
t
(Note 7)
(Note 7)
0
GND
ZH(SHDN)
OUTPUT LOW
t
0
V
CC
ZL(SHDN)
FIGURE 5A. TEST CIRCUIT
FIGURE 5. RECEIVER ENABLE AND DISABLE TIMES
FIGURE 5B. MEASUREMENT POINTS
Receiver inputs function with common mode voltages as
Application Information
great as 7V outside the power supplies (i.e., +12V and
-7V), making them ideal for long networks where induced
voltages are a realistic concern.
RS-485 and RS-422 are differential (balanced) data
transmission standards for use in long haul or noisy
environments. RS-422 is a subset of RS-485, so RS-485
transceivers are also RS-422 compliant. RS-422 is a point-
to-multipoint (multidrop) standard, which allows only one
driver and up to 10 (assuming one unit load devices)
receivers on each bus. RS-485 is a true multipoint standard,
which allows up to 32 one unit load devices (any
combination of drivers and receivers) on each bus. To allow
for multipoint operation, the RS-485 spec requires that
drivers must handle bus contention without sustaining any
damage.
All the receivers include a “fail-safe if open” function that
guarantees a high level receiver output if the receiver inputs
are unconnected (floating).
Receivers easily meet the data rates supported by the
corresponding driver, and receiver outputs are three-statable
via the active low RE input.
Driver Features
The RS-485 and RS-422 driver is a differential output device
that delivers at least 1.5V across a 54 load (RS-485), and
at least 2V across a 100 load (RS-422). The drivers feature
low propagation delay skew to maximize bit width, and to
minimize EMI.
Another important advantage of RS-485 is the extended
common mode range (CMR), which specifies that the driver
outputs and receiver inputs withstand signals that range from
+12V to -7V. RS-422 and RS-485 are intended for runs as
long as 4000’, so the wide CMR is necessary to handle
ground potential differences, as well as voltages induced in
the cable by external fields.
Driver outputs are three-statable via the active high DE
input.
The ISL8487 and ISL81483 driver outputs are slew rate
limited to minimize EMI, and to minimize reflections in
unterminated or improperly terminated networks. Data rate
on these slew rate limited versions is a maximum of
250kbps. ISL81487 drivers are not limited, so faster output
transition times allow data rates of at least 5Mbps.
Receiver Features
These devices utilize a differential input receiver for maximum
noise immunity and common mode rejection. Input sensitivity
is 200mV, as required by the RS-422 and RS-485
specifications.
Receiver input resistance of 96k surpasses the RS-422
spec of 4k, and is eight times the RS-485 “Unit Load (UL)”
requirement of 12k minimum. Thus, these products are
known as “one-eighth UL” transceivers, and there can be up
to 256 of these devices on a network while still complying
with the RS-485 loading spec.
Data Rate, Cables, and Terminations
RS-485 and RS-422 are intended for network lengths up to
4000’, but the maximum system data rate decreases as the
transmission length increases. Devices operating at 5Mbps
are limited to lengths less than a few hundred feet, while the
FN6050 Rev 8.00
March 14, 2016
Page 8 of 14
ISL8487, ISL81483, ISL81487
250kbps versions can operate at full data rates with lengths
in excess of 1000’.
exceeds the RS-485 spec, even at the common mode
voltage range extremes. Additionally, these devices utilize a
foldback circuit which reduces the short circuit current, and
thus the power dissipation, whenever the contending voltage
exceeds either supply.
Twisted pair is the cable of choice for RS-485/RS-422
networks. Twisted pair cables tend to pick up noise and
other electromagnetically induced voltages as common
mode signals, which are effectively rejected by the
differential receivers in these ICs.
In the event of a major short circuit condition, these devices
also include a thermal shutdown feature that disables the
drivers whenever the die temperature becomes excessive.
This eliminates the power dissipation, allowing the die to
cool. The drivers automatically re-enable after the die
temperature drops about 15 degrees. If the contention
persists, the thermal shutdown/re-enable cycle repeats until
the fault is cleared. Receivers stay operational during
thermal shutdown.
To minimize reflections, proper termination is imperative
when using the 5Mbps device. Short networks using the
250kbps versions need not be terminated, but, terminations
are recommended unless power dissipation is an overriding
concern.
In point-to-point, or point-to-multipoint (single driver on bus)
networks, the main cable should be terminated in its
characteristic impedance (typically 120) at the end farthest
from the driver. In multi-receiver applications, stubs
connecting receivers to the main cable should be kept as
short as possible. Multipoint (multi-driver) systems require
that the main cable be terminated in its characteristic
impedance at both ends. Stubs connecting a transceiver to
the main cable should be kept as short as possible.
Low Power Shutdown Mode (Excluding ISL81487)
These CMOS transceivers all use a fraction of the power
required by their bipolar counterparts, but the ISL8487 and
ISL81483 include a shutdown feature that reduces the
already low quiescent I
to a 500nA trickle. They enter
CC
shutdown whenever the receiver and driver are
simultaneously disabled (RE = V and DE = GND) for a
CC
Built-In Driver Overload Protection
period of at least 600ns. Disabling both the driver and the
receiver for less than 50ns guarantees that shutdown is not
entered.
As stated previously, the RS-485 spec requires that drivers
survive worst case bus contentions undamaged. These
devices meet this requirement via driver output short circuit
current limits, and on-chip thermal shutdown circuitry.
Note that receiver and driver enable times increase when
enabling from shutdown. Refer to Notes 5-9, at the end of
the Electrical Specification table, for more information.
The driver output stages incorporate short circuit current
limiting circuitry which ensures that the output current never
Typical Performance Curves V = 5V, T = 25°C, ISL8487, ISL81483 and ISL81487; Unless Otherwise Specified
CC
A
3.6
3.4
3.2
3
90
80
70
60
50
40
30
R
= 100
DIFF
2.8
2.6
2.4
2.2
2
R
= 54
DIFF
20
10
0
0
1
2
3
4
5
-40
0
50
85
-25
25
75
DIFFERENTIAL OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 6. DRIVER OUTPUT CURRENT vs DIFFERENTIAL
OUTPUT VOLTAGE
FIGURE 7. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs
TEMPERATURE
FN6050 Rev 8.00
March 14, 2016
Page 9 of 14
ISL8487, ISL81483, ISL81487
Typical Performance Curves V = 5V, T = 25°C, ISL8487, ISL81483 and ISL81487; Unless Otherwise Specified (Continued)
CC
A
400
160
140
120
ISL81487E, DE = V , RE = X
CC
ISL81487E
350
300
Y OR Z = LOW
100
80
ISL81487E, DE = GND, RE = X
ISL8487E, ISL81487L
60
40
20
0
250
200
150
100
-20
-40
-60
Y OR Z = HIGH
ISL8487E, ISL81487L, DE = V , RE = X
CC
ISL81487E
ISL8487E, ISL81487L
-80
ISL8487E, ISL81487L, DE = GND, RE = GND
-100
-120
-7 -6
-4
-2
0
2
4
6
8
10
12
-40
0
50
85
85
85
-25
25
75
OUTPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 8. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT
VOLTAGE
FIGURE 9. SUPPLY CURRENT vs TEMPERATURE
250
200
150
100
50
750
700
t
PLHY
t
|t
- t |
PLHY PHLZ
PLHZ
650
600
550
500
450
|t |
- t
PHLY PLHZ
t
PHLY
t
PHLZ
|CROSS PT. OF Y & Z - CROSS PT. OF Y & Z|
0
-40
-40
0
50
85
0
50
-25
25
75
-25
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 10. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL8487, ISL81483)
FIGURE 11. DRIVER SKEW vs TEMPERATURE
(ISL8487, ISL81483)
30
28
5
4
|t
- t
PHLY PLHZ|
26
24
22
20
18
16
3
2
1
0
|t
- t
PLHY PHLZ|
t
PLHY
t
PHLZ
t
PLHZ
|CROSSING PT. OF Y & Z - CROSSING PT. OF Y & Z|
t
PHLY
-25
-40
0
50
85
-40
0
50
25
75
-25
25
75
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 12. DRIVER PROPAGATION DELAY vs
TEMPERATURE (ISL81487)
FIGURE 13. DRIVER SKEW vs TEMPERATURE
(ISL81487)
FN6050 Rev 8.00
March 14, 2016
Page 10 of 14
ISL8487, ISL81483, ISL81487
Typical Performance Curves V = 5V, T = 25°C, ISL8487, ISL81483 and ISL81487; Unless Otherwise Specified (Continued)
CC
A
R
= 54, C = 100pF
R
= 54, C = 100pF
DIFF L
DIFF
L
5
0
5
0
DI
DI
5
0
5
0
RO
RO
4
4
B/Z
A/Y
A/Y
B/Z
3
2
3
2
1
0
1
0
TIME (400ns/DIV)
TIME (400ns/DIV)
FIGURE 14. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL8487, ISL81483)
FIGURE 15. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL8487, ISL81483)
R
= 54, C = 100pF
R
= 54, C = 100pF
DIFF L
DIFF
L
5
0
5
0
DI
DI
5
0
5
0
RO
RO
4
4
B/Z
A/Y
B/Z
3
3
2
1
0
2
1
0
A/Y
TIME (20ns/DIV)
TIME (20ns/DIV)
FIGURE 16. DRIVER AND RECEIVER WAVEFORMS,
LOW TO HIGH (ISL81487)
FIGURE 17. DRIVER AND RECEIVER WAVEFORMS,
HIGH TO LOW (ISL81487)
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
518
PROCESS:
Si Gate CMOS
FN6050 Rev 8.00
March 14, 2016
Page 11 of 14
ISL8487, ISL81483, ISL81487
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not
warranted. Please go to the web to make sure that you have the latest revision.
DATE
REVISION
CHANGE
March 14, 2016
FN6050.8
Added Rev History and About Intersil Verbiage.
Updated “Ordering Information” table on page 2.
Updated M8.15 to current revision. POD revision changes are as follows:
Note 1 "1982" to "1994
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2004-2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6050 Rev 8.00
March 14, 2016
Page 12 of 14
ISL8487, ISL81483, ISL81487
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1 2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN6050 Rev 8.00
March 14, 2016
Page 13 of 14
ISL8487, ISL81483, ISL81487
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN6050 Rev 8.00
March 14, 2016
Page 14 of 14
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