ISL85003A_技术文档

DATASHEET

ISL85005, ISL85005A

4.5V to 18V Input, 5A High Efficiency Synchronous Buck Regulator

FN8871

Rev.2.00

May 17, 2018

The ISL85005 and ISL85005A are monolithic, synchronous

Features

buck regulators with integrated 5A, 18V high-side and low-side

FETs. These devices provide an integrated bootstrap diode for

the high-side gate driver to reduce the external parts count.

These devices also have a wide input voltage range to support

applications with input voltage from multi-cell batteries or

regulated 5V and 12V power rails.

• 4.5V to 18V input voltage range

• Internal 5A, 18V high-side and low-side MOSFET switches

• ±1%, 0.8V feedback voltage reference

• Integrated bootstrap diode with undervoltage detection

• Current mode control with internal slope compensation

• Internal or external compensation options

The ISL85005 and ISL85005A regulate the output voltage

with current mode control and have an internal oscillator. The

switching frequency of the ISL85005 is internally set as

500kHz, and can be synchronized to an external clock signal

with frequency ranges from 300kHz to 2MHz. The ISL85005A

has a fixed 500kHz switching frequency.

• Default internally set 500kHz switching frequency

• Synchronization capability to external clock (ISL85005)

• Diode Emulation Mode (DEM) and Forced CCM (FCCM)

options (ISL85005)

The ISL85005 has a fixed 2.3ms soft-start, while the

ISL85005A features programmable soft-start to limit inrush

current during startup. With the SS pin floating, the soft-start

time of ISL85005A is also 2.3ms.

• Adjustable soft-start time (ISL85005A)

• Output Power-Good (PG) indicator

• Input Undervoltage Lockout (UVLO), input and output

overvoltage protection

The ISL85005 can be configured in either forced Continuous

Conduction Mode (CCM) or Diode Emulation Mode (DEM). DEM

enables high efficiency at light-load conditions. The

ISL85005A always operates in forced CCM.

• High-side cycle-by-cycle current limit, low-side forward and

reverse overcurrent protection, and thermal shutdown

• Small 12-pin 3mmx4mm Dual Flat No-Lead (DFN) package

with EPAD for enhanced thermal performance

The ISL85005 and ISL85005A have built-in protections

including input UVLO protection, input and output overvoltage

protection, high-side cycle-by-cycle current limit, low-side

forward current limit and reverse current limit, and thermal

shutdown.

Applications

• Network and communications equipment

• Battery powered systems

• Multifunction printers

Related Literature

For a full list of related documents, visit our website

• Point-of-load regulators

• Standard 12V rail supplies

• Embedded computing systems

• ISL85005, ISL85005A product pages

Typical Application

95

90

85

80

75

70

ISL85005

GND = DEM; VCC = FCCM

SYNC/

MODE

BOOT

VDD

1

2

3

4

5

6

12

11

C

4

V

IN

PG

EN

PG

4.5V TO 18V

EN

VIN 10

PGND

VIN

9

C

FB

C

6

3

C

5

V

R

1

OUT

2

PHASE

COMP

AGND

8

7

12V TO 5V

R

1

5A MAX

65

C

12V TO 3.3V

L

1

60

C

12V TO 1.8V

8

9

55

50

0

1

2

3

4

5

OUTPUT CURRENT (A)

FIGURE 1. ISL85005 WITH INTERNAL COMPENSATION

FIGURE 2. EFFICIENCY vs OUTPUT CURRENT

FN8871 Rev.2.00

May 17, 2018

Page 1 of 23

ISL85005, ISL85005A

Table of Contents

Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Operation Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

FCCM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Light-Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Enable, Soft-Start, and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Forward Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reverse Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Input Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Boot Undervoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Switching Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Compensator Design Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

High DC Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

FN8871 Rev.2.00

May 17, 2018

Page 2 of 23

ISL85005, ISL85005A

Functional Block Diagram

SS (ISL85005A)

SOFT-START

CONTROL

BOOT

1

12

11

BOOT

UVP

SYNC/MODE (ISL85005)

VDD

VIN

UNDERVOLTAGE

LOCKOUT

LDO

9

EN

OSCILLATOR

10

CSA

PG

2

0.8V

FAULT

+

REFERENCE

MONITOR

CIRCUITS

SLOPE

COMP

+

-

PHASE

PGND

7

8

EN

GATE DRIVE

CONTROL

CIRCUIT

3

VDD

+

THERMAL

SHUTDOWN

EA

13

-

FB

600k

30pF

4

5

ZERO CROSS

DETECTOR

AND

NEGATIVE

CURRENT

LIMIT

COMP

AGND

GND DETECTION

CIRCUIT

POSITIVE

LS OCP

6

FIGURE 3. BLOCK DIAGRAM

FN8871 Rev.2.00

May 17, 2018

Page 3 of 23

ISL85005, ISL85005A

Pin Configurations

ISL85005

(12 LD 3x4 DFN)

TOP VIEW

ISL85005A

(12 LD 3x4 DFN)

TOP VIEW

SS

PG

SYNC/MODE

1

2

3

4

5

6

12 BOOT

11

10

9

PG

EN

2

3

4

5

6

11

10

9

VDD

EN

VIN

PGND

(EPAD)

FB

VIN

FB

VIN

COMP

AGND

8

PHASE

COMP

AGND

8

PHASE

7

Pin Descriptions

NUMBER

NAME

DESCRIPTION

1

SYNC/ Synchronization and mode selection input. Connect to VDD for Forced Continuous Conduction Mode (FCCM). Connect to AGND

MODE for Diode Emulation Mode (DEM). Connect to an external function generator for synchronization with the positive edge trigger.

The internal 1MΩ pull-up resistor to VDD prevents an undefined logic state when SYNC is floating.

(ISL85005)

1

SS

Soft-start input. This pin provides a programmable soft-start. When the chip is enabled, the regulated 3.5µA pull-up current

source charges a capacitor connected from SS to ground. The output voltage of the converter follows the ramping voltage on

this pin. Without the external capacitor, the default soft-start is 2.3ms.

(ISL85005A)

2

PG

Power-good, open-drain output. Connect a 10kΩ to 100kΩ pull-up resistor between PG and VDD or between PG and a voltage

not exceeding 5.5V. PG transitions high about 1.5ms after the switching regulator’s output voltage reaches the regulation

threshold, which is typically 85% of the regulated output voltage.

3

4

EN

FB

Enable input. The regulator is held off when the pin is pulled to ground. The device is enabled when the voltage on this pin rises

above 0.6V.

Feedback input. The synchronous buck regulator employs a current mode control loop. FB is the negative input to the voltage

loop error amplifier. The output voltage is set by an external resistor divider connected to FB. The output voltage can be set to

any voltage between the power rail (reduced by converter losses) and the 0.8V reference.

5

6

COMP Compensation node. This pin is connected to the output of the error amplifier and compensates the loop. Internal

compensation meets most applications. Connect COMP to AGND to select internal compensation. Connect a compensation

network between COMP and FB to use external compensation.

AGND The AGND terminal. Provides the return path for the core analog control circuitry within the device. Connect AGND to the board

ground plane. AGND and PGND are connected internally within the device. Do not operate the device with AGND and PGND

connected to dissimilar voltages.

7, 8

PHASE Phase switch output node. Connect to the external output inductor.

9, 10

VIN

Voltage supply input. The main power input for the IC. Connect to a suitable voltage supply. Place a ceramic capacitor from VIN

to PGND, close to the IC for decoupling.

11

VDD

Low dropout linear regulator decoupling pin. VDD is the internally generated 5V supply voltage and is derived from VIN. The

VDD powers all the internal core analog control blocks and drivers. Connect a 1µF capacitor from VDD to the board ground

plane. If VIN is between 3V to 5.5V, then connect VDD directly to VIN to improve efficiency.

12

BOOT Bootstrap input. A floating bootstrap supply pin for the upper power MOSFET gate driver. Connect a 0.1µF capacitor between

BOOT and PHASE.

(EPAD)

PGND Power ground terminal. Provides thermal relief for the package and is connected to the source of the low-side output MOSFET.

Connect PGND to the board ground plane using as many vias as possible. AGND and PGND are connected internally within the

device. Do not operate the device with AGND and PGND connected to dissimilar voltages.

FN8871 Rev.2.00

May 17, 2018

Page 4 of 23

ISL85005, ISL85005A

Ordering Information

PART NUMBER

(Notes 2, 3, 4)

PART

MARKING

TEMP. RANGE

(°C)

FREQUENCY TAPE AND REEL

PACKAGE

PKG.

DWG. #

OPTION

(kHz) (UNITS) (Note 1) (RoHS COMPLIANT)

ISL85005FRZ

005F

-40 to +125 SYNC

500

-

12 Ld DFN

L12.3x4

ISL85005FRZ-T

ISL85005FRZ-TK

ISL85005FRZ-T7A

ISL85005AFRZ

005F

-40 to +125 SYNC

6k

1k

250

-

L12.3x4

005F

-40 to +125 SYNC

005F

-40 to +125 SYNC

005A

-40 to +125 SOFT-START

ISL85005AFRZ-T

ISL85005AFRZ-TK

ISL85005AFRZ-T7A

ISL85005AEVAL1Z

ISL85005ADEMO1Z

ISL85005EVAL1Z

ISL85005DEMO1Z

NOTES:

005A

6k

1k

250

005A

Evaluation Board

Demonstration Board

Evaluation Board

Demonstration Board

1. Refer to TB347 for details about reel specifications.

2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), see the ISL85005, ISL85005A product information pages. For more information about MSL, refer to TB363.

4. The ISL85005 is provided with a frequency synchronization input. The ISL85005A is a version of the part with programmable soft-start.

TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

INTERNAL/EXTERNAL

COMPENSATION

EXTERNAL FREQUENCY

SYNC

PROGRAMMABLE

SOFT-START

SWITCHING

FREQUENCY (kHz)

CURRENT

RATING

PART NUMBER

ISL85005A

ISL85005

Yes

No

Yes

No

Yes

No

500

5A

3A

ISL85003

No

ISL85003A

Yes

FN8871 Rev.2.00

May 17, 2018

Page 5 of 23

ISL85005, ISL85005A

Typical Application Schematics

ISL85005

GND = DEM; VCC = FCCM

MODE

SYNC/

MODE

BOOT

VDD

VIN

1

2

3

4

5

6

12

11

10

9

C

4

V

PG

EN

PG

EN

IN

4.5V TO 18V

PGND

VIN

C

FB

3

C

6

5

R

2

PHASE

8

COMP

AGND

V

OUT

5A MAX

R

1

C

1

7

L

1

C

8

9

FIGURE 4. ISL85005 V RANGE FROM 4.5V TO 18V WITH INTERNAL COMPENSATION

IN

ISL85005A

C

SS

BOOT

VDD

SS

1

2

3

4

5

6

12

11

C

4

PG

EN

V

PG

EN

IN

4.5V TO 18V

VIN 10

PGND

VIN

9

8

7

C

3

FB

C

5

6

R

2

PHASE

COMP

AGND

V

OUT

R

1

5A MAX

C

1

PHASE

L

1

C

8

9

FIGURE 5. ISL85005A V RANGE FROM 4.5V TO 18V, WITH INTERNAL COMPENSATION WITH PROGRAMMABLE SOFT-START

IN

TABLE 2. COMPONENTS SELECTION (REFER TO Figures 1 AND 2)

V

1.2V

1OµF

47µF

1.8V

1OµF

47µF

2.5V

1OµF

47µF

3.3V

1OµF

47µF

5V

OUT

C , C

1OµF

47µF

5

6

9

C , C

8

C

12pF

1

L

3.3µH

499kΩ

998kΩ

3.3µH

499kΩ

392kΩ

3.3µH

499kΩ

232kΩ

3.3µH

499kΩ

157kΩ

3.3µH

499kΩ

95.3kΩ

1

R

1

2

NOTE: V = 12V, I

IN

= 5A; The components selection table is a suggestion for typical application using internal compensation mode. For application

OUT

that requires high output capacitance greater than 200µF, R should be adjusted to maintain loop response bandwidth about 40kHz. See “Loop

1

Compensation Design” on page 19 for more detail.

FN8871 Rev.2.00

May 17, 2018

Page 6 of 23

ISL85005, ISL85005A

Absolute Maximum Ratings

Thermal Information

VIN, EN to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 24V

PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +24V (DC)

PHASE to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . -2V to +24V (40ns)

FB to AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 7V

BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to + 7V

VDD, COMP, SYNC, PG to AGND and PGND. . . . . . . . . . . . . . . -0.3V to + 7V

Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . .-55°C to +150°C

ESD Rating

Thermal Resistance

DFN Package (Notes 5, 6) . . . . . . . . . . . . . .

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493



(°C/W)

41



(°C/W)

3

JA

JC

Recommended Operating Conditions

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . .2.5kV

Machine Model (Tested per JESD22-A115-C) . . . . . . . . . . . . . . . . . 150V

Charged Device Model (Tested per JESD22-C101-E) . . . . . . . . . . . . . 1kV

Latch-Up (Tested per JESD-78D; Class 2, Level A) . . . . . . . . . . . . . . 100mA

V

Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V

IN

Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 5A

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5.  is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379.

JA

6. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications All parameter limits are established over the recommended operating conditions with T = -40°C to +125°C,

J

and with V = 12V unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across the operating junction temperature range,

IN

A

-40°C to +125°C.

MIN

MAX

PARAMETER

SUPPLY VOLTAGE

SYMBOL

TEST CONDITIONS

(Note 7) TYP (Note 7) UNIT

V

Voltage Range

V

I

4.5

18

4.5

11

V

IN

Quiescent Supply Current

Shutdown Supply Current

SYNC = Low, EN > 1V, FB = 0.85V, not switching

EN = AGND

3.2

6

mA

µA

Q

I

SD

UNDERVOLTAGE LOCKOUT

UVLO Threshold

V

Rising edge

Falling edge

4.20

3.8

4.35

5.50

V

IN

3.5

INTERNAL VDD LDO

V

Output Voltage

V

= 6V to 18V, I = 0mA to 30mA

VDD

4.30

5.00

50

V

DD

IN

Output Current Limit

mA

OSCILLATOR

Nominal Switching Frequency

Minimum On-Time

Minimum Off-Time

Synchronization Range

SYNC High-Time

f

400

500

120

140

600

140

kHz

ns

kHz

ns

V

SW

t

I

= 0mA (Note 8)

OUT

ON

t

(Note 8)

180

OFF

SYNC ISL85005

300

100

2000

t

ISL85005

HI

SYNC Low-Time

t

LO

SYNC Logic Input Low

SYNC Logic Input High

ERROR AMPLIFIER

FB Regulation Voltage

FB Leakage Current

Open-Loop Bandwidth

Gain

0.50

1.20

V

= 4.5V to 18V

0.792 0.800 0.808

V

FB

IN

= 0.8V (Note 8)

0.3

5.5

70

10.0

nA

FB

BW

MHz

dB

FN8871 Rev.2.00

May 17, 2018

Page 7 of 23

ISL85005, ISL85005A

Electrical Specifications All parameter limits are established over the recommended operating conditions with T = -40°C to +125°C,

J

and with V = 12V unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply across the operating junction temperature range,

IN

A

-40°C to +125°C. (Continued)

MIN

MAX

PARAMETER

Output Drive

SYMBOL

TEST CONDITIONS

(Note 7) TYP (Note 7) UNIT

V

= 1.5V

±110

0.15

550

µA

Ω

COMP

Current Sense Gain

Slope Compensation

ENABLE INPUT

RT

Se

f

= 500kHz

mV/µs

SW

EN Input Threshold

Rising edge

Hysteresis

0.5

60

0.6

0.7

V

100

140

mV

SOFT-START FUNCTION

Default Soft-Start Time

SS Internal Soft-Start Charging Current

POWER-GOOD OPEN-DRAIN OUTPUT

Output Low Voltage

ISL85005, ISL85005A with SS pin floating

ISL85005A

1.0

2.5

2.3

3.5

3.6

4.5

ms

µA

I

= 5mA sinking

0.25

0.01

85

V

µA

%

PG

PG Pin Leakage Current

PG Lower Threshold

V

= V

PG DD

Percentage of output regulation

80

90

PG Upper Threshold

110

115

3

120

%

PG Thresholds Hysteresis

Delay Time

%

Rising edge

Falling edge

1.5

18

ms

µs

FAULT PROTECTION

A

High-Side MOSFET Forward Current Limit

Threshold

I

6

7.8

-3.3

8.6

9.5

POCP

Low-Side MOSFET Reverse Current Limit

Threshold

I

Current forced into PHASE node, high-side MOSFET is off,

SYNC = High

NOCP

Low-Side MOSFET Forward Current Limit

Threshold

Current in low-side MOSFET at end of low-side cycle.

V

Overvoltage Threshold

V

rising

IN

19

20

1

V

IN

Hysteresis

Thermal Shutdown Threshold

T

Temperature rising

Hysteresis

165

10

°C

SD

T

HYS

POWER MOSFET

High-Side MOSFET On-Resistance

Low-Side MOSFET On-Resistance

PHASE Pull-Down Resistor

DIODE EMULATION

R

I

= 100mA

57

40

10

95

75

mΩ

kΩ

HDS

PHASE

R

LDS

EN = AGND

Zero-Cross Detection Threshold

NOTE:

ISL85005

150

mA

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.

8. Compliance to limits is assured by characterization and design.

FN8871 Rev.2.00

May 17, 2018

Page 8 of 23

ISL85005, ISL85005A

Typical Characteristics

V

= 12V, T = +25°C, unless otherwise noted.

A

IN

10

9

8

7

6

5

4

3

2

1

0

10

9

8

7

6

5

4

3

2

1

0

-40 -25 -10

5

20

35

50

65

80

95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (^oC)

FIGURE 7. V QUIESCENT CURRENT vs JUNCTION TEMPERATURE

IN

FIGURE 6. V SHUTDOWN CURRENT vs JUNCTION TEMPERATURE

IN

0.83

0.82

0.81

0.80

0.79

0.78

0.77

0.9

EN RISING

0.8

EN FALLING

0.7

0.6

0.5

0.4

0.3

0.2

-40 -25 -10

5

20

35

50

65

80

95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (^oC)

FIGURE 8. FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 9. ENABLE THRESHOLDS vs JUNCTION TEMPERATURE

4.5

560

540

520

500

480

460

440

420

400

UVLO START SWITCHING

UVLO STOP SWITCHING

4.3

4.1

3.9

3.7

3.5

3.3

-40 -25 -10

5

20

35

50

65

80

95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (^oC)

FIGURE 10. V UVLO THRESHOLD vs JUNCTION TEMPERATURE

IN

FIGURE 11. SWITCHING FREQUENCY vs JUNCTION TEMPERATURE

FN8871 Rev.2.00

May 17, 2018

Page 9 of 23

ISL85005, ISL85005A

Typical Characteristics

V

= 12V, T = +25°C, unless otherwise noted. (Continued)

A

IN

28

26

24

22

20

18

16

14

12

10

2.4

2.0

1.6

1.2

0.8

0.4

-40 -25 -10

5

20

35

50

65

80

95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (^oC)

FIGURE 13. PG DELAY (RISING) vs JUNCTION TEMPERATURE

FIGURE 12. PG DELAY (FALLING) vs JUNCTION TEMPERATURE

12

11

10

9

0

-1

-2

-3

-4

-5

-6

8

7

6

5

4

HIGH SIDE MOSFET

LOW SIDE MOSFET

-40 -25 -10

5

20

35

50

65

80

95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (^oC)

FIGURE 14. FORWARD OCP THRESHOLD vs JUNCTION TEMPERATURE

FIGURE 15. LOW-SIDE REVERSE OCP THRESHOLD vs JUNCTION

TEMPERATURE

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

-40 -25 -10

5

20

35

50

65

80

95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (^oC)

FIGURE 16. HIGH-SIDE r

vs JUNCTION TEMPERATURE

FIGURE 17. LOW-SIDE r vs JUNCTION TEMPERATURE

DS(ON)

FN8871 Rev.2.00

May 17, 2018

Page 10 of 23

ISL85005, ISL85005A

Typical Performance Curves Circuit of Figure 1. V = 12V, V = 5V, L = 3.3µH, f = 500kHz, T = +25°C, unless

IN

OUT

SW

A

otherwise noted.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

VIN = 12V, DEM

VIN = 5V, DEM

VIN = 12V, FORCED CCM

50

0

1

2

3

4

5

0

1

2

3

4

5

OUTPUT CURRENT (A)

FIGURE 19. EFFICIENCY vs LOAD, V

= 3.3V, DEM

FIGURE 18. EFFICIENCY vs LOAD, V

OUT

= 5V

OUT

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 12V, FORCED CCM

VIN = 5V, FORCED CCM

VIN = 12V, DEM

VIN = 5V, DEM

0

1

2

3

4

5

0

1

2

3

4

5

OUTPUT CURRENT (A)

FIGURE 20. EFFICIENCY vs LOAD, V

= 3.3V, FORCED CCM

FIGURE 21. EFFICIENCY vs LOAD, V

= 2.5V, DEM

OUT

100

95

90

85

80

75

70

65

100

95

90

85

80

75

70

65

60

55

50

VIN = 12V, DEM

VIN = 5V, DEM

60

55

50

VIN = 12V, FORCED CCM

VIN = 5V, FORCED CCM

0

1

2

3

4

5

0

1

2

3

4

5

OUTPUT CURRENT (A)

FIGURE 22. EFFICIENCY vs LOAD, V

= 2.5V, FORCED CCM

FIGURE 23. EFFICIENCY vs LOAD, V

= 1.8V, DEM

OUT

FN8871 Rev.2.00

May 17, 2018

Page 11 of 23

ISL85005, ISL85005A

Typical Performance Curves Circuit of Figure 1. V = 12V, V = 5V, L = 3.3µH, f = 500kHz, T = +25°C, unless

IN

OUT

SW

A

otherwise noted. (Continued)

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 12V, DEM

VIN = 5V, DEM

VIN = 12V, FORCED CCM

VIN = 5V, FORCED CCM

0

1

2

3

4

5

0

1

2

3

4

5

OUTPUT CURRENT (A)

FIGURE 25. EFFICIENCY vs LOAD, V

= 1.2V, DEM

FIGURE 24. EFFICIENCY vs LOAD, V

OUT

= 1.8V, FORCED CCM

OUT

100

95

90

85

80

75

70

65

60

55

50

V

(2V/DIV)

OUT

I

(2A/DIV)

L

VIN = 12V, FORCED CCM

VIN = 5V, FORCED CCM

EN (10V/DIV)

0

1

2

3

4

5

OU TPUT CURRENT (A)

1ms/DIV

FIGURE 26. EFFICIENCY vs LOAD, V

OUT

= 1.2V, FORCED CCM

FIGURE 27. START-UP WITH EN, NO LOAD

V

(2V/DIV)

V

(2V/DIV)

OUT

I

(2A/DIV)

L

I

(2A/DIV)

L

V

(5V/DIV)

IN

EN (10V/DIV)

1ms/DIV

2ms/DIV

FIGURE 28. START-UP WITH EN, I

= 5A

FIGURE 29. START-UP WITH V , NO LOAD

IN

OUT

FN8871 Rev.2.00

May 17, 2018

Page 12 of 23

ISL85005, ISL85005A

Typical Performance Curves Circuit of Figure 1. V = 12V, V = 5V, L = 3.3µH, f = 500kHz, T = +25°C, unless

IN

OUT

SW

A

otherwise noted. (Continued)

V

(2V/DIV)

OUT

V

(2V/DIV)

OUT

I

(2A/DIV)

L

I

(2A/DIV)

L

V

(5V/DIV)

IN

EN (10V/DIV)

50ms/DIV

2ms/DIV

FIGURE 30. START-UP WITH V , I

IN OUT

= 5A

FIGURE 31. SHUTDOWN WITH EN, I

= 10mA

OUT

V

(2V/DIV)

OUT

V

(2V/DIV)

OUT

I

(2A/DIV)

L

I

(2A/DIV)

L

V

(10V/DIV)

IN

EN (10V/DIV)

200µs/DIV

50ms/DIV

FIGURE 32. SHUTDOWN WITH EN, I

= 5A

FIGURE 33. SHUTDOWN WITH V , I = 10mA

IN OUT

OUT

V

(2V/DIV)

OUT

I

(500mA/DIV)

L

I

(2A/DIV)

L

V

(10V/DIV)

IN

PHASE (5V/DIV)

200µs/DIV

1µs/DIV

FIGURE 34. SHUTDOWN WITH V , I

IN OUT

= 5A

FIGURE 35. STEADY STATE OPERATION IN DCM, I

= 0.2A

OUT

FN8871 Rev.2.00

May 17, 2018

Page 13 of 23

ISL85005, ISL85005A

Typical Performance Curves Circuit of Figure 1. V = 12V, V = 5V, L = 3.3µH, f = 500kHz, T = +25°C, unless

IN

OUT

SW

A

otherwise noted. (Continued)

I

(500mA/DIV)

L

V

(100mV/DIV),

OUT

AC COUPLING

I

(1A/DIV)

OUT

PHASE (5V/DIV)

1µs/DIV

50µs/DIV

FIGURE 37. LOAD TRANSIENT, 0A → 2.5A → 0A, 2.5A/µs

FIGURE 36. STEADY STATE IN FORCED CCM, I

= 0.2A

OUT

V

(200mV/DIV),

OUT

AC COUPLING

V

(2V/DIV)

OUT

I

(2A/DIV)

L

I

(2A/DIV)

OUT

50µs/DIV

2ms/DIV

FIGURE 38. LOAD TRANSIENT, 0A → 5A → 0A, 2.5A/µs

FIGURE 39. HIGH-SIDE FORWARD OVER CURRENT PROTECTION

I

(2A/DIV)

L

I

(2A/DIV)

L

PHASE (5V/DIV)

PHASE (10V/DIV)

1µs/DIV

20µs/DIV

FIGURE 40. OUTPUT SHORT-CIRCUIT BEHAVIOR

FIGURE 41. LOW-SIDE MOSFET REVERSE OVER CURRENT

PROTECTION

FN8871 Rev.2.00

May 17, 2018

Page 14 of 23

ISL85005, ISL85005A

The error amplifier is an operational amplifier that converts the

voltage error signal to a voltage output. The voltage loop is

internally compensated with the 30pF and 600kΩ RC network

that can support most applications.

Detailed Description

The ISL85005 and ISL85005A combine a synchronous buck

controller with a pair of integrated switching MOSFETs. The buck

controller drives the internal high-side and low-side N-channel

MOSFETs to deliver load currents up to 5A. The buck regulator

can operate from an unregulated DC source, such as a battery,

with a voltage ranging from +4.5V to +18V. An internal 5V LDO

voltage regulator is used to bias the controller. The converter

output voltage is programmed using an external resistor divider

and generates regulated voltages down to 0.8V. These features

make the regulator suited for a wide range of applications.

PWM operation is initialized by the clock from the oscillator. The

upper MOSFET is turned on at the beginning of a cycle and the

current in the MOSFET starts to ramp up. When the sum of the

current amplifier CSA signal and the slope compensation

reaches the control reference of the current loop, the PWM

comparator sends a signal to the logic to turn off the upper

MOSFET and turn on the lower MOSFET. The lower MOSFET stays

on until the end of the cycle. Figure 42 shows the typical

operating waveforms during Continuous Conduction Mode (CCM)

operation. The dotted lines illustrate the sum of the

The controller uses a current mode loop, which simplifies the

loop compensation and permits fixed frequency operation over a

wide range of input and output voltages. The internal feedback

loop compensation option allows for a lower number of external

components. The regulator switches at a default of 500kHz, or it

can be synchronized from 300kHz to 2MHz on the ISL85005.

compensation ramp and the current-sense amplifier’s output.

V

EAMP

V

CSA

The buck regulator is equipped with a lossless current limit

scheme. The current in the output stage is derived from

temperature compensated measurements of the drain-to-source

voltage of the internal power MOSFETs. The current limit

threshold is internally set at 7.8A.

DUTY

CYCLE

I

L

Operation Initialization

V

To start operation, pull EN above 0.6V (typical). The power-on

reset circuitry prevents operation if the input voltage is below

4.2V. When the power-on reset requirement is met, the controller

soft-starts with a 2.3ms ramp on the ISL85005 or at a rate

determined by the value of a capacitor connected between SS

and AGND on the ISL85005A.

OUT

FIGURE 42. CCM OPERATION WAVEFORMS

Light-Load Operation

The ISL85005 monitors both the current in the low-side MOSFET

and the voltage of the FB node for regulation. Pulling the

SYNC/MODE pin low allows the ISL85005 to enter discontinuous

operation when lightly loaded by operating the low-side MOSFET

in Diode Emulation Mode (DEM). In this mode, reverse current is

not allowed in the inductor, and the output falls naturally to the

regulation voltage before the high-side MOSFET is switched for

the next cycle. The boundary is set by Equation 1:

FCCM Control Scheme

The regulator employs a current mode Pulse-Width

Modulation (PWM) control scheme for fast transient response

and pulse-by-pulse current limiting. The current loop consists of

the oscillator, the PWM comparator, current-sensing circuit, and

a slope compensation circuit. The gain of the current-sensing

circuit is typically 150mV/A and the slope compensation is

1.1V/T. The reference for the current loop is in turn provided by

the output of an Error Amplifier (EA), which compares the

feedback signal at the FB pin to the integrated 0.8V reference.

Therefore, the output voltage is regulated by using the error

amplifier to control the reference for the current loop.

V

1 – D

OUT

(EQ. 1)

----------------------------------

=

I

OUT

2Lf

SW

where D = duty cycle, f

SW

= switching frequency, L = inductor

= output voltage.

value, I

= output loading current, V

OUT

Synchronization Control

The ISL85005 can be synchronized from 300kHz to 2MHz by an

external signal applied to the SYNC pin. The rising edge on the

SYNC triggers the rising edge of the PHASE pulse. Make sure that

the on-time of the SYNC pulse is greater than 100ns. Although

the maximum synchronized frequency can be as high as 2MHz,

the ISL85005 is a current mode regulator that requires a

minimum of 140ns on-time to regulate properly. As an example,

the maximum recommended synchronized frequency will be

about 600kHz with 12V and 1V

.

IN OUT

FN8871 Rev.2.00

May 17, 2018

Page 15 of 23

ISL85005, ISL85005A

Enable, Soft-Start, and Disable

Forward Overcurrent Protection

Chip operation begins after V exceeds its rising POR trip point

The current flowing through the internal high-side MOSFET is

monitored during the on-time and compared to a typical 7.8A

overcurrent limit threshold. If the current exceeds the overcurrent

limit threshold, the high-side MOSFET is immediately turned off

and does not turn on again until the next switching cycle. The

current through the low-side switching MOSFET is sampled

during off time. If the low-side MOSFET current exceeds 8.6A at

the end of the low-side cycle, then the high-side MOSFET skips

the next cycle, allowing the inductor current to decay to a safe

level before resuming switching.

IN

(nominal 4.2V). If EN is held low externally, nothing happens until

this pin is released. When the voltage on the EN pin is above

0.6V, the LDO powers up and soft-start control begins. The

default soft-start time is 2.3ms.

On the ISL85005A, let SS float to select the internal soft-start

time with a default of 2.3ms. The soft-start time is extended by

connecting an external capacitor between SS and AGND. A 3.5µA

current source charges up the capacitor. The soft-start capacitor

is charged until the voltage on the SS pin reaches a 2.0V clamp

level. However, the output voltage reaches its regulation value

when the voltage on the SS pin reaches approximately 0.9V. The

capacitor, along with an internal 3.5µA current source, sets the

Reverse Overcurrent Protection

Similar to the overcurrent, the negative current protection is

enabled by monitoring the current across the low-side MOSFET,

as shown in Figure 41 on page 14. When the inductor current

reaches -3.3A, the synchronous rectifier is turned off. This limits

the ability of the regulator to actively pull down the output

voltage and prevents large reverse currents that may fall outside

the range of the high-side current-sense amplifier.

soft-start interval of the converter, t , according to Equation 2:

SS

(EQ. 2)

C

nF = 3.5  t mS – 1.6nF

SS

Output Voltage Selection

The regulator output voltage is programmed using an external

resistor divider that scales the feedback relative to the internal

reference voltage. The scaled voltage is fed back to the inverting

input of the error amplifier (see Figure 43).

Output Overvoltage Protection

The output overvoltage protection is triggered when the output

voltage exceeds 115% of the nominal voltage setting point. In

this condition, high-side and low-side MOSFETs are turned off

until the output drops to within the regulation band. When the

output is in regulation, the controller restarts under internal SS

control.

The output voltage programming resistor, R , depends on the

2

value chosen for the feedback resistor, R , and the desired

1

regulator output voltage, V

OUT

(see Equation 2). The R value

1

determines the gain of the feedback loop. See “Loop

Compensation Design” on page 19 for more details. The value for

the feedback resistor is typically between 10kΩ and 600kΩ.

Input Overvoltage Protection

R

 0.8V

The input overvoltage protection system prevents operation of

the switching regulator when the input voltage is higher than

20V. The high-side and low-side MOSFETs are turned off and the

converter restarts under internal SS control when the input

voltage returns to normal.

1

----------------------------------

R

=

(EQ. 3)

2

V

– 0.8V

OUT

If the output voltage desired is 0.8V, then R is left unpopulated.

R is still required to set the low frequency pole of the modulator

2

1

compensation.

Thermal Overload Protection

V

OUT

Thermal overload protection limits the maximum die

temperature, and thus the total power dissipation in the

regulator. A sensor on the chip monitors the junction

temperature. A signal is sent to the fault monitor circuits

R

1

-

+

EA

2

whenever the junction temperature (T ) exceeds +165°C, and

J

this causes the switching regulator and LDO to shut down.

0.8V

REFERENCE

The switching regulator turns on again and soft-starts after the

IC’s junction temperature cools by 10°C. For continuous

operation, do not exceed the +125°C junction temperature

rating.

FIGURE 43. EXTERNAL RESISTOR DIVIDER

Power Derating Characteristics

To prevent the regulator from exceeding the maximum junction

temperature, some thermal analysis is required. The

temperature rise is given by Equation 4:

Protection Features

The regulator limits current in all on-chip power devices.

Overcurrent limits are applied to the two output switching

MOSFETs as well as to the LDO linear regulator that feeds VDD.

Input and output overvoltage protection circuitry on the switching

regulator provides a second layer of protection.

(EQ. 4)

T

= PD



JA

RISE

where PD is the power dissipated by the regulator and  is the

JA

thermal resistance from the junction of the die to the ambient

FN8871 Rev.2.00

May 17, 2018

Page 16 of 23

ISL85005, ISL85005A

temperature. The junction temperature, T , is given by

J

Equation 5:

the manufacturer of the load on specific decoupling

requirements.

(EQ. 5)

The shape of the output voltage waveform during a load transient

that represents the worst case loading conditions ultimately

determines the number of output capacitors and their type.

When this load transient is applied to the converter, most of the

energy required by the load is initially delivered from the output

capacitors. This is due to the finite amount of time required for

the inductor current to slew up to the level of the output current

required by the load. This phenomenon results in a temporary dip

in the output voltage. At the very edge of the transient, the

Equivalent Series Inductance (ESL) of each capacitor induces a

spike that adds on top of the existing voltage drop due to the

ESR.

T

= T + T



RISE

J

A

where T is the ambient temperature. The DFN package’s  is

A

JA

49 (°C/W).

The actual junction temperature should not exceed the absolute

maximum junction temperature of +125°C when considering

the thermal design.

T

Application Guidelines

Boot Undervoltage Detection

After the initial spike, attributable to the ESR and ESL of the

capacitors, the output voltage experiences sag. This sag is a

direct consequence of the amount of capacitance on the output.

The internal driver of the high-side FET is equipped with a boot

Undervoltage (UV) detection circuit. If the voltage difference

between BOOT and PHASE falls below 2.5V, the UV detection

circuit allows the low-side MOSFET on for 300ns to recharge the

bootstrap capacitor.

During the removal of the same output load, the energy stored in

the inductor is dumped into the output capacitors. This energy

dumping creates a temporary hump in the output voltage. This

hump, as with the sag, can be attributed to the total amount of

capacitance on the output. Figure 45 shows a typical response to

a load transient.

Although the ISL85005 and ISL85005A include an internal

bootstrap diode, efficiency can be improved by using an external

supply voltage and bootstrap Schottky diode. The external diode

is then sourced from a fixed external 5V supply or from the

output of the switching regulator if this is at 5V. The bootstrap

diode can be a low cost type, such as the BAT54.

PHASE

V

HUMP

C

0.1 F

4

V

OUT

µ

BOOT

ISL85005

ISL85005A

V

ESR

V

BAT54

5V

SAG

ESL

or 5V SOURCE

OUT

I

FIGURE 44. EXTERNAL BOOTSTRAP DIODE

OUT

Switching Regulator Output Capacitor

Selection

I

tran

An output capacitor is required to filter the inductor current and

supply the load transient current. The filtering requirements are a

function of the switching frequency, the ripple current, and the

required output ripple. The load transient requirements are a

function of the slew rate (di/dt) and the magnitude of the

transient load current. These requirements are generally met

with a mix of capacitor types and careful layout.

FIGURE 45. TYPICAL TRANSIENT RESPONSE

The amplitudes of the different types of voltage excursions can

be approximated using Equations 6, 7, 8, and 9.

High-frequency ceramic capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors. The

bulk filter capacitor values are generally determined by the

Equivalent Series Resistance (ESR) and voltage rating

V

= ESR  I

tran

(EQ. 6)

(EQ. 7)

(EQ. 8)

ESR

ESL

SAG

dI

tran

---------------

dt

= ESL 

requirements rather than actual capacitance requirements.

Place he high-frequency decoupling capacitors as close to the

power pins of the load as physically possible. Be careful not to

add inductance in the circuit board wiring that could cancel the

usefulness of these low inductance components. Consult with

2

L

 I

OUT tran

----------------------------------------------------------

=

C

 V – V



OUT

IN

FN8871 Rev.2.00

May 17, 2018

Page 17 of 23

ISL85005, ISL85005A

inductor current from an initial current value to the transient

current level. During this interval, the difference between the

inductor current and the transient current level must be supplied

by the output capacitor. Minimizing the response time can

minimize the output capacitance required.

2

L

 I

OUT tran

(EQ. 9)

-------------------------------------

=

V

HUMP

C

 V

OUT

where I

= Output load current transient and C

= Total

OUT

tran

output capacitance.

The response time to a transient is different for the application of

load and the removal of load. Equations 14 and 15 give the

approximate response time interval for application and removal

of a transient load:

In a typical converter design, the ESR of the output capacitor

bank dominates the transient response. The ESR and the ESL are

typically the major contributing factors in determining the output

capacitance. The number of output capacitors can be

determined by using Equation 10, which relates the ESR and ESL

of the capacitors to the transient load step and the voltage limit

L x I

tran

(EQ. 14)

t

=

RISE

V

- V

IN OUT

(V ):

O

L x I

tran

(EQ. 15)

t

=

ESL  I

FALL

tran

V

-----------------------------

+ ESR  I

OUT

tran

dt

(EQ. 10)

-------------------------------------------------------------------

Number of Caps =

V

where I

is the transient load current step, t

is the

O

tran

RISE

FALL

response time to the application of load, and t

If V

SAG

or V are too large for the output voltage limits,

HUMP

response time to the removal of load. The worst case response

time can be either at the application or removal of load. Check

both of these equations at the minimum and maximum output

levels for the worst case response time.

then the amount of capacitance may need to be increased. In

this situation, a trade-off between output inductance and output

capacitance may be necessary.

The ESL of the capacitors, which is an important parameter in

the above equations, is not usually listed in the specification.

Practically, it can be approximated using Equation 11 if an

Impedance vs Frequency curve is given for a specific capacitor:

Input Capacitor Selection

Use a mix of input bypass capacitors to control the input voltage

ripple. Use ceramic capacitors for high frequency decoupling and

bulk capacitors to supply the current needed each time the

switching MOSFET turns on. Place the ceramic capacitors

physically close to the MOSFET VIN pins (switching MOSFET

drain) and PGND.

1

(EQ. 11)

----------------------------------------

ESL =

2

C2    f



res

where f is the resonant frequency in which the lowest

res

The important parameters for the bulk input capacitance are the

voltage rating and the RMS current rating. For reliable operation,

select bulk capacitors with voltage and current ratings above the

maximum input voltage and largest RMS current required by the

circuit. Their voltage rating should be at least 1.25 times greater

than the maximum input voltage, while a voltage rating of

1.5 times is a conservative guideline. For most cases, the RMS

current rating requirement for the input capacitor of a buck

regulator is approximately half the DC load current.

impedance is achieved.

The ESL of the capacitors becomes a concern when designing

circuits that supply power to loads with high rates of change in

the current.

Output Inductor Selection

Select the output inductor to meet the output voltage ripple

requirements and minimize the converter’s response time to the

load transient. The inductor value determines the converter’s

ripple current and the output ripple voltage is a function of the

ripple current. The ripple voltage and current are approximated

by Equations 12 and 13:

The maximum RMS current required by the regulator may be

more closely approximated through Equation 16:

2

V_OUT

-------------

V_IN

V_IN– V_OUTV_OUT

2

1

12



 

 

------ ---------------------------- -------------

I_RMS

=

 I_OUT

+





L  f_s

V_IN

MAX

V – V



V

OUT

IN

OUT

------------------------------------ ---------------

I =



(EQ. 12)

Fs  L

V

(EQ. 16)

IN

For a through-hole design, several electrolytic capacitors may be

needed, especially at temperatures less than -25°C. The

electrolytic's ESR can increase ten times higher than at room

temperature and cause input line oscillation. In this case, use a

more thermally stable capacitor such as X7R ceramic. For

surface mount designs, solid tantalum capacitors can be used,

but caution must be exercised with regard to the capacitor surge

current rating. Some capacitor series available from reputable

manufacturers are surge current tested.

V

= I x ESR

(EQ. 13)

OUT

Increasing the inductance value reduces the ripple current and

voltage. However, the large inductance values reduce the

converter’s response time to a load transient. Furthermore, the

ripple current is an important signed-in current mode control.

Therefore, set the ripple inductor current to approximately 30%

of the maximum output current for optimized performance.

One of the parameters limiting the converter’s response to a load

transient is the time required to change the inductor current.

Given a sufficiently fast control loop design, the regulator will

provide either 0% or 100% duty cycle in response to a load

transient. The response time is the time required to slew the

FN8871 Rev.2.00

May 17, 2018

Page 18 of 23

ISL85005, ISL85005A

Loop Compensation Design

Compensator Design Goal

When COMP is not connected to GND, the COMP pin is active for

external loop compensation. In an application with extreme

temperatures, such as less than -10°C or greater than +85°C,

use external compensation. The regulator uses constant

frequency peak current mode control architecture to achieve a

fast loop transient response. An accurate current sensing pilot

device in parallel with the upper MOSFET is used for peak current

control signal and overcurrent protection. The inductor is not

considered a state variable because its peak current is constant,

and the system becomes a single order system. It is much easier

to design a Type II compensator to stabilize the loop than to

implement voltage mode control. Peak current mode control has

an inherent input voltage feed-forward function to achieve good

line regulation. Figure 46 shows the small signal model of the

synchronous buck regulator.

High DC Gain

Choose Loop bandwidth f of approximately 50kHz or 1/10 of

the switching frequency.

c

• Gain margin: >10dB

• Phase margin: >40°

The compensator design procedure is as follows:

The loop gain at crossover frequency of f has a unity gain.

Therefore, the compensator resistance, R , is determined by

Equation 18.

c

6

(EQ. 18)

R

= 2f C R R  f  C R

c o t 1 c o 1

6

Note that C is the actual capacitance seen by the regulator,

o

which may include ceramic high frequency decoupling and bulk

output capacitors. Ceramic may have to be derated by

^

R

^

L

LP

i

P

i

L

v

o

in

^

V

^

IN

^

d

IN

1:D

approximately 40% depending on dielectric, voltage stress, and

I d

V

L

Rc

Co

temperature. Compensator capacitor C is then given by

Equations 19 and 20.

+

R

T

6

Ro

R C

V C

o o

10I R

o 6

o

(EQ. 19)

(EQ. 20)

-------------- -------------------

C

=

6

T (S)

i

10R

6

^

d

K

Fm

R C

1

c

o

C = max[--------------,---------------]

7

10R f R

s 6

T (S)

+

v

6

He(S)

^

Vcomp

^{An optional zero can boost the phase margin.}_CZ2is a zero due

to R and C .

-Av(S)

1

3

FIGURE 46. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK

REGULATOR

^{Put compensator zero,}_CZ2from 1/2f to f .

c

1

(EQ. 21)

-------------------

C =

3

2f R

c 1

C

V

7

O

R

6

For internal compensation mode, R is equal 600kΩ and C is

C

6

R

C

3

1

30pF. Equation 18 can be rearranged to solve for R .

1

-

V

COMP

Layout Considerations

V

FB

R

The layout is very important in a high frequency switching

+

2

V

REF

converter design. With power devices switching efficiently at

500kHz, the resulting current transitions from one device to

another cause voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage spikes

can degrade efficiency, radiate noise into the circuit, and lead to

device overvoltage stress. Careful component layout and Printed

Circuit Board (PCB) design minimizes these voltage spikes.

FIGURE 47. TYPE II COMPENSATOR

Figure 47 shows the Type II compensator. Its transfer function is

expressed, as shown in Equation 17:

S





 

 





------------

1 +

A snubber can be added to reduce voltage spikes. The snubber

consists of a resistor and a capacitor that are connected in series

from the PHASE pin to PGND pin. The snubber damps the voltage

ringing caused by parasitic inductance and capacitance. Another

option to reduce voltage spikes is to add a boot resistor in series

with the boot capacitor, which slows down the turn-on of the

high-side FET and allows more time for the parasitic network to

discharge.

ˆ



v

1

comp

cz1

cz2

(EQ. 17)

---------------- ------------------------------------- --------------------------------------------------------------

A S=

=

v

ˆ

C + C   R

S

v



 



6

7

1

o

-------------

S 1 +

1 +



 





cp1

cp2

where:

C

+ C

7

1

6

--------------

----------------------

 



=

,



=

 

=

 350kHz

cp2

cz1

cz2

cp1

R C

R C C

6 6 7

6

1

3

As an example, consider the turn-off transition of the upper

MOSFET. Before turn-off, the MOSFET is carrying the full load

FN8871 Rev.2.00

May 17, 2018

Page 19 of 23

ISL85005, ISL85005A

current. During turn-off, current stops flowing in the MOSFET and

is picked up by the internal body diode. Any parasitic inductance

in the switched current path generates a large voltage spike

during the switching interval. Careful component selection, tight

layout of the critical components, and short, wide traces

minimize the magnitude of voltage spikes.

V

IN

V

IN

C

IN

ISL85005

ISL85005A

L

V

OUT1

PHASE

There are two sets of critical components in the regulator

switching converter. The switching components are the most

critical because they switch large amounts of energy and

therefore tend to generate large amounts of noise. Next are the

small signal components, which connect to sensitive nodes or

supply critical bypass current and signal coupling.

C

OUT1

PGND

COMP

C

6

C

7

R

6

A multi-layer PCB is recommended. Figure 48 shows the

connections of the critical components in the converter. Note

R

1

FB

that capacitors C and C

could each represent numerous

IN OUT

R

PGND PAD

physical capacitors. Dedicate one solid layer, usually a middle

layer of the PCB, for a ground plane and make all critical

component ground connections with vias to this layer. Dedicate

another solid layer as a power plane and break this plane into

smaller islands of common voltage levels. Keep the metal runs

from the PHASE terminals to the output inductor short. The

power plane should support the input power and output power

nodes. Use copper-filled polygons on the top and bottom circuit

layers for the phase nodes. Use the remaining printed circuit

layers for small signal wiring.

2

C

3

KEY

ISLAND ON CIRCUIT AND/OR POWER PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 48. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

The critical small signal components include any bypass

capacitors, feedback components, and compensation

components. Place the compensation components close to the

FB and COMP pins. Place the feedback resistors as close as

possible to the FB pin with vias tied straight to the ground plane.

Figure 49 shows a recommended layout example.

To dissipate heat generated by the internal LDO and MOSFETs,

the ground pad should be connected to the internal ground plane

through at least five vias. This allows the heat to move away from

the IC and ties the pad to the ground plane through a low

impedance path.

Place the switching components close to the regulator first.

Minimize the length of the connections between the input

VIN

capacitors, C , and the power switches by placing them nearby.

IN

PHASE

L1

Position both the ceramic and bulk input capacitors as close to

the upper MOSFET drain as possible.

CIN

GND

COUT

FIGURE 49. RECOMMEND LAYOUT (TOP LAYER)

FN8871 Rev.2.00

May 17, 2018

Page 20 of 23

ISL85005, ISL85005A

Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not

warranted. Please visit our website to make sure you have the latest revision.

DATE

REVISION

FN8871.2

CHANGE

May 17, 2018

Updated Pin Configuration labels from “4X3” to “3X4”.

Updated Ordering information by adding tape and reel parts to table, adding tape and reel quantity column,

updating Note 1, adding demonstration board parts.

Removed About Intersil section and updated disclaimer.

Aug 17, 2017

FN8871.1

FN8871.0

In the Component Selection Table, for C , changed “15pF” to “12pF” for all voltages.

1

Updated Figures 27-34.

Updated Figure 39.

In Output Voltage Selection on page 16, changed the maximum value of the feedback resistor from “400kΩ” to

“600kΩ”.

In Layout Considerations on page 19, added the second paragraph, which is a description of a snubber.

Updated Figure 49.

Nov 28, 2016

Initial release

FN8871 Rev.2.00

May 17, 2018

Page 21 of 23

ISL85005, ISL85005A

For the most recent package outline drawing, see L12.3x4.

Package Outline Drawing

L12.3x4

12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 3/15

6

3.00

A

PIN #1

SEE DETAIL "X"

INDEX AREA

B

6

PIN 1

INDEX AREA

1

12

3.30 ±0.10

2X 2.50

6

(4X)

0.10

7

10X 0.50

12X 0.25 ±0.05

0.10M C A B

TOP VIEW

0.90 MAX

1.70

±0.10

4

C

12X 0.40 ± 0.05

SIDE VIEW

BOTTOM VIEW

(12X 0.60)

( 12 X 0.25)

( 3.30 )

( 2.50)

0.10 C

(10x 0.50)

C

0 . 203 REF

SEATING PLANE

0.08 C

(1.70)

0 . 00 MIN.

0 . 05 MAX.

( 2.80 )

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature and may be

located on any of the 4 sides (or ends).

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Reference document JEDEC MO-229.

FN8871 Rev.2.00

May 17, 2018

Page 22 of 23

Notice

1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for

the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by

you or third parties arising from the use of these circuits, software, or information.

2. Renesas Electronics hereby expressly disclaims any warranties against and liability for infringement or any other claims involving patents, copyrights, or other intellectual property rights of third parties, by or

arising from the use of Renesas Electronics products or technical information described in this document, including but not limited to, the product data, drawings, charts, programs, algorithms, and application

examples.

3. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4. You shall not alter, modify, copy, or reverse engineer any Renesas Electronics product, whether in whole or in part. Renesas Electronics disclaims any and all liability for any losses or damages incurred by

you or third parties arising from such alteration, modification, copying or reverse engineering.

5. Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The intended applications for each Renesas Electronics product depends on the

product’s quality grade, as indicated below.

"Standard":

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic

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Unless expressly designated as a high reliability product or a product for harsh environments in a Renesas Electronics data sheet or other Renesas Electronics document, Renesas Electronics products are

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liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or


型号：	ISL85003A
厂家：	RENESAS TECHNOLOGY CORP
描述：	4.5V to 18V Input, 5A High Efficiency Synchronous Buck Regulator
文件：	总23页 (文件大小：1254K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL85003A [RENESAS]

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