ISL85012FRZ-T7A_技术文档

DATASHEET

ISL85012

FN8677

Rev.2.00

Mar 17, 2017

12A, 3.8V to 18V Input, Synchronous Buck Regulator

The ISL85012 is a highly efficient, monolithic, synchronous

buck regulator that can deliver 12A of continuous output

current from a 3.8V to 18V input supply. The device uses

current mode control architecture with a fast transient

response and excellent loop stability.

Features

• Power input voltage range variable 3.8V to 18V

• PWM output voltage adjustable from 0.6V

• Up to 12A output load

The ISL85012 integrates very low ON-resistance high-side and

low-side FETs to maximize efficiency and minimize external

component count. The minimum BOM and easy layout

footprint are extremely friendly to space constraint systems.

• Prebias start-up, fixed 3ms soft-start

• Selectable f

of 300kHz, 600kHz, and external

SW

synchronization up to 1MHz

• Peak current mode control

- DCM/CCM

The operation frequency of this device can be set using the

FREQ pin: 600kHz (FREQ = float) and 300kHz (FREQ = GND).

The device can also be synchronized to an external clock up to

1MHz.

- Thermally compensated current limit

- Internal/external compensation

Both high-side and low-side MOSFET current limit along with

reverse current limit, fully protects the regulator in an

overcurrent event. Selectable OCP schemes can fit various

applications. Other protections, such as input/output

overvoltage and over-temperature, are also integrated into the

device which give required system level safety in the event of

fault conditions.

• Open-drain, PG window comparator

• Output overvoltage and thermal protection

• Input overvoltage protection

• Integrated boot diode with undervoltage detection

• Selectable OCP schemes

- Hiccup OCP

The ISL85012 is offered in a space saving 15 Ld 3.5mmx3.5mm

Pb-free TQFN package with great thermal performance and

0.8mm maximum height.

- Latch-off

• Compact size 3.5mmx3.5mm

Applications

Related Literature

• For a full list of related documents please visit our web page

- ISL85012 product page

• Servers and cloud infrastructure POLs

• IPCs, factory automation, PLCs

• Telecom and networking systems

• Storage systems

• Test measurement

R₁

200k

R₂

100k

C₅

C₁

R₃

200

1µF

4.7pF

15

14

13

12

11

10

FB

VIN

EN

DNC DNC COMP

VIN

L1

0.68µH

PVIN

9

8

3x22µF

V_OUT

4.5-18V

GND

PHASE

C_in

C_OUT

3x100µF

CERAMIC

1.8V/12A

GND

7

C₄

100nF

SYNC MODE FREQ PG

VDD BOOT

1

2

3

4

5

6

C₃

2.2µF

FIGURE 1. TYPICAL APPLICATION SCHEMATIC FOR INTERNAL COMPENSATION

FN8677 Rev.2.00

Mar 17, 2017

Page 1 of 19

ISL85012

Typical Application Schematic

330pF

C₂

R₁

20k



80.6k

R₃

C₅

1µF

C₁

47pF

15

14

13

12

DNC COMP

11

10

R₂

10k

FB

VIN

EN

DNC

VIN

L1

PVIN

9

0.68µH

V_OUT

4.5-18V

GND

PHASE

8

3x22µF

C_in

3x100µF

CERAMIC

C_OUT

1.8V/12A

GND

7

C₄

100nF

SYNC MODE FREQ

PG

4

VDD BOOT

1

2

3

5

6

C₃

2.2µF

FIGURE 2. TYPICAL APPLICATION SCHEMATIC FOR EXTERNAL COMPENSATION

TABLE 1. DESIGN TABLE FOR DIFFERENT OUTPUT VOLTAGE

V

(V)

0.9

1

1.2

4.5 to 18

300

1.5

4.5 to 18

600

1.8

4.5 to 18

600

2.5

4.5 to 18

600

3.3

5

6 to 18

600

OUT

(V)

V

4.5 to 18

300

4.5 to 18

300

4.5 to 18

600

IN

FREQ (kHz)

Compensation

Internal

3x22

Internal

3x22

Internal

3x22

Internal

3x22

4x100

0.68

Internal

3x22

3x100

0.68

Internal

3x22

4x47

1

Internal

3x22

4x47

1

Internal

3x22

4x47

1.5

C

(µF)

in

C

2x560 + 4x100 2x330 + 3x100 2x330 + 3x100

out

L

(µH)

(kΩ)

(pF)

0.68

100

200

DNP

0.68

100

150

DNP

1

R

147

DNP

150

200

301

365

80.6

3.3

365

1

2

100

95.3

4.7

49.9

3.3

C

10

4.7

1

NOTES:

1. The design table is referencing the schematic shown in Figure 1.

2. Ceramic capacitors are selected for 22µF and 100µF in the table.

3. 560µF (14mΩ) and 330µF (10mΩ) are selected low ESR conductive polymer aluminum solid capacitors.

4. Inductor 7443340068 (0.68µH), 7443340100 (1µH) and 7443340150 (1.5µH) from Wurth Electronics are selected for the above applications.

5. Recommend to keep the inductor peak-to-peak current less than 5A.

TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS

INTERNAL/EXTERNAL

COMPENSATION

EXTERNAL FREQUENCY

SYNC

PROGRAMMABLE

SOFT-START

SWITCHING

FREQUENCY (kHz)

CURRENT

RATING (A)

PART NUMBER

ISL85003

Yes

No

Yes

No

500

3

ISL85003A

ISL85005

500

Yes

No

500

5

ISL85005A

ISL85012

Yes

No

5

Yes

300 or 600 selectable

12

FN8677 Rev.2.00

Mar 17, 2017

Page 2 of 19

ISL85012

Ordering Information

PART NUMBER

(Notes 6, 7, 8)

TEMP. RANGE

(°C)

TAPE AND REEL

(UNITS)

PACKAGE

(RoHS COMPLIANT)

PKG.

DWG. #

PART MARKING

5012

ISL85012FRZ-T

-40 to +125

6k

15 Ld 3.5mmx3.5mm TQFN

L15.3.5x3.5

ISL85012FRZ-T7A

ISL85012EVAL1Z

NOTES:

5012

250

Evaluation Board

6. Refer to TB347 for details on reel specifications.

7. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

8. For Moisture Sensitivity Level (MSL), see product information page for ISL85012. For more information on MSL, see tech brief TB363.

Functional Block Diagram

PG

NC

FREQ

SYNC

EN

VDD

DELAY

POR

LDO

VIN

POWER-ON RESET MONITOR

OSCILLATOR

THERMAL

SHUT

OVP

MODE

DOWN

PVIN

UVP

CSA

FAULT

MONITOR

CIRCUITS

20V

HIGH SIDE

OCP

BOOT

SCHEME

SETTING

BOOT

UVP

NC

EA

GATE DRIVER

CONTROL LOGIC

INTERNAL SS

PHASE

0.6V

REF

VDD

FB

SLOPE

COMP

800/1200k

FREQ

CSA

30pF

ZERO CROSS

DETECTOR

DCM

COMP

NEGATIVE

GND

CURRENT LIMIT

AND FORWARD

CURRENT LIMIT

FIGURE 3. FUNCTIONAL BLOCK DIAGRAM

FN8677 Rev.2.00

Mar 17, 2017

Page 3 of 19

ISL85012

Pin Configuration

ISL85012

(15 LD 3.5mmx3.5mm TQFN)

TOP VIEW

15

14

13

12

11

10

VIN

EN

DNC DNC COMP FB

PVIN

9

PHASE

8

GND

7

SYNC MODE FREQ PG

VDD BOOT

1

2

3

4

5

6

Pin Descriptions

PIN#

1

NAME

DESCRIPTION

SYNC Synchronization and mode selection pin. Connect to VDD or float for PWM mode. Connect to GND for DCM mode in the light-load

condition. Connect to an external clock signal for synchronization with the rising edge trigger.

2

3

4

MODE OCP scheme select pin. Short it to GND for latch-off mode. Float it for hiccup mode.

FREQ Default frequency selection pin. Short it to GND for 300kHz. Float it for 600kHz.

PG

Power-good, open-drain output. It requires a pull-up resistor (10kΩ to 100kΩ) between PG and VDD or a voltage not exceeding

5.5V. PG pulls high when FB is in the range of ~90% to ~116% of its intended value.

5

6

VDD

Low dropout linear regulator decoupling pin. The VDD is the internally generated 5V supply voltage and is derived from VIN. The

VDD is used to power all the internal core analog control blocks and drivers. Connect a 2.2µF capacitor from VDD to the board

ground plane. If the V is between 3V to 5.5V, then connect VDD directly to VIN to improve efficiency.

IN

BOOT BOOT is the floating bootstrap supply pin for the high-side power MOSFET gate driver. A bootstrap capacitor, usually 0.1µF, is

required from BOOT to PHASE.

7

8

GND

Reference of the power circuit. For thermal relief, this pin should be connected to the ground plane by vias.

PHASE Switch node connection to the internal power MOSFETs (source of upper FET and drain of lower FET) and the external output

inductor.

9

PVIN Input supply for the PWM regulator power stage. A decoupling capacitor, typically ceramic, is required to be connected between

this pin and GND.

10

11

FB

Inverting input to the voltage loop error amplifier. The output voltage is set by an external resistor divider connected to FB.

COMP Output of the error amplifier. Compensation network between COMP and FB to configure external compensation. Place a 200Ω

resistor between COMP and GND for internal compensation, which is used to meet most applications.

12, 13

14

DNC

EN

Do Not Connect to pin. Float the pins in the design.

Enable input. The regulator is held off when this pin is pulled to ground. The device is enabled when the voltage on this pin rises

to about 0.6V.

15

VIN

Input supply for the control circuit and the source for the internal linear regulator that provides bias for the IC.

A decoupling capacitor, typically 1µF ceramic, is required connected between VIN and GND.

FN8677 Rev.2.00

Mar 17, 2017

Page 4 of 19

ISL85012

Absolute Maximum Ratings

Thermal Information

VIN, EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V

PVIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V

PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7V to +24V (DC)

PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +24V (40ns)

BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V

VDD, COMP, SYNC, PG, FB, MODE, FREQ, SS, IOCP to GND . . . -0.3V to +7V

ESD Rating

Human Body Model (Tested per JS-001-2014). . . . . . . . . . . . . . . . .2.5kV

Charged Device Model (Tested per JS-002-2014) . . . . . . . . . . . . . . . 1kV

Latch-Up (Tested per JESD78E; Class 2, Level A, +125°C). . . . . . .100mA

Thermal Resistance

TQFN Package (Notes 9, 10). . . . . . . . . . . .

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB49



(°C/W)

33



(°C/W)

1.2

JA

JC

Recommended Operating Conditions

VIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 18V

PVIN Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V to 18V

Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 12A

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

9.  is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features, except with

JA

3 vias under the GND EPAD strip contacting the GND plane, and two vias under the VIN EPAD strip contacting the VIN plane. See Tech Brief TB379.

10. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and

the typical specification are measured at the following conditions: T = -40°C to +125°C, V = 4.5V to 18V, unless otherwise noted. Typical values are at

J

IN

T

= +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C.

A

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 11) TYP (Note 11) UNIT

SUPPLY VOLTAGE

PVIN Voltage Range

3.8

4.5

18

5

V

PVIN

VIN

V

Voltage Range

IN

Quiescent Supply Current

Shutdown Supply Current

I

EN = 2V, FB = 0.64V

EN = GND

3

8

mA

µA

Q

I

13

SD

POWER-ON RESET

PVIN POR Threshold

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Hysteresis

2.9

4.49

0.7

V

1.9

V

POR Threshold

V

IN

3.4

0.5

V

EN POR Threshold

0.6

V

100

mV

V

POR Threshold

Rising edge

Falling edge

3.6

DD

2.4

4.3

V

INTERNAL VDD LDO

V

Output Voltage Regulation Range

Output Current Limit

V

= 6V to 18V, I

VDD

= 0mA to 30mA

5.0

80

5.5

V

mA

V

DD

IN

LDO Dropout Voltage

OSCILLATOR

V

= 5V, I

VDD

= 30mA

0.65

Nominal Switching Frequency

Minimum On-Time

f

FREQ = float

FREQ = GND

540

250

600

280

90

660

310

150

170

1000

0.5

kHz

ns

SW1

SW2

t

I

= 0mA

ON

OUT

Minimum Off-Time

t

140

ns

OFF

Synchronization Range

SYNC Logic Input Low

SYNC Logic Input High

100

1.2

kHz

V

FN8677 Rev.2.00

Mar 17, 2017

Page 5 of 19

ISL85012

Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and

the typical specification are measured at the following conditions: T = -40°C to +125°C, V = 4.5V to 18V, unless otherwise noted. Typical values are at

J

IN

T

= +25°C. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)

A

MIN

MAX

PARAMETER

SYMBOL

TEST CONDITIONS

(Note 11) TYP (Note 11) UNIT

ERROR AMPLIFIER

FB Regulation Voltage

FB Leakage Current

Open Loop Bandwidth

Gain

V

0.588

0.600

0.612

10

V

nA

FB

V

= 0.6V

FB

BW

5.5

70

MHz

dB

Output Drive

High-side clamp = 1.5V, low-side clamp = 0.4V

Tested at 600kHz

±100

0.055

470

µA

Current-Sense Gain

Slope Compensation

SOFT-START

RT

Se

0.050

1.9

0.063

4.7

Ω

mV/µs

Default Soft-Start Time

PG

3

ms

Output Low Voltage

PG Pin Leakage Current

PG Lower Threshold

PG Upper Threshold

PG Thresholds Hysteresis

Delay Time

I

= 5mA

0.3

0.01

87

V

µA

%

PG

Percentage of output regulation

SYNC is short-to-GND

Rising edge

81

92

110

116

3

121

%

1.5

23

ms

µs

Falling edge

FAULT PROTECTION

V

/PVIN Overvoltage Lockout

IN

Rising edge

19

18

20.5

19.5

1

22

21

V

Falling edge

Hysteresis

V

A

Positive Overcurrent Protection Threshold

I

High-side OCP

15.5

-10.8

110

18

19.5

-5.5

121

POCP

Low-side OCP

21

A

Negative Overcurrent Protection Threshold

Hiccup Blanking Time

I

Current forced into PHASE node, high-side MOSFET is off

-7.5

150

116

160

10

NOCP

ms

%

FB Overvoltage Threshold

Thermal Shutdown Temperature

T

Rising threshold

Hysteresis

°C

SD

T

HYS

POWER MOSFET

High-Side

R

IPHASE = 900mA

EN = GND

15

7

mΩ

kΩ

HDS

Low-Side

R

LDS

PHASE Pull-Down Resistor

NOTE:

22.5

11. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN8677 Rev.2.00

Mar 17, 2017

Page 6 of 19

ISL85012

Typical Performance Curves Circuit of Figure 2. Design table on page 2 shows the components value for different

output voltages. Plots are captured from ISL85012EVAL1Z boards. V = 12V, V

= 1.8V, FREQ = 600kHz, CCM, T = -40°C to +125°C unless otherwise

IN

OUT J

noted. Typical values are at T = +25°C.

A

100

90

80

70

60

50

40

100

90

80

70

60

50

40

30

20

5V

3.3V

1.5V

1V

1.2V

30

20

1.8V

0.9V

0

2

4

6

8

10

12

0

2

4

6

8

10

12

OUTPUT CURRENT (A)

FIGURE 4. EFFICIENCY vs LOAD (V = 12V, CCM, 600kHz)

IN

FIGURE 5. EFFICIENCY vs LOAD (V = 12V, CCM, 300kHz)

IN

100

90

80

70

60

50

40

30

20

90

80

70

60

50

40

30

20

3.3V

1.5V

1.8V

1V

0.9V

1.2V

0

2

4

6

8

10

12

0

2

4

6

8

10

OUTPUT CURRENT (A)

FIGURE 6. EFFICIENCY vs LOAD (V = 5V, CCM, 600kHz)

IN

FIGURE 7. EFFICIENCY vs LOAD (V = 5V, CCM, 300kHz)

IN

1.010

1.009

1.008

1.007

1.006

1.005

1.004

1.003

1.002

1.816

1.814

1.812

1.810

1.808

1.806

1.804

1.802

1.800

1.001

1.798

1.8V

1.796

1V

1.000

0

2

4

6

8

10

12

0

2

4

6

8

10

OUTPUT CURRENT (A)

FIGURE 8. V

REGULATION vs LOAD (V = 12V, CCM, 600kHz)

IN

FIGURE 9. V

REGULATION vs LOAD (V = 12V, CCM, 300kHz)

OUT IN

OUT

FN8677 Rev.2.00

Mar 17, 2017

Page 7 of 19

ISL85012

Typical Performance Curves Circuit of Figure 2. Design table on page 2 shows the components value for different

output voltages. Plots are captured from ISL85012EVAL1Z boards. V = 12V, V

= 1.8V, FREQ = 600kHz, CCM, T = -40°C to +125°C unless otherwise

IN

OUT J

noted. Typical values are at T = +25°C. (Continued)

A

C2: PHASE, 10V/DIV

C1: V

, 1V/DIV

OUT

C1: V

, 1V/DIV

OUT

50ms/DIV

FIGURE 10. LATCH-OFF OCP (V = 12V, V

IN

= 1.8V, 600kHz, CCM)

FIGURE 11. HICCUP OCP (V = 12V, V

= 1.8V, 600kHz, CCM)

OUT

IN

C2: PHASE, 10V/DIV

C1: V

, 20mV/DIV

OUT

C1: V

, 20mV/DIV

OUT

1µs/DIV

10ms/DIV

FIGURE 12. OUTPUT VOLTAGE RIPPLE (V = 12V, V

IN

= 1.8V AT

FIGURE 13. OUTPUT VOLTAGE RIPPLE (V = 12V, V

= 1.8V AT 0A,

OUT

IN

12A, 600kHz, CCM)

600kHz, DCM)

C3: EN, 10V/DIV

C1: V

, 1V/DIV

C1: V

, 1V/DIV

OUT

C4: PGOOD, 2V/DIV

2ms/DIV

FIGURE 14. START-UP BY EN (V = 12V, V

IN

= 1.8V AT 12A,

FIGURE 15. START-UP BY EN (V = 12V, V

= 1.8V AT 0A, 600kHz,

OUT

IN

600kHz, CCM)

DCM)

FN8677 Rev.2.00

Mar 17, 2017

Page 8 of 19

ISL85012

Typical Performance Curves Circuit of Figure 2. Design table on page 2 shows the components value for different

output voltages. Plots are captured from ISL85012EVAL1Z boards. V = 12V, V

= 1.8V, FREQ = 600kHz, CCM, T = -40°C to +125°C unless otherwise

IN

OUT J

noted. Typical values are at T = +25°C. (Continued)

A

C3: EN, 10V/DIV

C1: V

, 1V/DIV

OUT

C1: V

, 1V/DIV

OUT

C4: PGOOD, 2V/DIV

1ms/DIV

50ms/DIV

FIGURE 16. SHUTDOWN BY EN (V = 12V, V

IN

= 1.8V AT 12A,

FIGURE 17. SHUTDOWN BY EN (V = 12V, V

= 1.8V AT 0A,

OUT

IN

600kHz, CCM)

600kHz, DCM)

Typical Characteristics

12

10

8

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

6

4

2

0

-40 -25 -10

5

20

35

50 65

80

95 110 125

-40 -25 -10

5

20 35 50

65 80 95 110 125

JUNCTION TEMPERATURE (°C)

FIGURE 18. V SHUTDOWN CURRENT vs TEMPERATURE

IN

FIGURE 19. V QUIESCENT CURRENT vs TEMPERATURE

IN

0.606

0.604

0.602

0.600

0.598

0.596

0.594

0.65

0.63

0.61

0.59

0.57

0.55

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

JUNCTION TEMPERATURE (°C)

FIGURE 20. FEEDBACK VOLTAGE vs TEMPERATURE

FIGURE 21. ENABLE THRESHOLD vs TEMPERATURE

FN8677 Rev.2.00

Mar 17, 2017

Page 9 of 19

ISL85012

Typical Characteristics (Continued)

4.130

4.125

4.120

4.115

4.110

4.105

4.100

3.72

3.71

3.70

3.69

3.68

3.67

3.66

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

JUNCTION TEMPERATURE (°C)

FIGURE 22. V POR (RISING) vs TEMPERATURE

IN

FIGURE 23. V POR (FALLING) vs TEMPERATURE

IN

700

680

660

640

620

600

580

560

540

520

500

400

380

360

340

320

300

280

260

240

220

200

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

JUNCTION TEMPERATURE (°C)

FIGURE 24. FREQUENCY (600kHz DEFAULT) vs TEMPERATURE

FIGURE 25. FREQUENCY (300kHz DEFAULT) vs TEMPERATURE

1.40

1.35

1.30

1.25

1.20

1.15

1.10

25

20

15

10

5

0

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20

35

50

65

80

95 110 125

JUNCTION TEMPERATURE (°C)

FIGURE 26. PG DELAY vs TEMPERATURE

FIGURE 27. HIGH-SIDE r

vs TEMPERATURE

DS(ON)

FN8677 Rev.2.00

Mar 17, 2017

Page 10 of 19

ISL85012

Typical Characteristics (Continued)

10

9

8

7

6

5

4

3

2

1

0

-40 -25 -10

5

20

35

50 65

80

95 110 125

JUNCTION TEMPERATURE (°C)

FIGURE 28. LOW-SIDE r

vs TEMPERATURE

DS(ON)

Enable and Soft-Start

Detailed Description

Chip operation begins after V PVIN, and V exceed their rising

IN, DD

The ISL85012 combines a synchronous buck controller with a

pair of integrated switching MOSFETs. The buck controller drives

the internal high-side and low-side N-channel MOSFETs to deliver

load currents up to 12A. The buck regulator can operate from an

unregulated DC source, such as a battery, with a voltage ranging

from +3.8V to +18V. An internal 5V LDO voltage regulator is used

to bias the controller. The converter output voltage is

programmed using an external resistor divider and will generate

regulated voltages down to 0.6V. These features make the

regulator suited for a wide range of applications.

POR trip points. If EN is held low externally, nothing happens until

this pin is released. Once the voltage on the EN pin is above 0.6V,

the LDO powers up and soft-start control begins. The ISL85012

operates at Discontinuous Conduction Mode (DCM) during

soft-start. The soft-start time is 3ms. EN can be directly driven by

VIN or an external power supply. It is recommended to add an RC

filter at the EN pin if the signal which drives the EN is noisy.

The part is designed supporting start-up into a prebiased load

(the prebiased voltage requires to be less than the setting output

voltage). Both high-side and low-side switches are disabled until

the internal SS voltage exceeds the FB voltage during start-up.

The controller uses a current mode loop, which simplifies the

loop compensation and permits fixed frequency operation over a

wide range of input and output voltages. The internal feedback

loop compensation option allows for simple circuit design.

600kHz (FREQ = float) and 300kHz (FREQ = GND) can be

selected as the default switching frequency. The regulator can be

synchronized from 100kHz to 1MHz by SYNC pin as well.

PWM Control Scheme

The ISL85012 employs the current-mode Pulse-Width

Modulation (PWM) control scheme for fast transient response.

The current loop consists of the oscillator, the PWM comparator,

current sensing circuit, and the slope compensation circuit. The

gain of the current sensing circuit is typically 55mV/A and the

The buck regulator is equipped with a lossless current limit

scheme. The current in the output stage is derived from

temperature compensated measurements of the drain-to-source

voltage of the internal power MOSFETs.

slope compensation is 780mV/t (t = period). The control

SS SS

reference for the current loop comes from the Error Amplifier’s

(EA) output, which compares the feedback signal at FB pin to the

integrated 0.6V reference.

Operation Initialization

The power-on reset circuitry and enable inputs prevent false

start-up of the PWM regulator output. Once all the input criteria

are met (see Figure 29), the controller soft-starts the output

voltage to the programmed level.

Setting as internal compensation (COMP short to GND through a

200Ω resistor), the voltage loop is internally compensated with a

30pF and 800kΩ RC network either the switching regulator

works at default 600kHz (FREQ = float) or it is synchronized

externally by SYNC pin. A 30pF and 1200kΩ RC network is

implemented for internal compensation when It works at default

300kHz (FREQ = GND).

EN

0.6V

POR

VIN

4.4V

VDD

3.4V

PVIN

3.8V

FIGURE 29. POR CIRCUIT

FN8677 Rev.2.00

Mar 17, 2017

Page 11 of 19

ISL85012

The PWM operation is initialized by the clock from the oscillator.

The high-side MOSFET is turned on at the beginning of a PWM

cycle and the current in the MOSFET starts to ramp-up. When the

sum of the current amplifier CSA, and the slope compensation

The output voltage programming resistor, R , will depend on the

2

value chosen for the feedback resistor, R , and the desired

1

output voltage, V

; see Equation 2. The R value will

OUT

1

determine the gain of the feedback loop. See “Loop

(780mV/t ) reaches the control reference of the current loop

Compensation Design” on page 15 for more details. The value for

the feedback resistor is typically between 1kΩ and 370kΩ.

SS

(COMP), the PWM comparator sends a signal to the PWM logic to

turn off the upper MOSFET and turn on the lower MOSFET. The

lower MOSFET stays on until the end of the PWM cycle. Figure 30

shows the typical operating waveforms during Continuous

Conduction Mode (CCM) operation. The dotted lines illustrate

the sum of the compensation ramp and the current-sense

amplifier’s output.

R

 0.6V

1

----------------------------------

R

=

(EQ. 2)

2

V

– 0.6V

OUT

If the desired output voltage is 0.6V, then R is left unpopulated.

2

R is still required to set the low frequency pole of the modulator

1

compensation.

V

OUT

EAMP

R

1

V

CSA

-

+

DUTY

CYCLE

EA

2

0.6V

REFERENCE

I

L

V

OUT

FIGURE 31. EXTERNAL RESISTOR DIVIDER

Protection Features

FIGURE 30. PWM OPERATION WAVEFORMS

The regulator limits current in all on-chip power devices.

Overcurrent limits are applied to the two output switching

MOSFETs as well as to the LDO linear regulator that feeds V

The output overvoltage protection circuitry on the switching

regulator provides a second layer of protection.

Light-Load Operation

The ISL85012 monitor both the current in the low-side MOSFET

and the voltage of the FB node for regulation. Pulling the SYNC

pin low allows the regulator to enter discontinuous operation

when lightly loaded by operating the low-side MOSFET in Diode

Emulation Mode (DEM). In this mode, reverse current is not

allowed in the inductor and the output falls naturally to the

regulation voltage before the high-side MOSFET is switched for

the next cycle. In CCM mode, the boundary is set by Equation 1:

.

DD

High-Side MOSFET Overcurrent Protection

Current flowing through the internal high-side switching MOSFET

is monitored during on-time. The current, which is temperature

compensated, will compare to a default 18A overcurrent limit.

The ISL85012 offers two OCP schemes to implement the on-time

overcurrent protection, which can be configured by the MODE pin

(see Table 4).

V

1 – D

OUT

(EQ. 1)

----------------------------------

=

I

OUT

2Lf

SW

where D = duty cycle, f

= switching frequency, L = inductor

SW

= output loading current, and V

TABLE 4. OCP SCHEME SETTING

MODE

value, I

= output voltage.

OUT

Table 3 shows the operating modes determined by the SYNC pin.

Float

GND

TABLE 3. OPERATION MODE SETTING

SYNC

Enter hiccup mode after eight

consecutive cycle-by-cycle limit.

Blanking time is 150ms

Enter latch-off mode after

eight consecutive cycle-by-cycle

limit

Float

GND

DEM

Force CCM

If the measured current exceeds the overcurrent limit, the high-side

MOSFET is immediately turned off and will not turn on again until

the next switching cycle. After eight consecutive cycles of overcurrent

events detected, the converter will operate at the selected OCP

scheme according to the MODE pin configuration. A cycle where an

overcurrent condition is not detected will reset the counter.

Synchronization

The ISL85012 can be synchronized from 100kHz to 1MHz by an

external signal applied to the SYNC pin. The rising edge on the SYNC

triggers the rising edge of the PHASE pulse. Make sure the on-time

of the SYNC pulse is longer than 100ns.

The switching frequency will be folded back if the OCP is tripped

and the on-time of the PWM is less than 250ns to lower down the

average inductor current.

Output Voltage Selection

The regulator output voltages can be programmed using external

resistor dividers that scale the voltage feedback relative to the

internal reference voltage. The scaled voltage is fed back to the

inverting input of the error amplifier; refer to Figure 31.

FN8677 Rev.2.00

Mar 17, 2017

Page 12 of 19

ISL85012

Low-Side MOSFET Overcurrent Protection

BOOT Undervoltage Detection

Low-side current limit consists of forward current limit (from GND

to PHASE) and reverse current limit (from PHASE to GND).

The internal driver of the high-side FET is equipped with a BOOT

Undervoltage (UV) detection circuit. In the event the voltage

difference between BOOT and PHASE falls below 2.8V, the UV

detection circuit allows the low-side MOSFET on for 250ns, to

recharge the bootstrap capacitor.

Current through the low-side switching MOSFET is sampled

during off time. The low-side OCP comparator is flagged if the

low-side MOSFET current exceeds 21A (forward). It resets the flag

when the current falls below 15A. The PWM will skip cycles when

the flag is set, allowing the inductor current to decay to a safe

level before resuming switching (see Figure 32).

While the ISL85012 includes an internal bootstrap diode,

efficiency can be improved by using an external supply voltage

and bootstrap Schottky diode. The external diode is then sourced

from a fixed external 5V supply or from the output of the

switching regulator if this is at 5V. The bootstrap diode can be a

low cost type, such as the BAT54 (see Figure 33).

Similar to the forward overcurrent, the reverse current protection

is realized by monitoring the current across the low-side MOSFET.

When the low-side MOSFET current reaches -7.5A, the

synchronous rectifier is turned off. This limits the ability of the

regulator to actively pull-down on the output.

Power-Good

ISL85012 has a Power-Good (PG) indicator which is an open drain

of a MOSFET. It requires pull-up to VDD or other voltage source

lower than 5.5V through a resistor (usually from 10k to 100kΩ).

The PG asserted 1.5ms after the FB voltage reaches 90% of the

reference voltage in soft-start. It pulls low if the FB voltage drops to

87% of the reference voltage or exceeds 116% of the reference

voltage during the normal operation. Disabling the part also pulls

the PG low. The PG will reassert when the FB voltage drops back to

113% (100%) of the reference voltage after tripping the

21A

20A

18A

I

L

15A

overvoltage protection when SYNC is low (float/high).

PWM

PHASE

CLOCK

C

4

0.1µF

BOOT

FIGURE 32. LOW-SIDE FORWARD OCP

ISL85012

Output Overvoltage Protection

BAT54

5V

The overvoltage protection triggers when the output voltage

exceeds 116% of the set voltage. In this condition, high-side and

low-side MOSFETs are off until the output drops to within the

regulation band. Once the output is in regulation, the controller

will restart under internal SS control.

OR 5V SOURCE

OUT

FIGURE 33. EXTERNAL BOOTSTRAP DIODE

Application Guidelines

Input Overvoltage Protection

The input overvoltage protection system prevents operation of

the switching regulator whenever the input voltage is higher than

20V. The high-side and low-side MOSFETs are off and the

converter will restart under internal SS control when the input

voltage returns to normal.

Buck Regulator Output Capacitor Selection

An output capacitor is required to filter the inductor current and

supply the load transient current. The filtering requirements are a

function of the switching frequency, the ripple current and the

required output ripple. The load transient requirements are a

function of the slew rate (di/dt) and the magnitude of the

transient load current. These requirements are generally met

with a mix of capacitor types and careful layout.

Thermal Overload Protection

Thermal overload protection limits the maximum die

temperature, and thus the total power dissipation in the

regulator. A sensor on the chip monitors the junction

temperature. A signal is sent to the fault monitor circuits

High frequency ceramic capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors. The

bulk filter capacitor values are generally determined by the

Equivalent Series Resistance (ESR) and voltage rating

whenever the junction temperature (T ) exceeds +160°C, which

J

causes the switching regulator and LDO to shut down.

requirements rather than actual capacitance requirements.

The switching regulator turns on again and soft-starts after the

IC’s junction temperature cools by 10°C. The switching regulator

exhibits hiccup mode operation during continuous thermal

overload conditions. For continuous operation, do not exceed the

+125°C junction temperature rating.

FN8677 Rev.2.00

Mar 17, 2017

Page 13 of 19

ISL85012

2

L

 I

out TRAN

(EQ. 5)

(EQ. 6)

--------------------------------------------------------------

=

V

SAG

2C

 V – V



OUT

IN

DV

HUMP

2

L

 I

out TRAN

-----------------------------------------

=

HUMP

V

2C

 V

OUT

DV

ESR

where I

= Output Load Current Transient and C

= Total

OUT

TRAN

Output Capacitance.

DV

SAG

In a typical converter design, the ESR of the output capacitor

bank dominates the transient response. The ESR and the ESL are

typically the major contributing factors in determining the output

capacitance. The number of output capacitors can be

ESL

I

OUT

determined by using Equation 7, which relates the ESR and ESL

of the capacitors to the transient load step and the tolerable

I

tran

output voltage excursion during load transient (V ):

o

ESL  I

TRAN

----------------------------------

+ ESR  I

TRAN

dt

(EQ. 7)

-----------------------------------------------------------------------------

Number of Capacitors =

V

o

If V

SAG

and/or V are found to be too large for the output

HUMP

FIGURE 34. TYPICAL TRANSIENT RESPONSE

voltage limits, then the amount of capacitance may need to be

increased. In this situation, a trade-off between output

inductance and output capacitance may be necessary.

High frequency decoupling capacitors should be placed as close

to the power pins of the load as physically possible. Be careful

not to add inductance in the circuit board wiring that could

cancel the usefulness of these low inductance components.

Consult with the manufacturer of the load on specific decoupling

requirements.

The ESL of the capacitors, which is an important parameter in

the previous equations, is not usually listed in specification.

Practically, it can be approximated using Equation 8 if an

Impedance vs Frequency curve is given for a specific capacitor:

The shape of the output voltage waveform during a load transient

that represents the worst case loading conditions, will ultimately

determine the number of output capacitors and their type. When

this load transient is applied to the converter, most of the energy

required by the load is initially delivered from the output

capacitors. This is due to the finite amount of time required for

the inductor current to slew up to the level of the output current

required by the load. This phenomenon results in a temporary dip

in the output voltage. At the very edge of the transient, the

Equivalent Series Inductance (ESL) of each capacitor induces a

spike that adds on top of the existing voltage drop due to the

Equivalent Series Resistance (ESR).

1

(EQ. 8)

----------------------------------------

ESL =

2

C2    f



res

where f is the frequency where the lowest impedance is

res

achieved (resonant frequency).

The ESL of the capacitors becomes a concern when designing

circuits that supply power to loads with high rates of change in

the current.

Output Inductor Selection

The output inductor is selected to meet the output voltage ripple

requirements and minimize the converter’s response time to the

load transient. The inductor value determines the converter’s

ripple current and the ripple voltage is a function of the ripple

current. The ripple voltage and current are approximated by

Equations 9 and 10:

After the initial spike, attributable to the ESR and ESL of the

capacitors, the output voltage experiences sag. This sag is a

direct consequence of the amount of capacitance on the output.

During the removal of the same output load, the energy stored in

the inductor is dumped into the output capacitors. This energy

dumping creates a temporary hump in the output voltage. This

hump, as with the sag, can be attributed to the total amount of

capacitance on the output. Figure 34 shows a typical response to

a load transient.

V – V

 V

OUT

IN

OUT

(EQ. 9)

------------------------------------ ---------------

I =

V



f

 L

V

IN

SW

(EQ. 10)

= I  ESR

OUT

The amplitudes of the different types of voltage excursions can

be approximated using Equations 3, 4, 5 and 6.

Increasing the value of inductance reduces the ripple current and

voltage. However, the large inductance values reduce the

converter’s response time to a load transient. It is recommended

to set the ripple inductor current to approximately 30% of the

maximum output current for optimized performance.

Recommend the design of the inductor ripple current does not

exceeds 5A in the applications of ISL85012.

V

= ESR  I

(EQ. 3)

ESR

TRAN

I

TRAN

dt

(EQ. 4)

----------------

V

= ESL 

ESL

FN8677 Rev.2.00

Mar 17, 2017

Page 14 of 19

ISL85012

One of the parameters limiting the converter’s response to a load

transient is the time required to change the inductor current.

Given a sufficiently fast control loop design, the ISL85012 will

provide either 0% or 100% duty cycle in response to a load

transient. The response time is the time required to slew the

inductor current from an initial current value to the transient

current level. During this interval, the difference between the

inductor current and the transient current level must be supplied

by the output capacitor. Minimizing the response time can

minimize the output capacitance required.

Loop Compensation Design

When COMP is not connected to GND through a 200Ω resistor,

the COMP pin is active for external loop compensation. The

regulator uses constant frequency peak current mode control

architecture to achieve a fast loop transient response. An

accurate current sensing pilot device in parallel with the

high-side switch is used for peak current control signal and

overcurrent protection. The inductor is not considered as a state

variable since its peak current is constant, and the system

becomes a single order system. It is much easier to design a

type II compensator to stabilize the loop than to implement

voltage mode control. Peak current mode control has an inherent

input voltage feed-forward function to achieve good line

regulation. Figure 35 shows the small signal model of the

synchronous buck regulator.

The response time to a transient is different for the application of

load and the removal of load. Equations 11 and 12 give the

approximate response time interval for application and removal

of a transient load:

L x I

TRAN

- V

(EQ. 11)

t

=

RISE

V

IN OUT

V_IN

d

L

DCR

R

I_L

Vo

L x I

1:D

I_Ld

TRAN

VOUT

V_IN

(EQ. 12)

t

=

FALL

c

R_o

where I

is the transient load current step, t

is the

TRAN

response time to the application of load, and t

RISE

Rt

FALL

C_o

response time to the removal of load. The worst case response

time can be either at the application or removal of load. Be sure

to check both of these equations at the minimum and maximum

output levels for the worst case response time.

Ti(s)

d

Fm

Input Capacitor Selection

He(s)

Use a mix of input bypass capacitors to control the input voltage

ripple. Use ceramic capacitors for high frequency decoupling and

bulk capacitors to supply the current needed each time the

switching MOSFET turns on. Place the ceramic capacitors

physically close to the MOSFET VIN pins (switching MOSFET

drain) and PGND.

Tv(s)

-Av(s)

V_comp

FIGURE 35. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK

REGULATOR

The important parameters for the bulk input capacitance are the

voltage rating and the RMS current rating. For reliable operation,

select bulk capacitors with voltage and current ratings above the

maximum input voltage and largest RMS current required by the

circuit. Their voltage rating should be at least 1.25 times greater

than the maximum input voltage, while a voltage rating of 1.5

times is a conservative guideline. For most cases, the RMS

current rating requirement for the input capacitor of a buck

regulator is approximately 1/2 the DC load current.

To simplify the analysis, sample and hold effect block He(s) and

slope compensation are not taken into account. Assume V

comp

is equal to the current sense signal ILxRt and ignore the DCR of

the inductor, the power train can be approximated by a voltage

controlled current source supplying current to the output

capacitor and load resistor (see Figure 36). The transfer function

frequency response is presented in Figure 37.

L

V

o

The maximum RMS current required by the regulator may be

closely approximated through Equation 13:

I

L

R

c

2

R

o

V_OUT

-------------

V_IN

V

_IN– V_OUTV_OUT



 

 

 

V

comp

2

1

12

------ ---------------------------- -------------

I_RMS

=

 I

+







OUT

1/R

t

L  f

V_IN

MAX



SW

(EQ. 13)

C

o

For a through-hole design, several electrolytic capacitors may be

needed, especially at temperatures less than -25°C. The

electrolytic's ESR can increase ten times higher than at room

temperature and cause input line oscillation. In this case, a more

thermally stable capacitor such as X7R ceramic should be used.

For surface mount designs, solid tantalum capacitors can be

used, but caution must be exercised with regard to the capacitor

surge current rating. Some capacitor series available from

reputable manufacturers are surge current tested.

FIGURE 36. POWER TRAIN SMALL SIGNAL MODEL

FN8677 Rev.2.00

Mar 17, 2017

Page 15 of 19

ISL85012

fp

Gdc

R₃/R₁

fz2

fz1

fpc fc

f_c

fz

FIGURE 39. POWER TRAIN FREQUENCY RESPONSE

Design example: V = 12V, V = 1.8V, I = 10A, f

= 600kHz,

R = 200kΩ, R = 100kΩ, C = 3x100µF/3mΩ 6.3V ceramic

FIGURE 37. POWER TRAIN SMALL FREQUENCY RESPONSE

IN SW

O

1

2

o

The simplified transfer function is derived in Equation 14.

(actually ~150µF), L = 0.68µH.

S

------

1 +

Select f = 80kHz. The gain of the Gp(s)xAv(s) should has a unity

c

ˆ



v

o

z

(EQ. 14)

gain at crossover frequency. Thus, R can be derived as:

----------------

comp

----------------

GpS =

= Gdc

3

ˆ

S

v

------

1 +



(EQ. 17)

p

R

= 2f C R R = 829k

c o t 1

3

where:

Select 800kΩ for R . Place the zero f around the pole fp to

achieve -20db/dec roll off.

3

z1

R

1

o

------

-----------------

------------------------------------

Gdc =

;  = 2fz =

;  = 2fp =

z

p

R

t

R xC

R + R xC

o c

c

o

Ro + RcxC

o

(EQ. 15)

(EQ. 18)

-------------------------------------

C

=

= 29pF

2

R

3

Note that C is the actual capacitance seen by the regulator,

o

where Rc is the ESR of the output capacitor.

Select 30pF for C . Zero f is a phase boost zero to increase the

which may include ceramic high frequency decoupling and bulk

output capacitors. Ceramic may have to be derated by

approximately 40% depending on dielectric, voltage stress, and

temperature.

2

z2

phase margin. Place it between f and 1/2 switching frequency.

c

In this case, 4.7pF capacitor is selected and the zero is placed at

f

:

z2

Usually, a type II compensation network is used to compensate

the peak current mode control converter. Figure 38 shows a

typical type II compensation network and its transfer function is

expressed in Equation 16. The frequency response is shown in

Figure 39.

1

(EQ. 19)

----------------------

f

=

= 169kHz

z2

2R C

1

The calculated values for R , R , C , and R , C match with the

1.8V output application in the recommended design with internal

compensation shown in Table 1 on page 2. Do not select

1

2

1

3

2

V

o

resistance higher than 370kΩ for R in real applications to avoid

1

parasitic impaction.

R

3

C

2

C

1

R₁

In practice, it is recommended to select lower resistance for

R /R and R in the external compensation applications.

1

2

3

Usually, 10 times lower compared with the internal

compensation is a good start.

V

fb

V

comp

R

2

V

ref

FIGURE 38. TYPE II COMPENSATION NETWORK

S





 

 





------------

1 +

ˆ



v

comp

cz1

cz2

(EQ. 16)

---------------- ---------------------------------------------------------

A S=

=

v

ˆ

SC R

2

v

1

o

where:

1

--------------

----------------------

=



= 2f

=

 

= 2f

=

 f

cz1

z1

cz2

z2

pc

R C

2R C

3

2

1

1 2

FN8677 Rev.2.00

Mar 17, 2017

Page 16 of 19

ISL85012

Layout Considerations

The layout is very important in high frequency switching

converter design. With power devices switching efficiently at

600kHz, the resulting current transitions from one device to

another causing voltage spikes across the interconnecting

impedances and parasitic circuit elements. These voltage spikes

can degrade efficiency, radiate noise into the circuit and lead to

device overvoltage stress. Careful component layout and printed

circuit board design minimizes these voltage spikes.

As an example, consider the turn-off transition of the upper

MOSFET. Prior to turn-off, the MOSFET is carrying the full load

current. During turn-off, current stops flowing in the MOSFET and

is picked up by the internal body diode of the low-side MOSFET.

Any parasitic inductance in the switched current path generates

a large voltage spike during the switching interval. Careful

component selection, tight layout of the critical components, and

short, wide traces minimize the magnitude of voltage spikes.

FIGURE 40. RECOMMENDED TOP LAYER LAYOUT

A multilayer printed circuit board is recommended. Figures 40

and 41 show the recommended layout of the top layer and the

inner Layer 1 of the schematic in Figure 1 on page 1.

1. Place the input ceramic capacitors between PVIN and GND

pins. Put them as close to the pins as possible.

2. A 1µF decoupling input ceramic capacitor is recommended.

Place it as close to the VIN pin as possible.

3. A 2.2µF decoupling ceramic capacitor is recommended for

VDD pin. Place it as close to the VDD pin as possible.

4. The entire inner Layer 1 is recommended to be the GND plane

in order to reduce the noise coupling.

5. The switching node (PHASE) plane needs to be kept away

from the feedback network. Place the resistor divider close to

the IC.

FIGURE 41. SOLID GND PLANE OF INNER LAYER 1

6. Put three to five vias on the GND pin to connect the GND plane

of other layers for better thermal performance. This allows the

heat to move away from the IC. Keep the vias small but not so

small that their inside diameter prevents solder wicking

through the holes during reflow. An 8 mil hole with 15 mil

diameter vias are used on the evaluation board. Do not use

“thermal relief” patterns to connect the vias. It is important to

have a complete connection of the plated-through hole to

each plane.

FN8677 Rev.2.00

Mar 17, 2017

Page 17 of 19

ISL85012

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please visit our website to make sure that you have the latest revision.

DATE

REVISION

FN8677.2

CHANGE

Mar 17, 2017

In “Power-Good” on page 13, updated 88% to 87% and 114% to 113%.

Updated verbiage above Equation 7.

Updated Equations 10 and 18.

Updated verbiage above Equations 17 (changed 60kHz to 80kHz), 18 (changed 800Ω to 800kΩ), 19 (changed

R3 to C2).

Updated Layout Considerations for more clarification.

Jan 5, 2017

Oct 3, 2016

FN8677.1

FN8677.0

Updated ordering information table to remove bulk part and add tape and reel versions.

Added Table 2 on page 2.

Added the last two sentences in 1st paragraph in “Enable and Soft-Start” on page 11 to instruct how to use the

EN pin.

Initial Release

About Intersil

Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products

address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.

For the most updated datasheet, application notes, related documentation and related parts, please see the respective product

information page found at www.intersil.com.

For a listing of definitions and abbreviations of common terms used in our documents, visit: www.intersil.com/glossary.

You can report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.

Reliability reports are also available from our website at www.intersil.com/support

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8677 Rev.2.00

Mar 17, 2017

Page 18 of 19

ISL85012

For the most recent package outline drawing, see L15.3.5x3.5.

Package Outline Drawing

L15.3.5x3.5

15 LEAD THIN QUAD FLAT NO-LEAD PACKAGE (TQFN)

Rev 1, 9/14

SEE PIN 1 ID DETAIL

10 x 0.50 BSC

12x 0.25±0.05

5

A

3.50

B

0.10 M C A B

0.05

PIN #1

4

1

2

3

4

5

6

M

C

INDEX AREA

1.002

7

2x 0.45±0.05

0.749 BSC

0.653 BSC

8

9

0.10 M C A B

3.50

0.05

M

C

0.258±0.05

0.10 M C A B

1.096

0.05

M

C

(2X)

0.05 C

15 14 13 12 11 10

BOTTOM VIEW

12 x 0.48±0.1

0.05 C (2X)

TOP VIEW

0.15

PACKAGE

OUTLINE

(12x 0.25±0.05)

12x 0.68±0.1

1

0.15

(10x 0.50)

(1.002)

(2x 0.45±0.05)

(0.258±0.05)

0.37

(0.749)

(0.653)

PIN 1 ID DETAIL

(3.90)

0.10 C

(1.096)

0.203 REF

C

0.75 ±0.05

(0.20 TYP)

(3.90)

SEATING

PLANE

-0

+0.05

6

15x

0.08 C

0.02

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5m-1994.

2. All dimensions are in millimeters.

3.

N is the total number of terminals.

4. The location of the marked terminal #1 identifier is within the hatched area.

Dimension applies to metallized terminal and is measured between

0.15mm and 0.30mm from the terminal tip. If the terminal has a radius

on the other end of it, dimension b should not be measured in that

radius area.

5.

6.

Coplanarity applies to the terminals and all other bottom surface metallization.

FN8677 Rev.2.00

Mar 17, 2017

Page 19 of 19


型号：	ISL85012FRZ-T7A
厂家：	RENESAS TECHNOLOGY CORP
描述：	12A, 3.8V to 18V Input, Synchronous Buck Regulator
文件：	总19页 (文件大小：973K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL85012FRZ-T7A [RENESAS]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E