ISL85402IRZ-T [RENESAS]
2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter; QFN20; Temp Range: -40° to 85°C;
| 型号： | ISL85402IRZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter; QFN20; Temp Range: -40° to 85°C 开关 |
| 文件： | 总22页 (文件大小：1734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART
ISL85403
ISL85402
FN7640
Rev 1.00
April 25, 2013
2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or
Boost Buck Converter
The ISL85402 is a synchronous buck controller with a 125mΩ
Features
high-side MOSFET and low-side driver integrated. The ISL85402
supports a wide input range of 3V to 36V in buck mode. It
• Buck Mode: Input Voltage Range 3V to 36V (Refer to “Input
Voltage” on page 13 for more details)
supports 2.5A continuous load under conditions of 5V V , V
OUT IN
range of 8V to 36V, 500kHz and +105°C ambient temperature
with still air. For any specific application, the actual maximum
output current depends upon the die temperature not exceeding
+125°C with the power dissipated in the IC, which is related to input
voltage, output voltage, duty cycle, switching frequency, board layout
and ambient temperature, etc. Refer to “Output Current” on page 14
for more details.
• Boost Mode Expands Operating Input Voltage Lower Than
2.5V (Refer to “Input Voltage” on page 13 for more details)
• Selectable Forced PWM Mode or PFM Mode
• 300µA IC Quiescent Current (PFM, No Load); 180µA Input
Quiescent Current (PFM, No Load, V
AUXVCC)
Connected to
OUT
• Less than 3µA Shut Down Input Current (IC Disabled)
• Operational Topologies
The ISL85402 has a flexible selection of operation modes of
forced PWM mode and PFM mode. In PFM mode, the
quiescent input current is as low as 180µA (AUXVCC connected
- Synchronous Buck
to V
). The load boundary between PFM and PWM can be
- Non-Synchronous Buck
OUT
programmed to cover wide applications.
- Two-Stage Boost Buck
The low-side driver can be either used to drive an external low-side
MOSFET for a synchronous buck, or left unused for a standard
non-synchronous buck. The low-side driver can also be used to
drive a boost converter as a pre-regulator followed by a buck
controlled by the same IC, which greatly expands the operating
input voltage range down to 2.5V or lower (Refer to “Typical
Application Schematic III - Boost Buck Converter” on page 5).
• Programmable Frequency from 200kHz to 2.2MHz and
Frequency Synchronization Capability
• ±1% Tight Voltage Regulation Accuracy
• Reliable Overcurrent Protection
- Temperature Compensated Current Sense
- Cycle-by-Cycle Current Limiting with Frequency Foldback
- Hiccup Mode for Worst Case Short Condition
The ISL85402 offers the most robust current protections. It
uses peak current mode control with cycle-by-cycle current
limiting. It is implemented with frequency foldback under
current limit condition; besides that, the hiccup overcurrent
mode is also implemented to guarantee reliable operations
under harsh short conditions.
• 20 Ld 4x4 QFN Package
• Pb-Free (RoHS Compliant)
Applications
• General Purpose
• 24V Bus Power
• Battery Power
The ISL85402 has comprehensive protections against various faults
including overvoltage and over-temperature protections, etc.
•
Point of Load
• Embedded Processor and I/O Supplies
100
95
90
85
80
75
70
65
60
55
50
6V V
IN
PGOOD
12V V
IN
EN
V
IN
VIN
BOOT
MODE
SYNC
AUXVCC
36V V
IN
24V V
IN
VCC
ILIMIT
SS
V
OUT
ISL85402
PHASE
LGATE
PGND
EXT_BOOST
FS
SGND
FB
COMP
0.1m
1m
10m
100m
1.0
2.5
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
5V, T = +25°C
FIGURE 1. TYPICAL APPLICATION
V
OUT
A
FN7640 Rev 1.00
April 25, 2013
Page 1 of 22
ISL85402
ISL85402
(20 LD QFN)
TOP VIEW
Pin Configuration
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
EN
FS
SS
BOOT
PGND
21
PAD
LGATE
SYNC
FB
EXT_BOOST
COMP
6
7
8
9
10
Functional Pin Descriptions
PIN NAME
PIN #
DESCRIPTION
EN
1
The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW.
Range: 0V to 5.5V.
FS
SS
FB
2
3
4
Connecting this pin to VCC, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator
switching frequency can also be programmed by adjusting the resistor from this pin to GND.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start
interval of the converter. Also, this pin can be used to track a ramp on this pin.
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from
V
to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage
OUT
drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin
is also monitored for overvoltage events.
COMP
ILIMIT
5
6
Output of the voltage feedback error amplifier.
Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limiting threshold
is set to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND.
MODE
7
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode
when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and
PWM can also be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on
page 13.
PGOOD
8
PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV
or UV) or when the EN pin is pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (V > 90%).
O
PHASE
9, 10 These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of
the high-side N-channel MOSFET.
EXT_BOOST
11
This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the
controller will detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in
synchronous/non-synchronous buck mode and will latch in this state unless VCC is below POR falling threshold; if the voltage
on this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode, the
low-side driver output PWM with same duty cycle with upper-side driver to drive the boost switch.
In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high
threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost
converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “Boost Converter Operation” on page 14
for more details.
FN7640 Rev 1.00
April 25, 2013
Page 2 of 22
ISL85402
Functional Pin Descriptions (Continued)
PIN NAME
PIN #
DESCRIPTION
SYNC
12
This pin can be used to synchronize two or more ISL85402 controllers. Multiple ISL85402s can be synchronized with their
SYNC pins connected together. 180 degree phase shift is automatically generated between the master and slave ICs.
The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with
frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V.
This pin should be left floating if not used.
LGATE
13
In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency.
In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC before
VCC startup to have low-side driver (LGATE) disabled.
In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM.
PGND
BOOT
14
15
This pin is used as the ground connection of the power flow including driver. Connect it to large ground plane.
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive
the internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed.
A 1µF ceramic capacitor is recommended to be used between BOOT and PHASE pin.
VIN
16, 17 Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source
for the internal linear regulator that provides the bias of the IC. Range: 3V to 36V.
With the part switching, the operating input voltage applied to the VIN pins must be under 36V. This recommendation allows
for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding “Absolute Maximum
Ratings” on page 6.
SGND
VCC
18
19
This pin provides the return path for the control and monitor portions of the IC. Connect it to a quiet ground plane.
This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF
decoupling ceramic capacitor is recommended between VCC to ground.
AUXVCC
20
This pin is the input of the auxiliary internal linear regulator, which can be supplied by the regulator output after power-up.
With such configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V.
In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a
resistor divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V
minus the hysteresis, the boost PWM is enabled.
Range: 0V to 20V.
PAD
21
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground
copper plane with area as large as possible to effectively reduce the thermal impedance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(PB-Free)
PKG. DWG. #
L20.4x4C
ISL85402IRZ
85 402IRZ
Evaluation Board
-40 to +105
20 Ld 4x4 QFN
ISL85402EVAL1Z
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85402. For more information on MSL please see techbrief TB363.
FN7640 Rev 1.00
April 25, 2013
Page 3 of 22
Block Diagram
VCC
AUXVCC
PGOOD
VIN (x2)
VIN
CURRENT
MONITOR
AUXILARY LDO
BIAS LDO
ILIMIT
BOOT
POWER-ON
RESET
SGND
VCC
OCP, OVP, OTP
PFM LOGIC
BOOST MODE CONTROL
EN
EXT_BOOST
MODE
PFM/FPWM
PHASE (x2)
LGATE
GATE DRIVE
VOLTAGE
MONITOR
SYNC
FS
SLOPE
COMPENSATION
OSCILLATOR
+
+
BOOT REFRESH
0.8V
REFERENCE
SOFT-START
LOGIC
VCC
5 µA
COMPARATOR
EA
SS
FB
COMP
PGND
ISL85402
Typical Application Schematic I
PGOOD
PGOOD
EN
MODE
SYNC
AUXVCC
EN
V
IN
V
IN
VIN
VIN
BOOT
MODE
SYNC
AUXVCC
BOOT
VCC
ILIMIT
SS
V
VCC
ILIMIT
SS
V
OUT
OUT
ISL85402
ISL85402
PHASE
PHASE
LGATE
PGND
LGATE
PGND
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
FB
COMP
COMP
(b) NON-SYNCHRONOUS BUCK
(a) SYNCHRONOUS BUCK
Typical Application Schematic II - VCC Switch-Over to V
OUT
PGOOD
EN
MODE
SYNC
AUXVCC
PGOOD
EN
MODE
SYNC
AUXVCC
V
IN
V
IN
VIN
BOOT
VIN
BOOT
VCC
ILIMIT
SS
V
OUT
VCC
ILIMIT
SS
V
OUT
ISL85402
ISL85402
PHASE
PHASE
LGATE
PGND
LGATE
PGND
EXT_BOOST
FS
SGND
EXT_BOOST
FS
SGND
FB
FB
COMP
COMP
(a) SYNCHRONOUS BUCK
(b) NON-SYNCHRONOUS BUCK
Typical Application Schematic III - Boost Buck Converter
Battery
+
+
R1
R2
PGOOD
EN
MODE
EXT_BOOST
LGATE
R3
R4
AUXVCC
SYNC
VIN
VCC
ISL85402
BOOT
ILIMIT
SS
V
OUT
PHASE
FS
PGND
FB
SGND
COMP
FN7640 Rev 1.00
April 25, 2013
Page 5 of 22
ISL85402
Absolute Maximum Ratings
Thermal Information
VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V
Thermal Resistance
ISL85402 QFN 4x4 Package (Notes 4, 5). . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
JA (°C/W) JC (°C/W)
40 3.5
Absolute Boot Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V
BOOT
Upper Driver Supply Voltage, V
- V
. . . . . . . . . . . . . . . . . . . +6.0V
BOOT PHASE
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V
Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1000V
Latchup Rating (Tested per JESD78B; Class II, Level A) . . . . . . . . . 100mA
Recommended Operating Conditions
Supply Voltage on V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 36V
IN
AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating
Conditions Unless Otherwise Noted: V = 12V, or V = 4.5V ±10%, T = -40°C to +105°C. Typicals are at T = +25°C. Boldface limits apply
IN
CC
A
A
over the operating temperature range, -40°C to +105°C.
MIN
MAX
PARAMETER
PIN SUPPLY
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6) UNITS
V
IN
VIN Pin Voltage Range
VIN Pin
3.05
3.05
36
V
V
VIN Pin connected to VCC
5.5
Operating Supply Current
I
MODE = VCC/FLOATING (PFM), no load at the
output
300
1.2
1.8
µA
Q
MODE = GND (Forced PWM), V = 12V,
IN
IC Operating, Not Including Driving Current
mA
µA
Shut Down Supply Current
I
EN connected to GND, V = 12V
IN
3
IN_SD
INTERNAL MAIN LINEAR REGULATOR
MAIN LDO V Voltage
CC
V
V
V
V
> 5V
4.2
4.5
0.3
4.8
0.5
0.3
V
V
CC
IN
IN
IN
MAIN LDO Dropout Voltage
V
= 4.2V, I
= 35mA
DROPOUT_MAIN
VCC
= 3V, I
= 25mA
0.25
60
V
VCC
V
Current Limit of MAIN LDO
mA
CC
INTERNAL AUXILIARY LINEAR REGULATOR
AUXVCC Input Voltage Range
V
3
20
4.8
0.5
0.3
V
V
AUXVCC
AUX LDO V Voltage
CC
V
V
> 5V
4.2
4.5
0.3
CC
DROPOUT_AUX
AUXVCC
LDO Dropout Voltage
V
V
= 4.2V, I
= 35mA
= 25mA
VCC
V
AUXVCC
VCC
V
= 3V, I
0.25
60
V
AUXVCC
Current Limit of AUX LDO
mA
V
AUX LDO Switch-over Rising Threshold
AUX LDO Switch-over Falling Threshold Voltage
V
AUXVCC voltage rise; Switch to Auxiliary LDO
3
3.1
3.2
AUXVCC_RISE
V
AUXVCC voltage fall; Switch back to main BIAS
LDO
2.73
2.87
2.97
V
AUXVCC_FALL
AUX LDO Switch-over Hysteresis
V
AUXVCC Switch-over Hysteresis
0.2
V
AUXVCC_HYS
FN7640 Rev 1.00
April 25, 2013
Page 6 of 22
ISL85402
Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating
Conditions Unless Otherwise Noted: V = 12V, or V = 4.5V ±10%, T = -40°C to +105°C. Typicals are at T = +25°C. Boldface limits apply
IN
CC
A
A
over the operating temperature range, -40°C to +105°C. (Continued)
MIN
MAX
PARAMETER
POWER-ON RESET
Rising V POR Threshold
SYMBOL
TEST CONDITIONS
(Note 6) TYP (Note 6) UNITS
V
2.82
2.9
2.6
0.3
3.05
2.8
V
V
V
CC
Falling V POR Threshold
PORH_RISE
V
CC
POR Hysteresis
PORL_FALL
V
V
PORL_HYS
CC
ENABLE
Required Enable On Voltage
Required Enable Off Voltage
EN Pull-up Current
V
2
V
ENH
V
0.8
V
ENL
I
EN Left Floating, V = 24V
IN
0.8
0.5
µA
µA
µA
EN_PULLUP
EN Left Floating, V = 12V
IN
EN Left Floating, V = 5V
IN
0.25
OSCILLATOR
PWM Frequency
F
R
R
= 665kΩ
= 51.1kΩ
160
200
240
kHz
kHz
kHz
ns
OSC
FS
FS
1950 2200 2450
FS Pin Connected to VCC or Floating or GND
450
500
130
210
550
225
325
MIN ON Time
t
MIN_ON
MIN OFF Time
t
ns
MIN_OFF
SYNCHRONIZATION
Input High Threshold
Input Low Threshold
Input Minimum Pulse Width
Input Impedance
VIH
VIL
2
V
V
0.5
25
ns
kΩ
100
1.1
Input Minimum Frequency Divided by Free
Running Frequency
Input Maximum Frequency Divided by Free
Running Frequency
1.6
Output Pulse Width
Output Pulse High
C
= 100pF
100
ns
V
SYNC
VOH
VOL
R
= 1kΩ
VCC-
0.25
LOAD
Output Pulse Low
REFERENCE VOLTAGE
Reference Voltage
System Accuracy
FB Pin Source Current
Soft-start
GND
0.8
5
V
V
V
%
REF
-1.0
3
+1.0
7
nA
Soft-Start Current
ERROR AMPLIFIER
Unity Gain-Bandwidth
DC Gain
I
5
µA
SS
C
C
= 50pF
= 50pF
10
88
3.6
MHz
dB
V
LOAD
LOAD
Maximum Output Voltage
FN7640 Rev 1.00
April 25, 2013
Page 7 of 22
ISL85402
Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating
Conditions Unless Otherwise Noted: V = 12V, or V = 4.5V ±10%, T = -40°C to +105°C. Typicals are at T = +25°C. Boldface limits apply
IN
CC
A
A
over the operating temperature range, -40°C to +105°C. (Continued)
MIN
MAX
PARAMETER
Minimum Output Voltage
SYMBOL
SR
TEST CONDITIONS
(Note 6) TYP (Note 6) UNITS
0.5
5
V
Slew Rate
C
= 50pF
V/µs
LOAD
PFM MODE CONTROL
Default PFM Current Threshold
INTERNAL HIGH-SIDE MOSFET
MODE = VCC or Floating
700
125
mA
Upper MOSFET r
r
180
mΩ
DS(ON)
DS(ON)_UP
LOW-SIDE MOSFET GATE DRIVER
LGate Source Resistance
100mA Source Current
100mA Sink Current
3.5
3.3
Ω
Ω
LGATE Sink Resistance
BOOST CONVERTER CONTROL
EXT_BOOST Boost_Off Threshold Voltage
EXT_BOOST Hysteresis Sink Current
AUXVCC Boost Turn-Off Threshold Voltage
AUXVCC Hysteresis Sink Current
POWER-GOOD MONITOR
0.74
2.4
0.8
3.2
0.8
3.2
0.86
3.8
V
µA
V
I
EXT_BOOST_HYS
0.74
2.4
0.86
3.8
I
µA
AUXVCC_HYS
Overvoltage Rising Trip Point
Overvoltage Rising Hysteresis
Undervoltage Falling Trip Point
Undervoltage Falling Hysteresis
PGOOD Rising Delay
V
V
Percentage of Reference Point
Percentage Below OV Trip Point
Percentage of Reference Point
Percentage Above UV Trip Point
104
84
110
3
116
96
%
%
FB/ REF
V
V
V
FB/ OVTRIP
V
V
90
3
%
FB/ REF
V
%
FB/ UVTRIP
t
f
= 500kHz
2
ms
nA
V
PGOOD_DELAY
OSC
PGOOD Leakage Current
PGOOD HIGH, V
= 4.5V
10
0.10
PGOOD
PGOOD Low Voltage
V
PGOOD
PGOOD LOW, IPGOOD = 0.2mA
OVERCURRENT PROTECTION
Default Cycle-by-Cycle Current Limit Threshold
Hiccup Current Limit Threshold
OVERVOLTAGE PROTECTION
OV Latching-off Trip Point
I
I
= GND or VCC or Floating
3
3.6
4.2
A
OC_1
LIMIT
I
Hiccup, I
/I
OC_2 OC_1
115
%
OC_2
Percentage of Reference Point
LG = UG = LATCH LOW
120
110
%
%
%
OV Non-Latching-off Trip Point
Percentage of Reference Point
LG = UG = LOW
OV Non-Latching-off Release Point
OVER-TEMPERATURE PROTECTION
Over-Temperature Trip Point
Over-Temperature Recovery Threshold
NOTE:
Percentage of Reference Point
102.5
155
140
°C
°C
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN7640 Rev 1.00
April 25, 2013
Page 8 of 22
ISL85402
Performance Curves
100
95
90
85
80
75
70
65
60
55
50
100
95
6V V
IN
90
85
80
75
70
65
60
55
50
45
40
24V V
IN
36V V
12V V
IN
IN
12V V
IN
6V V
IN
36V V
IN
24V V
IN
35
30
0.1m
1m
10m
100m
1.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 3. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
FIGURE 4. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
MODE, 500kHz, V
5V, T = +25°C
V 5V, T = +25°C
OUT
A
OUT A
4.970
4.968
4.966
4.964
4.970
4.968
4.966
4.964
4.962
4.960
4.958
4.956
4.954
4.962
4.960
4.958
4.956
4.954
4.952
4.950
I
= 0A
O
24V V
I
= 2A
IN
O
6V V
IN
36V V
IN
I
= 1A
O
12V V
IN
4.952
4.950
0
5
10
15
20
25
30
36
0.0
0.5
1.0
1.5
2.0
2.5
INPUT VOLTAGE (V)
LOAD CURRENT (A)
FIGURE 5. LINE REGULATION, V
5V, T = +25°C
FIGURE 6. LOAD REGULATION, V 5V, T = +25°C
OUT A
OUT
A
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
100
95
90
85
80
75
70
65
60
55
50
45
40
6V V
IN
12V V
IN
24V V
IN
12V V
IN
36V V
IN
6V V
36V V
IN
IN
24V V
IN
0.0
0.5
1.0
1.5
2.0
2.5
0.1m
1m
10m
100m
1.0
2.5
LOAD CURRENT (A)
LOAD CURRENT (A)
FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM
MODE, 500kHz, V 3.3V, T = +25°C
FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE,
3.3V, T = +25°C
V
OUT
A
OUT
A
FN7640 Rev 1.00
April 25, 2013
Page 9 of 22
ISL85402
Performance Curves(Continued)
200
85
80
75
70
65
60
55
50
45
40
35
30
25
180
V
= 12V
IN
160
140
120
100
80
V
= 20V
O
V
= 24V
IN
V
= 12V
O
V
= 5V
O
60
40
20
0
-50
-25
0
25
50
75
100
125
0
5
10
15
20
(V)
25
30
35
40
V
AMBIENT TEMPERATURE (°C)
IN
FIGURE 9. INPUT QUIESCENT CURRENT UNDER NO LOAD,
PFM MODE, V = 5V
FIGURE 10. IC DIE TEMPERATURE UNDER +25°C AMBIENT
TEMPERATURE, STILL AIR, 500kHz, I = 2A
OUT
O
85
80
75
70
65
60
55
50
45
40
35
30
25
V
= 20V
O
V
2V/DIV
OUT
V
= 12V
O
V
= 5V
O
PHASE 20V/DIV
0
5
10
15
20
25
30
35
40
V
(V)
2ms/DIV
IN
FIGURE 11. IC DIE TEMPERATURE UNDER +25°C AMBIENT
TEMPERATURE, STILL AIR, 500kHz, I = 2.5A
FIGURE 12. SYNCHRONOUS BUCK MODE, V 36V, I 2A,
IN
O
ENABLE ON
O
V
2V/DIV
OUT
V
2V/DIV
OUT
PHASE 20V/DIV
PHASE 20V/DIV
2ms/DIV
2ms/DIV
FIGURE 14. V 36V, PREBIASED START-UP
IN
FIGURE 13. SYNCHRONOUS BUCK MODE, V 36V, I 2A,
IN
O
ENABLE OFF
FN7640 Rev 1.00
April 25, 2013
Page 10 of 22
ISL85402
Performance Curves(Continued)
V
20mV/DIV (5V OFFSET)
OUT
V
100mV/DIV (5V OFFSET)
OUT
I
1A/DIV
OUT
PHASE 20V/DIV
PHASE 20V/DIV
5µs/DIV
1ms/DIV
FIGURE 15. SYNCHRONOUS BUCK WITH FORCE PWM MODE,
36V, I 2A
FIGURE 16. V 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE
IN
V
IN
O
V
200mV/DIV (5V OFFSET)
OUT
V
70mV/DIV (5V OFFSET)
OUT
LGATE 5V/DIV
LGATE 5V/DIV
I
1A/DIV
OUT
PHASE 20V/DIV
PHASE 20V/DIV
100µs/DIV
1ms/DIV
FIGURE 17. V 24V, 80mA LOAD, PFM MODE
IN
FIGURE 18. V 24V, 0 TO 2A STEP LOAD, PFM MODE
IN
V
10mV/DIV (5V OFFSET)
OUT
V
10mV/DIV (5V OFFSET)
OUT
PHASE 5V/DIV
PHASE 10V/DIV
20µs/DIV
5µs/DIV
FIGURE 19. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
12V, NO LOAD
FIGURE 20. NON-SYNCHRONOUS BUCK, FORCE PWM MODE,
12V, 2A
V
V
IN
IN
FN7640 Rev 1.00
April 25, 2013
Page 11 of 22
ISL85402
Performance Curves(Continued)
V
BUCK 100mV/DIV (5V OFFSET)
OUT
V
BUCK 100mV/DIV (5V OFFSET)
OUT
V
_BOOST_INPUT 5V/DIV
IN
V
_BOOST_INPUT 5V/DIV
IN
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
PHASE_BOOST 10V/DIV
PHASE_BUCK 10V/DIV
20ms/DIV
10ms/DIV
FIGURE 21. BOOST BUCK MODE, BOOST INPUT STEP FROM
36V TO 3V, V
FIGURE 22. BOOST BUCK MODE, BOOST INPUT STEP FROM
BUCK = 5V, I
_BUCK = 1A
3V TO 36V, V
BUCK = 5V, I _BUCK = 1A
OUT
OUT
OUT
OUT
95
90
85
80
75
70
65
60
55
50
V
5V/DIV
OUT
15V V
IN
30V V
IN
IL_BOOST 2A/DIV
5V V
IN
6V V
IN
PHASE_BOOST 20V/DIV
PHASE_BUCK 20V/DIV
9V V
IN
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
10ms/DIV
LOAD CURRENT (A)
FIGURE 23. BOOST BUCK MODE, V = 9V, I = 1.8A, BOOST INPUT
FIGURE 24. EFFICIENCY, BOOST BUCK, 500kHz, VOUT 12V,
O
O
DROPS FROM 16V TO 9V DC
T = +25°C
A
FN7640 Rev 1.00
April 25, 2013
Page 12 of 22
ISL85402
default threshold is 700mA when there is no programming
resistor at the MODE pin.
Functional Description
Initialization
The current threshold for PWM/PFM boundary can be
Initially the ISL85402 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising ON
threshold, the internal LDO will start up to build up VCC. After
Power-On Reset (POR) circuits detect that VCC voltage has
exceeded the POR threshold, the soft-start will be initiated.
programmed by choosing the MODE pin resistor value calculated
from Equation 2, where IPFM is the desired PWM/PFM boundary
current threshold and R
118500
is the programming resistor.
MODE
(EQ. 2)
R
= ---------------------------------------
MODE
IPFM + 0.2
500
Soft-Start
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
400
300
200
(EQ. 1)
C
F = 6.5 t S
SS
SS
The SS ramp starts from 0 to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and IC gets into
steady state operation.
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at over load
condition. When a harsh conditon occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At dummy SS cycle, the current to charge soft-start cap
is cut down to 1/5 of its normal value. So a dummy SS cycle
takes 5x of the regular SS cycle. During the dummy SS period,
the control loop is disabled and no PWM output. At the end of
this cycle, it will start the normal SS. The hiccup mode persist
until the second overcurrent threshold is no longer reached.
100
0
0.0
0.2
0.4
0.6
0.8
(A)
1.0
1.2
1.4
I
PFM
FIGURE 25. R
vs I
PFM
MODE
Synchronous and Non-Synchronous Buck
The ISL85402 supports both Synchronous and non-synchronous
buck operations. For a non-synchronous buck operation when a
power diode is used as the low-side power device, the LGATE
driver can be disabled with LGATE connected to VCC (before IC
start-up).
The ISL85402 is capable of starting up with prebiased output.
PWM Control
AUXVCC Switch-Over
The ISL85402 has an auxiliary LDO integrated as shown in the
“Block Diagram” on page 4. It is used to replace the internal
MAIN LDO function after the IC startup. “Typical Application
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL85402 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
“Block Diagram” on page 4.
Schematic II - VCC Switch-Over to V
” on page 5 shows its
OUT
basic application setup with output voltage connected to
AUXVCC. After IC soft-start is done and the output voltage is built
up to steady state, and once the AUXVCC pin voltage is over the
AUX LDO Switch-over Rising Threshold, the MAIN LDO is shut off
and the AUXILIARY LDO is activated to bias VCC. Since the
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is trigger to shut down the PWM logic
to turn off the high-side MOSFET. The high-side MOSFET stays off
until the next clock signal comes for next cycle.
AUXVCC pin voltage is lower than the input voltage V , the
IN
internal LDO dropout voltage and the consequent power loss is
reduced. This feature brings substantial efficiency improvements
in light load range, especially at high input voltage applications.
The output voltage is sensed by a resistor divider from V
OUT
to
When the voltage at AUXVCC falls below the AUX LDO Switch-over
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
is re-activated to bias VCC. At the OV/UV fault events, the IC also
switches back over from AUXILIARY LDO to MAIN LDO.
the FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
PFM Mode Operation
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have PFM (Pulse Frequency Modulation)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL85402 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. The
Input Voltage
With the part switching, the operating ISL85402 input voltage
must be under 36V. This recommendation allows for short
voltage ringing spikes (within a couple of ns time range) due to
FN7640 Rev 1.00
April 25, 2013
Page 13 of 22
ISL85402
part switching while not exceeding the 44V, as stated in the
Absolute Maximum Ratings.
ambient conditions). For any other operating conditions, refer to
the previous mentioned thermal curves to estimate the
maximum output current. The output current should be derated
under any conditions causing the die temperature to exceed
+125°C.
The lowest IC operating input voltage (VIN pin) depends on VCC
voltage and the Rising and Falling V POR Threshold in
CC
Electrical Specifications table on page 7. At IC startup when VCC
is just over rising POR threshold, there is no switching before the
soft-start starts. Therefore, the IC minimum startup voltage on
Basically, the die temperature is equal to the sum of ambient
temperature and the temperature rise resulting from the power
dissipated by the IC package with a certain junction to ambient
thermal impedance JA. The power dissipated in the IC is related
to the MOSFET switching loss, conduction loss and the internal
LDO loss. Besides the load, these losses are also related to input
voltage, output voltage, duty cycle, switching frequency and
temperature. With the exposed pad at the bottom, the heat of
the IC mainly goes through the bottom pad and JA is greatly
reduced. The JA is highly related to layout and air flow
conditions. In layout, multiple vias (≥9) are strongly
the VIN pin is 3.05V (MAX of Rising V POR). When the soft-start
CC
is initiated, the regulator is switching and the dropout voltage
across the internal LDO increases due to driving current. Thus,
the IC VIN pin shutdown voltage is related to driving current and
VCC POR falling threshold. The internal upper side MOSFET has
typical 10nC gate drive. For a typical example of synchronous
buck with 4nC lower MOSFET gate drive and 500kHz switching
frequency, the driving current is 7mA total causing 70mV drop
across internal LDO under 3V V . Then the IC shut down voltage
IN
on the VIN pin is 2.87V (2.8V+0.07V). In practical design, extra
room should be taken into account with concern to voltage
spikes at VIN.
recommended in the IC bottom pad. The bottom pad with its vias
should be placed in the ground copper plane with an area as
large as possible across multiple layers. The JA can be reduced
further with air flow. Refer to Figures 8 and 9 for the thermal
performance with 100 CFM air flow.
With boost buck configuration, the input voltage range can be
expanded further down to 2.5V or lower depending on the boost
stage voltage drop upon maximum duty cycle. Since the boost
output voltage is connected to the VIN pin as the buck inputs,
after the IC starts up, the IC will keep operating and switching as
long as the boost output voltage can keep the VCC voltage higher
than falling threshold. Refer to “Boost Converter Operation” on
page 14 for more details.
Boost Converter Operation
“Typical Application Schematic III - Boost Buck Converter” on
page 5, shows the circuits where the boost works as a pre-stage
to provide input to the following Buck stage. This is for
applications when the input voltage could drop to a very low
voltage in some constants (in some battery powered systems as
for example), causing the output voltage to drop out of
regulation. The boost converter can be enabled to boost the input
voltage up to keep the output voltage in regulation. When system
input voltage recovers back to normal, the boost stage is
disabled while only the buck stage is switching.
Output Voltage
The ISL85402 output voltage can be programmed down to 0.8V
by a resistor divider from V
to FB. The maximum achievable
is the voltage drop
and
is decided by
OUT
voltage is (V *D ), where V
- V
IN MAX DROP DROP
in the power path including mainly the MOSFET r
inductor DCR. The maximum duty cycle D
MAX
DS(ON)
The EXT_BOOST pin is used to set boost mode and monitor the
boost input voltage. At IC start-up before soft-start, the controller
will be latched in boost mode when the voltage is at or above
200mV; it will latch in synchronous buck mode if voltage on this
pin is below 200mV. In boost mode the low-side driver output
PWM has the same PWM signal with the buck regulator.
(1 - Fs * t
).
MIN(OFF)
Output Current
With the high-side MOSFET integrated, the maximum output
current, which the ISL85402 can support is decided by the
package and many operating conditions. Thus, including input
voltage, output voltage, duty cycle, switching frequency and
temperature, etc. Note the following points.
In boost mode, the EXT_BOOST pin is used to monitor boost input
voltage to turn on and turn off the boost PWM. The AUXVCC pin is
used to monitor the boost output voltage to turn on and turn off
the boost PWM.
• The maximum output current is limited by the maximum OC
threshold that is 4.18A (TYP).
Referring to Figure 26 on page 15, a resistor divider from boost
input voltage to the EXT_BOOST pin is used to detect the boost
input voltage. When the voltage on EXT_BOOST pin is below 0.8V,
the boost PWM is enabled with a fixed 500µs soft-start and the
• From the thermal perspective, the die temperature shouldn’t
exceed +125°C with the power loss dissipated inside of the IC.
Figures 10 and 11 show the thermal performance of this part
operating at different conditions.
boost duty cycle increases linearly from t
*Fs to ~50%. A
MIN(ON)
3µA sinking current is enabled at the EXT_BOOST pin for
hysteresis purposes. When the voltage on the EXT_BOOST pin
recovers to be above 0.8V, the boost PWM is disabled
immediately. Use Equation 3 to calculate the upper resistor RUP
Figures 10 and 11 show 2A and 2.5A applications under +25°C
still air conditions over V range. The temperature rise data in
IN
these figures can be used to estimate the die temperature at
different ambient temperatures under various operating
conditions. Note that more temperature rise is expected at higher
ambient temperature due to more conduction loss caused by
(R1 in Figure 26) for a desired hysteresis V
voltage.
at boost input
HYS
VHYS
3A
r
increase.
R
M = ---------------------
(EQ. 3)
DS(ON)
UP
Generally, the part can output 2.5A in typical application
conditions (V 8~30V, V 5V, 500kHz, still air and +105°C
IN
O
FN7640 Rev 1.00
April 25, 2013
Page 14 of 22
ISL85402
Use Equation 4 to calculate the lower resistor RLOW (R2 in Figure 26)
according to a desired boost enable threshold.
From Equations 5 and 6, Equation 7 can be derived to estimate
the steady state boost output voltage as function of V and
BAT
V
:
OUT
R
0.8
UP
(EQ. 4)
R
= ---------------------------------------
LOW
VFTH – 0.8
(EQ. 7)
V
= V
+ V
OUT
OUTBST
BAT
Where VFTH is the desired falling threshold on boost input
voltage to turn on the boost, 3µA is the hysteresis current, and
0.8V is the reference voltage to be compared with.
After the IC starts up, the boost buck converters can keep
working when the battery voltage drops extremely low because
the IC’s bias (VCC) LDO is powered by the boost output. For
example, a 3.3V output application battery drops to 2V, and the
VIN pin voltage is powered by the boost output voltage that is
5.2V (Equation 7), meaning that the VIN pin (buck input) still sees
5.2V to keep the IC working.
Note the boost start-up threshold has to be selected in a way that
the buck is operating working well and kept in close loop
regulation before boost start-up. Otherwise, large in-rush current
at boost start-up could occur at boost input due to the buck open
loop saturation.
Note that in the previously mentioned case, the boost input current
could be high because the input voltage is very low
Similarly, a resistor divider from the boost output voltage to the
AUXVCC pin is used to detect the boost output voltage. When the
voltage on the AUXVCC pin is below 0.8V, the boost PWM is
enabled with a fixed 500µs soft-start, and a 3µA sinking current
is enabled at AUXVCC pin for hysteresis purposes. When the
voltage on the AUXVCC pin recovers to be above 0.8V, the boost
PWM is disabled immediately. Use Equation 3 to calculate the
(V *I = V *I /Efficiency). If the design is to achieve the low
IN IN OUT OUT
input operation with full load, the inductor and MOSFET have to be
selected with enough current ratings to handle the high current
appearing at boost input. The boost inductor current are the same
with the boost input current, which can be estimated as Equation 8,
where POUT is the output power, V
is the boost input voltage, and
BAT
upper resistor RUP (R in Figure 26) according to a desired
EFF is the estimated efficiency of the whole boost and buck stages.
3
hysteresis V at boost output voltage. Use Equation 4 to
HY
P
(EQ. 8)
OUT
IL = -------------------------------------
IN
calculate the lower resistor RLOW (R in Figure 26) according to a
4
V
EFF
BAT
desired boost enable threshold at boost output.
Based on the same concerns of the boost input current, the IC
should be disabled before the boost input voltage rises above a
certain level. PFM is not available in boost mode.
Assuming V
is the boost input voltage, VOUTBST is the boost
BAT
output voltage and V
is the buck output voltage, the steady
OUT
state transfer function are:
1
1 – D
(EQ. 5)
(EQ. 6)
-----------------
V
V
=
V
OUTBST
BAT
=
Oscillator and Synchronization
The oscillator has a default frequency of 500kHz with the FS pin
connected to VCC, or ground, or floating. The frequency can be
programmed to any frequency between 200kHz and 2.2MHz with
a resistor from FS pin to GND.
D
1 – D
-----------------
= D V
V
BAT
OUT
OUTBST
145000 – 16 FSkHz
R
k = ------------------------------------------------------------------------------------
FSkHz
(EQ. 9)
FS
BATTERY
VOUT_BST
+
+
R1
EXT_BOOST
0.8V
R2
I_HYS = 3µA
LOGIC
R3
R4
LGATE
AUXVCC
LGATE
DRIVE
PWM
0.8V
I_HYS = 3µA
FIGURE 26. BOOST CONVERTER CONTROL
FN7640 Rev 1.00
April 25, 2013
Page 15 of 22
ISL85402
dummy soft-start duration equaling to 5 regular soft-start periods.
After this dummy soft-start cycle, the true soft-start cycle is
attempted again. The IOC2 offers a robust and reliable protections
against the worst case conditions.
1200
1000
800
The frequency foldback is implemented for the ISL85402. When
overcurrent limiting, the switching frequency is reduced to be
proportional to output voltage in order to keep the inductor
current under limit threshold during overload condition. The low
limit of frequency under frequency foldback operation is 40kHz.
600
400
370
320
270
220
170
120
70
200
0
0
500
1000
1500
2000
2500
F
(kHz)
S
FIGURE 27. R vs FREQUENCY
FS
The SYNC pin is bi-directional and it outputs the IC’s default or
programmed local clock signal when it’s free running. The IC
locks to an external clock injected to the SYNC pin (external clock
frequency recommended to be 10% higher than the free running
frequency). The delay from the rising edge of the external clock
signal to the PHASE rising edge is half of the free running switching
period pulse 220ns, (0.5Tsw+220ns). The maximum external clock
frequency is recommended to be 1.6 of the free running frequency.
0.0
1.0
2.0
3.0
(A)
4.0
5.0
6.0
I
OC1
FIGURE 28. R
vs IOC1
LIM
When the part enters PFM pulse skipping mode, the
synchronization function is shut off and also no clock signal
output in SYNC pin.
Overvoltage Protection
If the voltage detected on the FB pin is over 110% of reference,
the high-side and low-side driver shuts down immediately and
won’t be allowed on until FB voltage drops to 0.8V. When the FB
voltage drops to 0.8V, the drivers are released to ON. If the 120%
overvoltage threshold is reached, the high-side and low-side
driver shuts down immediately and the IC is latched off. The IC
has to be reset for restart.
With the SYNC pins simply connected together, multiple
ISL85402s can be synchronized. The slave ICs automatically
have 180° phase shift with respective to the master IC.
Fault Protection
Overcurrent Protection
The overcurrent function protects against any overload condition
and output short at worst case, by monitoring the current flowing
through the upper MOSFET.
Thermal Protection
The ISL85402 PWM will be disabled if the junction temperature
reaches +155°C. A +15°C hysteresis insures that the device will
not restart until the junction temperature drops below +140°C.
There are 2 current limiting thresholds. The first one IOC1 is to
limit the high-side MOSFET peak current cycle-by-cycle. The
current limit threshold is set to default at 3.6A with ILIMIT pin
connected to GND or VCC, or left open. The current limit threshold
can also be programmed by a resistor RLIM at ILIMIT pin to
ground. Use Equation 10 to calculate the resistor.
Component Selections
The ISL85402 iSim model, which is available on the internet can
be used to simulate the behaviors to, which will assist with the
design.
300000
= ------------------------------------------------------
(EQ. 10)
Output Capacitors
R
LIM
I
A + 0.018
OC
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are 2 critical factors
when considering output capacitance choice. The current mode
control loop allows for the usage of low ESR ceramic capacitors
and thus smaller board layout. Electrolytic and polymer
capacitors may also be used.
Note that IOC1 is higher with lower R . Considering the OC
LIM
programming circuit tolerances over the temperature range -
40°C to 105°C, 71.5k is the lowest resistor value recommended
to be used for R
to achieve the highest OC threshold. With
LIM
71.5k R , the OC limit is 4.18A (TYP). A resistor lower than
LIM
71.5k would result in a default 3.6A OC1 threshold.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings with no DC
bias. In the DC/DC converter application, these conditions do not
The second current protection threshold IOC2 is 15% higher than
IOC1 mentioned previously. Instantly after the high-side MOSFET
current reaches IOC2, the PWM is shut off after 2-cycle delay and the
IC enters hiccup mode. In hiccup mode, the PWM is disabled for
FN7640 Rev 1.00
April 25, 2013
Page 16 of 22
ISL85402
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers data sheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
Increasing the value of inductance reduces the ripple current and
thus ripple voltage. However, the larger inductance value may
reduce the converter’s response time to a load transient. The
inductor current rating should be such that it will not saturate in
overcurrent conditions.
Low-Side Power MOSFET
In synchronous buck application, a power N MOSFET is needed
as the synchronous low side MOSFET and a good one should
have low Qgd, low r
and small Rg (Rg_typ < 1.5Ω
DS(ON)
recommended). Vgth_min is recommended to be higher than
1.2V. A good example is SQS462EN.
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
Output Voltage Feedback Resistor Divider
The output voltage can be programmed down to 0.8V by a
For the ceramic capacitors (low ESR):
resistor divider from V
to FB according to Equation 15.
OUT
I
----------------------------------
V
=
(EQ. 11)
OUTripple
R
8 F
C
UP
SW OUT
(EQ. 15)
V
= 0.8 1 + --------------------
OUT
R
LOW
where I is the inductor’s peak to peak ripple current, F
SW
is the
In an application requiring least input quiescent current, large
resistors should be used for the divider. 232k is recommended
for the upper resistor.
switching frequency and C
is the output capacitor.
OUT
If using electrolytic capacitors then:
V
= I*ESR
(EQ. 12)
OUTripple
Loop Compensation Design
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in V if the load is suddenly
The ISL85402 uses constant frequency peak current mode
control architecture to achieve fast loop transient response. An
accurate current sensing pilot device in parallel with the upper
MOSFET is used for peak current control signal and overcurrent
protection. The inductor is not considered as a state variable
since its peak current is constant, and the system becomes
single order system. It is much easier to design the compensator
to stabilize the loop compared with voltage mode control. Peak
current mode control has inherent input voltage feed-forward
function to achieve good line regulation. Figure 29 shows the
small signal model of a buck regulator.
OUT
removed. In this case, energy stored in the inductor will be
transferred to C causing its voltage to rise. After calculating
OUT
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. The following equation
determines the required output capacitor value in order to
achieve a desired overshoot relative to the regulated voltage.
2
I
L
*
OUT
------------------------------------------------------------------------------------
=
C
(EQ. 13)
OUT
2
2
– 1
OUTMAX OUT
V
V
V
*
OUT
where V is the relative maximum overshoot
/V
OUTMAX OUT
allowed during the removal of the load.
^
^
^
L
R
LP
i
P
i
L
v
in
o
Input Capacitors
Depending on the system input power rail conditions, the
aluminum electrolytic type capacitor is normally needed to
provide the stable input voltage. Thus, restrict the switching
frequency pulse current in a small area over the input traces for
better EMC performance. The input capacitor should be able to
handle the RMS current from the switching power devices.
^
d
V
in
^
^
1:D
I d
V
L
in
Rc
Co
+
R
T
Ro
T (S)
i
^
d
Ceramic capacitors must be used at VIN pin of the IC and
multiple capacitors including 1µF and 0.1µF are recommended.
Place these capacitors as closely as possible to the IC.
Fm
T (S)
+
v
He(S)
Buck Output Inductor
^
v
comp
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% to
40% of total load current. The inductor value can then be
calculated using Equation 14:
-Av(S)
FIGURE 29. SMALL SIGNAL MODEL OF BUCK REGULATOR
V
– V
V
OUT
V
IN
IN
OUT
(EQ. 14)
--------------------------- ------------
L =
Fs I
FN7640 Rev 1.00
April 25, 2013
Page 17 of 22
ISL85402
If T (S)>>1, then Equation 23 can be simplified as Equation 24:
i
PWM Comparator Gain F :
m
The PWM comparator gain Fm for peak current mode control is
given by Equation 16:
S
-----------
1 +
R
+ R
A S
esr v
1
R C
o o
o
LP
---------------------------------------------------------
-------------
(EQ. 24)
L S=
,
p
v
R
S
H S
t
e
------
1 +
ˆ
d
1
(EQ. 16)
----------------
-----------------------------
p
F
=
=
m
ˆ
S + S T
s
v
e
n
comp
Equation 24 shows that the system is a single order system.
Therefore, a simple type II compensator can be easily used to
stabilize the system. A type III compensator is needed to expand
the bandwidth for current mode control in some cases.
Where, S is the slew rate of the slope compensation and S is
given by Equation 17:
e
n
V
– V
(EQ. 17)
in
o
-------------------
S
= R
n
t
L
P
where, R is the gain of the current amplifier.
t
C1
R2
R3
C3
CURRENT SAMPLING TRANSFER FUNCTION H (S):
E
In current loop, the current signal is sampled every switching
cycle. It has the following transfer function in Equation 18:
VO
VCOMP
R1
VREF
RBIAS
2
(EQ. 18)
S
S
------ -------------
+
H S=
+ 1
e
2
n
Q
n
n
2
--
Q
= – = f
n
n
s
where, Q and are given by
n
n
FIGURE 30. TYPE III COMPENSATOR
Power Stage Transfer Functions
A type III compensator with 2 zeros and 1 pole is recommended
for this part, as shown in Figure 30. Its transfer function is
expressed as Equation 25:
Transfer function F (S) from control to output voltage is:
1
S
-----------
1 +
ˆ
v
esr
o
(EQ. 19)
-----
ˆ
--------------------------------------
F S =
= V
S
S
1
in
2
------------
------------
1 +
1 +
d
S
S
ˆ
v
------ -------------
+
+ 1
(EQ. 25)
1
comp
cz1
cz2
2
o
---------------- ----------------- --------------------------------------------------------
Q
A S=
=
o
p
v
ˆ
SR C
S
v
1
O
---------
1
1 +
cp
C
1
1
o
------------
----------------
=
,Q R ----- , =
Where,
esr
p
o
o
R C
L
L C
c
o
P
P
o
where,
Transfer function F (S) from control to inductor current is given
2
by Equation 20:
S
1
1
1
-------------
--------------------------------
-------------
=
,
=
=
cz1
cz2
cp
R C
R + R C
R C
3 3
2
1
1
3
3
-----
1 +
ˆ
V
I
(EQ. 20)
o
in
z
----
ˆ
---------------------- --------------------------------------
F S =
=
2
2
R
+ R
LP
d
o
Compensator design goal:
S
S
------ -------------
+
+ 1
1
4
1
10
2
Q
-- ------
to
o
p
f
Loop bandwidth f :
c
s
o
Gain margin: >10dB
Phase margin: 45°
1
-------------
=
where
.
z
R C
o
o
Current loop gain T (S) is expressed as Equation 21:
i
The compensator design procedure is as follows:
(EQ. 21)
T S = R F F SH S
i
t
m
2
e
1. Position CZ2 and CP to derive R and C .
3
3
Put the compensator zero CZ2 at (1 to 3)/(R C )
The voltage loop gain with open current loop is expressed in
Equation 22:
o o
(EQ. 26)
3
-------------
=
cz2
R C
o
o
T S = KF F SA S
(EQ. 22)
v
m
1
v
Put the compensator pole CP at ESR zero or 0.35 to 0.5 times
of switching frequency, whichever is lower. In all-ceramic-cap
design, the ESR zero is normally higher than half of the switching
frequency. R and C can be derived as following:
The Voltage loop gain with current loop closed is given by
Equation 23:
T S
3
3
v
(EQ. 23)
----------------------
L S =
1
v
1 + T S
--------------------
Case A: ESR zero
less than (0.35 to 0.5)f
s
i
2R C
c
o
FN7640 Rev 1.00
April 25, 2013
Page 18 of 22
ISL85402
R C – 3R C
c o
(EQ. 27)
(EQ. 28)
o
o
------------------------------------
C
=
=
3
3R
1
3R R
c
1
----------------------
R
3
R
– 3R
o
c
1
--------------------
Case B: ESR zero
larger than (0.35 to 0.5)f
s
2R C
c
o
0.33R C f – 0.46
(EQ. 29)
(EQ. 30)
o
f R
o s
------------------------------------------------
C
=
=
3
s
1
R
1
----------------------------------------
0.73R C f – 1
R
3
o
o s
2. Derive R2 and C1.
The loop gain L (S) at cross over frequency of f has unity gain.
v
c
Therefore, C is determined by Equation 31.
1
R + R C
3
(EQ. 31)
1
3
--------------------------------
=
C
1
2f R R C
c
t 1
o
The compensator zero CZ1 can boost the phase margin and
bandwidth. To put CZ1 at 2 times of cross cover frequency f is a
c
good start point. It can be adjusted according to specific design.
R1 can be derived from Equation 32.
(EQ. 32)
1
------------------
R
=
2
4f C
c
1
Example: V = 12V, V = 5V, I = 2A, fs = 500kHz,
in
o
o
C = 60µF/3m, L = 10µH, R = 0.20V/A, f = 50kHz, R1=105k,
o
t
c
R
= 20k.
BIAS
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramic, use Equation 29 and 30 to derive R3
to be 20k and C3 to be 470pF.
FIGURE 31. SIMULATED LOOP BODE PLOT
Then use Equation 31 and 32 to calculate C1 to be 180pF and
R2 to be 12.7k. Select 150pF for C1 and 15k for R2.
Boost Inductor
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole.
Besides the need to sustain the current ripple to be within a
certain range (30% to 50%), the boost inductor current at its
soft-start is a more important perspective to be considered in
selection of the boost inductor. Each time the boost starts up,
there is a fixed 500µs soft-start time when the duty cycle
Figure 31 shows the simulated bode plot of the loop. It is shown
that it has 26kHz loop bandwidth with 70° phase margin and -28
dB gain margin.
increases linearly from t
*Fs to ~50%. Before and after
MIN(ON)
boost start-up, the boost output voltage will jump from
to voltage (V + V ). The design target
Note in applications where the PFM mode is desired especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended at PFM applications.
V
IN_BOOST
IN_BOOST
OUT_BUCK
in boost soft-start is to ensure the boost input current is
sustained to minimum but capable to charge the boost output
voltage to have a voltage step equaling to V
inductor will block the inductor current to increase and not high
enough to be able to charge the output capacitor to the final
. A big
OUT_BUCK
steady state value (V
+ V ) within 500µs. A
IN_BOOST
OUT_BUCK
6.8µH inductor is a good starting point for its selection in design.
The boost inductor current at start-up must be checked by
oscilloscope to ensure it is under acceptable range. It is
suggested to run the iSim model, which is available on the
internet to assist in designing the proper inductor value.
FN7640 Rev 1.00
April 25, 2013
Page 19 of 22
ISL85402
Boost Output Capacitor
Based on the same theory in boost start-up previously described
in the boost inductor selection, a large capacitor at boost output
will cause high in-rush current at boost PWM start-up. 22µF is a
good choice for applications with a buck output voltage less than
10V. Also some minimum amount of capacitance has to be used
in boost output to keep the system stable. It is suggested to run
the iSim model, which is available on the internet to assist in
designing the proper capacitor value.
Layout Suggestions
1. Place the input ceramic capacitors as closely as possible to
the IC VIN pin and power ground connecting to the power
MOSFET or Diode. Keep this loop (input ceramic capacitor, IC
VIN pin and MOSFET/Diode) as tiny as possible to achieve the
least voltage spikes induced by the trace parasitic
inductance.
2. Place the input aluminum capacitors closely as possible to
the IC VIN pin.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors close to
the power stage components as well.
5. Place vias (≥9) in the bottom pad of the IC. The bottom pad
should be placed in ground copper plane with an area as large
as possible in multiple layers to effectively reduce the thermal
impedance.
6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin
(the closest place to the IC). Put multiple vias (≥3) close to the
ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using via in the LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the place to be
strictly regulated.
10. Place all the peripheral control components close to the IC.
FIGURE 32. PCB VIA PATTERN
FN7640 Rev 1.00
April 25, 2013
Page 20 of 22
ISL85402
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest revision.
DATE
REVISION
FN7640.1
CHANGE
April 25, 2012
1. Expanded the maximum temperature from 85°C to 105°C for the electrical characteristics and Ordering
Information.
2. Added application design guide for selection of inductor and capacitor and loop compensation.
3. Added typical electrical specification of EN pull-up current, synchronization.
4. Added boost-buck efficiency curve and AUVVCC switchover description.
5. Under "Output Voltage" description, corrected "(1/Fs tMINOFF)" To " (1 - Fs * tMIN(OFF))".
6. Under "Boost Converter Operation", corrected "(VIN*IIN = VOUT*IOUT*Efficiency)" to "(VIN*IIN =
VOUT*IOUT/Efficiency)".
7. Added recommendation of the maximum programmable OC threshold to be 4.18A(TYP) with 71.5k RLIM.
8. Corrected sentence in first paragraph on page 1 from: “ The ISL85402 supports a wide input range of 3V to
40V in buck mode.“ to “ The ISL85402 supports a wide input range of 3V to 36V in buck mode.“
9. Removed following sentence from last paragraph of “Power Stage Transfer Functions” on page 19: “Deleted
following sentence from last paragraph of “Power Stage Transfer Functions” on page 19: “A capacitor (<1nF)
at the FB pin to ground also helps proper PFM mode operation".
September 29, 2011
FN7640.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
© Copyright Intersil Americas LLC 2011-2013. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7640 Rev 1.00
April 25, 2013
Page 21 of 22
ISL85402
Package Outline Drawing
L20.4x4C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/06
4X
2.0
4.00
0.50
16X
A
6
B
16
20
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
1
15
2 .70 ± 0 . 15
11
5
(4X)
0.15
6
10
0.10 M
C
A B
4
20X 0.25 +0.05 / -0.07
20X 0.4 ± 0.10
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
0 . 90 ± 0 . 1
C
BASE PLANE
( 3. 8 TYP )
(
SEATING PLANE
0.08 C
2. 70 )
( 20X 0 . 5 )
SIDE VIEW
( 20X 0 . 25 )
( 20X 0 . 6)
5
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN7640 Rev 1.00
April 25, 2013
Page 22 of 22
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