ISL85410FRZ-T_技术文档

DATASHEET

ISL85410

Wide V 1A Synchronous Buck Regulator

IN

FN8375

Rev.8.00

Mar 15, 2019

The ISL85410 is a 1A synchronous buck regulator with an

input range of 3V to 40V. It provides an easy-to-use, high

efficiency low BOM count solution for a variety of applications.

Features

• Wide input voltage range: 3V to 40V

• Synchronous operation for high efficiency

• No compensation required

The ISL85410 integrates both high-side and low-side NMOS

FETs and features a PFM mode for improved efficiency at light

loads. This feature can be disabled if a forced PWM mode is

needed. The ISL85410 switches at a default frequency of

500kHz; however, it can also be programmed using an

external resistor from 300kHz to 2MHz. The ISL85410 has the

ability to use internal or external compensation. By integrating

both NMOS devices and providing internal configuration

options, minimal external components are required, which

reduces BOM count and complexity of design.

• Integrated high-side and low-side NMOS devices

• Selectable PFM or forced PWM mode at light loads

• Internal fixed frequency (500kHz) or adjustable switching

frequency (300kHz to 2MHz)

• Continuous output current up to 1A

• Internal or external soft-start

• Minimal external components required

• Power-good and enable functions available

With a wide V range and reduced BOM, the ISL85410

IN

provides an easy to implement design solution for a variety of

applications while giving superior performance. The ISL85410

provides a very robust design for high-voltage industrial

applications and an efficient solution for battery powered

applications.

Applications

• Industrial control

• Medical devices

The ISL85410 is available in a small Pb-free 4mmx3mm DFN

plastic package with a full-range industrial temperature of

-40°C to +125°C.

• Portable instrumentation

• Distributed power supplies

• Cloud infrastructure

Related Literature

For a full list of related documents, visit our website:

• ISL85410 device page

100

95

90

85

1

2

12

11

SS

FS

80

COMP

SYNC

BOOT

VIN

R₂

R₃

C_FB

V

= 15V

= 5V

IN

V

75

70

65

60

55

50

IN

10

9

3

4

FB

C_BOOT

100nF

GND

V

= 24V

IN

C_VIN

VCC

C_VCC

1µF

10µF

5

6

V_OUT

PHASE

PGND

V

= 12V

IN

PG

EN

L₁

22µH

C_OUT

10µF

V

= 33V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

INTERNAL DEFAULT PARAMETER SELECTION

FIGURE 2. EFFICIENCY vs LOAD, PFM, V

= 3.3V

FIGURE 1. TYPICAL APPLICATION

OUT

FN8375 Rev.8.00

Mar 15, 2019

Page 1 of 22

ISL85410

Table of Contents

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Efficiency Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Light Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Negative Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Boot Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Minimum On/Off-Time Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FN8375 Rev.8.00

Mar 15, 2019

Page 2 of 22

ISL85410

Pin Configuration

12 LD 4x3 DFN

TOP VIEW

12

11

10

9

FS

1

2

3

4

5

6

SS

SYNC

BOOT

VIN

COMP

FB

GND

VCC

PG

EN

PHASE

PGND

8

7

Pin Descriptions

PIN NUMBER

SYMBOL

PIN DESCRIPTION

1

SS

Controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground determines the

output ramp rate. See “Soft-Start” on page 14 for soft-start details. If the SS pin is tied to VCC, an internal

soft-start of 2ms is used.

2

SYNC

Synchronization and light load operational mode selection input. Connect to logic high or VCC for PWM

mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose

PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger.

The sync source must be higher than the programmed IC frequency. An internal 5MΩ pull-down resistor

prevents an undefined logic state if SYNC is left floating.

3

4

BOOT

VIN

Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the

necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this

pin to PHASE.

The input supply for the power stage of the regulator and the source for the internal linear bias regulator.

Place a minimum of 4.7µF ceramic capacitance from VIN to GND and close to the IC for decoupling.

5

6

7

PHASE

PGND

EN

Switch node output. It connects the switching FETs with the external output inductor.

Power ground connection. Connect directly to the system GND plane.

Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the

voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not

connect the EN pin to VCC because the LDO is controlled by EN voltage.

8

PG

Open-drain, power-good output that is pulled to ground when the output voltage is below regulation limits

or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.

9

VCC

FB

Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.

10

Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the

output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In

addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.

11

COMP

COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used. When only

an RC network is connected from COMP to GND, external compensation is used. See “Loop Compensation

Design” on page 17 for more details.

12

FS

Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for

adjustable frequency from 300kHz to 2MHz.

EPAD

GND

Signal ground connections. Connect to the application board GND plane with at least five vias. All voltage

levels are measured with respect to this pin. The EPAD MUST NOT float.

FN8375 Rev.8.00

Mar 15, 2019

Page 3 of 22

ISL85410

Typical Application Schematics

1

12

11

SS

FS

2

COMP

SYNC

R₂

R₃

C_FB

10

9

3

BOOT

FB

C_BOOT

100nF

GND

4

VIN

VCC

C_VIN

10µF

C_VCC

1µF

V_OUT

5

6

PHASE

PGND

PG

EN

L₁

22µH

C_OUT

10µF

FIGURE 3. INTERNAL DEFAULT PARAMETER SELECTION

12

1

2

SS

FS

R_FS

C_SS

11

10

9

COMP

SYNC

BOOT

VIN

R₂

R₃

C_FB

3

4

FB

C_BOOT

100nF

GND

VCC

C_VIN

10µF

C_VCC

1µF

5

6

V_OUT

PHASE

PGND

PG

EN

L₁

22µH

C_OUT

10µF

R_COMP

C_COMP

FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION

TABLE 1. EXTERNAL COMPONENT SELECTION

V

(V)

L

(µH)

C

(µF)

R

(kΩ)

R

(kΩ)

C

(pF)

R

(kΩ)

R

(kΩ)

C

(pF)

OUT

1

OUT

2

3

FB

FS

COMP

12

22

2 x 22

90.9

4.75

12.4

20

22

115

150

100

70

470

5

22

12

47 + 22

27

DNP (Note 1)

470

3.3

2.5

1.8

28.7

45.5

NOTE:

1. Connect FS to V

.

CC

FN8375 Rev.8.00

Mar 15, 2019

Page 4 of 22

ISL85410

Functional Block Diagram

PG

SS

EN

VIN

FB

POWER-

GOOD

5M

VCC

LOGIC

BIAS

LDO

EN/SOFT-

START

BOOT

FB

FS

FAULT

LOGIC

500mV/A

600mV VREF

CURRENT SENSE

GATE

DRIVE

AND

OSCILLATOR

PFM

PWM

PWM/PFM

SELECT LOGIC

s

Q

PHASE

PGND

FB

DEADTIME

R

5M

CURRENT

SET

SYNC

ZERO CURRENT

DETECTION

450mV/T SLOPE

COMPENSATION

(PWM ONLY)

150k

54pF

INTERNAL

COMPENSATION

PACKAGE

PADDLE

INTERNAL = 50µA/V

EXTERNAL = 230µA/V

COMP

GND

Ordering Information

PART NUMBER

(Notes 3, 4)

PART

MARKING

TEMP. RANGE

(°C)

TAPE AND REEL

(Units) (Note 2)

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

ISL85410FRZ

5410

-40 to +125

-

12 Ld DFN

L12.4x3

ISL85410FRZ-T

ISL85410FRZ -T7A

ISL85410EVAL1Z

ISL85410DEMO1Z

NOTES:

6k

12 Ld DFN

L12.4x3

250

Evaluation Board

Demonstration Board

2. See TB347 for details about reel specifications.

3. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate

plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. For Moisture Sensitivity Level (MSL), see the ISL85410 device page. For more information about MSL, see TB363.

FN8375 Rev.8.00

Mar 15, 2019

Page 5 of 22

ISL85410

Absolute Maximum Ratings

Thermal Information

VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V

PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V (DC)

PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +44V (20ns)

EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V

BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V

COMP, FS, PG, SYNC, SS, VCC to GND . . . . . . . . . . . . . . . . . . -0.3V to +5.9V

FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V

ESD Rating

Thermal Resistance

DFN Package (Notes 5, 6) . . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493



(°C/W)

42



(°C/W)

4.5

JA

JC

Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 2kV

Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .1.5kV

Latch-Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . 100mA

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +40V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5.  is measured in free air with the component mounted on a high-effective thermal conductivity test board with “direct attach” features. See TB379

JA

for details.

6. For  , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications T = -40°C to +125°C, V = 3V to 40V, unless otherwise noted. Typical values are at T = +25°C. Boldface

A

IN

A

limits apply across the junction temperature range, -40°C to +125°C

MIN

MAX

PARAMETER

SUPPLY VOLTAGE

SYMBOL

TEST CONDITIONS

(Note 9)

TYP

(Note 9)

UNIT

V

Voltage Range

V

I

3

40

V

µA

V

IN

CC

IN

Quiescent Supply Current

Shutdown Supply Current

Voltage

V

= 0.7V, SYNC = 0V, f

= V

SW CC

80

2

Q

FB

EN = 0V, V = 40V (Note 7)

I

4

SD

IN

V

= 6V, I

IN OUT

= 0 to 10mA

4.5

5.1

5.7

CC

POWER-ON RESET

POR Threshold

V

Rising edge

Falling edge

2.75

2.6

2.95

V

CC

2.35

OSCILLATOR

Nominal Switching Frequency

f

FS pin = V

CC

430

240

500

300

2000

150

90

570

360

kHz

ns

SW

Resistor from the FS pin to GND = 340kΩ

Resistor from the FS pin to GND = 32.4kΩ

Minimum Off-Time

t

V

= 3V

MIN_OFF

IN

(Note 10)

= 100kΩ

Minimum On-Time

t

ns

MIN_ON

FS Voltage

V

R

0.39

300

100

0.4

0.41

V

FS

SYNC

FS

Synchronization Frequency

SYNC Pulse Width

2000

kHz

ns

ERROR AMPLIFIER

Error Amplifier Transconductance Gain

g

External compensation

Internal compensation

165

230

50

295

µA/V

nA

m

FB Leakage Current

Current Sense Amplifier Gain

FB Voltage

V

= 0.6V

1

150

0.54

FB

R

0.46

0.590

0.5

V/A

V

T

= -40°C to +85°C

= -40°C to +125°C

0.599

0.606

0.607

A

T

V

A

FN8375 Rev.8.00

Mar 15, 2019

Page 6 of 22

ISL85410

Electrical Specifications T = -40°C to +125°C, V = 3V to 40V, unless otherwise noted. Typical values are at T = +25°C. Boldface

A

IN

A

limits apply across the junction temperature range, -40°C to +125°C (Continued)

MIN

MAX

PARAMETER

POWER-GOOD

SYMBOL

TEST CONDITIONS

(Note 9)

TYP

(Note 9)

UNIT

Lower PG Threshold - VFB Rising

Lower PG Threshold - VFB Falling

Upper PG Threshold - VFB Rising

Upper PG Threshold - VFB Falling

PG Propagation Delay

90

86

94

%

V

82.5

107

116.5

112

10

120

Percentage of the soft-start time

PG Low Voltage

I

= 3mA, EN = V , V = 0V

CC FB

0.05

0.3

SINK

TRACKING AND SOFT-START

Soft-Start Charging Current

Internal Soft-Start Ramp Time

FAULT PROTECTION

I_SS

4.2

1.5

5.5

2.4

6.5

3.4

µA

EN/SS = V

CC

ms

Thermal Shutdown Temperature

T

Rising threshold

Hysteresis

150

20

°C

SD

T

HYS

Current Limit Blanking Time

t

17

Clock

OCON

pulses

Overcurrent and Auto Restart Period

Positive Peak Current Limit

PFM Peak Current Limit

Zero Cross Threshold

Negative Current Limit

POWER MOSFET

t

8

SS cycle

OCOFF

IPLIMIT

(Note 8)

1.3

1.5

0.4

15

1.7

0.5

A

I

0.34

PK_PFM

mA

A

INLIMIT

-0.67

-0.6

-0.53

High-Side

R

I

= 100mA, V = 5V

CC

250

90

350

130

300

mΩ

nA

HDS

PHASE

Low-Side

R

= 100mA, V = 5V

CC

LDS

PHASE

PHASE Leakage Current

PHASE Rise Time

EN = PHASE = 0V

= 40V

t

V

10

ns

RISE

IN

EN/SYNC

Input Threshold

Falling edge, logic low

Rising edge, logic high

EN = 0V/40V

0.4

1

V

1.2

1.4

0.5

V

EN Logic Input Leakage Current

SYNC Logic Input Leakage Current

-0.5

µA

nA

µA

SYNC = 0V

10

100

1.55

SYNC = 5V

1.0

NOTES:

7. Test condition: V = 40V, FB forced above regulation point (0.6V), switching and power MOSFET gate charging current not included.

IN

8. Established by both current sense amplifier gain test and current sense amplifier output test at I = 0A.

L

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

10. Minimum on-time required to maintain loop stability.

FN8375 Rev.8.00

Mar 15, 2019

Page 7 of 22

ISL85410

Efficiency Curves

f

= 500kHz, T = +25°C

SW A

100

95

90

85

80

75

70

65

60

55

50

95

90

V

= 24V

V

= 24V

IN

V

= 15V

IN

V

= 15V

85

IN

80

V

= 33V

IN

75

70

65

60

55

50

V

= 33V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 5. EFFICIENCY vs LOAD, PFM, V

= 12V

FIGURE 6. EFFICIENCY vs LOAD, PWM, V

= 12V

OUT

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

V

= 12V

V

= 12V

IN

V

= 6V

V

= 6V

IN

V

= 24V

V

= 15V

V

= 24V

V

= 15V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 8. EFFICIENCY vs LOAD, PWM, V

= 5V, L = 30µH

1

FIGURE 7. EFFICIENCY vs LOAD, PFM, V

= 5V, L = 30µH

1

OUT

100

95

V

= 12V

IN

95

90

85

80

75

70

65

60

55

50

V

= 5V

IN

90

85

80

V

= 15V

V

= 15V

= 5V

IN

V

= 33V

75

70

65

60

55

50

IN

V

= 24V

IN

V

= 24V

IN

V

= 12V

IN

V

= 33V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 9. EFFICIENCY vs LOAD, PFM, V

OUT

= 3.3V

FIGURE 10. EFFICIENCY vs LOAD, PWM, V = 3.3V

OUT

FN8375 Rev.8.00

Mar 15, 2019

Page 8 of 22

ISL85410

Efficiency Curves

f

= 500kHz, T = +25°C (Continued)

SW A

100

95

90

85

80

75

70

65

60

55

50

100

V

= 12V

IN

95

V

= 12V

IN

V

= 5V

90

85

80

75

70

65

60

55

50

IN

V

= 5V

IN

V

= 15V

IN

V

= 15V

V

= 33V

V

= 33V

IN

V

= 24V

IN

V

= 24V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 12. EFFICIENCY vs LOAD, PWM, V

= 1.8V

FIGURE 11. EFFICIENCY vs LOAD, PFM, V

OUT

= 1.8V

OUT

5.004

5.003

5.002

5.001

5.000

4.999

4.998

4.997

4.996

4.995

4.994

4.993

5.030

5.025

5.020

5.015

5.010

5.005

5.000

4.995

4.990

V

= 6V

IN

V

= 6V

IN

V

= 12V

IN

V

= 12V

IN

V

= 15V

IN

V

= 15V

IN

V

= 24V

IN

V

= 24V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 14. V

REGULATION vs LOAD, PFM, V

OUT

= 5V, L = 30µH

1

FIGURE 13. V

REGULATION vs LOAD, PWM, V = 5V, L = 30µH

OUT 1

OUT

3.345

3.340

3.335

3.330

3.325

3.320

3.315

3.326

3.325

3.324

3.323

3.322

3.321

3.320

3.319

3.318

3.317

V

= 5V

IN

V

= 5V

IN

V

= 12V

IN

V

= 12V

IN

V

= 15V

V

= 33V

IN

V

= 15V

IN

V

= 24V

IN

V

= 33V

IN

V

= 24V

IN

3.316

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 16. V

OUT

REGULATION vs LOAD, PFM, V

= 3.3V

OUT

FIGURE 15. V

OUT

REGULATION vs LOAD, PWM, V

= 3.3V

OUT

FN8375 Rev.8.00

Mar 15, 2019

Page 9 of 22

ISL85410

Efficiency Curves

f

= 500kHz, T = +25°C (Continued)

SW A

1.810

1.818

1.816

1.814

1.812

1.810

1.808

1.806

1.804

1.802

1.800

V

= 5V

V

= 15V

IN

1.809

1.808

1.807

1.806

1.805

1.804

1.803

1.802

1.801

1.800

V

= 5V

IN

V

= 12V

IN

V

= 12V

IN

V

= 15V

IN

V

= 33V

V

= 24V

IN

V

= 33V

V

= 24V

IN

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

OUTPUT LOAD (A)

FIGURE 17. V

OUT

REGULATION vs LOAD, PWM, V

OUT

= 1.8V

FIGURE 18. V

REGULATION vs LOAD, PFM, V

= 1.8V

OUT

Measurements

f

= 500kHz, V = 24V, V = 3.3V, T = +25°C

IN OUT A

SW

LX 20V/DIV

V

2V/DIV

OUT

V

2V/DIV

OUT

EN 20V/DIV

PG 2V/DIV

EN 20V/DIV

PG 2V/DIV

5ms/DIV

FIGURE 19. START-UP AT NO LOAD, PFM

FIGURE 20. START-UP AT NO LOAD, PWM

LX 20V/DIV

V

2V/DIV

V

2V/DIV

OUT

EN 20V/DIV

PG 2V/DIV

EN 20V/DIV

PG 2V/DIV

100ms/DIV

FIGURE 22. SHUTDOWN AT NO LOAD, PWM

FIGURE 21. SHUTDOWN AT NO LOAD, PFM

FN8375 Rev.8.00

Mar 15, 2019

Page 10 of 22

ISL85410

Measurements

f

= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)

IN OUT A

SW

LX 20V/DIV

V

2V/DIV

OUT

V

2V/DIV

OUT

I

500mA/DIV

L

I

500mA/DIV

L

PG 2V/DIV

200µs/DIV

5ms/DIV

FIGURE 23. START-UP AT 1A, PWM

FIGURE 24. SHUTDOWN AT 1A, PWM

LX 20V/DIV

V

2V/DIV

OUT

V

2V/DIV

OUT

I

500mA/DIV

L

I

500mA/DIV

L

PG 2V/DIV

200µs/DIV

5ms/DIV

FIGURE 25. START-UP AT 1A, PFM

FIGURE 26. SHUTDOWN AT 1A, PFM

LX 5V/DIV

5ns/DIV

FIGURE 27. JITTER AT NO LOAD, PWM

FIGURE 28. JITTER AT 1A LOAD, PWM

FN8375 Rev.8.00

Mar 15, 2019

Page 11 of 22

ISL85410

Measurements

f

= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)

IN OUT A

SW

LX 20V/DIV

V

20mV/DIV

OUT

V

20mV/DIV

20mA/DIV

OUT

I

20mA/DIV

L

I

L

1µs/DIV

10ms/DIV

FIGURE 30. STEADY STATE AT NO LOAD, PWM

FIGURE 29. STEADY STATE AT NO LOAD, PFM

LX 20V/DIV

V

20mV/DIV

OUT

V

50mV/DIV

OUT

I

1A/DIV

L

I

200mA/DIV

L

1µs/DIV

10µs/DIV

FIGURE 31. STEADY STATE AT 1A, PWM

FIGURE 32. LIGHT LOAD OPERATION AT 20mA, PFM

LX 20V/DIV

V

100mV/DIV

OUT

V

10mV/DIV

OUT

I

200mA/DIV

L

I

1A/DIV

L

1µs/DIV

200µs/DIV

FIGURE 33. LIGHT LOAD OPERATION AT 20mA, PWM

FIGURE 34. LOAD TRANSIENT, PFM

FN8375 Rev.8.00

Mar 15, 2019

Page 12 of 22

ISL85410

Measurements

f

= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)

IN OUT A

SW

LX 20V/DIV

V

100mV/DIV

OUT

V

20mV/DIV

OUT

I

1A/DIV

I

1A/DIV

L

200µs/DIV

10µs/DIV

FIGURE 35. LOAD TRANSIENT, PWM

FIGURE 36. PFM TO PWM TRANSITION

LX 20V/DIV

V

2V/DIV

OUT

V

2V/DIV

OUT

I

1A/DIV

L

I

1A/DIV

L

PG 2V/DIV

10ms/DIV

50µs/DIV

FIGURE 38. OVERCURRENT PROTECTION HICCUP, PWM

FIGURE 37. OVERCURRENT PROTECTION, PWM

LX 20V/DIV

V

5V/DIV

OUT

SYNC 2V/DIV

I

1A/DIV

L

PG 2V/DIV

200ns/DIV

20µs/DIV

FIGURE 39. SYNC AT 1A LOAD, PWM

FIGURE 40. NEGATIVE CURRENT LIMIT, PWM

FN8375 Rev.8.00

Mar 15, 2019

Page 13 of 22

ISL85410

Measurements

f

= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)

IN OUT A

SW

LX 20V/DIV

V

5V/DIV

OUT

V

2V/DIV

OUT

I

500mA/DIV

L

PG 2V/DIV

200µs/DIV

500µs/DIV

FIGURE 42. OVER-TEMPERATURE PROTECTION, PWM

FIGURE 41. NEGATIVE CURRENT LIMIT RECOVERY, PWM

Power-Good

Detailed Description

PG is the open-drain output of a window comparator that

continuously monitors the buck regulator output voltage vrom

the FB pin. PG is actively held low when EN is low and during the

buck regulator soft-start period. After the soft-start period

completes, PG becomes high impedance if the FB pin is within

the range specified in the “Electrical Specifications” on page 7. If

FB exits the specified window, PG is pulled low until FB returns.

Over-temperature faults also force PG low until the fault

condition is cleared by an attempt to soft-start. There is an

internal 5MΩ internal pull-up resistor.

The ISL85410 combines a synchronous buck PWM controller

with integrated power switches. The buck controller drives

internal high-side and low-side N-channel MOSFETs to deliver

load current up to 1A. The buck regulator can operate from an

unregulated DC source, such as a battery, with a voltage ranging

from +3V to +40V. An internal LDO provides bias to the low

voltage portions of the IC.

Peak current mode control is used to simplify feedback loop

compensation and reject input voltage variation. User selectable

internal feedback loop compensation further simplifies design.

The ISL85410 switches at a default 500kHz.

PWM Control Scheme

The ISL85410 employs peak current-mode pulse-width

The buck regulator is equipped with an internal current sensing

circuit and the peak current limit threshold is typically set at

1.5A.

modulation (PWM) control for fast transient response and

pulse-by-pulse current limiting, as shown in the “Functional Block

Diagram” on page 5. The current loop consists of the current

sensing circuit, slope compensation ramp, PWM comparator,

oscillator, and latch. Current sense trans-resistance is typically

500mV/A and slope compensation rate, Se, is typically 450mV/T

where T is the switching cycle period. The control reference for the

Power-On Reset

The ISL85410 automatically initializes upon receipt of the input

power supply and continually monitors the EN pin state. If EN is

held below its logic rising threshold, the IC is held in shutdown

current loop comes from the error amplifier’s output (V

).

COMP

and consumes typically 2µA from the V supply. If EN exceeds

IN

A PWM cycle begins when a clock pulse sets the PWM latch and the

upper FET is turned on. Current begins to ramp up in the upper FET

its logic rising threshold, the regulator enables the bias LDO and

begins to monitor the VCC pin voltage. When the VCC pin voltage

clears its rising POR threshold, the controller initializes the

switching regulator circuits. If VCC never clears the rising POR

threshold, the controller does not allow the switching regulator to

operate. If VCC falls below its falling POR threshold while the

switching regulator is operating, the switching regulator is shut

down until VCC returns.

and inductor. This current is sensed (V ), converted to a voltage

CSA

and summed with the slope compensation signal. This combined

signal is compared to V

and when the signal is equal to V ,

COMP

the latch is reset. Upon latch reset, the upper FET is turned off and

the lower FET turned on allowing current to ramp down in the

inductor. The lower FET remains on until the clock initiates another

PWM cycle. Figure 44 shows the typical operating waveforms during

the PWM operation. The dotted lines illustrate the sum of the

current sense and slope compensation signal.

Soft-Start

To avoid large in-rush current, V

is slowly increased at start-up

OUT

Output voltage is regulated as the error amplifier varies VCOMP

and therefore varies the output inductor current. The error

amplifier is a transconductance type and its output (COMP) is

terminated with a series RC network to GND. This termination is

internal (150k/54pF) if the COMP pin is tied to VCC. Additionally,

the transconductance for COMP = VCC is 50µA/V vs 230µA/V for

external RC connection. Its noninverting input is internally

connected to a 600mV reference voltage and its inverting input is

connected to the output voltage from the FB pin and its

associated divider network.

to its final regulated value. Soft-start time is determined by the

SS pin connection. If SS is pulled to VCC, an internal 2ms timer is

selected for soft-start. For other soft-start times, connect a

capacitor from SS to GND. In this case, a 5.5µA current pulls up

the SS voltage and the FB pin follows this ramp until it reaches

the 600mV reference level. The soft-start time for this case is

described by Equation 1:

(EQ. 1)



Timems = CnF 0.109

FN8375 Rev.8.00

Mar 15, 2019

Page 14 of 22

ISL85410

PWM

DCM

PULSE SKIP

DCM

PWM

CLOCK

8 CYCLES

I

L

LOAD CURRENT

0

V

OUT

FIGURE 43. DCM MODE OPERATION WAVEFORMS

limit, V

OUT

begins to decline. A second comparator signals an FB

voltage 2% lower than the 600mV reference and forces the

converter to return to PWM operation.

V

COMP

V

CSA

Output Voltage Selection

The regulator output voltage is programmed using an external

DUTY

CYCLE

resistor divider to scale V relative to the internal reference

OUT

voltage. The scaled voltage is applied to the inverting input of the

error amplifier; see Figure 45.

I

L

The output voltage programming resistor, R , depends on the

3

value chosen for the feedback resistor, R , and the needed

2

V

OUT

output voltage, V , of the regulator. Equation 3 describes the

OUT

relationship between V

and resistor values.

OUT

R x0.6V

2

FIGURE 44. PWM OPERATION WAVEFORMS

----------------------------------

=

(EQ. 3)

R

3

V

– 0.6V

OUT

Light Load Operation

At light loads, converter efficiency can be improved by enabling

variable frequency operation (PFM). Connecting the SYNC pin to

GND allows the controller to choose such operation

automatically when the load current is low. Figure 43 shows the

DCM operation. The IC enters DCM mode when eight consecutive

cycles of inductor current crossing zero are detected. This

corresponds to a load current equal to 1/2 the peak-to-peak

inductor ripple current and set by Equation 2:

If the needed output voltage is 0.6V, then R is left unpopulated

3

and R is 0Ω.

2

V

OUT

R

2

FB

-

+

EA

3

0.6V

REFERENCE

V

1 – D

(EQ. 2)

OUT

----------------------------------

=

I

OUT

2L f

SW

FIGURE 45. EXTERNAL RESISTOR DIVIDER

where D = duty cycle, f

= switching frequency, L = inductor

SW

= output loading current, V

value, I

= output voltage.

OUT

Protection Features

The ISL85410 is protected from overcurrent, negative

overcurrent and over-temperature. The protection circuits

operate automatically.

While operating in PFM mode, the regulator controls the output

voltage with a simple comparator and pulsed FET current. A

comparator indicates the point at which FB is equal to the

600mV reference, at which time the regulator begins providing

pulses of current until FB is moved above the 600mV reference

by 1%. The current pulses are approximately 400mA and are

issued at a frequency equal to the converter’s programmed PWM

operating frequency.

Overcurrent Protection

During PWM on-time, current through the upper FET is monitored

and compared to a nominal 1.5A peak overcurrent limit. If

current reaches the limit, the upper FET is turned off until the

Due to the pulsed current nature of PFM mode, the converter can

supply limited current to the load. If load current rises beyond the

FN8375 Rev.8.00

Mar 15, 2019

Page 15 of 22

ISL85410

next switching cycle. In this way, FET peak current is always well

limited.

Application Guidelines

Simplifying the Design

If the overcurrent condition persists for 17 sequential clock

cycles, the regulator begins its hiccup sequence. In this case,

both FETs are turned off and PG is pulled low. This condition is

maintained for eight soft-start periods, after which the regulator

attempts a normal soft-start.

While the ISL85410 offers user programmed options for most

parameters, the easiest implementation with fewest

components involves selecting internal settings for SS, COMP,

and FS. Table 1 on page 4 provides component value selections

for a variety of output voltages and allows you to implement

solutions with a minimum of effort.

If output fault persists, the regulator repeats the hiccup

sequence indefinitely. There is no danger even if the output is

shorted during soft-start.

Operating Frequency

The ISL85410 operates at a default switching frequency of

ths

If V

OUT

is shorted very quickly, FB may collapse below 5/8 of

its target value before 17 cycles of overcurrent are detected. The

ISL85410 recognizes this condition and begins to lower its

switching frequency proportional to the FB pin voltage. This

adjustment ensures that the inductor current does not run away

under any circumstance (even with VOUT near 0V).

500kHz if the FS pin is tied to V . Tie a resistor from the FS pin

to GND to program the switching frequency from 300kHz to

2MHz, as shown in Equation 4.

CC



R

k = 108.75k t – 0.2s  1s

(EQ. 4)

FS

Where:

Negative Current Limit

t is the switching period in µs.

If an external source somehow drives current into V , the

OUT

controller attempts to regulate V

OUT

by reversing its inductor

400

current to absorb the externally sourced current. If the external

source is low impedance, the current may be reversed to

unacceptable levels and the controller initiates its negative current

limit protection. Similar to normal overcurrent, the negative

current protection is realized by monitoring the current through the

lower FET. When the valley point of the inductor current reaches

negative current limit, the lower FET is turned off and the upper

FET is forced on until current reaches the POSITIVE current limit or

an internal clock signal is issued. Next, the lower FET is allowed to

operate. If the current is pulled to the negative limit again on the

next cycle, the upper FET is forced on again and the current is

300

200

100

0

th

forced to 1/6 of the positive current limit. Next, the controller

turns off both FETs and waits for COMP to indicate a return to

normal operation. During this time, the controller applies a 100Ω

load from PHASE to PGND and attempts to discharge the output.

Negative current limit is a pulse-by-pulse style operation and

recovery is automatic.

250

500

750

1000

1250

(kHz)

1500

1750

2000

f

SW

FIGURE 46. R SELECTION vs f

FS

SW

Over-Temperature Protection

Over-temperature protection limits maximum junction

temperature in the ISL85410. When junction temperature (T )

exceeds +150°C, both FETs are turned off and the controller

waits for temperature to decrease by approximately 20°C.

During this time PG is pulled low. When temperature is within an

acceptable range, the controller initiates a normal soft-start

sequence. For continuous operation, do not exceed the +125°C

junction temperature rating.

Minimum On/Off-Time Limitation

Minimum on-time (t

) is the shortest duration of time that

the HS FET can be turned on and minimum off time (t ) is

MIN_ON

J

MIN_OFF

the shortest duration of time that the HS FET can be turned off.

The typical t

For a given t

is 90ns and the typical t

is 150ns.

MIN_ON

MIN_OFF

, a higher switching frequency

and t

MIN_OFF

results in a narrower range of allowed duty cycle, which

translates to a smaller allowed V range.

IN

) and switching frequency (f ),

For a given output voltage (V

OUT

SW

the maximum allowed voltage is given by (Equation 5):

Boot Undervoltage Protection

If the boot capacitor voltage falls below 1.8V, the boot

V

OUT

--------------------------------------

SW

undervoltage protection circuit turns on the lower FET for 400ns

to recharge the capacitor. This operation may arise during long

periods of no switching such as PFM no load situations. In PWM

(EQ. 5)

V

=

INmax

f

 t

MIN_ON

The minimum allowed voltage is given by (Equation 6):

operation near dropout (V near V

), the regulator can hold

IN OUT

V

the upper FET on for multiple clock cycles. To prevent the boot

capacitor from discharging, the lower FET is forced on for

approximately 200ns every 10 clock cycles.

OUT

--------------------------------------------------

(EQ. 6)

V

=

INmin

1 – f

 t

MIN_OFF

SW

FN8375 Rev.8.00

Mar 15, 2019

Page 16 of 22

ISL85410

Table 2 shows the recommended switching frequencies for the

ceramic capacitors are a very good choice in many applications

due to their reliability and extremely low ESR.

various V

to operate up to the maximum V (40V).

OUT

IN

Use the following equations to calculate the required

capacitance for ripple voltage. Additional capacitance may be

used.

TABLE 2. RECOMMENDED SWITCHING FREQUENCIES FOR VARIOUS

V

OUT

V

(V)

V

(V)

f

(kHz)

IN (max)

40

OUT

SW

For the ceramic capacitors (low ESR):

5

500

I

40

3.3

500

300

(EQ. 8)

is the

------------------------------------

V

=

OUTripple



C

OUT

8 f

SW

2.5

1.8

where I is the inductor’s peak-to-peak ripple current, f

SW

switching frequency and C

is the output capacitor.

OUT

Synchronization Control

If using electrolytic capacitors,

The frequency of operation can be synchronized up to 2MHz by

an external signal applied to the SYNC pin. The rising edge on the

SYNC triggers the rising edge of PHASE. To properly sync, the

external source must be at least 10% greater than the

programmed free running IC frequency.

(EQ. 9)

V

= I*ESR

OUTripple

Loop Compensation Design

When COMP is not connected to VCC, the COMP pin is active for

external loop compensation. The ISL85410 uses constant

frequency peak current mode control architecture to achieve a

fast loop transient response. An accurate current sensing pilot

device in parallel with the upper MOSFET is used for peak current

control signal and overcurrent protection. The inductor is not

considered as a state variable since its peak current is constant,

and the system becomes a single order system. It is much easier

to design a type II compensator to stabilize the loop than to

implement voltage mode control. Peak current mode control has

an inherent input voltage feed-forward function to achieve good

line regulation. Figure 47 shows the small signal model of the

synchronous buck regulator.

Output Inductor Selection

The inductor value determines the converter’s ripple current.

Choosing an inductor current requires a somewhat arbitrary

choice of ripple current, I. A reasonable starting point is 30% of

total load current. The inductor value can then be calculated

using Equation 7:

V

– V

V

OUT

V

IN

f

OUT

------------------------------- ---------------

(EQ. 7)

L =



 I

SW

Increasing the value of inductance reduces the ripple current and

thus, the ripple voltage. However, the larger inductance value

may reduce the converter’s response time to a load transient.

The inductor current rating should be such that it does not

saturate in overcurrent conditions. For typical ISL85410

applications, inductor values generally lie in the 10µH to 47µH

^

L

R

LP

^

P

i

in

L

v

o

^

V

d

^

1:D

in

I d

V

L

in

Rc

Co

+

R

T

range. In general, higher V

causes higher inductance.

OUT

Ro

Buck Regulator Output Capacitor Selection

An output capacitor is required to filter the inductor current. The

current mode control loop allows the use of low ESR ceramic

capacitors and thus supports very small circuit implementations

on the PC board. Electrolytic and polymer capacitors can also be

used.

T(S)

i

^

d

K

Fm

T (S)

+

v

He(S)

^

V

While ceramic capacitors offer excellent overall performance

and reliability, the actual in-circuit capacitance must be

considered. Ceramic capacitors are rated using large

peak-to-peak voltage swings and with no DC bias. In the DC/DC

converter application, these conditions do not reflect reality. As a

result, the actual capacitance may be considerably lower than

the advertised value. Consult the manufacturer’s datasheet to

determine the actual in-application capacitance. Most

comp

-Av(S)

FIGURE 47. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK

REGULATOR

manufacturers publish capacitance vs DC bias so that this effect

can be easily accommodated. The effects of AC voltage are not

frequently published, but an assumption of ~20% further

reduction generally suffices. The result of these considerations

may mean an effective capacitance 50% lower than nominal and

this value should be used in all design calculations. Nonetheless,

FN8375 Rev.8.00

Mar 15, 2019

Page 17 of 22

ISL85410

1

(EQ. 13)

---------------

C =

3

Vo

f R

c

2

Example: V = 12V, V = 5V, I = 1A, f

= 500kHz,

R = 90.9kΩ, C = 22µF/5mΩ, L = 39µH, f = 50kHz, then

IN SW

O

R

2

C

3

2

o

c

V

FB

compensator resistance R :

6

-

V

COMP

GM

V

REF

+

3

R

3

(EQ. 14)

R

= 22.7510  50kHz  5V  22F = 125.12k

6

R

C

6

C

7

It is acceptable to use 124kΩas theclosest standard value for

6

R .

6

5V  22F

1A  124k

(EQ. 15)

------------------------------

= 0.88nF

C

6

=

FIGURE 48. TYPE II COMPENSATOR

5m  22F

124k

1

C = max(--------------------------------,---------------------------------------------------- )= (0.88pF,5.1pF)

7

  500kHz  124k

Figure 48 shows the type II compensator and its transfer function

is expressed as shown in Equation 10:

(EQ. 16)

S

It is also acceptable to use the closest standard values for C and

6





 

 





------------

1 +

ˆ

GM  R



v

C . There is approximately 3pF parasitic capacitance from V

COMP

3

cz1

cz2

7

COMP

------------------- -------------------------------------------------------- --------------------------------------------------------------

A S=

=

v

ˆ

C + C   R + R 

S

to GND; Therefore, C is optional. Use C = 1500pF and

v



 



7

6

7

2

3

FB

------------

S 1 +

1 +



 





C = OPEN.

cp1

cp2

7

(EQ. 10)

1

(EQ. 17)

--------------------------------------------------

C =

= 70pF

3

  50kHz  90.9k

where;

C

+ C

R

+ R

2 3

1

6

7

--------------

----------------------



=

,



=

 

=

  =

cp2

Use C = 68pF. Note that C may increase the loop bandwidth

cz1

cz2

cp1

3

R C

R C C

C R R

3 2

6

2

3

6

7

3

from previous estimated value. Figure 49, on page 19 shows the

simulated voltage loop gain. It is shown that it has a 75kHz loop

bandwidth with a 61° phase margin and 6dB gain margin. It may

be more desirable to achieve an increased gain margin., which

Compensator design goal:

• High DC gain

can be accomplished by lowering R by 20% to 30%. In practice,

6

ceramic capacitors have significant derating on voltage and

temperature, depending on the type. See the ceramic capacitor

datasheet for more details.

• Choose loop bandwidth f less than 100kHz

c

• Gain margin: >10dB

• Phase margin: >40°

The compensator design procedure is as follows:

The loop gain at crossover frequency of f has a unity gain.

c

Therefore, the compensator resistance R is determined by

6

Equation 11.

2f V C R

o o t

3

c

(EQ. 11)

---------------------------------

= 22.7510  f V C

c o o

R

=

6

GM  V

FB

where GM is the transconductance, g , of the voltage error

m

amplifier in each phase. Compensator capacitor C is then given

6

by Equation 12.

R C

V C

o o

I R

o 6

R C

o

1

c

o

(EQ. 12)

-------------- --------------

,C = max(--------------,---------------------)

7

C

=

6

R

f

R

6

SW 6

Put one compensator pole at zero frequency to achieve high DC

gain, and put another compensator pole at either ESR zero

frequency or half switching frequency, whichever is lower in

Equation 12. An optional zero can boost the phase margin. _CZ2

is a zero due to R and C 

2

3

Put compensator zero 2 to 5 times f .

c

FN8375 Rev.8.00

Mar 15, 2019

Page 18 of 22

ISL85410

Place a 1µF MLCC near the VCC pin and directly connect its

return with a via to the system GND plane.

60

45

30

15

0

Place the feedback divider close to the FB pin and do not route

any feedback components near PHASE or BOOT. If external

components are used for SS, COMP, or FS, the same advice

applies.

CSS

R_RF_FS_S

CVIN

-15

-30

100

1k

10k

100k

1M

FREQUENCY (Hz)

180

150

120

90

L1

COUT

60

30

0.47”

0

100

FIGURE 50. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS

1k

10k

100k

1M

FREQUENCY (Hz)

FIGURE 49. SIMULATED LOOP GAIN

Layout Considerations

Proper layout of the power converter minimizes EMI and noise

and ensures first pass success of the design. Printed Circuit

Board (PCB) layouts are provided in multiple formats on the

Renesas website. In addition, Figure 50 illustrates the important

points in PCB layout. In reality, PCB layout of the ISL85410 is

quite simple.

A multilayer PCB with GND plane is recommended. Figure 50

shows the connections of the critical components in the

converter. Note that capacitors C and C

can each represent

IN

OUT

multiple physical capacitors. The most critical connections are to

tie the PGND pin to the package GND pad and then use vias to

directly connect the GND pad to the system GND plane. This

connection of the GND pad to system plane ensures a low

impedance path for all return current and an excellent thermal

path to dissipate heat. With this connection made, place the high

frequency MLCC input capacitor near the VIN pin and use vias

directly at the capacitor pad to tie the capacitor to the system

GND plane.

The boot capacitor is easily placed on the PCB side opposite the

controller IC and two vias directly connect the capacitor to BOOT

and PHASE.

FN8375 Rev.8.00

Mar 15, 2019

Page 19 of 22

ISL85410

Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.

Please visit our website to make sure you have the latest revision.

DATE

REVISION

FN8375.8

CHANGE

Mar 15, 2019

Updated links throughout document.

Updated Related Literature section

Updated the Ordering Information table by adding tape and reel parts, demo board, and updated notes.

Under Light Load Operation section changed 300mA to 400mA and 1% to 2%.

Added Minimum On/Off-Time Limitation section.

Removed About Intersil section.

Updated Disclaimer.

Updated POD L12.4x3 to the latest version changes are as follows:

Tiebar Note 5 updated

From: Tiebar shown (if present) is a non-functional feature.

To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).

Mar 13, 2015

FN8375.7

On page 1, updated all 36V references to 40V and replaced Figure 2.

On page 6, under “Absolute Maximum Ratings”

for VIN to GND updated max from “+42V” to “+43V”

for PHASE to GND updated max from “43V” to “+44V”

for EN to GND updated max from “+42V” to “+43V”

Under “Recommended Operating Conditions” updated supply voltage max from “36V” to “+40V”.

In “Electrical Specifications” updated all occurrences of VIN value from “36V” to “40V”.

Replaced Figure 9, on page 8.

On page 14, under “Detailed Description” section updated voltage range max from “+36V” to “+40V”.

Aug 28, 2014

Jul 24, 2014

FN8375.6

FN8375.5

POD changed from L12.3x4 back to original L12.4x3.

Changed title of Figure 13, on page 9 from “Efficiency vs Load, PWM, V

OUT

= 5V, L = 30µH” to “V

OUT

1

Regulation vs Load, PWM, V

= 5V, L = 30µH”.

OUT

1

Replaced Figure Figure 46, on page 16.

Updated POD from L12.4x3 to L12.3x4

Feb 25, 2014

Jan 17, 2014

FN8375.4

FN8375.3

“Power-On Reset” on page 14 changed 10µA to 2µA.

“Functional Block Diagram” on page 5 changed Internal=50µs, External=230µs

to Internal=50µA/V, External=230µA/V and 600mA/Amp to 500mV/A

“Detailed Description” on page 14 changed 0.9A to 1.5A

“Power-On Reset” on page 14 changed 1µA to 10µA

“PWM Control Scheme” on page 14 changed in last paragraph 50µs vs 220µs to 50µA/V vs 230µA/V and

600mA/Amp to 500mV/A in 1st paragraph

“Overcurrent Protection” on page 15 changed 0.9A to 1.5A

Nov 22, 2013

FN8375.2

Initial Release.

FN8375 Rev.8.00

Mar 15, 2019

Page 20 of 22

ISL85410

For the most recent package outline drawing, see L12.4x3.

Package Outline Drawing

L12.4x3

12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 3, 3/15

3.30 +0.10/-0.15

2X 2.50

4.00

A

6

10X 0.50

PIN 1

PIN #1 INDEX AREA

INDEX AREA

12 X 0.40 ±0.10

1.70 +0.10/-0.15

B

6

1

6

3.00

(4X)

0.15

12

7

0.10M C A B

TOP VIEW

4 12 x 0.23 +0.07/-0.05

BOTTOM VIEW

SEE DETAIL "X"

(3.30)

0.10 C

C

6

1

1.00 MAX

SEATING PLANE

0.08

C

SIDE VIEW

2.80

(1.70)

5

0.2 REF

C

12 X 0.60

0. 00 MIN.

0. 05 MAX.

7

12

(12 X 0.23)

(10X 0.5)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance: Decimal ± 0.05

4. Dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature and

may be located on any of the 4 sides (or ends).

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

6.

7. Compliant to JEDEC MO-229 V4030D-4 issue E.

FN8375 Rev.8.00

Mar 15, 2019

Page 21 of 22

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TOYOSU FORESIA, 3-2-24 Toyosu,

For further information on a product, technology, the most up-to-date

Koto-ku, Tokyo 135-0061, Japan

www.renesas.com

version of a document, or your nearest sales office, please visit:

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型号：	ISL85410FRZ-T
厂家：	RENESAS TECHNOLOGY CORP
描述：	Wide VIN 1A Synchronous Buck Regulator; DFN12; Temp Range: -40° to 125°C 开关
文件：	总22页 (文件大小：2277K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL85410FRZ-T [RENESAS]

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