ISL85412DEMO1Z [RENESAS]
Wide VIN 150mA Synchronous Buck Regulator;
| 型号： | ISL85412DEMO1Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Wide VIN 150mA Synchronous Buck Regulator |
| 文件： | 总19页 (文件大小：1265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL85412
Wide V 150mA Synchronous Buck Regulator
IN
FN8378
Rev 1.00
March 13, 2015
The ISL85412 is a 150mA synchronous buck regulator with an
input range of 3.5V to 40V. It provides an easy to use, high
efficiency low BOM count solution for a variety of applications.
Features
• Wide input voltage range of 3.5V to 40V
• Synchronous operation for high efficiency
• No compensation required
The ISL85412 integrates both high-side and low-side NMOS
FETs and features a PFM mode for improved efficiency at light
loads. This feature can be disabled if forced PWM mode is
desired. The part switches at a default frequency of 700kHz.
By integrating both NMOS devices and providing internal
configuration, minimal external components are required,
reducing BOM count and complexity of design.
• Integrated high-side and low-side NMOS devices
• Selectable PFM or forced PWM mode at light loads
• Internal switching frequency 700kHz
• Continuous output current up to 150mA
• Internal soft-start
With the wide V range and reduced BOM, the part provides
IN
an easy to implement design solution for a variety of
applications while giving superior performance. It will provide
a very robust design for high voltage industrial applications as
well as an efficient solution for battery powered applications.
• Minimal external components required
• Power-good and enable functions available
Applications
• Industrial control
The part is available in a small Pb-free 3mmx3mm TDFN
plastic package with an operation junction temperature range
of -40°C to +125°C.
• Medical devices
• Portable instrumentation
• Distributed power supplies
• Cloud infrastructure
Related Literature
• AN1929, “ISL85413EVAL1Z, ISL85412EVAL1Z Evaluation
Boards”
• AN1931, “ISL85413DEMO1Z, ISL85412DEMO1Z Wide VIN
Synchronous Buck Regulator - Short Form”
100
90
V
OUT
U1 ISL85412
C4
R1
1
2
3
4
8
7
6
5
MODE
MODE
BOOT
VIN
FB
VCC
PG
80
R2
C6
C5
0.1µF
70
+3.5 ... +40V
1µF
VIN
PG
3.3V
OUT
1.5V
OUT
1.8V
C1
20µF
GND
60
50
40
EN
PHASE
EN
1.2V
OUT
OUT
f
= 700kHz
5.0V
OUT
SW
2.5V
OUT
1.0V
VOUT
GND
OUT
MAX 150mA
C8
L1
Device must be
connected to GND
plane with vias.
0.00
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. EFFICIENCY vs LOAD, PFM, V = 12V
IN
FN8378 Rev 1.00
March 13, 2015
Page 1 of 19
ISL85412
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Efficiency Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Light Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Negative Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Boot Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8378 Rev 1.00
March 13, 2015
Page 2 of 19
ISL85412
Pin Configuration
ISL85412
(8 LD 3x3 TDFN)
TOP VIEW
1
2
3
4
MODE
BOOT
VIN
FB
VCC
PG
8
7
6
5
GND
PHASE
EN
Pin Descriptions
PIN #
SYMBOL
PIN DESCRIPTION
1
MODE
Mode Selection pin. Connect to logic high or VCC for PWM mode. Connect to logic low or ground for PFM
mode. Logic ground enables the IC to automatically choose PFM or PWM operation. There is an internal
5MΩ pull-down resistor to prevent an undefined logic state if MODE is left floating.
2
3
BOOT
VIN
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-channel MOSFET. Connect an external 100nF capacitor from this
pin to PHASE.
The input supply for the power stage of the regulator and the source for the internal linear bias regulator.
Place a minimum of 10µF ceramic capacitance from VIN to GND and close to the IC for decoupling.
4
5
PHASE
EN
Switch node output. It connects the switching FETs with the external output inductor.
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the
voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not
connect EN pin to VCC since the LDO is controlled by EN voltage.
6
PG
Open drain power-good output that is pulled to ground when the output voltage is below regulation limits
or during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
7
8
VCC
FB
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In
addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.
EPAD
GND
Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage levels
are measured with respect to this pin. The EPAD MUST not float.
TABLE 1. EXTERNAL COMPONENT SELECTION (Refer to Figure 1)
V
C
C
L
(µH)
R
R
2
(kΩ)
OUT
(V)
4
8
1
1
(pF)
100
100
100
100
100
100
100
100
(µF)
2x22
2x22
2x22
2x22
22
(kΩ)
90.9
90.9
90.9
90.9
90.9
90.9
90.9
90.9
1.0
1.2
1.5
1.8
2.5
3.3
5.0
12.0
10
137
10
90.9
60.4
45.3
28.7
20.0
12.4
4.75
16
16
22
22
33
22
47
22
100
FN8378 Rev 1.00
March 13, 2015
Page 3 of 19
ISL85412
Functional Block Diagram
PG
VIN
EN
FB
POWER-
GOOD
5M
VCC
LOGIC
BIAS
LDO
EN/SOFT-
START
BOOT
FB
FAULT
LOGIC
930mV/A
CURRENT
SENSE
600mV VREF
MODE
OSCILLATOR
GATE
DRIVE
AND
PWM
PWM
PWM/PFM
SELECT LOGIC
s
Q
Q
PHASE
FB
PFM
5M
DEADTIME
R
CURRENT
SET
ZERO CURRENT
DETECTION
PGND
450mV/T SLOPE
COMPENSATION
(PWM ONLY)
150k
54pF
INTERNAL
COMPENSATION
INTERNAL = 50µs
PACKAGE
PADDLE
GND
Ordering Information
PART NUMBER
PART
MARKING
TEMP. RANGE
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Notes 1, 2, 3)
ISL85412FRTZ
(°C)
5412
-40 to +125
8 Ld TDFN
L8.3x3H
ISL85412EVAL1Z
ISL85412DEMO1Z
NOTES:
Evaluation Board
Demonstration Board
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85412. For more information on MSL please see techbrief TB363.
FN8378 Rev 1.00
March 13, 2015
Page 4 of 19
ISL85412
Absolute Maximum Ratings
Thermal Information
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to 44V (20ns)
EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
COMP, FS, PG, MODE, SS, VCC to GND. . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
ESD Rating
Thermal Resistance
TDFN Package (Note 4, 5). . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Operating Junction Temperature Range . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
47
(°C/W)
4
JA
JC
Recommended Operating Conditions
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . .2.5kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . . . 1kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Latch-up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5V to 40V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379 for details.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications T = -40°C to +125°C, V = 3.5V to 40V, unless otherwise noted. Typical values are at T = +25°C. Boldface
J
IN
A
limits apply across the junction temperature range.
MIN
MAX
PARAMETER
SUPPLY VOLTAGE
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
(Note 8
UNITS
V
V
V
V
Voltage Range
V
I
3.5
40
V
µA
µA
V
IN
IN
IN
CC
IN
Quiescent Supply Current
Shutdown Supply Current
Voltage
V
= 0.7V, MODE = 0V
50
1.8
5.1
5
Q
FB
I
EN = 0V, V = 40V (Note 6)
2.5
5.5
SD
IN
V
V
V
= 40V
4.5
CC
IN
IN
= 12V; I
= 0A to 10mA
4.35
5.45
V
OUT
POWER-ON RESET
POR Threshold
V
Rising Edge
Falling Edge
3.3
3
3.46
784
V
V
CC
2.76
600
OSCILLATOR
Nominal Switching Frequency
Minimum Off-Time
f
f
= V
700
130
90
kHz
ns
SW
SW CC
t
V
= 3.5V
OFF
IN
Minimum On-Time
t
(Note 9)
ns
ON
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
FB Leakage Current
gm
50
1
µA/V
nA
V
= 0.6V
100
1.02
FB
Current Sense Amplifier Gain
FB Voltage
R
0.84
0.93
0.599
V/A
V
T
T
= -40°C to +125°C
0.589
0.606
A
POWER-GOOD
Lower PG Threshold - VFB Rising
Lower PG Threshold - VFB Falling
Upper PG Threshold - VFB Rising
Upper PG Threshold - VFB Falling
PG Propagation Delay
PG Low Voltage
91
85
94
%
%
%
%
%
V
81.5
107
118
111
10
121
Percentage of the soft-start time
= 3mA, EN = V , V = 0V
I
0.05
0.3
SINK
CC FB
FN8378 Rev 1.00
March 13, 2015
Page 5 of 19
ISL85412
Electrical Specifications T = -40°C to +125°C, V = 3.5V to 40V, unless otherwise noted. Typical values are at T = +25°C. Boldface
J
IN
A
limits apply across the junction temperature range. (Continued)
MIN
MAX
PARAMETER
TRACKING AND SOFT-START
Internal Soft-Start Ramp Time
FAULT PROTECTION
SYMBOL
TEST CONDITIONS
(Note 8)
TYP
2.3
(Note 8
UNITS
ms
EN/SS = V
1.5
3.1
CC
Thermal Shutdown Temperature
T
Rising Threshold
Hysteresis
150
20
°C
°C
SD
T
HYS
Current Limit Blanking Time
t
17
Clock
OCON
pulses
Overcurrent and Auto Restart Period
Positive Peak Current Limit
PFM Peak Current Limit
Zero Cross Threshold
Negative Current Limit
POWER MOSFET
t
8
0.4
0.22
5
SS cycle
OCOFF
IPLIMIT
(Note 7)
(Note 7)
0.36
0.17
0.44
0.27
A
A
I
PK_PFM
mA
A
INLIMIT
-0.33
-0.30
-0.27
High-side
R
I
I
= 100mA, V = 5V
CC
900
500
50
1300
800
mΩ
mΩ
nA
HDS
PHASE
Low-side
R
= 100mA, V = 5V
CC
LDS
PHASE
PHASE Leakage Current
PHASE Rise Time
EN = PHASE = 0V
= 40V
300
t
V
10
ns
RISE
IN
EN/MODE
Mode Input Threshold
Rising Edge, Logic High
Falling Edge, Logic Low
Rising Edge, Logic High
Falling Edge, Logic Low
EN = 0V/40V
1.3
1.0
1.2
0.9
1.45
1.45
V
V
0.4
EN Threshold
V
0.4
V
EN Logic Input Leakage Current
MODE Logic Input Leakage Current
MODE Pull-down Resistor
NOTES:
-0.5
0.5
100
6.15
µA
nA
MΩ
MODE = 0V
10
5
6. Test Condition: V = 40V, FB forced above regulation point (0.6V), no switching, and power MOSFET gate charging current not included.
IN
7. Established by both current sense amplifier gain test and current sense amplifier output test at I = 0A.
L
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
9. Minimum On-Time required to maintain loop stability.
FN8378 Rev 1.00
March 13, 2015
Page 6 of 19
ISL85412
Efficiency Curves
f
= 700kHz, T = +25°C, C = 20µF
SW
A
IN
100
90
80
70
60
50
40
100
90
80
1.8V
1.8V
OUT
OUT
1.5V
OUT
3.3V
2.5V
OUT
OUT
2.5V
3.3V
OUT
OUT
OUT
1.5V
OUT
70
60
50
40
OUT
1.2V
1.2V
OUT
1.0V
1.0V
OUT
0
0
0
0.03
0.06
0.09
0.12
0.15
0
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 3. EFFICIENCY vs LOAD, PFM, V = 5V
IN
FIGURE 4. EFFICIENCY vs LOAD, PWM, V = 5V
IN
100
90
80
70
60
50
40
100
90
80
70
60
50
40
3.3V
OUT
3.3V
OUT
1.5V
OUT
1.8V
5.0V
OUT
OUT
1.8V
OUT
1.2V
OUT
2.5V
OUT
5.0V
OUT
2.5V
OUT
1.5V
OUT
1.0V
OUT
1.2V
OUT
1.0V
OUT
0.06
OUTPUT LOAD (A)
0
0.03
0.06
0.09
0.12
0.15
0.03
0.09
0.12
0.15
OUTPUT LOAD (A)
FIGURE 5. EFFICIENCY vs LOAD, PFM, V = 12V
IN
FIGURE 6. EFFICIENCY vs LOAD, PWM, V = 12V
IN
100
90
80
70
60
50
40
100
90
80
70
60
50
40
5.0V
12V
OUT
OUT
2.5V
OUT
12V
OUT
2.5V
OUT
1.5V
OUT
OUT
3.3V
1.8V
OUT
5.0V
OUT
1.2V
OUT
1.5V
OUT
1.8V
1.2V
1.0V
OUT
OUT
OUT
1.0V
OUT
0
0.03
0.06
0.09
0.12
0.15
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 8. EFFICIENCY vs LOAD, PWM, V = 24V
IN
FIGURE 7. EFFICIENCY vs LOAD, PFM, V = 24V
IN
FN8378 Rev 1.00
March 13, 2015
Page 7 of 19
ISL85412
Efficiency Curves
f
= 700kHz, T = +25°C, C = 20µF (Continued)
IN
SW
A
100
100
90
80
70
60
50
40
12V
OUT
12V
OUT
5.0V
5.0V
OUT
90
80
70
60
50
40
OUT
3.3V
OUT
3.3V
OUT
2.5V
OUT
1.5V
1.2V
OUT
OUT
1.8V
2.5V
OUT
OUT
1.8V
OUT
1.5V
OUT
1.2V
OUT
0.09
OUTPUT LOAD (A)
0
0.03
0.06
0.09
0.12
0.15
0
0.03
0.06
0.12
0.15
OUTPUT LOAD (A)
FIGURE 9. EFFICIENCY vs LOAD, PFM, V = 36V
IN
FIGURE 10. EFFICIENCY vs LOAD, PWM, V = 36V
IN
1.23
1.22
1.21
1.20
1.19
1.18
1.17
1.020
1.015
1.010
1.005
1.000
0.995
0.990
5V PFM
IN
24V PFM
IN
5V PFM
IN
24V PFM
IN
36V PFM
IN
12V PFM
IN
12V PFM
IN
12V PWM
IN
5V PWM
IN
36V PWM
IN
12V PWM
IN
24V PWM
IN
5V PWM
IN
0
0.03
0.06
0.09
0.12
0.15
0
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 11. V
OUT
REGULATION vs LOAD, V
= 1V
FIGURE 12. V
OUT
REGULATION vs LOAD, V
= 1.2V
OUT
OUT
1.56
1.55
1.53
1.52
1.50
1.49
1.47
1.83
24V PFM
IN
5V PFM
IN
12V PFM
IN
36V PFM
IN
1.82
1.81
1.80
1.79
1.78
1.77
12V PFM
IN
36V PFM
IN
5V PFM
IN
24V PFM
IN
12V PWM
IN
5V PWM
IN
24V PWM
IN
36V PWM
IN
12V PWM
IN
5V PWM
IN
24V PWM
IN
36V PWM
IN
0
0.03
0.06
0.09
0.12
0.15
0
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 13. V
OUT
REGULATION vs LOAD, PWM, V
= 1.5V
OUT
FIGURE 14. V
OUT
REGULATION vs LOAD, V
= 1.8V
OUT
FN8378 Rev 1.00
March 13, 2015
Page 8 of 19
ISL85412
Efficiency Curves
f
= 700kHz, T = +25°C, C = 20µF (Continued)
IN
SW
A
2.55
3.35
3.34
3.33
3.32
3.31
3.30
3.29
5V PFM
IN
12V PFM
IN
2.54
2.53
2.52
2.51
2.50
2.49
36V PFM
IN
5V PFM
IN
36V PFM
IN
12V PFM
IN
24V PFM
IN
24V PFM
IN
12V PWM
IN
5V PWM
IN
12V PWM
IN
5V PWM
IN
36V PWM
IN
24V PWM
IN
36V PWM
IN
24V PWM
IN
0
0.03
0.06
0.09
0.12
0.15
0
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 16. V
OUT
REGULATION vs LOAD, V
= 3.3V
OUT
FIGURE 15. V
OUT
REGULATION vs LOAD, V = 2.5V
OUT
12.35
12.28
12.20
12.13
12.05
11.98
11.90
5.04
24V PFM
IN
5.03
5.01
5.00
4.98
4.97
4.95
12V PFM
IN
36V PFM
IN
24V PFM
IN
36V PFM
IN
12V PWM
IN
36V PWM
IN
24V PWM
IN
36V PWM
IN
24V PWM
IN
0
0.03
0.06
0.09
0.12
0.15
0
0.03
0.06
0.09
0.12
0.15
OUTPUT LOAD (A)
OUTPUT LOAD (A)
FIGURE 17. V
OUT
REGULATION vs LOAD, V
= 5V
FIGURE 18. V
REGULATION vs LOAD, V = 12V
OUT
OUT
OUT
FN8378 Rev 1.00
March 13, 2015
Page 9 of 19
ISL85412
Typical Performance Curves
V
= 12V, V
OUT
= 3.3V, f
= 700kHz, T = +25°C, C = 20µF,
IN
IN
SW
A
C
= 22µF.
OUT
PHASE 10V/DIV
PHASE 10V/DIV
V
2V/DIV
OUT
V
2V/DIV
OUT
VEN 10V/DIV
PG 5V/DIV
VEN 10V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 19. START-UP AT NO LOAD, PFM
FIGURE 20. START-UP AT NO LOAD, PWM
PHASE 10V/DIV
PHASE 10V/DIV
V
2V/DIV
V
2V/DIV
OUT
OUT
VEN 10V/DIV
PG 5V/DIV
VEN 10V/DIV
PG 5V/DIV
100ms/DIV
100ms/DIV
FIGURE 21. SHUTDOWN IN NO LOAD, PFM
FIGURE 22. SHUTDOWN AT NO LOAD, PWM
PHASE 10V/DIV
PHASE 10V/DIV
V
2V/DIV
V
2V/DIV
OUT
OUT
VEN 10V/DIV
PG 5V/DIV
VEN 10V/DIV
PG 5V/DIV
1ms/DIV
2ms/DIV
FIGURE 23. START-UP AT 150mA, PWM
FIGURE 24. SHUTDOWN AT 150mA, PWM
FN8378 Rev 1.00
March 13, 2015
Page 10 of 19
ISL85412
Typical Performance Curves
V
= 12V, V
OUT
= 3.3V, f
= 700kHz, T = +25°C, C = 20µF,
IN
IN
SW
A
C
= 22µF. (Continued)
OUT
PHASE 10V/DIV
PHASE 10V/DIV
V
2V/DIV
OUT
V
2V/DIV
OUT
VEN 10V/DIV
PG 5V/DIV
VEN 10V/DIV
PG 5V/DIV
1ms/DIV
5ms/DIV
FIGURE 25. START-UP AT 150mA, PFM
FIGURE 26. SHUTDOWN AT 150mA, PFM
V
10V/DIV
1V/DIV
IN
V
10V/DIV
2V/DIV
IN
V
V
OUT
OUT
I
100mA/DIV
PG 5V/DIV
I
100mA/DIV
PG 5V/DIV
L
L
1ms/DIV
1ms/DIV
FIGURE 27. START-UP V AT 150mA LOAD, PFM
IN
FIGURE 28. START-UP V AT 150mA LOAD, PWM
IN
V
10V/DIV
V
10V/DIV
IN
IN
V
2V/DIV
V
2V/DIV
OUT
OUT
I
100mA/DIV
PG 5V/DIV
I
100mA/DIV
PG 5V/DIV
L
L
5ms/DIV
5ms/DIV
FIGURE 29. SHUTDOWN V AT 150mA LOAD, PFM
IN
FIGURE 30. SHUTDOWN V AT 150mA LOAD, PWM
IN
FN8378 Rev 1.00
March 13, 2015
Page 11 of 19
ISL85412
Typical Performance Curves
V
= 12V, V
OUT
= 3.3V, f
= 700kHz, T = +25°C, C = 20µF,
IN
IN
SW
A
C
= 22µF. (Continued)
OUT
PHASE 10V/DIV
PHASE 10V/DIV
V
2V/DIV
OUT
V
V
2V/DIV
OUT
V
10v/DIV
IN
10v/DIV
IN
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 31. START-UP V AT NO LOAD, PFM
IN
FIGURE 32. START-UP V AT NO LOAD, PWM
IN
PHASE 10V/DIV
PHASE 10V/DIV
V
V
1V/DIV
OUT
V
V
2V/DIV
OUT
5v/DIV
IN
10v/DIV
IN
PG 5V/DIV
PG 5V/DIV
100ms/DIV
100ms/DIV
FIGURE 33. SHUTDOWN V AT NO LOAD, PFM
IN
FIGURE 34. SHUTDOWN V AT NO LOAD, PWM
IN
PHASE 1V/DIV
PHASE 1V/DIV
100ns/DIV
100ns/DIV
FIGURE 35. JITTER AT NO LOAD, PWM
FIGURE 36. JITTER AT FULL LOAD, PWM
FN8378 Rev 1.00
March 13, 2015
Page 12 of 19
ISL85412
Typical Performance Curves
V
= 12V, V
OUT
= 3.3V, f
= 700kHz, T = +25°C, C = 20µF,
IN
SW
A
IN
C
= 22µF. (Continued)
OUT
PHASE 10V/DIV
PHASE 10V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT
OUT
I
100mA/DIV
L
I
100mA/DIV
L
1µs/DIV
5ms/DIV
FIGURE 37. STEADY STATE AT NO LOAD, PFM
FIGURE 38. STEADY STATE AT NO LOAD, PWM
PHASE 10V/DIV
PHASE 10V/DIV
V
20mV/DIV
OUT
V
20mV/DIV
OUT
I
100mA/DIV
2µs/DIV
L
I
100mA/DIV
L
1µs/DIV
FIGURE 39. STEADY STATE AT 150mA LOAD, PWM
FIGURE 40. STEADY STATE AT 20mA LOAD, PFM
V
RIPPLE 100mV/DIV
OUT
V
RIPPLE 50mV/DIV
OUT
I
100mA/DIV
L
I
100mA/DIV
L
200µs/DIV
200µs/DIV
FIGURE 41. LOAD TRANSIENT, PFM
FIGURE 42. LOAD TRANSIENT, PWM
FN8378 Rev 1.00
March 13, 2015
Page 13 of 19
ISL85412
Typical Performance Curves
V
= 12V, V
OUT
= 3.3V, f
= 700kHz, T = +25°C, C = 20µF,
IN
IN
SW
A
C
= 22µF. (Continued)
OUT
PHASE 10V/DIV
PHASE 10V/DIV
V
2V/DIV
OUT
V
2V/DIV
OUT
I
500mA/DIV
PG 5V/DIV
L
I
500mA/DIV
PG 5V/DIV
L
20µs/DIV
10ms/DIV
FIGURE 43. OUTPUT SHORT CIRCUIT
FIGURE 44. OVERCURRENT PROTECTION
PHASE1 10V/DIV
PHASE1 10V/DIV
V
RIPPLE 20mV/DIV
V
RIPPLE 20mV/DIV
OUT1
OUT1
I
50mA/DIV
10µs/DIV
I
50mA/DIV
5µs/DIV
L
L
FIGURE 45. PFM TO PWM TRANSITION
FIGURE 46. PWM TO PFM TRANSITION
V
2V/DIV
PHASE 10V/DIV
OUT
I
200mA/DIV
L
V
2V/DIV
OUT
PG 2V/DIV
PG 5V/DIV
10µs/DIV
200ms/DIV
FIGURE 47. OVERVOLTAGE PROTECTION
FIGURE 48. OVERTEMPERATURE PROTECTION
FN8378 Rev 1.00
March 13, 2015
Page 14 of 19
ISL85412
A PWM cycle begins when a clock pulse sets the PWM latch and
the upper FET is turned on. Current begins to ramp up in the upper
Detailed Description
The ISL85412 combines a synchronous buck PWM controller
with integrated power switches. The buck controller drives
internal high-side and low-side N-channel MOSFETs to deliver
load current up to 150mA. The buck regulator can operate from
an unregulated DC source, such as a battery, with a voltage
ranging from +3.5V to +40V. An internal LDO provides bias to the
low voltage portions of the IC.
FET and inductor. This current is sensed (V ), converted to a
CSA
voltage and summed with the slope compensation signal. This
combined signal is compared to V and when the signal is
COMP
, the latch is reset. Upon latch reset the upper FET is
equal to V
COMP
turned off and the lower FET turned on allowing current to ramp
down in the inductor. The lower FET will remain on until the clock
initiates another PWM cycle. Figure 49 shows the typical operating
waveforms during the PWM operation. The dotted lines illustrate
the sum of the current sense and slope compensation signal.
Peak current mode control is utilized to simplify feedback loop
compensation and reject input voltage variation. User selectable
internal feedback loop compensation further simplifies design.
The ISL85412 switches at a default 700kHz.
Output voltage is regulated as the error amplifier varies its output
and thus output inductor current. The error amplifier is a
transconductance type and its output is terminated with a series
RC (150k/54pF) network to GND. The transconductance of the
error amplifier is 50µs. Its noninverting input is internally
connected to a 600mV reference voltage and its inverting input is
connected to the output voltage via the FB pin and its associated
divider network.
The buck regulator is equipped with an internal current sensing
circuit and the peak current limit threshold is typically set at
0.4A.
Power-On Reset
The ISL85412 automatically initializes upon receipt of the input
power supply and continually monitors the EN pin state. If EN is
held below its logic rising threshold, the IC is held in shutdown
and consumes typically 1.8µA from the VIN supply. If EN exceeds
its logic rising threshold, the regulator will enable the bias LDO
and begin to monitor the VCC pin voltage. When the VCC pin
voltage clears its rising POR threshold, the controller will initialize
the switching regulator circuits. If VCC never clears the rising POR
threshold, the controller will not allow the switching regulator to
operate. If VCC falls below its falling POR threshold while the
switching regulator is operating, the switching regulator will be
shut down until VCC returns.
V
COMP
V
CSA
DUTY
CYCLE
I
L
V
OUT
Soft-Start
To avoid large inrush current, V
to its final regulated value in 2.3ms.
is slowly increased at start-up
OUT
FIGURE 49. PWM OPERATION WAVEFORMS
Light Load Operation
Power-Good
At light loads, converter efficiency may be improved by enabling
variable frequency operation (PFM). Connecting the MODE pin to
GND will allow the controller to choose such operation
automatically when the load current is low. Figure 50 shows the
PFM operation. The IC enters the PFM mode of operation when 8
consecutive cycles of inductor current crossing zero are detected.
This corresponds to a load current equal to 1/2 the peak-to-peak
inductor ripple current and set by Equation 1:
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the
FB pin. PG is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
completes, PG becomes high impedance provided the FB pin is
within the range specified in the “Electrical Specifications” on
page 5. Should FB exit the specified window, PG will be pulled
low until FB returns. Over-temperature faults also force PG low
until the fault condition is cleared by an attempt to soft-start.
There is an internal 5MΩ internal pull-up resistor.
V
1 – D
(EQ. 1)
OUT
----------------------------------
=
I
OUT
2Lf
SW
PWM Control Scheme
where D = duty cycle, f
SW
= switching frequency, L = inductor
= output voltage.
The ISL85412 employs peak current-mode pulse-width
modulation (PWM) control for fast transient response and
pulse-by-pulse current limiting, as shown in the “Functional Block
Diagram” on page 4. The current loop consists of the current
sensing circuit, slope compensation ramp, PWM comparator,
oscillator and latch. Current sense transresistance is typically
930mV/A and slope compensation rate, Se, is typically 450mV/T
where T is the switching cycle period. The control reference for
the current loop comes from the error amplifier’s output.
value, I
= output loading current, V
OUT
OUT
While operating in PFM mode, the regulator controls the output
voltage with a simple comparator and pulsed FET current. A
comparator signals the point at which FB is equal to the 600mV
reference at which time the regulator begins providing pulses of
current until FB is moved above the 600mV reference by 1%. The
current pulses are approximately 200mA and are issued at a
frequency equal to the converter’s PWM operating frequency.
FN8378 Rev 1.00
March 13, 2015
Page 15 of 19
ISL85412
PWM
PFM
PULSE SKIP
PFM
PWM
CLOCK
8 CYCLES
I
L
LOAD CURRENT
0
V
OUT
FIGURE 50. PFM MODE OPERATION WAVEFORMS
Due to the pulsed current nature of PFM mode, the converter can
supply limited current to the load. Should load current rise
event that current reaches the limit, the upper FET will be turned
off until the next switching cycle. In this way, FET peak current is
always well limited.
beyond the limit, V
will begin to decline. A second comparator
OUT
signals an FB voltage 1% lower than the 600mV reference and
forces the converter to return to PWM operation.
If the overcurrent condition persists for 17 sequential clock
cycles, the regulator will begin its hiccup sequence. In this case,
both FETs will be turned off and PG will be pulled low. This
condition will be maintained for 8 soft-start periods after which
the regulator will attempt a normal soft-start.
Output Voltage Selection
The regulator output voltage is easily programmed using an
external resistor divider to scale V
relative to the internal
OUT
Should the output fault persist, the regulator will repeat the
hiccup sequence indefinitely. There is no danger even if the
output is shorted during soft-start.
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 51.
The output voltage programming resistor, R , depends on the
2
ths
If V
OUT
is shorted very quickly, FB may collapse below 5/8 of
value chosen for the feedback resistor, R and the desired output
1
its target value before 17 cycles of overcurrent are detected. The
ISL85412 recognizes this condition and will begin to lower its
switching frequency proportional to the FB pin voltage. This
voltage, V , of the regulator. Equation 2 describes the
OUT
relationship between V
and resistor values.
OUT
R x0.6V
1
insures that under no circumstance (even with V
near 0V) will
----------------------------------
=
(EQ. 2)
OUT
R
2
V
– 0.6V
OUT
the inductor current run away.
If the desired output voltage is 0.6V, then R is left unpopulated
2
Negative Current Limit
Should an external source somehow drive current into V , the
and R is 0Ω.
1
OUT
controller will attempt to regulate V
OUT
by reversing its inductor
V
OUT
current to absorb the externally sourced current. In the event that
the external source is low impedance, current may be reversed to
unacceptable levels and the controller will initiate its negative
current limit protection. Similar to normal overcurrent, the
negative current protection is realized by monitoring the current
through the lower FET. When the valley point of the inductor
current reaches negative current limit, the lower FET is turned off
and the upper FET is forced on until current reaches the positive
current limit or an internal clock signal is issued. At this point, the
lower FET is allowed to operate. Should the current again be pulled
to the negative limit on the next cycle, the upper FET will again be
R
R
1
FB
-
+
EA
2
0.6V
REFERENCE
FIGURE 51. EXTERNAL RESISTOR DIVIDER
th
forced on and current will be forced to 1/6 of the positive current
Protection Features
limit. At this point the controller will turn off both FETs and wait for
error amplifier’s output to indicate return to normal operation.
During this time, the controller will apply a 100Ω load from PHASE
to PGND and attempt to discharge the output. Negative current
limit is a pulse-by-pulse style operation and recovery is automatic.
Negative current limit protection is disabled in PFM operating
mode because reverse current is not allowed to build due to the
diode emulation behavior of the lower FET.
The ISL85412 is protected from overcurrent, negative
overcurrent and over-temperature. The protection circuits
operate automatically.
Overcurrent Protection
During PWM on-time, current through the upper FET is monitored
and compared to a nominal 0.4A peak overcurrent limit. In the
FN8378 Rev 1.00
March 13, 2015
Page 16 of 19
ISL85412
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, but an assumption of ~20% further
reduction will generally suffice. The result of these
considerations may mean an effective capacitance 50% lower
than nominal and this value should be used in all design
calculations. Nonetheless, ceramic capacitors are a very good
choice in many applications due to their reliability and extremely
low ESR.
Over-Temperature Protection
Over-temperature protection limits maximum junction
temperature in the ISL85412. When junction temperature (T )
exceeds +150°C, both FETs are turned off and the controller
waits for temperature to decrease by approximately 20°C.
During this time PG is pulled low. When temperature is within an
acceptable range, the controller will initiate a normal soft-start
sequence. For continuous operation, the +125°C junction
temperature rating should not be exceeded.
J
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
Boot Undervoltage Protection
If the Boot capacitor voltage falls below 1.8V, the Boot
undervoltage protection circuit will turn on the lower FET for
400ns to recharge the capacitor. This operation may arise during
long periods of no switching such as PFM no load situations. In
For the ceramic capacitors (low ESR):
I
(EQ. 4)
is the
------------------------------------
V
=
OUTripple
C
OUT
8 f
SW
PWM operation near dropout (V near V
), the regulator may
IN OUT
hold the upper FET on for multiple clock cycles. To prevent the
boot capacitor from discharging, the lower FET is forced on for
approximately 200ns every 34 clock cycles.
Where I is the inductor’s peak-to-peak ripple current, f
SW
switching frequency and C
is the output capacitor.
OUT
If using electrolytic capacitors then:
(EQ. 5)
V
= I*ESR
Application Guidelines
OUTripple
Simplifying the Design
Layout Considerations
Table 1 on page 3 provides component value selections for a
variety of output voltages and will allow the designer to
implement solutions with a minimum of effort.
Proper layout of the power converter will minimize EMI and noise
and insure first pass success of the design. PCB layouts are
provided in multiple formats on the Intersil web site. In addition,
Figure 52 will make clear the important points in PCB layout. In
reality, PCB layout of the ISL85412 is quite simple.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 3:
A multi-layer printed circuit board with GND plane is
recommended. Figure 52 shows the connections of the critical
components in the converter. Note that capacitors C and C
could each represent multiple physical capacitors. The most
critical connections are to tie the PGND pin to the package GND
pad and then use vias to directly connect the GND pad to the
system GND plane. This connection of the GND pad to system
plane insures a low impedance path for all return current, as well
as an excellent thermal path to dissipate heat. With this
connection made, place the high frequency MLCC input capacitor
near the VIN pin and use vias directly at the capacitor pad to tie
the capacitor to the system GND plane.
IN
OUT
V
– V
V
OUT
V
IN
IN
F
OUT
(EQ. 3)
------------------------------- ---------------
L =
I
S
Increasing the value of inductance reduces the ripple current and
thus, the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient.
The inductor current rating should be such that it will not saturate
in overcurrent conditions. For typical ISL85412 applications,
inductor values generally lies in the 10µH to 47µH range. In
The boot capacitor is easily placed on the PCB side opposite the
controller IC and 2 vias directly connect the capacitor to BOOT
and PHASE.
general, higher V
will mean higher inductance.
OUT
Buck Regulator Output Capacitor Selection
Place a 1µF MLCC near the VCC pin and directly connect its
return with a via to the system GND plane.
An output capacitor is required to filter the inductor current. The
current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations
on the PC board. Electrolytic and polymer capacitors may also be
used.
Place the feedback divider close to the FB pin and do not route
any feedback components near PHASE or BOOT.
While ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large
peak-to-peak voltage swings and with no DC bias. In the DC/DC
converter application, these conditions do not reflect reality. As a
result, the actual capacitance may be considerably lower than
the advertised value. Consult the manufacturers data sheet to
determine the actual in-application capacitance. Most
FN8378 Rev 1.00
March 13, 2015
Page 17 of 19
ISL85412
FIGURE 52. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN8378.1
CHANGE
March 13, 2015
Upgraded the max nom VIN from 36V to 40V and abs max to 43V.
- On page 1 - Changed all "36V" occurrences on to "40V" and also changed "36V" to "40V" in the Typical
Application diagram.
- On page 5 - Changed in the Abs Max Ratings: "42V" to "43V" (twice) and "43V" to "44V" (once) and in the
Recommended Operating Conditions "36V" to "40V".
On pages 5 and 6 - In the EC table, changed "36V" to "40V" all occurrences .
- on page 15 - Changed the occurrence "36V" to "40V" in the "Detailed Description".
April 11, 2014
FN8378.0
Initial Release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2014-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8378 Rev 1.00
March 13, 2015
Page 18 of 19
ISL85412
Package Outline Drawing
L8.3x3H
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN)
Rev 0, 2/08
2.38
1.50 REF
3.00
A
PIN #1 INDEX AREA
6
6 X 0.50
6
PIN 1
INDEX AREA
B
8 X 0.40
1
4
2.20
3.00
1.64
(4X)
0.15
5
8
0.10 M C A B
8 X 0.25
TOP VIEW
BOTTOM VIEW
( 2.38 )
SEE DETAIL "X"
0 .80 MAX
C
0.10
C
BASE PLANE
SEATING PLANE
0.08
C
2 . 80
( 2 .20 )
SIDE VIEW
0.2 REF
( 1.64 )
C
8X 0.60
0 . 00 MIN.
0 . 05 MAX.
( 8X 0.25 )
DETAIL “X”
( 6X 0 . 5 )
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width dimension applies to the metallized terminal and is
measured between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN8378 Rev 1.00
March 13, 2015
Page 19 of 19
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