ISL85415 [RENESAS]
Wide VIN 1.2A Synchronous Buck Regulator;
| 型号： | ISL85415 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Wide VIN 1.2A Synchronous Buck Regulator |
| 文件： | 总19页 (文件大小：1099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL854102
Wide V 1.2A Synchronous Buck Regulator
IN
FN8870
Rev 0.00
July 1, 2016
The ISL854102 is a 1.2A synchronous buck regulator with an
input range of 3V to 40V. It provides an easy to use, high
efficiency, low BOM count solution for a variety of applications.
Features
• Wide input voltage range 3V to 40V
• Synchronous operation for high efficiency
• No compensation required
The ISL854102 integrates both high-side and low-side NMOS
FETs and features a PFM mode for improved efficiency at light
loads. This feature can be disabled if a forced PWM mode is
desired. The part switches at a default frequency of 500kHz,
however, may also be programmed using an external resistor
from 300kHz to 2MHz. The ISL854102 has the ability to utilize
internal or external compensation. By integrating both NMOS
devices and providing internal configuration options, minimal
external components are required, reducing BOM count and
complexity of design.
• Integrated high-side and low-side NMOS devices
• Selectable PFM or forced PWM mode at light loads
• Internal fixed (500kHz) or adjustable switching frequency
300kHz to 2MHz
• Continuous output current up to 1.2A
• Internal or external soft-start
• Minimal external components required
• Power-good and enable functions available
With the wide V range and reduced BOM, the part provides
IN
an easy to implement design solution for a variety of
applications while giving superior performance. It will provide
a very robust design for high voltage industrial applications as
well as an efficient solution for battery powered applications.
Applications
• Industrial control
The part is available in a small Pb-free 4mmx3mm DFN plastic
package with a full-range industrial temperature of -40°C to
+125°C.
• Medical devices
• Portable instrumentation
• Distributed power supplies
• Cloud infrastructure
100
95
90
85
80
75
70
1
2
12
11
SS
FS
COMP
SYNC
BOOT
VIN
R2
R3
CFB
10
9
3
4
FB
CBOOT
100nF
GND
CVIN
10µF
VCC
VIN=12V
VIN=15V
VIN=24V
65
60
CVCC
1µF
5
6
VOUT
PHASE
PGND
PG
EN
L1
22µH
COUT
10µF
55
50
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
INTERNAL DEFAULT PARAMETER SELECTION
FIGURE 2. EFFICIENCY vs LOAD, PFM, V
OUT
= 5V, L = 22µH
1
FIGURE 1. TYPICAL APPLICATION
FN8870 Rev 0.00
July 1, 2016
Page 1 of 19
ISL854102
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Efficiency Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Light Load Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Negative Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Over-Temperature Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Boot Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Simplifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Synchronization Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Buck Regulator Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8870 Rev 0.00
July 1, 2016
Page 2 of 19
ISL854102
Pin Configuration
ISL854102
(12 LD 4x3 DFN)
TOP VIEW
12
11
10
9
FS
1
2
3
4
5
6
SS
SYNC
BOOT
VIN
COMP
FB
GND
VCC
PG
EN
PHASE
PGND
8
7
Pin Descriptions
PIN NUMBER
SYMBOL
PIN DESCRIPTION
1
SS
The SS pin controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground
determines the output ramp rate. See “Soft-Start” on page 12 for soft-start details. If the SS pin is tied to
VCC, an internal soft-start of 2ms will be used.
2
SYNC
Synchronization and light load operational mode selection input. Connect to logic high or VCC for PWM
mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose
PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger.
Sync source must be higher than the programmed IC frequency. There is an internal 5MΩ pull-down resistor
to prevent an undefined logic state if SYNC is left floating.
3
4
BOOT
VIN
Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the
necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this
pin to PHASE.
The input supply for the power stage of the regulator and the source for the internal linear bias regulator.
Place a minimum of 4.7µF ceramic capacitance from VIN to GND and close to the IC for decoupling.
5
6
7
PHASE
PGND
EN
Switch node output. It connects the switching FETs with the external output inductor.
Power ground connection. Connect directly to the system GND plane.
Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the
voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not
connect EN pin to VCC since the LDO is controlled by EN voltage.
8
PG
Open-drain power-good output that is pulled to ground when the output voltage is below regulation limits or
during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.
9
VCC
FB
Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.
10
Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the
output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In
addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.
11
COMP
COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used. When only
an RC network is connected from COMP to GND, external compensation is used. See “Loop Compensation
Design” on page 15 for more details.
12
FS
Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for adjustable
frequency from 300kHz to 2MHz.
EPAD
GND
Signal ground connections. Connect to application board GND plane with at least 5 vias. All voltage levels
are measured with respect to this pin. The EPAD MUST NOT float.
FN8870 Rev 0.00
July 1, 2016
Page 3 of 19
ISL854102
Typical Application Schematics
1
12
11
SS
FS
2
COMP
SYNC
R2
R3
CFB
10
9
3
BOOT
FB
CBOOT
100nF
GND
4
VIN
VCC
CVIN
10µF
CVCC
1µF
VOUT
5
6
PHASE
PGND
PG
EN
L1
22µH
COUT
10µF
FIGURE 3. INTERNAL DEFAULT PARAMETER SELECTION
12
1
2
SS
FS
RFS
CSS
11
10
9
COMP
SYNC
BOOT
VIN
R2
R3
CFB
3
4
FB
CBOOT
100nF
GND
VCC
CVIN
10µF
CVCC
1µF
5
6
VOUT
PHASE
PGND
PG
EN
L1
22µH
COUT
10µF
RCOMP
CCOMP
FIGURE 4. USER PROGRAMMABLE PARAMETER SELECTION
TABLE 1. EXTERNAL COMPONENT SELECTION
V
L
C
(µF)
R
R
C
R
(kΩ)
R
(kΩ)
C
OUT
1
OUT
2
3
FB
FS
COMP
COMP
(pF)
(V)
12
5
(µH)
22
22
22
22
12
(kΩ)
90.9
90.9
90.9
90.9
90.9
(kΩ)
4.75
12.4
20
(pF)
22
27
27
27
27
2 x 22
115
150
100
100
100
70
470
470
470
470
470
47 + 22
47 + 22
47 + 22
47 + 22
DNP (Note 1)
DNP (Note 1)
DNP (Note 1)
DNP (Note 1)
3.3
2.5
1.8
28.7
45.5
NOTE:
1. Connect FS to VCC.
FN8870 Rev 0.00
July 1, 2016
Page 4 of 19
ISL854102
Functional Block Diagram
SS
EN
VIN
PG
POWER-
GOOD
LOGIC
FB
5M
VCC
BIAS
LDO
EN/SOFT-
START
BOOT
FB
FS
FAULT
LOGIC
500mV/A
600mV VREF
CURRENT SENSE
OSCILLATOR
PFM
GATE
DRIVE AND
DEADTIME
PWM
PWM
PWM/PFM
SELECT LOGIC
s
Q
Q
PHASE
PGND
FB
R
5M
CURRENT
SET
SYNC
ZERO CURRENT
DETECTION
450mV/T SLOPE
COMPENSATION
(PWM ONLY)
150k
54pF
INTERNAL
COMPENSATION
PACKAGE
PADDLE
INTERNAL = 50µA/V
EXTERNAL = 230µA/V
GND
COMP
FIGURE 5. FUNCTIONAL BLOCK DIAGRAM
Ordering Information
PART NUMBER
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Notes 2, 3, 4)
ISL854102FRZ
NOTES:
2. Add “-T” suffix for 6k unit or “-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
4102
-40 to +125
12 Ld DFN
L12.4x3
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL854102. For more information on MSL please see techbrief TB363.
TABLE 2. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
INPUT VOLTAGE
(V)
OUTPUT
CURRENT
PART NUMBER
ISL85412
ISL85413
ISL85415
ISL85418
ISL85410
ISL854102
COMPENSATION
Internal Only
SWITCHING FREQUENCY
Internal 700kHz
Internal 700kHz
EXT SYNC
No
SOFT-START
Internal
3.5 to 40
3.5 to 40
3 to 36
3 to 40
3 to 40
3 to 40
150mA
300mA
500mA
800mA
1A
Internal Only
No
Internal
Internal/External Internal 500kHz/external 300kHz to 2MHz
Internal/External Internal 500kHz/external 300kHz to 2MHz
Internal/External Internal 500kHz/external 300kHz to 2MHz
Internal/External Internal 500kHz/external 300kHz to 2MHz
Yes
Internal/External
Internal/External
Internal/External
Internal/External
Yes
Yes
1.2A
Yes
FN8870 Rev 0.00
July 1, 2016
Page 5 of 19
ISL854102
Absolute Maximum Ratings
Thermal Information
VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V (DC)
PHASE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to +44V (20ns)
EN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +43V
BOOT to PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
COMP, FS, PG, SYNC, SS, VCC to GND . . . . . . . . . . . . . . . . . . -0.3V to +5.9V
FB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +2.95V
ESD Rating
Thermal Resistance
DFN Package (Notes 5, 6) . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
42
(°C/W)
4.5
JA
JC
Recommended Operating Conditions
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3V to +40V
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . . . . 2kV
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . .1.5kV
Latch-Up (Tested per JESD-78A; Class 2, Level A) . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379 for details.
6. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
T
= -40°C to +125°C, V = 3V to 40V, unless otherwise noted. Typical values are at T = +25°C. Boldface
IN
A
A
limits apply across the junction temperature range, -40°C to +125°C
MIN
MAX
PARAMETER
SUPPLY VOLTAGE
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
UNIT
V
V
V
V
Voltage Range
V
I
3
40
V
µA
µA
V
IN
IN
IN
CC
IN
Quiescent Supply Current
Shutdown Supply Current
Voltage
V
= 0.7V, SYNC = 0V, f
= V
SW CC
80
2
Q
FB
I
EN = 0V, V = 40V (Note 7)
4
SD
IN
V
V
= 6V, I
IN OUT
= 0 to 10mA
4.5
5.1
5.7
CC
POWER-ON RESET
POR Threshold
V
Rising edge
Falling edge
2.75
2.6
2.95
V
V
CC
2.35
OSCILLATOR
Nominal Switching Frequency
f
FS pin = V
CC
430
240
500
300
2000
150
90
570
360
kHz
kHz
kHz
ns
SW
Resistor from FS pin to GND = 340kΩ
Resistor from FS pin to GND = 32.4kΩ
Minimum Off-Time
t
V
= 3V
OFF
IN
(Note 10)
= 100kΩ
Minimum On-Time
t
ns
ON
FS Voltage
V
R
0.39
300
100
0.4
0.41
V
FS
FS
Synchronization Frequency
SYNC Pulse Width
SYNC
2000
kHz
ns
ERROR AMPLIFIER
Error Amplifier Transconductance Gain
g
External compensation
Internal compensation
165
230
50
295
µA/V
µA/V
nA
m
FB Leakage Current
Current Sense Amplifier Gain
FB Voltage
V
= 0.6V
1
150
0.54
FB
R
0.46
0.590
0.590
0.5
V/A
V
T
T
= -40°C to +85°C
= -40°C to +125°C
0.599
0.599
0.606
0.607
A
T
V
A
FN8870 Rev 0.00
July 1, 2016
Page 6 of 19
ISL854102
Electrical Specifications
T
= -40°C to +125°C, V = 3V to 40V, unless otherwise noted. Typical values are at T = +25°C. Boldface
IN
A
A
limits apply across the junction temperature range, -40°C to +125°C (Continued)
MIN
MAX
PARAMETER
POWER-GOOD
SYMBOL
TEST CONDITIONS
(Note 9)
TYP
(Note 9)
UNIT
%
%
%
%
%
Lower PG Threshold - VFB Rising
Lower PG Threshold - VFB Falling
Upper PG Threshold - VFB Rising
Upper PG Threshold - VFB Falling
PG Propagation Delay
90
86
94
82.5
107
116.5
112
10
120
Percentage of the soft-start time
PG Low Voltage
I
= 3mA, EN = V , VFB = 0V
CC
0.05
0.3
V
SINK
TRACKING AND SOFT-START
Soft-Start Charging Current
Internal Soft-Start Ramp Time
FAULT PROTECTION
I
4.2
1.5
5.5
2.4
6.5
3.4
µA
SS
EN/SS = V
CC
ms
Thermal Shutdown Temperature
T
Rising threshold
Hysteresis
150
20
°C
°C
SD
T
HYS
Current Limit Blanking Time
t
17
Clock
OCON
pulses
Overcurrent and Auto Restart Period
Positive Peak Current Limit
PFM Peak Current Limit
Zero Cross Threshold
Negative Current Limit
POWER MOSFET
t
8
SS cycle
OCOFF
I
(Note 8)
(Note 8)
1.4
1.6
0.4
15
1.8
0.5
A
A
PLIMIT
I
0.34
PK_PFM
mA
A
I
-0.67
-0.6
-0.53
NLIMIT
High-Side
R
I
I
= 100mA, V = 5V
CC
250
90
350
130
300
mΩ
mΩ
nA
HDS
PHASE
Low-Side
R
= 100mA, V = 5V
CC
LDS
PHASE
PHASE Leakage Current
PHASE Rise Time
EN = PHASE = 0V
= 40V
t
V
10
ns
RISE
IN
EN/SYNC
Input Threshold
Falling edge, logic low
Rising edge, logic high
EN = 0V/40V
0.4
1
V
1.2
1.4
0.5
V
EN Logic Input Leakage Current
SYNC Logic Input Leakage Current
-0.5
µA
nA
µA
SYNC = 0V
10
100
1.55
SYNC = 5V
1.0
NOTES:
7. Test Condition: V = 40V, FB forced above regulation point (0.6V), no switching and power MOSFET gate charging current not included.
IN
8. Established by both current sense amplifier gain test and current sense amplifier output test at I = 0A.
L
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Minimum On-Time required to maintain loop stability.
FN8870 Rev 0.00
July 1, 2016
Page 7 of 19
ISL854102
Efficiency Curves
f
= 500kHz, T = +25°C
A
SW
100
95
90
85
80
75
70
65
60
55
50
95
90
85
80
75
70
65
60
55
50
VIN=12V
VIN=15V
VIN=24V
VIN=12V
VIN=15V
VIN=24V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
FIGURE 6. EFFICIENCY vs LOAD, PFM, V
= 5V, L = 22µH
1
FIGURE 7. EFFICIENCY vs LOAD, PWM, V
= 5V, L = 22µH,
OUT
OUT 1
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VIN=12V
VIN=15V
VIN=24V
VIN=12V
VIN=15V
VIN=24V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
FIGURE 8. EFFICIENCY vs LOAD, PFM, V
= 3.3V, L = 22µH
1
FIGURE 9. EFFICIENCY vs LOAD, PWM, V
= 3.3V, L = 22µH
1
OUT
OUT
5.100
5.080
5.060
5.040
5.020
5.000
4.980
4.960
4.940
4.920
4.900
5.021
VIN=12V
VIN=15V
VIN=24V
VIN=33V
VIN=12V
VIN=15V
VIN=24V
VIN=33V
5.019
5.017
5.015
5.013
5.011
5.009
5.007
5.005
5.003
5.001
4.999
4.997
4.995
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1.1 1.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
OUTPUT LOAD (A)
FIGURE 10. V
REGULATION vs LOAD, PFM, V
= 5V,
FIGURE 11. V
OUT
REGULATION vs LOAD, PWM, V
= 5V
OUT
OUT
OUT
FN8870 Rev 0.00
July 1, 2016
Page 8 of 19
ISL854102
Efficiency Curves
f
= 500kHz, T = +25°C (Continued)
SW A
3.450
3.350
VIN=12V
VIN=15V
VIN=24V
VIN=33V
VIN=12V
3.430
3.347
3.344
3.341
3.338
3.335
3.332
3.329
3.326
3.323
3.320
VIN=15V
3.410
VIN=24V
3.390
VIN=33V
3.370
3.350
3.330
3.310
3.290
3.270
3.250
0
0.2
0.4
0.6
0.8
1
1.2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
OUTPUT LOAD (A)
1
1.1 1.2
OUTPUT LOAD (A)
FIGURE 12. V
OUT
REGULATION vs LOAD, PFM, V
= 3.3V
FIGURE 13. V
OUT
REGULATION vs LOAD vs LOAD, PWM, V
= 3.3V
OUT
OUT
Measurements
f
= 500kHz, V = 24V, V = 3.3V, T = +25°C
IN OUT A
SW
LX 20V/DIV
LX 20V/DIV
V
2V/DIV
OUT
V
2V/DIV
OUT
EN 20V/DIV
PG 2V/DIV
EN 20V/DIV
PG 2V/DIV
5ms/DIV
5ms/DIV
FIGURE 14. START-UP AT NO LOAD, PFM
FIGURE 15. START-UP AT NO LOAD, PWM
LX 20V/DIV
LX 20V/DIV
V
2V/DIV
V
2V/DIV
OUT
OUT
EN 20V/DIV
PG 2V/DIV
EN 20V/DIV
PG 2V/DIV
100ms/DIV
100ms/DIV
FIGURE 17. SHUTDOWN AT NO LOAD, PWM
FIGURE 16. SHUTDOWN AT NO LOAD, PFM
FN8870 Rev 0.00
July 1, 2016
Page 9 of 19
ISL854102
Measurements
f
= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)
IN OUT A
SW
LX 20V/DIV
LX 20V/DIV
V
2V/DIV
1A/DIV
OUT
V
2V/DIV
1A/DIV
OUT
I
L
I
L
PG 2V/DIV
PG 2V/DIV
5ms/DIV
200µs/DIV
FIGURE 18. START-UP AT 1.2A
FIGURE 19. SHUTDOWN AT 1.2A
LX 20V/DIV
LX 20V/DIV
V
20mV/DIV
OUT
V
20mV/DIV
20mA/DIV
OUT
I
20mA/DIV
L
I
L
1µs/DIV
10ms/DIV
FIGURE 20. STEADY STATE AT NO LOAD, PFM
FIGURE 21. STEADY STATE AT NO LOAD, PWM
LX 20V/DIV
LX 20V/DIV
V
50mV/DIV
OUT
V
10mV/DIV
OUT
I
200mA/DIV
L
I
1A/DIV
L
10µs/DIV
1µs/DIV
FIGURE 22. STEADY STATE AT 1.2A LOAD
FIGURE 23. LIGHT LOAD OPERATION AT 20mA, PFM
FN8870 Rev 0.00
July 1, 2016
Page 10 of 19
ISL854102
Measurements
f
= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)
IN OUT A
SW
LX 20V/DIV
V
100mV/DIV
OUT
V
10mV/DIV
OUT
I
200mA/DIV
L
I
1A/DIV
L
1µs/DIV
200µs/DIV
FIGURE 25. LOAD TRANSIENT, PFM
FIGURE 24. LIGHT LOAD OPERATION AT 20mA
LX 20V/DIV
V
100mV/DIV
OUT
V
2V/DIV
OUT
I
1A/DIV
L
I
1A/DIV
L
PG 5V/DIV
200µs/DIV
50µs/DIV
FIGURE 26. LOAD TRANSIENT, PWM
FIGURE 27. OVERCURRENT PROTECTION, PWM
LX 20V/DIV
LX 20V/DIV
V
2V/DIV
OUT
SYNC 2V/DIV
I
1A/DIV
L
PG 5V/DIV
200ns/DIV
10ms/DIV
FIGURE 29. SYNC AT 1.2A LOAD, PWM
FIGURE 28. OVERCURRENT PROTECTION HICCUP, PWM
FN8870 Rev 0.00
July 1, 2016
Page 11 of 19
ISL854102
Measurements
f
= 500kHz, V = 24V, V = 3.3V, T = +25°C (Continued)
IN OUT A
SW
LX 20V/DIV
LX 20V/DIV
V
I
5V/DIV
OUT
V
5V/DIV
OUT
I
1A/DIV
500mA/DIV
PG 2V/DIV
L
L
PG 2V/DIV
200µs/DIV
20µs/DIV
FIGURE 31. NEGATIVE CURRENT LIMIT RECOVERY, PWM
FIGURE 30. NEGATIVE CURRENT LIMIT, PWM
Power-Good
Detailed Description
PG is the open-drain output of a window comparator that
continuously monitors the buck regulator output voltage via the
FB pin. PG is actively held low when EN is low and during the
buck regulator soft-start period. After the soft-start period
completes, PG becomes high impedance provided the FB pin is
within the range specified in the “Electrical Specifications” on
page 7. Should FB exit the specified window, PG will be pulled
low until FB returns. Over-temperature faults also force PG low
until the fault condition is cleared by an attempt to soft-start.
There is an internal 5MΩ internal pull-up resistor.
The ISL854102 combines a synchronous buck PWM controller
with integrated power switches. The buck controller drives
internal high-side and low-side N-channel MOSFETs to deliver
load current up to 1.2A. The buck regulator can operate from an
unregulated DC source, such as a battery, with a voltage ranging
from +3V to +40V. An internal LDO provides bias to the low
voltage portions of the IC.
Peak current mode control is utilized to simplify feedback loop
compensation and reject input voltage variation. User selectable
internal feedback loop compensation further simplifies design.
The ISL854102 switches at a default of 500kHz.
PWM Control Scheme
The ISL854102 employs peak current-mode Pulse-Width
Modulation (PWM) control for fast transient response and
pulse-by-pulse current limiting, as shown in the “Functional Block
Diagram” on page 5. The current loop consists of the current
sensing circuit, slope compensation ramp, PWM comparator,
oscillator and latch. Current sense transresistance is typically
500mV/A and slope compensation rate, Se, is typically 450mV/T,
where T is the switching cycle period. The control reference for the
The buck regulator is equipped with an internal current sensing
circuit and the peak current limit threshold is typically set at
1.6A.
Power-On Reset
The ISL854102 automatically initializes upon receipt of the input
power supply and continually monitors the EN pin state. If EN is
held below its logic rising threshold, the IC is held in shutdown
current loop comes from the error amplifier’s output (V
).
COMP
and consumes typically 2µA from the V supply. If EN exceeds
IN
its logic rising threshold, the regulator will enable the bias LDO
and begins to monitor the VCC pin voltage. When the VCC pin
voltage clears its rising POR threshold, the controller will initialize
A PWM cycle begins when a clock pulse sets the PWM latch and the
upper FET is turned on. Current begins to ramp up in the upper FET
and inductor. This current is sensed (V ), converted to a voltage
CSA
the switching regulator circuits. If V never clears the rising POR
and summed with the slope compensation signal. This combined
CC
threshold, the controller will not allow the switching regulator to
signal is compared to V
and when the signal is equal to V ,
COMP
COMP
operate. If V falls below its falling POR threshold while the
switching regulator is operating, the switching regulator will be
the latch is reset. Upon latch reset, the upper FET is turned off and
the lower FET turned on allowing current to ramp down in the
inductor. The lower FET will remain on until the clock initiates
another PWM cycle. Figure 33 on page 13 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the current sense and slope compensation
signal.
CC
shut down until V returns.
CC
Soft-Start
To avoid large inrush current, V
is slowly increased at start-up
OUT
to its final regulated value. Soft-start time is determined by the
SS pin connection. If SS is pulled to VCC, an internal 2ms timer is
selected for soft-start. For other soft-start times, simply connect
a capacitor from SS to GND. In this case, a 5.5µA current pulls up
the SS voltage and the FB pin will follow this ramp until it reaches
the 600mV reference level. Soft-start time for this case is
described by Equation 1:
The output voltage is regulated as the error amplifier varies
V
and thus varies the output inductor current. The error
COMP
amplifier is a transconductance type and its output (COMP) is
terminated with a series RC network to GND. This termination is
internal (150k/54pF) if the COMP pin is tied to VCC. Additionally,
the transconductance for COMP = V is 50µA/V vs 230µA/V for
CC
external RC connection. Its noninverting input is internally
connected to a 600mV reference voltage and its inverting input is
(EQ. 1)
Timems = CnF 0.109
FN8870 Rev 0.00
July 1, 2016
Page 12 of 19
ISL854102
PWM
DCM
PULSE SKIP
DCM
PWM
CLOCK
8 CYCLES
I
L
LOAD CURRENT
0
V
OUT
FIGURE 32. DCM MODE OPERATION WAVEFORMS
connected to the output voltage via the FB pin and its associated
divider network.
Due to the pulsed current nature of PFM mode, the converter can
supply limited current to the load. Should load current rise
beyond the limit, V
will begin to decline. A second comparator
OUT
signals an FB voltage 1% lower than the 600mV reference and
forces the converter to return to PWM operation.
V
COMP
Output Voltage Selection
V
CSA
The regulator output voltage is easily programmed using an
external resistor divider to scale V
relative to the internal
OUT
DUTY
reference voltage. The scaled voltage is applied to the inverting
input of the error amplifier; refer to Figure 34.
CYCLE
I
The output voltage programming resistor, R , depends on the
3
L
value chosen for the feedback resistor, R , and the desired
2
output voltage, V , of the regulator. Equation 3 describes the
OUT
V
OUT
relationship between V
and resistor values.
OUT
R x0.6V
2
----------------------------------
=
(EQ. 3)
R
3
V
– 0.6V
OUT
FIGURE 33. PWM OPERATION WAVEFORMS
If the desired output voltage is 0.6V, then R is left unpopulated
3
Light Load Operation
At light loads, converter efficiency may be improved by enabling
variable frequency operation (PFM). Connecting the SYNC pin to
GND will allow the controller to choose such operation
and R is 0Ω.
2
V
OUT
R
R
2
automatically when the load current is low. Figure 32 shows the
DCM operation. The IC enters the DCM mode of operation when 8
consecutive cycles of inductor current crossing zero are detected.
This corresponds to a load current equal to 1/2 the peak-to-peak
inductor ripple current and set by Equation 2:
FB
-
+
EA
3
0.6V
REFERENCE
V
1 – D
(EQ. 2)
OUT
----------------------------------
=
I
OUT
2L f
SW
Where D = duty cycle, f
SW
= switching frequency, L = inductor
= output voltage.
FIGURE 34. EXTERNAL RESISTOR DIVIDER
value, I
= output loading current, V
OUT
OUT
Protection Features
While operating in PFM mode, the regulator controls the output
voltage with a simple comparator and pulsed FET current. A
comparator signals the point at which FB is equal to the 600mV
reference at which time the regulator begins providing pulses of
current until FB is moved above the 600mV reference by 1%. The
current pulses are approximately 300mA and are issued at a
frequency equal to the converters programmed PWM operating
frequency.
The ISL854102 is protected from overcurrent, negative
overcurrent and over-temperature. The protection circuits
operate automatically.
Overcurrent Protection
During PWM on-time, current through the upper FET is monitored
and compared to a nominal 1.6A peak overcurrent limit. In the
event that current reaches the limit, the upper FET will be turned
FN8870 Rev 0.00
July 1, 2016
Page 13 of 19
ISL854102
off until the next switching cycle. In this way, FET peak current is
always well limited.
Application Guidelines
Simplifying the Design
While the ISL854102 offers user programmed options for most
parameters, the easiest implementation with fewest
components involves selecting internal settings for SS, COMP
and FS. Table 1 on page 4 provides component value selections
for a variety of output voltages and will allow the designer to
implement solutions with a minimum of effort.
If the overcurrent condition persists for 17 sequential clock
cycles, the regulator will begin its hiccup sequence. In this case,
both FETs will be turned off and PG will be pulled low. This
condition will be maintained for 8 soft-start periods after which
the regulator will attempt a normal soft-start.
Should the output fault persist, the regulator will repeat the
hiccup sequence indefinitely. There is no danger even if the
output is shorted during soft-start.
Operating Frequency
ths
If V
OUT
is shorted very quickly, FB may collapse below 5/8 of
The ISL854102 operates at a default switching frequency of
500kHz if the FS pin is tied to VCC. Tie a resistor from the FS pin
to GND to program the switching frequency from 300kHz to
2MHz, as shown in Equation 4.
its target value before 17 cycles of overcurrent are detected. The
ISL854102 recognizes this condition and will begin to lower its
switching frequency proportional to the FB pin voltage. This
insures that under no circumstance (even with V
the inductor current run away.
near 0V) will
OUT
R
k = 108.75k t – 0.2s 1s
(EQ. 4)
FS
Where:
Negative Current Limit
t is the switching period in µs.
Should an external source somehow drive current into V , the
OUT
controller will attempt to regulate V
OUT
by reversing its inductor
400
current to absorb the externally sourced current. In the event that
the external source is low impedance, current may be reversed to
unacceptable levels and the controller will initiate its negative
current limit protection. Similar to normal overcurrent, the
negative current protection is realized by monitoring the current
through the lower FET. When the valley point of the inductor
current reaches negative current limit, the lower FET is turned off
and the upper FET is forced on until current reaches the Positive
current limit or an internal clock signal is issued. At this point, the
lower FET is allowed to operate. Should the current again be
pulled to the negative limit on the next cycle, the upper FET will
300
200
100
0
th
again be forced on and current will be forced to 1/6 of the
positive current limit. At this point the controller will turn off both
FETs and wait for COMP to indicate return to normal operation.
During this time, the controller will apply a 100Ω load from
PHASE to PGND and attempt to discharge the output. Negative
current limit is a pulse-by-pulse style operation and recovery is
automatic.
250
500
750
1000
1250
(kHz)
1500
1750
2000
f
SW
FIGURE 35. R SELECTION vs f
FS
SW
Synchronization Control
Over-Temperature Protection
The frequency of operation can be synchronized up to 2MHz by
an external signal applied to the SYNC pin. The rising edge on the
SYNC triggers the rising edge of PHASE. To properly synchronize,
the external source must be at least 10% greater than the
programmed free running IC frequency.
Over-temperature protection limits maximum junction
temperature in the ISL854102. When junction temperature (T )
J
exceeds +150°C, both FETs are turned off and the controller
waits for the temperature to decrease by approximately 20°C.
During this time PG is pulled low. When temperature is within an
acceptable range, the controller will initiate a normal soft-start
sequence. For continuous operation, the +125°C junction
temperature rating should not be exceeded.
Output Inductor Selection
The inductor value determines the converter’s ripple current.
Choosing an inductor current requires a somewhat arbitrary
choice of ripple current, I. A reasonable starting point is 30% of
total load current. The inductor value can then be calculated
using Equation 5:
Boot Undervoltage Protection
If the boot capacitor voltage falls below 1.8V, the boot
undervoltage protection circuit will turn on the lower FET for
400ns to recharge the capacitor. This operation may arise during
long periods of no switching such as PFM no load situations. In
V
– V
V
OUT
V
IN
IN
f
OUT
------------------------------- ---------------
(EQ. 5)
L =
I
SW
PWM operation near dropout (V near V
), the regulator may
IN OUT
Increasing the value of inductance reduces the ripple current and
thus, the ripple voltage. However, the larger inductance value
may reduce the converter’s response time to a load transient.
hold the upper FET on for multiple clock cycles. To prevent the
boot capacitor from discharging, the lower FET is forced on for
approximately 200ns every 10 clock cycles.
FN8870 Rev 0.00
July 1, 2016
Page 14 of 19
ISL854102
The inductor current rating should be such that it will not saturate
in overcurrent conditions. For typical ISL854102 applications,
inductor values generally lie in the 10µH to 47µH range. In
^
^
L
R
LP
^
P
i
i
L
v
in
o
^
V
d
^
^
1:D
in
general, higher V
will mean higher inductance.
I d
L
OUT
V
in
Rc
Co
+
R
T
Buck Regulator Output Capacitor Selection
Ro
An output capacitor is required to filter the inductor current. The
current mode control loop allows the use of low ESR ceramic
capacitors and thus supports very small circuit implementations
on the PC board. Electrolytic and polymer capacitors may also be
used.
T(S)
i
^
d
K
Fm
While ceramic capacitors offer excellent overall performance
and reliability, the actual in-circuit capacitance must be
considered. Ceramic capacitors are rated using large
peak-to-peak voltage swings and with no DC bias. In the DC/DC
converter application, these conditions do not reflect reality. As a
result, the actual capacitance may be considerably lower than
the advertised value. Consult the manufacturers datasheet to
determine the actual in-application capacitance. Most
manufacturers publish capacitance vs DC bias so that this effect
can be easily accommodated. The effects of AC voltage are not
frequently published, however, an assumption of ~20% further
reduction will generally suffice. The result of these
considerations may mean an effective capacitance 50% lower
than nominal and this value should be used in all design
calculations. Nonetheless, ceramic capacitors are a very good
choice in many applications due to their reliability and extremely
low ESR.
T (S)
v
+
He(S)
^
V
comp
-Av(S)
FIGURE 36. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK
REGULATOR
Vo
R
C
2
3
3
V
FB
-
V
COMP
GM
V
REF
+
R
R
C
6
C
7
6
The following equations allow calculation of the required
capacitance to meet a desired ripple voltage level. Additional
capacitance may be used.
For the ceramic capacitors (low ESR):
FIGURE 37. TYPE II COMPENSATOR
I
(EQ. 6)
is the
------------------------------------
V
=
Figure 37 shows the type II compensator and its transfer function
is expressed as shown in Equation 8:
OUTripple
C
OUT
8 f
SW
Where I is the inductor’s peak-to-peak ripple current, f
SW
S
S
------------
------------
1 +
1 +
ˆ
switching frequency and C
is the output capacitor.
GM R
v
OUT
COMP
3
cz1
cz2
------------------- -------------------------------------------------------- --------------------------------------------------------------
A S=
=
v
ˆ
C + C R + R
S
S
v
6
7
2
3
FB
------------
------------
If using electrolytic capacitors then:
S 1 +
1 +
cp1
cp2
(EQ. 7)
V
= I*ESR
OUTripple
(EQ. 8)
Where,
Loop Compensation Design
C
+ C
R + R
2 3
C R R
3 2 3
1
1
6
7
--------------
--------------
----------------------
----------------------
=
=
,
=
=
cp2
When COMP is not connected to VCC, the COMP pin is active for
external loop compensation. The ISL854102 uses constant
frequency peak current mode control architecture to achieve a
fast loop transient response. An accurate current sensing pilot
device in parallel with the upper MOSFET is used for peak current
control signal and overcurrent protection. The inductor is not
considered as a state variable since its peak current is constant,
and the system becomes a single order system. It is much easier
to design a Type II compensator to stabilize the loop than to
implement voltage mode control. Peak current mode control has
an inherent input voltage feed-forward function to achieve good
line regulation. Figure 36 shows the small signal model of the
synchronous buck regulator.
cz1
cz2
cp1
R C
R C
R C C
6
6
2
3
6
6
7
Compensator design goal:
High DC gain
Choose loop bandwidth f less than 100kHz
c
Gain margin: >10dB
Phase margin: >40°
FN8870 Rev 0.00
July 1, 2016
Page 15 of 19
ISL854102
The compensator design procedure is as follows:
60
45
30
15
0
The loop gain at crossover frequency of f has a unity gain.
c
Therefore, the compensator resistance R is determined by
6
Equation 9.
2f V C R
o o t
3
c
(EQ. 9)
---------------------------------
= 22.7510 f V C
c o o
R
=
6
GM V
FB
Where GM is the transconductance, g , of the voltage error
m
amplifier in each phase. Compensator capacitor C is then given
6
by Equation 10.
-15
-30
R C
V C
o o
R C
o
R
o
1
c
o
(EQ. 10)
-------------- --------------
,C = max(--------------,---------------------)
7
C
=
=
6
I R
o 6
R
f
R
6
6
SW 6
100
1k
10k
100k
1M
FREQUENCY (Hz)
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 10. An optional zero can boost the phase margin. CZ2
180
150
120
90
is a zero due to R and C .
2
3
Put compensator zero 2 to 5 times f .
c
1
(EQ. 11)
---------------
C =
3
f R
c
2
Example: V = 12V, V = 5V, I = 1.2A, f
IN
= 500kHz,
O
O
SW
c
60
R = 90.9kΩ, C = 22µF/5mΩ, L = 39µH, f = 50kHz, then
2
o
compensator resistance R :
6
30
3
(EQ. 12)
R
= 22.7510 50kHz 5V 22F = 125.12k
6
0
100
1k
10k
100k
1M
It is acceptable to use 124kΩ as the closest standard value for
FREQUENCY (Hz)
R .
6
FIGURE 38. SIMULATED LOOP GAIN
5V 22F
1A 124k
(EQ. 13)
------------------------------
= 0.88nF
C
6
=
5m 22F
124k
1
C = max(--------------------------------,---------------------------------------------------- )= (0.88pF,5.1pF)
7
500kHz 124k
(EQ. 14)
It is also acceptable to use the closest standard values for C and
6
C . There is approximately 3pF parasitic capacitance from V
7
COMP
to GND; Therefore, C is optional. Use C = 1500pF and
7
6
C = OPEN.
7
1
(EQ. 15)
--------------------------------------------------
C =
= 70pF
3
50kHz 90.9k
Use C = 68pF. Note that C may increase the loop bandwidth
3
3
from previous estimated value. Figure 38 shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop bandwidth
with a 61° phase margin and 6dB gain margin. It may be more
desirable to achieve an increased gain margin. This can be
accomplished by lowering R by 20% to 30%. In practice,
6
ceramic capacitors have significant derating on voltage and
temperature, depending on the type. Please refer to the ceramic
capacitor datasheet for more details.
FN8870 Rev 0.00
July 1, 2016
Page 16 of 19
ISL854102
Place the feedback divider close to the FB pin and do not route
any feedback components near PHASE or BOOT. If external
components are used for SS, COMP or FS the same advice
applies.
Layout Considerations
Proper layout of the power converter will minimize EMI and noise,
and insure first pass success of the design. PCB layouts are
provided in multiple formats on the Intersil web site. In addition,
Figure 39 will make clear the important points in PCB layout. In
reality, PCB layout of the ISL854102 is quite simple.
CSS
RFS
A multilayer printed circuit board with GND plane is
recommended. Figure 39 shows the connections of the critical
N
CVIN
components in the converter. Note that capacitors C and C
IN
OUT
could each represent multiple physical capacitors. The most
critical connections are to tie the PGND pin to the package GND
pad and then use vias to directly connect the GND pad to the
system GND plane. This connection of the GND pad to system
plane insures a low impedance path for all return current, as well
as an excellent thermal path to dissipate heat. With this
connection made, place the high frequency MLCC input capacitor
near the VIN pin and use vias directly at the capacitor pad to tie
the capacitor to the system GND plane.
L1
C
COUT
The boot capacitor is easily placed on the PCB side opposite the
controller IC and 2 vias directly connect the capacitor to BOOT
and PHASE.
Place a 1µF MLCC near the VCC pin and directly connect its
return with a via to the system GND plane.
0.47”
FIGURE 39. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
FN8870 Rev 0.00
July 1, 2016
Page 17 of 19
ISL854102
Revision History The revision history provided is for informational purposes only and is believed to be accurate, however, not
warranted. Please go to web to make sure you have the latest revision.
DATE
REVISION
FN8870.0
CHANGE
July 1, 2016
Initial Release
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2016. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8870 Rev 0.00
July 1, 2016
Page 18 of 19
ISL854102
Package Outline Drawing
L12.4x3
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 3/15
3.30 +0.10/-0.15
2X 2.50
4.00
A
6
10X 0.50
PIN 1
PIN #1 INDEX AREA
6
INDEX AREA
12 X 0.40 ±0.10
1.70 +0.10/-0.15
B
1
6
3.00
(4X)
0.15
12
7
0.10M C A B
TOP VIEW
4 12 x 0.23 +0.07/-0.05
BOTTOM VIEW
SEE DETAIL "X"
(3.30)
0.10 C
C
6
1
1.00 MAX
SEATING PLANE
0.08
C
SIDE VIEW
2.80
(1.70)
5
0.2 REF
C
12 X 0.60
0. 00 MIN.
0. 05 MAX.
7
12
(12 X 0.23)
(10X 0.5)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance: Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature and
may be located on any of the 4 sides (or ends).
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6.
7. Compliant to JEDEC MO-229 V4030D-4 issue E.
FN8870 Rev 0.00
July 1, 2016
Page 19 of 19
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