ISL8703IBZT [RENESAS]
DSP-ADDRESS SEQUENCER, PDSO14, PLASTIC, MS-012AB, SOIC-14;
| 型号： | ISL8703IBZT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DSP-ADDRESS SEQUENCER, PDSO14, PLASTIC, MS-012AB, SOIC-14 双倍数据速率 光电二极管 |
| 文件： | 总12页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL8700, ISL8701, ISL8702, ISL8702A,
ISL8703, ISL8704, ISL8705
®
Data Sheet
March 14, 2006
FN9250.0
Adjustable Quad Sequencer
Features
The ISL8700, ISL8701, ISL8702, ISL8702A, ISL8703,
ISL8704, ISL8705 family of ICs provide four delay adjustable
sequenced outputs while monitoring an input voltage all with
a minimum of external components.
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
High performance DSP, FPGA, µP and various subsystems
require input power sequencing for proper functionality at
initial power up and the ISL870X provides this function while
monitoring the distributed voltage for over and undervoltage
compliance.
• Under and Overvoltage Adjustable Delay to Auto Start
Sequence
• I/O Options
ENABLE (ISL8700, ISL8702, ISL8702A, ISL8704) and
ENABLE# (ISL8701, ISL8703, ISL8705)
SEQ_EN (ISL8702, ISL8702A, ISL8703) and SEQ_EN#
(ISL8704, ISL8705)
The ISL8700 and ISL8701 operate over the +2.5V to +24V
nominal voltage range, whereas the ISL8702 operates over
the 2.5V to +12V range. All three have a user adjustable
time from UV and OV voltage compliance to sequencing
start via an external capacitor when in auto start mode and
adjustable time delay to subsequent ENABLE output signal
via external resistors.
• Voltage Compliance Fault Output
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Power Supply Sequencing
Additionally, ISL8702A, ISL8703, ISL8704 and ISL8705
provide I/O for sequencing on and off operation (SEQ_EN)
and for voltage window compliance reporting (FAULT) over
the +2.5V to +24V voltage range. The ISL8702 also has this
feature but operates over the 2.5V to +12V range.
• System Timing Function
Pinout
ISL870X
(14 LD SOIC)
TOP VIEW
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870X provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
14
13
ENABLE_D
ENABLE_C
ENABLE_B
1
2
3
4
5
6
7
VIN
TD
12 TC
ENABLE_A
OV
TB
11
Ordering Information
TIME
10
9
PARTNUMBER
(Notes 1, 2)
PART
TEMP.
PACKAGE
(Pb-free)
PKG.
UV
SEQ_EN (NC on ISL8700/01)
FAULT (NC on ISL8700/01)
MARKING RANGE (°C)
DWG. #
GND
8
ISL8700IBZ*
ISL8701IBZ*
ISL8702IBZ*
ISL8702AIBZ-T
ISL8700IBZ
ISL8701IBZ
ISL8702IBZ
-40 to +85 14 Ld SOIC
-40 to +85 14 Ld SOIC
-40 to +85 14 Ld SOIC
-40 to +85 14 Ld SOIC
M14.15
M14.15
M14.15
M14.15
ISL8701, ISL8703, ISL8705 PINS 1-4 ARE ENABLE# FUNCTION
ISL8704, ISL8705 PIN 9 IS SEQ_EN# FUNCTION
(Tape and Reel)
2.5-24V (12Vmax for ISL8702)
ISL8703IBZ*
ISL8704IBZ*
ISL8705IBZ*
ISL8703IBZ
ISL8704IBZ
ISL8705IBZ
-40 to +85 14 Ld SOIC
-40 to +85 14 Ld SOIC
-40 to +85 14 Ld SOIC
M14.15
M14.15
M14.15
EN
DC/DC
Vo1
Vo2
Vo3
V04
VIN
SEQ_EN *
Ru
ENABLE_A
ENABLE_B
ENABLE_C
ENABLE_D
EN
DC/DC
ISL870XEVAL1 Evaluation Platform
UV
*Add “-T” suffix for tape and reel.
NOTES:
Rm
Rl
FAULT *
OV
EN
EN
DC/DC
GND TB TC TD TIME
1. Part Numbers in Bold are available now, others will soon be available,
contact factory for availability schedule.
2. Intersil Pb-free plus anneal products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DC/DC
* SEQ_EN and FAULT are not available on ISL8700 and ISL8701
FIGURE 1. ISL870X IMPLEMENTATION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 3)
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
(SOIC Lead Tips Only)
V
, ENABLE(#), FAULT . . . . . . . . . . . . . . . . . . . . . . . 27V, to -0.3V
θ
(°C/W)
IN
JA
130
ISL8702 V , ENABLE(#), FAULT . . . . . . . . . . . . . . . . 14V, to -0.3V
IN
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V +0.3V, to -0.3V
IN
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 2.5V to 24V
ISL8702 Supply Voltage Range (Nominal) . . . . . . . . . . 2.5V to 12V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications Nominal V = 2.5V to +24V, T = T = -40°C - 85°C, Unless Otherwise Specified.
IN
A
J
ISL8702 V = 2.5V to +12V
IN
PARAMETER
UV AND OV INPUTS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UV/OV Rising Threshold
UV/OV Falling Threshold
UV/OV Hysteresis
V
1.16
1.21
1.10
104
10
1.28
V
V
UVRvth
V
1.06
1.18
UVFvth
V
V
- V
UVFvth
-
-
-
-
mV
nA
UVhys
UVRvth
UV/OV Input Current
I
UV
TIME, ENABLE/ENABLE# OUTPUTS
TIME Pin Charging Current
TIME Pin Threshold
I
-
2.6
2.0
30
-
µA
V
TIME
V
1.9
2.25
TIME_VTH
VINSEQpd
Time from V Valid to ENABLE_A
IN
t
SEQ_EN = high, C
SEQ_EN = high, C
SEQ_EN = high, C
= open
= 10nF
= 500nF
-
-
µs
ms
ms
µs
Ω
TIME
TIME
TIME
t
t
-
7.7
435
-
-
VINSEQpd_10
VINSEQpd500
-
-
-
Time from V Invalid to Shutdown
IN
t
UV or OV to simultaneous shutdown
1
shutdown
ENABLE Output Resistance
ENABLE Output Low
R
I
I
= 1mA
= 1mA
-
100
0.1
15
-
EN
ENABLE
Vol
-
-
V
ENABLE
ENABLE Pull-down Current
Delay to Subsequent ENABLE Turn-on/off
I
ENABLE = 1V
10
155
3.5
-
-
240
6
mA
ms
ms
ms
pulld
t
R
R
R
= 120kΩ
= 3kΩ
= 0Ω
195
4.7
0.5
del_120
TX
TX
TX
t
del_3
t
-
del_0
SEQUENCE ENABLE AND FAULT I/O
V
V
Valid to FAULT Low
t
15
-
30
0.5
15
50
µs
µs
mA
V
IN
IN
FLTL
Invalid to FAULT High
t
-
-
FLTH
FAULT Pull-down Current
FAULT = 1V
10
-
SEQ_EN Pull-up Voltage
V
SEQ_EN open
V
-
SEQ
IN
SEQ_EN Low Threshold Voltage
SEQ_EN High Threshold Voltage
Delay to ENABLE_A Deasserted
Vil
-
-
-
0.3
-
V
SEQ_EN
Vih
1.2
-
V
SEQ_EN
SEQ_EN_ENA
t
SEQ_EN low to ENABLE_A low
0.2
1
µs
FN9250.0
2
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Electrical Specifications Nominal V = 2.5V to +24V, T = T = -40°C - 85°C, Unless Otherwise Specified.
IN
IN
A
J
ISL8702 V = 2.5V to +12V (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS
IC Supply Current
I
V
V
V
V
= 2.2V
-
-
-
-
191
246
286
2.08
-
400
-
µA
µA
µA
V
VIN_2.2V
IN
IN
IN
IN
I
= 12V
VIN_12V
VIN_24V
I
= 24V
V
Power On Reset
V
low to high
2.5
IN
IN_POR
Pin Descriptions
PINS
870 870 8702 870 870 870
0
1
8702A
3
4
5
PIN NAME
FUNCTION DESCRIPTION
NA
1
NA
1
NA
1
ENABLE#_ Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701, ISL8703, ISL8705. Tracks V upon bias.
D
IN
1
NA
2
NA
2
1
NA
2
NA
2
1
NA
2
NA ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output to
sequence off for the ISL8700, ISL8702, ISL8704. Pulls low with V < 1V.
IN
2
ENABLE#_ Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
C
off after ENABLE#_D for the ISL8701, ISL8703, ISL8705. Tracks V upon bias.
IN
NA
3
NA
3
NA ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700, ISL8702, ISL8704. Pulls low with V < 1V.
IN
NA
3
NA
3
NA
3
3
ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701, ISL8703, ISL8705. Tracks V upon bias.
IN
NA
4
NA
4
NA ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700, ISL8702, ISL8704. Pulls low with V < 1V.
IN
NA
4
NA
4
NA
4
4
ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701, ISL8703, ISL8705. Tracks V upon bias.
IN
NA
5
NA
5
NA ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE_B for the ISL8700, ISL8702, ISL8704. Pulls low with V < 1V.
IN
5
5
5
5
6
OV
UV
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull ups.
6
6
6
6
6
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull ups.
7
7
7
8
7
8
7
8
7
8
GND
IC ground.
NA
NA
FAULT
The V voltage when not within the desired UV to OV window will cause FAULT to be
IN
released to be pulled high to a voltage equal to or less than V via an external resistor.
IN
NA
NA
10
NA
NA
10
9
9
NA
9
NA
9
SEQ_EN
This pin provides a sequence on signal input with a high input. Internally pulled high to V .
IN
NA
10
NA
10
SEQ_EN# This pin provides a sequence on signal input with a low input. Internally pulled high to V .
IN
10
10
TIME
This pin provides a 2.6µA current output so that an adjustable V valid to sequencing on and
IN
off start delay period is created with a capacitor to ground.
11
12
13
14
11
12
13
14
11
12
13
14
11
12
13
14
11
12
13
14
11
12
13
14
TB
A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
TC
TD
A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via the
SEQ_IN input.
V
IC Bias Pin Nominally 2.5V to 24V (12V max for ISL8702).
This pin requires a 1µF decoupling capacitor close to IC pin.
IN
FN9250.0
3
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Functional Block Diagram
VIN (2.2V MIN - 27V MAX, 14V for ISL8702)
VIN
VREF
1.17V
VOLTAGE
REFERENCE
VIN
3.5V
SEQ_EN
UV
INTERNAL VOLTAGE
REGULATOR
+
-
eo
ENABLE_A
ENABLE_B
ENABLE_C
2.0V VIN POR
+
-
LOGIC
OV
FAULT
30µs
GND
TIME
V
TIME_VTH
ENABLE_D
PROGRAMMABLE
DELAY TIMER
VIN
2.6µA
TB
TC
TD
voltage on TIME is compared to the internal reference
Functional Description
(V
) comparator input and when greater than
TIME_VTH
TIME_VTH
The ISL870X family of ICs provides four delay adjustable
sequenced outputs while monitoring a single distributed voltage
in the nominal range of 2.5V to 24V for both under and
overvoltage. Only when the voltage is in compliance will the
ISL870X initiate the pre-programmed A-B-C-D sequence of the
ENABLE (ISL8700, ISL8702, ISL8704) or ENABLE# (ISL8701,
ISL8703, ISL8705) outputs. Although this IC has a bias range
of 2.5V to 24V (12V for ISL8702) it can monitor any voltage
>1.22V via the external divider if a suitable bias voltage is
otherwise provided.
V
the ISL8700, ISL8702, ISL8704 ENABLE_A is
released to go high via an external pull-up resistor or a pull-up
in a DC/DC convertor enable input, for example. Conversely,
ENABLE#_A output will be pulled low at this time on an
ISL8701, ISL8703, ISL8705. The time delay generated by the
external capacitor is to assure continued voltage compliance
within the programmed limits, as during this time any OV or UV
condition will halt the start-up process. TIME cap is discharged
once V
is met.
TIME_VTH
Once ENABLE_A is active (either released high on the
ISL8700, ISL8702, ISL8704 or pulled low, ISL8701, ISL8703,
ISL8705) a counter is started and using the resistor on TB as a
timing component a delay is generated before ENABLE_B is
activated. At this time, the counter is restarted using the resistor
on TC as its timing component for a separate timed delay until
ENABLE_C is activated. This process is repeated for the
resistor on TD to complete the A-B-C-D sequencing order of
the ENABLE or ENABLE# outputs. At any time during
During initial bias voltage (V ) application the ISL8700,
IN
ISL8702, ISL8704 ENABLE outputs are held low once
V
= 1V whereas the ISL8701, ISL8703, ISL8705 ENABLE#
IN
outputs follow the rising V . Once V > the V bias power on
IN
IN
reset threshold (POR) of 2.0V, V is constantly monitored for
IN
compliance via the input voltage resistor divider and the
voltages on the UV and OV pins and reported by the FAULT
output. Internally, voltage regulators generate 3.5V and 1.17V
±5% voltage rails for internal usage once V > POR. Once UV
IN
sequencing if an OV or UV event is registered, all four ENABLE
outputs will immediately return to their reset state; low for
ISL8700, ISL8702, ISL8704 and high for ISL8701, ISL8703,
> 1.22V and with the SEQ_EN pin high or open, (SEQ_EN#
must be pulled low on ISL8704, ISL8705) the auto sequence of
the four ENABLE (ENABLE#) outputs begins as the TIME pin
charges its external capacitor with a 2.6µA current source. The
ISL8705. C
is immediately discharged after initial ramp up
TIME
thus waiting for subsequent voltage compliance to restart. Once
FN9250.0
4
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
sequencing is complete, any subsequently registered UV or OV
event will trigger an immediate and simultaneous reset of all
ENABLE or ENABLE# outputs.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The following is a practical example worked out. For detailed
equatons on how to perform this operation for a given supply
requirement please see the next section.
On the ISL8702, ISL8703, ISL8704 and ISL8705, enabling of
on or off sequencing can also be signaled via the SEQ_EN or
SEQ_EN# input pin once voltage compliance is met. Initially the
SEQ_EN pin should be held low and released when sequence
start is desired. The SEQ# is internally pulled high and
1. Determine if turn-on or shutdown limits are preferred and
in this example we will determine the resistor values
based on the shutdown limits.
sequencing is enabled when it is pulled low. The on sequence
of the ENABLE outputs is as previously described. The off
sequence feature is only available on the variants having the
SEQ_EN or the SEQ_EN# inputs, these being the ISL8702,
ISL8703, ISL8704, ISL8705. The sequence is D off, then C off,
then B off and finally A off. Once SEQ_EN (SEQ_EN#) is
signaled low (high) the TIME cap is charged to 2V once again.
Once this Vth is reached ENABLE_D transitions to its reset
state and CTIM is discharged. A delay and subsequent
sequence off is then determined by TD resistor to ENABLE_C.
Likewise, a delay to ENABLE_B and then ENABLE_A turn-off
is determined by TC and TB resistor values respectively.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, Ir = divider
current
4. (Rm+Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
5. Rm+Rl = 1.1V/Ir @ UV = Rm+Rl = 1.1V/(10.8V/100kΩ) =
10.370kΩ
6. Rl = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242kΩ
7. Rm = 10.370kΩ - 9.242kΩ = 1.128kΩ
8. Ru = 100kΩ - 10.370kΩ = 89.630kΩ
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors.values.
In our example with the closest standard values of
Ru = 90.9kΩ, Rm = 1.13kΩ and Rl = 9.31kΩ, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
With the ISL8700, ISL8701 a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
Programming the Under and Overvoltage Limits
When choosing resistors for the divider remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ -1000kΩ range is advisable
with high precision resistors being used to reduce monitoring
error. Although for the ISL870X two dividers of two resistors
each can be employed to separately monitor the OV and UV
levels for the V voltage we will discuss here using a single
IN
three resistor string for monitoring the V voltage, referencing
IN
Figure 1. In the three resistor divider string with Ru (upper), Rm
(middle) & Rl (lower) the ratios of each in combination to the
other two is balanced to achieve the desired UV & OV trip
levels. Although this IC has a bias range of 2.5V to 24V (12V for
ISL8702) it can monitor any voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (gnd connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
FN9250.0
5
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
So with a single three resistor string, the resistor values can
be calculated as:
An Advanced Tutorial on Setting UV & OV Levels
This section discusses in additional detail the nuances of
setting the UV and OV levels, providing more insight into the
ISL870X than the earlier text.
Rl = (V
/Iload) (1 - Vtol/V )
REF IN
Rm = 2(V
x Vtol)/(V x Iload)
REF IN
Ru = 1/Iload x (V - V
IN
(1+Vtol/V ))
REF
IN
The following equation set can alternatively be used to work
out ideal values for a 3 resistor divider string of Ru, Rm and
For the above example with Vtol = 0.99V, assuming a 100µA
Iload at V = 12V:
Rl. These equations assume that V
is the center point
+ V )/2
IN
REF
between V
and V
(i.e. (V
UVRvth
UVRvth
UVFvth
UVFvth
Rl = 10.7kΩ
Rm = 1.9kΩ
Ru = 107.3kΩ
= 1.17V), Iload is the load current in the resistor string
(i.e. V /(Ru + Rm + Rl)), V is the nominal input voltage
IN IN
and Vtol is the acceptable voltage tolerance, such that the
Programming the ENABLE Output Delays
UV and OV thresholds are centered at V ± Vtol. The actual
IN
acceptable voltage window will also be affected by the
hysteresis at the UV and OV pins. This hysteresis is
amplified by the resistor string such that the hysteresis at the
top of the string is:
The delay timing between the four sequenced ENABLE outputs
are programmed with four external passive components. The
delay from a valid V (ISL8700 and ISL8701) to ENABLE_A
IN
and SEQ_EN being valid (ISL8702, ISL8702A, ISL8703,
ISL8704, ISL8705) to ENABLE_A is determined by the value of
the capacitor on the TIME Pin to GND. The external TIME Pin
capacitor is charged with a 2.6µA current source. Once the
voltage on TIME is charged up to the internal reference voltage,
(VTIME_VTH) the ENABLE_A output is released out of its reset
state. The capacitor value for a desired delay (±10%) to
Vhys = V
UVhys
x V
/V
OUT REF
This means that the V ± Vtol thresholds will exhibit
IN
hysteresis resulting in thresholds of V + Vtol ± Vhys/2 and
IN
V
- Vtol ± Vhys/2.
IN
There is a window between the V rising UV threshold and
IN
ENABLE_A once V and SEQ_EN where applicable has been
IN
the V falling OV threshold where the input level is
IN
satisfied is determined by:
guaranteed not to be detected as a fault. This window exists
between the limits V ± (Vtol - Vhys/2). There is an
C
= t /770kΩ
IN
TIME VINSEQpd
extension of this window in each direction up to
Once ENABLE_A reaches VTIME_VTH the TIME pin is pulled
low in preparation for a sequenced off signal via SEQ_EN. At
this time the sequencing of the subsequent outputs is started.
ENABLE_B is released out of reset after a programmable time,
then ENABLE_C, then ENABLE _D, all with their own
programmed delay times.
V
± (Vtol + Vhys/2), where the voltage may or may not be
IN
detected as a fault, depending on the direction from which it
is approached. These two equations may be used to
determine the required value of Vtol for a given system. For
example, if V is 12V, Vhys = (0.1 x 12)/1.17 = 1.03V. If V
IN IN
must remain within 12V ± 1.5V, Vtol = 1.5 - 1.03/2 = 0.99V.
This will give a window of 12 ±0.48V where the system is
guaranteed not to be in fault and a limit of 12 ±1.5V beyond
which the system is guaranteed to be in fault.
The subsequent delay times are programmed with a single
external resistor for each ENABLE output providing maximum
flexibility to the designer through the choice of the resistor value
connected from TB, TC and TD pins to GND. The resistor
values determine the charge and discharge rate of an internal
capacitor comprising an RC time constant for an oscillator
whose output is fed into a counter generating the timing delay
to ENABLE output sequencing.
It is wise to check both these voltages for if the latter is made
to tight, the former will cease to exist. This point comes when
Vtol < Vhys/2 and results from the fact that the acceptable
window for the OV pin no longer aligns with the acceptable
window for the UV pin. In this case, the application will have
to be changed such that UV and OV are provided separate
resistor strings. In this case the UV and OV thresholds can
be individually controlled by adjusting the relevant divider.
The R value for a given delay time is defined as:
TX
t
del
R
= --------------------
TX
1667nF
The above example will give voltage thresholds of :
with V rising
IN
UVr = V - Vtol + Vhys/2 = 11.5V and
IN
OVr = V + Vtol + Vhys/2 = 13.5V
IN
with V falling
IN
Ovf = V + Vtol - Vhys/2 = 12.5V and
IN
UVf = V - Vtol - Vhys/2 = 10.5V.
IN
FN9250.0
6
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
FAULT
SEQ_EN
TIME
A
B
C
D
D
C
B
A
ENABLE OUTPUTS
FIGURE 2. ISL8702 OPERATIONAL DIAGRAM
OVERVOLTAGE
LIMIT
t
FLTH
t
<t
FLTH
FLTL
UNDERVOLTAGE
LIMIT
t
FLTL
t
MONITORED VOLTAGE
RAMPING UP & DOWN
FLTH
FAULT OUTPUT
FIGURE 3. ISL8702, ISL8703, ISL8704, ISL8705 FAULT OPERATIONAL DIAGRAM
Typical Performance Curves
1.208
1.207
1.206
1.205
310
290
270
250
230
210
190
170
150
V
= 24V
IN
V
= 2.5V
1.204
1.203
1.202
1.201
1.200
1.199
1.198
IN
V
= 12V
V
= 12V
IN
IN
V
0
= 2.5V
25
IN
V
= 24V
IN
-40
-10
0
25
TEMP (°C)
60
85
100
-40
-10
60
85
100
TEMP (°C)
FIGURE 4. UV/OV RISING THRESHOLD
FIGURE 5. V CURRENT
IN
FN9250.0
7
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
bound conditions by being released to pull high to the VHI
Applications Usage
Using the ISL870XEVAL1 Platform
voltage as shown in Figures 6 and 7.
Once the voltage monitoring FAULT is resolved and where
applicable, the SEQ_EN(#) is satisfied, sequencing of the
ENABLE_X(#) outputs begins. When sequence enabled the
ENABLE_A, ENABLE_B, ENABLE_C and lastly
ENABLE_D are asserted in that order and when SEQ_EN is
disabled the order is reversed. See Figures 8 and 9
The ISL870XEVAL1 platform is the primary evaluation board
for this family of sequencers. See Figure 16 for photograph
and schematic.The evaluation board is shipped with an
ISL8702 mounted in the left position and with the other
device variants loose packed. In the following discussion,
test points names are bold on initial occurrence for
identification.
demonstrating the sequenced enabling and disabling of the
ENABLE outputs. The timing between ENABLE outputs is
set by the resistor values on the TB, TC, TD pins as shown.
Figure 10 illustrates the timing from either SEQ_EN and/or
VMONITOR being valid to ENABLE_A being asserted with a
10nF TIME capacitor. Figure 11 shows that ENABLE_X
The V test point is the chip bias and can be biased from
IN
2.5V to 24V. The VHI test point is for the ENABLE and
FAULT pull-up voltage which are limited to a maximum of
24V independent of V . The UV/OV resistor divider is set so
IN
that a nominal 12V on the VMONITOR test point is compliant
outputs are pulled low even before V = 1V. This is critical
IN
and with a rising OV set at 13.2V and a falling UV set at
to ensure that a false enable is not signaled. Figure 12
illustrates the SEQ_EN# input disabling and enabling the
ISL8705 ENABLE# outputs. Notice the reversal in order and
delay timing from ENABLE_X# to ENABLE_X#. Figure 13
shows the time from SEQ_EN transition with the voltage
ramping across the TIME capacitor to TIME Vth being met.
This results in the immediate pull down of the TIME pin and
simultaneous ENABLE_A enabling.
10.7V. These three test points (V ,VHI and VMONITOR)
IN
are brought out separately for maximum flexibility in
evaluation.
VMONITOR ramping up and down through the UV and OV
levels will result in the FAULT output signaling the out of
VMON FALLING
VMON RISING
VMON > OV
VMON > OV
LEVEL
VMON > UV
LEVEL
LEVEL
VMON > UV
LEVEL
FAULT OUTPUT
FAULT OUTPUT
FIGURE 6. VMONITOR RISING TO FAULT
FIGURE 7. VMONITOR FALLING TO FAULT
FN9250.0
8
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
R
= 3k
TB
DELAY = 5ms
R
= 3k
TB
DELAY = 5ms
R
= 51k
TC
DELAY = 86ms
R
= 120k
TD
DELAY = 196ms
R
= 51k
TC
DELAY = 86ms
R
= 120k
TD
DELAY = 196ms
FIGURE 9. ENABLE_X TO ENABLE_X DISABLING
FIGURE 8. ENABLE_X TO ENABLE_X ENABLING
V
RISING
IN
C
= 10nF
TIME
DELAY = 8.5ms
ENABLE OUTPUTS TRACKS V TO < 0.8V
IN
1V/DIV
10ms/DIV
FIGURE 10. V /SEQ_EN VALID TO ENABLE_A
IN
FIGURE 11. ENABLE AS V RISES
IN
SEQ_EN#
SEQ_EN
ENABLE_A
ENABLE_A#
ENABLE_B#
TIME
0.5V/DIV
ENABLE_C#
ENABLE_D#
FIGURE 12. ISL8705 ENABLE_X# TO ENABLE_X#
FIGURE 13. SEQ_EN TO ENABLE_A
FN9250.0
9
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
VMONITOR OV
VMONITOR UV
FAULT = LOW
8µs/DIV
FIGURE 14. OV & UV TRANSIENT IMMUNITY
Application Concerns and Recommendations
Best practices V decoupling is required, a 1µF capacitor is
IN
recommended.
PIN 4
Coupling from the ENABLE_X pins to the sensitive UV and
OV pins can cause false OV/UV events to be detected. This
is most relevant for ISL8700, ISL8702, ISL8704 parts due to
the ENABLEA and OV pins being adjacent. This coupling
can be reduced by adding a ground trace between UV and
the ENABLE/FAULT signals, as shown in Figure 15. The
PCB traces on OV and UV should be kept as small as
practical and the ENABLE_X and FAULT traces should
ideally not be routed under/over the OV/UV traces on
different PCB layers unless there is a ground or power plane
in between. Other methods that can be used to eliminate this
issue are by reducing the value of the resistors in the
network connected to UV and OV (R2, R3, R5 in Figure 16)
or by adding small decoupling capacitors to OV and UV (C2
and C7 in Figure 16). Both these methods act to reduce the
AC impedance at the nodes, although the latter method acts
to filter the signals which will also cause an increase in the
time that a UV/OV fault takes to be detected.
GND
PIN 5
FIGURE 15. LAYOUT DETAIL OF GND BETWEEN PINS 4 & 5
When the ISL870X is implemented on a hot swappable card
that is plugged into an always powered passive back plane
an RC filter is required on the V pin to prevent a high dv/dt
IN
transient. With the already existing 1µF decoupling capacitor
the addition of a small series R (>50Ω) to provide a time
constant >50µs is all that is necessary.
Only the ISL8702 has a V limitation of 14V maximum.
IN
FN9250.0
10
March 14, 2006
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
.
PULL UP
RESISTORS
TIMING
COMPONENTS
UV/OV SET
RESISTORS
FIGURE 16. ISL870XEVAL1 PHOTOGRAPH AND SCHEMATIC OF LEFT CHANNEL
TABLE 1. ISL870XEVAL1 LEFT CHANNEL COMPONENT LISTING
COMPONENT
DESIGNATOR
COMPONENT FUNCTION
ISL8702, Quad Under/Overvoltage Sequencer
UV Resistor for Divider String
COMPONENT DESCRIPTION
U1
R3
R2
R5
C1
R1
R9
R7
Intersil, ISL8702, Quad Under/Overvoltage Sequencer
1.1kΩ 1%, 0603
VMONITOR Resistor for Divider String
OV Resistor for Divider String
88.7kΩ 1%, 0603
9.1kΩ 1%, 0603
C
R
R
R
Sets Delay from Sequence Start to First ENABLE
0.01µF, 0603
TIME
Sets Delay from Third to Fourth ENABLE
Sets Delay from First to Second ENABLE
Sets Delay from Second to Third ENABLE
120kΩ 1%, 0603
TD
TB
TC
3.01kΩ 1%, 0603
51kΩ 1%, 0603
R4, R6, R8, R10, ENABLE_X(#) and FAULT Pull-up Resistors
R11
4kΩ 10%, 0402
C3
Decoupling Capacitor
1µF, 0603
FN9250.0
March 14, 2006
11
ISL8700, ISL8701, ISL8702, ISL8703, ISL8704, ISL8705
Small Outline Plas tic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
SEATING PLANE
A
9
0.0075
0.3367
0.1497
0.0098
0.3444
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9250.0
12
March 14, 2006
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