ISL98604IRTZ-EVZ [RENESAS]
6-Channel Integrated LCD Supply;
| 型号： | ISL98604IRTZ-EVZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 6-Channel Integrated LCD Supply CD |
| 文件： | 总28页 (文件大小：1202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
ISL98604
FN7687
Rev 1.00
6-Channel Integrated LCD Supply
April 9, 2015
The ISL98604 is a high power, fully programmable 6-Channel
output control IC targeted at large panel LCD displays. The
ISL98604 integrates a high power, boost converter and delay
switch for AVDD generation, one VIO asynchronous buck
regulator, two synchronous buck regulators for HAVDD and
Features
• 8V to 16.5V input supply
• AVDD boost up to 19.0V, with integrated 4.0A
FET
PEAK
FET
• HAVDD synchronous buck for 8V with 1A
• Overvoltage protection (OVP)
• Internal AVDD delay FET
PEAK
VCORE supply generation, and linear regulator controllers for V
ON
and V
OFF
charge pumps.
Operating at 750kHz, the AVDD boost converter features a 4.0A
boost FET and 6-bit resolution programmable from 12.7V to
19.0V. The delay switch is also integrated for power sequence.
• Dual linear regulator controllers for V and V
ON
OFF
• V temperature compensation
ON
• VIO buck with integrated 2A
PEAK
FET
The asynchronous buck converter for VIO supply features an
integrated 2A FET. It also operates at 750kHz internal clock and
compensation features.
• VCORE synchronous buck with integrated 1A
• Internal feedback and compensation
• Programmable output control with IIC
• Programmable sequencing with IIC
• UVLO and OTP protection
FET
PEAK
The two synchronous bucks are integrated with controller,
upper, and lower side switches for HAVDD and VCORE
generation with internal compensation. The HAVDD and
VCORE outputs are both programmable ranging from 6.4V to
9.55V and 0.9V to 2.4V, respectively.
• Thermally enhanced 5x5 Thin QFN package
• Pb-free (RoHS compliant)
Dual linear regulator controllers are provided to allow generation
of accurate V and V
charge pumps and bipolar power transistors. V output voltage
can be compensated adoptively by temperature sensing.
voltages in conjunction with external
ON OFF
Applications
• LCD TV
ON
All output voltages are programmed through IIC and stored in
EEPROM. Alternative factory set voltages may be available for the
ISL98604.
Pin Configuration
ISL98604
(40 LD 5x5 TQFN)
TOP VIEW
40 39 38 37 36 35 34 33 32 31
EN
30
VCORE
1
2
29 SDA
TCOMP
VDC
28
3
SCL
27
26
25
24
23
22
21
4
A0
AGND
AVIN
5
PG
THERMAL
PAD
6
NC
PVIN3
NC
7
DRVN
NC
8
PHASE1
HAVDD
PGND3
9
FBN
FBP
10
11 12 13 14 15 16 17 18 19 20
FN7687 Rev 1.00
April 9, 2015
Page 1 of 28
ISL98604
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test Circuits and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
HAVDD Synchronous Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VIO Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCORE Buck Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
V
V
Linear-Regulator Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ON
Linear-Regulator Controller and Charge Pump. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
OFF
Calculation of the Linear Regulator Base-Emitter Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VON/VOFF Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
VON Temperature Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2
I C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Start-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
FN7687 Rev 1.00
April 9, 2015
Page 2 of 28
ISL98604
Pin Descriptions
PIN #
SYMBOL
DESCRIPTION
1
2
EN
IC enable pin; pull high to enable all the outputs.
TCOMP
Temperature compensation input, connect NTC resistor in the resistor ladder from VDC to GND to set the curve of V
temperature.
vs
ON
3
4
5
6
VDC
AGND
AVIN
PVIN3
NC
Internal linear regulator output, connected to external 1µF capacitor close to the pin.
Analog ground pin.
Internal regulator supply pin; connect to external 10µF capacitor close to the pin.
HAVDD buck power input pin; connect to external 10µF capacitor close to the pin.
Not connected.
7, 19,
23, 25,
34, 37,
40
8
PHASE1
HAVDD buck switch node; connect an inductor to the pin for synchronous mode, or connect a inductor and a Schottky diode
to the pin for asynchronous mode.
9
10
HAVDD
PGND3
SS
HAVDD buck output feedback input pin.
HAVDD buck Power ground.
11
AVDD boost and HAVDD buck soft-start timing capacitor connection for step-up.
AVDD boost compensation pin; connect a 5.6kΩ resistor and 15nF capacitor in series to the pin.
AVDD boost power ground.
12
COMP
PGND2, 1
SW2, 1
SWIN
SWO
13, 14
15, 16
17
AVDD boost switch node connection.
AVDD delay FET input, connect a 10µF capacitor close to the pin.
AVDD delay FET output, connect a 22µF capacitors close to the pin.
Positive charge pump LDO transistor driver, connect the base of an external PNP bipolar to the pin.
Positive charge pump output feedback input pin.
Negative charge pump output feedback input pin.
Negative charge pump LDO transistor driver, connect the base of an external NPN bipolar to the pin.
Power-good output.
18
20
DRVP
FBP
21
22
FBN
24
DRVN
PG
26
27
A0
IIC slave address select pin.
28
SCL
IIC clock pin.
29
SDA
IIC data pin.
30
VCORE
PGND4
PHASE2
VCORE buck output feedback input pin.
31
VCORE buck power ground.
32
VCORE buck switch node, connect an inductor to the pin for synchronous mode, or connect a inductor and a Schottky diode
to the pin for asynchronous mode.
33
35, 36
38, 39
-
VIO
VIO buck output feedback input pin.
SWB1, 2
PVIN2, 1
PAD
VIO asynchronous buck switch node connection.
VIO buck and VCORE buck power input pin; connect to external 10µF capacitor close to the pin.
Thermal Pad.
FN7687 Rev 1.00
April 9, 2015
Page 3 of 28
ISL98604
Typical Application Circuit
L1
4.7µH
SS34
D1
AVDD: 16V
12.7V~19.0V
VIN: 12V
8V~16.5V
LX
C1
10µF
C4
10µF
C02
20µF
C03
20µF
C04
10µF
VIO BUCK
BOOST
PVIN1
PVIN2
SW1
SW2
SWIN
SWO
L2
6.8µH
SWB1
SWB2
VIO: 3.3V
3.0V~3.7V
R01
AVDD
COMP
PGND1
PGND2
C11
20µF
5.6k
C01
15nF
D11
SS33
BAT54S
D61
LX
0
R64
C63
1µF
VIO
C64
0.1µF
SS
C05
47nF
VON C.P.
VCORE BUCK
R63
VON:
HT: 26V
700
7V~32V
DRVP
VCORE: 1.8V, 0.9V~2.4V
LT: 28V, 19V~34V
C65
Q1
VCORE
fmmt3906
PHASE2
L3
2.2µF
10µF
C21
10µF
FBP
TCOMP
VDC
PGND4
R61
10k
ASYNC MODE
TDK NTC 1068 E TYPE 10k
NTC
R62
10k
SWB1
VOFF C.P.
HAVDD BUCK
PVIN3
R53
0
VIN
C2
10µF
VOFF:
C53
HAVDD: 8.0V
6.4V~9.55V
5V, -8.1V~1.8V
0.22µF
HAVDD
MMBT3904
Q2
D52
D51
C51
PHASE1
BAT54S
DRVN
FBN
C52
L4
6.8µH
4.7µF
R54
100nF
C31
4.7µF
PGND3
700
ASYNC MODE
VIO
VIO
VIO
R42
10k
INTERFACE/SEQUENCE
R43
100k
R44
100k
PG
PGOOD
SCL
SDA
VIN
AVIN
PC
C3
10µF
A0
EN
C40
1µF
VDC
AGND
FN7687 Rev 1.00
April 9, 2015
Page 4 of 28
ISL98604
Block Diagram
COMP
AGND
VIO
SWO
SW1
SW2
FOSC
750kHz
PVIN1
PVIN2
S
R
Q
REF
FOSC
750kHz
PGND1
PGND2
SWIN
SLOPE
COMPENSATION
S
R
Q
SWB1
SWB2
DELAY
FET
SWO
PGOOD
MONITORING
PG
VON
LINEAR
REGULATOR
CONTROL
DRVP
FBP
EN
SS
I2C INTERFACE
AND
EEPROM
TCOMP
SCL
SCA
SEQUENCE
CONTROL
4.5V
REGULATOR
REF
VOFF
LINEAR
REGULATOR
CONTROL
A0
DRVN
FBN
VDC
AVIN
HAVDD
PVIN3
VCORE
VIO
FOSC
3MHz
FOSC
1MHz
REF
REF
S
R
S
R
Q
Q
Q
Q
PHASE1
PGND3
PHASE2
PGND4
AVIN
AVIN
FN7687 Rev 1.00
April 9, 2015
Page 5 of 28
ISL98604
Ordering Information
AVDD HAVDD VIO VCORE
V
V
TEMP
ON
ON
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
BOOST BUCK BUCK BUCK
LT
(V)
HT
(V)
V
(V)
DLY1 DLY2 DLY3 RANGE PACKAGE
PKG.
DWG. #
OFF
(V)
16
(V)
(V)
(V)
(ms)
(ms)
(ms)
(°C)
(Pb-free)
ISL98604IRTZ
ISL9860 4IRZ
8.0
3.3
1.0
28
26
-5
10
30
30
-40 to 40 Ld
L40.5x5D
+85 5x5 TQFN
ISL98604IRTZ-EVZ Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL98604. For more information on MSL please see techbrief TB363.
FN7687 Rev 1.00
April 9, 2015
Page 6 of 28
ISL98604
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
DRVP to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +45V
FBP to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +36V
FBN to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3V to -10V
SW1, SW2, SWI, and SWO . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +24V
PVIN1, PVIN2, AVIN, SWB1, SWB2, PHASE1, PHASE2, HAVDD, and EN to
AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18.6V
DRVN, VDC, VCORE, SS, PGOOD, SCL, SDA, and A0
to AGND and PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +5.5V
Voltage between AGND and PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5V
All other pins to GND, AGND and PGND . . . . . . . . . . . . . . . . -0.5V to +5.5V
ESD Rating
Thermal Resistance (Typical)
5x5 TQFN Package (Notes 4, 5) . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
JA (°C/W)
32
JC (°C/W)
2.4
Recommended Operating Conditions
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 16.5V
Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD22-C101). . . . . . . . . . . . . 750V
Latch-up (Tested per JESD-78B; Class II, Level A). . . . . . . . . . . . . . . 100mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications V = 12V, EN = VDC, AVDD = 16V, V = 28V, V
= -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply across the operating temperature range, T = -40°C to +85°C, unless otherwise noted.
IN
ON
OFF
A
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
TYP (Note 6) UNITS
SUPPLY PINS
P
+SUP
Supply Voltage
8
12
1.25
8
16.5
V
VIN
IV +SUP
Supply Current when Disabled
Supply Current when Enabled
Enable Input Bias Current
EN = 0V
mA
mA
µA
µA
V
IN
IV +SUP
IN
EN = VDC, no loading on all channels
IEN
EN = 0
0.01
10
0.1
15
EN = VDC
V
Internal LDO Output Voltage
4.5
LDO
AVDD BOOST
V
Output Voltage Range
Output Voltage Accuracy
Switch Peak Current Limit
Peak Efficiency
1.14*VIN
16
19.0
2
V
%
A
AVDD
ACC
AVDD = 16V, I
= 100mA
Boost Peak Current limit
-2
AVDD
LOAD
I
3.5
4
4.5
SWPL_AVDD
EFF
93
%
µA
Ω
AVDD
I
Switch Leakage Current
Switch ON-Resistance
Line Regulation
22
SWLK_AVDD
r
T
= +25°C, I
= 500mA
0.125
0.08
0.19
DS(ON)_AVDD
A SW
DV
/DV
9.5V < PVIN < 13.5V,
= 200mA,
%
AVDD
IN
I
LOAD
DV
/DI
Load Regulation
100mA < I
< 500mA
LOAD
0.5
87
%
%
AVDD
OUT
D
D
Maximum Duty Cycle
Minimum Duty Cycle
Oscillator Frequency
F
= 750kHz
= 750kHz
82
MAX_AVDD
MIN_AVDD
OSC
F
12
16
%
OSC
F
Internal OSC
675
750
825
kHz
OSC_AVDD
AVDD DELAY SWITCH
Switch ON-Resistance
r
0.15
0.24
Ω
DS(ON)_DLY
FN7687 Rev 1.00
April 9, 2015
Page 7 of 28
ISL98604
Electrical Specifications V = 12V, EN = VDC, AVDD = 16V, V = 28V, V
= -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply across the operating temperature range, T = -40°C to +85°C, unless otherwise noted. (Continued)
IN
ON
OFF
A
MIN
MAX
SYMBOL
PARAMETER
Switch Peak Current Limit
TEST CONDITIONS
(Note 6)
TYP (Note 6) UNITS
I
2.3
3.1
1
3.8
A
ms
A
SWPL_DLY
FET timeout
Delay FET Fault Timeout
I
> I
SWO DLY
I
I
Switch High Current Limit, Immediate Shut Down
Once Triggered
6.0
SWPL_Immed
Leakage Current When Disabled
V
= 16.5V, V
SWIN
= 19V, V
= 0V,
5
8
20
µA
SWLK_ DLY
IN
EN = 0V
SWO
HAVDD SYNC BUCK
V
Output Voltage Range
Output voltage accuracy
Switching Peak Current Limit
Lower Switch Reverse Current Limit
Peak Efficiency
Internal feedback
HAVDD = 8V
6.4
-1.6
1
9.55
1.6
V
%
HAVDD
ACC
HAVDD
I
I
A
SWPL_HAVDD
SWRL_HAVDD
0.65
0.9
93
1.15
A
EFF
%
HAVDD
r
r
Upper Switch ON-Resistance
Lower Switch ON-Resistance
Feedback Input Current
Line Regulation
T
= +25°C , I
= +25°C , I
= 500mA
= 500mA
0.3
0.3
11
0.37
0.37
Ω
DS(ON)_U_HAVDD
DS(ON)_L_HAVDD
FB_HAVDD
A
SW
T
Ω
A
SW
I
µA
%
DV
/DV
9.5V < PV < 13.5V, I
IN LOAD
= 200mA
0.3
0.3
5
HAVDD
IN
DV
/DI
Load Regulation
200mA < I
< 1000mA
%
HAVDD
OUT
LOAD
= +25°C
A
I
Switch Leakage Current
Maximum Duty Cycle
Minimum Duty Cycle
T
20
µA
%
SWLK_HAVDD
DMAX_HAVDD
F
= 750kHz
= 750kHz
OSC
85
90
OSC
D
F
15
%
MIN_HAVDD
F
Oscillator Frequency
Internal OSC
675
750
825
kHz
OSC_HAVDD
VIO BUCK
V
Output Voltage Range
Output Voltage Accuracy
Output Current
Internal feedback
= 3.3V
3.0
3.3
0.7
86
3.7
V
%
A
IO
ACC
V
-2.25
2.25
VIO
IO
I
I
Internal feedback
Current limit
VIO
SWPL_VIO
Switch Peak Current Limit
Peak Efficiency
2
A
EFF
See graphs and “Applications Information”
on page 15 for component
recommendations
%
VIO
r
Switch On-Resistance
Line Regulation
T
= +25°C, I
= 500mA
0.200 0.300
Ω
%
DS(ON)_VIO
A SW
DV /DV
VIO
9.5V < PV < 13.5V, I
IN LOAD
= 200mA
0.3
0.3
IN
DV /DI
VIO
Load Regulation
200mA < I < 1000mA
%
OUT
LOAD
I
Feedback Input Current
Switch Leakage Current
Maximum Duty Cycle
Minimum Duty Cycle
Oscillator Frequency
2.5
5
100
nA
µA
%
FB_VIO
SWLK_VIO
I
T
= +25°C
20
A
D
F
= 750kHz
= 750kHz
85
86
10
750
MAX_VIO
MIN_VIO
OSC
D
F
15.5
825
%
OSC
F
Internal OSC
675
kHz
OSC_VIO
VCORE BUCK
V
Output Voltage Range
Internal feedback
= 1.0V
0.9
1.0
2.4
2.5
V
CORE
ACC
Output Voltage Accuracy
V
-2.5
%
VCORE
CORE
FN7687 Rev 1.00
April 9, 2015
Page 8 of 28
ISL98604
Electrical Specifications V = 12V, EN = VDC, AVDD = 16V, V = 28V, V
= -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply across the operating temperature range, T = -40°C to +85°C, unless otherwise noted. (Continued)
IN
ON
OFF
A
MIN
MAX
SYMBOL
CORE
SWPL_VCORE
PARAMETER
TEST CONDITIONS
(Note 6)
TYP (Note 6) UNITS
I
I
Output Current
0.5
A
A
Switch Peak Current Limit
Peak Efficiency
Current limit
1
EFF
See graphs and “Applications Information”
on page 15 for component
recommendations
86
%
VCORE
r
r
Upper Switch ON-Resistance
Lower Switch ON-Resistance
Line Regulation of VCORE Buck
Load Regulation of VCORE Buck
Feedback Input Current
Switch leakage current
Maximum Duty Cycle
T
= +25°C , I
= 500mA
= 500mA
0.18
0.18
0.1
0.3
5
Ω
Ω
DS(ON)_U_VCORE
A
SW
SW
T
= +25°C , I
DS(ON)_L_VCORE
A
DV
DV
/DV
9.5V < PV < 13.5V, I
IN LOAD
= 200mA
%
VCORE
IN
/DI
200mA < I
< 500mA
%
VCORE
OUT
LOAD
= 1.8V
VCORE
I
I
V
µA
µA
%
FB_VCORE
SWLK_VCORE
3
10
D
F
= 3MHz
= 3MHz
85
90
MAX_VCORE
MIN_VCORE
OSC
D
Minimum Duty Cycle
F
8
%
OSC
F
Oscillator Frequency
Internal OSC
1.32
1.50
1.68
MHz
OSC_VCORE
V
LDO
ON
V
Output Voltage Range
Low temperature
High temperature
19
17
28
26
34
32
V
V
VON
ACC
VON
Output Voltage Accuracy
Load Regulation
V
= 28V
-2.1
2.1
%
%
ON
DV /DI
ON OUT
I
= 60µA to 120µA with MMBT3906
0.64
DRVP
PNP, related resistors are shown in the
application circuit
DV /DV
ON IN
Line Regulation
I
= 100µA, V = 9.5V to 14V
IN
0.5
6
%
mA
µA
V
DRVP
I
Positive Source Current (Max)
DRVP Off Leakage Current
Threshold Voltage in Temp. Compensation
V
= 1.15V, V
= 10V
= 30V
3
DRVP
LEAK_DRVP
FBP
FBP
DRVN
DRVN
I
V
= 1.40V, V
0.1
10
V
1.265
TCOMP_TH
(Note 7)
V
Hysteresis Voltage in Temp. Compensation
V
= 1.265V
= -5V
20
-5
mV
TCOMP_HYST
REF
V
LDO
VOFF
OFF
V
Output Voltage Range
Output Voltage Accuracy
LDO Input Bias Current
Load Regulation
-8.1
-1.8
V
%
VOFF
ACC
V
-3.75
3.75
OFF
I
V
-5V
11
µA
%
FBN
FBN =
DV /DI
I
= 60µA to 120µA with MMBT3904
2.7
OFF OUT
DRVN
NPN, related resistors are shown in the
application circuit, I = 200mA
OUT
I
I
Negative Source Current
DRVN Off Leakage Current
V
V
= 0.6V, V
= 0.5V, V
= -10V
= -6V
3
5
mA
µA
DRVN
FBN
DRVN
0.1
10
LEAK_DRVN
FBN
DRVN
FN7687 Rev 1.00
April 9, 2015
Page 9 of 28
ISL98604
Electrical Specifications V = 12V, EN = VDC, AVDD = 16V, V = 28V, V
= -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply across the operating temperature range, T = -40°C to +85°C, unless otherwise noted. (Continued)
IN
ON
OFF
A
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 6)
TYP (Note 6) UNITS
LOGIC INPUTS
V
Logic “HIGH”
Logic “LOW”
SCL, SDA, A0
EN
1.85
1.6
V
V
HI
V
SCL, SDA, A0
EN
0.85
0.675
25
V
V
LO
I
Logic Pin Pull-Down Current
SCL Frequency
V
> V
µA
LG_PD
2
LG LO
I C (Note 7)
f
t
400
50
kHz
ns
SCL
Pulse Width Suppression Time at SDA and SCL
Inputs
Any pulse narrower than max spec is
suppressed
iN
t
SCL Falling Edge to SDA Output Data Valid
SCL falling edge crossing 30% of VO_LDO,
until SDA exits the 30% to 70% of VO_LDO
window
900
ns
ns
AA
t
Time the Bus Must Be Free before the Start of a New SDA crossing 70% of VO_LDO during a STOP
1300
BUF
Transmission
condition, to SDA crossing 70% of VO_LDO
during the following START condition
t
t
t
Clock LOW Time
Measured at the 30% of VO_LDO crossing
Measured at the 70% of VO_LDO crossing
1300
600
ns
ns
ns
LOW
Clock HIGH Time
HIGH
SU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both
crossing 70% of VO_LDO
600
t
t
t
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
SDA falling edge crossing 30% of VO_LDO to
SCL falling edge crossing 70% of VO_LDO
600
100
0
ns
ns
ns
HD:STA
SU:DAT
HD:DAT
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge cross 30% of V
CC
From SCL falling edge crossing 70% of V
CC
900
to SDA entering the 30% to 70% of V
CC
window
t
t
t
Stop Condition Setup Time
Stop Condition Hold Time
Output Data Hold Time
From SCL rising edge crossing 70% of V
to SDA rising edge cross 30% of V
CC
,
600
600
0
ns
ns
ns
SU:STO
HD:ST0
DH
CC
From SDA rising edge to SCL falling edge.
Both crossing 70% of V
CC
From SCL falling edge crossing 30% of V
CC,
until SDA enters the 30% to 70% of V
window
CC
t
t
SDA and SCL Rise Time
Depend on Load
1000
ns
ns
R
nWR Condition Setup Time
From nWR rising/falling edge crossing
70/30% of V , to SDA falling edge cross
600
800
SU:A
CC
30% of V (START)
CC
t
nWR Data Hold Time
From SDA rising edge crossing 70% of V
(STOP) to nWR rising/falling edge crossing
ns
HD:A
F
CC
70/30% of V window
CC
t
SDA and SCL Fall Time
300
400
ns
pF
pF
2
Cb
I C Bus Capacitive Load
C
Capacitance on SDA
5
SDA
FN7687 Rev 1.00
April 9, 2015
Page 10 of 28
ISL98604
Electrical Specifications V = 12V, EN = VDC, AVDD = 16V, V = 28V, V
= -5V, HAVDD = 8.0V, VIO = 3.3V, VCORE = 1.0V. Boldface
limits apply across the operating temperature range, T = -40°C to +85°C, unless otherwise noted. (Continued)
IN
ON
OFF
A
MIN
MAX
SYMBOL
SCL
PARAMETER
Capacitance on SCL
TEST CONDITIONS
(Note 6)
TYP (Note 6) UNITS
C
nWR = 0
nWR = 1
5
5
pF
pF
t
Nonvolatile Write Cycle Time
12
20
ms
WP
EEPROM
t
EEPROM Programming Time
EEPROM Memory Retention
EEPROM Read/Write Cycles
T
= +25°C
= +25°C
= +25°C
90
88
1
ms
EEPROM
A
R
T
kHrs
kCyc
EEPROM
A
C
T
A
EEPROM
FAULT DETECTION THRESHOLD
OVP Overvoltage Protection Off Threshold to Shutdown IC
20.5
7.5
V
V
V
Undervoltage Lock Out Threshold
PV rising
IN
7.2
6.0
7.9
6.6
UVLO
PV falling
IN
6.3
V
T
Thermal Shutdown All Channels
Temperature rising
140
°C
OFF
START-UP AND SOFT-START
I
Soft-Start Current
C
C
= 47nF
= 47nF
6
µA
ms
ms
ms
ms
ms
ms
SS_AVDD
SS
t
t
t
t
t
t
Boost and HAVDD Buck Soft-Start Time
Positive Charge Pump Soft-Start Period
Negative Charge Pump Soft-Start Period
Delay Time from VIO to /RST Start
10
6.4
SS_HAVDD
SS_VON
SS_VOFF
DLY1
SS
t
= -1.6*V -15
OFF
1.6
0
9
SS_VOFF
From 90% of VIO
From 90% of V
10
30
30
Delay Time from V
OFF
to AVDD Start
0
DLY2
OFF
Delay Time from AVDD to V Start
ON
From 90% of AVDD
0
DLY3
POWER GOOD BLOCK
V
PGOOD Output Low Voltage
PGOOD Leakage Current
IPGOOD = 1mA
VPGOOD = 3V
0.007 0.025
V
PGOOD
I
0.05
µA
PGLEAK
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by design or characterization but not production tested.
FN7687 Rev 1.00
April 9, 2015
Page 11 of 28
ISL98604
Typical Performance Curves
95
94
93
92
91
90
89
88
87
0.04
0.02
V
= 12V
IN
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
V
= 12V
IN
86
85
84
L = RLF7030T-4R7M3R4
D = SS34
0
0.2
0.4
0.6
0.8
1.0
1.2
0.1
0.3
0.5
0.7
0.9
1.1
I_AVDD (A)
I_AVDD (A)
FIGURE 1. AVDD BOOST EFFICIENCY
FIGURE 2. AVDD BOOST LOAD REGULATION
0.01
0.01
I
= 200mA
AVDD
AVDD RIPPLE (500mV/DIV)
0.00
-0.01
-0.01
-0.02
-0.02
-0.03
I
(100mA/DIV)
AVDD
9
10
11
12
13
14
V
(V)
V
= 12V
IN
IN
FIGURE 3. AVDD BOOST LINE REGULATION
FIGURE 4. AVDD BOOST TRANSIENT RESPONSE
0.04
0.02
100
90
80
70
60
50
40
30
20
10
0
V
= 12V
IN
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
V
= 12V
IN
L = RLF7030T-6R8M2R8
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.2
0.4
0.6
0.8
I_HAVDD (A)
I_HAVDD (A)
FIGURE 5. HAVDDBUCK EFFICIENCY
FIGURE 6. HAVDD BUCK REGULATION
FN7687 Rev 1.00
April 9, 2015
Page 12 of 28
ISL98604
Typical Performance Curves(Continued)
0.10
HAVDD RIPPLE (50mV/DIV)
I
= 200mA
HAVDD
0.05
0.00
I
(100mA/DIV)
HAVDD
-0.05
-0.10
9.5
10.0 10.5
11.0 11.5
(V)
12.0 12.5
13.0 13.5
V
IN
FIGURE 7. HAVDD BUCK LINE REGULATION
FIGURE 8. HAVDD BUCK TRANSIENT RESPONSE
90
85
80
75
70
65
60
0.05
0.00
V
= 12V
IN
-0.05
-0.10
-0.15
V
= 12V
IN
L = RLF7030T-6R8M2R8
D = SS33
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
0.5
1.0
I_VIO (A)
1.5
2.0
I_VIO (A)
FIGURE 9. VIO BUCK EFFICIENCY
FIGURE 10. VIO BUCK LOAD REGULATION
0.04
0.03
0.03
0.02
0.02
0.01
0.01
0.00
I
= 200mA
VIO
VIO RIPPLE (50mV/DIV)
I
(100mA/DIV)
VIO
V
= 12V
9.5
10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5
(V)
IN
V
IN
FIGURE 11. VIO BUCK LINE REGULATION
FIGURE 12. VIO BUCK TRANSIENT RESPONSE
FN7687 Rev 1.00
April 9, 2015
Page 13 of 28
ISL98604
Test Circuits and Waveforms
95
93
91
89
87
85
83
81
79
0.04
0.02
V
= 12V
IN
0.00
-0.02
-0.04
-0.06
-0.08
-0.10
V
= 12V
IN
L = RLF7030T-2R2M5R4
77
75
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
I_VCORE (A)
I_VCORE (A)
FIGURE 13. VCORE BUCK EFFICIENCY
FIGURE 14. VCORE BUCK LOAD REGULATION
0.01
0.01
0.01
0.01
0.00
0.00
0.00
0.00
I
= 200mA
VCORE
VCORE RIPPLE (50mV/DIV)
I
(100mA/DIV)
VCORE
V = 12V
IN
9.5
10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5
(V)
V
IN
FIGURE 16. VCORE BUCK TRANSIENT RESPONSE
FIGURE 15. VCORE BUCK LINE REGULATION
0.10
0.05
0.04
V
= 12V
I
= 20mA
IN
VON
0.02
0.00
0.00
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.02
-0.04
-0.06
-0.08
-0.10
0
0.01
0.02
0.03
0.04
0.05
9.5
10.5
11.5
(V)
12.5
13.5
V
I_VON (A)
IN
FIGURE 18. V LINE REGULATION
ON
FIGURE 17. V LOAD REGULATION
ON
FN7687 Rev 1.00
April 9, 2015
Page 14 of 28
ISL98604
Test Circuits and Waveforms(Continued)
0.10
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
I
= 20mA
VOFF
V
= 12V
IN
0.00
-0.10
-0.20
-0.30
-0.40
-0.50
9.5
10.5
11.5
(V)
12.5
13.5
0
0.01
0.02
0.03
0.04
0.05
V
I_VOFF (A)
IN
FIGURE 20. V
LINE REGULATION
FIGURE 19. V
LOAD REGULATION
OFF
OFF
V
Applications Information
The ISL98604 provides a complete power solution for TFT LCD
applications. The system consists of one boost converter to
D
f
SW
IN
--------- ----------
I
=
(EQ. 3)
L
L
ISL98604 uses internal feedback resistor divider to divide the
output voltage down to the nominal reference voltage. The boost
converter output voltage is programmable through I C control,
which will be described in more detail in section “I C Control” on
page 20.
generate A
voltage for column drivers, one asynchronous
VDD
2
buck converter to provide voltage to logic circuit in the LCD panel,
two synchronous bucks for core voltage and HAVDD, LDO
2
controllers for V and V
charge pump outputs, and A
ON OFF
VDD
delay FET. With the high output current capability, this part is
ideal for LCD TV and monitor panel application.
INPUT CAPACITOR
An input capacitor is used to suppress the voltage ripple injected
into the boost converter. A ceramic capacitor with low ESR should be
chosen to minimize the ripple. The voltage rating of input capacitor
should be larger than the maximum input voltage. Some capacitors
are recommended in Table 1.
Boost Converter
OPERATION
The AVDD boost converter is a current mode PWM converter
operating at a fixed switching frequency (750kHz). It can operate
in both discontinuous conduction mode (DCM) at light loads and
continuous mode (CCM). In continuous current mode, current
flows continuously in the inductor during the entire switching
cycle in steady state operation. The voltage conversion ratio in
continuous current mode is given by Equation 1:
TABLE 1. BOOST CONVERTER INPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/25V
22µF/25V
SIZE
VENDOR
PART NUMBER
C3216X7R1E106K
1206 TDK
1206 Murata
GRM31CR61E226KE15L
V
1
boost
(EQ. 1)
------------------
-------------
=
V
1 – D
BOOST INDUCTOR
IN
The boost inductor is a critical part which influences the output
voltage ripple, transient response, and efficiency. The selection
where D is the duty cycle of the switching MOSFET.
The boost converter uses a summing amplifier architecture for
voltage feedback, current feedback, and slope compensation. A
comparator looks at the peak inductor current cycle-by-cycle and
terminates the PWM cycle if the current limit is triggered. Since
this comparison is cycle based, the PWM output will be released
after the peak current goes below the current limit threshold.
of inductor should be based on its maximum current (I
)
SAT
characteristics, power dissipation (DCR) and size. Values of
3.3µH to 10µH are recommended to match the internal slope
compensation as well as to maintain a good transient response
performance. The inductor must be able to handle the average
and peak currents shown in Equations 4 and 5:
I
O
(EQ. 4)
The current through the MOSFET is limited to 4A peak. This restricts
the maximum output current (average) based on Equation 2:
------------------------------
I
=
LAVG
1 – DxEff
I
L
(EQ. 5)
I
V
IN
V
O
--------
I
= I
+
LAVG
L
(EQ. 2)
LPK
--------
---------
I
=
I
–
LMT
2
OMAX
2
Where Eff is the efficiency of the boost converter; 90% can be used
in calculation as approximation.
Where I is peak-to-peak inductor ripple current, and is set by
L
Equation 3. f is the switching frequency (750kHz).
SW
FN7687 Rev 1.00
April 9, 2015
Page 15 of 28
ISL98604
Some inductors are recommended in Table 2.
COMPENSATION
The boost converter of ISL98604 can be compensated by a RC
network connected from the COMP pin to ground. The resistance
sets the high -frequency integrator gain for fast transient
response and the capacitance sets the integrator zero to ensure
loop stability. On the demo board 5.6k and 15nF RC network is
used. Stability can be examined by repeatedly changing the load
between 100mA and a max level that is likely to be used in the
TABLE 2. BOOST INDUCTOR RECOMMENDATION
DIMENSIONS
INDUCTANCE DCR (mΩ)
(mm)
VENDOR
PART NUMBER
4.7µH/
31
7.3x6.8x3.2 TDK
RLF7030T-4R7M3R4
3.4A
PEAK
4.7µH/
44.1
11.2
4.0x4.0x3.1 Coilcraft XAL4030-472MEB
12.9x12.9x4 SUMIDA CDEP12D38NP-4R3M
application. The A
voltage should be examined with an
VDD
4.5A
PEAK
oscilloscope set to AC and observe the amount of ringing when
the load current changes.
4.3µH/
6.4A
PEAK
SOFT-START
RECTIFIER DIODE
The soft-start is provided by an internal current source to charge
the external soft-start capacitor. The ISL98604 ramps up the
current limit from 0A up to the full value, as the voltage at the SS
pin ramps up from 0.8V. Hence, the soft-start time is 2.9ms
when the soft-start capacitor is 22nF, 6.3ms for 47nF and
13.3ms for 100nF.
A high-speed diode is necessary due to the high switching
frequency. Schottky diodes are recommended because of their
fast recovery time and low forward voltage. The reverse voltage
rating of this diode must be higher than the maximum output
voltage. Also the average/peak current rating of the selected
Schottky diode must meet the output current and peak inductor
current requirements. Table 3 shows some recommendations for
boost converter diodes.
AVDD DELAY SWITCH
ISL98604 integrates a disconnect switch for the AVDD boost
output to disconnect V from AVDD when the EN input is low or
IN
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION
when DLY2 is not completed. When EN is taken high and DLY2
timing is finished, the integrated FET is turned on to connect
power to the display. The AVDD delay switch circuitry constantly
monitors both the current flowing through the switch and the
voltage at SWOUT. The delay switch has two current limits: a low
current limit and a high current limit. If the current flowing
through delay switch is higher than the delay switch low current
limit, the IC faults out after 1ms; if the delay switch high current
limit is reached, the IC faults out immediately.
V /I
AVG
R
DIODE
SS34
RATING
40V/3A
30V/3A
PACKAGE
DO-214
VENDOR
Fairchild
NXP
PMEG3030
SOD128
OUTPUT CAPACITOR
The output capacitors smooths the output voltage and supplies
load current directly during the conduction phase of the power
switch. Output ripple voltage consists of two components: the
voltage drop due to the inductor ripple current flowing through
the ESR of output capacitor, and the charging and discharging of
the output capacitor.
HAVDD Synchronous Buck Converter
OPERATION
HAVDD synchronous buck converter is a step down converter with
a fixed switching frequency (750kHz) supplying voltage bias for
gamma buffer in the LCD system. The ISL98604 integrates two
MOSFETs to reduce external component count, save cost, and
improve efficiency. In continuous current mode, the relationship
between input voltage and output voltage is as shown in Equation 7:
V
– V
I
O
1
f
s
O
IN
----------------------- --------------- ---
V
= I
ESR +
LPK
(EQ. 6)
RIPPLE
V
C
O
OUT
The conservation of charge principle also indicates that, during
the boost switch Off period, the output capacitor is charged with
the inductor ripple current, minus a relatively small output
current in boost topology. As a result, the user must select an
output capacitor with low ESR and adequate input ripple current
capability.
HVDD
(EQ. 7)
-----------------
= D
V
IN
where D is the duty cycle of the upper switching MOSFET.
Because D is always less than 1, the output voltage of the HAVDD
buck converter is lower than the input voltage.
Table 4 shows some recommendations of output capacitors.
The peak current limit of HAVDD buck converter is set to 0.9A,
which restricts the maximum output current based on
Equation 8:
Note: Capacitors have a voltage coefficient that makes their effective
capacitance drop as the voltage across them increases. C
in
OUT
Equation 6 assumes the effective value of the capacitor at a
particular voltage and not the manufacturer's stated value,
measured at 0V.
I
P-P
(EQ. 8)
---------------
I
= 0.9 –
HAVDDMAX
2
Where I is the ripple current in the buck inductor as shown in
Equation 9:
P-P
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/50V
22µF/25V
SIZE
1206
1210
VENDOR
TDK
PART NUMBER
C3216X5R1H106K
HAVDD
----------------------
I
=
1 – D
(EQ. 9)
P-P
L f
SW
Murata
GRM32ER71E226KE15L
FN7687 Rev 1.00
April 9, 2015
Page 16 of 28
ISL98604
Where L is the buck inductance, f is the switching frequency of
SW
HADD buck inductor (750kHz).
OUTPUT CAPACITOR
The output ripple and transient response typically drives the
selection of an output capacitor. A 10µF or a 22µF ceramic
capacitor is recommended (see Table 7).
ISL98604 uses internal feedback resistor divider to divide the
output HAVDD voltage down to the nominal reference voltage. The
2
HAVDD voltage is programmable through I C control, which will be
TABLE 7. HAVDD BUCK OUTPUT CAPACITOR RECOMMENDATION
2
described in more detail in section “I C Control” on page 20.
CAPACITOR
22µF/16V
10µF/25V
SIZE
0805
0805
VENDOR
TDK
PART NUMBER
C2012X5R1C226K
C2012X5R1E106M
INPUT CAPACITOR
Selection of input capacitance is important for input voltage
ripple. A ceramic capacitor should be used because of its small
ESR. Another important criteria when selecting input capacitor is
that it should be able to support the maximum AC RMS current
which occurs at D = 0.5 and maximum output current.
TDK
VIO Buck Converter
OPERATION
I
=
D 1 – D I
HAVDD
(EQ. 10)
ACRMS
VIO buck converter is an asynchronous step down converter with
a fixed switching frequency (750kHz) supplying power to the logic
circuit of the LCD system. In continuous current mode, the
relationship between input voltage and output voltage, is as shown
in Equation 11.
Where I
is the output current of the buck converter. Table 5
HAVDD
shows recommendations for input capacitors.
TABLE 5. HAVDD BUCK CONVERTER INPUT CAPACITOR
RECOMMENDATION
VIO
(EQ. 11)
----------
= D
V
IN
CAPACITOR
10µF/25V
22µF/25V
SIZE
1206
1206
VENDOR
TDK
PART NUMBER
C3216X7R1E106K
where D is the duty cycle of the switching MOSFET.
Murata
GRM31CR61E226KE15L
The peak current limit of VIO buck converter is set to 2A, which
restricts the maximum output current based on Equation 12:
I
P-P
2
HAVDD BUCK INDUCTOR
(EQ. 12)
---------------
I
= 2 –
VIOMAX
The inductance is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce
the converter’s response time to load transients. Taking all the
factors into consideration, a 3.3µH to 10µH inductor range is
recommended for the HAVDD buck converter. Besides the
inductance, the DC resistance and the saturation current are also
factors that need to be considered when choosing a buck
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor
current in the application. Table 6 shows some
Where I
is the ripple current in the buck inductor as shown in
P-P
Equation 13:
VIO
-----------------
I
=
1 – D
(EQ. 13)
P-P
L f
SW
Where L is the buck inductance, f is the switching frequency of
SW
VIO buck inductor.
ISL98604 uses internal feedback resistor divider to divide the
output VIO voltage down to the nominal reference voltage. The VIO
voltage is programmable through I C control, which will be
2
2
described in more detail in section “I C Control” on page 20.
recommendations for the HAVDD buck inductor.
INPUT CAPACITOR
TABLE 6. HAVDD BUCK INDUCTOR RECOMMENDATION
Selection of input capacitance is important for input voltage
ripple. A ceramic capacitor should be used because of its small
ESR. Another important criteria when selecting input capacitor is
that it should be able to support the maximum AC RMS current,
which occurs at D = 0.5 and maximum output current.
DCR
(mΩ)
DIMENSIONS
(mm)
PART
NUMBER
INDUCTANCE
6.8µH/
VENDOR
Coilcraft
74.1
4.0x4.0x3.1
XAL4030-
682MEB
3.6A
PEAK
6.8µH/
45
7.3x6.8x3.2
TDK
RLF7030T-
6R8M2R8
I
=
D 1 – D I
VIO
(EQ. 14)
2.8A
ACRMS
PEAK
Where I
is the output current of the VIO buck converter. Table 8
VIO
shows recommendations for input capacitors.
TABLE 8. VIO BUCK CONVERTER INPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/25V
22µF/25V
SIZE
1206
1206
VENDOR
TDK
PART NUMBER
C3216X7R1E106K
Murata
GRM31CR61E226KE15L
FN7687 Rev 1.00
April 9, 2015
Page 17 of 28
ISL98604
VIO BUCK INDUCTOR
VCORE Buck Converter
The inductance is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce
the converter’s response time to load transients. Taking all the
factors into consideration, a 3.3µH to 10µH inductor range is
recommended for the VIO buck converter. Besides the
inductance, the DC resistance and the saturation current are also
factors that need to be considered when choosing a buck
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor
current in the application. Table 9 shows some
OPERATION
VCORE buck converter is a synchronous step-down converter with
a fixed switching frequency (1.5MHz) to generate voltage and
supply current to the core circuit of the LCD system. In continuous
current mode, the relationship between input voltage and output
voltage is as shown in Equation 16.
VCORE
(EQ. 16)
----------------------
= D
V
IN
where D is the duty cycle of the upper MOSFET and V of the
IN
VCORE buck converter is the output voltage of the VIO buck
converter.
recommendations for the VIO buck inductor.
TABLE 9. VIO BUCK INDUCTOR RECOMMENDATION
The peak current limit of the VCORE buck converter is set to 1A,
which restricts the maximum output current based on
Equation 17:
DCR
(mΩ)
DIMENSIONS
(mm)
PART
INDUCTANCE
6.8µH/
VENDOR
Coilcraft
NUMBER
I
P-P
74.1
4.0x4.0x3.1
XAL4030-
682MEB
(EQ. 17)
--------------
I
= 1 –
VCOREMAX
2
3.6A
PEAK
6.8µH/
2.8A
45
7.3x6.8x3.2
TDK
RLF7030T-
6R8M2R8
Where I is the ripple current in the buck inductor, as shown in
Equation 18:
P-P
PEAK
VCORE
----------------------
I
=
1 – D
(EQ. 18)
VIO BUCK DIODE
P-P
L f
SW
A Schottky diode is recommended for its fast recovery time and
low forward voltage. The reverse voltage rating should be higher
than the maximum input voltage. The peak current rating should
be higher than the current limit of the VIO switch, and the
average current rating should be higher than the value given by
Equation 15.
Where L is the buck inductance and f is the switching frequency
SW
of the VCORE buck inductor.
The ISL98604 uses internal feedback resistor divider to divide the
output VCORE voltage down to the nominal reference voltage. The
2
VCORE voltage is programmable through I C control, which will be
2
I
= 1 – D*I
VIO
(EQ. 15)
described in more detail in section “I C Control” on page 20.
AVG
INPUT CAPACITOR
Where I
is the output current of the VIO buck converter. Table 10
shows diode recommendations..
VIO
The input of the VCORE buck converter is internally connected to
the output of VIO buck converter. Therefore, the output
capacitors of the VIO buck converter also plays the role of input
capacitor of the VCORE buck converter. Please refer to the
“Output Capacitor” section of the “VIO Buck Converter” on
page 17 for selection of input capacitors for the VCORE buck
converter.
TABLE 10. VIO BUCK DIODE RECOMMENDATION
V /I
R
AVG
DIODE
PMEG2020EJ
SS22
RATING
20V/2A
20V/2A
PACKAGE
SOD323F
SMB
VENDOR
NXP Semiconductors
Fairchild Semiconductor
VCORE BUCK INDUCTOR
The inductance is selected to meet the output voltage ripple
requirements and minimize the converter’s response time to the
load transient. Increasing the inductance reduces the ripple
current and voltage. However, the large inductance values reduce
the converter’s response time to load transients. Besides the
inductance, the DC resistance and the saturation current are also
factors that need to be considered when choosing a buck
inductor. Low DC resistance can help maintain high efficiency.
Saturation current rating should be higher than the peak inductor
current in the application. Taking all the factors into
OUTPUT CAPACITOR
The output ripple and transient response typically drives the
selection of output capacitor. 10µF or 22µF ceramic capacitors
(Table 11) are recommended.
.
TABLE 11. VIO BUCK OUTPUT CAPACITOR RECOMMENDATION
CAPACITOR
10µF/10V
10µF/10V
22µF/10V
SIZE
0805
0805
0805
VENDOR
TDK
PART NUMBER
C2012X7R1A106K
GRM21BR71A106KE51L
C2012X5R1A226M
Murata
TDK
consideration, 2.2µH inductors as shown in Table 12 are
recommended for the VCORE buck inductor.
FN7687 Rev 1.00
April 9, 2015
Page 18 of 28
ISL98604
TABLE 12. VCORE BUCK INDUCTOR RECOMMENDATION
Calculation of the Linear Regulator
Base-Emitter Resistors
For the pass transistor of the linear regulator, DC current gain (Hfe)
and unity gain frequency (fT) are usually specified in the datasheet.
The pass transistor adds a pole to the loop transfer function at
fp = fT/Hfe. Therefore, in order to maintain phase margin at low
frequency, the best choice for a pass device is often a high
frequency, low gain switching transistor. Further improvement can
DCR
(mΩ)
DIMENSIONS
(mm)
PART
NUMBER
INDUCTANCE
2.2µH/
VENDOR
TDK
55
35.2
12
3.0x2.5x1.2
4.0x4.0x2.1
7.3x6.8x3.2
VLF302512M
T-2R2M
1.26A
PEAK
2.2µH/
Coilcraft
TDK
XAL4020-
222ME
5.6A
PEAK
2.2µH/
5.5A
RLF7030T-
2R2M5R4
be obtained by adding a base-emitter resistor R , which increases
BE
PEAK
the pole frequency to: fp = fT * (1 + Hfe * re/R )/Hfe, where
BE
re = KT/qIc. Therefore, choose the lowest value R in the design as
long as there is still enough base current (I ) to support the
B
BE
OUTPUT CAPACITOR
maximum output current (I ).
The output ripple and transient response typically drives the
selection of output capacitor. 10µF or 22µF ceramic capacitors
(Table 13) are recommended.
C
For example, the V linear regulator. If a Fairchild MMBT3906 PNP
ON
transistor is used as the external pass transistor (Q7 in the “Typical
Application Circuit” on page 4), then for a maximum V operating
TABLE 13. VIO BUCK OUTPUT CAPACITOR RECOMMENDATION
ON
requirement of 50mA, the data sheet indicates Hfe_min = 60. The
base-emitter saturation voltage is: Vbe_max = 0.7V.
CAPACITOR
10µF/6.3V
10µF/6.3V
22µF/6.3V
SIZE
0603
0402
0603
VENDOR
MURATA
TDK
PART NUMBER
GRM188R60J106ME47D
C1005X5R0J106M
C1608X5R0J226M
For the ISL98604, the minimum drive current is:
I_DRVP_min = 3mA.
TDK
The minimum base-emitter resistor, R , can now be calculated as
BP
Equation 19:
VON Linear-Regulator Controller
RBP_min= VBE_max (I_DRVP_min - Ic/Hfe_min =
(EQ. 19)
The ISL98604 includes two independent linear-regulator controllers
0.7V 3mA – 50mA 60= 325
for positive output voltage (V ) and negative voltage (V ). The
ON OFF
linear-regulator controller subcircuit is shown in the
V
and V
ON
OFF
This is the minimum value that can be used so, we now choose a
convenient value greater than this minimum value (e.g., 400W).
Larger values may be used to reduce quiescent current, however,
“Typical Application Circuit” on page 4.
The V power supply is used to power the positive supply of the row
ON
regulation may be adversely affected by supply noise if R is made
BP
driver in the LCD panel. It consists of an external charge pump
powered from the switching node (LX) of the boost converter,
followed by a low dropout linear regulator (LDO_ON). The LDO_ON
regulator uses an external PNP transistor as the pass element. The
onboard LDO controller is a wide band (>10MHz) transconductance
amplifier capable of 5mA output current, which is sufficient for up to
50mA or more output current under the low dropout condition
too high in value.
V
/V
Charge Pump
ON OFF
Single or multiple stages of charge pumps are needed to generate
output voltage higher than V and negative voltage. The charge
BOOST
pumps can be driven by switching node of the boost converter and
VIO buck converter, as shown in “Typical Application Circuit” on
page 4.
(forced beta of 10). Typical V voltage supported by ISL98604 is
ON
2
programmable from +19V to +34V through I C control, which will be
2
described in more detail in section “I C Control” on page 20.
The number of the charge pump stages can be calculated using
Equations 20 and 21.
VOFF Linear-Regulator Controller and Charge
Pump
VOFF
= N V – 2 N V – VOFF 0
IN d
(EQ. 20)
HEADROOM
The V
power supply is used to power the negative supply of the
OFF
row driver in the LCD panel. It consists of an external diode-capacitor
charge pump powered from the switching node of the VIO buck
converter, followed by a low dropout linear regulator (LDO_OFF). The
LDO_OFF regulator uses an external NPN transistor as the pass
element. The onboard LDO controller is a wide band (>10MHz)
transconductance amplifier capable of 5mA output current, which is
sufficient for up to 50mA or more output current under the low
VON
= N + 1 AVDD – N V – VON 0
(EQ. 21)
HEADROOM
d
Where N is the number of the charge pump stages, V is the
d
forward voltage drop of one Schottky diode used in the charge
pumps. V is varied with forward current and ambient
temperature, so it should be the maximum value in the diode
datasheet according to max forward current and lowest
temperature in the application condition.
d
dropout condition (forced beta of 10). Typical V
voltage
OFF
supported by ISL98604 is programmable from -8.1V to -1.8V
2
through I C control, which will be described in more detail in section
2
“I C Control” on page 20.
Once the number of the charge pump stages is determined, the
relationship between output voltages and the maximum current
that the charge pump can deliver can be calculated using
Equations 22 and 23 as follows:
FN7687 Rev 1.00
April 9, 2015
Page 19 of 28
ISL98604
2
The I C protocol defines any device that sends data on to the bus
(EQ. 22)
Freq C
V
V
= N – VIN + 2 V + I
Freq C
OFF
ON
d
VOFF fly
as a transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, ISL98604 operates as a slave device in all
= AVDD + N AVDD – 2 V – I
d
VON
fly
(EQ. 23)
Where Freq is the switching frequency of the AVDD boost, C_fly is
the flying capacitance (C64, C53 in the application diagram).
applications. The fall and rise time of SDA and SCL signal should
be in the range listed in Table 14. The capacitive load on the I C
I
and I
are the loadings of V and V
.
2
VON
VOFF
ON OFF
bus is also specified in Table 14.
CHARGE PUMP OUTPUT CAPACITORS
2
All communication over the I C interface is conducted by sending
A ceramic capacitor with low ESR is recommended. With ceramic
capacitors, the output ripple voltage is dominated by the
capacitance value. The capacitance value can be chosen by
Equation 24:
the MSB of each byte of data first.
2
TABLE 14. I C INTERFACE SPECIFICATION
PARAMETER
SDA and SCL Rise Time
SDA and SCL Fall Time
MIN
TYP
MAX
1000
300
UNITS
ns
I
OUT
(EQ. 24)
------------------------------------------------------
C
OUT
2 V
f
OSC
RIPPLE
ns
For V charge pump, f
is the switching frequency of boost
charge pump, f is the switching frequency of
ON OSC
2
converter; for V
I C Bus Capacitive Load
400
pF
OFF OSC
VIO buck converter.
PROTOCOL CONVENTIONS
V
Temperature Compensation
ON
Data states on the SDA line can change only during SCL LOW
periods. SDA state changes during SCL HIGH are reserved for
indicating START and STOP conditions (see Figure 22). On
power-up, the SDA pin is in the input mode.
The ISL98604 can output two levels of V voltages depending
ON
on the temperature. A voltage divider which consists of two
resistors (R61 and R62) and a thermistor, as shown in the
“Typical Application Circuit” on page 4 connected to TCOMP pin is
2
used to determine the V voltage.
All I C interface operations must begin with a START condition,
ON
which is a HIGH to LOW transition of SDA while SCL is HIGH.
ISL98604 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
Figure 21 shows that the V voltage will be VON_LT when the
ON
TCOMP voltage is above the compensation threshold voltage. If
the TCOMP voltage is below the compensation threshold voltage,
2
condition is met (see Figure 22). All I C interface must be
the V voltage will be VON_HT. There is a 20mV hysteresis
ON
terminated by a STOP condition, which is a LOW to HIGH
transition of SDA while SCL is high (see Figure 22). An ACK
(Acknowledge) is a software convention used to indicate a
successful data transfer. The transmitting device, either master or
slave, releases the SDA bus after transmitting eight bits. During the
ninth clock cycle, the receiver pulls the SDA line LOW to
between the threshold when TCOMP voltage rises and the
threshold when TCOMP voltage falls. R61, R62, and thermistor
values are selected to set the V voltage at desired
ON
temperature. VON_LT and VON_HT are programmable through
2
2
I C control, which will be described in more detail in section “I C
Control” in the following.
acknowledge the reception of the eight bits of data (see Figure 23).
FBP
VDC
WRITE OPERATION
To write into a DAC register (DR), it requires a START condition
VON_LT
R61
R62
from the Master, followed by 7-bit device address (010000A ),
0
TCOMP
R/W bit (= 0 when writing), a valid DAC register address Byte
(01h-09h), a data byte, and a STOP condition. After each of the
three bytes, the ISL98604 responds with an ACK. At this time, if
the data byte is to be written only to volatile registers, the device
enters its standby state.
NTC
VON_HT
TEMPERATURE WHEN TCOMP VOLTAGE
> V = 1.265V
Example: Writing 21h to register address 01h (HAVDD)
TCOMP_TH
TEMPERATURE (°C)
TEMPERATURE HYSTERESIS RESULTED FROM V
To write data in the DAC registers into EEPROM, it requires a
START condition from the Master, followed by 7-bit device
address, R/W bit (= 0 when writing), Control Register (CR)
address byte (FFh), a data byte of 80h to write data in DRs to
EEPROM and a STOP condition. After each of the three bytes,
ISL98604 responds with an ACK. If the Data Byte is to be written
to EEPROM, ISL98604 begins its internal write cycle, which takes
25ms to finish. During the internal EEPROM write cycle, the
device ignores transitions at the SDA and SCL pins and the SDA
output is at high impedance state. When the internal EEPROM
write cycle is completed, the ISL98604 enters its standby state.
= 20mV
TCOMP_HYST
FIGURE 21. V TEMPERATURE COMPENSATION
ON
2
I C Control
2
The ISL98604 supports all rail outputs with fully programmable I C
control. The programmed output values can be stored into EEPROM
during the operation and read out.
FN7687 Rev 1.00
April 9, 2015
Page 20 of 28
ISL98604
Example: Writing current data in DRs into EEPROM.
Example: Reading data from DR address 06h (V ).
OFF
To read from EEPROM first, it first requires to write 01 into the
Control Register (CR) (FFh) to specify that the data is read from
EEPROM. Then it sends the desired DR address to be read
(00h-09h). Finally, it reads data from DR, which requires a START
condition from Master, followed by 7-bit device address
READ OPERATION
To read from the DAC register (DR), it first requires to write 00
into the Control Register (CR) (FFh) to specify that the data is
read from DR. Then it sends desired DR address to be read
(00h-09h). Finally, it reads data from DR, which requires a START
condition from Master, followed by 7-bit device address
(010000A ), R/W bit (= 1 when reading); the second byte
0
contains the data read from EEPROM. Note that the Master will
not acknowledge this byte. Finally, the last Master sends STOP
condition.
(010000A ), R/W bit (= 1 when reading); the second byte
0
contains the data read from the specified DR. Note that the
Master will not acknowledge this byte. Finally, the last Master
sends STOP condition.
Example: Reading data from EEPROM address 06h (V ).
OFF
SCL
SDA
START
DATA
STABLE
DATA
CHANGE STABLE
DATA
STOP
FIGURE 22. VALID DATA CHANGES, START, AND STOP CONDITION
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
START
ACK
FIGURE 23. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN7687 Rev 1.00
April 9, 2015
Page 21 of 28
ISL98604
REGISTER MAP AND REGISTER VALUES
TABLE 16. DATA FORMAT OF DAC REGISTER AND EEPROM
AVDD (Default Data: 21h)
Table 15 shows the address of the DAC registers and their
default values. Table 16 shows the data format of each register.
Table 17 shows the parameters corresponding to different
register values.
MSB
R
LSB
1
R
1
0
0
0
R
0
1
1
0
R
R
R
0
0
0
0
0
0
0
0
0
0
R
0
0
1
0
0
0
0
0
1
1
R
HAVDD (Default Data: 20h)
MSB
TABLE 15. MEMORY MAP OF DAC REGISTER AND EEPROM
LSB
0
DATA
R
R
1
0
(VOLATILE/
NONVOLATILE)
FACTORY DEFAULT
(POWER-UP)
REGISTER ADDRESS
VIO (Default Data: 03h)
MSB
AVDD
HAVDD
VIO
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
FFh
6-bit Nonvolatile
6-bit Nonvolatile
3-bit Nonvolatile
4-bit Nonvolatile
4-bit Nonvolatile
4-bit Nonvolatile
6-bit Nonvolatile
3-bit Nonvolatile
3-bit Nonvolatile
3-bit Nonvolatile
Volatile
21h
20h
03h
01h
09h
09h
20h
01h
03h
03h
00h
LSB
1
R
R
R
R
VCORE (Default Data: 01h)
MSB
VCORE
VON_LT
VON_HT
LSB
1
R
R
R
R
VON_LT (Default Data: 09h)
MSB
V
OFF
LSB
1
DLY1
DLY2
DLY3
CR
R
R
R
R
VON_HT (Default Data: 09h)
MSB
LSB
1
R
R
R
R
V
(Default Data: 20h)
OFF
MSB
LSB
0
R
R
1
0
DLY1 (Default Data: 01h)
MSB
LSB
1
R
R
R
R
DLY2 (Default Data: 03h)
MSB
LSB
1
R
R
R
R
DLY3 (Default Data: 03h)
MSB
LSB
1
R
R
R
R
Control Register (Default Data: 00h)
MSB
LSB
Write
EEPROM
Data
R
R
R
R
Read EEPROM
or DR data
R: Reserved
<Contol Register Data>
0h: Read DAC register data only
01h: ead EEPROM data only
80h Write all DAC Register data to EEPROM
FN7687 Rev 1.00
April 9, 2015
Page 22 of 28
ISL98604
TABLE 17. PARAMETER VALUES CORRESPONDING TO REGISTER VALUES
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
AVDD
(V)
HAVDD
(V)
VIO
(V)
VCORE
(V)
VON_LT
(V)
VON_HT
(V)
VOFF
(V)
DLY1
(ms)
DLY2
(ms)
DLY3
(ms)
STEP HEX
0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
12.7
12.8
12.9
13.0
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
13.9
14.0
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
15.0
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
15.9
16.0
16.1
16.2
16.3
16.4
6.40
6.45
6.50
6.55
6.60
6.65
6.70
6.75
6.80
6.85
6.90
6.95
7.00
7.05
7.10
7.15
7.20
7.25
7.30
7.35
7.40
7.45
7.50
7.55
7.60
7.65
7.70
7.75
7.80
7.85
7.90
7.95
8.00
8.05
8.10
8.15
8.20
8.25
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-1.8
-1.9
-2.0
-2.1
-2.2
-2.3
-2.4
-2.5
-2.6
-2.7
-2.8
-2.9
-3.0
-3.1
-3.2
-3.3
-3.4
-3.5
-3.6
-3.7
-3.8
-3.9
-4.0
-4.1
-4.2
-4.3
-4.4
-4.5
-4.6
-4.7
-4.8
-4.9
-5.0
-5.1
-5.2
-5.3
-5.4
-5.5
0
0
0
1
10
20
30
40
50
60
70
10
20
30
40
50
60
70
10
20
30
40
50
60
70
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
FN7687 Rev 1.00
April 9, 2015
Page 23 of 28
ISL98604
TABLE 17. PARAMETER VALUES CORRESPONDING TO REGISTER VALUES (Continued)
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
AVDD
(V)
HAVDD
(V)
VIO
(V)
VCORE
(V)
VON_LT
(V)
VON_HT
(V)
VOFF
(V)
DLY1
(ms)
DLY2
(ms)
DLY3
(ms)
STEP HEX
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
16.5
16.6
16.7
16.8
16.9
17.0
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
18.0
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
18.9
19.0
8.30
8.35
8.40
8.45
8.50
8.55
8.60
8.65
8.70
8.75
8.80
8.85
8.90
8.95
9.00
9.05
9.10
9.15
9.20
9.25
9.30
9.35
9.40
9.45
9.50
9.55
-5.6
-5.7
-5.8
-5.9
-6.0
-6.1
-6.2
-6.3
-6.4
-6.5
-6.6
-6.7
-6.8
-6.9
-7.0
-7.1
-7.2
-7.3
-7.4
-7.5
-7.6
-7.7
-7.8
-7.9
-8.0
-8.1
NOTE: Shaded numbers are the factory default at power-up.
PROTECTIONS
The ISL98604 integrates overcurrent protection (OCP), overvoltage
protection (OVP), and over-temperature protection (OTP). The
protection threshold and the reaction of the chip are listed in
Table 18.
FN7687 Rev 1.00
April 9, 2015
Page 24 of 28
ISL98604
TABLE 18. ISL98604 PROTECTION TABLE
CONTINUED FAUTL TIME
RE-ENABLE
CATEGORY
CHANNEL
AVDD
TRIP LEVEL (TYP)
TO SHUTDOWN
CHIP REACTION
Terminate PWM
MECHANISM
OCP
Switch peak current
higher than 4A
NA
NA
AVDD delay FET
IDS current higher than
3.1A during operation
1ms
Shut down whole IC
Shut down whole IC
Power Cycle
Power Cycle
IDS current higher than
6A at start-up and
normal operation
Immediately
HAVDD
Switch peak current
higher than 1A or lower
switch peak current
higher than 0.9A
NA
Terminate PWM
NA
VIO
VCORE
Switch peak current
higher than 2A
NA
Terminate PWM
Terminate PWM
NA
Switch peak current
higher than 1A
NA
NA
OVP
OTP
AVDD
Higher than 20.5V on
SWI pin
Immediately
Immediately
Shut down whole IC
Shut down whole IC
Power Cycle
Power Cycle
Junction Temp
Temperature higher
than +140°C
6. The exposed die plate, on the underside of the package,
should be soldered to an equivalent area of metal on the PCB.
This contact area should have multiple via connections to the
back of the PCB as well as connections to intermediate PCB
layers, if available, to maximize thermal dissipation away
from the IC.
Start-Up Sequence
When VIN rising exceeds UVLO and EN is high, VIO and VCORE
start-up. When VIO and VCORE reach 90% of the their target
values, after a delay time of DLY1, PGOOD rises up and VOFF
soft-starts; when VOFF reaches 90% of its target value, after a
delay time of DLY2, AVDD and HAVDD start to rise up. The
soft-start time of AVDD and HAVDD depends on the capacitance
on the soft-start pin. When AVDD and HAVDD reach 90% of their
target values, after a delay time of DLY3, V starts to rise up.
DLY1, DLY2 and DLY3 are programmable through I C control,
which is described in section “I C Control” on page 20. The detailed
start-up sequence is shown in Figure 24.
7. To minimize the thermal resistance of the package when
soldered to a multilayer PCB, the amount of copper track and
ground plane area connected to the exposed die plate should
be maximized and spread out as far as possible from the IC.
The bottom and top PCB areas especially should be
ON
2
2
maximized to allow thermal dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
Layout Recommendation
PCB layout is critical especially at high switching frequency. The
device's performance, including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout.
A demo board is available to illustrate the proper layout
implementation.
There are some general guidelines for layout:
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
2. Place V and V
DC REF
bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew rate.
4. The feedback network should sense the output voltage
directly from the point of load, and be as far away from the LX
node as possible.
5. The power ground (PGND) and signal ground (SGND) pins
should be connected at the ISL98604 exposed die plate area.
FN7687 Rev 1.00
April 9, 2015
Page 25 of 28
ISL98604
UVLO
VHI
U VLO
VLO
VIN
VD C
EN
VIO
90%
VC O R E
D LY1
PG O O D
VO FF
90%
90%
50%
D LY2
A VD D
50%
H A VD D
D LY3
VO N
NOTES:
8. VIO and VCORE start when EN is enabled and 90% rising point will occur at the same time.
The timing gap between VIO and VCORE at 90% rising point will be less than 3ms.
9. PGOOD and V
OFF
will be triggered after VIO and VCORE rise and not before delay time DLY1.
10. AVDD and HAVDD start-up after delay time DLY2. Both are synchronized at 50% rising point.
11. V will be triggered after AVDD and HAVDD rise and not before delay time DLY3.
ON
FIGURE 24. ISL98604 START-UP SEQUENCE
FN7687 Rev 1.00
April 9, 2015
Page 26 of 28
ISL98604
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7687.1
CHANGE
April 9, 2015
Removed "please contact Consumer Product Marketing via email at Consumer-All@intersil.com"
Updated About Intersil verbiage, Added word datasheet on page 1 and submit feedback button.
Changed switching frequency fs to fsw to be consistent throughout document.
December 17, 2012
FN7687.0
Initial Release.
About Intersil
IIntersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2012-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7687 Rev 1.00
April 9, 2015
Page 27 of 28
ISL98604
Package Outline Drawing
L40.5x5D
40 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 9/10
4X 3.60
36X 0.40
5.00
A
B
6
6
PIN #1 INDEX AREA
PIN 1
INDEX AREA
(4X)
0.15
40X 0.4± 0.1
0.20
4
0.10 M
C A B
b
TOP VIEW
BOTTOM VIEW
PACKAGE OUTLINE
0.40
SEE DETAIL "X"
0.750
0.10C
//
C
BASE PLANE
SEATING PLANE
0.08 C
0.050
SIDE VIEW
(36X 0.40)
(40X 0.20)
(40X 0.60)
5
0.2 REF
C
0.00 MIN
0.05 MAX
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.27mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
JEDEC reference drawing: MO-220WHHE-1
7.
FN7687 Rev 1.00
April 9, 2015
Page 28 of 28
相关型号：
ISL98665IRTZ
1-CHANNEL POWER SUPPLY SUPPORT CKT, PQCC28, 4 X 5 MM, ROHS COMPLIANT, PLASTIC, TQFN-28
RENESAS
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