ISLA216P25IR1Z [RENESAS]
16-Bit, 250MSPS/200MSPS/130MSPS ADC;
| 型号： | ISLA216P25IR1Z |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-Bit, 250MSPS/200MSPS/130MSPS ADC |
| 文件： | 总35页 (文件大小：1485K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISLA216P
16-Bit, 250MSPS/200MSPS/130MSPS ADC
FN7574
Rev 2.00
December 10, 2012
The ISLA216P is a family of low power, high performance
16-bit analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge™ technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA216P is part of a pin-compatible portfolio
of 12 to 16-bit A/Ds with maximum sample rates ranging from
130MSPS to 500MSPS.
Features
• Single supply 1.8V operation
• Clock duty cycle stabilizer
• 75fs Clock jitter
• 700MHz Bandwidth
• Programmable built-in test patterns
• Multi-ADC support
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
- SPI Programmable fine gain and offset control
- Support for multiple ADC synchronization
- Optimized output timing
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA216P is available in a 72-contact QFN
package with an exposed paddle. Operating from a 1.8V
supply, performance is specified over the full industrial
temperature range (-40°C to +85°C).
• Nap and sleep modes
- 200µs Sleep wake-up time
• Data output clock
Key Specifications
• SNR @ 250/200/130MSPS
• DDR LVDS-compatible or LVCMOS outputs
• Selectable Clock Divider
- 75.0/76.6/77.5dBFS f = 30MHz
IN
Applications
• Radar array processing
- 72.1/72.6/72.4dBFS f = 363MHz
IN
• SFDR @ 250/200/130MSPS
- 87/91/96dBc f = 30MHz
IN
• Software defined radios
- 81/80/82dBc f = 363MHz
IN
• Total Power Consumption = 786mW @ 250MSPS
• Broadband communications
• High-performance data acquisition
• Communications test equipment
Pin-Compatible Family
SPEED
(MSPS)
MODEL
RESOLUTION
ISLA216P25
ISLA216P20
ISLA216P13
ISLA214P50
ISLA214P25
ISLA214P20
ISLA214P13
ISLA212P50
ISLA212P25
ISLA212P20
ISLA212P13
16
16
16
14
14
14
14
12
12
12
12
250
200
130
500
250
200
130
500
250
200
130
CLKP
CLKOUTP
CLKOUTN
CLOCK
MANAGEMENT
CLKN
VINP
VINN
16-BIT
250 MSPS
ADC
SHA
D[14:0]P
D[14:0]N
DIGITAL
ERROR
CORRECTION
+
–
VCM
SPI
CONTROL
FN7574 Rev 2.00
December 10, 2012
Page 1 of 35
ISLA216P
Pin Configuration - LVDS MODE
ISLA216P
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63
62 61 60 59 58 57 56 55
DNC
DNC
1
2
54 DNC
DNC
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
D6P
4
D6N
5
AVSS
AVDD
AVSS
VINN
DNC
6
DNC
7
CLKOUTP
CLKOUTN
RLVDS
OVSS
D8P
8
9
VINN
10
11
12
13
14
VINP
VINP
AVSS
AVDD
AVSS
CLKDIV
IPTAT
DNC
D8N
DNC
DNC
15
16
17
40
D10P
39 D10N
38
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
DNC
37 DNC
Connect Thermal Pad to AVSS
RESETN 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Pin Descriptions - 72 Ld QFN, LVDS Mode
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
1, 2, 17, 28, 29, 33, 34, 37,
38, 41, 42, 49, 50, 53, 54,
57, 58
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71, 72
AVDD
AVSS
1.8V Analog Supply
Analog Ground
5, 7, 12, 14
27, 32, 62
26, 45, 61, 65
3
OVDD
OVSS
1.8V Output Supply
Output Ground
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
FN7574 Rev 2.00
December 10, 2012
Page 2 of 35
ISLA216P
Pin Descriptions - 72 Ld QFN, LVDS Mode (Continued)
PIN NUMBER
LVDS PIN NAME
LVDS PIN FUNCTION
4
VCM
Common Mode Output
Analog Input Negative
Analog Input Positive
8, 9
VINN
10, 11
VINP
15
CLKDIV
Tri-Level Clock Divider Control
16
IPTAT
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
18
RESETN
22, 23
CLKP, CLKN
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
DDR Logical Bits 14, 15 Complement
DDR Logical Bits 14, 15 True
24, 25
CLKDIVRSTP, CLKDIVRSTN
30
D14N
D14P
D12N
D12P
D10N
D10P
D8N
31
35
DDR Logical Bits 12, 13 Complement
DDR Logical Bits 12, 13 True
36
39
DDR Logical Bits 10, 11 Complement
DDR Logical Bits 10, 11 True
40
43
DDR Logical Bits 8, 9 Complement
DDR Logical Bits 8, 9 True
44
D8P
46
RLVDS
CLKOUTN, CLKOUTP
D6N
LVDS Bias Resistor (Connect to OVSS with 1%10k)
LVDS Clock Output Complement, True
DDR Logical Bits 6, 7 Complement
DDR Logical Bits 6, 7 True
47, 48
51
52
D6P
55
D4N
DDR Logical Bits 4, 5 Complement
DDR Logical Bits 4, 5 True
56
D4P
59
D2N
DDR Logical Bits 2, 3 Complement
DDR Logical Bits 2, 3 True
60
D2P
63
D0N
DDR Logical Bits 0, 1 Complement
DDR Logical Bits 0, 1 True
64
D0P
66
SDO
SPI Serial Data Output
67
CSB
SPI Chip Select (active low)
68
69
SCLK
SPI Clock
SDIO
SPI Serial Data Input/Output
Exposed Paddle
AVSS
Analog Ground
FN7574 Rev 2.00
December 10, 2012
Page 3 of 35
ISLA216P
Pin Configuration - CMOS MODE
ISLA216P
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61
60 59
58 57 56 55
DNC
DNC
1
2
54 DNC
DNC
D6
53
52
51
50
49
48
47
46
45
44
43
42
41
3
NAPSLP
VCM
4
DNC
DNC
DNC
CLKOUT
DNC
RLVDS
OVSS
D8
5
AVSS
AVDD
AVSS
VINN
VINN
VINP
VINP
AVSS
AVDD
AVSS
CLKDIV
IPTAT
DNC
6
7
8
9
10
11
12
13
14
DNC
DNC
DNC
D10
15
16
17
40
39
38
DNC
DNC
Thermal Pad Not Drawn to Scale,
Consult Mechanical Drawing
for Physical Dimensions
Connect Thermal Pad to AVSS
RESETN 18
37 DNC
19 20 21 22 23 24 25 26
27 28 29 30 31 32 33 34 35 36
Pin Descriptions - 72 Ld QFN, CMOS Mode
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
1, 2, 17, 28, 29, 30, 33, 34,
35, 37, 38, 39, 41, 42, 43,
47, 49, 50, 51, 53, 54, 55,
57, 58, 59, 63
DNC
Do Not Connect
6, 13, 19, 20, 21, 70, 71, 72
AVDD
AVSS
1.8V Analog Supply
Analog Ground
5, 7, 12, 14
27, 32, 62
26, 45, 61, 65
3
OVDD
OVSS
1.8V Output Supply
Output Ground
NAPSLP
Tri-Level Power Control (Nap, Sleep modes)
FN7574 Rev 2.00
December 10, 2012
Page 4 of 35
ISLA216P
Pin Descriptions - 72 Ld QFN, CMOS Mode (Continued)
PIN NUMBER
CMOS PIN NAME
CMOS PIN FUNCTION
4
VCM
Common Mode Output
Analog Input Negative
Analog Input Positive
8, 9
VINN
10, 11
VINP
15
CLKDIV
Tri-Level Clock Divider Control
16
IPTAT
Temperature Monitor (Output current proportional to absolute temperature)
Power On Reset (Active Low)
Clock Input True, Complement
Synchronous Clock Divider Reset True, Complement
DDR Logical Bits 14, 15
18
RESETN
22, 23
CLKP, CLKN
24, 25
CLKDIVRSTP, CLKDIVRSTN
31
D14
D12
D10
D8
36
DDR Logical Bits 12, 13
40
DDR Logical Bits 10, 11
44
DDR Logical Bits 8, 9
46
RLVDS
CLKOUT
D6
LVDS Bias Resistor (Connect to OVSS with 1%10k)
CMOS Clock Output
48
52
DDR Logical Bits 6, 7
56
D4
DDR Logical Bits 4, 5
60
D2
DDR Logical Bits 2, 3
64
D0
DDR Logical Bits 0, 1
66
SDO
CSB
SPI Serial Data Output
67
SPI Chip Select (active low)
SPI Clock
68
69
SCLK
SDIO
AVSS
SPI Serial Data Input/Output
Analog Ground
Exposed Paddle
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISLA216P13IRZ
ISLA216P20IRZ
ISLA216P25IRZ
ISLA216P13 IRZ
ISLA216P20 IRZ
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
72 Ld QFN
L72.10x10E
72 Ld QFN
72 Ld QFN
L72.10x10E
L72.10x10E
ISLA216P25 IRZ
ISLA216P13 IR1Z
ISLA216P20 IR1Z
Coming Soon
ISLA216P13IR1Z
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
48 Ld QFN
48 Ld QFN
48 Ld QFN
TBD
TBD
TBD
Coming Soon
ISLA216P20IR1Z
Coming Soon
ISLA216P25IR1Z
ISLA216P25 IR1Z
ISLA216IR72EV1Z
Evaluation Board (72 pin QFN ADC)
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4
termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for ISLA216P. For more information on MSL please see techbrief TB363.
FN7574 Rev 2.00
December 10, 2012
Page 5 of 35
ISLA216P
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User Initiated Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Divider Synchronous Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Global Device Configuration/Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Digital Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Equivalent Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
A/D Evaluation Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
LVCMOS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
FN7574 Rev 2.00
December 10, 2012
Page 6 of 35
ISLA216P
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latchup (Tested per JESD-78C;Class 2,Level A) . . . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
72 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . .
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
(°C/W)
23
24
(°C/W)
0.9
1.0
JA
JC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
4. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -2dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply
SAMPLE
A
IN
over the operating temperature range, -40°C to +85°C.
ISLA216P25
MIN MAX
ISLA216P20
MIN MAX
ISLA216P13
MIN MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
DC SPECIFICATIONS (Note 6)
Analog Input
Full-Scale Analog Input
Range
V
Differential
1.95
2.0
2.2
1.95
2.0
2.2
1.95
2.0
2.2
V
P-P
FS
Input Resistance
Input Capacitance
R
C
Differential
Differential
Full Temp
300
9
300
9
300
9
IN
pF
IN
Full Scale Range Temp.
Drift
A
180
180
180
ppm/°C
VTC
Input Offset Voltage
V
-5.0
-1.7
5.0
-5.0
-1.7
5.0
-5.0
-1.7
5.0
mV
V
OS
Common-Mode Output
Voltage
V
0.94
0.94
0.94
CM
Common-Mode Input
Current (per pin)
I
5.2
5.2
5.2
µA/MSPS
CM
Clock Inputs
Inputs Common Mode
Voltage
0.9
1.8
0.9
1.8
0.9
1.8
V
V
CLKP,CLKN Input Swing
Power Requirements
1.8V Analog Supply
Voltage
AVDD
OVDD
1.7
1.7
1.8
1.8
372
64
1.9
1.9
397
73
1.7
1.7
1.8
1.8
342
58
1.9
1.9
360
68
1.7
1.7
1.8
1.8
293
50
1.9
1.9
310
58
V
1.8V Digital Supply
Voltage
V
1.8V Analog Supply
Current
I
I
mA
mA
dB
AVDD
1.8V Digital Supply
Current (Note 6)
3mA LVDS
OVDD
Power Supply Rejection
Ratio
PSRR
30MHz, 50mVP-Psignal
on AVDD
-65
-65
-65
FN7574 Rev 2.00
December 10, 2012
Page 7 of 35
ISLA216P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -2dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply
SAMPLE
A
IN
over the operating temperature range, -40°C to +85°C. (Continued)
ISLA216P25
MIN MAX
ISLA216P20
MIN MAX
ISLA216P13
MIN MAX
PARAMETER
Total Power Dissipation
Normal Mode
SYMBOL
CONDITIONS
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
P
2mA LVDS
771
786
760
88
706
720
685
83
603
616
580
77
mW
mW
mW
mW
mW
µs
D
3mA LVDS
CMOS
846
770
662
Nap Mode
P
P
103
19
99
19
94
19
D
Sleep Mode
CSB at logic high
7
7
7
D
Nap/Sleep Mode
Wakeup Time
Sample Clock Running
200
400
630
AC SPECIFICATIONS
Differential Nonlinearity
DNL
INL
f
= 30MHz
-0.99 ±0.35
±10
-0.99 ±0.25
±6
-0.99 ±0.25
±5
LSB
IN
No Missing Codes
Integral Nonlinearity
f
= 30MHz
LSB
IN
Minimum Conversion
Rate (Note 7)
f
MIN
40
40
40
MSPS
S
Maximum Conversion
Rate
f
MAX
250
200
130
MSPS
S
Signal-to-Noise Ratio
(Note 8)
SNR
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
f
= 30MHz
75.0
76.6
77.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
71.7
74.9
74.2
72.1
71.1
69.2
74.7
74.1
73.1
71.6
69.2
65.7
12.12
74.8
76.4
75.3
72.6
71.1
69.2
76.5
76.1
74.7
71.7
68.6
64.9
12.42
75.5
76.9
75.3
72.4
70.8
68.9
77.4
76.1
74.6
71.9
67.9
66.3
12.56
Signal-to-Noise and
Distortion
(Note 8)
SINAD
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
70.0
73.2
72.6
Effective Number of Bits
(Note 8)
ENOB
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
11.34 12.02
11.85
11.87 12.35
12.12
11.77 12.35
12.10
Bits
Bits
11.60
11.62
11.65
Bits
11.20
11.10
10.99
Bits
10.62
10.49
10.72
Bits
FN7574 Rev 2.00
December 10, 2012
Page 8 of 35
ISLA216P
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
T
= -40°C to +85°C (typical specifications at +25°C), A = -2dBFS, f
= Maximum Conversion Rate (per speed grade). Boldface limits apply
SAMPLE
A
IN
over the operating temperature range, -40°C to +85°C. (Continued)
ISLA216P25
MIN MAX
ISLA216P20
MIN MAX
ISLA216P13
MIN MAX
PARAMETER
SYMBOL
SFDR
CONDITIONS
= 30MHz
(Note 5) TYP (Note 5) (Note 5) TYP (Note 5) (Note 5) TYP (Note 5) UNITS
Spurious-Free Dynamic
Range
(Note 8)
f
f
f
f
f
f
f
f
f
f
f
f
f
f
87
83
81
81
73
67
89
92
88
83
82
79
94
87
91
89
84
80
72
67
91
93
92
87
85
82
92
87
96
83
83
82
70
67
99
96
96
94
91
89
88
87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBFS
dBFS
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 30MHz
74
74
72
Spurious-Free Dynamic SFDRX23
Range Excluding H2, H3
(Note 8)
= 105MHz
= 190MHz
= 363MHz
= 461MHz
= 605MHz
= 70MHz
80
82
82
Intermodulation
Distortion
IMD
= 170MHz
-12
-12
-12
Word Error Rate
Full Power Bandwidth
NOTES:
WER
10
700
10
700
10
700
FPBW
MHz
5. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
6. Digital Supply Current is dependent upon the capacitive loading of the digital outputs. I
7. The DLL Range setting must be changed for low-speed operation.
8. Minimum specification guaranteed when calibrated at +85°C.
specifications apply for 10pF load on each digital output.
OVDD
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
(Note 5)
TYP
(Note 5) UNITS
INPUTS
Input Current High (RESETN)
Input Current Low (RESETN)
Input Current High (SDIO)
Input Current Low (SDIO)
Input Current High (CSB)
Input Current Low (CSB)
I
V
V
V
V
V
V
= 1.8V
= 0V
0
1
-12
4
10
-7
µA
µA
µA
µA
µA
µA
V
IH
IN
IN
IN
IN
IN
IN
I
-25
IL
I
= 1.8V
= 0V
12
IH
I
-600
40
-415
58
5
-300
75
IL
I
= 1.8V
= 0V
IH
I
10
IL
Input Voltage High (SDIO, RESETN)
Input Voltage Low (SDIO, RESETN)
Input Current High (CLKDIV) (Note 9)
Input Current Low (CLKDIV)
V
1.17
IH
V
0.63
34
V
IL
I
16
25
-25
4
µA
µA
pF
IH
I
-34
-16
IL
Input Capacitance
C
DI
FN7574 Rev 2.00
December 10, 2012
Page 9 of 35
ISLA216P
Digital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
(Note 5)
MAX
(Note 5) UNITS
PARAMETER
LVDS INPUTS (CLKDIVRSTP,CLKDIVRSTN)
Input Common Mode Range
Input Differential Swing (peak to peak, single-ended)
CLKDIVRSTP Input Pull-down Resistance
CLKDIVRSTN Input Pull-up Resistance
LVDS OUTPUTS
SYMBOL
CONDITIONS
TYP
V
825
250
1575
450
mV
mV
k
k
ICM
V
ID
R
R
100
100
Ipd
Ipu
Differential Output Voltage (Note 10)
Output Offset Voltage
V
3mA Mode
3mA Mode
612
1150
240
mV
P-P
T
V
1120
1200
mV
ps
OS
Output Rise Time
t
R
Output Fall Time
t
240
ps
F
CMOS OUTPUTS
Voltage Output High
V
I
I
= -500µA
= 1mA
OVDD - 0.3 OVDD - 0.1
V
V
OH
OH
Voltage Output Low
V
0.1
1.8
1.4
0.3
OL
OL
Output Rise Time
t
ns
ns
R
Output Fall Time
t
F
NOTES:
9. The Tri-Level Inputs internal switching thresholds are approximately. 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending
on desired function.
10. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential swing.
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUTN
CLKOUTP
tDC
tPD
D[14/12/…/2/0]N
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[14/12/…/2/0]P
FIGURE 1A. LVDS
FN7574 Rev 2.00
December 10, 2012
Page 10 of 35
ISLA216P
Timing Diagrams
INP
INN
tA
CLKN
CLKP
LATENCY = L CYCLES
tCPD
CLKOUT
tDC
tPD
ODD
N-L
EVEN
N-L
ODD
N-L+1
EVEN
N-L+1
EVEN
N-1
ODD
N
EVEN
N
D[14/12/…/2/0]
FIGURE 1B. CMOS
FIGURE 1. TIMING DIAGRAMS
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
(Note 5)
MAX
(Note 5)
PARAMETER
SYMBOL
CONDITION
TYP
UNITS
ADC OUTPUT
Aperture Delay
t
114
75
ps
fs
A
RMS Aperture Jitter
j
A
Input Clock to Output Clock Propagation
Delay
t
t
AVDD, OVDD = 1.7V to 1.9V,
1.65
2.4
3
ns
CPD
T
= -40°C to +85°C
A
AVDD, OVDD = 1.8V, T = +25°C
A
1.9
2.3
2.75
450
ns
ps
CPD
Relative Input Clock to Output Clock
Propagation Delay (Note 13)
dt
AVDD, OVDD = 1.7V to 1.9V,
-450
CPD
T
= -40°C to +85°C
A
Input Clock to Data Propagation Delay
t
t
1.65
-0.1
2.4
3.5
0.5
ns
ns
PD
Output Clock to Data Propagation Delay,
LVDS Mode
Rising/Falling Edge
Rising/Falling Edge
0.16
DC
Output Clock to Data Propagation Delay,
CMOS Mode
t
-0.1
0.4
0.2
0.65
ns
ns
DC
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
t
0.06
RSTS
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
t
0.02
52
0.35
ns
µs
RSTH
Synchronous Clock Divider Reset Recovery
Time
t
DLL recovery time after
Synchronous Reset
RSTRT
L
Latency (Pipeline Delay)
10
cycles
FN7574 Rev 2.00
December 10, 2012
Page 11 of 35
ISLA216P
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Overvoltage Recovery
SYMBOL
CONDITION
(Note 5)
TYP
1
(Note 5)
UNITS
cycles
t
OVR
SPI INTERFACE (Notes 11, 12)
SCLK Period
t
Write Operation
16
16
28
5
cycles
cycles
cycles
cycles
cycles
cycles
cycles
CLK
CLK
t
Read Operation
Read or Write
Write
CSB to SCLKSetup Time
CSB after SCLK Hold Time
Data Valid to SCLK Setup Time
Data Valid after SCLK Hold Time
Data Valid after SCLK↓ Time
NOTES:
t
S
t
H
t
Write
6
DS
DH
t
Read or Write
Read
4
5
t
DVR
11. SPI Interface timing is directly proportional to the ADC sample period (t ). Values above reflect multiples of a 4ns sample period, and must be scaled
S
proportionally for lower sample rates. ADC sample clock must be running for SPI communication.
12. The SPI may operate asynchronously with respect to the ADC sample clock.
13. The relative propagation delay is the difference in propagation time between any two devices that are matched in temperature and voltage, and is
specified over the full operating temperature and voltage range.
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -2dBFS,
A
IN
f
= 105MHz, f
= 250MSPS.
IN
SAMPLE
95
-65
-70
HD2 @ 250MSPS
90
85
80
75
SFDR @ 130MSPS
SFDR @ 250MSPS
-75
-80
-85
HD3 @ 250MSPS
-90
70
65
60
SNR @ 130MSPS
SNR @ 250MSPS
-95
HD3 @ 130MSPS
HD2 @ 130MSPS
-100
-105
0
100
200
300
400
500
600
0
100
200
300
400
500
600
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
FIGURE 3. HD2 AND HD3 vs f
FIGURE 2. SNR AND SFDR vs f
IN
IN
100
-40
-50
90
80
70
60
50
40
30
20
10
HD2 (dBc)
SFDR(dBfs)
-60
SNR(dBfs)
SFDR(dBc)
-70
HD3 (dBc)
-80
SNR(dBc)
HD2 (dBfs)
HD3 (dBfs)
-90
-100
-110
-60
-50
-40
-30
-20
-10
0
-60
-50
-40
-30
-20
-10
0
INPUT AMPLITUDE (dBFS)
INPUT AMPLITUDE (dBFS)
FIGURE 4. SNR AND SFDR vs A
FIGURE 5. HD2 AND HD3 vs A
IN
IN
FN7574 Rev 2.00
December 10, 2012
Page 12 of 35
ISLA216P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -2dBFS,
A
IN
f
= 105MHz, f
= 250MSPS. (Continued)
IN
SAMPLE
90
-75
-80
SFDR
H3
85
80
75
-85
-90
-95
SNR
H2
-100
-105
70
70
90
110 130 150 170 190 210 230 250
SAMPLE RATE (MSPS)
70
90
110 130 150 170 190 210 230 250
SAMPLE RATE (MSPS)
FIGURE 6. SNR AND SFDR vs f
FIGURE 7. HD2 AND HD3 vs f
SAMPLE
SAMPLE
1.5
800
750
700
650
600
550
500
1.0
0.5
0
LVDS
-0.5
-1.0
-1.5
CMOS
450
40
60
80 100 120 140 160 180 200 220 240
SAMPLE RATE (MSPS)
0
10,000 20,000 30,000 40,000 50,000 60,000
CODES
FIGURE 8. POWER vs f
IN 3mA LVDS MODE
FIGURE 9. DIFFERENTIAL NONLINEARITY
SAMPLE
20
85
80
75
70
65
60
SFDR
15
10
5
SNR
0
-5
-10
-15
-20
0
10,000 20,000 30,000 40,000 50,000 60,000
CODES
0.75
0.85
0.95
1.05
1.15
INPUT COMMON MODE (V)
FIGURE 10. INTEGRAL NONLINEARITY
FIGURE 11. SNR AND SFDR vs VCM
FN7574 Rev 2.00
December 10, 2012
Page 13 of 35
ISLA216P
Typical Performance Curves
All Typical Performance Characteristics apply under the following conditions unless otherwise noted: AVDD = OVDD = 1.8V, T = +25°C, A = -2dBFS,
A
IN
f
= 105MHz, f
= 250MSPS. (Continued)
IN
SAMPLE
0
-20
25000
A
= -2 dBFS
IN
SNR = 75.4 dBFS
SFDR = 82 dBc
SINAD = 74.5 dBFS
20000
15000
10000
5000
0
-40
-60
-80
-100
-120
0
20
40
60
80
100
120
120
120
32696 32700 32704 32708 32712 32716 32720 32724
CODE
FREQUENCY (MHz)
FIGURE 13. SINGLE-TONE SPECTRUM @ 105MHz
FIGURE 12. NOISE HISTOGRAM
0
-20
0
A
= -2 dBFS
IN
A
= -2 dBFS
IN
SNR = 74.5 dBFS
SFDR = 81 dBc
SNR = 72.4 dBFS
SFDR = 80 dBc
SINAD = 71.3 dBFS
-20
-40
SINAD = 73.67 dBFS
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 15. SINGLE-TONE SPECTRUM @ 363MHz
FIGURE 14. SINGLE-TONE SPECTRUM @ 190MHz
0
0
IMD3 = -94dBFS
IMD2
IMD3 = -87dBFS
IMD2
IMD3
2nd Harmonics
3rd Harmonics
IMD3
2nd Harmonics
3rd Harmonics
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-100
-120
0
20
40
60
80
100
120
0
20
40
60
80
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 16. TWO-TONE SPECTRUM
(F1 = 70MHz, F2 = 71MHz AT -7dBFS)
FIGURE 17. TWO-TONE SPECTRUM
(F1 = 170MHz, F2 = 171MHz AT -7dBFS)
FN7574 Rev 2.00
December 10, 2012
Page 14 of 35
ISLA216P
following conditions must be adhered to for the power-on
calibration to execute successfully:
Theory of Operation
Functional Description
The ISLA216P is based upon a 16-bit, 250MSPS A/D converter
core that utilizes a pipelined successive approximation
• A frequency-stable conversion clock must be applied to the
CLKP/CLKN pins
• DNC pins must not be connected
architecture (Figure 18). The input voltage is captured by a
Sample-Hold Amplifier (SHA) and converted to a unit of charge.
Proprietary charge-domain techniques are used to successively
compare the input to a series of reference charges. Decisions
made during the successive approximation operations determine
the digital code for each input value. Digital error correction is also
applied, resulting in a total latency of 10 clock cycles. This is
evident to the user as a latency between the start of a conversion
and the data being available on the digital outputs.
• SDO has an internal pull-up and should not be driven externally
• RESETN is pulled low by the ADC internally during POR.
External driving of RESETN is optional.
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the event
that the above conditions cannot be met at power-up.
After the power supply has stabilized the internal POR releases
RESETN and an internal pull-up pulls it high, which starts the
calibration sequence. If a subsequent user-initiated reset is
desired, the RESETN pin should be connected to an open-drain
driver with an off-state/high impedance state leakage of less
than 0.5mA to assure exit from the reset state so calibration can
start.
The ISLA216P family operates by simultaneously sampling the
input signal with two ADC cores in parallel and summing the
digital result. Since the input signal is correlated between the two
cores and noise is not, an increase in SNR is achieved. As a result,
the offset, gain, or operational mode of both cores should be
adjusted when a change to the ADC's offset, gain, or operational
mode is desired.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 19. Calibration status can be
determined by reading the cal_status bit (LSB) at 0xB6. This bit is
‘0’ during calibration and goes to a logic ‘1’ when calibration is
complete. The data outputs produce 0xCCCC during calibration;
this can also be used to determine calibration status.
Power-On Calibration
As mentioned previously, the cores perform a self-calibration at
start-up. An internal power-on-reset (POR) circuit detects the
supply voltage ramps and initiates the calibration when the
analog and digital supply voltages are above a threshold. The
If the selectable clock divider is set to 1 (default), the output
clock (CLKOUTP/CLKOUTN) will not be affected by the assertion
of RESETN. If the selectable clock divider is set to 2 or 4, the
output clock is set low while RESETN is asserted (low). Normal
operation of the output clock resumes at the next input clock
edge (CLKP/CLKN) after RESETN is de-asserted. At 250MSPS the
nominal calibration time is 200ms, while the maximum
calibration time is 550ms.
CLOCK
GENERATION
INP
2.5-BIT
2.5-BIT
6- STAGE
1.5-BIT/ STAGE
3- STAGE
1-BIT/ STAGE
3-BIT
FLASH
SHA
FLASH
FLASH
INN
+
1.25V
–
DIGITAL
ERROR
CORRECTION
LVDS/ LVCMOS
OUTPUTS
FIGURE 18. A/D CORE BLOCK DIAGRAM
FN7574 Rev 2.00
December 10, 2012
Page 15 of 35
ISLA216P
CLKN
CLKP
CALIBRATION
TIME
RESETN
CALIBRATION
BEGINS
CAL_STATUS
BIT
CALIBRATION
COMPLETE
CLKOUTP
FIGURE 19. CALIBRATION TIMING
User Initiated Reset
Recalibration of the A/D can be initiated at any time by driving
the RESETN pin low for a minimum of one clock cycle. An
open-drain driver with a drive strength in its high impedance
state of less than 0.5mA is recommended, as RESETN has an
internal high impedance pull-up to OVDD. As is the case during
power-on reset, RESETN and DNC pins must be in the proper
state for the calibration to successfully execute.
The performance of the ISLA216P25 changes with variations in
temperature, supply voltage or sample rate. The extent of these
changes may necessitate recalibration, depending on system
performance requirements. Best performance will be achieved
by recalibrating the A/D under the environmental conditions at
which it will operate.
A supply voltage variation of <100mV will generally result in an
SNR change of <0.5dBFS and SFDR change of <3dBc.
In situations where the sample rate is not constant, best results
will be obtained if the device is calibrated at the highest sample
rate. Reducing the sample rate by less than 80MSPS will typically
result in an SNR change of <0.5dBFS and an SFDR change of
<3dBc.
Figures 20 through 25 show the effect of temperature on SNR
and SFDR performance with power on calibration performed at
-40°C, +25°C, and +85°C. Each plot shows the variation of
SNR/SFDR across temperature after a single power on
calibration at -40°C, +25°C and +85°C. Best performance is
typically achieved by a user-initiated power on calibration at the
operating conditions, as stated earlier. However, it can be seen
that performance drift with temperature is not a very strong
function of the temperature at which the power on calibration is
performed; also note that SFDR performance typically improves
as the analog input level moves away from full-scale as Figure 4
shows.
FN7574 Rev 2.00
December 10, 2012
Page 16 of 35
ISLA216P
Temperature Calibration
78
95
90
85
80
130MSPS
77
250MSPS
130MSPS
200MSPS
250MSPS
200MSPS
76
75
74
-40
-35
-30
-25
-20
-40
-35
-30
-25
-20
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
FIGURE 20. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT -40°C, f = 105MHz, -2dBFS
DEVICE CALIBRATED AT -40°C, f = 105MHz, -2dBFS
IN
IN
78
77
76
75
74
95
130MSPS
200MSPS
200MSPS
90
130MSPS
85
250MSPS
10
250MSPS
80
5
15
20
25
30
35
40
45
5
10
15
20
25
30
35
40
45
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 22. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
FIGURE 23. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +25°C, f = 105MHz, -2dBFS
DEVICE CALIBRATED AT +25°C, f = 105MHz, -2dBFS
IN
IN
95
90
85
80
78
77
76
75
74
130MSPS
200MSPS
200MSPS
250MSPS
130MSPS
250MSPS
65
67
69
71
73
75
77
79
81
83
85
65
70
75
80
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 25. TYPICAL SFDR PERFORMANCE vs TEMPERATURE,
FIGURE 24. TYPICAL SNR PERFORMANCE vs TEMPERATURE,
DEVICE CALIBRATED AT +85°C, f = 105MHz, -2dBF
DEVICE CALIBRATED AT +85°C, f = 105MHz, -2dBFS
IN
IN
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
Analog Input
A single fully differential input (VINP/VINN) connects to the
sample and hold amplifier (SHA) of each unit A/D. The ideal
full-scale input voltage is 2.0V, centered at the VCM voltage of
0.94V as shown in Figure 26.
1.8
1.4
1.0
0.6
0.2
VINN
VINP
VCM
0.94V
1.0V
FIGURE 26. ANALOG INPUT RANGE
Best performance is obtained when the analog inputs are driven
differentially. The common-mode output voltage, VCM, should be
used to properly bias the inputs as shown in Figures 27 through
29. An RF transformer will give the best noise and distortion
performance for wideband and/or high intermediate frequency
(IF) inputs. Two different transformer input schemes are shown in
Figures 27 and 28.
ADT1-1WT
ADT1-1WT
1000pF
A/D
VCM
0.1µF
FIGURE 27. TRANSFORMER INPUT FOR GENERAL PURPOSE
APPLICATIONS
TX-2-5-1
ADTL1-12
1000pF
A/D
VCM
1000pF
FIGURE 28. TRANSMISSION-LINE TRANSFORMER INPUT FOR
HIGH IF APPLICATIONS
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
This dual transformer scheme is used to improve common-mode
rejection, which keeps the common-mode level of the input
matched to VCM. The value of the shunt resistor should be
determined based on the desired load impedance. The
differential input resistance of the ISLA216P25 is 300.
1000pF
TC4-19G2+
CLKP
200
0.01µF
The SHA design uses a switched capacitor input stage (see
Figure 42), which creates current spikes when the sampling
capacitance is reconnected to the input voltage. This causes a
disturbance at the input which must settle before the next
sampling point. Lower source impedance will result in faster
settling and improved performance. Therefore a 2:1 or 1:1
transformer and low shunt resistance are recommended for
optimal performance.
CLKN
1000pF
1000pF
FIGURE 30. RECOMMENDED CLOCK DRIVE
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
A/D
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
AVSS
DIVIDE RATIO
2
1
4
FIGURE 29. DIFFERENTIAL AMPLIFIER INPUT
Float
A differential amplifier, as shown in the simplified block diagram
in Figure 29, can be used in applications that require
AVDD
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 24. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
DC-coupling. In this configuration, the amplifier will typically
dominate the achievable SNR and distortion performance.
Intersil’s new ISL552xx differential amplifier family can also be
used in certain AC applications with minimal performance
degradation. Contact the factory for more information.
Clock Input
The clock input circuit is a differential pair (see Figure 43).
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Driving these inputs with a high level (up to 1.8V
on each
P-P
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (t ) and SNR is shown in Equation 1 and is
J
illustrated in Figure 31.
The recommended drive circuit is shown in Figure 30. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
1
-------------------
SNR = 20 log
(EQ. 1)
10
2f
t
IN J
FN7574 Rev 2.00
December 10, 2012
Page 19 of 35
ISLA216P
Nap/Sleep
100
95
90
85
80
75
70
65
60
55
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to <103mW while Sleep mode reduces power
dissipation to <19mW.
tj = 0.1ps
14 BITS
12 BITS
tj = 1ps
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52µs
to regain lock at 250MSPS.
tj = 10ps
10 BITS
tj = 100ps
50
1M
10M
100M
1G
INPUT FREQUENCY (Hz)
FIGURE 31. SNR vs CLOCK JITTER
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instant shown in Figure1A. The internal aperture jitter
combines with the input clock jitter in a root-sum-square fashion,
since they are not statistically correlated, and this determines
the total jitter in the system. The total jitter, combined with other
noise sources, then determines the achievable SNR.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
AVSS
MODE
Normal
Sleep
Nap
Float
AVDD
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
contained in “Serial Peripheral Interface” on page 24.
Voltage Reference
A temperature compensated internal voltage reference provides
the reference charges used in the successive approximation
operations. The full-scale range of each A/D is proportional to the
reference voltage. The nominal value of the voltage reference is
1.25V.
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Interface” on page 24.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 1A and 1B show the timing
relationships for LVDS and CMOS modes, respectively.
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA(default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout, therefore the user should
experiment to determine if performance degradation is
observed.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 32 shows this
operation.
BINARY
15
14
13
1
0
• • • •
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
page 24.
An external resistor creates the bias for the LVDS drivers. A 10k,
1% resistor must be connected from the RLVDS pin to OVSS.
• • • •
• • • •
Power Dissipation
GRAY CODE
15
14
13
1
0
The power dissipated by the ISLA216P25 is primarily dependent
on the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
FIGURE 32. BINARY TO GRAY CODE CONVERSION
FN7574 Rev 2.00
December 10, 2012
Page 20 of 35
ISLA216P
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 33.
Clock Divider Synchronous Reset
If the selectable clock divider is used, the ADC's internal sample
clock will be at half the frequency (DIV=2) or one quarter the
frequency (DIV=4) of the device clock. The phase relationship
between the sample clock and the device clock is initially
indeterminate. An output clock (CLKOUTP, CLKOUTN) is provided
to facilitate latching of the sampled data and estimation of the
internal sample clock's phase. The output clock has a fixed
phase relationship to the sample clock. When the selectable
clock divider is set to 2 or 4, the output clock's phase relationship
to the sample clock remains fixed but is initially indeterminate
with respect to the device clock. When the selectable clock
divider is set to 2 or 4, the synchronous clock divider reset
feature allows the phase of the internal sample clock and the
output clock to be synchronized (refer to Figure 34) with respect
to the device clock. This simplifies data capture in systems
employing multiple A/Ds where sampling of the inputs is desired
to be synchronous.
GRAY CODE
15
14
13
1
0
• • • •
• • • •
• • • •
• • • •
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 11).
A 100 differential termination resistor must be supplied
between CLKDIVRSTP and CLKDIVRSTN, external to the ADC, (on
the PCB) and should be located as close to the CLKDIVRSTP/N
pins as possible.
BINARY
15
14
13
1
0
FIGURE 33. GRAY CODE TO BINARY CONVERSION
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
TWO’S
VOLTAGE
OFFSET BINARY
COMPLEMENT
GRAY CODE
–Full Scale 0000 0000 0000
0000
1000 0000 0000
0000
0000 0000 0000
0000
–Full Scale 0000 0000 0000
1000 0000 0000
0001
0000 0000 0000
0001
+ 1LSB
0001
Mid–Scale 1000 0000 0000
0000
0000 0000 0000
0000
1100 0000 0000
0000
+Full Scale 1111 1111 1111
0111 1111 1111
1110
1000 0000 0000
0001
– 1LSB
1110
+Full Scale 1111 1111 1111
1111
0111 1111 1111
1111
1000 0000 0000
0000
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
DEVICE CLOCK INPUT
ANALOG INPUT
(Note 14)
L+td
s1
tRSTH
(Note 15)
CLKDIVRSTP
tRSTS
tRSTRT
ADC1 OUTPUT DATA
s0
S0
s1
s1
ODD
EVEN
ODD
EVEN
ADC1 CLKOUTP
S0
EVEN
S1
EVEN
s0
ODD
s1
ODD
ADC2 OUTPUT DATA
ADC2 CLKOUTP
(Note 16)
(PHASE 1)
ADC2 CLKOUTP
(PHASE 2)
(Note 16)
FIGURE 34. SYNCHRONOUS RESET OPERATION, CLOCK DIVIDE = 2
NOTES:
14. Delay equals fixed pipeline latency (L cycles of sample clock) plus fixed analog propagation delay, td.
15. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.CLKDIVRSTN is not
shown, but must be driven, and is the compliment of CLKDIVRSTP.
16. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
CSB
SCLK
SDIO
R/W
W1
W0
A12
A11
A10
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
FIGURE 35. MSB-FIRST ADDRESSING
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
CSB
SCLK
SDIO
A0
A1
A2
A11
A12
W0
W1
R/W
D0
D1
D2
D3
D4
D5
D6
D7
FIGURE 36. LSB-FIRST ADDRESSING
t
DSW
t
t
t
CLK
HI
H
t
DHW
CSB
t
t
S
LO
SCLK
SDIO
R/W W1 W0 A12 A11 A10 A9
A8
A7
D0
D5
D4
D3
D2
D1
SPI WRITE
FIGURE 37. SPI WRITE
tDSW
tCLK
tH
tHI
tDVR
tS
CSB
tDHW
tLO
SCLK
WRITING A READ COMMAND
READING DATA
)
( 3 WIRE MODE
D2 D1 D0
SDIO
SDO
R/W
W1 W0
A12 A11
A10
A9
A2
A1
A0
D7
D6
D3
( 4 WIRE MODE)
D3 D2 D1 D0
D7
SPI READ
FIGURE 38. SPI READ
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD 2
FIGURE 39. 2-BYTE TRANSFER
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
LAST LEGAL
CSB STALLING
CSB
SCLK
SDIO
INSTRUCTION/ADDRESS
DATA WORD 1
DATA WORD N
FIGURE 40. N-BYTE TRANSFER
MSB-first mode, the address is incremented for multi-byte
transfers, while in LSB-first mode it’s decremented.
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate
In the default mode, the MSB is R/W, which determines if the
data is to be read (active high) or written. The next two bits, W1
and W0, determine the number of data bytes to be read or
written (see Table 4). The lower 13 bits contain the first address
for the data transfer. This relationship is illustrated in Figure 37,
and timing values are given in “Switching
configuration of the device and to optimize performance. The SPI
bus consists of chip select (CSB), serial clock (SCLK) serial data
output (SDO), and serial data input/output (SDIO). The maximum
SCLK rate is equal to the A/D sample rate (f
) divided by 16
SAMPLE
for both write operations and read operations. At f
=
SAMPLE
250MHz, maximum SCLK is 15.63MHz for writing and read
operations. There is no minimum SCLK rate.
Specifications Boldface limits apply over the operating
temperature range, -40°C to +85°C.” on page 11.
The following sections describe various registers that are used to
configure the SPI or adjust performance or functional parameters.
Many registers in the available address space (0x00 to 0xFF) are
not defined in this document. Additionally, within a defined
register there may be certain bits or bit combinations that are
reserved. Undefined registers and undefined values within defined
registers are reserved and should not be selected. Setting any
reserved register or value may produce indeterminate results.
After the instruction/address bytes have been read, the
appropriate number of data bytes are written to or read from the
A/D (based on the R/W bit status). The data transfer will
continue as long as CSB remains low and SCLK is active. Stalling
of the CSB pin is allowed at any byte boundary
(instruction/address or data) if the number of bytes being
transferred is three or less. For transfers of four bytes or more,
CSB is allowed to stall in the middle of the instruction/address
bytes or before the first data byte. If CSB transitions to a high
state after that point the state machine will reset and terminate
the data transfer.
SPI Physical Interface
The serial clock pin (SCLK) provides synchronization for the data
transfer. By default, all data is presented on the serial data
input/output (SDIO) pin in three-wire mode. The state of the SDIO
pin is set automatically in the communication protocol
(described in the following). A dedicated serial data output pin
(SDO) can be activated by setting 0x00[7] high to allow operation
in four-wire mode.
TABLE 4. BYTE TRANSFER SELECTION
[W1:W0]
00
BYTES TRANSFERRED
1
01
2
3
The SPI port operates in a half duplex master/slave
configuration, with the ISLA216P25 functioning as a slave.
Multiple slave devices can interface to a single master in
three-wire mode only, since the SDO output of an unaddressed
device is asserted in four wire mode.
10
11
4 or more
Figures 39 and 40 illustrate the timing relationships for 2-byte
and N-byte transfers, respectively. The operation for a 3-byte
transfer can be inferred from these diagrams.
The chip-select bar (CSB) pin determines when a slave device is
being addressed. Multiple slave devices can be written to
concurrently, but only one slave device can be read from at a
given time (again, only in three-wire mode). If multiple slave
devices are selected for reading at the same time, the results will
be indeterminate.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit order
can be selected as MSB to LSB (MSB first) or LSB to MSB (LSB
first) to accommodate various micro controllers.
The communication protocol begins with an instruction/address
phase. The first rising SCLK edge following a high-to-low
Bit 7 SDO Active
Bit 6 LSB First
transition on CSB determines the beginning of the two-byte
instruction/address command; SCLK must be static low before
the CSB transition. Data can be presented in MSB-first order or
LSB-first order. The default is MSB-first, but this can be changed
by setting 0x00[6] high. Figures 35 and 36 show the appropriate
bit ordering for the MSB-first and LSB-first modes, respectively. In
Setting this bit high configures the SPI to interpret serial data
as arriving in LSB to MSB order.
FN7574 Rev 2.00
December 10, 2012
Page 24 of 35
ISLA216P
Bit 5 Soft Reset
ADDRESS 0X22: GAIN_COARSE_ADC0
ADDRESS 0X23: GAIN_MEDIUM_ADC0
ADDRESS 0X24: GAIN_FINE_ADC0
Setting this bit high resets all SPI registers to default values.
Bit 4 Reserved
This bit should always be set high.
Gain of the A/D core can be adjusted in coarse, medium and fine
steps. Coarse gain is a 4-bit adjustment while medium and fine
are 8-bit. Multiple Coarse Gain Bits can be set for a total
adjustment range of ±4.2%. (‘0011’ -4.2% and ‘1100’ +4.2%)
It is recommended to use one of the coarse gain settings (-4.2%,
-2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and fine-tune the gain using the
registers at 0x0023 and 0x24.
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode can
improve throughput by eliminating redundant addressing. The
burst is ended by pulling the CSB pin high. Setting the burst_end
address determines the end of the transfer. During a write
operation, the user must be cautious to transmit the correct
number of bytes based on the starting and ending addresses.
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x23 and 0x24 to be used by the
ADC (see description for 0xFE).
Bits 7:0 Burst End Address
This register value determines the ending address of the burst
data.
TABLE 6. COARSE GAIN ADJUSTMENT
Device Information
0x22[3:0] core 0
0x26[3:0] core 1
NOMINAL COARSE GAIN ADJUST
(%)
ADDRESS 0X08: CHIP_ID
Bit3
Bit2
Bit1
Bit0
+2.8
+1.4
-2.8
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number, respectively, can
be read from these two registers.
-1.4
Device Configuration/Control
A common SPI map, which can accommodate single-channel or
multi-channel devices, is used for all Intersil A/D products.
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
0x23[7:0]
0x24[7:0]
PARAMETER
Steps
MEDIUM GAIN
FINE GAIN
ADDRESS 0X20: OFFSET_COARSE_ADC0
ADDRESS 0X21: OFFSET_FINE_ADC0
256
-2%
256
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-0.20%
0.00%
The input offset of the A/D core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is twos complement.
0.00%
+2%
+0.2%
0.016%
0.0016%
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register. Bit 0 in register 0xFE must be set high
to enable updates written to 0x20 and 0x21 to be used by the
ADC (see description for 0xFE).
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to“Nap/Sleep” on page 20). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
TABLE 5. OFFSET ADJUSTMENTS
0x20[7:0]
0x21[7:0]
PARAMETER
Steps
COARSE OFFSET
FINE OFFSET
TABLE 8. POWER-DOWN CONTROL
0x25[2:0]
255
255
–Full Scale (0x00)
Mid–Scale (0x80)
+Full Scale (0xFF)
Nominal Step Size
-133LSB (-47mV)
0.0LSB (0.0mV)
+133LSB (+47mV)
1.04LSB (0.37mV)
-5LSB (-1.75mV)
0.0LSB
VALUE
000
001
POWER DOWN MODE
Pin Control
+5LSB (+1.75mV)
0.04LSB (0.014mV)
Normal Operation
Nap Mode
010
100
Sleep Mode
FN7574 Rev 2.00
December 10, 2012
Page 25 of 35
ISLA216P
controlled through the SPI, as shown in Table 9. This register is
not changed by a Soft Reset.
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
TABLE 9. CLOCK DIVIDER SELECTION
The input offset of A/D core#1 can be adjusted in fine and
coarse steps in the same way that offset for core#0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
0x72[2:0]
VALUE
000
CLOCK DIVIDER
Pin Control
The default value of each register will be the result of the self-
calibration after initial power-up. If a register is to be incremented or
decremented, the user should first read the register value then write
the incremented or decremented value back to the same register.
Bit 0 in register 0xFE must be set high to enable updates written to
0x26 and 0x27 to be used by the ADC (see description for 0xFE).
001
Divide by 1
010
Divide by 2
other
Not Allowed
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA216P25 can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default,3mA or low (2mA).
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Bit 0 in register 0xFE must be set high to enable updates written to
0x29 and 0x2A to be used by the ADC (see description for 0xFE).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
This register is not changed by a Soft Reset.
TABLE 10. OUTPUT MODE CONTROL
0x73[7:5]
VALUE
000
OUTPUT MODE
LVDS 3mA (Default)
LVDS 2mA
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
001
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily latch
the data from each A/D by controlling the phase of the output data
clock. This control is accomplished through the use of the phase_slip
SPI feature, which allows the rising edge of the output data clock to be
advanced by one input clock period, as shown in the Figure 41.
Execution of a phase_slip command is accomplished by first writing a
'0' to bit 0 at address 0x71, followed by writing a '1' to bit 0 at address
0x71.
100
LVCMOS
TABLE 11. OUTPUT FORMAT CONTROL
0x73[2:0]
VALUE
OUTPUT FORMAT
Two’s Complement (Default)
Gray Code
000
010
100
Offset Binary
ADC Input
Clock (500MHz)
ADDRESS 0X74: OUTPUT_MODE_B
2ns
4ns
Output Data
Clock (250MHz)
No clock_slip
Bit 6 DLL Range
2ns
This bit sets the DLL operating range to fast (default) or slow.
Output Data
Clock (250MHz)
1 clock_slip
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 12 shows the allowable
sample rate ranges for the slow and fast settings.Note that Bit 4
at 0x74 is reserved and must not change value. A user writing to
Bit 6 should first read 0x74 to determine proper value to write
back to Bit 4 when writing to 0x74
Output Data
Clock (250MHz)
2 clock_slip
FIGURE 41. PHASE SLIP
TABLE 12. DLL RANGES
DLL RANGE
Slow
MIN
40
MAX
100
250
UNIT
MSPS
MSPS
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA216P25 has a selectable clock divider that can be set to
divide by two or one (no division). By default, the tri-level CLKDIV
pin selects the divisor This functionality can be overridden and
Fast
80
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
ADDRESS 0XB6: CALIBRATION STATUS
ADDRESS 0XC3: USER_PATT2_LSB
ADDRESS 0XC4: USER_PATT2_MSB
The LSB at address 0xB6 can be read to determine calibration
status. The bit is ‘0’ during calibration and goes to a logic ‘1’
when calibration is complete.This register is unique in that it can
be read after POR at calibration, unlike the other registers on
chip, which can’t be read until calibration is complete.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 2
ADDRESS 0XC5: USER_PATT3_LSB
ADDRESS 0XC6: USER_PATT3_MSB
DEVICE TEST
The ISLA216P25 can produce preset or user defined patterns on
the digital outputs to facilitate in-situ testing. A user can pick
from preset built-in patterns by writing to the output test mode
field [7:4] at 0xC0 or user defined patterns by writing to the user
test mode field [2:0] at 0xC0. The user defined patterns should
be loaded at address space 0xC1 through 0xD0, see the “SPI
Memory Map” on page 29 for more detail.The predefined
patterns are shown in Table 13. The test mode is enabled
asynchronously to the sample clock, therefore several sample
clock cycles may elapse before the data is present on the output
bus.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 3
ADDRESS 0XC7: USER_PATT4_LSB
ADDRESS 0XC8: USER_PATT4_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 4.
ADDRESS 0XC9: USER_PATT5_LSB
ADDRESS 0XCA: USER_PATT5_MSB
ADDRESS 0XC0: TEST_IO
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 5.
Bits 7:4 Output Test Mode
These bits set the test mode according to Table 13. Other
values are reserved.User test patterns loaded at 0xC1 through
0xD0 are also available by writing ‘1000’ to [7:4] at 0xC0 and a
pattern depth value to [2:0] at 0xC0. See “SPI Memory Map”
on page 29.
ADDRESS 0XCB: USER_PATT6_LSB
ADDRESS 0XCC: USER_PATT6_MSB
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 6
Bits 2:0 User Test Mode
ADDRESS 0XCD: USER_PATT7_LSB
ADDRESS 0XCE: USER_PATT7_MSB
The three LSBs in this register determine the test pattern in
combination with registers 0xC1 through 0xD0. Refer to the
“SPI Memory Map” on page 29.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 7.
TABLE 13. OUTPUT TEST MODES
0xC0[7:4]
ADDRESS 0XCF: USER_PATT8_LSB
ADDRESS 0XD0: USER_PATT8_MSB
VALUE
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
OUTPUT TEST MODE
WORD 1
WORD 2
Off
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 8.
Midscale
0x8000
0xFFFF
0x0000
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Positive Full-Scale
Negative Full-Scale
Reserved
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments ADC0 (0x20 and 0x21), ADC1
(0x26 and 0x27) and gain medium and gain fine adjustments
ADC0 (0x23 and 0x24), ADC1 (0x29 and 0x2A). It is
recommended that new data be written to the offset and gain
adjustment registers ADC0(0x20, 0x21, 0x23, 0x24) and
ADC1(0x26, 0x27, 0x29, 0x2A) while Bit 0 is a '0'. Subsequently,
Bit 0 should be set to '1' to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a '0' upon completion
Reserved
N/A
Reserved
N/A
Reserved
User Pattern
Reserved
user_patt1
N/A
user_patt2
N/A
Ramp
N/A
N/A
Digital Temperature Sensor
ADDRESS 0XC1: USER_PATT1_LSB
ADDRESS 0XC2: USER_PATT1_MSB
ADDRESS 0X4B: TEMP_COUNTER_HIGH
Bits [2:0] of this register hold the 3 MSBs of the 11-bit
temperature code.
These registers define the lower and upper eight bits,
respectively, of the user-defined pattern 1.
FN7574 Rev 2.00
December 10, 2012
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ISLA216P
Bit [7] of this register indicates a valid temperature_counter read
was performed. A logic ‘1’ indicates a valid read.
ADDRESS 0X4C: TEMP_COUNTER_LOW
Bits [7:0] of this register hold the lower 8 LSBs of the 11-bit
temperature code.
ADDRESS 0X4D: TEMP_COUNTER_CONTROL
Bit [7] Measurement mode select bit, set to ‘1’ for recommended
PTAT mode. ‘0’ (default) is IPTAT mode and is less accurate and
not recommended.
Bit [6] Temperature counter enable bit. Set to ‘1’ to enable.
Bit [5] Temperature counter power down bit. Set to ‘1’ to
power-down temperature counter.
Bit [4] Temperature counter reset bit. Set to ‘1’ to reset count.
Bit [3:1] Three bit frequency divider field. Sets temperature
counter update rate. Update rate is proportional to ADC sample
clock rate and divide ratio. A ‘101’ updates the temp counter
every ~ 66µs (for 250MSPS). Faster updates rates result in lower
precision.
Bit [0] Select sampler bit. Set to ‘0’.
This set of registers provides digital access to an PTAT or
IPTAT-based temperature sensor, allowing the system to
estimate the temperature of the die, allowing easy access to
information that can be used to decide when to recalibrate the
A/D as needed.
The nominal transfer function of the temperature monitor should
be estimated for each device by reading the temperature sensor
at two temperatures and extrapolating a line through these two
points.
A typical temperature measurement can occur as follows:
1. Write ‘0xCA’ to address 0x4D - enable temp counter,
divide=’101’
2. Wait ≥ 132µs (at 250Msps) - longer wait time ensures the
sensor completes one valid cycle.
3. Write ‘0x20’ to address 0x4D - power down, disable temp
counter-recommended between measurements. This
ensures that the output does not change between MSB and
LSB reads.
4. Read address 0x4B (MSBs)
5. Read address 0x4C (LSBs)
6. Record temp code value
7. Write ‘0x20’ to address 0x4D - power-down, disable temp
counter. Contact the factory for more information if needed.
FN7574 Rev 2.00
December 10, 2012
Page 28 of 35
ISLA216P
SPI Memory Map
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
port_config
Reserved
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
00
SDO Active LSB First Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
01
Reserved
02
burst_end
Burst end address [7:0]
Reserved
00h
03-07
Reserved
08
09
chip_id
chip_version
Chip ID #
Chip Version #
Reserved
Read only
Read only
0A-0F
10-1F
20
Reserved
Reserved
Reserved
offset_coarse_adc0
offset_fine_adc0
gain_coarse_adc0
gain_medium_adc0
gain_fine_adc0
modes_adc0
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
21
22
Reserved
Reserved
Coarse Gain
23
Medium Gain
Fine Gain
24
25
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT reset by
Soft Reset
100 = Sleep
Other codes = Reserved
26
27
28
29
2A
2B
offset_coarse_adc1
offset_fine_adc1
gain_coarse_adc1
gain_medium_adc1
gain_fine_adc1
Coarse Offset
Fine Offset
cal. value
cal. value
cal. value
cal. value
cal. value
Reserved
Reserved
Coarse Gain
Medium Gain
Fine Gain
modes_adc1
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
00h
NOT reset by
Soft Reset
100 = Sleep
Other codes = Reserved
2C-2F
30-4A
4B
Reserved
Reserved
Reserved
Reserved
temp_counter_high
temp_counter_low
temp_counter_control
Reserved
Temp Counter [10:8]
Read only
Read only
00h
4C
Temp Counter [7:0]
Reset
4D
Enable
PD
Divider [2:0]
Select
4E-6F
70
Reserved
skew_diff
Differential Skew
Reserved
80h
00h
71
phase_slip
Next Clock
Edge
72
clock_divide
Clock Divide [2:0]
00h
000 = Pin Control
001 = divide by 1
NOT reset by
Soft Reset
010 = divide by 2
100 = divide by 4
Other codes = Reserved
FN7574 Rev 2.00
December 10, 2012
Page 29 of 35
ISLA216P
SPI Memory Map (Continued)
ADDR.
DEF. VALUE
(HEX)
(Hex)
PARAMETER NAME
output_mode_A
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
73
Output Mode [7:5]
Output Format [2:0]
00h
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
000 = Two’s Complement (Default) NOT reset by
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
Soft Reset
74
output_mode_B
DLL Range
0 = Fast
1 = Slow
Reserved
00h
NOT reset by
Soft Reset
Default=’0’
75-B5
B6
Reserved
cal_status
Reserved
Calibration
Done
Read Only
00h
B7-BF
C0
Reserved
test_io
Output Test Mode [7:4]
User Test Mode [2:0]
0 = user pattern 1 only
0 = Off (Note 17)
1 = Midscale Short
2 = +FS Short
1 = cycle pattern 1,3
2 = cycle pattern 1,3,5
3 = cycle pattern 1,3,5,7
4-7 = NA
3 = -FS Short
4 = Reserved (Note18)
5-6 = Reserved
7 = Reserved (Note19)
8 = User Pattern (1 to 4 deep)
9 = Reserved
10 = Ramp
11-15 = Reserved
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
user_patt1_lsb
user_patt1_msb
user_patt2_lsb
user_patt2_msb
user_patt3_lsb
user_patt3_msb
user_patt4_lsb
user_patt4_msb
user_patt5_lsb
user_patt5_msb
user_patt6_lsb
user_patt6_msb
user_patt7_lsb
user_patt7_msb
user_patt8_lsb
user_patt8_msb
Reserved
B7
B15
B7
B6
B14
B6
B5
B13
B5
B4
B12
B4
B3
B11
B3
B2
B10
B2
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B1
B9
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
B0
B8
0x00
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CD
CE
B15
B7
B14
B6
B13
B5
B12
B4
B11
B3
B10
B2
CF
D0
D1-FD
FE
B15
B14
B13
B12
B11
B10
Reserved
Reserved
Offset/Gain_Adjust_Enable
Enable
00h
1 = Enable
FF
Reserved
Reserved
NOTES:
17. During Calibration xCCCC (MSB justified) is presented at the output data bus, toggling on the LSB (and higher) data bits occurs at completion of
calibration. This behavior can be used as an option to determine calibration state.
18. Use test_io = 0x80 and User Pattern 1 = 0x9999 for Checkerboard outputs on DDR Outputs.
19. Use test_io = 0x80 and User Pattern 1 = 0xAAAA for all ones/zeroes outputs on DDR Outputs
FN7574 Rev 2.00
December 10, 2012
Page 30 of 35
ISLA216P
Equivalent Circuits
AVDD
AVDD
TO
CLOCK-PHASE
GENERATION
CLKP
AVDD
AVDD
CSAMP
9pF
TO
11k
11k
INP
INN
CHARGE
PIPELINE
18k
E2
E3
E3
E1
300
AVDD
CSAMP
9pF
18k
AVDD
TO
CHARGE
PIPELINE
E2
CLKN
E1
FIGURE 42. ANALOG INPUTS
FIGURE 43. CLOCK INPUTS
AVDD
AVDD
(20k PULL-UP
ON RESETN
ONLY)
OVDD
AVDD
75k
OVDD
AVDD
TO
SENSE
LOGIC
75k
280
OVDD
20k
INPUT
INPUT
TO
LOGIC
280
75k
75k
FIGURE 44. TRI-LEVEL DIGITAL INPUTS
FIGURE 45. DIGITAL INPUTS
OVDD
2mA OR
3mA
OVDD
DATA
DATA
OVDD
OVDD
D[14:0]P
OVDD
DATA
D[14:0]
D[14:0]N
DATA
DATA
2mA OR
3mA
FIGURE 47. CMOS OUTPUTS
FIGURE 46. LVDS OUTPUTS
FN7574 Rev 2.00
December 10, 2012
Page 31 of 35
ISLA216P
Equivalent Circuits(Continued)
AVDD
VCM
+
0.94V
–
FIGURE 48. VCM_OUT OUTPUT
LVDS Outputs
A/D Evaluation Platform
Output traces and connections must be designed for 50 (100
differential) characteristic impedance. Keep traces direct and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
Intersil offers an A/D Evaluation platform which can be used to
evaluate any of Intersil’s high speed A/D products. The platform
consists of a FPGA based data capture motherboard and a family
of A/D daughtercards. This USB based platform allows a user to
quickly evaluate the A/D’s performance at a user’s specific
application frequency requirements. More information is
available at
LVCMOS Outputs
Output traces and connections must be designed for 50
http://www.intersil.com/converters/adc_eval_platform/
characteristic impedance.
Unused Inputs
Layout Considerations
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will
not be operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state, and therefore should be biased according to the desired
functionality.
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and should be connected to a large copper plane
using numerous vias for optimal thermal performance.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Bypass and Filtering
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces will
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
FN7574 Rev 2.00
December 10, 2012
Page 32 of 35
ISLA216P
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
I2E The Intersil Interleave Engine. This highly configurable
circuitry performs estimates of offset, gain, and sample time
skew mismatches between the core converters, and updates
analog adjustments for each to minimize interleave spurs.
Integral Non-Linearity (INL) is the maximum deviation of the
A/D’s transfer function from a best fit line determined by a least
squares curve fit of that transfer function, measured in units of
LSBs.
Least Significant Bit (LSB) is the bit that has the smallest value or
weight in a digital word. Its value in terms of input voltage is
N
V
/(2 -1) where N is the resolution in bits.
FS
Missing Codes are output codes that are skipped and will never
appear at the A/D output. These codes cannot be reached with
any input value.
Most Significant Bit (MSB) is the bit that has the largest value or
weight.
Pipeline Delay is the number of clock cycles between the
initiation of a conversion and the appearance at the output pins
of the data.
Power Supply Rejection Ratio (PSRR) is the ratio of the observed
magnitude of a spur in the A/D FFT, caused by an AC signal
superimposed on the power supply voltage.
Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one half the clock frequency, including
harmonics but excluding DC.
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
FN7574 Rev 2.00
December 10, 2012
Page 33 of 35
ISLA216P
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
FN7574.2
FN7574.1
CHANGE
November 28, 2012
April 15, 2011
Datasheet update for better accuracy and clarity.
-Updated Ordering Information by Changing Eval board name from ISLA216P25EVAL TO ISLA216IR72EV1Z
and updating description
-Electrical Specifications Table change:
DC Specifications ->Analog Input->Common-Mode Input Current (per pin) -> TYP "10.8" to "5.2"
Added CMOS Power Typical Specs under Total Power Dissipation ->Normal Mode
Digital Specifications Table ->Input Capacitance->TYP "3" to "4"
Digital Specifications Table ->LVDS INPUTS (CLKRSTP, CLKRSTN) TO LVDS INPUTS (CLKDIVRSTP,
CLKDIVRSTN)
-Updated temperature calibration curves
-Added clkdiv description in Clock Input Section
-Removed '2-wire mode' text in "Address 0x02:Burst_End" section
-Updated Bit6 at Address 0x74:Output_Mode_B section
January 13, 2011
FN7574.0
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISLA216P
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
© Copyright Intersil Americas LLC 2012. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7574 Rev 2.00
December 10, 2012
Page 34 of 35
ISLA216P
Package Outline Drawing
L72.10x10E
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 11/09
10.00
A
Z
X
6
EXPOSED
PAD AREA
9.75
B
PIN #1
72
72
INDEX AREA
1
1
6
PIN 1
INDEX AREA
9.75
10.00
0.100 M C A B
(4X)
0.15
4.150 REF.
7.150 REF.
TOP VIEW
9.75 ±0.10
0.100 M C A B
BOTTOM VIEW
11°
Y
ALL AROUND
C0.400X45° (4X)
10.00 ±0.10
SIDE VIEW
(0.350)
R0.200
(7.15)
(4.15 REF)
1
0.500 ±0.100
R0.115 TYP.
72
(4X 9.70)
(4X 8.50)
(3.00 )
DETAIL "X"
DETAIL "Z"
(6.00)
R0.200 MAX.
ALL AROUND
( 72X 0 .23)
0.100 C
( 72X 0 .70)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
SEATING
PLANE
0.080C
0.190~0.245
0.23 ±0.050
2. Dimensioning and tolerancing conform to ANSI Y14.5m-1994.
0.50
C
0.025 ±0.020
3.
Unless otherwise specified, tolerance : Decimal ± 0.10
Angular ±2.50°
0.100M C A B
0.050M C
4. Dimension applies to the metallized terminal and is measured
between 0.015mm and 0.30mm from the terminal tip.
DETAIL "Y"
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
Package outline compliant to JESD-M0220.
7.
FN7574 Rev 2.00
December 10, 2012
Page 35 of 35
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