M16C26_技术文档

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Pin Description

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Description

Pin name

Signal name

I/O type

Function

Power supply

input

VCC, VSS

Supply 2.7V to 5.5V to the VCC pin. Supply 0V to the VSS pin.

This pin is used to select, at reset, operation in either single-chip

user or serial boot programming mode. If connected to V^SS

operation after reset will employ single-chip user mode. If

connected to V^CC, reset will cause entry into boot mode.

,

CNVSS

CNV^SS

Input

RESET

Reset input

A "L" on this input resets the microcomputer.

The user must leave this pin unconnected.

IVCC

Power supply

These pins are provided for the main clock generating

X

IN

Clock input

Input

circuit. Connect a ceramic resonator or crystal between the X^IN

and the XOUT pins. To use an externally-derived clock, input it to

the X^INpin and leave the XOUT pin open.

XOUT

Clock output

Output

Analog power

supply input

This pin is a power supply input for the A-D converter. Connect

AVCC

this pin to V^CC

.

Analog power

supply input

This pin is a power supply input for the A-D converter. Connect

AV^SS

this pin to V^SS

.

Reference

voltage input

VREF

Input

This pin is a reference voltage input for the A-D converter.

This is a 3-bit I/O port. When used for input pin, the port can be

set to have or not have a pull-up resistor by software. P1

5

to P1

to INT

can be configured to act

7

P1

P6

P7

5

0

to P1

to P6

to P7

7

I/O port P1

I/O port P6

I/O port P7

Input/output

also function as the input pins for external interrupts INT

3

5

as selected by software. Additionally, P1

as the A/D trigger source (AD^TRG).

5

This is an 8-bit I/O port. When used for input pin, the port can be

set to have or not have a pull-up resistor in units of four bits by

software. Pins in this port also function as UART0 and UART1 I/O

pins as selected by software.

Input/output

This is an 8-bit I/O port. When used for input pin, the port can be

set to have or not have a pull-up resistor in units of four bits by

software (P7

0

to P7 are N channel open-drain outputs). Pins in

1

this port also function as timer A0-A3 I/O, UART2 I/O pins, or 3-

phase PWM V/W outputs as selected by software.

This is a 7-bit I/O port. When used for input pin, the port can be

set to have or not have a pull-up resistor in units of four bits by

software. Using software, they can be made to function as the I/O

pins for timer A4, the input pins for external interrupts INT0, INT1,

NMI, or 3-phase PWM U outputs and 3-phase PWM shutdown

P8

0

5

to P8

3

7

,

I/O port P8

Input/output

input. P8

I/O pins for a sub clock generation circuit. In this case, connect a

quartz oscillator between P8 (XCOUT pin) and P8 (XCIN pin).

6

to P8

7

can be set using software to function as the

6

7

This is a 4-bit I/O port. When used for input pin, the port can be

set to have or not have a pull-up resistor in units of four bits by

software. Pins in this port also function as Timer B0-B2 input pins

as selected by software.

P9

0

to P9

3

I/O port P9

Input/output

This is an 8-bit I/O port. When used for input pin, the port can be

set to have or not have a pull-up resistor in units of four bits by

software Pins in this port also function as A-D converter input pins

P10

0

to P10

7

I/O port P10

as selected by software. Furthermore, P10

4

-P10 also function as

7

input pins for the key input interrupt function pins as selected by

software.

Table 1.3. Pin Descriptions

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Preliminary Specifications Rev. 0.9

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Memory

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Functional Block Operation

The M16C/26 group accommodates certain units in a single chip. These units include ROM and

RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/

logic operations. Also included are peripheral units such as timers, serial I/O, A-D converter, and

I/O ports.

Memory

Figure 1.4.1 is a memory map of the M16C/26 group. The linear address space of 1M bytes extends

from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30262F4, there

is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the

reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is

stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the

internal register (INTB). See the section on interrupts for details.

From 0040016 up is RAM. For example, in the M30262F4, 1K bytes of internal RAM is mapped to the

space from 0040016 to 07FF16. In addition to storing data, the RAM also stores the stack used when

calling subroutines and when interrupts are generated.

These devices also contain two blocks of Flash ROM as Virtual EEPROM memory to store data. These

2 blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions.

The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for

peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR

area that is not occupied is reserved and cannot be used for other purposes.

00000₁₆

Type No.

A ddress XX XX X ₁₆

007FF₁₆

Address Y Y Y Y Y ₁₆

FA 000₁₆

M 30262F3G P

M 30262F4G P

M 30262F6G P

M 30262F8G P

SFR area

007FF₁₆

F8000₁₆

00BFF₁₆

F4000₁₆

00BFF₁₆

F0000₁₆

00400₁₆

Internal RAM area

RESERVED

FFE00₁₆

XXXXX₁₆

Special Page

Vector Table

0F000₁₆

0F800₁₆

10000₁₆

Virtual EEPROM

FFFDC₁₆

Undefined Instruction

Overflow

Break Instruction

Address Match

Single Step

Watchdog Timer

DBC

RESERVED

Flash ROM

Hardware

Vectors

YYYYY₁₆

NMI

Reset

FFFFF₁₆

Figure 1.4.1. Memory map

8

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Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

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M16C/26 Group

CPU

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.4.2. Seven of these registers (R0, R1, R2, R3, A0,

A1, and FB) come in two sets; therefore, these have two register banks.

b15

b8

7

b0

R0^(Note)

R1^(Note)

R2^(Note)

R3^(Note)

A0^(Note)

A1^(Note)

FB^(Note)

L

H

b19

b0

PC

Program counter

Data

registers

b0

Interrupt table

register

INTB

H

L

b15

User stack pointer

USP

ISP

SB

b0

Interrupt stack

pointer

Address

registers

Static base

register

FLG

Frame base

registers

Flag register

Note: These registers consist of two register banks.

Figure 1.4.2. Central processing unit register

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and

arithmetic/logic operations.

Registers R0 and R1 can each be used as dual 8-bit data registers. As such, their high-order bytes are

designated R0H/R1H, while their low-order bytes become R0L/R1L, respectively. In some instructions,

registers R2 and R0, as well as R3 and R1, can be combined to serve as 32-bit data registers (R2R0/R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) consist of 16 bits each. Individually, they can be used for three types of

register-based addressing: register direct, address register indirect, and address register relative. They

are also used for transfer and arithmetic/logic operations, as well as three special instruction addressing

modes: address register relative with 20-bit displacement, 32-bit address register indirect, and 32-bit

register direct. These last two modes combine A0 and A1 for use as a single 32-bit register (A1A0).

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Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

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M16C/26 Group

CPU

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(3) Frame base register (FB)

Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.

(4) Program counter (PC)

Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.

(5) Interrupt table register (INTB)

Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector

table.

(6) Stack pointer (USP/ISP)

Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-

ured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).

This flag is located at the position of bit 7 in the flag register (FLG).

(7) Static base register (SB)

Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.

(8) Flag register (FLG)

Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.3 shows the flag

register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

• Bit 1: Debug flag (D flag)

This flag enables a single-step interrupt.

When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is

cleared to “0” when the interrupt is acknowledged.

• Bit 2: Zero flag (Z flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.

• Bit 3: Sign flag (S flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”

.

• Bit 4: Register bank select flag (B flag)

This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is

selected when this flag is “1”.

• Bit 5: Overflow flag (O flag)

This flag is set to “1” when an arithmetic operation resulted in overflow.

• Bit 6: Interrupt enable flag (I flag)

This flag enables a maskable interrupt.

An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared

to “0” when the interrupt is acknowledged.

• Bit 7: Stack pointer select flag (U flag)

Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected

when this flag is “1”.

This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software

interrupt Nos. 0 to 31 is executed.

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Preliminary Specifications Rev. 0.9

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M16C/26 Group

CPU

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

• Bits 8 to 11: Reserved area

• Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight

processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt

is enabled.

• Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the software manual for

details.

b15

b0

Flag register (FLG)

Carry flag

Debug flag

Zero flag

Sign flag

Register bank select flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Figure 1.4.3. Flag register (FLG)

11

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M16C/26 Group

Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

There are two types of reset: a hardware reset and a software reset (See “Software Reset” for details on

software resets.)

Hardware reset

There are two kinds of hardware reset: hardware reset 1 and hardware reset 2.

Hardware reset 1

A reset is applied using the RESET pin. When a low-level signal (“L”) is applied to the RESET pin,

while the power supply voltage is within the recommended operating voltage, the pins are initialized

(see Table 1.5.1). When the input level of the RESET pin is released from low to high, the CPU and

SFR are initialized. The program is executed starting from the address indicated by the reset vector.

The internal RAM is not initialized. If the RESET pin is pulled low while writing to the internal RAM, the

internal RAM becomes indeterminate.

Figure 1.5.1 shows an example of the reset circuit. Table 1.5.1 shows the status of the other pins while

the RESET pin is “L”. Figure 1.5.2 shows the reset sequence. Figure 1.5.3 shows the status of the

CPU registers. Refer to the SFR section on the status of SFR registers after reset.

1. When the power supply is stable (warm start)

(1) Apply a low-level signal to the RESET pin

(2) Supply at least 20 clock cycles to the XIN pin

(3) Apply a high-level signal to the RESET pin

2. Power on (cold start)

(1) Apply a low-level signal to the RESET pin

(2) Turn on or increase the power supply voltage until it meets the recommended operation

voltage.

(3) Wait at least 2ms for the power supply to stabilize

(4) Supply at least 20 clock cycles to the XIN pin

(5) Apply a high-level signal to the RESET pin

Hardware reset 2

This reset is generated by the microcomputer's internal voltage detection circuit. The voltage detec-

tion circuit monitors the voltage supplied to the VCC pin. A reset is generated when the VCC input

voltage drops to VDET3 or less while VCR2 register's VC26 bit is equal to “1” (VDET3 detection circuit

enabled). When the input voltage increases so it is greater than VDET3, the CPU, SFR, and pins are

initialized, and the program is executed starting from the address indicated by the reset vector. After

VDET3 is detected, it takes about 2ms before the program is executed. The status of the pins and

registers after the reset is similar to that of hardware reset 1.

Take note, however, that the value of VC26 has no effect in stop mode. Therefore, a reset is not

applied even if the VCC input voltage drops to VDET3 or lower.

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M16C/26 Group

Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software reset

When the PM0 register's PM03 bit is set “1” (microcomputer reset), the CPU, SFR, and pins of the

microcomputer are initialized similar to a hardware reset. After reset, the program is executed starting

from the address indicated by the reset vector.

Figure 1.5.2 shows the reset sequence and Figure 1.5.3 shows the status of the CPU registers after

reset.

Recommended

operating

voltage

V

CC

0V

VCC

RESET

0V

Equal to or less

than 0.2VCC

Equal to or less

than 0.2VCC

More than 20 cycles of XIN +2 ms are

needed.

Figure 1.5.1. Example reset circuit

VCC

XIN

More than More than

2ms are

needed

20 cycles

are needed

Single chip

mode

RESET

BCLK

BCLK 28cycles

FFFFC16

Content of reset vector

Address

FFFFE16

Figure 1.5.2. Reset sequence

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M16C/26 Group

Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.5.1. Pin status at RESET for User / Boot operating modes

Status

Pin name

Boot Mode (CNVSS = VCC

)

User Mode (CNVSS = VSS

Input port (high impedance)

)

Data input (high impedance)

P1

P6

5

0

4

5

to P1

7

3

to P6

Data input (high impedance)

BUSY output

SCLK input

RXD input

P6

6

7

TXD output

P6

Input port (high impedance)

Data input (high impedance)

P7

P80 to P83, P85

P8

6

7

CE input

Data input (high impedance)

P8

Data input (high impedance)

P90 to P93, P10

b15

b0

000016

Data register(R0)

Data register(R1)

Data register(R2)

000016

Data register(R3)

Address register(A0)

Address register(A1)

Frame base register(FB)

b19

b0

0000016

Interrupt table register(INTB)

Content of addresses FFFFE16 to FFFFC16

Program counter(PC)

b15

b0

User stack pointer(USP)

000016

Interrupt stack pointer(ISP)

Static base register(SB)

b15

b0

Flag register(FLG)

000016

b15

b8 b7

IPL

U

I

O B S

Z D C

Figure 1.5.3. CPU register status after reset

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Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Voltage detection circuit

The voltage detection circuit has monitoring circuits to check the input voltage of the VCC pin. These

circuits monitor the the input voltage at VDET3 and VDET4. Bits VC26 and VC27 of VCR2 register are

used to enable/disable these monitoring circuits.

The VDET3 monitoring circuit is used for detecting the minimum VCC that guarantees proper chip

operation.

The VDET4 monitoring circuit can be set to detect whether the input voltage is equal to and greater or

less than VDET4 depending on the value of VC13 bit of the VCR1 register. In addition, the VDET4

monitoring circuit, if enabled, can generate an interrupt.

WDC5 bit

Write to WDC register

Internal power on reset

WARM/COLD

(warm or cold start)

Q

S

R

VCR2 register

b7 b6

Internal power

supply voltage

stable time

RESET

1 shot

CK

td(S-R)

Q

+

Internal reset

("L" active)

>

VDET3

E

CM10 bit = 1

(stop mode)

+

VCC

≥

VDET4

E

Noise rejection

VDET4 detect signal

VCR1 register

b3

VC13 bit

Figure 1.5.4. Reset circuit block

Watchdog timer control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

WDC

Address

000F16 00?XXXXX

After reset

(Note1)

0

2

Bit symbol

Bit name

Function

RW

High-order bit of watchdog timer

RO

RW

Cold start / warm start

WDC5

0 : Cold start

discrimination flag (Note 2) 1 : Warm start

Reserved bit

Set to 0

WDC7

Prescaler select bit

0 : Divided by 16

1 : Divided by 128

RW

Note 1: The WDC5 bit is set to 0 immediately after power-on (cold start).

Note 2: The WDC5 bit will always be set to a 1 whenever the WDC SFR is written (regardless of value of WDC5 bit).

Figure 1.5.5. WDC register

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Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Power supply detection register 1

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

VCR1

Address

001916

After reset

000010002

0 0 0 0

0 0 0

Bit name

Reserved bit

F unction

RW

Bit symbol

VC13

RW

RO

Set to “0”

V

DET4 power supply

0: VCC < VDET4

monitor flag (Note)

1: VCC ≥ VDET4

RW

Reserved bit

Set to “0”

Note: The VC13 bit is useful when the VCR2 register's VC27 bit = 1 (VDET4 detection circuit enabled).

The VC13 bit is always 1 (VCC ≥ VDET4) when the VCR2 register's VC27 bit = 0 (VDET4 detection circuit disabled).

Power supply detection register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

VCR2

Address

001A16

After reset

0016

0 0 0 0 0 0

Bit name

Reserved bit

Bit symbol

Function

RW

Set to “0”

VC26

VC27

Power supply V^DET3monitor

bit

0: Disables detection circuit

1: Enables detection circuit

RW

0: Disables detection circuit

1: Enables detection circuit

Power supply V^DET4monitor

bit (Note 2)

Note 1: Write to this register after the PRCR register’s PRC3 bit is set to “1” (write enabled).

Note 2: To use the VCR1 register’s VC13 bit or D4INT register’s D42 bit, set the VC27 bit to “1” (VDET4 detection circuit enabled).

Power supply VDET4 detection register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

D4INT

Address

001F16

After reset

0016

Bit symbol

D40

Bit name

Function

RW

V

DET4 detection interrupt

enable bit.

0 : Disable

1 : Enable

0: Disable (do not use the VDET4

detection interrupt to get out

of stop mode)

1: Enable (use the V^DET4

detection interrupt to get out

of stop mode)

STOP mode deactivation

control bit

(Note 4)

D41

RW

V

DET4 up/down detection flag

D42

D43

DF0

DF1

0: Not detected

1: V^DET4up/down detected

(Note

(Note 2)

3)

RW

WDT overflow detected

flag

0: Not detected

1: Detected

(Note

3)

b5b4

Sampling clock select

bit

RW

00 : BCLK divided by 8

01 : BCLK divided by 16

10 : BCLK divided by 32

11 : BCLK divided by 64

RW

Nothing is assigned. In an attempt to write to these bits, write

“0”. The value, if read, turns out to be “0”.

(b7-b6)

Note 1: Write to this register after the PRCR register’s PRC3 bit is set to “1” (write enabled).

Note 2: Useful when the VCR2 register's VC27 bit = 1 (V^DET4detection circuit enabled). If the VC27 bit is cleared

to 0 (V^DET4detection circuit disabled), the D42 bit is set to 0 (Not detected).

Note 3: This bit is cleared to “0” by writing a “0” in a program. (Writing a “1” has no effect.)

Note 4: If the V^DET4detection interrupt needs to be used to get out of stop mode again after once used for that

purpose, reset the D41 bit by writing a 0 and then a 1.

Figure 1.5.6. VCR1, VCR2, and D4INT registers

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Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Typical operation of hardware reset 2 (Note)

5.0V

V

DET4

DET3r

DET3

V

VCC

V

DET3s

SS

V

RESET

Internal reset signal

VC13 bit

VC26 bit

VC27 bit

undefined

Set to “1” in a program (reset level detection circuit enable)

Set to “1” in a program

(power supply down detection circuit enable)

undefined

Note: Please refer to "Electrical Characteristics" section, Table 1.18.6, for values of VDET4, VDET3

,

V

DET3s, and VDET3r

.

Figure 1.5.7. Typical operation of hardware reset 2

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Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Voltage detection circuit

A VDET4 detection interrupt request is generated when the input voltage of the VCC pin rises over

VDET4 or drops under VDET4 while the D40 bit of the D4INT register is equal to “1” (VDET4 detection

interrupt enabled). The VDET4 detection interrupt shares the interrupt vector with the watchdog

timer and oscillation stop detection interrupts.

To use the VDET4 detection interrupt as a way to get out of stop mode, set D41 bit of the D4INT

register to “1” (enabled) prior to going into stop mode.

D42 bit of the the D4INT register is set to “1” when an input voltage over or under VDET4 is de-

tected. A VDET4 detection interrupt is generated when the D42 bit changes state from “0” to “1”.

The D42 bit needs to be cleared to “0" in the program. However, while in stop mode, if the input

voltage goes over VDET4 when the D41 bit is equal to “1”, a VDET4 detection interrupt is generated

regardless of the value of D42, which causes the microcomputer to get out of stop mode.

Table 1.5.2 shows the conditions under which a VDET4 detection interrupt request is generated.

The sampling clock, used for detecting when the input voltage goes over or under VDET4, is set

using the DF1 and DF0 bits of the D4INT register. Table 1.5.3 shows the sampling clock periods.

Table 1.5.2. VDET4 detection interrupt request generation conditions

operation mode VC27 bit

D40 bit

D41 bit

D42 bit

CM02 bit

VC13 bit

0 to 1 (Note 3)

1 to 0 (Note 3)

0 to 1 (Note 3)

1 to 0 (Note 3)

0 to 1

Normal

operation

mode (Note 1)

0 to 1

(Note 2)

Wait mode

(Note 4)

1

0 to 1

0

Stop mode

(Note 4)

1

0

1

0 to 1

Note 1: The status is handled as normal mode when not in wait or stop modes. (Refer to "Clock

Generating Circuit".)

Note 2: " " implies either "0" or "1".

Note 3: An interrupt request for voltage reduction is generated a sampling time after the value of

the VC13 bit has changed. Refer to Figure 1.5.9 "VDET4 detection interrupt generation circuit

operation example" for details.

Note 4: Refer to "Limitations on stop mode", "Limitations on wait instructions with peripheral clocks

turned off".

Table 1.5.3. Sampling clock periods

Sampling time (µs)

BCLK

DF1 to DF0=00

DF1 to DF0=01

DF1 to DF0=10

DF1 to DF0=11

(MHz)

(BCLK divided by 8) (BCLK divided by 16) (BCLK divided by 32) (BCLK divided by 64)

16

3.0 6.0 12.0 24.0

Precautions

1. Limitations on stop mode

With the VC13 bit of the VCR1 register equal to “1” (VCC ³ VDET4), VC27 bit of the VCR2 register

equal to “1” (VDET4 detection circuit enabled), and D40 bit of the D4INT register equal to “1” (VDET4

detection interrupt enabled), if the CM10 bit of the CM1 register is set to “1” (stop mode), a VDET4

detection interrupt is immediately generated, causing the microcomputer to get out of stop mode.

In systems where the microcomputer enters the stop mode when the input voltage in the VCC pin

drops under VDET4 and exits from stop mode when the input voltage goes over VDET4, ensure that

the CM10 bit is set to “1” when VC13 = “0” (VCC < VDET4)

18

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

2. Limitations on wait instructions with peripheral clocks turned off

If the WAIT instruction is executed when bit VC13 of the VCR1 register is equal to “1” (VCC ³

VDET4), bit VC27 of the VCR2 register is equal to “1” (VDET4 detection circuit enabled), and bit D40

of the D4INT register is equal to “1” (VDET4 detection interrupt enabled), a VDET4 detection interrupt

is immediately generated, causing the microcomputer to exit from wait mode.

In systems where the microcomputer enters wait mode when the input voltage in the VCC pin drops

under VDET4 and exits from wait mode when the input voltage goes over VDET4, ensure that the

WAIT instruction is executed when VC13 = “0” (VCC < VDET4).

VDET4 detect interrupt generation circuit

VDET4 detect circuit

DF1, DF0

00

01

10

11

2

D42 bit is cleared to 0 (not

detected) by writing a in a

program. VC27 bit is cleared to

(VDET4 detection circuit

disabled), the D42 bit is set to

0 .

0

VC27

0

BCLK

VC13

1/8

1/2

D42

watchdog

timer interrupt

signal

V

CC

+

-

Noise

rejection

Noise rejection

circuit

Digital

filter

VREF

VDET4 detect

(Rejection wide:200 ns)

signal

V

DET4 detect

H

when VC27

interrupt signal

Non-maskable

interrupt signal

D41

bit= 0 (disabled)

Oscillation stop

detection

interrupt signal

CM02

WAIT instruction(wait mode)

Watchdog timer block

D43

D40

Watchdog timer

overflow signal

This bit is cleared to 0 (not detected) by writing a

0 in a program.

Figure 1.5.8. VDET4 detection interrupt generation block

V

CC

VC13 bit

sampling

No VDET4 detection interrupt signals are generated

when the D42 bit is H .

Output of the digital filter (Note 2)

D42 bit

Set to

0

in a

Set to 0 in a

program (not

detected)

program (not

detected)

VDET4 detect interrupt signal

(Note 1)

Note 1 : D40 is 1 (VDET4 detect interrupt enabled)

Note 2 : Output of the digital filter shown in Figure 1.5.8.

Figure 1.5.9. VDET4 detection interrupt generation circuit operation example

19

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Special Function Registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Special Function Registers

Figures 1.6.1 through 1.6.5 display special function register (SFR) names, addresses, acronyms, and

reset values.

Address

0000₁₆

0001₁₆

0002₁₆

0003₁₆

Register Name

Acronym Value after Reset

0004₁₆Processor mode register 0

0005₁₆Processor mode register 1

0006₁₆System clock control register 0

0007₁₆System clock control register 1

0008₁₆

PM0

0 0 0 0 0 0 0 0

0 0 0 0 1 0 0 0

0 1 0 0 1 0 0 0

0 0 1 0 0 0 0 0

PM1

CM0

CM1

0009₁₆Address match interrupt enable register

000A₁₆Protect register

AIER

PRCR

0 0

0 0 0 0 0

000B₁₆

000C₁₆Oscillation stop detection register

000D₁₆

CM2

0 0 0 0 0 0 0 0

000E₁₆Watchdog timer start register

000F₁₆Watchdog timer control register

0010₁₆Address match interrupt register 0 (low)

0011₁₆Address match interrupt register 0 (mid)

0012₁₆Address match interrupt register 0 (high)

0013₁₆

0014₁₆Address match interrupt register 1 (low)

0015₁₆Address match interrupt register 1 (mid)

0016₁₆Address match interrupt register 1 (high)

0017₁₆

WDTS

WDC

RMAD0

?

0 0 ? ? ? ? ? ?

00₁₆

0 0 0 0

RMAD1

00₁₆

0 0 0 0

0018₁₆

0019₁₆Power supply detection register 1

001A₁₆Power supply detection register 2

001B₁₆

VCR1

VCR2

0 0 0 0 1 0 0 0

0 0 0 0 0 0 0 0

001C₁₆

001D₁₆

001E₁₆Processor mode register 2

001F₁₆Power supply 4 V detection register

0020₁₆DMA0 source pointer (low)

0021₁₆DMA0 source pointer (mid)

0022₁₆DMA0 source pointer (high)

0023₁₆

PM2

D4INT

SAR0

0 0 0 0 0

0 0 0 0 0 0 0 0

?

? ? ? ?

0024₁₆DMA0 destination pointer (low)

0025₁₆DMA0 destination pointer (mid)

0026₁₆DMA0 destination pointer (high)

0027₁₆

0028₁₆DMA0 transfer counter (low)

0029₁₆DMA0 transfer counter (high)

002A₁₆

DAR0

?

? ? ? ?

TCR0

?

002B₁₆

002C₁₆DMA0 control register

002D₁₆

002E₁₆

DM0CON

SAR1

? 0 0

0 0 0 0 0

002F₁₆

0030₁₆DMA1 source pointer (low)

0031₁₆DMA1 source pointer (mid)

0032₁₆DMA1 source pointer (high)

0033₁₆

?

? ? ? ?

0034₁₆DMA1 destination pointer (low)

0035₁₆DMA1 destination pointer (mid)

0036₁₆DMA1 destination pointer (high)

0037₁₆

0038₁₆DMA1 transfer counter (low)

0039₁₆DMA1 transfer counter (high)

003A₁₆

DAR1

?

? ? ? ?

TCR1

?

003B₁₆

003C₁₆DMA1 control register

003D₁₆

DM1CON

? 0 0

0 0 0 0 0

003E₁₆

003F₁₆

Reserved address, do not write

Value indeterminate at reset

reset value is zero

?

0

1

0

1

reset value is one

reserved bit, must write to zero

reserved bit, must write to one

Nothing is mapped to this bit

(value is indeterminate when read)

Figure 1.6.1. Location of peripheral unit control registers (1)

20

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Special Function Registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address

0040₁₆

0041₁₆

0042₁₆

0043₁₆

Register Name

Acronym Value after Reset

0044₁₆INT3 interrupt control register

INT3IC

0 0 ? 0 0 0

0045₁₆

0046₁₆

0047₁₆

0048₁₆INT5 interrupt control register

0049₁₆INT4 interrupt control register

004A₁₆Bus collision detection interrupt control register BCNIC

INT5IC

INT4IC

0 0 ? 0 0 0

? 0 0 0

0 0 ? 0 0 0

004B₁₆DMA0 interrupt control register

004C₁₆DMA1 interrupt control register

004D₁₆Key input interrupt control register

004E₁₆A-D conversion interrupt control register

004F₁₆UART2 transmit interrupt control register

0050₁₆UART2 receive interrupt control register

0051₁₆UART0 transmit interrupt control register

0052₁₆UART0 receive interrupt control register

0053₁₆UART1 transmit interrupt control register

0054₁₆UART1 receive interrupt control register

0055₁₆Timer A0 interrupt control register

0056₁₆Timer A1 interrupt control register

0057₁₆Timer A2 interrupt control register

0058₁₆Timer A3 interrupt control register

0059₁₆Timer A4 interrupt control register

005A₁₆Timer B0 interrupt control register

005B₁₆Timer B1 interrupt control register

005C₁₆Timer B2 interrupt control register

005D₁₆INT0 interrupt control register

DM0IC

DM1IC

KUPIC

ADIC

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

TA3IC

TA4IC

TB0IC

TB1IC

TB2IC

INT0IC

INT1IC

005E₁₆INT1 interrupt control register

005F₁₆

to

01B3₁₆Flash Control Register 4

01B4₁₆

01B5₁₆Flash Control Register 1

01B6₁₆

FMR4

FMR1

FMR0

0 1 0 0 0 0 0 0

0

0 0

0

1 1

01B7₁₆Flash Control Register 0

0 0 0 0 0 1

0 0

01B8₁₆

01B9₁₆

01BA₁₆

01BB₁₆

01BC₁₆

01BD₁₆

01BE₁₆

01BF₁₆

01C0₁₆

01C1₁₆

01C2₁₆

to

025C₁₆

025D₁₆

025E₁₆Peripheral Clock Select Register

PLCKR

0 0 0 0 0 0 1 1

025F₁₆

0260₁₆

to

033E₁₆

033F₁₆

Reserved address, do not write

Value indeterminate at reset

reset value is zero

?

0

1

0

1

reset value is one

reserved bit, must write to zero

reserved bit, must write to one

Nothing is mapped to this bit

(value is indeterminate when read)

Figure 1.6.2. Location of peripheral unit control registers (2)

21

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Special Function Registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address

0340₁₆

0341₁₆

Register Name

Acronym Value after Reset

0342₁₆Timer A1-1 register (low)

TA11

?

0343₁₆Timer A1-1 register (high)

0344₁₆Timer A2-1 register (low)

0345₁₆Timer A2-1 register (high)

0346₁₆Timer A4-1 register (low)

?

TA21

TA41

0347₁₆Timer A4-1 register (high)

0348₁₆Three-phase PWM control register 0

0349₁₆Three-phase PWM control register 1

034A₁₆Three-phase output buffer register 0

034B₁₆Three-phase output buffer register 1

034C₁₆Dead time timer

?

INVC0

INVC1

IDB0

IDB1

DTT

0 0 0 0 0 0 0 0

0 0 0 0 0 0

?

0 0

Timer B2 interrupt occurrences frequency set counter

034D₁₆

034E₁₆

034F₁₆

0350₁₆

0351₁₆

0352₁₆

0353₁₆

0354₁₆

0355₁₆

0356₁₆

0357₁₆

0358₁₆

0359₁₆

035A₁₆

035B₁₆

035C₁₆

035D₁₆

035E₁₆

ICTB2

? ? ? ?

035F₁₆Interrupt request cause select register

0360₁₆

IFSR

0 0 0 0 0

0 0 0

0361₁₆

0362₁₆

0363₁₆

0364₁₆

0365₁₆

0366₁₆

0367₁₆

0368₁₆

0369₁₆

036A₁₆

036B₁₆

036C₁₆

036D₁₆

036E₁₆

036F₁₆

0370₁₆

0371₁₆

0372₁₆

0373₁₆

0374₁₆UART2 special mode register 4

0375₁₆UART2 special mode register 3

0376₁₆UART2 special mode register 2

0377₁₆UART2 special mode register

0378₁₆UART2 transmit/receive mode register

0379₁₆UART2 bit rate generator

037A₁₆UART2 transmit buffer register (low)

037B₁₆UART2 transmit buffer register (high)

037C₁₆UART2 transmit/receive control register 0

037D₁₆UART2 transmit/receive control register 1

037E₁₆UART2 receive buffer register (low)

037F₁₆UART2 receive buffer register (high)

U2SMR4

U2SMR3

U2SMR2

U2SMR

U2MR

U2BRG

U2TB

0 0 0 0 0 0 0 0

0 0 0

0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

0

?

0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0

?

U2C0

U2C1

U2RB

? ? ? ? ?

?

Reserved address, do not write

Value indeterminate at reset

reset value is zero

?

0

1

0

1

reset value is one

reserved bit, must write to zero

reserved bit, must write to one

Nothing is mapped to this bit

(value is indeterminate when read)

Figure 1.6.3. Location of peripheral unit control registers (3)

22

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Special Function Registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address

Register Name

Acronym Value after Reset

0380₁₆Count start flag

0381₁₆Clock prescaler reset flag

0382₁₆One-shot start flag

0383₁₆Trigger select register

0384₁₆Up/down flag

TABSR

CPSRF

ONSF

TRGSR

UDF

0 0 0 0 0 0 0 0

0

0 0

0 0 0 0 0

0

0 0 0 0 0 0 0 0

0385₁₆

0386₁₆Timer A0 register (low)

0387₁₆Timer A0 register (high)

0388₁₆Timer A1 register (low)

0389₁₆Timer A1 register (high)

038A₁₆Timer A2 register (low)

038B₁₆Timer A2 register (high)

038C₁₆Timer A3 register (low)

038D₁₆Timer A3 register (high)

038E₁₆Timer A4 register (low)

038F₁₆Timer A4 register (high)

0390₁₆Timer B0 register (low)

0391₁₆Timer B0 register (high)

0392₁₆Timer B1 register (low)

0393₁₆Timer B1 register (high)

0394₁₆Timer B2 register (low)

0395₁₆Timer B2 register (high)

0396₁₆Timer A0 mode register

0397₁₆Timer A1 mode register

0398₁₆Timer A2 mode register

0399₁₆Timer A3 mode register

039A₁₆Timer A4 mode register

039B₁₆Timer B0 mode register

039C₁₆Timer B1 mode register

039D₁₆Timer B2 mode register

039E₁₆Timer B2 special mode register

039F₁₆

TA0

TA1

TA2

TA3

TA4

TB0

TB1

TB2

?

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

0 0 0 0 0 0 0 0

0 0 ? ? 0 0 0 0

0 0 ?

0 0 0 0

0 0

03A0₁₆UART0 transmit/receive mode register

03A1₁₆UART0 bit rate generator

03A2₁₆UART0 transmit buffer register (low)

03A3₁₆UART0 transmit buffer register (high)

03A4₁₆UART0 transmit/receive control register 0

03A5₁₆UART0 transmit/receive control register 1

03A6₁₆UART0 receive buffer register (low)

03A7₁₆UART0 receive buffer register (high)

03A8₁₆UART1 transmit/receive mode register

03A9₁₆UART1 bit rate generaT1r

03AA₁₆UART1 transmit buffer register (low)

03AB₁₆UART1 transmit buffer register (high)

03AC₁₆UART1 transmit/receive control register 0

03AD₁₆UART1 transmit/receive control register 1

03AE₁₆UART1 receive buffer register (low)

03AF₁₆UART1 receive buffer register (high)

03B0₁₆UART transmit/receive control register 2

03B1₁₆

U0MR

U0BRG

U0TB

0 0 0 0 0 0 0 0

?

0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0

?

U0C0

U0C1

U0RB

? ? ? ? ?

?

U1MR

U1BRG

U1TB

0

0 0 0 0 0 0 0

?

U1C0

U1C1

U1RB

0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0

?

? ? ? ? ?

?

UCON

0 0 0 0 0 0 0

03B2₁₆

03B3₁₆

03B4₁₆

03B5₁₆

03B6₁₆

03B7₁₆

03B8₁₆DMA0 request cause select register

03B9₁₆

03BA₁₆DMA1 request cause select register

03BB₁₆

DM0SL

DM1SL

0 0

0 0 0 0

03BC₁₆

03BD₁₆

03BE₁₆

03BF₁₆

Reserved address, do not write

Value indeterminate at reset

reset value is zero

?

0

1

0

1

reset value is one

reserved bit, must write to zero

reserved bit, must write to one

Nothing is mapped to this bit

(value is indeterminate when read)

Figure 1.6.4. Location of peripheral unit control registers (4)

23

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Special Function Registers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Address

Register Name

Acronym Value after Reset

03C0₁₆A-D register 0 (low)

AD0

?

03C1₁₆A-D register 0 (high)

03C2₁₆A-D register 1 (low)

03C3₁₆A-D register 1 (high)

03C4₁₆A-D register 2 (low)

03C5₁₆A-D register 2 (high)

03C6₁₆A-D register 3 (low)

03C7₁₆A-D register 3 (high)

03C8₁₆A-D register 4 (low)

03C9₁₆A-D register 4 (high)

03CA₁₆A-D register 5 (low)

03CB₁₆A-D register 5 (high)

03CC₁₆A-D register 6 (low)

03CD₁₆A-D register 6 (high)

03CE₁₆A-D register 7 (low)

03CF₁₆A-D register 7 (high)

03D0₁₆

? ?

AD1

AD2

AD3

AD4

AD5

AD6

AD7

03D1₁₆

03D2₁₆

03D3₁₆

03D4₁₆A-D control register 2

03D5₁₆

ADCON2

0

0 0 0

0

0 0 0

03D6₁₆A-D control register 0

03D7₁₆A-D control register 1

03D8₁₆

ADCON0

ADCON1

0 0 0 0 0 ? ? ?

0 0 0 0 0 0 0 0

03D9₁₆

03DA₁₆

03DB₁₆

03DC₁₆

03DD₁₆

03DE₁₆

03DF₁₆

03E0₁₆

03E1₁₆Port P1 register

03E2₁₆

03E3₁₆Port P1 direction register

03E4₁₆

P1

? ? ?

0 0 0

0 0 0 0 0

PD1

03E5₁₆

03E6₁₆

03E7₁₆

03E8₁₆

03E9₁₆

03EA₁₆

03EB₁₆

03EC₁₆Port P6 register

03ED₁₆Port P7 register

03EE₁₆Port P6 direction register

03EF₁₆Port P7 direction register

03F0₁₆Port P8 register

03F1₁₆Port P9 register

03F2₁₆Port P8 direction register

03F3₁₆Port P9 direction register

03F4₁₆Port P10 register

03F5₁₆

P6

P7

PD6

PD7

P8

? ? ? ? ? ? ? ?

0 0 0 0 0 0 0 0

? ? ?

0 0 0 0

0 0 0

? ? ? ?

0 0 0 0

0

P9

PD8

PD9

P10

0

0 0 0 0

? ? ? ? ? ? ? ?

03F6₁₆Port P10 direction register

03F7₁₆

PD10

0 0 0 0 0 0 0 0

03F8₁₆

03F9₁₆

03FA₁₆

03FB₁₆

03FC₁₆Pull-up control register 0

03FD₁₆Pull-up control register 1

03FE₁₆Pull-up control register 2

03FF₁₆Port control register

PUR0

PUR1

PUR2

PCR

0

0 0 0 0

0 0 0

0 0 0 0

0 0 0

0

0 0

0

0 0 0 0 0 0 0

Reserved address, do not write

Value indeterminate at reset

reset value is zero

?

0

1

0

1

reset value is one

reserved bit, must write to zero

reserved bit, must write to one

Nothing is mapped to this bit

(value is indeterminate when read)

Figure 1.6.5. Location of peripheral unit control registers (5)

24

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Processor Mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Processor Mode

This device functions in single-chip mode only. In single-chip mode, only internal memory space (SFR,

internal RAM, and internal ROM) can be accessed. Ports P1_5 to P1_7, P6, P7, P8, P9_0 to P9_3 and P10

can be used as programmable I/O ports or as I/O ports for the internal peripheral functions. Figure 1.7.1

shows the processor mode registers 0 and 1. Figure 1.7.2 shows the processor mode register 2.

Processor mode register 0 (Note)

Symbol

PM0

Address

000416

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

0

R W

Bit symbol

Reserved Bit

PM03

Bit name

Function

Must always be set to "0".

Software reset bit

The device is reset when this bit is set

hen

of this bit is 0 w

to 1. The value

read.

Reserved Bit

Must always be set to "0".

Note: Set bit 1 of the protect register (address 000A16) to 1 when writing new

values to this register.

Processor mode register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PM1

Address

000516

When reset

00001000

2

0

1

0

R

W

Bit symbol

PM10

Bit name

Function

0: Disabled

Flash data block

access bit (Note 4)

1: Enabled (Note 3)

Must always be set to "0".

Reserved bit

PM12

0 : Interrupt

1 : Reset (Note 2)

Watchdog timer function

select bit

Must always be set to "1".

Must always be set to "0".

Reserved bit

Must always be set to 0 . The

value, if read, turns out to be

indeterminate.

Reserved bit

PM17

.

0 : No wait state

1 : Wait state inserted

Wait bit

Note 1: Set bit 1 of the protect register (address 000A16) to 1 when writing new values to this register.

Note 2: This bit can only be set to 1.

Note 3: When EW entry bit (FMR01) =1, this bit is automatically set to 1 during that time.

Note 4: To access the two 2K byte data blocks in address range F80016 to FFFF16, this bit must be set to 1.

Figure 1.7.1. Processor mode register 0 and 1

25

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Processor Mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Processor mode register 2 (Note 1)

Symbol

PM2

Address

001E16

When reset

XXX00000

b7 b6 b5 b4 b3 b2 b1 b0

2

0

0 0

0

R W

Bit symbol

PM20

Bit name

Function

Specifying wait when

accessing SFR registers

(Note 2)

0 : 2 waits

1 : 1 wait

0 : Clock is protected by PRCR

register

1 : Clock modification disabled

System clock protective bit

(Notes 3,4)

PM21

PM22

0 : CPU clock is used for the

watchdog timer count source

1 : Ring oscillator clock is used

for the watchdog timer count

source

WDT count source

protective bit (Notes 3,5)

Reserved bit

PM24

Must always be set to "0"

P8

5

/NMI configuration bit

0: P8

5 function (NMI disable)

(Notes 3,6,7)

1: NMI function

Nothing is assigned.

Writes must set each bit to "0". Read values are indeterminate.

Note 1: Set bit 1 of the protect register (address 000A16) to "1" before writing new values

to this register.

Note 2: When the system clock is 16Mhz and more, must set to 2 waits.

Note 3: This bit cannot be changed from "1" to "0" in software.

Note 4: Setting PM21 to "1" results in the following:

• BCLK is not halted by WAIT instruction.

• Writing to the following bits has no effect:

CM02, of register CM0

CM05, of register CM0 (main clock is not halted)

CM07, of register CM0 (CPU clock source does not change)

CM10, of register CM1 (stop mode is not entered)

CM20, of register CM2 (oscillation stop, re-oscillation detection function settings

do not change)

Note 5: Setting PM22 to "1" results in the following:

• The ring oscillator starts oscillating, and the ring oscillator clock becomes the

watchdog timer count source.

• Writing to CM10 disabled (stop mode is not entered).

• Watchdog timer does not stop when in wait mode or hold state.

Note 6: For NMI function, this bit must be set to "1" in first instruction after reset.

Note 7: When this bit is set to "1", the P85 direction register must be "0".

Figure 1.7.2. Processor mode register 2

Software Reset

Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the

microcomputer. A software reset has the same effect as a hardware reset except the contents of internal

RAM are preserved after a software reset.

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect

register (address 000A16) to “1”.

26

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Processor Mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software wait

A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address

000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).

A software wait is inserted in the internal ROM/RAM area by setting the wait bit of processor mode register

1. When set to "0", each bus cycle is executed in one BCLK cycle. When set to "1", each bus cycle is

executed in two BCLK cycles. After the microcomputer has been reset, this bit defaults to "0". When set to

"1", a wait is applied to all memory areas (two BCLK cycles). Set this bit after referring to the recommended

operating conditions (main clock input oscilliation frequecny) of the electrical characteristics.

The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.

Table 1.7.1 shows the software wait and bus cycles.

Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect

register (address 000A16) to “1”.

Table 1.7.1. Software waits and bus cycles

Bus cycle

Area

Wait bit

0

1

1 BCLK cycle

2 BCLK cycles

Internal

ROM/RAM

27

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M16C/26 Group

Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Generating Circuit

The clock generating circuit contains three oscillator circuits as follows:

(1) Main clock generating circuit

(2) Sub clock generating circuit

(3) Ring oscillator

Table 1.8.1 lists the clock generating circuit specifications.

Table 1.8.1. Clock generating circuits

Example of oscillator circuit

Main clock

generating circuit

Sub clock

generating circuit

Ring oscillator

Item

-

- CPU's operating

clock source

- CPU's operating

clock source

CPU clock source

Peripheral function

clock source

CPU and peripheral

function clock source

when main clock

frequency stops

Use of clock

- Internal peripheral - Timer A/B's count

unit's operating

clock source

-

- Ceramic oscillator - Crystal oscillator About 1MHz

- Crystal oscillator

Usable oscillator

X

IN, XOUT

XCIN, XCOUT

Pins to connect

oscillator

Available

Stopped

Available

Stopped

Oscillation stop/

restart function

Oscillating

Oscillator status

after reset

Externally derived clock can be input

Other

28

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Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.8.1 shows some examples of the main clock circuit, one using an oscillator connected to the

circuit, and the other one using an externally derived clock for input. Figure 1.8.2 shows some examples of

sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally

derived clock for input. Circuit constants in Figures 1.8.1 and 1.8.2 vary with each oscillator used. Use the

values recommended by the manufacturer of your oscillator.

Microcomputer

(Built-in feedback resistor)

Microcomputer

(Built-in feedback resistor)

XIN

XOUT

X

IN

XOUT

Open

(Note)

R

d

Externally derived clock

Vcc

Vss

C

IN

C

OUT

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

capacity setting. Use the value recommended by the maker of the oscillator.

When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's

data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN

and XOUT following the instruction.

Figure 1.8.1. Examples of main clock

Microcomputer

(Built-in feedback resistor)

Microcomputer

(Built-in feedback resistor)

XCIN

XCOUT

XCIN

XCOUT

Open

(Note)

R

Cd

Externally derived clock

C

CIN

CCOUT

Vcc

Vss

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

capacity setting. Use the value recommended by the maker of the oscillator.

Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip,

insert a feedback resistor between XCIN and XCOUT following the instruction.

Figure 1.8.2. Examples of sub-clock

29

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Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Control

Figure 1.8.3 shows the block diagram of the clock generating circuit.

Sub-clock

generating circuit

X

CIN

XCOUT

fC32

1/32

CM04

f

1

2

PCLK0=1

PCLK0=0

Sub-clock

f

fC

Ring

oscillator

clock

f8

Ring

oscillator

CM21

f32

fAD

Oscillation

stop, re-

oscillation

detection

circuit

f

1SIO

PCLK1=1

PCLK1=0

f2SIO

f8SIO

CM10=1(stop mode)

S

R

Q

XIN

XOUT

f32SIO

e

b

c

1

0

1

CM07=0

a

d

Divider

0

Main

clock

BCLK

CM21

CM20

fC

Main clock

generating circuit

CM07=1

CM05

CM02

S

R

Q

WAIT instruction

c

e

b

1/2

a

1/32

RESET

1/2

1/4

1/8

1/16

Software reset

NMI

CM06=0

CM17–CM16=11

2

CM06=1

2

CM06=0

CM17–CM16=10

Interrupt request level judgment output

d

CM02, CM04, CM05, CM06, CM07: CM0 register bits

CM10, CM11, CM16, CM17: CM1 register bits

PCLK0, PCLK1: PCLK register bits

CM06=0

CM17–CM16=01

2

CM21, CM27 : CM2 register bits

CM06=0

CM17–CM16=00

2

Details of divider

Figure 1.8.3. Clock generating circuit

30

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Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

The following paragraphs describes the clocks generated by the clock generating circuit.

(1) Main clock

The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to

the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the

clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.

After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock

oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).

Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit

changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power

dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed

mode, the value before high-speed/medium-speed mode is retained.

(2) Sub-clock

The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.

After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be

selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure

that the sub-clock oscillation has fully stabilized before switching.

After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock

oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).

Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit

changes to “1” when the port XC select bit (bit 4 at address 000616) is set to “0” , shifting to stop mode and

at a reset.

When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.

(3) BCLK

The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by

1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.

The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-

speed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting

from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed

mode is retained.

(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)

The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The

peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function

clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.

By setting the timer A, B clock select bit (bit 0 at address 001E16) and SIO clock select bit (bit 1 at address

001E16) to "1" respectively, f1 and f1SIO2 can be changed to the main clock divided by 2.

(5) fC32

This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.

(6) fC

This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.

Figure 1.8.4a shows the system clock control registers 0 and 1 and Figure 1.8.4b shows peripheral clock

select register.

31

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Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

System clock control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

CM0

Address

000616

When reset

4816

Bit symbol

Bit name

Function

0

R W

Must always be set to

Reserved bit

0

WAIT peripheral function

clock stop bit

0 : Do not stop peripheral function clock in wait mode

1 : Stop peripheral function clock in wait mode (Note 8)

CM02

CM03

X

CIN-XCOUT drive capacity 0 : LOW

select bit (Note 2)

1 : HIGH

Port X

(Note 10)

Main clock (XIN-XOUT

stop bit (Note 3, 4, 5)

C

select bit

0 : I/O port

1 : XCIN-XCOUT generation (Note 9)

CM04

CM05

)

0 : On

1 : Off

Main clock division select 0 : CM16 and CM17 valid

CM06

CM07

bit 0 (Note 7)

1 : Division by 8 mode

System clock select bit

(Note 6)

0 : XIN, XOUT

1 : XCIN, XCOUT

Note 1: Set bit 0 of the protect register (address 000A16) to 1 before writing to this register.

Note 2: Changes to 1 when shifting to stop mode and at a reset.

Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock

oscillation is stable, set system clock select bit (CM07) to 1 before setting this bit to 1 . The main clock division select

bit 0 (CM06) and the XIN-XOUT drive capacity select bit (CM15) change to 1 when this bit is set to 1 .

Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.

Note 5: If this bit is set to 1 , XOUT turns H . The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT

( H ) via the feedback resistor.

Note 6: Set port XC select bit (CM04) to 1 and stabilize the sub-clock oscillating before setting this bit from 0 to 1 .

Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to 0 and stabilize the main clock

oscillating before setting this bit from 1 to 0 .

Note 7: This bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation

mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/

medium-speed mode is retained.

Note 8: fC32 is not included. Do not set to 1 when using low-speed or low power dissipation mode.

Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.

Note 10: When setting this bit to "0", XCIN-XCOUT drive capacity select bit becomes "1".

System clock control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

CM1

Address

000716

When reset

2016

0

Bit symbol

CM10

Bit name

Function

R W

All clock stop control bit

(Note4)

0 : Clock on

1 : All clocks off (stop mode)

Must always be set to

0

Reserved bit

X

IN-XOUT drive capacity

0 : LOW

1 : HIGH

b7 b6

CM15

select bit (Note 2)

Main clock division

select bit 1 (Note 3)

0 0 : No division mode

CM16

CM17

0 1 : Division by 2 mode

1 0 : Division by 4 mode

1 1 : Division by 16 mode

Note 1: Set bit 0 of the protect register (address 000A16) to 1 before writing to this register.

Note 2: This bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation

mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/

medium-speed mode is retained.

Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is 0 . If 1 , division mode is fixed at 8.

Note 4: If this bit is set to 1 , XOUT turns H , and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state.

Figure 1.8.4a. Clock control registers 0 and 1

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Clock Generating Circuit

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Peripheral clock select register (Note)

Symbol

PCLKR

Address

025E16

When reset

0316

b7 b6 b5 b4 b3 b2 b1 b0

0

0 0 0 0 0

R W

Bit symbol

PCLK0

Bit name

Function

Timers A, B clock select bit

(Clock source for the

timers A, B, and the dead

time timer)

0 : f

1 : f

2

1

SI/O clock select bit

(Clock source for UART0

to UART2)

PCLK1

0 : f2SIO

1 : f1SIO

Reserved bit

Must always be set to

0

Note: Set the bit 0 of the protect register (address 000A16) to "1" before rewriting

this register.

Figure 1.8.4b. Peripheral clock select register

Processor mode register 2 (Note 1)

Symbol

PM2

Address

001E16

When reset

b7 b6 b5 b4 b3 b2 b1 b0

XXX00000

2

0

0 0

R W

Bit symbol

PM20

Bit name

Function

Specifying wait when

accessing SFR registers

(Note 2)

0 : 2 waits

1 : 1 wait

0 : Clock is protected by PRCR

register

1 : Clock modification disabled

System clock protective bit

(Notes 3,4)

PM21

PM22

0 : CPU clock is used for the

watchdog timer count source

1 : Ring oscillator clock is used

for the watchdog timer count

source

WDT count source

protective bit (Notes 3,5)

Reserved bit

PM24

Must always be set to "0"

P8

5

/NMI configuration bit

0: P8

5 function (NMI disable)

(Notes 3,6,7)

1: NMI function

Nothing is assigned.

Writes must set each bit to "0". Read values are indeterminate.

Note 1: Set bit 1 of the protect register (address 000A16) to "1" before writing new values

to this register.

Note 2: When the system clock is 16Mhz and more, must set to 2 waits.

Note 3: This bit cannot be changed from "1" to "0" in software.

Note 4: Setting PM21 to "1" results in the following:

• BCLK is not halted by WAIT instruction.

• Writing to the following bits has no effect:

CM02, of register CM0

CM05, of register CM0 (main clock is not halted)

CM07, of register CM0 (CPU clock source does not change)

CM10, of register CM1 (stop mode is not entered)

CM20, of register CM2 (oscillation stop, re-oscillation detection function settings

do not change)

Note 5: Setting PM22 to "1" results in the following:

• The ring oscillator starts oscillating, and the ring oscillator clock becomes the

watchdog timer count source.

• Writing to CM10 disabled (stop mode is not entered).

• Watchdog timer does not stop when in wait mode or hold state.

Note 6: For NMI function, this bit must be set to "1" in first instruction after reset.

Note 7: When this bit is set to "1", the P85 direction register must be "0".

Figure 1.8.4c. Processor mode register 2

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Oscillation Stop Detection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Oscillation Stop Detection Function

The oscillation stop detection function detects abnormal stopping of the clock by causes such as opening

and shorting of the XIN oscillation circuit. When oscillation stop is detected, either an internal reset or an

oscillation stop detection interrupt is generated. The selection depends on the value in the bit 7 of the

oscillation stop detection register (address 000C16). When an oscillation stop detection interrupt is gener-

ated, the ring oscillator in the microcomputer operates automatically and is used as the system clock in

place of the XIN clock. This allows interrupt processing.

The oscillation stop detection function can be enabled/disabled with bit 0 of the oscillation stop detection

register. When this bit is set to “1,” the function is enabled. After the reset is released, the oscillation stop

detection function becomes disabled because the bit value is “0.”

Table 1.8.2 gives an specification overview of the oscillation stop detection function, Figure 1.8.5 is a

configuration diagram of the oscillation stop detection circuit and Figure 1.8.6 shows the configuration of

the oscillation stop detection register.

Table 1.8.2. Specification overview of the oscillation stop detection function

Item

Specification

Oscillation stop detectable clock f(XIN) ³ 2 MHz

and frequency bandwidth

Enabling condition for oscillation When the oscillation stop detection bit (bit 0 of address 000C16)

stop detection function

Operation at oscillation stop,

re-oscillation detection

is set to “1”

• Internal reset occurs (when bit CM27 = "0")

• Oscillation stop, re-oscillation detection interrupt occurs (when bit

CM27 = “1”)

Notes on STOP mode

Before setting up the stop mode, write “0” in the oscillation stop

detection enable bit to disable the oscillation stop detection function.

Write "1" in the bit again after the stop mode is.

Internal reset

generating circuit

Pulse generation

circuit for clock

edge detection

and charge/

0

1

Internal reset

To the CPU

Charge/

discharge

circuit

X

IN

Oscillation stop

detection interrupt

generating circuit

discharge control

CM07

Watchdog

timer

interrupt

CM21, CM20

Main clock switch control

11

01

Ring oscillator

To the main clock

division circuit

Main clock

#:When XIN is supplied, this repeats charge and discharge with pulses by XIN edge detection.

When XIN is not supplied, this continues charging. When the charge exceeds a certain level,

it regards the oscillation as stopped.

Figure 1.8.5. Oscillation stop detection circuit

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Oscillation Stop Detection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Oscillation stop detection register (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

CM2

Address

000C₁₆

When reset

0X000000₂

0

(Note 10)

Function

R W

Bit symbol

Bit name

0 : Oscillation stop, re-oscillation

detection function is disabled.

1 : Oscillation stop, re-oscillation

detection function enabled.

Oscillation stop, re-

oscillation detection bit

(Notes 7, 8, 9, 10)

CM20

CM21

0 : Main clock (Ring oscillator

turned off

1 : Ring oscillator clock

(Ring oscillator oscillating)

CPU clock switch bit

(Notes 2, 3, 6, 10)

0 : Main clock stop, re-oscillation

not detected

1 : Main clock stop, re-oscillation

detected

Oscillation stop, re-

oscillation detection flag

(Note 4)

CM22

CM23

0 : Main clock oscillating

1 : Main clock turned off

XIN monitor flag (Note 5)

Reserved bit

Must always be set to "0".

Nothing is assigned. Writes must set to "0". Reads are indeterminate.

Operation select bit

0 : Reset

(when an oscillation stop,

re-oscillation is detected)

(Note 10)

CM27

1 : Oscillation stop, re-oscillation

detection interrupt

Note 1: Write to this register after setting bit PRC0, of register PRCR, to "1" (write enable).

Note 2: CM21 is set to "1" (ring oscillator clock) when the main clock is stopped, and the following conditions exist:

• CM20 is "1" (oscillation stop, re-oscillation detection function enabled).

• CM27 is "1" (oscillation stop, re-oscillation detection interrupt).

• CPU clock source is the main clock.

Note 3: If CM20 is "1", and CM23 is "1" (main clock turned off), do not set CM21 to "0".

Note 4: This bit is set to "1" by main clock stop detection and re-oscillation detection. Each oscillation stop, re-oscillation

detection interrupt must correspond to a "0" to "1" transition of CM22. Once an interrupt is received, the bit can

only be cleared via an explicit "0" write operation. Otherwise, further interrupts will be disabled. Only "0" writes can

affect the bit value. CM22 is also used as a means for distinguishing between those interrupts caused by the

oscillation stop, re-oscillation detection circuitry, and those initiated by the watchdog timer.

Note 5: Read CM23 in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main

clock status.

Note 6: Effective when bit CM07, of register CM0, is "0".

Note 7: When bit PM21, of register PM2, is "1" (clock modification disabled), writing to CM20 has no effect.

Note 8: Set CM20 to "0" (disable) before entering stop mode. After exiting stop mode, set CM20 back to "1" (enable).

Note 9: Set CM20 to "0" (disable) before setting bit CM05, of register CM0.

Note 10: CM20, CM21, and CM27 do not change at oscillation stop detection reset.

Figure 1.8.6. Oscillation stop detection register

35

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Oscillation Stop Detection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Oscillation stop detection bit (CM20)

You can start the oscillation stop detection by setting this bit to “1”. The detection is not executed when

this bit is set to “0” or in reset status. Be sure to set this bit to “0” before setting for the stop-mode. Set this

bit again to “1” after release from stop-mode. This is because it is necessary to cancel the oscillation stop

detection function due to a certain period of unstable oscillation after release from stop-mode. Set this bit

to “0” also before setting the main clock stop bit (bit 5 at 000616) to “1”.

Do not set this bit to “1” if the frequency of XIN is lower than 2 MHz.

Main clock switch bit (CM21)

You can use the ring oscillator as a system clock by setting this bit to “1”. When this bit is "0", the ring

oscillator is not in operation. For more explanation, see the section of the clock generating circuit.

Oscillation stop detection status (CM22)

You can see the status of the oscillation stop detection. When this bit is “1”, an oscillation stop is de-

tected. For usage of this bit, see the explanation on CM27.

Clock monitor bit (CM23)

You can see the operation status of the XIN clock. When this bit is “0”, XIN is operating correctly. You can

check the operation status of XIN when an oscillation stop detection interrupt is generated.

Operation select (when an oscillation stop is detected) bit (CM27)

(1) Operation when internal reset is selected (CM27 is set to “0”.)

An internal reset is generated when an abnormal stop of XIN is detected. The microcomputer stops in

reset status and does not operate further.

Note: Release from this status is only possible through an external reset. However, in case of a

defect XIN clock, further operation cannot be compensated.

All ports are configured to input port (floating) after an internal reset is generated.

(2) Operation when oscillation stop detection interrupt is selected (CM27 is set to “1”.)

An oscillation stop detection interrupt is generated when an abnormal stop of XIN is detected. The ring

oscillator starts operation instead of the XIN clock which stopped abnormally. The operation goes further

with the supply from the ring oscillator. For the oscillation stop detection interrupt judgement on the

interrupt condition is necessary, because this interrupt shares the vector table with watchdog timer inter-

rupt. Use the oscillation stop detection status (CM22) for the judgment. By clearing CM22, the accep-

tance of oscillation stop detection interrupt resumes. Figure 1.8.7 shows the flow of the judgment.

36

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Oscillation Stop Detection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Oscillation stop detection interrupt

or watchdog timer interrupt

is generated

Read CM22

NO

CM22=1?

YES

Jump to the execution

program for oscillation stop

detection interrupt

Jump to the execution

program for watchdog timer

interrupt

Figure 1.8.7. Flow of the judgment

37

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

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Oscillation Stop Detection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Stop Mode

Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-

puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC

remains above 2V.

Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral

functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B

operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions

provided an external clock is selected. Port pins retain their status from before stop mode is entered.

Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop

mode, that interrupt must first have been enabled, and the priority level of the interrupts which are not used

to cancel must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only

a hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupts

to 0, then shift to stop mode.

The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-speed/

medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from

high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is

retained.

Wait Mode

When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this

mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral

function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal

peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32

does not stop so that the peripherals using fC32 do not contribute to the power saving. When the microcom-

puter is running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”.

Port pins retain their status from before wait mode is entered.

Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that

interrupt must first have been enabled, and the priority level of the interrupts which are not used to cancel

must have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed

is set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hard-

ware reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupts to 0,

then shift to wait mode.

38

Renesas Technology Corp.

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Status Transition of BCLK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Status Transition of BCLK

Power dissipation can be reduced and low-voltage operation achieved by changing the count source for

BCLK. Table 1.8.3 shows the operating modes corresponding to the settings of system clock control

registers 0 and 1.

When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address

000616) and the XIN-XOUT drive capacity select bit (bit 5 at address 000716) change to “1” when shifting

from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset.

When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/

medium-speed mode is retained. The following shows the operational modes of BCLK.

(1) Division by 2 mode

The main clock is divided by 2 to obtain the BCLK.

(2) Division by 4 mode

The main clock is divided by 4 to obtain the BCLK.

(3) Division by 8 mode

The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this

mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4

mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption

mode, make sure the sub-clock is oscillating stably.

(4) Division by 16 mode

The main clock is divided by 16 to obtain the BCLK.

(5) No-division mode

The main clock is divided by 1 to obtain the BCLK.

(6) Low-speed mode

fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before

transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-

clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately

after powering up and after stop mode is cancelled.

(7) Low power dissipation mode

fC is the BCLK and the main clock is stopped.

39

Renesas Technology Corp.

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development

M16C/26 Group

Status Transition of BCLK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.8.3. Operating modes dictated by settings of system clock control registers 0, 1, and 2

CM2 register

CM1 register

CM11 CM17, CM16

CM0 register

Modes

CM21

CM07

CM06

CM05

CM04

High-speed mode

0

00

01

10

2

0

1

0

1

0

Midium-

speed

mode

divided by 2

divided by 4

divided by 8

divided by 16

11

2

Low-speed mode

1

Low power dissipation mode

1(Note 1) 1(Note 1)

Ring

oscillator

mode

divided by 1

divided by 2

divided by 4

divided by 8

divided by 16

1

0

1

0

1

0

1

0

2

0

1

0

1

0

1

2

0

Ring oscillator low power

dissipation mode

(Note 2)

Note 1: When set the CM05 bit to “1” (main clock turned off), CM06 bit become “1” (divided by 8 mode).

Note 2: The divide-by-n value can be selected the same way as in ring oscillator mode.

40

Renesas Technology Corp.

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Power Control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Power control

The following is a description of the three available power control modes:

Modes

Power control is available in three modes.

(a) Normal operation mode

• High-speed mode

Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK.

Each peripheral function operates according to its assigned clock.

• Medium-speed mode

Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the BCLK.

The CPU operates with the BCLK. Each peripheral function operates according to its assigned clock.

• Low-speed mode

fC becomes the BCLK. The CPU operates according to the fC clock. The fC clock is supplied by the

subclock. Each peripheral function operates according to its assigned clock.

• Low power dissipation mode

The main clock operating in low-speed mode is stopped. The CPU operates according to the fC

clock. The fC clock is supplied by the subclock. The only peripheral functions that operate are

those with the subclock selected as the count source.

• Ring oscillator mode

The ring oscillator clock divided by 1 (undivided), 2, 4, 8, or 16 provides BCLK. The ring oscillator

clock is also the clock source for the peripheral function clocks. If the sub-clock is on, fC32 can be

used as the count source for timers A and B.

• Ring oscillator low power dissipation mode

The main clock is turned off after being placed in ring oscillator mode. The CPU clock can be selected as

in the ring oscillator mode. The ring oscillator clock is the clock source for the peripheral function clocks.

If the sub-clock is on, fC32 can be used as the count source for timers A and B. When the operation

mode is returned to the high and medium speed modes, set the CM06 bit to “1” (divided by 8 mode).

(b) Wait mode

The CPU operation is stopped. The oscillators do not stop.

(c) Stop mode

All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three

modes listed here, is the most effective in decreasing power consumption.

Table 1.8.4. Oscillation state in each mode

XIN

XCIN

Ring

OFF

Medium-speed mode (divide-by-8

frequency after reset released)

BCLK

OFF

High/medium-speed

Low-speed mode

BCLK

ON

ON/OFF ON/OFF

BCLK

OFF

Low power dissipation mode

Ring oscillator mode

OFF

ON/OFF ON/OFF

OFF ON/OFF

BCLK

Ring oscillator low power

dissipation mode

BCLK

Figure 1.8.8 is the state transition diagram of the above modes.

41

Renesas Technology Corp.

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Power Control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Transition of stop mode, wait mode

Reset

CPU operation stopped

WAIT

instruction

CM10=1

All oscillators stopped

Medium-speed mode

(divided-by-8 mode)

Wait mode

Stop mode

Interrupt

WAIT

instruction

All oscillators stopped

High-speed/medium-

speed mode

Wait mode

Stop mode

Interrupt

CM10=1

When

low power

dissipation low-speed

mode mode

When

WAIT

instruction

(Note 1)

All oscillators stopped

Low-speed/low power

dissipation mode

Stop mode

Wait mode

Interrupt

CM10=1

WAIT

instruction

(Note 1)

Ring oscillator, Ring oscillator

dissipation mode

Stop mode

Interrupt

(Note 2)

Normal mode

(Refer to the following for the transition of normal mode.)

Main clock is oscillating

Sub clock is stopped

Transition of normal mode

Medium-speed mode

(divided-by-8 mode)

CM06 =

1

BCLK : f(XIN)/8

CM07 =

0

CM06 = 1

CM07 =

CM06 =

CM04 =

0

1

0

(Note 3)

CM04 =

0

CM04 =

1

Main clock is oscillating

Sub clock is oscillating

Main clock is oscillating

Sub clock is oscillating

(Notes 3, 5)

Medium-speed mode

(divided-by-2 mode)

Low-speed mode

CM07 =

(Note 3, 5)

0

High-speed mode

Medium-speed mode

(divided-by-8 mode)

BCLK : f(XIN

)

BCLK : f(XIN)/2

CM07 =

CM17 =

0

CM06 =

CM16 =

0

CM07 =

CM17 =

0

CM06 =

CM16 =

0

1

BCLK : f(XCIN

CM07 =

)

BCLK : f(XIN)/8

CM07 =

(Note 4)

1

CM07 =

CM06 =

0

1

Medium-speed mode

(divided-by-4 mode)

Medium-speed mode

(divided-by-16 mode)

BCLK : f(XIN)/4

BCLK : f(XIN)/16

CM07 =

CM17 =

0

1

CM06 =

CM16 =

0

CM07 =

CM17 =

0

1

CM06 =

CM16 =

0

1

CM05 =

1

CM05 =

0

Main clock is stopped

Sub clock is oscillating

Low power

dissipation mode

CM04 =

0

CM04 =

1

CM07 =

CM05 =

1

(Note 4)

BCLK : f(XCIN

CM07 = 1 , CM06 =

CM15 =

)

Main clock is oscillating

Sub clock is stopped

1

Medium-speed mode

(divided-by-2 mode)

High-speed mode

CM07 =

CM06 =

CM04 =

0

1

(Note 3)

(Note 5)

BCLK : f(XIN

)

BCLK : f(XIN)/2

CM07 =

CM17 =

0

CM06 =

CM16 =

0

CM07 =

CM17 =

0

CM06 =

CM16 =

0

1

CM06 =

(Notes 3, 5)

0

Medium-speed mode

(divided-by-4 mode)

Medium-speed mode

(divided-by-16 mode)

BCLK : f(XIN)/4

BCLK : f(XIN)/16

CM07 =

CM17 =

0

1

CM06 =

CM16 =

0

CM07 =

CM17 =

0

1

CM06 =

CM16 =

0

1

CM03="1"

Note 1: When bit PM21 = "0" (system clock protective function unused).

Note 2: The ring oscillator clock divided by 8 provides BCLK.

Note 3: Switch clock after oscillation of main clock is sufficiently stable.

Note 4: Switch clock after oscillation of sub clock is sufficiently stable.

Note 5: Change CM06 after changing CM17 and CM16.

Figure 1.8.8. State transition diagram of power control mode

42

Renesas Technology Corp.

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Protection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Protection

The protection function is provided so that the values in important registers cannot be changed in the event

that the program runs out of control. Figure 1.8.9 shows the protect register. The values in the processor

mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-

ister 0 (address 000616), system clock control register 1 (address 000716), oscillation stop detection regis-

ter (address 000C16), processor mode register 2 (001E16), peripheral clock select register (address

025E16), timer B2 special mode register (039E16), port P9 direction register (address 03F316), three-phase

PWM control register 0 (address 034816) and three-phase PWM control register 1 (address 034916) can

only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs

can be allocated to port P9.

Protect register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PRCR

Address

000A16

When reset

XXX00000

0

2

Bit symbol

PRC0

Bit name

Function

R W

Enables writing to system clock

control registers 0 and 1 (addresses

0 : Write-inhibited

1 : Write-enabled

000616 and 000716

detection register (address 000C16),

peripheral clock select register

), oscillation stop

(address 025E16

)

PRC1

Enables writing to processor mode

registers 0,1 and 2 (addresses 000

0 : Write-inhibited

1 : Write-enabled

4

16,000516 and 001E16), timer B2

special mode register (address

039E16), three-phase PWM control

registers 0 and 1 (addresses

034816 and 034916

)

Enables writing to port P9 direction

register (address 03F316) (note)

0 : Write-inhibited

1 : Write-enabled

PRC2

Enables writing to VCR2 (address

001A16) and D4INT (address 001F16

0 : Write-inhibited

1 : Write-enabled

PRC3

)

Must always set to "0"

Reserved bit

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be

indeterminate.

Note: Writing a value to an address after 1 is written to this bit returns the bit

to 0 . Other bits do not automatically return to 0 and they must therefore

be reset by the program.

Figure 1.8.9. Protect register

43

Renesas Technology Corp.

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupts

Type of Interrupts

Figure 1.9.1 lists the types of interrupts.

Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

Software

INT instruction

Reset

Interrupt

NMI

DBC

Special

Watchdog timer

Single step

Address matched

Hardware

Peripheral I/O (Note)

Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.

Figure 1.9.1. Classification of interrupts

• Maskable interrupt :

An interrupt which can be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority can be changed by priority level.

• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority cannot be changed by priority level.

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable

interrupts.

• Undefined instruction interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

• Overflow interrupt

An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to

“1”. The following are arithmetic instructions changes O flag:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

• BRK interrupt

A BRK interrupt occurs when executing the BRK instruction.

• INT interrupt

An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-

ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-

rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/

O interrupt does.

The stack pointer (SP) used for the INT interrupt is dependent on the software interrupt number

involved.

For software interrupt numbers 0 through 31, the microcomputer saves the stack pointer assignment

flag (U flag) when it accepts an interrupt request. The U flag is changed to “0” and the interrupt stack

pointer (ISP) is selected, and then, the interrupt sequence is executed. When returning from the

interrupt routine, the U flag is returned to the state it was before the interrupt request was accepted.

For software numbers 32 through 63, the U flag is not changed, and so the stack pointer is not

affected.

45

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.

(1) Special interrupts

Special interrupts are non-maskable interrupts.

• Reset

Reset occurs if an “L” is input to the RESET pin.

• NMI interrupt

If enabled, an NMI interrupt occurs if an “L” is input to the NMI pin.

• DBC interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances.

• Watchdog timer interrupt

Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer

interrupt occurs (initialize watchdog timer).

• Single-step interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug

flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.

• Address match interrupt

An address match interrupt occurs immediately before the instruction held in the address indicated by

the address match interrupt register is executed with the address match interrupt enable bit set to “1”.

If an address other than the first address of the instruction in the address match interrupt register is set,

no address match interrupt occurs.

(2) Peripheral I/O interrupts

A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-

tions are dependent on classes of products, so the interrupt factors too are dependent on classes of

products. The interrupt vector table is the same as the one for software interrupt numbers 0 through

31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.

• Bus collision detection interrupt

This is an interrupt that UART2 generates.

• DMA0 interrupt, DMA1 interrupt

These are interrupts that DMA generates.

• Key-input interrupt

A key-input interrupt occurs if an “L” is input to the KI pin.

• A-D conversion interrupt

This is an interrupt that the A-D converter generates.

• UART0, UART1, and UART2/NACK2 transmission interrupt

These are interrupts that the serial I/O transmission generates.

• UART0, UART1, and UART2/ACK2 reception interrupt

These are interrupts that the serial I/O reception generates.

• Timer A0 interrupt through timer A4 interrupt

These are interrupts that timer A generates

• Timer B0 interrupt through timer B2 interrupt

These are interrupts that timer B generates.

• INT0, INT1, INT3 through INT5 interrupt

An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector

table. The first address of the interrupt routine is stored in the corresponding vector. Figure 1.9.2 shows

the format for specifying the address.

Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and

variable vector table in which addresses can be varied by the setting.

MSB

LSB

Vector address + 0

Vector address + 1

Vector address + 2

Vector address + 3

Figure 1.9.2. Format for specifying interrupt vector addresses

• Fixed vector table

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an

address range extending from FFFDC16 to FFFFF16. A vector consists of four bytes. Set the first

address of interrupt routine in the corresponding vector. Table 1.9.1 shows the interrupts assigned to

the fixed vector table and the vector addresses.

Table 1.9.1. Interrupts assigned to the fixed vector tables and addresses of vector tables

Vector table addresses

Address (L) to address (H)

Interrupt source

Remarks

Undefined instruction

Overflow

BRK instruction

FFFDC16 to FFFDF16

FFFE016 to FFFE316

FFFE416 to FFFE716

Interrupt on UND instruction

Interrupt on INTO instruction

If the vector contains FF16, program execution starts from

the address shown by the vector in the variable vector table.

There is an address-matching interrupt enable bit.

Do not use.

Address match

Single step (Note)

Watchdog timer,

FFFE816 to FFFEB16

FFFEC16 to FFFEF16

FFFF016 to FFFF316

Oscillation stop and

re-oscillation detection,

VDET4 detection

DBC (Note)

NMI

Reset

FFFF416 to FFFF716

FFFF816 to FFFFB16

FFFFC16 to FFFFF16

Do not use.

External interrupt by input to NMI pin.

Note: Interrupts used for debugging purposes only.

47

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

• Variable vector tables

The addresses in the variable vector table can be modified by user’s settings. The first address of the

variable vector table is specified by the user using the interrupt table register (INTB). The subsequent

256-byte addresses becomes the area for the variable vector tables. A vector consists of four bytes.

Set the first address of the interrupt routine in the corresponding vector. Table 1.9.2 shows the

interrupts assigned to the variable vector table and the vector addresses.

Table 1.9.2. Interrupts assigned to the variable vector tables and addresses of vector tables

Vector table address

Software interrupt number

Software interrupt number 0

Interrupt source

BRK instruction

Remarks

Address (L) to address (H)

+0 to +3 (Note 1)

Cannot be masked I flag

Software interrupt number 4

Software interrupt number 5

+16 to +19 (Note 1)

+20 to +23 (Note 1)

INT3

Reserved

Software interrupt number 6

Software interrupt number 7

Software interrupt number 8

Software interrupt number 9

Software interrupt number 10

Software interrupt number 11

+24 to +27 (Note 1)

+28 to +31 (Note 1)

+32 to +35 (Note 1)

+36 to +39 (Note 1)

+40 to +43 (Note 1)

+44 to +47 (Note 1)

Reserved

INT5

INT4

UART 2 bus collision detection

DMA0

Software interrupt number 12

Software interrupt number 13

Software interrupt number 14

Software interrupt number 15

Software interrupt number 16

Software interrupt number 17

Software interrupt number 18

Software interrupt number 19

Software interrupt number 20

Software interrupt number 21

Software interrupt number 22

Software interrupt number 23

Software interrupt number 24

Software interrupt number 25

Software interrupt number 26

Software interrupt number 27

Software interrupt number 28

Software interrupt number 29

Software interrupt number 30

Software interrupt number 31

Software interrupt number 32

+48 to +51 (Note 1)

+52 to +55 (Note 1)

+56 to +59 (Note 1)

+60 to +63 (Note 1)

+64 to +67 (Note 1)

+68 to +71 (Note 1)

+72 to +75 (Note 1)

+76 to +79 (Note 1)

+80 to +83 (Note 1)

+84 to +87 (Note 1)

+88 to +91 (Note 1)

+92 to +95 (Note 1)

+96 to +99 (Note 1)

+100 to +103 (Note 1)

+104 to +107 (Note 1)

+108 to +111 (Note 1)

+112 to +115 (Note 1)

+116 to +119 (Note 1)

+120 to +123 (Note 1)

+124 to +127 (Note 1)

+128 to +131 (Note 1)

DMA1

Key input interrupt

A-D

UART2 transmit/NACK2 (Note 2)

UART2 receive/ACK2 (Note 2)

UART0 transmit

UART0 receive

UART1 transmit

UART1 receive

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

Timer B0

Timer B1

Timer B2

INT0

INT1

Reserved

to

Cannot be masked I flag

Software interrupt

Software interrupt number 63

+252 to +255 (Note 1)

Note 1: Address relative to address specified in interrupt table register (INTB).

Note 2: When IIC mode is selected, NACK and ACK interrupts are selected.

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt Control

This section describes how to enable or disable maskable interrupts and how to set the priority to be

accepted. The discussion here does not apply to non-maskable interrupts.

Maskable interrupts are enabled or disabled using the interrupt enable flag (I flag), the interrupt priority

level selection bit, and the processor interrupt priority level (IPL). Whether an interrupt request is present

or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level

selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I

flag) and the IPL are located in the flag register (FLG).

Figure 1.9.3 shows the configuration and memory map of the interrupt control registers.

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Interrupts

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Interrupt control register (Note 2)

Symbol

Address

When reset

BCNIC

DMiIC(i=0, 1)

KUPIC

XXXXX000

2

004A₁₆

004B16, 004C ¹⁶

004D¹⁶

2

ADIC

004E¹⁶

SiTIC(i=0 to 2)

SiRIC(i=0 to 2)

TAiIC(i=0 to 4)

TBiIC(i=0 to 2)

0051¹⁶, 005316, 004F16

0052¹⁶, 005416, 005016

0055¹⁶to 005916

005A¹⁶to 005C16

b7 b6 b5 b4 b3 b2 b1 b0

R

W

Bit symbol

ILVL0

Bit name

Function

Interrupt priority level

select bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

ILVL1

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL2

IR

Interrupt request bit

0 : Interrupt not requested

1 : Interrupt requested

(Note 1)

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns

out to be indeterminate.

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).

Note 2: To rewrite the interrupt control register, do so at a point that does not generate the

interrupt request for that register. For details, see the precautions for interrupts.

Symbol

INTiIC(i=3)

INTiIC(i=4, 5)

INTiIC(i=0, 1)

Address

004416 XX00X000

004916, 004816 XX00X000

005D16, 005E₁₆

When reset

2

b7 b6 b5 b4 b3 b2 b1 b0

XX00X000

0

R

W

Bit symbol

ILVL0

Bit name

Interrupt priority level

select bit

Function

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

ILVL1

ILVL2

IR

Interrupt request bit

Polarity select bit

0: Interrupt not requested

1: Interrupt requested

(Note 1)

POL

0 : Selects falling edge

1 : Selects rising edge

Reserved bit

Must always be set to 0

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns

out to be indeterminate.

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).

Note 2: To rewrite the interrupt control register, do so at a point that does not generate the

interrupt request for that register. For details, see the precautions for interrupts.

Figure 1.9.3. Interrupt control registers

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Interrupt Enable Flag (I flag)

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this

flag to “1” enables all maskable interrupts while setting it to “0” disables all maskable interrupts. This flag

is set to “0” after reset.

Interrupt Request Bit

The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is

accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The

interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”).

Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits

of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared

with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.

Therefore, setting the interrupt priority level to “0” disables the interrupt.

Table 1.9.3 shows the settings of interrupt priority levels and Table 1.9.4 shows the interrupt levels

enabled, according to the contents of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = “1”

· interrupt request bit = “1”

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are

independent, and so, not affected by one another.

Table 1.9.4. Interrupt levels enabled according

Table 1.9.3. Settings of interrupt priority levels

to the contents of the IPL

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

IPL

Enabled interrupt priority levels

b2 b1 b0

IPL

2

IPL

1

IPL0

Level 0 (interrupt disabled)

0

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

0

1

0

1

0

1

0

1

0

1

0

1

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

0

1

0

Low

0

1

0

1

0

1

0

1

High

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Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for

that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after

the interrupt is disabled. The program examples are described as follow:

Example 1:

INT_SWITCH1:

FCLR

I

; Disable interrupts.

AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.

NOP

FSET

; Four NOP instructions are required when using HOLD function.

; Enable interrupts.

I

Example 2:

INT_SWITCH2:

FCLR

I

; Disable interrupts.

AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

; Enable interrupts.

FSET

I

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

; Disable interrupts.

FCLR

I

AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.

POPC FLG ; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted

before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the

interrupt control register is rewritten due to effects of the instruction queue.

When changing an interrupt control register at a point where the interrupt is disabled, please read the

following precautions on instructions used before changing the register.

(1) Changing a non-interrupt request bit (interrupt priority level)

If an interrupt request for an interrupt control register is generated during an instruction to rewrite the

register is being executed, it is possible that the interrupt request bit is overwritten (reset to "0") and

consequently the interrupt is ignored. This will depend on the instruction used. If this creates problems,

use the instructions below to change the register.

Instructions : AND, OR, BCLR, BSET

(2) Changing the interrupt request bit

When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit

is not cleared sometimes. This will depend on the instruction used. If this creates problems, use the

instructions below to change the register.

Instructions : MOV

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Interrupt Sequence

This section describes an interrupt sequence — what are performed over a period from the time an inter-

rupt is accepted until the time the interrupt routine is executed .

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

In the interrupt sequence, the processor operates in the following sequence:

(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address

0000016. After this, the corresponding interrupt request bit becomes “0”.

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence

in the temporary register (Note) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to

“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32 through 63,

is executed)

(4) Saves the content of the temporary register (Note) within the CPU in the stack area.

(5) Saves the content of the program counter (PC) in the stack area.

(6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the first

address of the interrupt routine.

Note: This register cannot be utilized by the user.

Interrupt Response Time

'Interrupt response time' is the period between the time an interrupt occurs and the time the first instruc-

tion within the interrupt routine has been executed. This time comprises the period from the occurrence

of an interrupt to the completion of the instruction under execution at that moment (a) and the time

required for executing the interrupt sequence (b). Figure 1.9.4 shows the interrupt response time.

Interrupt request generated

Interrupt request acknowledged

Time

Instruction in

interrupt routine

Instruction

(a)

Interrupt sequence

(b)

Interrupt response time

(a) Time from interrupt request is generated to when the instruction then under execution is completed.

(b) Time in which the instruction sequence is executed.

Figure 1.9.4. Interrupt response time

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Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the

DIVX instruction (without wait).

Time (b) is as shown in Table 1.9.5.

Table 1.9.5. Time required for executing the interrupt sequence

Interrupt vector address Stack pointer (SP) value

6-Bit bus, without wait

8-Bit bus, without wait

Even

Odd

18 cycles (Note 1)

19 cycles (Note 1)

20 cycles (Note 1)

Even

Odd (Note 2)

Even

Odd

Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match

interrupt or of a single-step interrupt.

Note 2: Locate an interrupt vector address in an even address, if possible.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

BCLK

Address

0000

Address bus

Data bus

Indeterminate

SP-2

SP-4

vec

vec+2

PC

Interrupt

information

SP-2

SP-4

vec

vec+2

contents contents contents contents

R

Indeterminate

W

The indeterminate segment is dependent on the queue buffer.

If the queue buffer is ready to take an instruction, a read cycle occurs.

Figure 1.9.5. Time required for executing the interrupt sequence

Variation of IPL when Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set

in the IPL.

When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed

in Table 1.9.6 is set in the IPL. Shown in Table 1.9.6 are the IPL values of software and special interrupts

when they are accepted.

Table 1.9.6. Relationship between interrupts without interrupt priority levels and IPL

Interrupt sources without priority levels

Level that is set to IPL

Watchdog timer, NMI, Oscillation stop and re-oscillation detection,

7

VDET4 detection

Software, address match, DBC, single-step

Not changed

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Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter

(PC) are saved in the stack area.

First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8

lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the

program counter. Figure 1.9.6 shows the state of the stack as it was before the acceptance of the

interrupt request, and the state the stack after the acceptance of the interrupt request.

To save other necessary registers, use the PUSHM instruction to save these registers except the stack

pointer (SP)at the beginning of the interrupt routine.

Stack area

Address

MSB

Address

MSB

LSB

[SP]

New stack

pointer value

m - 4

Program counter (PC

L

)

m - 3

m - 2

m - 1

m

m - 3

m - 2

m - 1

m

Program counter (PC )

M

Flag register (FLG )

L

Flag register

(FLG

Program

counter (PC )

H

)

H

[SP]

Stack pointer

value before

interrupt occurs

Content of previous stack

m + 1

Stack status before interrupt request

is acknowledged

Stack status after interrupt request

is acknowledged

Figure 1.9.6. State of stack before and after acceptance of interrupt request

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The operation of saving registers carried out in the interrupt sequence is dependent on whether the

content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If

the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the

program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at

a time. Figure 1.9.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer

indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).

(1) Stack pointer (SP) contains even number

Sequence in which order

registers are saved

Address

Stack area

[SP] - 5 (Odd)

[SP] - 4 (Even)

[SP] - 3 (Odd)

[SP] - 2 (Even)

[SP] - 1 (Odd)

Program counter (PC )

L

(2) Saved simultaneously,

all 16 bits

Program counter (PC

Flag register (FLG

M

)

L

)

(1) Saved simultaneously,

all 16 bits

Flag register

(FLG

Program

counter (PC )

H

)

H

[SP]

(Even)

Finished saving registers

in two operations.

(2) Stack pointer (SP) contains odd number

Address

Stack area

Sequence in which order

registers are saved

[SP] - 5 (Even)

[SP] - 4 (Odd)

[SP] - 3 (Even)

[SP] - 2 (Odd)

[SP] - 1 (Even)

Program counter (PC )

L

(3)

(4)

Program counter (PC

Flag register (FLG

M

)

Saved simultaneously,

all 8 bits

L

)

(1)

(2)

Program

counter (PC )

Flag register

(FLG

H

)

[SP]

(Odd)

Finished saving registers

in four operations.

Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Figure 1.9.7. Operation of saving registers

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Returning from an Interrupt Routine

Executing a REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG)

as it was immediately before the start of interrupt sequence and the contents of the program counter (PC),

both of which have been saved in the stack area. Then control returns to the program that was being

executed before the acceptance of the interrupt request, so that the suspended process resumes.

To return the other registers saved by software within the interrupt routine, use the POPM or similar instruc-

tion before executing the REIT instruction.

Interrupt Priority

If there are two or more interrupt requests generated at the same time, the interrupt assigned with a higher

priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level

select bit. If the same interrupt priority level is assigned, however, the interrupt assigned with a higher

hardware priority is accepted.

Priorities for the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority),

watchdog timer interrupt, etc. are controlled by hardware.

Figure 1.9.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

Figure 1.9.8. Hardware interrupts priorities

Interrupt resolution circuit

When two or more interrupts are generated simultaneously, the circuit in Figure 1.9.9 selects the interrupt

based on the priority level shown.

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Priority level of each interrupt

Level 0 (initial value)

High

INT1

Timer B2

Timer B0

Timer A3

Timer A1

INT3

INT0

Timer B1

Timer A4

Timer A2

UART1 receive

UART0 receive

UART2 receive/ACK2

A-D conversion

DMA1

Priority of peripheral I/O interrupts

(if priority levels are same)

UART 2 bus collision detection

INT5

Timer A0

UART1 transmit

UART0 transmit

UART2 transmit/NACK2

Key input interrupt

DMA0

INT4

Interrupt request level judgment output

to clock generating circuit (Fig.1.8.3)

Low

Processor interrupt priority level (IPL)

Interrupt enable flag (I flag)

Interrupt

request

accepted

Address match

Watchdog timer

DBC

NMI

Reset

Figure 1.9.9. Maskable interrupts priorities (peripheral I/O interrupts)

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INT Interrupt

INT0, INT1, INT3 to INT5 are triggered by the edges of external inputs. The edge polarity of the interrupt is

selected using the polarity select bit in the interrupt control registers, 004416, 004816, 004916, 005D16 and

005E16.

To generate interrupts on both rising and falling edges, set the INTi interrupt polarity switching bit of the

interrupt request cause select register (035F16) to "1". Interrupt on both rising and falling edges will be

generated regardless of the value set in the polarity select bit of the corresponding interrupt control regis-

ter.

Figure 1.9.10 shows the Interrupt request cause select register.

Interrupt request cause select register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

IFSR

Address

035F16

When reset

0016

R

W

Bit symbol

Bit name

Function

IFSR0

INT0 interrupt polarity

switching bit

0 : One edge

1 : Two edges

IFSR1

IFSR2

IFSR3

IFSR4

IFSR5

IFSR6

IFSR7

INT1 interrupt polarity

switching bit

0 : One edge

1 : Two edges

Reserved

INT3 interrupt polarity

switching bit

0 : One edge

1 : Two edges

INT4 interrupt polarity

switching bit

0 : One edge

1 : Two edges

INT5 interrupt polarity

switching bit

0 : One edge

1 : Two edges

Interrupt request cause

select bit

0 : Reserved

1 : INT4 (note)

Interrupt request cause

select bit

0 : Reserved

1 : INT5 (note)

Note: To use INTi (i=4,5) functionality, this bit must be set to a 1.

Figure 1.9.10. Interrupt request cause select register

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NMI Interrupt

If enabled, an NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The

NMI interrupt is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit

5 at address 03F016).

NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using bit 4 of

processor mode register 2. Once enabled, it can only be disabled by a reset signal.

Key Input Interrupt

If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key

input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-

ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to

P107 as A-D input ports. Figure 1.9.11 shows the block diagram of the key input interrupt. Note that if an “L”

level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an

interrupt.

Port P104-P107 pull-up

select bit

Pull-up

transistor

Key input interrupt control register

(address 004D16

)

Port P10

register

7 direction

Port P10

7

direction register

P10

7

/KI

3

2

Port P10

register

6 direction

Pull-up

transistor

Key input interrupt

request

Interrupt control circuit

P10

6

/KI

Pull-up

Port P10

register

5

direction

transistor

P105/KI1

Port P10

register

4

Pull-up

transistor

P104/KI0

Figure 1.9.11. Block diagram of key input interrupt

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Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents

match the program counter value. Four address match interrupts can be set, each of which can be enabled

and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the

interrupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the

value of the program counter (PC) that is saved to the stack area varies depending on the instruction being

executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot

be used for external area.

Figure 1.9.12 shows the address match interrupt-related registers.

Address match interrupt enable register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

AIER

Address

000916

When reset

XXXXXX00

2

Bit symbol

AIER0

Bit name

Function

R W

Address match interrupt 0

enable bit

0 : Interrupt disabled

1 : Interrupt enabled

Address match interrupt 1

enable bit

AIER1

0 : Interrupt disabled

1 : Interrupt enabled

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to

be indeterminated.

Address match interrupt register i (i = 0, 1)

(b19)

b3

(b16)(b15)

b0 b7

(b8)

b0 b7

(b23)

b7

Symbol

RMAD0

RMAD1

Address

001216 to 001016

001616 to 001416

When reset

X0000016

b0

Function

Values that can be set

R W

Address setting register for address match interrupt

0000016 to FFFFF16

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to

be indeterminated.

Figure 1.9.12. Address match interrupt-related registers

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Precautions for Interrupts

(1) Reading address 0000016

• Do not read address 0000016 by software.

When a maskable interrupt is generated, the CPU reads the interrupt information (the interrupt number

and interrupt request level) in the interrupt sequence. The interrupt request bit of this interrupt is written

in address 0000016. Therefore, reading 0000016 may cancel the interrupt or generate an unexpected

one.

(2) Setting the stack pointer

• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt

before setting a value in the stack pointer may cause a runaway program. Be sure to set a value in the

stack pointer before accepting an interrupt.

When using the NMI interrupt, initialize the stack pointer at the beginning of the program. Concerning the

first instruction immediately after reset, the generation of any interrupts, including the NMI interrupt, is

prohibited.

(3) The NMI interrupt

•The NMI interrupt is enabled or disabled in bit4 of the processor mode register 2. It is disabled by

default (the pin is used as P85)after reset. Once enabled, it stays enabled until a reset is applied.

• The NMI interrupt input level can be determined by reading the contents of the P8 register.

• If NMI is enabled, do not attempt to go into stop mode with the NMI input in the “L” state. With the NMI

input in the “L” state, the CM10 is fixed to “0”, therefore, any attempt to go into stop mode is turned

down.

• If NMI is enabled, going into wait mode with the NMI input in the “L” state does not reduce the power

consumption. With the NMI input in the “L” state, the CPU stops but the oscillation is not stop, so

power consumption is not reduced. Having NMI in "L" state when going into a wait mode may also

cause an unpredictable behavior of the program.

• Signal input to the NMI pin require an “L” level of '2 cycles of BCLK + 300ns' or more.

(4) External interrupt

• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0

, INT1, INT3 through INT5 regardless of the CPU operation clock.

Clear the interrupt enable flag to 0

(Disable interrupt)

Set the interrupt priority level to level 0

(Disable INTi interrupt)

Set the polarity select bit

Clear the interrupt request bit to 0

Set the interrupt priority level to level 1 to 7

(Enable the accepting of INTi interrupt request)

Set the interrupt enable flag to 1

(Enable interrupt)

Note: Execute the setting above individually. Don't execute two or

more settings at once(by one instruction).

Figure 1.9.13. Switching condition of INT interrupt request

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• When the polarity of the INT0 , INT1, INT3 through INT5 pins is changed, the interrupt request bit is

sometimes set to “1”. After changing the polarity, set the interrupt request bit to “0”. Figure 1.9.13

shows the procedure for changing the INT interrupt generate factor.

(5) Watchdog timer interrupt

• Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog

timer).

(6) Rewrite the interrupt control register

Example 1:

INT_SWITCH1:

FCLR

I

; Disable interrupts.

AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.

NOP

FSET

; Four NOP instructions are required when using HOLD function.

; Enable interrupts.

I

Example 2:

INT_SWITCH2:

FCLR

I

; Disable interrupts.

AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

; Enable interrupts.

FSET

I

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

; Disable interrupts.

FCLR

I

AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.

POPC FLG ; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted

before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the

interrupt control register is rewritten due to effects of the instruction queue.

• To rewrite the interrupt control register, do so at a point where an interrupt request for that register is not

generated. If there is possibility of the interrupt request occur, disable the interrupt before rewriting the

interrupt control register. Some program examples are described as follow:

When changing an interrupt control register with interrupts enabled, please read the following precau-

tions on instructions used before changing the register.

(1) Changing a non-interrupt request bit

If an interrupt request for an interrupt control register is generated during an instruction to rewrite the

register is being executed, there is a case that the interrupt request bit is not set and consequently the

interrupt is ignored. This will depend on the instruction. If this creates problems, use the instructions

below to change the register.

Instructions : AND, OR, BCLR, BSET

(2) Changing the interrupt request bit

When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit

is not cleared sometimes. This will depend on the instruction. If this creates problems, use the instruc-

tions below to change the register.

Instructions : MOV

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Watchdog Timer

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Watchdog Timer

The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-

mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter

which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer

interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. When the

watchdog timer interrupt is selected, write to the watchdog timer start register after the watchdog timer

interrupt occurs (initialize watchdog timer). Watchdog timer interrupt is selected when bit 2 (PM12) of the

processor mode register 1 (address 000516) is “0” and reset is selected when PM12 is “1”. No value other

than “1” can be written in PM12. Once when reset is selected (PM12=“1”), watchdog timer interrupt cannot

be selected by software.

When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the

prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for

division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watch-

dog timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an

error due to the prescaler.

With XIN chosen for BCLK

prescaler dividing ratio (16 or 128) X watchdog timer count (32768)

Watchdog timer period =

BCLK

With XCIN chosen for BCLK

prescaler dividing ratio (2) X watchdog timer count (32768)

Watchdog timer period =

BCLK

For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the

prescaler, then the watchdog timer's period becomes approximately 32.8 ms.

The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when

a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer

is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started

by writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state,

the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes

or state are released.

Also PM12 is initialized only when reset. The watchdog timer interrupt is selected after reset is cancelled.

Figure 1.10.1 shows the block diagram of the watchdog timer. Figure 1.10.2 shows the watchdog timer-

related registers.

64

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Watchdog Timer

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Prescaler

1/16

CM07 = 0

WDC7 = 0

PM12 = 0

Watchdog timer

interrupt request

CM07 = 0

WDC7 = 1

BCLK

HOLD

1/128

1/2

Watchdog timer

Reset

PM12 = 1

CM07 = 1

Write to the watchdog timer

start register

(address 000E16

Set to

7FFF16

)

RESET

Figure 1.10.1. Block diagram of watchdog timer

Watchdog timer control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

WDC

Address

000F16 00?XXXXX

After reset

0

2

(Note1)

Bit symbol

Bit name

Function

RW

RO

High-order bit of watchdog timer

Cold start / warm start

WDC5

0 : Cold start

discrimination flag (Note 2) 1 : Warm start

RW

Reserved bit

Set to 0

WDC7

Prescaler select bit

0 : Divided by 16

1 : Divided by 128

RW

Note 1: The WDC5 bit is set to 0 immediately after power-on (cold start).

Note 2: The WDC5 bit will always be set to a 1 whenever the WDC SFR is written (regardless of value of WDC5 bit).

Watchdog timer start register

b7

b0

Symbol

WDTS

Address

000E16

When reset

Indeterminate

Function

R W

The watchdog timer is initialized and starts counting after a write instruction to

this register. The watchdog timer value is always initialized to 7FFF16

regardless of whatever value is written.

Figure 1.10.2. Watchdog timer control and start registers

65

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent

to memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a

higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this

account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-

bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.11.1 shows the block diagram

of the DMAC. Table 1.11.1 shows the DMAC specifications. Figures 1.11.2 to 1.11.4 show the registers

used by the DMAC.

DMA0 source pointer SAR0(20)

(addresses 002216 to 002016

DMA0 destination pointer DAR0 (20)

(addresses 002616 to 0024

DMA0 forward address pointer (20) (Note)

)

DMA0 transfer counter reload register TCR0 (16)

DMA1 source pointer SAR1 (20)

(addresses 003216 to 003016)

(addresses 002916, 0028

)

DMA0 transfer counter TCR0 (16)

(addresses 003616 to 003416

)

DMA1 forward address pointer (20) (Note)

DMA1 transfer counter reload register TCR1 (16)

(addresses 003916, 003816

DMA latch high-order bits DMA latch low-order bits

DMA1 transfer counter TCR1 (16)

Data bus low-order bits

Data bus high-order bits

Note: Pointer is incremented by a DMA request.

Figure 1.11.1. Block diagram of DMAC

Either a write to the software DMA request bit or an interrupt request factor are used as a DMA transfer

request signal. The DMA transfer is not affected by the interrupt enable flag (I flag) nor by the interrupt

priority level. The DMA transfer does not affect interrupts.

If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request

signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA

transfer cycle, there can be instances in which the number of transfer requests do not agree with the

number of transfers. For details, see the description of the DMA request bit.

66

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Preliminary Specifications Rev. 0.9

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M16C/26 Group

DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.11.1. DMAC specifications

Item

Specification

No. of channels

2 (cycle steal method)

Transfer memory space

• From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space

• From a fixed address to a fixed address

(Note that DMA-related registers [002016 to 003F16] cannot be ac-

cessed)

Maximum No. of bytes transferred128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors (Note)

Falling edge of INT0 or INT1 or both edge

Timer A0 to timer A4 interrupt requests

Timer B0 to timer B2 interrupt requests

UART0 transfer and reception interrupt requests

UART1 transfer and reception interrupt requests

UART2 transfer and reception interrupt requests

A-D conversion interrupt requests

Software triggers

Channel priority

DMA0 takes precedence if DMA0 and DMA1 requests are

generated simultaneously

Transfer unit

8 bits or 16 bits

Transfer address direction

forward/fixed (forward direction cannot be specified for both source and

destination simultaneously)

Transfer mode

• Single transfer mode

After the transfer counter underflows, the DMA enable bit turns to “0”,

and the DMAC turns inactive

• Repeat transfer mode

After the transfer counter underflows, the value of the transfer counter

reload register is reloaded to the transfer counter.

The DMAC remains active unless a “0” is written to the DMA enable bit.

When an underflow occurs in the transfer counter

DMA interrupt request

generation timing

Active

When the DMA enable bit is set to “1”, the DMAC is active.

When the DMAC is active, data transfer starts every time a DMA

transfer request signal occurs.

Inactive

• When the DMA enable bit is set to “0”, the DMAC is inactive.

• After the transfer counter underflows in single transfer mode

At the time of starting data transfer immediately after turning the DMAC

active, the value of one of source pointer and destination pointer - the one

specified for the forward direction- is reloaded to the forward direction

address pointer, and the value of the transfer counter reload register is

reloaded to the transfer counter.

Writing to register

Registers specified for forward direction transfer are always write enabled.

Registers specified for fixed address transfer are write-enabled when

the DMA enable bit is “0”.

Reading the register

Can be read at any time.

However, when the DMA enable bit is “1”, reading the register set up as the

forward register is the same as reading the value of the forward address pointer.

Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable

flag (I flag) nor by the interrupt priority level.

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMA0 request cause select register

Symbol

DM0SL

Address

03B816

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

Function

Bit symbol

DSEL0

Bit name

R

W

b3 b2 b1 b0

DMA request cause

select bit

0 0 0 0 : Falling edge of INT0 pin

0 0 0 1 : Software trigger

0 0 1 0 : Timer A0

0 0 1 1 : Timer A1

0 1 0 0 : Timer A2

0 1 0 1 : Timer A3

0 1 1 0 : Timer A4 (DMS=0)

DSEL1

DSEL2

DSEL3

/two edges of INT0 pin (DMS=1)

0 1 1 1 : Timer B0 (DMS=0)

1 0 0 0 : Timer B1 (DMS=0)

1 0 0 1 : Timer B2 (DMS=0)

1 0 1 0 : UART0 transmit

1 0 1 1 : UART0 receive

1 1 0 0 : UART2 transmit

1 1 0 1 : UART2 receive

1 1 1 0 : A-D conversion

1 1 1 1 : UART1 transmit

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

DMA request cause

expansion select bit

0 : Normal

1 : Expanded cause

DMS

DSR

If software trigger is selected, a

DMA request is generated by

setting this bit to 1 (When read,

the value of this bit is always 0 )

Software DMA

request bit

Figure 1.11.2. DMAC register (1)

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMA1 request cause select register

Symbol

DM1SL

Address

03BA16

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Function

Bit symbol

DSEL0

R

W

b3 b2 b1 b0

DMA request cause

select bit

0 0 0 0 : Falling edge of INT1 pin

0 0 0 1 : Software trigger

0 0 1 0 : Timer A0

0 0 1 1 : Timer A1

0 1 0 0 : Timer A2

DSEL1

DSEL2

DSEL3

0 1 0 1 : Timer A3 (DMS=0)

0 1 1 0 : Timer A4 (DMS=0)

0 1 1 1 : Timer B0 (DMS=0)

/two edges of INT1 (DMS=1)

1 0 0 0 : Timer B1

1 0 0 1 : Timer B2

1 0 1 0 : UART0 transmit

1 0 1 1 : UART0 receive

1 1 0 0 : UART2 transmit

1 1 0 1 : UART2 receive/ACK2

1 1 1 0 : A-D conversion

1 1 1 1 : UART1 receive

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

0 : Normal

1 : Expanded cause

DMA request cause

expansion select bit

DMS

DSR

Software DMA

request bit

If software trigger is selected, a

DMA request is generated by

setting this bit to 1 (When read,

the value of this bit is always 0 )

DMAi control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

DMiCON(i=0,1)

Address

002C16, 003C16

When reset

00000X00

2

Bit symbol

DMBIT

Bit name

F unction

R

W

Transfer unit bit select bit 0 : 16 bits

1 : 8 bits

Repeat transfer mode

select bit

0 : Single transfer

1 : Repeat transfer

DMASL

DMAS

DMAE

0 : DMA not requested

1 : DMA requested

DMA request bit (Note 1)

DMA enable bit

(Note 2)

0 : Disabled

1 : Enabled

Source address direction

select bit (Note 3)

0 : Fixed

1 : Forward

DSD

DAD

Destination address

direction select bit (Note 3)

0 : Fixed

1 : Forward

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Note 1: DMA request can be cleared by resetting the bit.

Note 2: This bit can only be set to 0 .

Note 3: Source address direction select bit and destination address direction select bit

cannot be set to 1 simultaneously.

Figure 1.11.3. DMAC register (2)

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAi source pointer (i = 0, 1)

(b19)

b3

(b16)(b15)

b0 b7

(b8)

b0 b7

(b23)

b7

b0

Symbol

SAR0

SAR1

Address

002216 to 002016

003216 to 003016

When reset

Indeterminate

Transfer address

specification

Function

R W

Source pointer

Stores the source address

0000016 to FFFFF16

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

DMAi destination pointer (i = 0, 1)

(b19)

b3

(b16)(b15)

b0 b7

(b8)

b0 b7

(b23)

b7

b0

Symbol

DAR0

DAR1

Address

002616 to 002416

003616 to 003416

When reset

Indeterminate

Transfer address

specification

Function

R W

Destination pointer

Stores the destination address

0000016 to FFFFF16

Nothing is assigned.

In an attempt to write to these bits, write 0.

DMAi transfer counter (i = 0, 1)

(b15)

b7

(b8)

b0 b7

b0

Symbol

TCR0

TCR1

Address

002916, 002816

003916, 003816

When reset

Indeterminate

Transfer count

specification

Function

R W

Transfer counter

Set a value one less than the transfer count

000016 to FFFF16

Figure 1.11.4. DMAC register (3)

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) Transfer cycle

The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area

(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination

write). The number of read and write bus cycles depends on the source and destination addresses. Also,

the bus cycle itself is longer when software waits are inserted.

(a) Effect of source and destination addresses

When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd

addresses, there are one more source read cycle and destination write cycle than when the source

and destination both start at even addresses.

(b) Effect of software wait

When the SFR area or a memory area with a software wait is accessed, the number of cycles is

increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.

Figure 1.11.5 shows the example of the transfer cycles for a source read. For convenience, the destina-

tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.

In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the

transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-

tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure

1.11.5, if 16-bit data is being transferred from an odd source address to an odd destination address, two

bus cycles are required for both the source read cycle and the destination write cycle.

(2) DMAC transfer cycles

Any combination of even or odd transfer read and write addresses is possible. Table 1.11.2 shows the

number of DMAC transfer cycles.

The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) 8-bit transfers

16-bit transfers and the source address is even.

BCLK

Address

bus

Dummy

cycle

CPU use

Source

Destination

CPU use

RD signal

WR signal

Data

bus

Dummy

cycle

CPU use

Source

Destination

CPU use

(2) 16-bit transfers and the source address is odd

BCLK

Address

bus

Dummy

cycle

CPU use

Source

Source + 1 Destination

CPU use

RD signal

WR signal

Data

bus

Dummy

cycle

CPU use

Source + 1

Source

CPU use

Destination

(3) One wait is inserted into the source read under the conditions in (1)

BCLK

Address

bus

Dummy

cycle

CPU use

Source

Destination

CPU use

RD signal

WR signal

Data

bus

Dummy

cycle

CPU use

Source

Destination

CPU use

(4) One wait is inserted into the source read under the conditions in (2)

BCLK

Address

bus

Dummy

cycle

CPU use

Source

Source + 1

Destination

CPU use

RD signal

WR signal

Data

bus

Dummy

cycle

CPU use

Source

Source + 1

Destination

CPU use

Note: The same timing changes occur with the respective conditions at the destination as at the source

Figure 1.11.5. Example of the transfer cycles for a source read

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DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.11.2. No. of DMAC transfer cycles

Single Chip Mode

Transfer Unit

8-bit transfers

(DMBIT="1")

16-bit transfers

(DMBIT="0")

Bus Width

16 bit

Access Address No. of Read Cycles

No. of Write Cycles

Even

Odd

1

2

1

2

16 bit

Even

Odd

Coefficient j, k

Internal Memory

Internal ROM/RAM

With Wait

Internal ROM/RAM

No Wait

1

SFR Area

3

2

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M16C/26 Group

DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMA enable bit

Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following opera-

tions at the time data transfer starts immediately after DMAC is turned active.

(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the

forward direction - to the forward direction address pointer.

(2) Reloads the value of the transfer counter reload register to the transfer counter.

Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given

above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA enable

bit.

DMA request bit

The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of

DMA request factors for each channel.

DMA request factors include the following.

* Factors effected by using the interrupt request signals from the built-in peripheral functions and soft-

ware DMA factors (internal factors) effected by a program.

* External factors effected by utilizing the input from external interrupt signals.

For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.

The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC's state (regard-

less of whether the DMA enable bit is set to “1” or “0”). It turns to “0” immediately before data transfer starts.

In addition, it can be set to “0” by use of a program, but cannot be set to “1”.

There can be instances in which a change in DMA request factor selection bit causes the DMA request bit to

turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit is changed.

The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately

before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the

DMA request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the

DMAC is active, read the DMA enable bit.

Here follows the timing of changes in the DMA request bit.

(1) Internal factors

Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to “1” due

to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to

turn to “1” due to several factors.

Turning the DMA request bit to “0” due to an internal factor is timed to be effected immediately before the

transfer starts.

(2) External factors

An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on

which DMAC channel is used).

Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from

these pins to become the DMA transfer request signals.

The timing for the DMA request bit to turn to “1” when an external factor is selected synchronizes with the

signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes

with the trailing edge of the input signal to each INTi pin, for example).

With an external factor selected, the DMA request bit is timed to turn to “0” immediately before data

transfer starts similarly to the state in which an internal factor is selected.

74

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M16C/26 Group

DMAC

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(3) The priorities of channels and DMA transfer timing

If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from

the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently

turn to “1”. If the channels are active at that moment, DMA0 is given a high priority to start data transfer.

When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus

access, then DMA1 starts data transfer and gives the bus right to the CPU.

An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer

request signals due to external factors concurrently occur.

Figure 1.11.6 shows the DMA transfer effected by external factors.

An example in which DMA transmission is carried out in minimum

cycles at the time when DMA transmission request signals due to

external factors concurrently occur.

BCLK

DMA0

Obtainment

of the bus

right

DMA1

CPU

INT0

DMA0

request bit

INT1

DMA1

request bit

Figure 1.11.6. An example of DMA transfer effected by external factors

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Timers

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers

There are eight 16-bit timers. These timers can be classified by function into timers A (five) and timers B

(three). All these timers function independently. Figures 1.12.1 and 1.12.2 show the block diagram of

timers.

f

2

PCLK0 bit = "0"

Clock prescaler

1/2

1/8

f

1 or f2

f

1

fC32

1/32

XCIN

• XIN

PCLK0 bit = "1"

• Ring oscillator

clock

Reset

f

8

Clock prescaler reset flag (bit 7

at address 038116) set to "1"

f1 or f2

f

32

1/4

f8 f32 fC32

· Timer mode

· One-shot timer mode

· PWM mode

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

Timer A0

Noise

filter

TA0IN

TA1IN

TA2IN

TA3IN

TA4IN

· Event counter mode

· Timer mode

· One-shot timer mode

· PWM mode

Timer A1

Timer A2

Timer A3

Timer A4

Noise

filter

· Event counter mode

· Timer mode

· One-shot timer mode

· PWM mode

Noise

filter

· Event counter mode

· Timer mode

· One-shot timer mode

· PWM mode

Noise

filter

· Event counter mode

· Timer mode

· One-shot timer mode

· PWM mode

Noise

filter

·

Event counter mode

Timer B2 overflow

Figure 1.12.1. Timer A block diagram

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Timers

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

f

2

PCLK0 bit = "0"

Clock prescaler

1/2

1/8

f

1 or f2

f1

fC32

• XIN

1/32

Reset

XCIN

PCLK0 bit = "1"

• Ring oscillator

clock

f

8

Clock prescaler reset flag (bit 7

at address 038116) set to "1"

f

32

1/4

f1 or f2

f8 f32 fC32

Timer A

ÄTimer mode

ÄPulse width measuring mode

Timer B0 interrupt

Noise

filter

Timer B0

TB 0IN

ÄEvent counter mode

ÄTimer mode

ÄPulse width measuring mode

Timer B1 interrupt

Timer B2 interrupt

Noise

filter

1

IN

TB

Timer B1

ÄEvent counter mode

ÄTimer mode

ÄPulse width measuring mode

Noise

filter

2

IN

Timer B2

ÄEvent counter mode

Figure 1.12.2. Timer B block diagram

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Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Figure 1.12.3 shows the block diagram of timer A. Figures 1.12.4 to 1.12.6 show the timer A-related

registers.

Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode

register (i = 0 to 4) bits 0 and 1 to choose the desired mode.

Timer A has the four operation modes listed as follows:

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external source or a timer over flow.

• One-shot timer mode: The timer stops counting when the count reaches “000016”.

• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.

Data bus high-order bits

Clock source

selection

Data bus low-order bits

ÄTimer

ÄOne shot

ÄPWM

f1

or f

2

Low-order

8 bits

High-order

8 bits

Clock selection

f

8

ÄTimer

(gate function)

f32

Reload register (16)

fC32

ÄEvent counter

Clock selection

Counter (16)

Polarity

selection

Up count/down count

TAiIN

(i = 0 to 4)

Always down count except

in event counter mode

Count start flag

(Address 038016

)

TAi

Addresses

TAj

TAk

Timer A0 0387¹⁶038616

Timer A1 0389¹⁶038816

Timer A4 Timer A1

Timer A0 Timer A2

TB2 overflow

TAj overflow

To external

trigger circuit

Timer A2 038B¹⁶038A16 Timer A1 Timer A3

Timer A3 038D¹⁶038C16 Timer A2 Timer A4

Timer A4 038F¹⁶038E16 Timer A3 Timer A0

Down count

(j = i 1. Note, however, that j = 4 when i = 0)

Up/down flag

(Address 038416

TAk overflow

(k = i + 1. Note, however, that k = 0 when i = 4)

)

Pulse output

TAiOUT

(i = 0 to 4)

Toggle flip-flop

Figure 1.12.3. Block diagram of timer A

Timer Ai mode register

Symbol

Address

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

TAiMR(i=0 to 4) 039616 to 039A16

R W

Bit symbol

TMOD0

Bit name

Function

b1 b0

Operation mode select bit

0 0 : Timer mode

0 1 : Event counter mode

1 0 : One-shot timer mode

1 1 : Pulse width modulation

(PWM) mode

TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Function varies with each operation mode

Count source select bit

(Function varies with each operation mode)

Figure 1.12.4. Timer A-related registers (1)

78

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer Ai register (Note 1)

Symbol

TA0

TA1

TA2

TA3

Address

When reset

Indeterminate

(b15)

(b8)

b0 b7

038716,038616

038916,038816

038B16,038A16

038D16,038C16

038F16,038E16

b7

b0

TA4

Values that can be set

R W

Function

·

Timer mode

Counts an internal count source

000016 to FFFF16

Event counter mode

Counts pulses from an external source or timer overflow

000016 to FFFF16

·

One-shot timer mode

Counts a one shot width

000016 to FFFF16

(Note 2,6)

·

Pulse width modulation mode (16-bit PWM)

Functions as a 16-bit pulse width modulator

000016 to FFFE16

(Note 3,4,6)

0016 to FE16

Pulse width modulation mode (8-bit PWM)

Timer low-order address functions as an 8-bit

prescaler and high-order address functions as an 8-bit

pulse width modulator

(High-order address)

0016 to FF16

(Low-order address)

(Note 3,5,6)

Note 1: Read and write data in 16-bit units.

Note 2: When the timer Ai register is set to 000016 , the counter does not

operate and the timer Ai interrupt request is not generated. When

the pulse is set to output, the pulse does not output from the TAiOUT

pin.

Note 3: When the timer Ai register is set to 000016 , the pulse width

modulator does not operate and the output level of the TAiOUT pin

remains L level, therefore the timer Ai interrupt request is not

generated. This also occurs in the 8-bit pulse width modulator mode

when the significant 8 high-order bits in the timer Ai register are set

to 0016

.

Note 4: When the set value =n, PWM period and "H" width of PWM pule are

as follows:

16

PWM perild: (2 - 1)/ fi, "H" width of PWM pulse: n / fi

Note 5: When the set value of upper-address=n and lower-address=m,

PWM period and "H" width of PWM pule are as follows:

8

PWM perild: (2 - 1)x(m+1)/ fi, "H" width of PWM pulse: (m+1)n / fi

Note 6: Use MOV instruction to write to this register.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

TABSR

Address

038016

When reset

0016

Bit symbol

TA0S

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

Bit name

Function

0 : Stops counting

R W

Timer A0 count start flag

Timer A1 count start flag

Timer A2 count start flag

Timer A3 count start flag

Timer A4 count start flag

Timer B0 count start flag

Timer B1 count start flag

Timer B2 count start flag

1 : Starts counting

Up/down flag (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UDF

Address

038416

When reset

0016

R W

Bit symbol

TA0UD

Bit name

F

unction

Timer A0 up/down flag

0 : Down count

1 : Up count

TA1UD

TA2UD

TA3UD

TA4UD

Timer A1 up/down flag

Timer A2 up/down flag

Timer A3 up/down flag

Timer A4 up/down flag

This specification becomes valid

when the up/down flag content is

selected for up/down switching

cause

0 : two-phase pulse signal

processing disabled

1 : two-phase pulse signal

processing enabled (Note 2)

TA2P

TA3P

TA4P

Timer A2 two-phase pulse

signal processing select bit

Timer A3 two-phase pulse

signal processing select bit

When not using the two-phase

pulse signal processing function,

Timer A4 two-phase pulse

signal processing select bit

set the select bit to

0

Note 1: Use MOV instruction to write to this register.

Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to 0 .

Figure 1.12.5. Timer A-related registers (2)

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

One-shot start flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ONSF

Address

038216

When reset

0016

0

R W

Bit symbol

Bit name

Function

Timer A0 one-shot start flag

Timer A1 one-shot start flag

Timer A2 one-shot start flag

Timer A3 one-shot start flag

Timer A4 one-shot start flag

TA0OS

TA1OS

TA2OS

TA3OS

TA4OS

1 : Timer start

When read, the value is 0

Reserved bit

Must always be set to 0

b7 b6

TA0TGL

TA0TGH

Timer A0 event/trigger

select bit

0 0 : Input on TA0IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA4 overflow is selected

1 1 : TA1 overflow is selected

Note: Set the corresponding port direction register to 0 .

Trigger select register

Symbol

TRGSR

Address

038316

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

Bit symbol

TA1TGL

Bit name

Timer A1 event/trigger

select bit

Function

R W

b1 b0

0 0 : Input on TA1IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA0 overflow is selected

1 1 : TA2 overflow is selected

TA1TGH

TA2TGL

b3 b2

Timer A2 event/trigger

select bit

0 0 : Input on TA2IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA1 overflow is selected

1 1 : TA3 overflow is selected

TA2TGH

TA3TGL

TA3TGH

b5 b4

Timer A3 event/trigger

select bit

0 0 : Input on TA3IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA2 overflow is selected

1 1 : TA4 overflow is selected

b7 b6

Timer A4 event/trigger

select bit

TA4TGL

TA4TGH

0 0 : Input on TA4IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA3 overflow is selected

1 1 : TA0 overflow is selected

Note: Set the corresponding port direction register to 0 .

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

CPSRF

Address

038116

When reset

0XXXXXXX

2

Bit symbol

Bit name

Function

R W

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be

indeterminate.

0 : No effect

1 : Prescaler is reset

CPSR

Clock prescaler reset flag

(When read, the value is 0 )

Figure 1.12.6. Timer A-related registers (3)

80

Renesas Technology Corp.

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.12.1.) Figure 1.12.7

shows the timer Ai mode register in timer mode.

Table 1.12.1. Specifications of timer mode

Item

Count source

Count operation

Specification

f1, f2, f8, f32, fC32

• Down count

•

When the timer underflows, it reloads the reload register contents before continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count stop condition

Count start flag is set (= 1)

Count start flag is reset (= 0)

Interrupt request generation timing When the timer underflows

TAiIN pin function

TAiOUT pin function

Read from timer

Write to timer

Programmable I/O port or gate input

Programmable I/O port or pulse output

Count value can be read out by reading timer Ai register

• When counting stopped

When a value is written to timer Ai register, it is written to both reload register and counter

• When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

• Gate function

Select function

Counting can be started and stopped by the TAiIN pin’s input signal

• Pulse output function

Each time the timer underflows, the TAiOUT pin’s polarity is reversed

Timer Ai mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Address

When reset

0016

TAiMR(i=0 to 4) 039616 to 039A16

0

0 0

Bit symbol

Bit name

Function

R W

b1 b0

Operation mode

select bit

TMOD0

TMOD1

MR0

0 0 : Timer mode

Pulse output function

select bit

0 : Pulse is not output

(TAiOUT pin is a normal port pin)

1 : Pulse is output (Note 1)

(TAiOUT pin is a pulse output pin)

b4 b3

Gate function select bit

MR1

MR2

0 X (Note 2): Gate function not available

(TAiIN pin is a normal port pin)

1 0 : Timer counts only when TAiIN pin is

held L (Note 3)

1 1 : Timer counts only when TAiIN pin is

held H (Note 3)

MR3

0 (Must always be 0 in timer mode)

b7 b6

TCK0

Count source select bit

0 0 : f

1

8

or f2

0 1 : f

TCK1

1 0 : f32

1 1 : fC32

Note 1: The settings of the corresponding port register and port direction register

are invalid.

Note 2: The bit can be 0 or 1 .

Note 3: Set the corresponding port direction register to 0 .

Figure 1.12.7. Timer Ai mode register in timer mode

81

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Event Counter Mode

In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can

count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-

phase external signal. Table 1.12.2 lists timer specifications when counting a single-phase external

signal. Figure 1.12.8 shows the timer Ai mode register in event counter mode.

Table 1.12.3 lists timer specifications when counting a two-phase external signal. Figure 1.12.9 shows

the timer Ai mode register in event counter mode.

Table 1.12.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)

Item

Specification

Count source

•

External signals input to TAiIN pin (effective edge can be selected by software)

• TB2 overflow, TAj overflow

Count operation

• Up count or down count can be selected by external signal or software

• When the timer overflows or underflows, it reloads the reload register con

tents before continuing counting (Note)

1/ (FFFF16 - n + 1) for up count

Divide ratio

1/ (n + 1) for down count

Count start flag is set (= 1)

Count start flag is reset (= 0)

n : Set value

Count start condition

Count stop condition

Interrupt request generation timing The timer overflows or underflows

TAiIN pin function

TAiOUT pin function

Read from timer

Write to timer

Programmable I/O port or count source input

Programmable I/O port, pulse output, or up/down count select input

Count value can be read out by reading timer Ai register

• When counting stopped

When a value is written to timer Ai register, it is written to both reload register and counter

• When counting in progress

When a value is written to timer Ai register, it is written to only reload

(Transferred to counter at next reload time)

register

Select function

• Free-run count function

Even when the timer overflows or underflows, the reload register content is not reloaded to it

• Pulse output function

Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed

Note: This does not apply when the free-run function is selected.

Timer Ai mode register

(When not using two-phase pulse signal processing)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Address

When reset

0016

0

0 1

TAiMR(i = 0 to 4) 039616 to 039A16

Bit symbol

Bit name

Function

R W

b1 b0

TMOD0

TMOD1

MR0

Operation mode select bit

0 1 : Event counter mode (Note 1)

0 : Pulse is not output

Pulse output function

select bit

(TAiOUT pin is a normal port pin)

1 : Pulse is output (Note 2)

(TAiOUT pin is a pulse output pin)

MR1

MR2

Count polarity

select bit (Note 3)

0 : Counts external signal's falling edge

1 : Counts external signal's rising edge

Up/down switching

cause select bit

0 : Up/down flag's content

1 : TAiOUT pin's input signal (Note 4)

MR3

0 (Must always be

0 in event counter mode)

TCK0

Count operation type

select bit

0 : Reload type

1 : Free-run type

TCK1

Invalid when not using two-phase pulse signal processing

Can be or

0

1

Note 1: In event counter mode, the count source is selected by the event / trigger select bit

(addresses 038216 and 038316).

Note 2: The settings of the corresponding port register and port direction register are invalid.

Note 3: Valid only when counting an external signal.

to

L signal is input the TAiOUT pin, the downcount is activated. When H ,

Note 4: When an

the upcount is activated. Set the corresponding port direction register to 0 .

Figure 1.12.8. Timer Ai mode register in event counter mode

82

Renesas Technology Corp.

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.12.3. Timer specifications in event counter mode

(when processing two-phase pulse signal with timers A2, A3, and A4)

Item Specification

Count source

• Two-phase pulse signals input to TAiIN or TAiOUT pin

• Up count or down count can be selected by two-phase pulse signal

• When the timer overflows or underflows, the reload register content is

reloaded and the timer starts over again (Note 1)

Count operation

Divide ratio

1/ (FFFF16 - n + 1) for up count

1/ (n + 1) for down count

Count start flag is set (= 1)

Count start flag is reset (= 0)

n : Set value

Count start condition

Count stop condition

Interrupt request generation timing Timer overflows or underflows

TAiIN pin function

Two-phase pulse input (Set the TAiIN pin correspondent port direction register to “0”.)

Two-phase pulse input

TAiOUT pin function

(Set the TAiOUT pin correspondent port direction register to “0”.)

Count value can be read out by reading timer A2, A3, or A4 register

• When counting stopped

Read from timer

Write to timer

When a value is written to timer A2, A3, or A4 register, it is written to both

reload register and counter

• When counting in progress

When a value is written to timer A2, A3, or A4 register, it is written to only

reload register. (Transferred to counter at next reload time.)

Select function (Note 2) • Normal processing operation (timer A2 and timer A3)

The timer counts up rising edges or counts down falling edges on the

TAiIN pin when input signal on the TAiOUT pin is “H”.

TAiOUT

TAiIN

(i=2,3)

Up

count

Up

count

Up

Down

count

Down

count

count count

• Multiply-by-4 processing operation (timer A3 and timer A4)

If the phase relationship is such that the TAiIN pin goes “H” when the input

signal on the TAiOUT pin is “H”, the timer counts up rising and falling edges

on the TAiOUT and TAiIN pins. If the phase relationship is such that the

TAiIN pin goes “L” when the input signal on the TAiOUT pin is “H”, the timer

counts down rising and falling edges on the TAiOUT and TAiIN pins.

TAiOUT

Count down all edges

Count up all edges

TAiIN

(i=3,4)

Note 1: This does not apply when the free-run function is selected.

Note 2: Timer A3 alone can be selected. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to

multiply-by-4 processing operation.

83

Renesas Technology Corp.

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Specifications in this manual are tentative and subject to change.

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Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer Ai mode register

(When using two-phase pulse signal processing)

Symbol

Address

When reset

0016

b6 b5 b4 b3 b2 b1 b0

TAiMR(i = 2 to 4) 039816 to 039A16

0

1 0 0 0 1

Bit name

Function

0 1 : Event counter mode

R W

b1 b0

TMOD0

Operation mode select bit

TMOD1

0 (Must always be 0 when using two-phase pulse signal

processing)

MR0

0 (Must always be 0 when using two-phase pulse signal

processing)

MR1

MR2

1 (Must always be 1 when using two-phase pulse signal

processing)

0 (Must always be 0 when using two-phase pulse signal

processing)

MR3

Count operation type

select bit

0 : Reload type

1 : Free-run type

TCK0

Two-phase pulse

processing operation

select bit (Note 1)(Note 2)

TCK1

0 : Normal processing operation

1 : Multiply-by-4 processing operation

Note 1: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing

operation, and timer A4 is fixed to multiply-by-4 processing operation.

Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse

signal processing operation select bit (address 038416) is set to "1". Also, always be

sure to set the event/trigger select bit (addresses 038216 and 038316) to '00

finally, set the port direction bits for TAiIN and TAiOUT to "0" (input mode).

2'. And

Figure 1.12.9. Timer Ai mode register in event counter mode

84

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(3) One-shot timer mode

In this mode, the timer operates only once. (See Table 1.12.4.) When a trigger occurs, the timer starts

up and continues operating for a given period. Figure 1.12.12 shows the timer Ai mode register in

one-shot timer mode.

Table 1.12.4. Timer specifications in one-shot timer mode

Item

Count source

Count operation

Specification

f1, f2, f8, f32, fC32

• The timer counts down

• When the count reaches 000016, the timer stops counting after reloading a new count

• If a trigger occurs when counting, the timer reloads a new count and restarts counting

Divide ratio

1/n

n : Set value

Count start condition

• An external trigger is input

• The timer overflows

• The one-shot start flag is set (= 1)

• A new count is reloaded after the count has reached 000016

• The count start flag is reset (= 0)

Count stop condition

Interrupt request generation timing The count reaches 000016

TAiIN pin function

TAiOUT pin function

Read from timer

Write to timer

Programmable I/O port or trigger input

Programmable I/O port or pulse output

When timer Ai register is read, it indicates an indeterminate value

• When counting stopped

When a value is written to timer Ai register, it is written to both reload

register and counter

• When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

Timer Ai mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Address

When reset

0016

TAiMR(i = 0 to 4) 039616 to 039A16

0

1 0

Bit symbol

Bit name

R W

Function

b1 b0

TMOD0

TMOD1

MR0

Operation mode select bit

1 0 : One-shot timer mode

Pulse output function

select bit

0 : Pulse is not output

(TAiOUT pin is a normal port pin)

1 : Pulse is output (Note 1)

(TAiOUT pin is a pulse output pin)

MR1

MR2

0 : Falling edge of TAiIN pin's input signal (Note 3)

1 : Rising edge of TAiIN pin's input signal (Note 3)

External trigger select

bit (Note 2)

0 : One-shot start flag is valid

1 : Selected by event/trigger select

bits

Trigger select bit

MR3

0 (Must always be 0 in one-shot timer mode)

b7 b6

TCK0

Count source select bit

0 0 : f

0 1 : f

1 0 : f32

1 or f2

8

TCK1

1 1 : fC32

Note 1: The settings of the corresponding port register and port direction register are invalid.

Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit

(addresses 038216 and 038316). If timer overflow is selected, this bit can be 1 or 0 .

Note 3: Set the corresponding port direction register to 0 .

Figure 1.12.12. Timer Ai mode register in one-shot timer mode

85

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(4) Pulse width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession. (See Table 1.12.5.) In this mode, the

counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.12.13

shows the timer Ai mode register in pulse width modulation mode. Figure 1.12.14 shows the example of

how a 16-bit pulse width modulator operates. Figure 1.12.15 shows the example of how an 8-bit pulse width

modulator operates.

Table 1.12.5. Timer specifications in pulse width modulation mode

Item

Count source

Count operation

Specification

f1, f2, f8, f32, fC32

• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

The timer reloads a new count at a rising edge of PWM pulse and continues counting

•

• The timer is not affected by a trigger that occurs when counting

High level width n / fi n : Set value

• Cycle time(2 -1) / fi fixed

16-bit PWM

16

8-bit PWM

•

High level width

Cycle time (2

n

(m+1) / fi n : values set to timer Ai register’s high-order address

(m+1) / fi m : values set to timer Ai register’s low-order address

8

-

1)

Count start condition

• External trigger is input

• The timer overflows

• The count start flag is set (= 1)

• The count start flag is reset (= 0)

Count stop condition

Interrupt request generation timing PWM pulse goes “L”

TAiIN pin function

TAiOUT pin function

Read from timer

Write to timer

Programmable I/O port or trigger input

Pulse output

When timer Ai register is read, it indicates an indeterminate value

• When counting stopped

When a value is written to timer Ai register, it is written to both reload

register and counter

• When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

Timer Ai mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Address

When reset

0016

1

TAiMR(i=0 to 4) 039616 to 039A16

R W

Bit symbol

Bit name

Function

b1 b0

TMOD0

TMOD1

Operation mode

select bit

1 1 : PWM mode

MR0

MR1

1 (Must always be 1 in PWM mode)

External trigger select

bit (Note 1)

0: Falling edge of TAiIN pin's input signal (Note 2)

1: Rising edge of TAiIN pin's input signal (Note 2)

MR2

MR3

0: Count start flag is valid

1: Selected by event/trigger select bits

Trigger select bit

0: Functions as a 16-bit pulse width modulator

1: Functions as an 8-bit pulse width modulator

16/8-bit PWM mode

select bit

b7 b6

Count source select bit

TCK0

TCK1

0 0 : f

0 1 : f

1 0 : f32

1 1 : fC32

1

8

or f2

Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit

(addresses 038216 and 038316). If timer overflow is selected, this bit can be 1 or 0 .

Note 2: Set the corresponding port direction register to 0 .

Figure 1.12.13. Timer Ai mode register in pulse width modulation mode

86

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

development

Timer A

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Condition : Reload register = 000316, when external trigger

(rising edge of TAiIN pin input signal) is selected

1 / fi X

(2¹⁶1)

Count source

H

L

TAiIN pin

input signal

Trigger is not generated by this signal

1 / f

i

X n

H

L

PWM pulse output

from TAiOUT pin

1

0

Timer Ai interrupt

request bit

fi

: Frequency of count source

(f , f , f , f32, fC32

1

2

8

)

Cleared to 0 when interrupt request is accepted, or cleared by software

Note: n = 000016 to FFFE16

.

Figure 1.12.14. Example of how a 16-bit pulse width modulator operates

Condition : Reload register high-order 8 bits = 0216

Reload register low-order 8 bits = 0216

External trigger (falling edge of TAiIN pin input signal) is selected

1 / fi

X (m + 1) X (2⁸1)

Count source (Note1)

TAiIN pin input signal

H

L

1 / fi X (m + 1)

H

L

Underflow signal of

8-bit prescaler (Note2)

1 / fi X (m + 1) X n

H

L

PWM pulse output

from TAiOUT pin

1

0

Timer Ai interrupt

request bit

fi

: Frequency of count source

(f , f , f , f32, fC32

Cleared to 0 when interrupt request is accepted, or cleaerd by software

1

2

8

)

Note 1: The 8-bit prescaler counts the count source.

Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.

Note 3: m = 0016 to FF16; n = 0016 to FE16

.

Figure 1.12.15. Example of how an 8-bit pulse width modulator operates

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Timer B

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Figure 1.13.16 shows the block diagram of timer B. Figures 1.13.17 and 1.13.18 show the timer B-related

registers.

Use the timer Bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode.

Timer B has three operation modes listed as follows:

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external source or a timer overflow.

• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or

pulse width.

Data bus high-order bits

Data bus low-order bits

Clock source selection

High-order 8 bits

Low-order 8 bits

f1 or f2

Timer

Reload register (16)

Pulse period/pulse width measurement

f8

Clock selection

f32

fC32

Counter (16)

Event counter

Count start flag

(address 038016

Polarity switching

and edge pulse

TBi^IN

(i = 0 to 2)

)

Counter reset circuit

Can be selected in only

event counter mode

TBi

Address

TBj

TBj overflow

( j = i 1. Note, however,

j = 2 when i = 0)

Timer B0 0391¹⁶039016 Timer B2

Timer B1 0393¹⁶039216 Timer B0

Timer B2 0395¹⁶039416 Timer B1

Figure 1.13.16. Block diagram of timer B

Timer Bi mode register

Symbol

Address

When reset

00XX00002

b7 b6 b5 b4 b3 b2 b1 b0

TBiMR(i = 0 to 2) 039B16 to 039D16

R

W

Bit symbol

TMOD0

Function

Bit name

b1 b0

Operation mode select bit

0 0 : Timer mode

0 1 : Event counter mode

1 0 : Pulse period/pulse width

measurement mode

TMOD1

1 1 : Must not be set.

MR0

MR1

MR2

Function varies with each operation mode

(Note 1)

(Note 2)

MR3

TCK0

TCK1

Count source select bit

(Function varies with each operation mode)

Note 1: Timer B0.

Note 2: Timer B1, timer B2.

Figure 1.13.17. Timer B-related registers (1)

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Timer B

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer Bi register (Note)

(b15)

b7

(b8)

b0 b7

b0

Symbol

TB0

TB1

Address

When reset

039116, 039016 Indeterminate

039316, 039216 Indeterminate

039516, 039416 Indeterminate

TB2

Values that can be set

000016 to FFFF16

Function

R W

ÄTimer mode

Counts the timer's period

ÄEvent counter mode

000016 to FFFF16

Counts external pulses input or a timer overflow

ÄPulse period / pulse width measurement mode

Measures a pulse period or width

Note: Read and write data in 16-bit units.

Count start flag

Symbol

TABSR

Address

038016

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

R W

Bit symbol

TA0S

Bit name

Function

Timer A0 count start flag

Timer A1 count start flag

Timer A2 count start flag

Timer A3 count start flag

Timer A4 count start flag

Timer B0 count start flag

Timer B1 count start flag

Timer B2 count start flag

0 : Stops counting

1 : Starts counting

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

Clock prescaler reset flag

Symbol

CPSRF

Address

038116

When reset

0XXXXXXX2

b7 b6 b5 b4 b3 b2 b1 b0

Bit symbol

Bit name

Function

R W

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns

out to be indeterminate.

0 : No effect

1 : Prescaler is reset

(When read, the value is 0 )

CPSR

Clock prescaler reset flag

Figure 1.13.18. Timer B-related registers (2)

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Timer B

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.13.6.) Figure 1.13.19

shows the timer Bi mode register in timer mode.

Table 1.13.6. Timer specifications in timer mode

Item

Count source

Count operation

Specification

f1, f8, f32, fC32

• Counts down

• When the timer underflows, it reloads the reload register contents before

continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count stop condition

Count start flag is set (= 1)

Count start flag is reset (= 0)

Interrupt request generation timing The timer underflows

TBiIN pin function

Read from timer

Write to timer

Programmable I/O port

Count value is read out by reading timer Bi register

• When counting stopped

When a value is written to timer Bi register, it is written to both reload register

and counter

• When counting in progress

When a value is written to timer Bi register, it is written to only reload register

(Transferred to counter at next reload time)

Timer Bi mode register

Symbol

Address

When reset

00XX0000

b7 b6 b5 b4 b3 b2 b1 b0

TBiMR(i=0 to 2) 039B16 to 039D16

2

0

Bit symbol

R

W

Bit name

Function

0 0 : Timer mode

b1 b0

TMOD0

TMOD1

MR0

Operation mode select bit

Invalid in timer mode

Can be 0 or 1

MR1

MR2

MR3

0 (Must always be 0 in timer mode ; i = 0)

Nothing is assiigned (i = 1, 2)

In an attempt to write to this bit, write 0 . The value, if read, turns out

to be indeterminate.

(Note 1)

(Note 2)

.

Invalid in timer mode.

In an attempt to write to this bit, write 0 . The value, if read in

timer mode, turns out to be indeterminate.

b7 b6

Count source select bit

TCK0

TCK1

0 0 : f

1

8

or f2

0 1 : f

1 0 : f32

1 1 : fC32

Note 1: Timer B0.

.

Note 2: Timer B1,B2.

Figure 1.13.19. Timer Bi mode register in timer mode

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Timer B

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.13.7.)

Figure 1.13.20 shows the timer Bi mode register in event counter mode.

Table 1.13.7. Timer specifications in event counter mode

Item

Specification

• External signals input to TBiIN pin

Count source

• Effective edge of count source can be a rising edge, a falling edge, or falling

and rising edges as selected by software

• Counts down

Count operation

• When the timer underflows, it reloads the reload register contents before

continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count stop condition

Count start flag is set (= 1)

Count start flag is reset (= 0)

Interrupt request generation timing The timer underflows

TBiIN pin function

Read from timer

Write to timer

Count source input

Count value can be read out by reading timer Bi register

• When counting stopped

When a value is written to timer Bi register, it is written to both reload register

and counter

• When counting in progress

When a value is written to timer Bi register, it is written to only reload register

(Transferred to counter at next reload time)

Timer Bi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Address

When reset

TBiMR(i=0 to 2) 039B16 to 039D16

00XX0000

2

0

1

R

W

Bit symbol

Bit name

Function

b1 b0

TMOD0

TMOD1

MR0

Operation mode select bit

0 1 : Event counter mode

b3 b2

Count polarity select

bit (Note 1)

0 0 : Counts external signal's

falling edges

0 1 : Counts external signal's

rising edges

MR1

1 0 : Counts external signal's

falling and rising edges

1 1 : Must not be set.

0 (Must always be 0 in event counter mode; i = 0)

Nothing is assigned (i = 1, 2)

In an attempt to write to this bit, write 0 . The value, if read,

turns out to be indeterminate.

MR2

MR3

(Note 2)

(Note 3)

.

Invalid in event counter mode.

In an attempt to write to this bit, write 0 . The value, if read in

event counter mode, turns out to be indeterminate.

Invalid in event counter mode.

Can be 0 or 1 .

TCK0

TCK1

0 : Input from TBiIN pin (Note 4)

1 : TBj overflow

(j = i 1; however, j = 2 when i = 0)

Event clock select

Note 1: Valid only when input from the TBiIN pin is selected as the event clock.

If timer's overflow is selected, this bit can be 0 or 1 .

Note 2: Timer B0.

Note 3: Timer B1, timer B2.

.

Note 4: Set the corresponding port direction register to 0 .

Figure 1.13.20. Timer Bi mode register in event counter mode

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Timer B

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(3) Pulse period/pulse width measurement mode

In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.13.8.)

Figure 1.13.21 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure

1.13.22 shows the operation timing when measuring a pulse period. Figure 1.13.23 shows the operation

timing when measuring a pulse width.

Table 1.13.8. Timer specifications in pulse period/pulse width measurement mode

Item

Count source

Count operation

Specification

f1, f2, f8, f32, fC32

• Up count

• Counter value “000016” is transferred to reload register at measurement

pulse's effective edge and the timer continues counting

Count start flag is set (= 1)

Count start condition

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)

• When an overflow occurs. (Simultaneously, the timer Bi overflow flag

changes to “1”. Assume that the count start flag condition is “1” and then

the timer Bi overflow flag becomes “1”. If the timer Bi mode register has a

write-access after next count cycle of the timer from the above condition, the

timer Bi overflow flag becomes “0”.)

TBiIN pin function

Read from timer

Measurement pulse input

When timer Bi register is read, it indicates the reload register’s content

(measurement result) (Note 2)

Write to timer

Cannot be written to

Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.

Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is

input after the timer has started counting.

Timer Bi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Address

When reset

00XX0000

TBiMR(i=0 to 2) 039B16 to 039D16

2

1

0

R

W

Bit symbol

Bit name

Function

b1 b0

TMOD0

TMOD1

Operation mode

select bit

1 0 : Pulse period / pulse width

measurement mode

b3 b2

MR0

MR1

Measurement mode

select bit

0 0 : Pulse period measurement (Interval between

measurement pulse's falling edge to falling edge)

0 1 : Pulse period measurement (Interval between

measurement pulse's rising edge to rising edge)

1 0 : Pulse width measurement (Interval between

measurement pulse's falling edge to rising edge,

and between rising edge to falling edge)

1 1 : Must not be set.

0 (Must always be

0

in pulse period/pulse width measurement mode; i = 0)

MR2

(Note 2)

(Note 3)

Nothing is assigned (i = 1, 2).

In an attempt to write to this bit, write 0 . The value, if read, turns out to be

indeterminate.

Timer Bi overflow

flag ( Note 1)

0 : Timer did not overflow

1 : Timer has overflowed

MR3

b7 b6

TCK0

TCK1

Count source

select bit

0 0 : f

0 1 : f

1 0 : f32

1 1 : fC32

1

8

or f2

Note 1: It is indeterminate when reset. Assume that the count start flag condition is

1 and then the timer Bi

overflow flag becomes 1 . If the timer Bi mode register has a write access after next count cycle of

the timer from the above condition, the timer Bi overflow flag becomes 0 . This flag cannot be set to

1

by software.

Note 2: Timer B0.

Note 3: Timer B1, timer B2.

Figure 1.13.21. Timer Bi mode register in pulse period/pulse width measurement mode

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M16C/26 Group

Timer B

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

When measuring measurement pulse time interval from falling edge to falling edge

Count source

H

L

Measurement pulse

Transfer

(indeterminate value)

(measured value)

Reload register counter

transfer timing

(Note 1)

(Note 2)

Timing at which counter

reaches 000016

1

Count start flag

0

1

0

Timer Bi interrupt

request bit

Cleared to 0 when interrupt request is accepted, or cleared by software.

1

0

Timer Bi overflow flag

Note 1: Counter is initialized at completion of measurement.

Note 2: Timer has overflowed.

Figure 1.13.22. Operation timing when measuring a pulse period

Count source

H

Measurement pulse

L

Transfer

(measured value)

Transfer

(measured value)

Transfer

(indeterminate

value)

Transfer

(measured

value)

Reload register counter

transfer timing

(Note 1)

(Note 1) (Note 1)

(Note 2)

Timing at which counter

reaches 000016

1

Count start flag

0

1

0

Timer Bi interrupt

request bit

Cleared to 0 when interrupt request is accepted, or cleared by software.

1

0

Timer Bi overflow flag

Note 1: Counter is initialized at completion of measurement.

Note 2: Timer has overflowed.

Figure 1.13.23. Operation timing when measuring a pulse width

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M16C/26 Group

Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Three-Phase Motor Control Timer Function

Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor

driving waveforms. This function requires that P85 become SD, making it important that P85 not be used for

general purpose I/O (GPIO). If the SD feature is not needed, then P85/SD must always be driven high.

Three-phase PWM control register 0 (Note 4)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

INVC0

Address

034816

When reset

0016

Bit symbol

INV00

Bit name

Description

R W

Effective interrupt output

polarity select bit

0: A timer B2 interrupt occurs when the

timer A1 reload control signal is 1 .

1: A timer B2 interrupt occurs when the

timer A1 reload control signal is 0 .

(Note 3)

Effective interrupt output

specification bit

0: Not specified.

1: Selected by the INV00 bit.

INV01

INV02

(Note 2)

(Note 3)

Mode select bit

0: Normal mode

1: Three-phase PWM output mode

(Note 4)

Output control bit (Note 9) 0: Output disabled

1: Output enabled

(Note 10)

INV03

INV04

Positive and negative

0: Feature disabled

phases concurrent L output 1: Feature enabled

disable function enable bit

Positive and negative

phases concurrent L output 1: Already detected

detect flag

0: Not detected yet

INV05

INV06

(Note 5)

0: Triangular wave modulation mode

1: Sawtooth wave modulation mode

Modulation mode select

bit

(Note 6)

(Note 7)

0: Ignored

1: Trigger generated

INV07

Software trigger bit

(Note 8)

Note 1: Set bit 1 of the protect register (address 000A16) to 1 before writing to this register.

Note 2: Set bit 1 of this register to 1 after setting timer B2 interrupt occurrences frequency set counter.

Note 3: Effective only in three-phase mode 1(Three-phase PWM control register's bit 1 = 1 ).

Note 4: Selecting three-phase PWM output mode causes the dead time timer, the U, V, W phase output control circuits,

and the timer B2 interrupt frequency set circuit works.

Note 5: No value other than 0 can be written.

Note 6: The dead time timer starts in synchronization with the falling edge of timer Ai output. The data transfer from the

three-phase buffer register to the three-phase output shift register is made only once in synchronization with the

transfer trigger signal after writing to the three-phase output buffer register.

Note 7: The dead time timer starts in synchronization with the falling edge of timer A output and with the transfer trigger

signal. The data transfer from the three-phase output buffer register to the three-phase output shift register is

made with respect to every transfer trigger.

Note 8: The value, when read, is 0 .

Note 9: The INV03 bit is set to 0 in the following cases:

• When reset.

• When positive and negative go active simultaneously while INV04 bit is 1 .

• When set to 0 in a program.

• When input on the SD pin changes state from H to L . (The INV03 bit cannot be set to 1 when SD input is L .)

Note 10: When INV03 = 1 (three-phase motor control timer output enabled) P80, P81, P72, P73, P74, and P75 function

as U, U, V, V, W, and W.

Figure 1.14.1. Registers related to timers for three-phase motor control (1)

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M16C/26 Group

Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Three-phase PWM control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

INVC1

Address

034916

When reset

0016

Bit symbol

INV10

Bit name

D escription

R W

Timer Ai start trigger signal 0: Timer B2 overflow signal

select bit

1: Timer B2 overflow signal,

signal for writing to timer B2

Timer A1-1, A2-1, A4-1

control bit

0: Three-phase mode 0

1: Three-phase mode 1

INV11

INV12

Dead time timer count

source select bit

0 : f1

1

or f

2

1 : f

divided by 2, or f

2

divided by 2

0: Rising edge of triangular waveform

1: Falling edge of triangular waveform

INV13

Carrier wave detect flag

(Note 2)

(Note 4)

Output polarity control bit

Dead time invalid bit

0 : Low active

1 : High active

INV14

INV15

0: Dead time valid bit

1: Dead time invalid bit

Dead time timer trigger

select bit

0: Triggers from corresponding timer

1: Rising edge of corresponding phase

output

INV16

(Note 3)

Reserved bit

This bit should be set to "0".

(b7)

Note 1: Set bit 1 of the protect register (address 000A16) to 1 before writing to this register.

Note 2: INV13 is valid only in triangular waveform mode (INV06=0) and three-phase mode (INV11=1).

Note 3:Usually set to 1 .

Note 4: When INV14="1", INV13="0" is falling edge of triangular waveform and INV13="1" is rising edge of triangular

waveform.

Figure 1.14.2. Registers related to timers for three-phase motor control (2)

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M16C/26 Group

Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Three-phase output buffer register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

IDB0

Address

034A16

When reset

0016

R

W

Bit name

Bit Symbol

DU0

Function

U phase output buffer 0

V phase output buffer 0

Setting in U phase output buffer 0 (Note)

(Note)

DUB0

DV0

Setting in U phase output buffer 0

Setting in V phase output buffer 0

(Note)

DVB0

DW0

V phase output buffer 0

Setting in V phase output buffer 0

W phase output buffer 0 Setting in W phase output buffer 0

DWB0

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Note: When executing read instruction of this register, the contents of three-phase shift

register is read out.

Three-phase output buffer register 1

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

IDB1

Address

034B16

When reset

0016

R

W

Bit Symbol

DU1

Bit name

Function

U phase output buffer 1

V phase output buffer 1

Setting in U phase output buffer 1 (Note)

DUB1

DV1

(Note)

Setting in V phase output buffer 1

DVB1

DW1

Setting in V phase output buffer 1 (Note)

W phase output buffer 1 Setting in W phase output buffer 1 (Note)

(Note)

W phase output buffer 1 Setting in W phase output buffer 1

DWB1

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Note: When executing read instruction of this register, the contents of three-phase shift

register is read out.

Dead time timer (Note)

b7

b0

Symbol

DTT

Address

034C16

When reset

Indeterminate

R

W

Function

Values that can be set

to 255

Set dead time timer

1

Note: Use MOV instruction to write to this register.

Timer B2 interrupt occurrences frequency set counter (Note 1, 2, 3)

b3

b0

Symbol

ICTB2

Address

034D16

When reset

Indeterminate

Function

R

W

Values that can be set

1 to 15

Set occurrence frequency of timer B2

interrupt request

Note 1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of three-

phase PWM control register 0, do not change the B2 interrupt occurrences frequency

set counter to deal with the timer function for three-phase motor control.

Note 2: Do not write at the timing of an overflow occurrence in timer B2.

Note 3: Use MOV instruction to write to this register.

Figure 1.14.3. Registers related to timers for three-phase motor control (3)

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer Ai (i=1, 2, 4) register (Notes 1, 4)

(b15)

b7

(b8)

b0

Symbol

TA1

TA2

Address

When reset

Indeterminate

b0 b7

038916,038816

038B16,038A16

038F16,038E16

TA4

Function

R W

Values that can be set

000016 to FFFF16

· Timer mode

Counts an internal count source

· One-shot timer mode

Counts a one shot width

000016 to FFFF16

(Note 2, 3)

Note 1: Read and write data in 16-bit units.

Note 2: When the timer Ai register is set to "000016", the counter does not operate

and a timer Ai interrupt does not occur.

Note 3: Use MOV instruction to write to this register.

Note 4: Do not write to these registers synchronously with a timer B2 underflow.

Timer Ai-1 (i=1, 2, 4) register (Notes 1, 2)

(b15)

b7

(b8)

b0 b7

Symbol

TA11

TA21

TA41

Address

When reset

Indeterminate

b0

034316,034216

034516,034416

034716,034616

Function

Counts an internal count source

R W

Values that can be set

000016 to FFFF16

Note 1: Read and write data in 16-bit units.

Note 2: Do not write to these registers synchronously with a timer B2 underflow.

Timer B2 special mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

TB2SC

Address

039E16

When reset

XXXXXX002

Bit symbol

PWCOM

Bit name

Function

R W

0 : Next underflow

1 : Synchronized rising edge of

triangular wave

Timer B2 reload timing

switching bit

Three phase output port 0 : SD pin input port Hi-z disabled

SD control bit 1 1 : SD pin input port Hi-z enabled

(Note 1,2,3)

IVPCR1

Nothing is assigned.

When write, set 0 . When read, its content is 0 .

Note 1: Set the protect register (address 000A16) to "1" before writing to this register.

Note 2: Related pins are P80, P81, P72, P73, P74, and P75, regardless of function

assigned.

Note 3: Select P85 as input port prior to setting IVPCR1 to "1".

Figure 1.14.4. Registers related to timers for three-phase motor control (4)

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Trigger select register

b7 b6 b5 b4 b3 b2 b1

b0

Symbol

TRGSR

Address

038316

When reset

0016

Bit symbol

TA1TGL

Bit name

Function

R W

b1 b0

Timer A1 event/trigger

select bit

0 0 : Input on TA1^INis selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA0 overflow is selected

1 1 : TA2 overflow is selected

TA1TGH

TA2TGL

b3 b2

Timer A2 event/trigger

select bit

0 0 : Input on TA2IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA1 overflow is selected

1 1 : TA3 overflow is selected

TA2TGH

TA3TGL

b5 b4

Timer A3 event/trigger

select bit

0 0 : Input on TA3IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA2 overflow is selected

1 1 : TA4 overflow is selected

TA3TGH

b7 b6

TA4TGL

TA4TGH

Timer A4 event/trigger

select bit

0 0 : Input on TA4IN is selected (Note)

0 1 : TB2 overflow is selected

1 0 : TA3 overflow is selected

1 1 : TA0 overflow is selected

Note: Set the corresponding port direction register to 0 .

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

TABSR

Address

038016

When reset

0016

Bit symbol

TA0S

TA1S

TA2S

TA3S

TA4S

TB0S

TB1S

TB2S

Bit name

F unction

R W

Timer A0 count start flag

Timer A1 count start flag

Timer A2 count start flag

Timer A3 count start flag

Timer A4 count start flag

Timer B0 count start flag

Timer B1 count start flag

Timer B2 count start flag

0 : Stops counting

1 : Starts counting

Figure 1.14.5. Registers related to timers for three-phase motor control (5)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Three-phase motor driving waveform output mode (three-phase PWM output mode)

Setting “1” in the mode select bit (bit 2 at 034816) shown in Figure 1.14.1 - causes three-phase PWM

output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.14.6, set

timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode

using the respective timer mode registers.

Timer Ai mode register

Symbol

TA1MR

TA2MR

TA3MR

Address

039716

039816

039A16

When reset

0016

b7 b6 b5 b4 b3 b2 b1 b0

0

1 0

0

1

0016

Function

Bit symbol

Bit name

R W

TMOD0

TMOD1

MR0

^b1^{1 b}0⁰: One-shot timer mode

Operation mode

select bit

0 (Must always be 0 in three-phase PWM

output mode)

Pulse output function

select bit

MR1

MR2

Invalid in three-phase PWM output mode

External trigger select

bit

Trigger select bit

1 : Selected by event/trigger select

register

MR3

0 (Must always be 0 in one-shot timer mode)

b7 b6

0 0 : f

TCK0

Count source select bit

1

8

or f2

0 1 : f

1 0 : f32

TCK1

1 1 : fC32

Timer B2 mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

TB2MR

Address

039D16

When reset

00XX0000

2

0

0 0

Bit symbol

R W

Bit name

Function

^b0^{1 b}0⁰: Timer mode

TMOD0

TMOD1

MR0

Operation mode select bit

Invalid in timer mode

Can be 0 or 1

MR1

0 (Must always be 0 in timer mode)

MR2

MR3

Invalid in timer mode.

In an attempt to write to this bit, write "0". When read in timer mode,

its content is indeterminate.

b7 b6

0 0 :

0 1 : f

1 0 : f32

Count source select bit

TCK0

TCK1

f

1

8

or f

2

1 1 : fC32

Figure 1.14.6. Timer mode registers in three-phase PWM output mode

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.14.7 shows the block diagram for three-phase PWM output mode. When selecting output polar-

ity “L” active in three-phase PWM output mode, the positive-phase waveforms (U phase, V phase, and W

phase) and negative waveforms (U phase, V phase, and W phase), six waveforms in total, are output

from P80, P81, P72, P73, P74, and P75 as active on the “L” level. Of the timers used in this mode, timer A4

controls the U phase and U phase, timer A1 controls the V phase and V phase, and timer A2 controls the

W phase and W phase respectively; timer B2 controls the periods of one-shot pulse output from timers

A4, A1, and A2.

In outputting a waveform, dead time can be set so as to cause the “L” level of the positive waveform

output (U phase, V phase, and W phase) not to lap over the “L” level of the negative waveform output (U

phase, V phase, and W phase).

To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value

from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead

time works as a one-shot timer. If a value is written to the dead time timer (034C16), the value is written

to the reload register shared by the three timers for setting dead time.

Any of the timers for setting dead time takes the value of the reload register into its counter, if a start

trigger comes from its corresponding timer, and performs a down count in line with the clock source

selected by the dead time timer count source select bit (bit 2 at 034916). The timer can receive another

trigger again before the workings due to the previous trigger are completed. In this instance, the timer

performs a down count from the reload register’s content after its transfer, provoked by the trigger, to the

timer for setting dead time.

Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes;

it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to come.

The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V

phase, and W phase) in three-phase PWM output mode are output from respective ports by means of

setting “1” in the output control bit (bit 3 at 034816). Setting “0” in this bit causes the ports to be the state

of set by port direction register. This bit can be set to “0” not only by use of the applicable instruction, but

by entering a falling edge in the NMI terminal or by resetting. Also, if “1” is set in the positive and negative

phases concurrent L output disable function enable bit (bit 4 at 034816) causes one of the pairs of U

phase and U phase, V phase and V phase, and W phase and W phase concurrently go to “L”, as a result,

the port becomes the state of set by port direction register.

100

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figure 1.14.7. Block diagram for three-phase PWM output mode

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Triangular wave modulation

To generate a PWM waveform of triangular wave modulation, set “0” in the modulation mode select bit

(bit 6 at 034816). Also, set “1” in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 034916). In this mode, each

of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register’s content to the

counter every time timer B2 counter’s content becomes 000016. If “0” is set to the effective interrupt

output specification bit (bit 1 at 034816), the frequency of interrupt requests that occur every time the

timer B2 counter’s value becomes 000016 can be set by use of the timer B2 counter (034D16) for setting

the frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting • 0).

Setting “1” in the effective interrupt output specification bit (bit 1 at 034816) provides the means to choose

which value of the timer A1 reload control signal to use, “0” or “1”, to cause timer B2’s interrupt request to

occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 034816).

An example of U phase waveform is shown in Figure 1.14.8, and the description of waveform output

workings is given below. Set “1” in DU0 (bit 0 at 034A16). And set “0” in DUB0 (bit 1 at 034A16). In

addition, set “0” in DU1 (bit 0 at 034B16) and set “1” in DUB1 (bit 1 at 034B16). Also, set “0” in the effective

interrupt output specification bit (bit 1 at 034816) to set a value in the timer B2 interrupt occurrence

frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter’s content

becomes 000016 as many as (setting) times. Furthermore, set “1” in the effective interrupt output speci-

fication bit (bit 1 at 034816), set “0” in the effective interrupt output polarity select bit (bit 0 at 034816) and

set "1" in the interrupt occurrence frequency set counter (034D16). These settings cause a timer B2

interrupt to occur every other interval when the U phase output goes to “H”.

When the timer B2 counter’s content becomes 000016, timer A4 starts outputting one-shot pulses. In

this instance, the content of DU1 (bit 0 at 034B16) and that of DU0 (bit 0 at 034A16) are set in the three-

phase output shift register (U phase), the content of DUB1 (bit 1 at 034B16) and that of DUB0 (bit 1 at

034A16) are set in the three-phase output shift register (U phase). After triangular wave modulation

mode is selected, however, no setting is made in the shift register even though the timer B2 counter’s

content becomes 000016.

The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)

respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when

timer A4 finishes outputting one-shot pulses, the three-phase shift register’s content is shifted one posi-

tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase

output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time

used for setting the time over which the “L” level of the U phase waveform does not lap over the “L” level

of the U phase waveform, which has the opposite phase of the former. The U phase waveform output that

started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot

pulses even though the three-phase output shift register’s content changes from “1” to “0” by the effect of

the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, “0” already

shifted in the three-phase shift register goes effective, and the U phase waveform changes to the “L”

level. When the timer B2 counter’s content becomes 000016, the timer A4 counter starts counting the

value written to timer A4-1 (034716, 034616), and starts outputting one-shot pulses. When timer A4 fin-

ishes outputting one-shot pulses, the three-phase shift register’s content is shifted one position, but if the

three-phase output shift register’s content changes from “0” to “1” as a result of the shift, the output level

changes from “L” to “H” without waiting for the timer for setting dead time to finish outputting one-shot

pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the

three-phase output shift register on the U phase side is used, the workings in generating a U phase

102

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U

phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in

which the “L” level of the U phase waveform doesn’t lap over that of the U phase waveform, which has the

opposite phase of the U phase waveform. The width of the “L” level too can be adjusted by varying the

values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases,

the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with

the U and U phases to generate an intended waveform.

Carrier wave

Signal wave

Timer B2

Timber B2 interrupt occurres

Rewriting timer A4 and timer A4-1.

Possible to set the number of overflows to generate an

interrupt by use of the interrupt occurrences frequency

set circuit

Trigger signal for

timer Ai start

(timer B2 overflow

signal)

The three-phase

shift register

shifts in

m

n

m

n

m

p

o

Timer A4 output

synchronization

with the falling

edge of the A4

output.

Control signal for

timer A4 reload

U phase

output signal

U phase

output signal

U phase

(Note 1)

U phase

Dead time

U phase

(Note 2)

U phase

INV13(Triangular wave

modulation detect flag)

(Note 3)

Note 1: When INV14="0" (output wave Low active)

Note 2: When INV14="1" (output wave High active)

Note 3: Set to triangular wave modulation mode and to three-phase mode 1.

Figure 1.14.8. Timing chart of operation (1)

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Assigning certain values to DU0 (bit 0 at 034A16) and DUB0 (bit 1 at 034A16), and to DU1 (bit 0 at

034B16) and DUB1 (bit 1 at 034B16) allows the user to output the waveforms as shown in Figure 1.14.9,

that is, to output the U phase alone, to fix U phase to “H”, to fix the U phase to “H,” or to output the U phase

alone.

Carrier wave

Signal wave

Timer B2

Rewriting timer A4 every timer B2 interrupt occurs.

Timer B2 interrupt occurs.

Trigger signal for

Rewriting three-phase buffer register.

timer Ai start

(timer B2 overflow

signal)

Timer A4 output

m

n

m

n

m

p

o

U phase

output signal

U phase

output signal

U phase

Dead time

Note: Set to triangular wave modulation mode and to three-phase mode 0.

Figure 1.14.9. Timing chart of operation (2)

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Figures 1.14.1 to 1.14.5 show registers related to timers for three-phase motor control.

Sawtooth modulation

To generate a PWM waveform of sawtooth wave modulation, set “1” in the modulation mode select bit (bit

6 at 034816). Also, set “0” in the timers A4-1, A1-1, and A2-1 control bit (bit 1 at 034916). In this mode, the

timer registers of timers A4, A1, and A2 comprise conventional timers A4, A1, and A2 alone, and reload

the corresponding timer register’s content to the counter every time the timer B2 counter’s content be-

comes 000016. The effective interrupt output specification bit (bit 1 at 034816) and the effective interrupt

output polarity select bit (bit 0 at 034816) go nullified.

An example of U phase waveform is shown in Figure 1.14.10, and the description of waveform output

workings is given below. Set “1” in DU0 (bit 0 at 034A16), and set “0” in DUB0 (bit 1 at 034A16). In addition,

set “0” in DU1 (bit 0 at 034A16) and set “1” in DUB1 (bit 1 at 034A16).

When the timber B2 counter’s content becomes 000016, timer B2 generates an interrupt, and timer A4

starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer

registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of

DUB1 and DUB0 are set in the three-phase output shift register (U phase). After this, the three-phase

buffer register’s content is set in the three-phase shift register every time the timer B2 counter’s content

becomes 000016.

The value of DU0 and that of DUB0 are output to the U terminal (P80) and to the U terminal (P81)

respectively. When the timer A4 counter counts the value written to timer A4 (038F16, 038E16) and when

timer A4 finishes outputting one-shot pulses, the three-phase output shift register’s content is shifted one

position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U

output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time

used for setting the time over which the “L” level of the U phase waveform doesn’t lap over the “L” level of

the U phase waveform, which has the opposite phase of the former. The U phase waveform output that

started from the “H” level keeps its level until the timer for setting dead time finishes outputting one-shot

pulses even though the three-phase output shift register’s content changes from “1” to “0 ”by the effect of

the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already

shifted in the three-phase shift register goes effective, and the U phase waveform changes to the “L”

level. When the timer B2 counter’s content becomes 000016, the contents of the three-phase buffer

registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of

DUB1 and DUB0 are set in the three-phase output shift register (U phase) again.

A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase

output shift register on the U phase side is used, the workings in generating a U phase waveform, which

has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In

this way, a waveform can be picked up from the applicable terminal in a manner in which the “L” level of

the U phase waveform doesn’t lap over that of the U phase waveform, which has the opposite phase of

the U phase waveform. The width of the “L” level too can be adjusted by varying the values of timer B2

and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase

of the former, have the corresponding timers work similarly to dealing with the U and U phases to gener-

ate an intended waveform.

Setting “1” both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U

phase output to “H” as shown in Figure 1.14.11.

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A carrier wave of sawtooth waveform

Carrier wave

Signal wave

Timer B2

Data transfer is made from the three-

phase buffer register to the three-

phase shift register in step with the

timing of the timer B overflow.

Interrupt occurs.

Rewriting the value of timer A4.

Trigger signal for

timer Ai start

(timer B2 overflow

signal)

The three-phase

shift register

n

p

Timer A4 output

m

o

shifts in

synchronization

with the falling

edge of timer A4.

U phase output

signal

U phase

output signal

U phase

Dead time

Note: Set to sawtooth modulation mode and to three-phase mode 0.

Figure 1.14.10. Timing chart of operation (3)

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Three-Phase Motor Control Timer Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A carrier wave of sawtooth waveform

Carrier wave

Signal wave

Timer B2

Interrupt occurs.

Rewriting the value of timer A4.

Interrupt occurs.

Rewriting the value of timer A4.

Data transfer is made from the three-

phase buffer register to the three-

phase shift register in step with the

timing of the timer B overflow.

Trigger signal for

timer Ai start

(timer B2 overflow

signal)

Rewriting three-phase

output buffer register

The three-phase

shift register shifts

in synchronization

Timer A4 output

m

n

p

o

with the falling

edge of timer A4.

U phase

output signal

U phase

output signal

U phase

Dead time

Note: Set to sawtooth modulation mode and to three-phase mode 0.

Figure 1.14.11. Timing chart of operation (4)

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Serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

Serial I/O is configured as three channels: UART0, UART1, and UART2.

UARTi (i = 0 to 2)

UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate

independently of each other.

Figure 1.15.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.15.2 and 1.15.3 show

the block diagram of the transmit/receive unit.

UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous

serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses

03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a

UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.

UART2, in particular, is used for the SIM (Subscriber Identity Module) interface with some extra settings

added in clock-asynchronous serial I/O mode.

Table 1.15.1 shows the comparison of functions of UART0 through UART2, and Figures 1.15.4 to 1.15.10

show the registers related to UARTi.

Table 1.15.1. Comparison of functions of UART0 through UART2

Function

UART0

UART1

UART2

CLK polarity selection

(Note 1)

Supported

(Note 1)

Supported

(Note 1)

LSB first / MSB first selection

(Note 2)

(Note 1)

Continuous receive mode selection

Supported

Supported (Note 1)

Not Supported

Transfer clock output from multiple

pins selection

Not Supported

(Note 3)

Serial data logic switch

Not Supported

Supported

TxD, RxD I/O polarity switch

N-channel open-drain

output

TxD, RxD port output format

Parity error signal output

Bus collision detection

CMOS output/Nch OD

Not Supported

CMOS output/Nch OD

Not Supported

(Note 3)

Supported

Not Supported

Supported

Not Supported

Note 1: Only when in clock synchronous serial I/O mod. e.

Note 2: Only when in clock synchronous serial I/O mode and 8-bit UART mode.

Note 3: Used for SIM interface.

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Serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(UART0)

RxD

0

TxD

0

UART reception

Clock source selection

CLK1 to CLK0

Receive

clock

1/16

1/2

Reception

Clock synchronous

type

control circuit

00

01

10

External

2

Transmit/

receive

unit

U0BRG

register

f

1SIO or

f

2SIO

8SIO

32SIO

Internal

2

CKDIR=0

CKDIR=1

UART transmission

2

Transmit

clock

f

1 / (n0+1)

Transmission control

circuit

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

CKDIR=0

Clock synchronous type

(when external clock is selected)

CKPOL

CKDIR=1

Clock synchronous type

(when internal clock is selected)

CLK

polarity

reversing

circuit

CLK

0

CTS/RTS disabled

CTS/RTS selected

CRS=1

RTS

0

CTS0 / RTS

0

CRS=0

V

CC

CTS/RTS disabled

RCSP=0

RCSP=1

CRD=1

CRD=0

CTS

0

CTS0 from UART1

(UART1)

RxD

1

TxD

1

UART reception

Clock source selection

CLK1 to CLK0

Receive

clock

1/16

Reception

Clock synchronous

type

control circuit

Transmit/

receive

unit

00

01

10

2

U1BRG

register

f

1SIO or

f

2SIO

8SIO

32SIO

Internal

2

CKDIR=0

2

UART transmission

Transmit

clock

f

1/16

1/2

1 / (n1+1)

Transmission

control circuit

Clock synchronous

type

External

CKDIR=1

Clock synchronous type

(when internal clock is selected)

CKDIR=0

Clock synchronous type

(when external clock is selected)

Clock synchronous type

(when internal clock is selected)

CKPOL

CKDIR=1

CLK

polarity

reversing

circuit

CLKMD0=0

CLKMD0=1

CLK

1

Clock output

pin select

CLKMD1=1

CTS/RTS selected

CRS=1

CTS/RTS disabled

CTS

1

0

/ RTS

1

/

RTS1

/ CLKS

1

CLKMD1=0

CRS=0

V

CC

CTS/RTS disabled

CTS1

CTS

RCSP=0

RCSP=1

CRD=1

CRD=0

0

from UART0

(UART2)

TxD

polarity

reversing

circuit

RxD polarity

reversing circuit

RxD

2

TxD

2

UART reception

Clock source selection

CLK1 to CLK0

00

Receive

clock

1/16

(Note)

Reception

Clock synchronous

type

control circuit

2

Transmit/

receive

unit

U2BRG

register

f1SIO or

f

2SIO

8SIO

32SIO

01

2

Internal

CKDIR=0

CKDIR=1

UART transmission

10

2

Transmit

clock

f

1/16

1/2

1 / (n2+1)

Transmission

control circuit

Clock synchronous

type

External

Clock synchronous type

(when internal clock is selected)

CKDIR=0

Clock synchronous type

(when external clock is selected)

CKDIR=1

CKPOL

CLK

Clock synchronous type

(when internal clock is selected)

polarity

reversing

circuit

CLK

2

CTS/RTS disabled

CTS/RTS

selected

CRS=1

CRS=0

RTS

2

CTS2 / RTS

2

V

CC

CTS/RTS disabled

CRD=1

CRD=0

CTS

2

i = 0 to 2

: Values set to the UiBRG register

SMD2 to SMD0, CKDIR: UiMR register's bits

n

i

CLK1 to CLK0, CKPOL, CRD, CRS: UiC0 register's bits

CLKMD0, CLKMD1, RCSP: UCON register's bits

Note: UART2 is the N-channel open-drain output. Cannot be set to the CMOS output.

Figure 1.15.1. Block diagram of UARTi (i = 0 to 2)

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Serial I/O

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Clock

synchronous type

UART (7 bits)

UART (8 bits)

Clock

UARTi receive register

synchronous

type

UART (7 bits)

PAR

disabled

1SP

2SP

SP

PAR

RxDi

PAR

enabled

UART

UART (9 bits)

Clock

synchronous type

UART (8 bits)

UART (9 bits)

UARTi receive

buffer register

0

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address 03A616

Address 03A716

Address 03AE16

Address 03AF16

MSB/LSB conversion circuit

Data bus high-order bits

Data bus low-order bits

MSB/LSB conversion circuit

UARTi†transmit

buffer register

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

8

Address 03A216

Address 03A316

Address 03AA16

Address 03AB16

UART (8 bits)

UART (9 bits)

Clock synchronous

type

UART (9 bits)

PAR

enabled

UART

2SP

1SP

SP

PAR

TxDi

Clock

synchronous

type

PAR

disabled

UART (7 bits)

UARTi transmit register

UART (7 bits)

UART (8 bits)

SP: Stop bit

PAR: Parity bit

0

Clock synchronous

type

Figure 1.15.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit

110

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Specifications in this manual are tentative and subject to change.

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Serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

No reverse

Reverse

RxD data

reverse circuit

RxDi

Clock

synchronous type

UART

(7 bits)

UART

(8 bits)

Clock

synchronous

type

UARTi receive register

PAR

disabled

UART(7 bits)

1SP

SP

PAR

SP

2SP

Clock

synchronous type

PAR

enabled

UART

(9 bits)

UART

(8 bits)

UART

(9 bits)

UARTi receive

buffer register

0

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Address 037E16

Address 037F16

Logic reverse circuit + MSB/LSB conversion circuit

Data bus high-order bits

Data bus low-order bits

Logic reverse circuit + MSB/LSB conversion circuit

UARTi transmit

buffer register

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D

8

Address 037A16

Address 037B16

UART

(8 bits)

UART

(9 bits)

UART

(9 bits)

Clock

synchronous type

PAR

enabled

UART

2SP

SP

PAR

1SP

Clock

synchronous

type

PAR

disabled

UART

(7 bits)

UART

(8 bits)

UART(7 bits)

UARTi transmit register

0

Clock

synchronous type

Error signal output

disable

No reverse

TxD data

reverse circuit

Error signal

output circuit

TxDi

Reverse

Error signal output

enable

SP: Stop bit

PAR: Parity bit

Figure 1.15.3. Block diagram of UART2 transmit/receive unit

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Serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UARTi transmit buffer register (Note)

Symbol

U0TB

U1TB

U2TB

Address

When reset

Indeterminate

(b15)

b7

(b8)

03A3¹⁶, 03A216

03AB16, 03AA16

037B¹⁶, 037A16

b0 b7

b0

Function

R W

Transmit data

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be indeterminate.

Note: Use MOV instruction to write to this register.

UARTi receive buffer register

(b15)

b7

(b8)

b0 b7

Symbol

U0RB

U1RB

U2RB

Address

When reset

Indeterminate

b0

03A7¹⁶, 03A616

03AF¹⁶, 03AE16

037F16, 037E16

Function

(During clock synchronous

serial I/O mode)

Bit

symbol

Function

(During UART mode)

Bit name

R W

Receive data

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Arbitration lost detecting

flag (Note 2)

0 : Not detected

1 : Detected

Invalid

ABT

Overrun error flag (Note 1)

0 : No overrun error

1 : Overrun error found

0 : No overrun error

1 : Overrun error found

OER

FER

Framing error flag (Note 1) Invalid

0 : No framing error

1 : Framing error found

PER

SUM

Parity error flag (Note 1)

Error sum flag (Note 1)

Invalid

0 : No parity error

1 : Parity error found

0 : No error

1 : Error found

Note 1: Bits 15 through 12 are set to

03A816 and 037816) are set to 000

(Bit 15 is set to when bits 14 to 12 all are set to 0 .) Bits 14 and 13 are also set to

0

when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0¹⁶

,

2

or the receive enable bit is set to 0 .

0

0 when the

lower byte of the UARTi receive buffer register (addresses 03A6¹⁶, 03AE16 and 037E16) is read out.

Note 2: Arbitration lost detecting flag is allocated to U2RB and only "0" must be written. Nothing is assigned

in bit 11 of U0RB and U1RB. Set to "0" when writing. If read, value is "0".

UARTi bit rate generator (Note 1, 2)

Symbol

U0BRG

U1BRG

U2BRG

Address

03A1¹⁶

03A9¹⁶

0379¹⁶

When reset

Indeterminate

b7

b0

R W

Function

Values that can be set

0016 to FF16

Assuming that set value = n, BRGi divides the count source by

n + 1

Note 1: Write a value to this register while transmit/receive halts.

Note 2: Use MOV instruction to write to this register.

Figure 1.15.4. Serial I/O-related registers (1)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UARTi transmit/receive mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UiMR(i=0,1)

Address

03A016, 03A816

When reset

0016

0

Function

(During clock synchronous

serial I/O mode)

Bit

symbol

Function

(During UART mode)

Bit name

R W

b2 b1 b0

Must be fixed to 001

SMD0

Serial I/O mode

select bits

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

b2 b1 b0

0 0 0 : Serial I/O invalid

0 1 0 : Inhibited

0 1 1 : Inhibited

SMD1

SMD2

1 1 1 : Inhibited

0 1 1 : Inhibited

1 1 1 : Inhibited

Internal/external clock

select bit

0 : Internal clock

1 : External clock

0 : Internal clock

1 : External clock (Note 1)

CKDIR

STPS

0 : One stop bit

1 : Two stop bits

Stop bit length select bit

Invalid

Valid when bit 6 = “1”

0 : Odd parity

PRY

Odd/even parity select bit Invalid

1 : Even parity

0 : Parity disabled

1 : Parity enabled

PRYE

Parity enable bit

Invalid

Must always be “0”

Reserved

UARTi transmit/receive control register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UiC0(i=0,1)

Address

03A416, 03AC16

When reset

0816

Function

(During clock synchronous

serial I/O mode)

Bit

Function

(During UART mode)

R W

Bit name

symbol

CLK0

b1 b0

BRG count source

select bits

0 0 : f1SIO or f2SIO is selected 0 0 : f1SIO or f2SIO is selected

(Note 2)

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Inhibited

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Inhibited

CLK1

CRS

Valid when bit 4 = “0”

0 : CTS function is selected (Note 1)

1 : RTS function is selected (Note 3)

Valid when bit 4 = “0”

0 : CTS function is selected (Note 1)

1 : RTS function is selected (Note 3)

CTS/RTS function

select bit

0 : Data present in transmit

register (during transmission)

1 : No data present in transmit

register (transmission

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

register (transmission completed)

TXEPT Transmit register empty

flag

completed)

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

(P60 and P64 function as

CRD

NCH

CTS/RTS disable bit

Data output select bit

(P6

0

and P6

4

function as

programmable I/O port)

0 : TXDi pin is CMOS output

1 : TXDi pin is N-channel

open-drain output

0: TXDi pin is CMOS output

1: TXDi pin is N-channel

open-drain output

0 : Transmit data is output at

falling edge of transfer clock

and receive data is input at

rising edge

Must always be “0”

CKPOL CLK polarity select bit

1 : Transmit data is output at

rising edge of transfer clock

and receive data is input at

falling edge

0 : LSB first

1 : MSB first

UFORM Transfer format select bit

Must always be “0”

Note 1: Set the corresponding port direction register to “0”.

Note 2: Periperal clock select register bit PCLK1 is used to select between f1SIO and f2SIO

Note 3: The settings of the corresponding port register and port direction register are invalid.

.

Figure 1.15.5. Serial I/O-related registers (2)

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Serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 transmit/receive mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2MR

Address

037816

When reset

0016

Function

(During clock synchronous

serial I/O mode)

Bit

symbol

Function

(During UART mode)

Bit name

R W

b2 b1 b0

SMD0

SMD1

Serial I/O mode select bit

0 0 0 : Serial I/O invalid

0 0 1 : Serial I/O

0 1 0 : I²C mode

0 1 1 :

0 0 0 : Serial I/O invalid

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

Except the above : Must not be set

:

Must not be set

SMD2

1 1 1 :

CKDIR

STPS

PRY

Internal/external clock

select bit

0 : Internal clock

1 : External clock (Note 1)

0 : Internal clock

1 : External clock (Note 1)

0 : One stop bit

1 : Two stop bits

Stop bit length select bit

Invalid

Valid when bit 6 = 1

0 : Odd parity

Odd/even parity select bit Invalid

1 : Even parity

0 : Parity disabled

1 : Parity enabled

PRYE

Parity enable bit

Invalid

TxD, RxD I/O polarity

reverse bit

0 : No reverse

1 : Reverse

0 : No reverse

1 : Reverse

IOPOL

Usually set to 0

UART2 transmit/receive control register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2C0

Address

037C16

When reset

0816

Function

(During clock synchronous

serial I/O mode)

Bit

Function

(During UART mode)

R W

Bit name

symbol

b1 b0

BRG count source

select bit

0 0 : f1SIO or f2SIO is selected 0 0 : f1SIO or f2SIO is selected

CLK0

(Note 2)

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Must not be set.

0 1 : f8SIO is selected

1 0 : f32SIO is selected

1 1 : Must not be set.

CLK1

Valid when bit 4 = "0"

0 : CTS function is selected (Note 1)

1 : RTS function is selected (Note 3)

Valid when bit 4 = "0"

0 : CTS function is selected (Note 1)

1 : RTS function is selected (Note 3)

CTS/RTS function

select bit

CRS

0 : Data present in transmit

register (during transmission)

1 : No data present in transmit

register (transmission

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

register (transmission completed)

Transmit register empty

flag

TXEPT

CRD

completed)

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

CTS/RTS disable bit

)

(P6

0

, P6

4

and P7

3

function

(P6

0, P64 and P73 function

as programmable I/O port

as programmable I/O port)

Nothing is assigned.

In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.

0 : Transmit data is output at

Must always be "0"

CKPOL CLK polarity select bit

falling edge of transfer clock

and receive data is input at

rising edge

1 : Transmit data is output at

rising edge of transfer clock

and receive data is input at

falling edge

0 : LSB first

1 : MSB first

0 : LSB first

1 : MSB first

UFORM Transfer format select bit

(Note 4)

Note 1: Set the corresponding port direction register to "0".

Note 2: Periperal clock select register bit PCLK1 is used to select between f1SIO and f2SIO

.

Note 3: The settings of the corresponding port register and port direction register are invalid.

Note 4: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.

Figure 1.15.6. Serial I/O-related registers (3)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UARTi transmit/receive control register 1 (i=0, 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UiC1(i=0,1)

Address

03A516,03AD16

When reset

0216

Function

(During clock synchronous

serial I/O mode)

Bit

symbol

Function

(During UART mode)

Bit name

R W

TE

Transmit enable bit

0 : Transmission disabled

1 : Transmission enabled

0 : Transmission disabled

1 : Transmission enabled

TI

Transmit buffer

empty flag

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

1 : No data present in

transmit buffer register

RE

RI

Receive enable bit

0 : Reception disabled

1 : Reception enabled

0 : Reception disabled

1 : Reception enabled

Receive complete flag

0 : No data present in

receive buffer register

1 : Data present in

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

UART2 transmit/receive control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2C1

Address

037D16

When reset

0216

Function

(During clock synchronous

serial I/O mode)

Bit

Function

(During UART mode)

Bit name

symbol

R W

TE

TI

Transmit enable bit

0 : Transmission disabled

1 : Transmission enabled

0 : Transmission disabled

1 : Transmission enabled

Transmit buffer

empty flag

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

1 : No data present in

transmit buffer register

RE

RI

Receive enable bit

0 : Reception disabled

1 : Reception enabled

0 : Reception disabled

1 : Reception enabled

Receive complete flag

0 : No data present in

receive buffer register

1 : Data present in

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

U2IRS UART2 transmit interrupt 0 : Transmit buffer empty

0 : Transmit buffer empty

(TI = 1)

cause select bit

(TI = 1)

1 : Transmit is completed

(TXEPT = 1)

1 : Transmit is completed

(TXEPT = 1)

U2RRM UART2 continuous

receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Must always be "0"

U2LCH Data logic select bit

0 : No reverse

1 : Reverse

0 : No reverse

1 : Reverse

U2ERE Error signal output

enable bit

Must be fixed to 0

0 : Output disabled

1 : Output enabled

Figure 1.15.7. Serial I/O-related registers (4)

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Serial I/O

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART transmit/receive control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UCON

Address

03B016

When reset

X0000000

2

Function

(During clock synchronous

serial I/O mode)

Bit

symbol

Function

(During UART mode)

Bit

name

R W

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

U0IRS UART0 transmit

interrupt cause select bit

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

U1IRS UART1 transmit

interrupt cause select bit

U0RRM UART0 continuous

0 : Continuous receive

mode disabled

Must always be 0

receive mode enable bit

1 : Continuous receive

mode enable

U1RRM UART1 continuous

receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Must always be 0

CLKMD0 CLK/CLKS select bit 0

Valid when bit 5 = 1

0 : Clock output to CLK1

1 : Clock output to CLKS1

Invalid

CLKMD1 CLK/CLKS select

bit 1 (Note)

0 : Normal mode

Must always be 0

(CLK output is CLK1 only)

1 : Transfer clock output

from multiple pins

function selected

0 : CTS/RTS shared pin

1 : CTS/ RTS separated

0 : CTS/RTS shared pin

1 : CTS/ RTS separated

RCSP

Separate CTS/RTS bit

Nothing is assigned.

In an attempt to write to this bit, write 0 . The value, if read, turns out to be indeterminate.

Note: When using multiple pins to output the transfer clock, the following requirements must be met:

* UART1 internal/external clock select bit (bit 3 at address 03A816) = 0 .

UART2 special mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2SMR

Address

037716

When reset

X0000000

2

Function

(During clock synchronous

serial I/O mode)

Bit

symbol

Function

(During UART mode)

Bit

name

R W

0 : Normal mode

1 : I²C mode

Must always be 0

IICM

ABC

I²C mode select bit

Arbitration lost detecting 0 : Update per bit

flag control bit

1 : Update per byte

0 : STOP condition detected

1 : START condition detected

BBS

Bus busy flag

Must always be 0

Must always be 0.

(Note1)

Reserved bit

Must always be 0.

Must always be 0

(b3)

Bus collision detect

sampling

0 : Rising edge of transfer

clock

ABSCS

clock select bit

1 : Underflow signal of timer Aj

(Note 2)

Auto clear function

select bit of transmit

enable bit

Must always be 0

0 : No auto clear function

1 : Auto clear at occurrence of

bus collision

ACSE

SSS

0 : Ordinary

1 : Falling edge of RXDi

Transmit start condition

select bit

Nothing is assigned.

In an attempt to write to this bit, write 0 . The value, if read, turns out to be indeterminate.

Note 1: Nothing but 0 may be written.

Note 2: Underflow signal of timer A0 in UART2.

Figure 1.15.8. Serial I/O-related registers (5)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 special mode register 2

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2SMR2

Address

0376 ₁₆

When reset

X0000000

2

Bit

symbol

Bit name

Function

R W

2

I C mode select bit 2

Refer to Table 1.15.14

IICM2

CSC

Clock-synchronous bit

SCL wait output bit

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

SWC

ALS

SDA output stop bit

UARTi initialization bit

SCL wait output bit 2

SDA output disable bit

0 : Disabled

1 : Enabled

0 : Disabled

1 : Enabled

STAC

SWC2

0: UART2 clock

1: 0 output

0: Enabled

1: Disabled (high impedance)

SDHI

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be

indeterminate.

UART2 special mode register 3

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2SMR3

Address

037516

When reset

000X0X0X

2

Bit

symbol

Bit name

Function

R W

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be

indeterminate.

CKPH

Clock phase set bit

0 : Without clock delay

1 : With clock delay

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be

indeterminate.

NODC Clock output select bit

0 : CLKi is CMOS output

1 : CLKi is N-channel open drain output

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be

indeterminate.

b7 b6 b5

DL0

DL1

DL2

SDAi (T

setup bit

(Note 1, Note 2)

XDi) digital delay

0 0 0 : Without delay

0 0 1 : 1 to 2 cycle(s) of BRG count source

0 1 0 : 2 to 3 cycles of BRG count source

0 1 1 : 3 to 4 cycles of BRG count source

1 0 0 : 4 to 5 cycles of BRG count source

1 0 1 : 5 to 6 cycles of BRG count source

1 1 0 : 6 to 7 cycles of BRG count source

1 1 1 : 7 to 8 cycles of BRG count source

Note 1 : These bits are used for SDAi (TxDi)output digital delay when using UARTi for I²C interface.

Otherwise,must set to 000

2

.

Note 2 : The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the amount of

delay increases by about 100 ns, so be sure to take this into account when using the device.

Figure 1.15.9. Serial I/O-related registers (6)

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UART2 special mode register 4

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2SMR4

Address

037416

When reset

0016

Bit

symbol

Bit name

Start condition

Function

R W

0 : Clear

1 : Start

STAREQ

generate bit (Note)

Restart condition

generate bit (Note)

0 : Clear

1 : Start

RSTAREQ

Stop condition

generate bit (Note)

0 : Clear

1 : Start

STPREQ

STSPSEL

SCL,SDA output

select bit

0 : Ordinal block

1 : Start/stop condition generate block

ACK data bit

0 : ACK

1 : NACK

ACKD

ACK data output

enable bit

0 : SI/O data output

1 : ACKD output

ACKC

SCLHI

SWC9

0 : Disabled

1 : Enabled

SCL output stop

enable bit

Final bit L hold enable

bit

0 : SCL L hold disabled

1 : SCL L hold enabled

Note: When start condition is generated,these bits automatically become 0 .

Figure 1.15.10. Serial I/O-related registers (7)

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Clock Synchronous Serial I/O Mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.15.2

and 1.15.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.15.11 shows the

UARTi transmit/receive mode register.

Table 1.15.2. Specifications of clock synchronous serial I/O mode (1)

Item

Specification

Transfer data format

Transfer clock

• Transfer data length: 8 bits

• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816

= “0”) : fi/ 2(n+1) (Note 1) fi = f1SIO, f2SIO, f8SIO, f32SIO

• When external clock is selected (bit 3 at addresses 03A016, 03A816,

= “1”) : Input from CLKi pin

037816

Transmission/reception control • CTS function, RTS function, CTS and RTS function disabled: selectable

Transmission start condition • To start transmission, the following requirements must be met:

_

Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”

_

Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”

When CTS function selected, CTS input level = “L”

_

•

Furthermore, if external clock is selected, the following requirements must also be met:

CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:

CLKi input level = “H”

_

CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:

CLKi input level = “L”

Reception start condition • To start reception, the following requirements must be met:

_

Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”

_

Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”

Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”

_

• Furthermore, if external clock is selected, the following requirements must

also be met:

_

CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:

CLKi input level = “H”

_

CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:

CLKi input level = “L”

• When transmitting

Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at

Interrupt request

generation timing

_

address 037D16) = “0”: Interrupts requested when data transfer from

transfer buffer register to UARTi transmit register is completed

Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at

UARTi

_

address 037D16) = “1”: Interrupts requested when data transmission from

UARTi transfer register is completed

• When receiving

_

Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

• Overrun error (Note 2)

Generated 7 clock periods after the device started receiving the next data

before reading out the contents of the UARTi receive buffer register.

Note 1: “n” denotes the value 0016 to FF16 that is set in the UART bit rate generator.

Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. In addition,

the UARTi receive interrupt request bit does not change.

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Table 1.15.3. Specifications of clock synchronous serial I/O mode (2)

Item

Specification

Select function

• CLK polarity selection

Whether transmit data output/input timing is at the rising edge or falling

edge of the transfer clock can be selected

• LSB first/MSB first selection

Whether transmission/reception begins with bit 0 or bit 7 can be selected

• Continuous receive mode selection

Reception is enabled automatically after the receive buffer register is

read

• Switching serial data logic (UART2)

Whether to invert data (1's complement) when writing to the

transmission buffer register or reading the reception buffer register can

be selected.

• TxD, RxD I/O polarity reverse (UART2)

This function inverts the TxD port output and RxD port input. All I/O

data level is reversed.

• Transfer clock output from multiple pins selection (UART1)

UART1 transfer clock can be chosen by software to be output from one

of the two pins set

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Table 1.15.4. Registers used in clock synchronous serial I/O mode and the register values set

Register

Bit

Function

Set transmission data

UiTB(Note3) 0 to 7

UiRB(Note3) 0 to 7

OER

Reception data can be read

Overrun error flag

UiBRG

0 to 7

Set a transfer rate

UiMR(Note3) SMD2 to SMD0

Set to “0012”

CKDIR

IOPOL

Select the internal clock or external clock

Set to “0”

UiC0

CLK1 to CLK0

CRS

Select the count source for the UiBRG register

Select CTS or RTS to use

TXEPT

CRD

Transmit register empty flag

Enable or disable the CTS or RTS function

Select TxDi pin output mode (Note 2)

Select the transfer clock polarity

Select the LSB first or MSB first

Set this bit to “1” to enable transmission/reception

Transmit buffer empty flag

NCH

CKPOL

UFORM

TE

UiC1

TI

RE

Set this bit to “1” to enable reception

Reception complete flag

RI

U2IRS (Note 1)

U2RRM (Note 1)

UiLCH

Select the source of UART2 transmit interrupt

Set this bit to “1” to use continuous receive mode

Set this bit to “1” to use inverted data logic

Set to “0”

UiERE

0 to 7

UiSMR

Set to “0”

UiSMR2

UiSMR3

0 to 7

Set to “0”

0 to 2

Set to “0”

NODC

Select clock output mode

4 to 7

Set to “0”

UiSMR4

UCON

0 to 7

Set to “0”

U0IRS, U1IRS

U0RRM, U1RRM

CLKMD0

CLKMD1

RCSP

Select the source of UART0/UART1 transmit interrupt

Set this bit to “1” to use continuous receive mode

Select the transfer clock output pin when CLKMD1 = 1

Set this bit to “1” to output UART1 transfer clock from two pins

Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin

Set to “0”

7

Note 1: Set the U0C1 and U1C1 register bit 4 and bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits

are in the UCON register.

Note 2: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.

Note 3: Not all register bits are described above. Set those bits to “0” when writing to the registers in clock

synchronous serial I/O mode.

i=0 to 2

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UARTi transmit/receive mode register (i=0 to 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UiMR(i=0 to 1)

Address

03A016, 03A816

When reset

0016

0

0 0 1

Bit symbol

Bit name

Function

R W

b2 b1 b0

SMD0

SMD1

SMD2

CKDIR

Serial I/O mode select bit

0 0 1 : Clock synchronous serial

I/O mode

Internal/external clock

select bit

0 : Internal clock

1 : External clock (Note)

STPS

PRY

Invalid in clock synchronous serial I/O mode

PRYE

Reserved Must always be "0".

Note: Set the corresponding port direction register to "0".

UART2 transmit/receive mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2MR

Address

0378 16

When reset

0016

0

0 0 1

Bit symbol

Bit name

Function

R W

b2 b1 b0

SMD0

SMD1

SMD2

CKDIR

Serial I/O mode select bit

0 0 1 : Clock synchronous serial

I/O mode

Internal/external clock

select bit

0 : Internal clock

1 : External clock (Note 2)

STPS

PRY

Invalid in clock synchronous serial I/O mode

PRYE

IOPOL

TxD, RxD I/O polarity

reverse bit (Note 1)

0 : No reverse

1 : Reverse

Note 1: Usually set to 0 .

Note 2: Set the corresponding port direction register to 0 .

Figure 1.15.11. UARTi transmit/receive mode register in clock synchronous serial I/O mode

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Table 1.15.5 lists the functions of the input/output pins during clock synchronous serial I/O mode. This

table shows the pin functions when the transfer clock output from multiple pins function is not selected.

Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi

pin outputs an “H”. (If the N-channel open-drain is selected, this pin is in floating state.)

Table 1.15.5. Input/output pin functions in clock synchronous serial I/O mode

(when transfer clock output from multiple pins is not selected)

Pin name

TxDi

(P6 , P6

RxDi

(P6 , P6

Function

Method of selection

Serial data output

(Outputs dummy data when performing reception only)

3

7, P70)

Serial data input

Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,

2

6

, P7

1

)

bit 1 at address 03EF16)= 0

(Can be used as an input port when performing transmission only)

CLKi

(P6 , P6

Transfer clock output

Transfer clock input

Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = 0

Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = 1

1

5

, P7

2

Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,

bit 2 at address 03EF16) = 0

CTSi/RTSi

(P6 , P6 , P73)

CTS input

CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = 0

0

4

CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = 0

Port P6 , P6 and P7 direction register (bits 0 and 4 at address 03EE16

0

4

3

,

bit 3 at address 03EF16) = 0

RTS output

CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = 0

CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = 1

Programmable I/O port

CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = 1

Table 1.15.6. P64 pin function in clock synchronous serial I/O mode

Pin function Bit set value

UCON register

U1C0 register

PD6 register

PD6_4

CLKMD0

CLKMD1

RCSP

CRS

CRD

P6

4

1

0

1

0

Input: 0, Output: 1

0

1

0

CTS

RTS

CTS

CLKS

1

0

1

0(Note1)

1

1(Note 2)

Note 1: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS

C0 register’s CRS bit to “1” (RTS selected).

0/RTS0 enabled) and the U0

0

Note 2: When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:

• High if the U1C0 register’s CLKPOL bit = 0

• Low if the U1C0 register’s CLKPOL bit = 1

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• Example of transmit timing (when internal clock is selected)

Tc

Transfer clock

1

Transmit enable

0

1

Data is set in UARTi transmit buffer register

bit (TE)

Transmit buffer

empty flag (Tl)

0

Transferred from UARTi transmit buffer register to UARTi transmit register

H

CTSi

CLKi

TCLK

L

Stopped pulsing because CTS =

H

Stopped pulsing because transfer enable bit =

0

TxDi

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D7

Transmit

register empty

flag (TXEPT)

1

0

1

0

Transmit interrupt

request bit (IR)

Cleared to

0

when interrupt request is accepted, or cleared by software

Tc = TCLK = 2(n + 1) / fi

Shown in ( ) are bit symbols.

The above timing applies to the following settings:

* Internal clock is selected.

fi: frequency of BRGi count source (f

1, f8, f32)

* CTS function is selected.

n: value set to BRGi

* CLK polarity select bit = 0 .

* Transmit interrupt cause select bit = 0 .

• Example of receive timing (when external clock is selected)

1

Receive enable

bit (RE)

0

1

Transmit enable

0

1

Dummy data is set in UARTi transmit buffer register

bit (TE)

Transmit buffer

empty flag (Tl)

0

Transferred from UARTi transmit buffer register to UARTi transmit register

H

RTSi

CLKi

RxDi

Even if the reception is completed, RTS do not assert,

and it is asserted by readout of receive buffer register.

L

1 / fEXT

Receive data is taken in

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

0

D

1

D

2

D

4

D5

D

7

D3

Transferred from UARTi receive register

to UARTi receive buffer register

Read out from UARTi receive buffer register

1

0

Receive complete

flag (Rl)

1

0

Receive interrupt

request bit (IR)

Cleared to 0 when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

Meet the following conditions are met when the CLK

input before data reception = H

The above timing applies to the following settings:

* External clock is selected.

* Transmit enable bit

* Receive enable bit

1

* RTS function is selected.

1

* CLK polarity select bit = 0 .

* Dummy data write to UARTi transmit buffer register

fEXT: frequency of external clock

Figure 1.15.12. Typical transmit/receive timings in clock synchronous serial I/O mode

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(a) Polarity select function

As shown in Figure 1.15.13, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16)

allows selection of the polarity of the transfer clock.

1. When CLK polarity select bit = 0

CLK

i

Note 1: The CLKi pin level when not

transferring data is H .

D0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

TXDi

D

0

D

1

D

2

D

D4

D

RXDi

2. When CLK polarity select bit = 1

CLK

i

Note 2: The CLKi pin level when not

transferring data is L .

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D7

TXDi

D

0

D

1

D

2

D

3

D

5

D

6

D7

RXDi

Figure 1.15.13. Polarity of transfer clock

(b) LSB first/MSB first select function

As shown in Figure 1.15.14, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,

037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.

1. When transfer format select bit = 0

CLK

i

D0

D

1

D

2

D

3

D

4

D

5

D

6

D7

TXDi

LSB first

D

1

D

2

D

3

D

5

D

6

D7

D

0

RXDi

2. When transfer format select bit = 1

CLK

i

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D0

TXDi

MSB first

D

6

D

5

D

4

D

2

D

1

D0

RXDi

Note: This applies when the CLK polarity select bit = 0 .

Figure 1.15.14. Transfer format

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(c) Transfer clock output from multiple pins function (UART1)

This function allows the setting two transfer clock output pins and choosing one of the two to output a

clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.15.15.)

The multiple pins function is valid only when the internal clock is selected for UART1.

Microcomputer

TXD

1

(P67

)

CLKS

1

(P6

4

)

CLK

(P65

IN

CLK

Note: This applies when the internal clock is selected and transmission

is performed only in clock synchronous serial I/O mode.

Figure 1.15.15. The transfer clock output from the multiple pins function usage

(d) Continuous receive mode

If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is

set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register

is read out, the SIO simultaneously goes to a receive enable state without having to write dummy data

to the transmit buffer register back again.

(e) Serial data logic switch function (UART2)

When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or

reading from receive buffer register, data is reversed. Figure 1.15.16 shows the example of serial data

logic switch timing.

ÄWhen LSB first

H

Transfer clock

L

H

TxD2

D0

D1

D2

D3

D4

D5

D6

D7

(no reverse)

L

H

L

TxD2

(reverse)

Figure 1.15.16. Serial data logic switch timing

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(f) CTS/RTS separate function (UART0)

This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0

from the P64 pin. To use this function, set the register bits as shown below.

• U0C0 register's CRD bit = 0 (enables UART0 CTS/RTS)

• U0C0 register's CRS bit = 1 (outputs UART0 RTS)

• U1C0 register's CRD bit = 0 (enables UART1 CTS/RTS)

• U1C0 register's CRS bit = 0 (inputs UART1 CTS)

• UCON register's RCSP bit = 1 (inputs CTS0 from the P64 pin)

• UCON register's CLKMD1 bit = 0 (CLKS1 not used)

Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be

used.

IC

Microcomputer

TX

D

0

(P6 )

3

IN

R

X

D

0

(P6

2

)

OUT

CLK

(P6

1

CLK

CTS

RTS

0

(P6

0

)

CTS

0

(P64

)

Figure 1.15.17. CTS/RTS separate function usage

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Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and

transfer data format. Tables 1.15.7 and 1.15.8 list the specifications of the UART mode. Figure

1.15.18 shows the UARTi transmit/receive mode register.

Table 1.15.7. Specifications of UART Mode (1)

Item

Specification

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit

Transfer data format

• Parity bit: Odd, even, or nothing as selected

• Stop bit: 1 bit or 2 bits as selected

Transfer clock

•

When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :

fi/16 (n+1) (Note 1)

fi = f1SIO, f2SIO, f8SIO, f32SIO

•

When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816 =“1”) :

fEXT/16(n+1) (Note 1) (Note 2)

Transmission/reception control • CTS function, RTS function, CTS and RTS function disabled: selectable

Transmission start condition • To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”

-

Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”

- When CTS function selected, CTS input level = “L”

Reception start condition • To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”

- Start bit detection

Interrupt request

generation timing

• When transmitting

- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at

address 037D16) = “0”: Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at

address 037D16) = “1”: Interrupts requested when data transmission from

UARTi transfer register is completed

• When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

• Overrun error (Note 3)

Generated 6.5, 7, or 8.5 clock periods after the device started receiving the

next data before reading out the contents of the UARTi receive buffer register.

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set

• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.

Note 2: fEXT is input from the CLKi pin.

Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

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Table 1.15.8. Specifications of UART Mode (2)

Item

Specification

• Serial data logic switch (UART2)

Select function

This function is reversing logic value of transferring data. Start bit,

parity bit and stop bit are not reversed.

• TXD, RXD I/O polarity switch (UART2)

This function is reversing TXD port output and RXD port input. All I/O

data level is reversed.

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Table 1.15.9 Registers used in UART mode and the register values set

Register

UiTB

Bit

0 to 8

Function

Set transmission data (Note 1)

Reception data can be read (Note 1)

UiRB

OER,FER,PER,SUM Error flag

UiBRG

UiMR

---

Set a transfer rate

SMD2 to SMD0

Set these bits to ‘1002’ when transfer data is 7 bits long

Set these bits to ‘1012’ when transfer data is 8 bits long

Set these bits to ‘1102’ when transfer data is 9 bits long

Select the internal clock or external clock

Select the stop bit

CKDIR

STPS

PRY, PRYE

IOPOL

CLK0, CLK1

CRS

Select whether parity is included and whether odd or even

Select the TxD/RxD input/output polarity

Select the count source for the UiBRG register

Select CTS or RTS to use

UiC0

TXEPT

CRD

Transmit register empty flag

Enable or disable the CTS or RTS function

Select TxDi pin output mode (Note 2)

Set to “0”

NCH

CKPOL

UFORM

LSB first or MSB first can be selected when transfer data is 8 bits long. Set this

bit to “0” when transfer data is 7 or 9 bits long.

Set this bit to “1” to enable transmission

Transmit buffer empty flag

UiC1

TE

TI

RE

Set this bit to “1” to enable reception

Reception complete flag

RI

U2IRS (Note 2)

U2RRM (Note 2)

UiLCH

Select the source of UART2 transmit interrupt

Set to “0”

Set this bit to “1” to use inverted data logic

Set to “0”

UiERE

UiSMR

0 to 7

Set to “0”

UiSMR2

UiSMR3

0 to 7

Set to “0”

0 to 7

Set to “0”

UiSMR4

UCON

0 to 7

Set to “0”

U0IRS, U1IRS

U0RRM, U1RRM

CLKMD0

CLKMD1

RCSP

Select the source of UART0/UART1 transmit interrupt

Set to “0”

Invalid because CLKMD1 = 0

Set to “0”

Set this bit to “1” to accept as input the UART0 CTS0 signal from the P64 pin

Set to “0”

7

Note 1: The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long;

bit 0 to bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.

Note 2: Set the U0C1 and U1C1 registers bit 4 to bit 5 to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits

are included in the UCON register.

Note 3: TxD2 pin is N channel open-drain output. Set the U2C0 register's NCH bit to “0”.

i=0 to 2

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UARTi transmit / receive mode registers

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

UiMR(i=0,1)

Address

03A016, 03A816

When reset

0016

R W

Bit symbol

Bit name

Function

b2 b1 b0

SMD0

SMD1

SMD2

CKDIR

Serial I/O mode select bit

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

Internal / external clock

select bit

0 : Internal clock

1 : External clock (Note)

STPS

PRY

Stop bit length select bit

0 : One stop bit

1 : Two stop bits

Odd / even parity

select bit

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

PRYE

Parity enable bit

0 : Parity disabled

1 : Parity enabled

Reserved Must always be "0".

Note: Set the corresponding port direction register to "0".

UART2 transmit / receive mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

U2MR

Address

037816

When reset

0016

R W

Bit symbol

Bit name

Function

b2 b1 b0

SMD0

SMD1

SMD2

CKDIR

Serial I/O mode select bit

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long

1 1 0 : Transfer data 9 bits long

Internal / external clock

select bit

Must always be fixed to “0”

STPS

PRY

Stop bit length select bit

0 : One stop bit

1 : Two stop bits

Odd / even parity

select bit

Valid when bit 6 = “1”

0 : Odd parity

1 : Even parity

PRYE

Parity enable bit

0 : Parity disabled

1 : Parity enabled

IOPOL

TxD, RxD I/O polarity

reverse bit (Note)

0 : No reverse

1 : Reverse

Note: Usually set to “0”.

Figure 1.15.18. UARTi transmit/receive mode register in UART mode

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Table 1.15.10 lists the functions of the input/output pins during UART mode. Note that for a period

from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”.

(If the N-channel open-drain is selected, this pin is in floating state.)

Table 1.15.10. Input/output pin functions in UART mode

Pin name

TxDi

(P6 , P67, P70)

Function

Method of selection

Serial data output

3

RxDi

(P6 , P6

Serial data input

Port P6

bit 1 of address 03EF16)= 0

(Can be used as an input port when performing transmission only)

2

, P6

6

and P7

1

direction register (bits 2 and 6 of address 03EE16,

2

6

, P7

1

)

CLKi

(P6 , P6

Programmable I/O port

Transfer clock input

Internal/external clock select bit (bit 3 of address 03A016, 03A816, 037816) = 0

Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = 1

1

5

, P7

2

Port P61, P65 and P72 direction register (bits 1 and 5 of address 03EE16) = 0

(Do not use external for UART2)

CTSi/RTSi

(P6 , P6 , P73)

CTS/RTS disable bit (bit 4 of address 03A416, 03AC16, 037C16) = 0

CTS/RTS function select bit (bit 2 of address 03A416, 03AC16, 037C16) = 0

Port P60, P64 and P73 direction register (bits 0 and 4 of address 03EE16,

CTS input

0

4

bit 3 at address 03EF16) = 0

CTS/RTS disable bit (bit 4 of address 03A416, 03AC16, 037C16) = 0

CTS/RTS function select bit (bit 2 of address 03A416, 03AC16, 037C16) = 1

RTS output

Programmable I/O port

CTS/RTS disable bit (bit 4 of address 03A416, 03AC16, 037C16) = 1

Table 1.15.11. P64 pin function in UART mode

Pin function

Bit set value

UCON register

U1C0 register

PD6 register

PD6_4

CLKMD1

RCSP

CRS

CRD

P6

4

1

0

1

0

Input: 0, Output: 1

0

CTS

1

0

1

0

RTS

CTS

0

(Note)

0

Note: In addition to this, set the U0C0 register’s CRD bit to “0” (CTS

0/RTS0

enabled) and the U0C0 register’s CRS bit to “1” (RTS selected).

0

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• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

The transfer clock stops momentarily as CTS is H when the stop bit is checked.

The transfer clock starts as the transfer starts immediately CTS changes to L .

Tc

Transfer clock

1

Transmit enable

bit(TE)

0

1

0

Data is set in UARTi transmit buffer register.

Transmit buffer

empty flag(TI)

Transferred from UARTi transmit buffer register to UARTi transmit register

H

L

CTSi

Stopped pulsing because transmit enable bit = 0

Start

bit

Parity Stop

bit bit

TxDi

ST

D0

D1

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

SP

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

D

6

D

6

SP

1

0

Transmit register

empty flag (TXEPT)

1

0

Transmit interrupt

request bit (IR)

Cleared to 0 when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT

The above timing applies to the following settings :

* Parity is enabled.

fi : frequency of BRGi count source (f1SIO, f2SIO, f8SIO, f32SIO

)

fEXT : frequency of BRGi count source (external clock)

* One stop bit.

n : value set to BRGi

* CTS function is selected.

* Transmit interrupt cause select bit = 1 .

• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Tc

Transfer clock

1

Transmit enable

bit(TE)

Data is set in UARTi transmit buffer register

0

1

Transmit buffer

empty flag(TI)

0

Transferred from UARTi transmit buffer register to UARTi transmit register

Start

bit

Stop Stop

bit

TxDi

ST

D0

D1

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

D

8

ST

D

0

D

1

D

2

D

3

D

4

D5

D

7

D8

SPSP

D

6

SP SP

D

6

1

0

Transmit register

empty flag (TXEPT)

1

0

Transmit interrupt

request bit (IR)

Cleared to 0 when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings :

* Parity is disabled.

* Two stop bits.

Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT

fi : frequency of BRGi count source (f1SIO, f2SIO, f8SIO, f32SIO

EXT : frequency of BRGi count source (external clock)

n : value set to BRGi

)

f

* CTS function is disabled.

* Transmit interrupt cause select bit = 0 .

Figure 1.15.19. Typical transmit timing in UART mode (UART0, UART1)

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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Tc

Transfer clock

1

Transmit enable

bit(TE)

Data is set in UART2 transmit buffer register

0

1

Note

Transmit buffer

empty flag(TI)

0

Transferred from UART2 transmit buffer register to UARTi transmit register

Parity

bit

Stop

bit

Start

bit

TxD

2

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

D

6

SP

D

6

SP

1

0

Transmit register

empty flag (TXEPT)

1

0

Transmit interrupt

request bit (IR)

Cleared to

0 when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings :

* Parity is enabled.

* One stop bit.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO

n : value set to BRG2

)

* Transmit interrupt cause select bit = 1 .

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

Figure 1.15.20. Typical transmit timing in UART mode (UART2)

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

BRGi count

source

1

Receive enable bit

0

Stop bit

Start bit

D

1

D7

RxDi

D0

Sampled L

Receive data taken in

Transfer clock

Transferred from UARTi receive register to

UARTi receive buffer register

Reception triggered when transfer clock

is generated by falling edge of start bit

1

Receive

complete flag

0

H

L

RTSi

Receive interrupt

request bit

1

0

Cleared to 0 when interrupt request is accepted, or cleared by software

The above timing applies to the following settings :

* Parity is disabled.

* One stop bit.

* RTS function is selected.

Figure 1.15.21. Typical receive timing in UART mode

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(a) Function for switching serial data logic (UART2)

When the data logic select bit (bit 6 of address 037D16) is assigned 1, data is inverted in writing to

the transmission buffer register or reading the reception buffer register. Figure 1.15.22 shows the

example of timing for switching serial data logic.

When LSB first, parity enabled, one stop bit

H

Transfer clock

L

H

TxD

2

ST

D0

D1

D2

D3

D4

D5

D6

D7

P

SP

(no reverse)

L

H

L

TxD

2

(reverse)

ST : Start bit

P : Even parity

SP : Stop bit

Figure 1.15.22. Timing for switching serial data logic (UART2)

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(b) TxD, RxD I/O polarity reverse function (UART2)

This function reverses/inverts TXD pin output and RXD pin input. The level of any data to be input or

output (including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not re-

versed/inverted) for normal use.

(c) Bus collision detection function (UART2)

This function samples the output level of the TXD pin and the input level of the RXD pin at the rising

edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.15.23

shows the example of detection timing of a bus collision (in UART mode).

H

Transfer clock

L

H

TxD

2

ST

SP

L

H

L

RxD

Bus collision detection

interrupt request signal

1

0

Bus collision detection

interrupt request bit

1

0

ST : Start bit

SP : Stop bit

Figure 1.15.23. Detection timing of a bus collision (in UART mode)

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Clock-Asynchronous Serial I/O Mode (used for SIM interface)

The SIM (Subscriber Identity Module) interface is used for connecting the microcomputer with a memory

card or the like; adding some extra settings in UART2 clock-asynchronous serial I/O mode allows the user

to use this function. Table 1.15.12 shows the specifications of clock-asynchronous serial I/O mode (used

for SIM interface).

Table 1.15.12. Specifications of clock-asynchronous serial I/O mode (used for SIM interface)

Item

Specification

• Transfer data 8-bit UART mode (bit 2, bit1, bit 0 of address 0378¹⁶= “101

2”)

Transfer data format

• One stop bit (bit 4 of address 037816 = “0”)

• With the direct format chosen

Set parity to “even” (bit 5, bit 6 of address 0378¹⁶= “11

2”)

Set data logic to “direct” (bit 6 of address 037D¹⁶= “0”)

Set transfer format to LSB (bit 7 of address 037C¹⁶= “0”)

• With the inverse format chosen

Set parity to “odd” (bit 5, bit 6 of address 0378¹⁶= “01 ”)

2

Set data logic to “inverse” (bit 6 of address 037D¹⁶= “1”)

Set transfer format to MSB (bit 7 of address 037C¹⁶= “1”)

• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1)

(Note 1) : fi = f1SIO, f2SIO, f8SIO, f32SIO (Do not set external clock)

• Disable the CTS and RTS function (bit 4 of address 037C¹⁶= “1”)

• UART2 does not support sleep mode function.

• Set transmission interrupt factor to “transmission completed” (bit 4 of

address 037D¹⁶= “1”)

Transfer clock

Transmission/reception control

Other settings

Transmission start condition

Reception start condition

• To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 of address 037D¹⁶) = “1”

- Transmit buffer empty flag (bit 1 of address 037D¹⁶) = “0”

• To start reception, the following requirements must be met:

- Reception enable bit (bit 2 of address 037D¹⁶) = “1”

- Detection of a start bit

Interrupt request

generation timing

• When transmitting

When data transmission from the UART2 transmit register is completed

(bit 4 of address 037D¹⁶= “1”)

• When receiving

When data transfer from the UART2 receive register to the UART2 receive

buffer register is completed

• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)

• Framing error (see the specifications of clock-asynchronous serial I/O)

• Parity error (see the specifications of clock-asynchronous serial I/O)

- On the reception side, an “L” level is output from the TXD2 pin by use of

Error detection

the parity error signal output function (bit 7 of address 037D¹⁶= “1”)

when a parity error is detected

- On the transmission side, a parity error is detected by the level of input to

the RXD2 pin when a transmission interrupt occurs

• The error sum flag (see the specifications of clock-asynchronous serial I/O)

.

Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator.

.

Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. In addition, the

UART2 receive interrupt request bit does not change.

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Tc

Transfer clock

1

Transmit enable

bit(TE)

0

1

Data is set in UART2 transmit buffer register

Transmit buffer

empty flag(TI)

0

Transferred from UART2 transmit buffer register to UART2 transmit register

Start

bit

Parity

bit

Stop

bit

TxD

2

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

P

SP

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

P

SP

RxD

2

An

L level returns from TxD2 due to

the occurrence of a parity error.

Signal conductor level

(Note)

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

The level is

D

6

SP

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D7

detected by the

interrupt routine.

The level is detected by the

interrupt routine.

1

0

Transmit register

empty flag (TXEPT)

1

0

Transmit interrupt

request bit (IR)

Cleared to 0 when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO

The above timing applies to the following settings :

* Parity is enabled.

)

n : value set to BRG2

* One stop bit.

* Transmit interrupt cause select bit = 1 .

Note : Equal in waveform because TxD

2

and RxD

2

are connected.

Tc

Transfer clock

1

Receive enable

bit (RE)

0

Parity

bit

Stop

bit

Start

bit

SP

RxD

TxD

2

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

ST

D

0

D

1

D

2

D

3

D

4

D

5

D

7

P

D

6

SP

D6

2

An

L level returns from TxD2 due to

the occurrence of a parity error.

Signal conductor level

(Note)

SP

ST

D

7

P

D

0

D

1

D

2

D

3

D

4

D

5

D7

D

SP

D6

1

Receive complete

flag (RI)

0

Read to receive buffer

1

0

Receive interrupt

request bit (IR)

Cleared to 0 when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings :

* Parity is enabled.

* One stop bit.

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f1SIO, f2SIO, f8SIO, f32SIO

n : value set to BRG2

)

* Transmit interrupt cause select bit = 0 .

Note : Equal in waveform because TxD2 and RxD2 are connected.

Figure 1.15.24. Typical transmit/receive timing in UART mode (used for SIM interface)

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(a) Function to output a parity error signal

During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you

can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission,

comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is as-

signed “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock.

Therefore parity error signals can be detected by a transmission completion interrupt program. Figure

1.15.25 shows the output timing of the parity error signal.

LSB first

H

Transfer

L

clock

H

ST

D0

D1

D2

D3

D4

D5

D6

D7

P

SP

RxD

TxD

2

L

H

L

Hi-Z

2

1

0

Receive

complete flag

ST : Start bit

P : Even Parity

SP : Stop bit

Figure 1.15.25. Output timing of the parity error signal

(b) Direct format/inverse format

Connecting the SIM card allows you to switch between direct format and inverse format. If you choose

the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted

and output from TxD2.

Figure 1.15.26 shows the SIM interface format.

Transfer

clcck

TxD

(direct)

2

D0

D7

D1

D6

D2

D5

D3

D4

D3

D5

D2

D6

D1

D7

D0

P

TxD

(inverse)

2

P : Even parity

Figure 1.15.26. SIM interface format

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Figure 1.15.27 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and

apply pull-up.

Microcomputer

SIM card

TxD

2

RxD

Figure 1.15.27. Connecting the SIM interface

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UART2 Special Mode Register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register

The UART2 special mode register (address 037716) is used to control UART2 in various ways.

2

Bit 0 of the UART2 special mode register are used as the I C mode select bit.

2

Setting “1” in the I C mode select bit (bit 0) goes the circuit to achieve the I C bus (simplified I C bus)

interface effective.

2

Table 1.15.13 shows the relation between the I C mode select bit and respective control workings.

Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.

2

Table 1.15.13. Features in I C mode

2

Function

Normal mode

I C mode (Note 1)

Start condition detection or stop

condition detection

Bus collision detection

1

Factor of interrupt number 10 (Note 2, 4)

2

3

4

5

6

7

8

Factor of interrupt number 15 (Note 2)

Factor of interrupt number 16 (Note 2)

UART2 transmission output delay

UART2 transmission

UART2 reception

Not delayed

No acknowledgment detection (NACK)

Acknowledgment detection (ACK)

Delayed

P

SDA (input/output) (Note 3)

SCL (input/output)

70

71

72

TxD2 (output)

RxD2 (input)

at the time when UART2 is in use

P

CLK2

P

72

DMA1 factor at the time when 1101 is assigned to

the DMA request factor selection bits

UART2 reception

Acknowledgment detection (ACK)

15ns

Noise filter width

9

200ns

Reading the terminal when 0 is

assigned to the direction register

Reading the terminal regardless of the

value of the direction register

Reading P

10

71

H level (when 0 is assigned to

the CLK polarity select bit)

The value set in latch P when the

70

11 Initial value of UART2 output

port is selected (Note 3)

2

Note 1: Make the settings given below when I C mode is in use.

Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.

Disable the RTS/CTS function. Choose the MSB First function.

Note 2: Follow the steps given below to switch from a factor to another.

1. Disable the interrupt of the corresponding number.

2. Switch from a factor to another.

3. Reset the interrupt request flag of the corresponding number.

4. Set an interrupt level of the corresponding number.

Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.

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UART2 Special Mode Register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

TxD2/SDA2

Timer

I/O

IICM=1

To DMA0, DMA1

Selector

UART2

IICM=0

or IICM2=1

UART2 transmission/NACK

interrupt request

UARTi

Transmission

register

Analog

delay

IICM=1

and IICM2=0

IICM=0

SDHI

ALS

D

Q

Arbitration

T

Noize

Filter

Timer

To DMA0, DMA1

IICM=1

IICM=0

or IICM2=1

UART2 reception/ACK interrupt

request, DMA1 request

Reception register

UART2

IICM=0

IICM=1

Start condition

detection

and IICM2=0

S

Q

Bus busy

R

Stop condition

detection

NACK

D

Q

L-synchronous

output enabling

bit

Falling edge

detection

T

D

Q

RxD2/SCL2

I/O

R

ACK

T

Q

Data bus

1 output data latch)

9th pulse

(Port P7

UARTi

Selector

Bus collision/start, stop condition

detection interrupt request

IICM=1

IICM=0

Internal clock

Bus collision

detection

UARTi

IICM=1

SWC2

CLK

control

Noize

Filter

IICM=1

External clock

Noize

Filter

Falling edge of 9 bit

SWC

IICM=0

Port reading

With IICM set to 1, the port terminal is to be readable

UART2

IICM=0

*

CLK2

even if 1 is assigned to P71 of the direction register.

Selector

I/O

Timer

2

Figure 1.15.28. Functional block diagram for I C mode

2

Figure 1.15.28 shows the functional block diagram for I C mode.

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UART2 Special Mode Register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Setting “1” in the I2C mode select bit (IICM) causes ports to work as data transmission-reception terminal

SDAi, clock input-output terminal SCLi, and port respectively. A delay circuit is added to the SDA2 trans-

mission output, so the SDA2 output changes after SCL2 fully goes to “L”.

An attempt to read Port (SCL2) results in getting the terminal’s level regardless of the content of the port

direction register. The initial value of SDA2 transmission output in this mode goes to the value set in port.

The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2

reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection

interrupt, and acknowledgment detection interrupt respectively.

The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA2

terminal is detected with the SCL2 terminal staying “H”. The stop condition detection interrupt refers to

the interrupt that occurs when the rising edge of the SDA2 terminal is detected with the SCL2 terminal

staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the start condition

detection, and set to “0” by the stop condition detection.

The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA2 terminal

level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment

detection interrupt refers to the interrupt that occurs when SDA2 terminal’s level is detected already went

to “L” at the 9th transmission clock. Also, assigning (UART2 reception) to the DMA1 request factor select

bits provides the means to start up the DMA transfer by the effect of acknowledgment detection.

Bit 1 of the UART2 special mode register is used as the arbitration lost detecting flag control bit. Arbitra-

tion means the act of detecting the nonconformity between transmission data and SDA2 terminal data at

the timing of the SCL2 rising edge. This detecting flag is located at bit 11 of the UART2 reception buffer

register, and “1” is set in this flag when nonconformity is detected. Use the arbitration lost detecting flag

control bit to choose which way to use to update the flag, bit by bit or byte by byte. When setting this bit to

“1” and updated the flag byte by byte if nonconformity is detected, the arbitration lost detecting flag is set

to “1” at the falling edge of the 9th transmission clock.

If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-

ing the first byte acknowledge detect and before starting the next one byte transmission.

Bit 3 of the UART2 special mode register is used as SCL2- and L-synchronous output enable bit. Setting

this bit to “1” goes the port data register to “0” in synchronization with the SCL2 terminal level going to “L”.

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UART2 Special Mode Register

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Some other functions added are explained here. Figure 1.15.29 shows their workings.

Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The

bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the noncon-

formity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”.

If this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer Aj rather than at

the rising edge of the transfer clock.

Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable

bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus

collision detect interrupt request bit (nonconformity).

Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit

to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.

1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)

0: Rising edges of the transfer clock

CLK

TxD/RxD

Timer A0

1: Timer A0 overflow

2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)

CLK

TxD/RxD

Bus collision

detect interrupt

request bit

Transmit

enable bit

3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)

0: In normal state

CLK

TxD

Enabling transmission

With "1: falling edge of RxD2" selected

CLK

TxD

RxD

Figure 1.15.29. Some other functions added

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UART2 Special Mode Register 2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2

2

UARTi special mode register 2 (address 037616) is used to further control UART2 in I C mode.

2

Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I C mode select bit 2. Table

2

1.15.14 shows the types of control to be changed by I C mode select bit 2 when the I C mode select bit

is set to “1”. Table 1.15.15 shows the timing characteristics of detecting the start condition and the stop

condition.

2

Table 1.15.14. Functions changed by I C mode select bit 2

IICM2 = 1

Function

IICM2 = 0

1

2

UART2 transmission (the rising edge

of the final bit of the clock)

Factor of interrupt number 15

No acknowledgment detection (NACK)

Factor of interrupt number 16

Acknowledgment detection (ACK)

UART2 reception (the falling edge of

the final bit of the clock)

3

DMA1 factor at the time when 1101 is

assigned to the DMA request factor

selection bits.

UART2 reception (the falling edge of

the final bit of the clock)

4

5

Timing for transferring data from the

UART2 reception shift register to the

reception buffer.

The rising edge of the final bit of the

reception clock

The falling edge of the final bit of the

reception clock

Timing for generating a UART2

reception/ACK interrupt request

The rising edge of the final bit of the

reception clock

The falling edge of the final bit of the

reception clock

Table 1.15.15. Timing characteristics of detecting the start condition and the stop condition (Note 1)

3 to 6 cycles < duration for setting-up (Note)

3 to 6 cycles < duration for holding (Note)

Note: Cycles is in terms of the input oscillation frequency f(XIN) of the main clock.

Duration for

setting up

Duration for

holding

SCL

SDA

(Start condition)

SDA

(Stop condition)

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UART2 Special Mode Register 2

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bit 3 of the UARTi special mode register 2 are used as the SDAi output stop bit. Setting this bit to “1”

causes an arbitration loss to occur, and the SDAi pin turns to high-impedance state at the instant when

the arbitration lost detecting flag is set to “1”.

Bit 1 of the UART2 special mode register 2 are used as the clock synchronization bit. With this bit set to

“1” at the time when the internal SCL2 is set to “H”, the internal SCL2 turns to “L” if the falling edge is

found in the SCL2 pin; and the baud rate generator reloads the set value, and start counting within the “L”

interval.

When the internal SCL2 changes from “L” to “H” with the SCL2 pin set to “L”, stops counting the baud rate

generator, and starts counting it again when the SCL2 pin turns to “H”. Due to this function, the UART2

transmission-reception clock becomes the logical product of the signal flowing through the internal SCL2

and that flowing through the SCL2 pin. This function operates over the period from the moment earlier by

a half cycle than falling edge of the UART2 first clock to the rising edge of the ninth bit. To use this

function, choose the internal clock for the transfer clock.

Bit 2 of the UART2 special mode register 2 are used as the SCL2 wait output bit. Setting this bit to “1”

causes the SCL2 pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to “0”

frees the output fixed to “L”.

Bit 4 of the UART2 special mode register 2 are used as the UART2 initialization bit. Setting this bit to “1”,

and when the start condition is detected, the microcomputer operates as follows.

(1) The transmission shift register is initialized, and the content of the transmission register is transferred

to the transmission shift register. This starts transmission by dealing with the clock entered next as the

first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the

entrance of the clock, and remains unchanged from the value at the moment when the microcomputer

detected the start condition.

(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the

clock entered next as the first bit.

(3) The SCL2 wait output bit turns to “1”. This turns the SCL2 pin to “L” at the falling edge of the ninth bit

of the clock.

Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the

transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.

Bit 5 of the UART2 special mode register 2 are used as the SCL2 pin wait output bit 2. Setting this bit to

“1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL2 pin even if UART2

is in operation. Setting this bit to “0” frees the “L” output from the SCL2 pin, and the UART2 clock is input/

output.

Bit 6 of the UART2 special mode register 2 are used as the SDA2 output disable bit. Setting this bit to “1”

forces the SDA2 pin to turn to the high-impedance state. Refrain from changing the value of this bit at the

rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting flag is

turned on.

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UART2 Special Mode Register 3

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 3

Bit 1 of UART2 special mode register 3 (address 037516) are used to clock phase set bit. Figure1.15.9

shows UART2 special mode register 3.

When both the IIC mode select bit (bit 0 of UART2 special mode select register) and the IIC mode select

bit 2 (bit 0 of U2SMR2 register) are “1”, functions changed by these bits are shown in table 1.15.16 and

figure 1.15.30.

Bits 5 to 7 of UART2 special mode register 3 are SDA digital delay setting bits. By setting these bits, it is

possible to turn the SDA delay OFF or set the BRG count source delay to 2 to 8 cycles.

Table 1.15.16. Functions changed by clock phase set bits

Function

CKPH = 0, IICM = 1, IICM2 = 1 CKPH = 1, IICM = 1, IICM2 = 1

Initial value = H, last value = L Initial value = L, last value = L

SCL initial and last value

Transfer interrupt factor

Data transfer times from UART

receive shift register to receive Falling edge of 9th bit

buffer register

Rising edge of 9th bit

Falling edge of 10th bit

Two times :falling edge of 9th bit

and rising edge of 9th bit

(1) CKPH= "0" (IICM=1, IICM2=1)

SCL

D7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D8

SDA

(Internal clock, transfer data 9 bits long and MSB first selected.)

Receive interrupt

Transmit interrupt

Transfer to receive buffer

(2) CKPH= "1" (IICM=1, IICM2=1)

SCL

D7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

D8

SDA

(Internal clock, transfer data 9 bits long and MSB first selected.)

Receive interrupt

Transmit interrupt

Transfer to receive buffer

Figure 1.15.30. Functions changed by clock phase set bits

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UART2 Special Mode Register 4

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 4

Bit 0 of UART2 special mode register 4 (address 037416) are used to start condition generate bit. When

the SCL, SDA output select bit (bit 3 of U2SMR4 register) is “1” and this bit is “1”, then the start condition

is generated.

Bit 1 of UART2 special mode register 4 are used to restart condition generate bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is “1” and this bit is “1“, then the restart

condition is generated.

Bit 2 of UART2 special mode register 4 are used to stop condition generate bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is “1” and this bit is “1”, then the stop

condition is generated.

Bit 3 of UART2 special mode register 4 are used to SCL, SDA output select bit.

Functions changed by these bits are shown in table 1.15.17 and figure 1.15.31.

Bit 4 of UART2 special mode register 4 are used to ACK data bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is “0” and the ACK data output enable bit

(bit 5 of U2SMR4 register) is “1”, then the content of ACK data bit is output to SDA pin.

Bit 5 of UART2 special mode register 4 are used to ACK data output enable bit.

When the SCL, SDA output select bit (bit 3 of U2SMR4 register) is “0” and this bit is “1”, then the content

of ACK data bit is output to SDA pin.

Bit 6 of UART2 special mode register 4 are used to SCL output stop bit.

When this bit is “1”, SCL output is stopped at stop condition detection. (Hi-impedance status).

Bit 7 of UART2 special mode register 4 are used to SCL wait output bit.

When this bit is “1”, SCL output is fixed to "L" at falling edge of 10th bit of clock. When this bit is “0”, SCL

output fixed to “L” is released.

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UART2 Special Mode Register 4

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.15.17. Functions changed by SCL, SDA output select bit

Function

STSPSEL = 0

STSPSEL = 1

SCL, SDA output

Output of SI/O control circuit

Output of start/stop

conditioncontrol circuit

Completion of start/stop condition

generation

Start/stop condition interrupt factor Start/stop condition detection

(1) When slave mode (CKDIR=0, STSPSEL=0)

SCL

SDA

Start condition detection

interrupt

Stop condition detection

interrupt

(2) When master mode (CKDIR=1, STSPSEL=1)

STSPSEL=0 STSPSEL=1

STSPSEL=0

STSPSEL=1 STSPSEL=0

SCL

SDA

STAREQ=1

Start condition detection

interrupt

STPREQ=1

Stop condition detection

interrupt

Figure 1.15.31 Functions changed by SCL, SDA output select bit

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Serial Interface Special Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial Interface Special Function

UARTi can control communications on the serial bus (Figure 1.15.32). The master outputting the transfer

clock transfers data to the slave inputting the transfer clock. In this case, in order to prevent a data

collision on the bus, the master floats the output pin of other slaves/masters using the SSi input pins.

IC1

IC2

P1

3

2

P9

3

P72(CLK2)

P71(RxD2)

P70(TxD2)

P72(CLK2)

P71(RxD2)

P70(TxD2)

M16C/26 (Master)

M16C/26 (Slave)

IC3

P9

3

P72(CLK2)

P71(RxD2)

P70(TxD2)

M16C/26 (Slave)

Figure 1.15.32. Programmable serial bus communication control example

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Serial Interface Special Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

• Clock Phase Setting

With bit 1 of UART2 special mode register 3 (addresses 036D16, 037116 and 037516) and bit 6 of

UART2 transmission-reception control register 0 (addresses 03A416, 02AC16 and 037C16), four com-

binations of transfer clock phase and polarity can be selected.

Bit 6 of UART2 transmission-reception control register 0 sets transfer clock polarity, whereas bit 1 of

U2SMR3 register sets transfer clock phase.

Transfer clock phase and polarity must be the same between the master and slave involved in the

transfer.

(a) Master (Internal Clock)

Figure 1.15.33 shows the transmission and reception timing.

(b) Slave (External Clock)

• Figure 1.15.34 shows the timing when bit 1 of address 037516)=“0”

• Figure 1.15.35 shows the timing when bit 1 of address037516)=“1”

"H"

Clock output

"L"

(CKPOL=0, CKPH=0)

"H"

"L"

Clock output

(CKPOL=1, CKPH=0)

Clock output

(CKPOL=0, CKPH=1)

"H"

"L"

"H"

"L"

Clock output

(CKPOL=1, CKPH=1)

"H"

"L"

Data output timing

Data input timing

D0

D

1

D

2

D

3

D

4

D

5

D

6

D7

Figure 1.15.33. The transmission and reception timing in master mode (internal clock)

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Serial Interface Special Function

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

"H"

Slave control input

"L"

"H"

Clock input

"L"

(CKPOL=0, CKPH=0)

"H"

"L"

Clock input

(CKPOL=1, CKPH=0)

"H"

"L"

Data output timing

(Note)

D

0

D

1

D

2

D

3

D

4

D5

D

6

D7

High-

inpedance

High-

inpedance

Data input timing

Indeterminate

Note :UART2 output is an N-channel open drain and needs to be pulled-up externally.

Figure 1.15.34. The transmission and reception timing (CKPH=0) in slave mode (external clock)

"H"

Slave control input

"L"

"H"

Clock input

"L"

(CKPOL=0, CKPH=0)

"H"

"L"

Clock input

(CKPOL=1, CKPH=0)

"H"

"L"

Data output timing

(Note)

D

0

D1

D2

D

3

D

4

D

5

D

6

D7

High-

inpedance

High-

inpedance

Data input timing

Note :UART2 output is an N-channel open drain and needs to be pulled-up externally.

Figure 1.15.35. The transmission and reception timing (CKPH=1) in slave mode (external clock)

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A-D Converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P10 to P10 also function as the analog signal input pins AN to AN . The direction registers of these pins

0

7

0

7

for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the

resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used.

Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the

A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF

.

The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits

are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are

stored in the even addresses. Table 1.16.1 shows the performance of the A-D converter. Figure 1.16.1 shows the

block diagram of the A-D converter, and Figures 1.16.2 and 1.16.3 show the A-D converter-related registers.

Table 1.16.1. Performance of A-D converter

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AVCC (VCC)

Operating clock fAD (Note 2) fAD, fAD/2, fAD/3, fAD/4, fAD/6, or fAD/12 where fAD=f(XIN)

Resolution

8-bit or 10-bit (selectable)

Integral nonlinearity error When AVCC = VREF = 5V

• With 8-bit resolution: 2LSB

• With 10-bit resolution: 3LSB

When AVCC = VREF = 3.3V

• With 8-bit resolution: 2LSB

• With 10-bit resolution: 5LSB

Operating modes

Analog input pins

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

8pins (AN0 to AN7)

A-D conversion start condition • Software trigger

A-D conversion starts when the A-D conversion start flag changes to “1”

• External trigger (can be retriggered)

A-D conversion starts when the A-D conversion start flag is “1” and the

ADTRG/P15 input (shared with INT3) changes from “H” to “L”

Conversion speed per pin • Without sample and hold function

8-bit resolution: 49 AD cycles 10-bit resolution: 59

• With sample and hold function

8-bit resolution: 28 AD cycles 10-bit resolution: 33

f

,

f

AD cycles

f

,

f

Note 1: Does not depend on use of sample and hold function.

Note 2: Divide the fAD if f(XIN) exceeds 10MHZ, and make fAD frequency equal to or less than 10MHz.

Without sample and hold function, set the

f

AD frequency to 250kHZ min.

With the sample and hold function, set the

f

AD frequency to 1MHZ min.

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A-D Converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D conversion rate

selection

CKS1=1

CKS2=0

ø

AD

CKS0=1

CKS0=0

CKS1=0

1/2

fAD

1/3

CKS2=1

V

REF

VCUT=0

VCUT=1

Resistor ladder

AVSS

Successive conversion register

A-D control register 1

(address 03D716

)

A-D control register 0

(address 03D616

)

Addresses

(03C116, 03C016

)

A-D register 0(16)

A-D register 1(16)

A-D register 2(16)

A-D register 3(16)

A-D register 4(16)

A-D register 5(16)

A-D register 6(16)

A-D register 7(16)

(03C316, 03C216

)

(03C516, 03C416

Decoder

for A-D register

(03C716, 03C616

(03C916, 03C816

(03CB16, 03CA16

(03CD16, 03CC16

(03CF16, 03CE16

)

Data bus high-order

Data bus low-order

0 0 0

A-D control register 2

(address 03D416

)

PM00

PM01

V

ref

IN

Decoder

for channel

selection

Comparator

V

CH2,CH1,CH0

=000

Port P2 group

P10

0

1

2

3

4

5

6

7

/AN

0

1

2

3

4

5

6

7

=001

=010

=011

=100

=101

=110

=111

Figure 1.16.1. Block diagram of A-D converter

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A-D Converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D control register 0 (Note 1)

Symbol

ADCON0

Address

03D616

When reset

00000XXX2

b7 b6 b5 b4 b3 b2 b1 b0

R W

Bit symbol

Bit name

Function

0 is selected

b2 b1 b0

CH0

0 0 0 : AN

0 0 1 : AN

0 1 0 : AN

0 1 1 : AN

1 0 0 : AN

1 0 1 : AN

1 1 0 : AN

1 1 1 : AN

b4 b3

Analog input pin select bit

1

is selected

2

3

4

5

6

7

CH1

CH2

MD0

MD1

(Note 2)

A-D operation mode

select bit 0

0 0 : One-shot mode

0 1 : Repeat mode

1 0 : Single sweep mode

1 1 : Repeat sweep mode 0

Repeat sweep mode 1

Trigger select bit

0 : Software trigger

1 : ADTRG trigger

TRG

ADST

CKS0

A-D conversion start flag

0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit

Refer to table 1.16.2

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON1

Address

03D716

When reset

0016

Bit symbol

Bit name

Function

R W

When single sweep and repeat sweep

A-D sweep pin select bit

mode 0 are selected

b1 b0

SCAN0

SCAN1

0 0 : AN

0 1 : AN

1 0 : AN

1 1 : AN

0

, AN

1

(2 pins)

to AN

3

5

7

(4 pins)

(6 pins)

(8 pins)

When repeat sweep mode 1 is selected

b1 b0

0 0 : AN

0 1 : AN

1 0 : AN

1 1 : AN

0

(1 pin)

, AN

1

(2 pins)

to AN

2

3

(3 pins

(4 pins)

A-D operation mode

select bit 1

0 : Any mode other than repeat sweep

mode 1

1 : Repeat sweep mode 1

MD2

8/10-bit mode select bit

0 : 8-bit mode

1 : 10-bit mode

BITS

CKS1

Frequency select bit

Vref connect bit

Refer to table 1.16.2

0 : Vref not connected

1 : Vref connected

VCUT

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Figure 1.16.2. A-D converter control registers (1)

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A-D Converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D control register 2 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON2

Address

03D416

When reset

0

0016

Bit symbol

SMP

Bit name

Function

R W

0 : Without sample and hold

1 : With sample and hold

A-D conversion method

select bit

Must always be set to 0

Refer to table 1.16.2

Reserved bits

CKS2

Frequency select bit 2

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if read, turns out to be 0 .

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Symbol

ADi(i=0 to 7)

Address

When reset

A-D register i

(b15)

b7

03C016 to 03CF16 Indeterminate

(b8)

b0 b7

b0

Function

R W

Eight low-order bits of A-D conversion result

During 10-bit mode

Two high-order bits of A-D conversion result

During 8-bit mode

When read, the content is indeterminate

Nothing is assigned.

In an attempt to write to these bits, write 0 . The value, if

read, turns out to be 0 .

Figure 1.16.3. A-D converter control registers (2)

Table 1.16.2. Operation clock fAD

φ

CKS0 CKS1 CKS2

AD

AD/4

AD/12

AD

0

1

0

1

0

1

0

1

0

1

0

1

0

1

f

AD/3

AD/2

AD/6

AD

AD/3

φ

Z, and make

AD

.

Note: Divide the fAD if f(XIN) exceeds 10MH

frequency equal to or less than 10MH

Z

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A-D Converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(1) One-shot mode

In one-shot mode, the pin selected using the analog input pin select bits , is used for one-shot A-D

conversion. Table 1.16.3 shows the specifications of one-shot mode. Figure 1.16.4 shows the settings of

the A-D control registers in one-shot mode.

Table 1.16.3. One-shot mode specifications

Specification

Item

Function

The pin selected by the analog input pin select bits is used for one A-D conversion

Writing "1" to the A-D conversion start flag

Start condition

Stop condition

• End of A-D conversion (A-D conversion start flag changes to "0" - except when

external trigger is selected

• Writing "0" to the A-D conversion start flag

Interrupt request

generation timing

End of A-D conversion

Input pin

Select one from AN0 to AN7

Read A-D register that corresponds to selected analog input pin

Reading of A-D result

A-D control register 0 (Note 1)

Symbol

ADCON0

Address

03D616

When reset

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

2

0

Bit symbol

Bit name

Function

R W

b2 b1 b0

Analog input pin select

bit

CH0

CH1

CH2

0 0 0 : AN

0 0 1 : AN

0 1 0 : AN

0 1 1 : AN

1 0 0 : AN

1 0 1 : AN

1 1 0 : AN

1 1 1 : AN

0

1

2

3

4

5

6

7

is selected

(Note 2)

b4 b3

MD0

MD1

A-D operation mode

select bit 0

0 0 : One-shot mode

Trigger select bit

0 : Software trigger

1 : ADTRG trigger

TRG

ADST

CKS0

A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit 0

Refer to table 1.16.2

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pins again.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON1

Address

03D716

When reset

0016

1

0

Bit symbol

Bit name

A-D sweep pin

select bit

Function

R W

Invalid in one-shot mode

SCAN0

SCAN1

Set to 0 when this mode is selected

A-D operation mode

select bit 1

MD2

BITS

8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode

CKS1

VCUT

Frequency select bit1

Refer to table 1.16.2

Vref connect bit (Note 2) 1 : Vref connected

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting

A-D conversion.

Figure 1.16.4. A-D conversion control registers in one-shot mode

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A-D Converter

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(2) Repeat mode

In repeat mode, the pin selected using the analog input pin select bits , is used for one-shot A-D conver-

sion. Table 1.16.4 shows the specifications of repeat mode. Figure 1.16.5 shows the settings of the A-D

control registers in repeat-shot mode.

Table 1.16.4. Repeat mode specifications

Specification

Item

Function

The pin selected by the analog input pin select bits is used for one A-D conversion

Writing "1" to the A-D conversion start flag

Start condition

Stop condition

Writing "0" to the A-D conversion start flag

Interrupt request

generation timing

None generated

Input pin

Select one from AN0 to AN7

Reading of A-D result

Read A-D register that corresponds to selected analog input pin (at any time)

A-D control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON0

Address

03D616

When reset

00000XXX2

0

1

Bit symbol

CH0

Bit name

Function

R W

b2 b1 b0

Analog input pin select

bit

0 0 0 : AN

0 0 1 : AN

0 1 0 : AN

0 1 1 : AN

1 0 0 : AN

1 0 1 : AN

1 1 0 : AN

1 1 1 : AN

0

1

2

3

4

5

6

7

is selected

CH1

CH2

(Note 2)

b4 b3

MD0

MD1

A-D operation mode

select bit 0

0 1 : Repeat mode

Trigger select bit

0 : Software trigger

1 : ADTRG trigger

TRG

ADST

CKS0

A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit 0

Refer to table 1.16.2

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pins again.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON1

Address

03D716

When reset

0016

1

0

Bit symbol

Bit name

A-D sweep pin

select bit

Function

Invalid in repeat mode

R W

SCAN0

SCAN1

when this mode is selected

Set to 0

A-D operation mode

select bit 1

MD2

BITS

8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode

CKS1

VCUT

Frequency select bit1

Refer to table 1.16.2

Vref connect bit (Note 2) 1 : Vref connected

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting

A-D conversion.

Figure 1.16.5. A-D conversion control registers in repeat mode

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(3) Single sweep mode

In single sweep mode, the pins selected using the A-D sweep pin select bits, are used for one-by-one A-

D conversion. Table 1.16.5 shows the specifications of single sweep mode. Figure 1.16.6 shows the

settings of the A-D control registers in single sweep mode.

Table 1.16.5. Single sweep mode specifications

Specification

Item

Function

The pin selected by the analog input pin select bits is used for one A-D conversion

Writing "1" to the A-D conversion start flag

Start condition

Stop condition

• End of A-D conversion (A-D conversion start flag changes to "0" - except when

external trigger is selected

• Writing "0" to the A-D conversion start flag

Interrupt request

generation timing

End of A-D conversion

Input pin

AN0 - AN1 (2 pins), AN0 - AN3 (4 pins), AN0 - AN5 (6 pins), or AN0 - AN7 (8 pins)

Read A-D register that corresponds to selected analog input pin

Reading of A-D result

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON0

Address

03D616

When reset

00000XXX

0

1

2

Bit symbol

CH0

Bit name

Function

R W

Analog input pin select

bit

Invalid in single sweep mode

CH1

CH2

b4 b3

MD0

MD1

A-D operation mode

select bit 0

1 0 : Single sweep mode

Trigger select bit

0 : Software trigger

1 : ADTRG trigger

TRG

ADST

CKS0

A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit 0

Refer to table 1.16.2

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON1

Address

03D716

When reset

0016

1

0

Bit symbol

SCAN0

Bit name

A-D sweep pin

select bit

Function

W

R

When single sweep mode is selected

b1 b0

0 0 : AN

0 1 : AN

1 0 : AN

1 1 : AN

0

, AN

1

(2 pins)

to AN

3

5

7

(4 pins)

(6 pins)

(8 pins)

SCAN1

MD2

Set to 0 when this mode is selected

A-D operation mode

select bit 1

8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode

BITS

CKS1

Frequency select bit1

Refer to table 1.16.2

Vref connect bit (Note 2) 1 : Vref connected

VCUT

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting

A-D conversion.

Figure 1.16.6. A-D conversion control registers in single sweep mode

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(4) Repeat sweep mode 0

In repeat sweep mode 0, the pins selected using the A-D sweep pin select bits , are used for repeat

sweep A-D conversion. Table 1.16.6 shows the specifications of repeat sweep mode 0. Figure 1.16.7

shows the settings of the A-D control registers in repeat sweep mode 0.

Table 1.16.6. Repeat sweep mode 0 specifications

Specification

Item

Function

The pin selected by the analog input pin select bits is used for one A-D conversion

Writing "1" to the A-D conversion start flag

Start condition

Stop condition

Writing "0" to the A-D conversion start flag

Interrupt request

generation timing

None generated

Input pin

AN

0 - AN1 (2 pins), AN0 - AN3 (4 pins), AN0 - AN5 (6 pins), or AN0 - AN7 (8 pins)

Reading of A-D result

Read A-D register that corresponds to selected analog input pin (at any time)

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON0

Address

03D616

When reset

00000XXX

1

2

Bit symbol

CH0

Bit name

Function

R W

Analog input pin select

bit

Invalid in repeat sweep mode 0

CH1

CH2

b4 b3

MD0

MD1

A-D operation mode

select bit 0

1 1 : Repeat sweep mode 0

Trigger select bit

0 : Software trigger

1 : ADTRG trigger

TRG

ADST

CKS0

A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit 0

Refer to table 1.16.2

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON1

Address

03D716

When reset

0016

1

0

Bit symbol

SCAN0

Bit name

A-D sweep pin

select bit

Function

W

R

When repeat sweep mode 0 is selected

b1 b0

0 0 : AN

0 1 : AN

1 0 : AN

1 1 : AN

0

, AN

1

(2 pins)

to AN

3

5

7

(4 pins)

(6 pins)

(8 pins)

SCAN1

MD2

Set to

0 when this mode is selected

A-D operation mode

select bit 1

8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode

BITS

CKS1

Frequency select bit1

Refer to table 1.16.2

Vref connect bit (Note 2) 1 : Vref connected

VCUT

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting

A-D conversion.

Figure 1.16.7. A-D conversion control registers in repeat sweep mode 0

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(5) Repeat sweep mode 1

In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected

using the A-D sweep pin select bits. Table 1.16.7 shows the specifications of repeat sweep mode 1.

Figure 1.16.8 shows the settings of the A-D control registers in repeat sweep mode 1.

Table 1.16.7. Repeat sweep mode 1 specifications

Specification

Item

Function

The pin selected by the analog input pin select bits is used for one A-D conversion

Writing "1" to the A-D conversion start flag

Start condition

Stop condition

Writing "0" to the A-D conversion start flag

Interrupt request

generation timing

None generated

Input pin

With emphasis on these pins:

AN0, AN0 - AN1 (2 pins), AN0 - AN2 (3 pins), AN0 - AN3 (4 pins)

Reading of A-D result Read A-D register that corresponds to selected analog input pin (at any time)

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON0

Address

03D616

When reset

00000XXX

1

2

Bit symbol

CH0

Bit name

Function

R W

Analog input pin select

bit

Invalid in repeat sweep mode 1

CH1

CH2

b4 b3

MD0

MD1

A-D operation mode

select bit 0

1 1 : Repeat sweep mode 1

Trigger select bit

0 : Software trigger

1 : ADTRG trigger

TRG

ADST

CKS0

A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit 0

Refer to table 1.16.2

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ADCON1

Address

03D716

When reset

0016

1

0

Bit symbol

SCAN0

Bit name

A-D sweep pin

select bit

Function

W

R

When repeat sweep mode 1 is selected

b1 b0

0 0 : AN

0 1 : AN

1 0 : AN

1 1 : AN

0

(1 pin)

, AN

1

(2 pins)

to AN

2

3

(3 pins)

(4 pins)

SCAN1

MD2

to AN

Set to 1 when this mode is selected

A-D operation mode

select bit 1

8/10-bit mode select bit 0 : 8-bit mode

1 : 10-bit mode

BITS

CKS1

Frequency select bit1

Refer to table 1.16.2

Vref connect bit (Note 2) 1 : Vref connected

VCUT

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

Note 2: If the VCUT bit is reset from "0" (Vref unconnected) to "1" (Vref connected), wait for 1 µs or more before starting

A-D conversion.

Figure 1.16.8. A-D conversion control registers in repeat sweep mode 1

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A-D Converter

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(a) Sample and Hold

Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When

sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is

achieved in 8-bit resolution and 33 AD in 10-bit resolution. Sample and hold can be selected in all

f

modes. However, in all modes, be sure to specify whether to use sample and hold before starting A-D

conversion.

(b) Caution of using A-D converter

(1) Set the port direction bits corresponding to the following pins to input: those P10 pins to be used for

analog input, plus external trigger input pin (P15).

(2) In using a key-input interrupt, none of 4 pins (AN4 through AN7) can be used as an A-D conversion port

(if the A-D input voltage goes to ‘‘L’’ level, a key-input interrupt occurs).

(3) Insert the capacitor between AVCC and AVSS, between VREF and AVss, and between the analog input

pin (ANi) and AVSS, to prevent a malfunction or program runaway, and to reduce conversion error,

due to noise. Figure 1.16.9 is an example connection of each pin.

Microcomputer

VCC

AVCC

VREF

C4

C2

C1

C3

VSS

AVSS

ANi

Note 1: C1 ≥ 0.47uF, C2 ≥ 0.47uF, C3 ≥ 100pF, C4 ≥ 0.1uF (reference)

Note 2: Ensure these connections are as thick and short as possible.

Figure 1.16.9. Example connection of VCC, VSS, AVCC, AVSS, VREF and ANi

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Programmable I/O Ports

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Ports

There are 38 programmable I/O ports: P15 - P17, P6, P7, P8 (except P84), P90 - P93, and P10. Each port

can be set independently for input or output using the direction register. A pull-up resistance for each block

of 4 ports can be set.

Figures 1.17.1 to 1.17.3 show the programmable I/O ports. Figure 1.17.4 shows the I/O pins.

Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.

To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input

mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs

regardless of the contents of the direction registers. See the descriptions of the respective functions for

how to set up the built-in peripheral devices.

(1) Direction registers

Figure 1.17.5 shows the port direction registers.

These registers are used to choose the direction of the programmable I/O ports. Each bit in these

registers corresponds one for one to each I/O pin.

Note: The Port 9 direction register incorporates a write protection function. Before writing to the port 9

direction register the write protection must be disabled by setting PRC2 of the Protect register (bit 2 at

000A16) to "1". Note that PRC2 is automatically reset to "0" after the next write to an SFR address.

(2) Port registers

Figure 1.17.6 shows the port registers.

These registers are used to read and write data for input and output to and from an external device. A

port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit

in the port registers corresponds one for one to each I/O pin.

(3) Pull-up control registers

Figure 1.17.7 shows the pull-up control registers.

The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports

are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register

is set to input.

(4) Port control register

Figure 1.17.8 shows the port control register.

Bit 0 of the port control register is used to control the read of port P1 as follows:

0 : When port P1 is set as an input port, the port input level is read.

When port P1 is set as an output port , the contents of the port P1 register are read.

1 : The contents of the port P1 register are always read.

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Programmable I/O Ports

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pull-up selection

Direction register

P15

to P1

7

Port P1 control register

Data bus

Port latch

(Note)

Input to respective peripheral functions

Pull-up selection

Direction

register

P60

, P6

1

, P6

4

, P6

5

,

"1"

P72

- P7

6

, P8

0

, P8

1

Output

Port latch

Data bus

(Note)

Input to respective peripheral functions

Pull-up selection

Direction register

P62

, P66, P77,

P90

to P9

2

Port latch

Data bus

(Note)

Input to respective peripheral functions

Pull-up selection

Direction register

P10

(inside dotted-line not included)

P10 to P10

(inside dotted-line included)

0 to P103

4

7

Data bus

Port latch

(Note)

Analog input

Input to respective peripheral functions

Note :

symbolizes a parasitic diode.

Do not apply a voltage higher than Vcc to each port.

Figure 1.17.1. Programmable I/O ports (1)

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Pull-up selection

Direction register

P6

3

, P6

7

1

Output

Port latch

Data bus

(Note 1)

Switching between CMOS and Nch

Direction register

P70, P71

1

Output

Data bus

Port latch

(Note 2)

Input to respective peripheral functions

Pull-up selection

Direction register

P82, P83

Port latch

Data bus

(Note 1)

Input to respective peripheral functions

Pull-up selection

Direction register

P9

3

Port latch

Data bus

(Note 1)

Note :1

Note :2

symbolizes a parasitic diode.

Do not apply a voltage higher than Vcc to each port.

symbolizes a parasitic diode.

Figure 1.17.2. Programmable I/O ports (2)

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Pull-up selection

NMI Enable

P85

Direction register

Data bus

Port latch

(Note)

NMI Interrupt Input

NMI Enable

SD

Pull-up selection

Port Xc Select bit

Direction register

P87

Data bus

Port latch

(Note)

fc

Rf

Pull-up selection

Port Xc Select bit

Direction register

Rd

P8

6

Data bus

Port latch

(Note)

Note :

symbolizes a parasitic diode.

Do not apply a voltage higher than Vcc to each port.

Figure 1.17.3. Programmable I/O ports (3)

(Note 2)

(Note 1)

CNVSS

CNVSS signal input

RESET

RESET signal input

(Note 1)

Note 1:

symbolizes a parasitic diode.

Do not apply a voltage higher than Vcc to each pin.

Note 2: A parasitic diode on the VCC side is added to the mask ROM version.

Do not apply a voltage higher than Vcc to each pin.

Figure 1.17.4. I/O pins

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Port Pi direction register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PDi (i = 6, 7, 10)

Address

03EE16, 03EF16, 03F616

When reset

0016

Bit symbol

Bit name

Function

0 : Input mode

(Functions as an input port)

1 : Output mode

R W

PDi_0

PDi_1

PDi_2

Port Pi

0

direction register

1

2

(Functions as an output port)

PDi_3

PDi_4

PDi_5

PDi_6

PDi_7

3

direction register

(i = 6, 7, 10)

4

Port Pi

5

6

7

Port P1 direction register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PD1

Address

03E316

When reset

000XXXXX

2

Bit symbol

Nothing is assigned.

Bit name

Function

R W

Write "0" when writing to this bit. The value is "0" when read.

0 : Input mode

(Functions as an input port)

1 : Output mode

PD1_5

PD1_6

PD1_7

Port P1

5

6

7

direction register

(Functions as an output port)

Port P8 direction register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PD8

Address

03F216

When reset

000X0000

2

Bit symbol

PD8_0

Bit name

Function

0 : Input mode

(Functions as an input port)

1 : Output mode

R W

Port P8

0

direction register

PD8_1

PD8_2

PD8_3

1

Port P8

2

(Functions as an output port)

Port P8

3

Nothing is assigned.

Write "0" when writing to this bit. The value is "0" when read.

PD8_5

PD8_6

PD8_7

Port P8

5

direction register

0 : Input mode

(Functions as an input port)

1 : Output mode

Port P8

6

7

(Functions as an output port)

Port P9 direction register (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PD9

Address

03F316

When reset

XXXX0000

2

Bit symbol

PD9_1

Bit name

Function

0 : Input mode

(Functions as an input port)

1 : Output mode

R W

Port P9

0

direction register

3 direction register

PD9_2

Port P9

1

PD9_3

Port P9

2

(Functions as an output port)

PD9_4

Port P9

Nothing is assigned.

Write "0" when writing to this bit. The value is "0" when read.

Note : Set bit 2 of the protect register (address 000A16) to "1" when writing new values to this register.

Figure 1.17.5. Direction registers

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M16C/26 Group

Programmable I/O Ports

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Port Pi register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

Pi (i = 6, 7, 10)

Address

03EC16, 03ED16, 03F416

When reset

XX16

Bit symbol

Bit name

Port Pi register

Port Pi

Function

R W

Pi_0

Pi_1

Pi_2

Pi_3

0

(Note)

1

2

register

0 : "L" level data

1 : "H" level data

Port Pi

3

(i = 6, 7, 10)

Pi_4

Pi_5

Pi_6

Pi_7

4

register

Port Pi

5

6

7

Note : Since P7

0

and P7

1

are N-channel open drain ports, the data is high impedance.

Port P1 register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

P1

Address

03E1¹⁶

When reset

XX16

Bit symbol

Nothing is assigned.

Bit name

Function

R W

Write "0" when writing to this bit. The value is "0" when read.

P1_5

P1_6

P1_7

Port P1

5

register

(Note)

0 : "L" level data

1 : "H" level data

6

7

Port P8 register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

P8

Address

03F016

When reset

XX16

Bit symbol

P8_0

Bit name

Function

R W

Port P8

0

register

(Note)

P8_1

P8_2

P8_3

1

0 : "L" level data

1 : "H" level data

Port P8

2

Port P8

3

Nothing is assigned.

Write "0" when writing to this bit. The value is "0" when read.

P8_5

P8_6

Port P8

5

register

(Note)

0 : "L" level data

1 : "H" level data

Port P8

6

P8_7

Port P8

7

register

Port P9 register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

P9

Address

03F1¹⁶

When reset

XX16

Bit symbol

P9_0

Bit name

0 register

Function

R W

Port P9

(Note)

P9_1

1

register

0 : "L" level data

1 : "H" level data

P9_2

Port P9

2

P9_3

Port P9

3

Nothing is assigned.

Write "0" when writing to this bit. The value is "0" when read.

Note: Data is input and output to and from each pin by reading and writing to and from each corresponding bit.

Figure 1.17.6. Port registers

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Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Programmable I/O Ports

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pull-up control register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PUR0

Address

03FC16

When reset

00000000

2

Bit symbol

Bit name

Function

R W

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

PU03

P1

5

to P1

7

pull-up

The corresponding port is pulled

high with a pull-up resistor

0 : Not pulled high

1 : Pulled high

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Pull-up control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PUR1

Address

03FD16

When reset

00000000

2

R W

Bit symbol

Bit name

Function

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

PU14

PU15

P6

P7

0

to P6

to P7

3

pull-up

The corresponding port is pulled

high with a pull-up resistor

0 : Not pulled high

4

7

PU16

PU17

2

3

pull-up (Note 1)

pull-up

1 : Pulled high

P7

4

to P7

7

Note 1: Since P70 and P71 are N-channel open drain ports, pull-up is not available for them.

Pull-up control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

PUR2

Address

03FE16

When reset

00000000

2

Bit symbol

PU20

Bit name

Function

R W

P8

0

5

to P8

3

pull-up

The corresponding port is pulled

high with a pull-up resistor

0 : Not pulled high

PU21

PU22

P8

to P8

7

pull-up

1 : Pulled high

P9

0

to P9

3

pull-up

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

PU24

PU25

P10

0

to P10

3

pull-up

0 : Not pulled high

1 : Pulled high

P10

4

to P10

7 pull-up

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be 0.

Figure 1.17.7. Pull-up Control registers

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Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Programmable I/O Ports

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Port control register

b7 b6 b5 b4 b3 b2 b1 b0

Symbpl

PCR

Address

03FF16

When reset

00000000

2

R W

Bit symbol

PCR0

Bit name

Port P1 control register

Function

0 : When input port, read port

input level. When output port,

read the contents of port P1

register.

1 : Read the contents of port P1

register when input and output

port.

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns

out to be 0.

Figure 1.17.8. Port control register

Table 1.17.1. Example connection of unused pins in single-chip mode

Pin name

Connection

After setting to input mode, connect every pin to Vss via a resistor (pull-down);

or after setting to output mode, leave these pins open.

Ports P1

5

-P1

, P8

, P10

7

, P6, P7,

P8

0

-P83

6

-P8

7,

P90

-P3

P8

5

(NMI/SD)

(Note 1)

OUT

After setting to input mode, connect to Vcc via a resistor (pull-up).

Open

X

AVcc

Connect to Vcc

AVSS, VREF

VDC

Connect to Vss

Connect via a 0.1uF capacitor to Vss

X

IN

Note 1: With external clock input to

pin.

Microcomputer

Port P1

5

-P1

7

, P6, P7, P8

-P9 , P10

(Input mode)

0-P83,

P8 -P8

5

7

, P9

0

3

(Output mode

Open

)

NMI (Note)

XOUT

VCC

AVCC

AVSS

VREF

VDC

V

SS

Note: When P8

5

is to be used as NMI,

a pullup resistor should be connected.

Figure 1.17.9. Example connection of unused pins

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Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical Characteristics

Table 1.18.1. Absolute maximum ratings

Symbol

Parameter

Condition

Rated Value

Unit

V

CC

Supply voltage

VCC=AVCC

V

-0.3 to 6.5

AVCC

Analog supply voltage

VCC=AVCC

-0.3 to 6.5

V

P1

P8

5

0

to P17, P6

to P8 ,P8

to P10 , XIN, VREF, RESET, CNVSS

0

to P6

7

, P7

2

to P7

7,

Input

voltage

-0.3 to VCC+0.3

3

5

to P8

7

, P9

0

to P9

3,

V

I

P10

0

7

P7

0

, P7

1

-0.3 to 6.5

V

Output

voltage

P1

P8

5

0

to P17, P6

to P8 , P8

0

to P6

to P8

7

, P7

, P9

2

to P7

to P93,

7,

-0.3 to VCC+0.3

3

5

7

0

P10

0

to P107, XOUT

V

P

O

d

P7

0, P71

-0.3 to 6.5

300

V

Power dissipation

Topr=25

mW

C

T

opr

stg

Operating ambient temperature

Storage temperature

C

-20 to 85 / -40 to 85 (Note)

-65 to 150

Note : Specify a product of -40°C to 85°C to use it.

Tables 1.18.2a. & 1.18.2b. Electrical Characteristics for Flash ROM E/W Cycles

Table 1.18.2a. Characteristics (Note 1) for 100 E/W cycle products (D3, D5, U3, U5)

Standard value

Typ.

(Note 2)

Symbol

Parameter

Unit

Min.

Max.

cycle

–

Erase/Write cycle (Note 3)

Word write time

100 (Note 4)

µs

600

9

75

0.2

s

Block erase time

2Kbyte block

8Kbyte block

s

0.4

0.7

1.2

9

16Kbyte block

32Kbyte block

ms

td(SR-ES)

–

20

Time delay from Suspend Request until Erase Suspend

Data retention time (Note 5)

year

10

Table 1.18.2b. Characteristics (Note 6) for 10000 E/W cycle products (D7, D9, U7, U9) [Block A and Block B (Note 7)]

Standard value

Typ.

(Note 2)

Symbol

Parameter

Erase/Write cycle (Notes 3, 8, 9)

Unit

Min.

Max.

cycle

–

10000 (Notes 4, 10)

µs

Word write time

100

0.3

s

Block erase time (2Kbyte block)

Time delay from Suspend Request until Erase Suspend

ms

td(SR-ES)

20

Note 1: When not otherwise specified, Vcc = 2.7-5.5V; Topr = 0-60 C.

Note 2: Vcc=5.0V; Topr = 25 C.

Note 3: Definition of E/W cycle: Each block may be written to a variable number of times - up to a maximum of the total number of

distinct word addresses - for every block erase. Performing multiple writes to the same address before an erase operation is

prohibited.

Note 4: Maximum number of E/W cycles for which operation is guaranteed.

Note 5: Topr = -40-85 C (D3, D7, U3, U7) / -20-85 C (D5, D9, U5, U9).

Note 6: When not otherwise specified, Vcc = 2.7-5.5V; Topr = -20-85 C (D9, U9) / -40-85 C (D7, U7).

Note 7: Table 1.18.2b applies for Block A or B E/W cycles > 1000. Otherwise, use Table 1.18.2a.

Note 8: To reduce the number of E/W cycles, a block erase should ideally be performed after writing as many different word

addresses (only one time each) as possible. It is important to track the total number of block erases.

Note 9: Should erase error occur during block erase, attempt to execute clear status register command, then block erase

command at least three times until erase error disappears.

Note 10: When Block A or B E/W cycles exceed 100 (D7, D9, U7, U9), select one wait state per block access. When

FMR17 is set to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17.

Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 -

regardless of the setting of FMR17.

Note 11: Customers desiring E/W failure rate information should contact their Renesas technical support representative.

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Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.18.3. Recommended operating conditions (referenced to VCC = 2.7V to 5.5V

at Topr = – 20^oC to 85^oC / – 40^oC to 85^oC (Note 3) unless otherwise specified)

Standard

Symbol

Parameter

Unit

Min.

Typ.

Max.

V

CC

2.7

5.5

V

Supply voltage(VCC

)

AVcc

Vss

Vcc

0

Analog supply voltage

Supply voltage

V

AVss

0

V

Analog supply voltage

P1

P9

CNVss

5

to P1

to P9

7

, P6

, P10

0

to P6

7

, P7

2

to P7

IN, RESET,

7, P80 to P83, P85 to P87,

HIGH input

voltage

0

3

0

to P107,

X

0.8Vcc

0

V

Vcc

6.5

V

IH

V

P70, P7

1

LOW input

voltage

P1

P9

5

0

to P1

to P9

7

3

, P6

, P10

0

to P6

7

, P7

0

to P7

IN, RESET,

7, P80 to P83, P85 to P87,

V

IL

0.2Vcc

0

to P107,

X

CNVss

P1

P8

5

to P1

7

, P6

0

to P6

7

, P7

2

to P7

7

, P8

0

to P8

3

,

HIGH peak output

current

-10.0

-5.0

I

OH (peak)

mA

to P8

7

, P9

0

to P9

3

, P10

0

to P107

P1

P8

5

to P1

7

, P6

, P9

0

to P6

7

, P7

, P10

2

to P7

7

, P8

0

to P8

3

,

HIGH average

output current

I

OH (avg)

OL (peak)

to P8

7

0

to P9

3

0

to P10

7

P1

P8

5

to P1

to P8

7

, P6

, P9

0

to P6

to P9

7

, P7

, P10

0

to P7

, P8

LOW peak output

current

7

0

3

0

to P10

7

10.0

mA

P1

P8

5

to P1

to P8

7

, P6

, P9

0

to P6

to P9

7

, P7

, P10

0

to P7

7, P8

LOW average

output current

IOL (avg)

5.0

20

7

0

3

0

to P107

Main clock input

oscillation frequency

(Note4)

0

MHz

kHz

Vcc=3.0V to 5.5V

Vcc=2.7V to 3.0V

No wait

f (XIN

)

33.33 X Vcc

-80

32.768

1

50

f (XCIN

)

Subclock oscillation frequency

Ring oscillation frequency

CPU operation clock

f (Ring)

MHz

f (BCLK)

0

20

Note 1: The mean output current is the mean value within 100ms.

Note 2: The total IOL (peak) output current for all ports must be 80mA max. The total IOH (peak) output current for all ports must be

-80mA max.

Note 3: Specify a product of -40°C to 85°C to use it.

Note 4: Relationship between main clock oscillation frequency and supply voltage.

Main clock input oscillation frequency

( No wait )

20.0

33.3 X VCC-80MHz

10.0

0.0

2.7

Supply voltage[V]

(BCLK: no division)

3.0

5.0

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Electrical Characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.18.4. A-D conversion characteristics (Notes 1–3)

Standard

Min. Typ. Max.

Unit

Symbol

–

Parameter

Measuring condition

Resolution

V

REF =VCC

10

3

Bits

LSB

AN

0

to AN

7

input

V

5V

REF

=

CC

Integral

non-

linearity

error

INL

10 bit

AN

5

LSB

V

3.3V

REF

=

CC

2

3

LSB

V

REF =VCC =3.3V

8 bit

AN

0

to AN

7

input

V

REF

=

CC

5V

Absolute

accuracy

10 bit

8 bit

AN

0

to AN

7

5

LSB

–

V

REF

=

CC

3.3V

V

REF =VCC =3.3V

2

1

3

LSB

Differential non-linearity error

DNL

–

Offset error

LSB

kΩ

Gain error

3

Ladder resistance

10

40

R

LADDER

V

REF =VCC

Conversion time(10bit), Sample & hold

function available

3.3

t

CONV

REF =VCC =5V, øAD=10MHz

µs

Conversion time(8bit), Sample & hold

function available

2.8

0.3

V

REF =VCC= 5V, øAD=10MHz

t

CONV

SAMP

Sampling time

µs

V

REF

IA

Reference voltage

Analog input voltage

2.0

0

V

CC

V

REF

Note 1: Referenced to VCC = AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 ˚C / -40 to 85 ˚C unless otherwise

specified. Specify a product of -40 to 85 ˚C to use it.

Note 2: AD operation clock frequency (ØAD frequency) must be 10 MHz or less. And divide the fAD if VCC is less than 4.2V,

and make ØAD frequency equal to or lower than fAD/2.

Ø

AD frequency must be ≥

250 kHz, but less than the upper limit set by Note 2.

Note 3: When not using sample & hold function,

When using sample & hold function, ØAD frequency must be ≥ 1MHz, but less than the upper limit set by Note 2.

Table 1.18.5. Flash memory version electrical characteristics

o

(referenced to VCC = 5.0V, at Topr = 25 C, unless otherwise specified)

Standard

Typ.

Min.

_

Max.

_

Parameter

Unit

us

~1K E/W cycles ~10K E/W cycles

Word program time

Block erase time:

75

100

_

2Kbyte block

8Kbyte block

16Kbyte block

32Kbyte block

0.2

0.4

0.7

1.2

0.3

_

s

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Preliminary Specifications Rev. 0.9

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Specifications in this manual are tentative and subject to change.

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Electrical Characteristics

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.18.6. Low Voltage Detection Circuit Electrical Characteristics (Note 1)

Standard

Typ.

Symbol

Measuring condition

Parameter

Unit

Min.

3.3

Max.

4.4

Power supply down detection voltage (Note 1)

Reset level detection voltage (Note 1)

Vdet4

Vdet3

3.8

2.8

V

2.2

3.6

V

CC = 0.8 to 5.5V

V

Low voltage reset retention voltage (Note 2)

Low voltage reset release voltage

0.8

2.2

Vdet3s

Vdet3r

2.9

4.0

Note 1: VDET4 > VDET3

Note 2: VDET3s is the min voltage at which "hardware reset 2" is maintained. Below this voltage, "hardware reset 1" (using reset pin) must be

applied in order to resume operation.

Table 1.18.7. Power Supply Circuit Timing Characteristics

Standard

Typ.

Symbol

Measuring condition

Parameter

Unit

Min.

Max.

150

µs

td(R-S)

td(W-S)

td(M-L)

td(S-R)

td(E-A)

STOP release time (Note 2)

150

µs

Low power dissipation mode wait mode release time (Note 2)

V

CC = 2.7 to 5.5V

Time for internal power supply stabilization when main clock oscillation starts

50

Hardware reset 2 release wait time

VCC = VDET3r to 5.5V

6 (Note 1)

20

ms

µs

Low voltage detection circuit operation start time (Note 3)

V

CC = 2.7 to 5.5V

Note 1: When Vcc = 5V

Note 2: This is the time between interrupt for (STOP/WAIT) mode release and resumption of CPU clock operation.

Note 3: After enabling low voltage detection, this time is required before proper detection can occur.

Table 1.18.8. Hardware Reset 2 Release Wait Time

Vdet3r

VCC

CPU clock

td(S-R)

Table 1.18.9. STOP Release Time

Interrupt for

stop mode

release

CPU clock

td(R-S)

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Preliminary Specifications Rev. 0.9

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Electrical Characteristics (Vcc = 5V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V

Table 1.18.10. Electrical characteristics (referenced to VCC = 4.2V to 5.5V, VSS = 0V

o

at Topr = – 20 C to 85 C / – 40 C to 85 C (Note 2), f(XIN) = 20MH

Z

unless otherwise specified)

Standard

Symbol

Measuring condition

Parameter

Unit

Min. Typ. Max.

P1

P8

5

to P1

7

, P6

0

to P6

7

, P7

2

to P7

7

, P8

7

0

to P8

3

,

HIGH output

voltage

to P8

7

,

P90

to P9

3

, P10

0

to P10

VOH

I

OH=-5mA

3.0

V

CC

V

P1

P8

5

to P1

7

, P6

0

to P6

7

, P7

2

to P7

7

, P8

0

HIGH output

voltage

to P8

7

,

P90

to P9

3

, P10

0

to P10

7

VOH

IOH=-200µA

4.7

V

I

OL=-1mA

3.0

V

CC

HIGHPOWER

LOWPOWER

HIGH output

voltage

X

OUT

V

IOH=-0.5mA

V

OH

With no load applied

2.5

1.6

HIGHPOWER

LOWPOWER

HIGH output

voltage

COUT

P1

5

to P1

7

, P6

0

to P6

to P9

7

, P7

0

to P7

7

, P8

0

to P8

3

,

LOW output

voltage

P8

5

to P8

7

, P9

0

3

, P100 to P107

V

OL

I

OL=5mA

2.0

V

P1

P8

5

to P1

7

, P6

, P9

0

to P6

to P9

7, P7

0

to P7

7

, P8

0

to P8

3

LOW output

voltage

to P8

7

0

3

, P10

0

to P107

V

IOL=200µA

0.45

V

I

OL=1mA

2.0

HIGHPOWER

LOWPOWER

LOW output

voltage

X

OUT

VOL

V

I

OL=0.5mA

With no load applied

0

HIGHPOWER

LOWPOWER

LOW output

voltage

COUT

TA0IN to TA4IN, TB0IN to TB2IN

,

Hysteresis

INT

AD^TRG, CTS

CLK to CLK

KI to KI , RxD

0

, INT

1

, INT

3

to INT

5

, NMI,

V

T+-

V

T-

0

to CTS

2, SCL, SDA,

0.2

1.0

V

0

2, TA2OUT to TA4OUT

,

0

3

0

to RxD

2

Hysteresis

RESET

2.5

5.0

V

P1

P8

5

to P1

to P8

7

, P6

0

to P6

to P9

CNVss

7

, P7

0

to P7

7

, P8

0

to P8

3

,

HIGH input

current

7,

P

90

3

, P10

0

to P107

µA

IIH

X

IN, RESET

,

V

I

=5V

=0V

P1

P8

5

to P1

to P8

7, P6

0

to P6

to P9

CNVss

7, P7

0

to P7

7

, P8

0

3

LOW input

current

7,

P

,

9

0

3

, P10

0

to P10

7

X

IN, RESET

I

IL

V

-5.0

µA

kΩ

R

PULLUP

P1

P8

5

to P1

to P8

7, P6

0

to P6

7, P7

2

to P7

7

, P8

0

to P8

3,

Pull-up

resistance

7, P9

0

to P9

3

, P10

0

to P10

7

VI=0V

30.0

2.0

50.0 170.0

R

fXIN

Feedback resistance

1.5

15

MΩ

X

IN

R

fXCIN

CIN

V

RAM

RAM retention voltage

When clock is stopped

V

The output pins are open and

other pins are Vss

Flash memory

version

f(XIN) = 20MHz

Square wave, no division

16

25

19

mA

Flash memory

version

f(XCIN) = 32kHz

Square wave, in RAM

µA

Flash memory

version

f(XCIN) = 32kHz

Square wave, in Flash

420

f(X^CIN) = 32kHz

When a WAIT instruction

is executed. (Note 1)

Oscillation capacity High

7.5

2.0

µA

Power supply current

(Vcc = 3.0 to 5.5V)

Icc

Flash memory

version

f(X^CIN) = 32kHz

When a WAIT instruction

is executed. (Note 1)

Oscillation capacity Low

Topr = 25°C

when clock is stopped

0.8

3.0

µA

I

DET4

DET3

V

DET4 detection dissipation current (Note 3)

0.7

1.2

4

8

µA

Reset level detection dissipation current (Note 3)

Note 1: With one timer operated using fC32.

Note 2: Specify a product of -40°C to 85°C to use it.

Note 3: IDET is dissipation current when the following bit is set to "1" (detection circuit enabled)

175

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 5V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V

Timing requirements

o

(referenced to VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C (*) unless otherwise specified)

* : Specify a product of -40 to 85°C to use it.

Table 1.18.11. External Clock Input (XIN input)

Standard

Symbol

Parameter

Unit

Min.

50

Max.

t

c

ns

External clock input cycle time

t

w(H

)

External clock input HIGH pulse width

External clock input LOW pulse width

External clock rise time

22

t

w(L)

22

t

r

5

t

f

External clock fall time

176

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 5V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V

Timing requirements

o

(referenced to VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C (*) unless otherwise specified)

* : Specify a product of -40 to 85°C to use it.

Table 1.18.12. Timer A input (counter input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

ns

t

c(TA)

TAiIN input cycle time

t

w(TAH)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

t

w(TAL)

40

Table 1.18.13. Timer A input (gating input in timer mode)

Standard

Min. Max.

400

Symbol

Parameter

Unit

ns

t

c(TA)

TAiIN input cycle time

t

w(TAH)

200

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

t

w(TAL)

Table 1.18.14. Timer A input (external trigger input in one-shot timer mode)

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

ns

t

c(TA)

TAiIN input cycle time

t

w(TAH)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

t

w(TAL)

Table 1.18.15. Timer A input (external trigger input in pulse width modulation mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t

w(TAH)

ns

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

t

w(TAL)

Table 1.18.16. Timer A input (up/down input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

2000

1000

400

Max.

t

c(UP)

ns

TAiOUT input cycle time

t

w(UPH)

w(UPL)

TAiOUT input HIGH pulse width

t

TAiOUT input LOW pulse width

TAiOUT input setup time

TAiOUT input hold time

t

su(UP-TIN

)

t

h(TIN-UP)

400

Table 1.18.17. Timer A input (two-phase pulse input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

800

200

Max.

t

c(TA)

ns

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

t

su(TAIN-TAOUT

)

t

su(TAOUT-TAIN

177

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 5V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 5V

Timing requirements

o

(referenced to VCC = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C (*) unless otherwise specified)

* : Specify a product of -40 to 85°C to use it.

Table 1.18.18. Timer B input (counter input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t

c(TB)

ns

TBiIN input cycle time (counted on one edge)

t

w(TBH)

w(TBL)

c(TB)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

40

t

200

80

t

w(TBH)

t

w(TBL)

80

Table 1.18.19. Timer B input (pulse period measurement mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t

c(TB)

TBiIN input cycle time

ns

t

w(TBH)

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

w(TBL)

Table 1.18.20. Timer B input (pulse width measurement mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t

c(TB)

ns

TBiIN input cycle time

t

w(TBH)

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

t

w(TBL)

Table 1.18.21. A-D trigger input

Standard

Unit

Symbol

Paramete

Min.

1000

125

Max.

t

c(AD)

ns

ADTRG input cycle time (trigger able minimum)

ADTRG input LOW pulse width

t

w(ADL)

Table 1.18.22. Serial I/O

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

t

c(CK)

w(CKH)

w(CKL)

ns

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

TxDi output delay time

TxDi hold time

t

d(C-Q)

h(C-Q)

80

t

0

30

90

t

su(D-C)

RxDi input setup time

RxDi input hold time

t

h(C-D)

Table 1.18.23. External interrupt INTi inputs

Standard

Symbol

Parameter

Unit

Min.

250

Max.

t

w(INH)

w(INL)

ns

INTi input HIGH pulse width

INTi input LOW pulse width

t

178

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 3V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V

Table 1.18.24. Electrical characteristics (referenced to VCC = 2.7 to 3.3V, VSS = 0V

o

at Topr = – 20 C to 85 C / – 40 C to 85 C (Note 1), f(XIN) = 10MHZ with wait

unless otherwise specified)

Standard

Min. Typ. Max.

Measuring condition

Symbol

Parameter

Unit

HIGH output P1

5

to P1

7

, P6

0

to P6

to P9

7

, P7

, P10

2

to P7

7, P80 to P83,

V

I

OH=-1mA

2.5

voltage

P85

to P8

7

, P9

0

3

0

to P107

V

OH

HIGHPOWER

LOWPOWER

I

OH=-0.1mA

2.5

HIGH output

voltage

XOUT

V

OH=-50µA

With no load applied

2.5

1.6

HIGHPOWER

LOWPOWER

HIGH output

voltage

X

COUT

V

P1

P8

5

to P1

to P8

7

, P6

0

to P6

7

, P7

0

to P7

7, P80 to P83,

LOW output

voltage

I

OL=1mA

0.5

V

OL

7, P9

0

to P9

3

, P10

0

to P107

I

^OL=0.1mA

0.5

HIGHPOWER

LOW output

voltage

X

OUT

V

LOWPOWER

HIGHPOWER

^OL=50µA

With no load applied

0

LOW output

voltage

XCOUT

LOWPOWER

Hysteresis

TA0IN to TA4IN, TB0IN to TB2IN,

INT

AD^TRG, CTS

CLK to CLK

KI to KI , RxD

0

, INT

1

, INT

3

to INT

5

, NMI,

V

T+-

V

T-

0

to CTS

2, SCL, SDA,

0.2

0.8

V

0

2, TA2OUT to TA4OUT

,

0

3

0

to RxD

2

V

1.8

4.0

V

Hysteresis

RESET

HIGH input

current

P1

P8

5

to P1

7

, P6

0

to P6

to P9

CNVss

7, P7

0

to P7

7

, P8

0

to P8

3

,

IIH

to P8

7

,

P9

0

3, P10

0

to P107

V

I

=3V

=0V

µA

XIN, RESET

,

LOW input

current

P1

P8

5

to P1

7

, P6 to P6

to P9

CNVss

, P6 to P6

, P9 to P9

0

7, P7

0

to P7

7

, P8

0

to P8

3

IIL

to P8

7

,

P

9

0

3, P10

0

to P107

VI

-4.0

500

µA

kΩ

XIN, RESET,

RPULLUP

P1

P8

5

to P1

7

0

7, P7

2

to P7

7

, P8

0

to P8

3

,

Pull-up

resistance

to P8

7

0

3, P10

0

to P107

VI=0V

66

160

R

fXIN

Feedback resistance

RAM retention voltage

X

IN

3.0

MΩ

V

RfXCIN

X

CIN

25.0

VRAM

2.0

When clock is stopped

Flash memory

version

f(XIN) = 10MHz

The output pins are open

and other pins are Vss

8

13

mA

µA

Square wave, no division

Flash memory

version

f(X^CIN) = 32kHz

Square wave, in RAM

25

Flash memory

version

f(XCIN) = 32kHz

Square wave, in Flash

420

µA

f(X^CIN) = 32kHz

When a WAIT instruction

is executed.(Note 2)

Oscillation capacity High

6.0

µA

Power supply current

(Vcc=2.7 to 3.0V)

Icc

Flash memory

version

f(X^CIN) = 32kHz

When a WAIT instruction

is executed.(Note 2)

Oscillation capacity Low

1.8

0.7

µA

Topr = 25°C

when clock is stopped

3.0

I

DET4

DET3

V

DET4 detection dissipation current (Note 3)

0.6

0.4

4

2

µA

Reset level detection dissipation current (Note 3)

Note 1: Specify a product of -40°C to 85°C to use it.

Note 2: With one timer operated using f^C32

Note 3: IDET is dissipation current when the following bit is set to "1" (detection circuit enabled).

.

I

DET4: VC27 bit of VCR2 register

DET3: VC26 bit of VCR2 register

179

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 3V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V

Timing requirements

o

(referenced to VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C (*) unless otherwise specified)

* : Specify a product of -40 to 85°C to use it.

Table 1.18.25. External Clock Input (XIN input)

Standard

Symbol

Parameter

Unit

Min.

100

40

Max.

t

c

ns

External clock input cycle time

t

w(H

)

External clock input HIGH pulse width

External clock input LOW pulse width

External clock rise time

t

w(L)

40

t

r

18

t

f

External clock fall time

180

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 3V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V

Timing requirements

o

(referenced to VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C (*) unless otherwise specified)

* : Specify a product of -40 to 85°C to use it.

Table 1.18.26. Timer A input (counter input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

ns

t

c(TA)

TAiIN input cycle time

60

w(TAH)

w(TAL)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Table 1.18.27. Timer A input (gating input in timer mode)

Standard

Min. Max.

Symbol

Parameter

Unit

ns

t

c(TA)

600

300

TAiIN input cycle time

w(TAH)

w(TAL)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Table 1.18.28. Timer A input (external trigger input in one-shot timer mode)

Standard

Min. Max.

Symbol

Parameter

Unit

ns

t

c(TA)

300

150

TAiIN input cycle time

w(TAH)

w(TAL)

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

Table 1.18.29. Timer A input (external trigger input in pulse width modulation mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

t

w(TAH)

ns

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

t

w(TAL)

Table 1.18.30. Timer A input (up/down input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

3000

1500

600

Max.

t

c(UP)

ns

TAiOUT input cycle time

w(UPH)

w(UPL)

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup time

su(UP-TIN

h(TIN-UP)

)

TAiOUT input hold time

600

Table 1.18.31. Timer A input (two-phase pulse input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

2

Max.

t

c(TA)

µs

ns

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

su(TAIN-TAOUT

su(TAOUT-TAIN

)

500

181

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Electrical Characteristics (Vcc = 3V)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

VCC = 3V

Timing requirements

o

(referenced to VCC = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C (*) unless otherwise specified)

* : Specify a product of -40 to 85°C to use it.

Table 1.18.32. Timer B input (counter input in event counter mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

t

c(TB)

ns

TBiIN input cycle time (counted on one edge)

t

w(TBH)

w(TBL)

c(TB)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

TBiIN input cycle time (counted on both edges)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

60

t

300

160

t

w(TBH)

t

w(TBL)

Table 1.18.33. Timer B input (pulse period measurement mode)

Standard

Symbo

Parameter

Unit

Min.

600

300

Max.

t

c(TB)

TBiIN input cycle time

ns

t

w(TBH)

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

w(TBL)

Table 1.18.34. Timer B input (pulse width measurement mode)

Standard

Symbo

Parameter

Unit

Min.

600

300

Max.

t

c(TB)

ns

TBiIN input cycle time

t

w(TBH)

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

t

w(TBL)

Table 1.18.35. A-D trigger input

Standard

Symbol

Parameter

U

Unit

Min.

1500

200

Max.

t

c(AD)

ns

ADTRG input cycle time (trigger able minimum)

ADTRG input LOW pulse width

t

w(ADL)

Table 1.18.36. Serial I/O

Standard

Symbol

Parameter

Unit

Min.

300

150

Max.

t

c(CK)

w(CKH)

w(CKL)

ns

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

TxDi output delay time

TxDi hold time

t

d(C-Q)

h(C-Q)

160

t

0

50

90

t

su(D-C)

RxDi input setup time

RxDi input hold time

t

h(C-D)

Table 1.18.37. External interrupt INTi inputs

Standard

Symbo

Parameter

Unit

Min.

380

Max.

t

w(INH)

w(INL)

ns

INTi input HIGH pulse width

INTi input LOW pulse width

t

182

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

Timing

M16C/26 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

tc(TA)

tw(TAH)

tw(UPH)

TAiIN input

tw(TAL)

tc(UP)

TAiOUT input

tw(UPL)

TAiOUT input

(Up/down input)

During event counter mode

TAiIN input

(When count on falling

edge is selected)

th(TIN UP)

tsu(UP TIN

)

TAiIN input

(When count on rising

edge is selected)

tc(TB)

tw(TBH)

tw(ADL)

tw(CKH)

TBiIN input

tw(TBL)

tc(AD)

ADTRG input

tc(CK)

CLKi

tw(CKL)

th(C Q)

TxDi

RxDi

tsu(D C)

td(C Q)

th(C D)

tw(INL)

INTi input

tw(INH)

Figure 1.18.1. Timing diagram (1)

183

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Flash Memory

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Outline Performance

Table 1.19.1 shows the outline performance of the M16C/26 (flash memory version).

Table 1.19.1. Outline performance of the M16C/26 (flash memory version)

Item

Performance

Flash memory operation mode

Three user modes (standard serial I/O, CPU rewrite, parallel I/O)

Erase block

User ROM area

division

See Figure 1.19.1

In units of word.

Write method

Block erase

Erase method

Erase/Write (E/W) control method

E/W control by software command

Two 8Kbyte user by register lock bit (FMR02)

5 commands

Protect method

Number of commands

Erase/Write count (Notes 1, 2)

Depends on device code (see Table 1.2b)

10 years

Data Retention

Parallel I/O and standard serial I/O modes are supported.

ROM code protect

Note 1: Block A and Block B are 10,000 times E/W. All other blocks are 1000 times E/W. (Under

development; mass production scheduled to start in the 3rd quarter of 2003.)

Note 2: Definition of E/W times:

The E/W times are defined to be per-block erasure times. For example, assume a case whereby a

4-Kbyte Block A is programmed one word at a time and erased once all 2048 write operations

have completed. In this case, the block is considered to have been written and erased once.

If a product is 100 times E/W, each block in it can be erased up to 100 times. When 10,000 times

E/W, Block A and Block B can each be erased up to 10,000 times. All other blocks can each be

erased up to 1000 times.

184

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Flash Memory

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Flash Memory

The M16C/26 (flash memory version) contains the flash memory that can be rewritten with a single voltage.

For this flash memory, three flash memory modes are available in which to read, program, and erase:

parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program-

mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit

(CPU). Each mode is detailed in the following sections.

The flash memory is divided into several blocks as shown in Figure 1.19.1, so that memory can be erased

one block at a time.

00F00016

Block B :2K bytes (Note 2)

Block A :2K bytes (Note 2)

00FFFF16

0F0000¹⁶

Block 3 : 32K bytes

0F7FFF16

0F800016

Block 2 : 16K bytes

0FBFFF16

0FC00016

Block 1 : 8K bytes

0FDFFF16

0FE00016

Block 0 : 8K bytes

Note 1: To specify a block, use the maximum address in the block

that is an even address.

Note 2: To access 2Kbyte data blocks, set PM10 to "1".

0FFFFF¹⁶

User ROM area

Figure 1.19.1. Block diagram of flash memory (64-Kbyte) version (Note 1)

185

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

CPU Rewrite Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU Rewrite Mode

The CPU rewrite mode is used to perform a read, program, or erase operation on the internal flash memory

under control by the central processing unit (CPU). There are two variations of this mode: erase write 0

mode (EW0) in which said operation is performed using a rewrite program residing in memory (i.e. RAM)

other than the internal flash memory and erase write 1 mode (EW1) in which said operation is performed

using the program residing in the internal flash memory.

In CPU rewrite mode, only the user ROM area shown in Figure 1.19.1 can be rewritten. The Program and

Block Erase commands can be executed only for the user ROM area in block intervals.

The EW0 mode control program must be stored in the user ROM area. In EW0 mode, because the flash

memory cannot be read from the CPU, the rewrite control program must be transferred to memory loca-

tions other than the internal flash memory before it can be executed.

The EW1 mode control program must be stored in the user ROM area. In this mode, the rewrite control

program does not have to be transferred to other memory locations before executing it. However, in this

mode, the block where the rewrite control program is stored cannot be operated on by the Program or

Erase commands.

User Mode and Boot Mode

The control program for CPU rewrite mode must be written into the user ROM area, in parallel I/O mode,

beforehand.

Normal user mode is entered when the microcomputer is reset with pulling CNVSS pin low. In this case,

the CPU starts operating using the control program in the user ROM area.

When the microcomputer is reset by pulling both the CNVSS and the P86 [CE] pins high, the CPU starts

operating using the standard serial I/O control program. This mode is called the “boot” mode. When reset

is deasserted in boot mode, be sure the P65 pin is not at high or the P67 pin is not at low.

Block Address

Block addresses refer to an even address of each block. These addresses are used in the block erase

command.

Outline Performance (CPU Rewrite Mode)

In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by

software commands. There are two variations of this mode: erase write 0 mode (EW0) where operation is

executed in other than the internal flash memory such as the internal RAM and erase write 1 mode (EW1)

where operation is executed in the internal flash memory. One-wait must be set in both modes.

EW0 mode (CPU rewrite mode)

In this mode, the program must be executing out of RAM. The microcomputer is placed in EW0 mode by

setting the CPU rewrite mode select bit (address 01B716, bit 1) to 1, becoming ready to accept software

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commands.

In CPU rewrite mode (whether EW0 or EW1), make sure all software commands and data are written to

and read from even addresses (byte address Ao = 0) in 16 bit units. Make sure the write data is written in

16 bit units beginning with an even address. Writing in 16 bit units beginning with an odd address and

writing in 8 bit units are inhibited. When using 8-bit software commands, always be sure to write to even

addresses. Writing to odd addresses has no effect.

Use software commands to control program and erase operations. Whether program and erase opera-

tions have terminated normally or in error can be verified by reading the status register. Even when

reading the status register, set to even addresses in the user ROM area also.

EW1 mode (CPU rewrite mode)

In EW1 mode, operation is executed using the control program residing in the internal flash memory.

Unlike in EW0 mode, there is no need to transfer the control program to other than the internal flash

memory (e.g., internal RAM). However, make sure the control program is located in the 64-Kbyte user

block or 4-Kbyte data block.

For EW1 mode, set the EW0 mode select bit (address 01B716, bit 1) to 1 (by writing 0 and then 1 in

succession) and set the EW1 mode select bit (address 01B516, bit 6) to 1 (by writing 0 and then 1 in

succession). This places the microcomputer in EW1 mode, ready to accept software commands. Al-

though software commands operate the same way as in EW0 mode, there are following differences.

(1) Do not perform Block Erase or Program operations on control program execution blocks (blocks in

which the control program is located).

(2) Do not execute the Read Status Register command. (In EW1 mode, this command has no effect.)

After erase and program operations are completed during EW1 mode, the microcomputer is in read

array mode, and not in read status mode. (During EW0 mode, the microcomputer is in read status

mode after operations are completed.)

Therefore, to verify whether program or erase operations have terminated normally or in error, read the

flash memory control register 0. Be aware that during EW1 mode, the status register cannot be read.

During EW1 mode, the CPU remains in a hold state while executing erase and program operations. The

ports retain the status in which they were before commands were issued. (They do not go Hi-Z even while

executing erase or program operations.)

After erase or program operations are completed, the CPU restarts execution of the rest of the control

program.

While erase or program operations are underway in EW1 mode, make sure that no interrupts except

NMI, watchdog timer, and reset will be generated, and that no DMA transfers will be committed.

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Erase-Suspend Feature

The M16C/26 Flash ROM has been designed to be more compact and require a smaller layout footprint.

This, as a result, causes longer erase times. The M16C/26 Flash ROM is however not available/acces-

sible during an erase operation. This may sometimes cause time critical interrupt driven operations re-

quiring data/program in the flash to not be satisfied during the erase operation.

To circumvent this issue, the M16C/26 Flash ROM offers a new 'erase-suspend' feature which allows the

erase operation to be suspended, and access made available to the flash. The erase operation may

subsequently be resumed via software.

There are CPU erase/write (CPUEW) modes available EW0 (execution out of RAM) and EW1 (execution

out of FLASH). The erase-suspend feature is different in each of these modes. Please note that 1-wait

needs to be set in CPUEW operations.

EW0:

In EW0, program code is executed out of the RAM. After the erase command has been executed,

program execution continues in the RAM. As stated earlier the FLASH is not accessible during an

erase operation. If there is a request for data/code from the FLASH (via a maskable peripheral/exter-

nal interrupt), the interrupt must first request an erase-suspend. This is achieved by setting bits

FMR40 (SUSPEND_ENABLE) and FMR41 (SUSPEND_REQUEST). The routine then polls FMR46

(SUSPENDL) until it is set. At this point the erase has been suspended and the flash is accessible.

Once the required accesses are complete FMR41 (SUSPEND_REQUEST) is cleared and the routine

is completed. The erase operation resumes and continues to completion or until another erase-sus-

pend request occurs.

User actions:

1.0 Execute erase command out of RAM.

2.0 Maskable Interrupt request.

2.1 Set FMR40 & FMR41.

2.2 Poll FMR46 until '1'.

2.3 Access flash data/code.

2.4 Clear FMR41.

2.5 Return

3.0 Continue execution out of RAM

FMR40 may also be set before the erase command is executed, instead of in the interrupt routine.

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EW1:

In EW1, program code is executed out of the FLASH. First FMR40 (SUSPEND_ENABLE) must be set

to allow the erase-suspend feature. After ther erase command is executed the CPU goes into HOLD.

A maskable interrupt will set FMR41 (SUSPEND_REQUEST) if in an erase operation. Once the erase

is suspended the HOLD is deasserted and execution from the FLASH continues. The interrupt routine

can now be servised, after which control is returned to the main program. If the

SUSPEND_REQUEST has been set, it should be cleared, and when the erase resumes the CPU

goes back into HOLD until the erase operation is complete or another interrupt occurs.

User actions:

1.0 Set FMR40

2.0 Execute erase command out of FLASH.

3.0 HOLD_POINT (in HOLD)

4.0 Maskable Interrupt request. (FMR41 set by h/w)

4.1 Access flash data/code.

4.2 Return

5.0 if FMR41 is set, clear FMR41, jump to HOLD_POINT.

6.0 Continue execution out of FLASH.

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Register Description

Figure 1.20.1 shows the flash identification register, flash memory control register 0 and flash memory

control register 1.

Flash memory control register 0 (FMR0):

Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the

operating status of the flash memory. During programming, erase, and erase-suspend operations, it

is “0”. Otherwise, it is “1”.

Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode

is entered by setting this bit to “1”, so that software commands become acceptable. To set this bit to

“1”, it is necessary to write “0” and then write “1” in succession. To set this bit to “0” by only writing a

“0”.

Bit 2 of the flash memory control register 0 allows program and erase operations to occur on the two

8K byte user blocks. When this bit is set to "0", no program or erase operations can occur on these

blocks. To permit program and erase operations to occur on these blocks, set this bit to a "1". To set

this bit to “1”, it is necessary to write “0” and then write “1” in succession. This bit can be manipulated

only when the CPU rewrite mode select bit = “1” (Bit 1 of this register).

Bit 3 of the flash memory control register is the flash memory reset bit used to reset the control circuit

of the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory

access has failed. When the CPU rewrite mode select bit is “1”, writing “1” for this bit resets the control

circuit. To release the reset, it is necessary to set this bit to “0” when RY/BY status flag is “1”. Also

when this bit is set to “1”, power is not supplied to the internal flash memory, thus power consumption

can be reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit

to “1”, it is necessary to write “0” and then write “1” in succession when the CPU rewrite mode select

bit is “1”. Use this bit mainly in the low speed mode (when XCIN is the count source of BCLK).

It is not particularly necessary to set bit 3 of the flash memory control register 0 on return from STOP/

WAIT.

Figure 1.20.2c shows a flowchart for shifting to the low power dissipation mode. Always perform

operation as indicated in these flowcharts.

Bit 6 of the flash memory control register 0 is the program status flag used exclusively to read the

operating status of the auto program operation. If a program error occurs, it is set to “1”. Otherwise,

it is “0”.

Bit 7 of the flash memory control register 0 is the erase status flag used exclusively to read the

operating status of the auto erase operation. If an erase error occurs, it is set to “1”. Otherwise, it is “0”.

Figure 1.20.2a shows a EW0 mode set/reset flowchart, figure 1.20.2b shows a EW1 mode set/reset

flowchart. Always perform operation as indicated in these flowcharts.

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Flash memory control register 1 (FMR1):

Bit 1 allows the user to enter EW1 mode. This bit is relevant only if bit FMR01 is set.

Bit 7, when set to "0", inserts one wait state per access to Block A or B - regardless of the value of

PM17. Wait state insertion during access to all other blocks, as well as to internal RAM, is controlled

by PM17 - regardless of the setting of FMR17. In cases where E/W cycles to Block A or B exceed 100

times (D7, D9, U7, U9), please set FMR17 to "1" (with wait).

Flash memory control register 4 (FMR4):

Bit 0 must be set to enable the erase-suspend feature.

Bit 1 is to be used to request a suspend of an erase operation. This bit is set automatically in EW1 by

a maskable interrupt, and by software in EW0. This bit is to be always cleared by software at the end

of the erase suspend.

Bit 6 indicates suspend status. Poll this bit in EW0 after requesting a suspend, before accessing the

flash.

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Flash memory control register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

FMR0

Address

01B716

When reset

00000001

2

0

R

W

Bit name

Function

Bit symbol

0: Busy (being written or erased)

1: Ready

FMR00

RY/BY status flag

FMR01

EW entry bit

(Note 1)

0: Normal mode

(Software commands invalid)

1: EW mode

(Software commands acceptable)

8Kbyte EW mode enable bit

(Note 2)

0: EW mode disabled on 8Kbyte blocks

1: EW mode enabled on 8Kbyte blocks

FMR02

FMSTP

0: Normal operation

1: Reset

Flash memory reset bit

(Note 3, Note 5)

Must always be set to 0

Reserved bits

0: Pass

1: Error

FMR06

FMR07

Program status flag (Note 6)

Erase status flag (Note 6)

0: Pass

1: Error

Flash memory control register 1

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

FMR1

Address

01B516

When reset

0XX00101₂

0

1

R

W

Bit symbol

Bit name

Function

Reserved bit

FMR11

Must always be set to "1"

0: EW0 mode

1: EW1 mode

EW mode select bit (Note 1)

Reserved bit

Must always be set to "1"

Must always be set to "0"

Reserved bits

Nothing is assigned.

In an attempt to write to these bits, write 0. The value, if read, turns out to be

indeterminate.

Blocks A and B access wait

bit (Note 7)

0: PM17 controls wait state insertion

1: Wait state inserted (1 wait)

FMR17

Flash memory control register 4

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

FMR4

Address

01B316

When reset

01000000₂

0

R

W

Bit name

Function

Bit symbol

0: Invalid

1: Valid

FMR40

Suspend enable (Note 1)

FMR41

Suspend request (Note 4)

0: Erase restart

1: Suspend request

Reserved bits

Must always be set to 0

0: Erase Active

1: Erase Inactive

FMR46

Suspend status

Reserved bits

Must always be set to 0

Note 1: To set this bit to "1", write a "0" and then a "1" to it in succession. Make sure no interrupts or DMA

transfers occur before completion of these two write operations. While in EW0 mode, write to this

bit from a program located in other than flash memory.

Note 2: To set this bit to "1", first ensure that the CPU rewrite mode select bit is set = "1"; then write a "0"

followed by a "1" to FMR02 in succession. Make sure no interrupts or DMA transfers occur before

completion of these last two successive write operations. Additionally, bit FMR01 must also be set

to "1" prior to setting this bit to a "1".

Note 3: Effective only when the CPU rewrite mode select bit = "1". After writing "1", write "0" when RY/BY

status flag is "1".

Note 4: This bit becomes valid only when FMR40 = "1" and when in an erase operation.

•

In EW0 mode, this bit can be set to "0" or "1" by program.

•

In EW1 mode, this bit is automatically set to "1" when a maskable interrupt occurs. It can NOT be

set to "1" by program. (Writing "0" is available.)

Note 5: Write to this bit from a program in other than the flash memory.

Note 6: This flag is cleared to "0" by executing the Clear Status command.

Note 7: In cases where E/W cycles to Block A or B exceed 100 times (D7, D9, U7, U9), please set this bit

to "1" (with wait). When FMR17 is set to "1", one wait state is inserted per access to Block A or B -

regardless of the value of PM17. Wait state insertion during access to all other blocks, as well as

to internal RAM, is controlled by PM17 - regardless of the setting of FMR17.

Figure 1.20.1. Flash memory control registers 0, 1

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EW0 mode operation procedure

Program in ROM

Program in RAM

Start

*1

Single-chip mode, memory expansion

mode, or boot mode (Note 1)

(Boot mode only)

Set user ROM area select bit to

1

Set CPU rewrite mode select bit to

1

(by

Set processor mode register (Note 2)

writing

0 and then 1 in succession)(Note 3)

Transfer CPU rewrite mode control

program to internal RAM

Using software command execute erase,

program, or other operation

(Set lock bit disable bit as required)

Jump to transferred control program in RAM

(Subsequent operations are executed by control

program in this RAM)

Execute read array command or reset flash

memory by setting flash memory reset bit (by

writing

1 and then 0 in succession) (Note 4)

*1

Write

0 to CPU rewrite mode select bit

(Boot mode only)

Write

0

to user ROM area select bit (Note 5)

End

Note 1: In EW0 mode, must not be set to boot mode.

Note 2: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6

at address 000616 and bits 6 and 7 at address 000716):

6.25 MHz or less when wait bit (bit 7 at address 000516) =

10.0 MHz or less when wait bit (bit 7 at address 000516) =

Note 3: For CPU rewrite mode select bit to be set to 1 , the user needs to write a

0

1

(without internal access wait state)

(with internal access wait state)

0 and then a 1 to it in

succession. When it is not this procedure, it is not enacted in 1 . This is necessary to ensure that no

interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of

an area other than the internal flash memory. Also only when NMI pin is

H level.

Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to

execute a read array command or reset the flash memory.

Note 5:

1 can be set. However, when this bit is 1 , user ROM area is accessed.

Figure 1.20.2a. EW0 mode set/reset flowchart

EW1 mode operation procedure

Program in ROM

Start

Single-chip mode or memory expansion mode

(Note 1)

Set processor mode register (Note 2)

Set EW1 mode select bit to

having set EW0 mode select bit to

(by writing and then in succession)(Note 3)

1 after

1

0

1

Using software command execute erase,

program, or other operation

(Set lock bit disable bit as required)

Write

0

to EW0 mode select bit

End

Note 1: In EW0 mode, must not be set to boot mode.

Note 2: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit (bit 6

at address 000616 and bits 6 and 7 at address 000716):

6.25 MHz or less when wait bit (bit 7 at address 000516) =

10.0 MHz or less when wait bit (bit 7 at address 000516) =

Note 3: For CPU rewrite mode select bit to be set to 1 , the user needs to write a

0

1

(without internal access wait state)

(with internal access wait state)

0 and then a 1 to it in

succession. When it is not this procedure, it is not enacted in 1 . This is necessary to ensure that no

interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of

an area other than the internal flash memory. Also only when NMI pin is

H level.

Note 4: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to

execute a read array command or reset the flash memory.

Note 5:

1 can be set. However, when this bit is 1 , user ROM area is accessed.

Figure 1.20.2b. EW1 mode set/reset flowchart

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Program in ROM

Start

Program in RAM

*1

Set CPU rewrite mode select bit to 1

(by writing 0 and then 1 in succession)

Transfer the program to be executed in the low

power dissipation mode, to the internal RAM.

Jump to transferred control program in RAM

(Subsequent operations are executed by control

program in this RAM)

Set flash memory reset bit to 1

(by writing 0 and then 1 in succession)(Note 1)

Switch the count source of BCLK.

*1

X

IN stop. (Note 2)

Process of low power dissipation mode

XIN oscillating

Wait until the XIN has stabilized

Switch the count source of BCLK (Note 2)

Set flash memory reset bit to 0

Set CPU rewrite mode select bit to 0

Wait time until the internal circuit stabilizes (10 µs)

(Note 3)

End

Note 1: For flash memory reset bit to be set to 1 , the user needs to write a 0 and then a 1 to it in succession.

When it is not this procedure, it is not enacted in 1 . This is necessary to ensure that no interrupt or DMA

transfer will be executed during the interval.

Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which

the count source is going to be switched must be oscillating stably.

Note 3: Make a waiting time for 10 µs by software.

In this waiting time, do not access flash memory.

Figure 1.20.2c. Shifting to the low power dissipation mode flowchart

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Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.

(1) Operation speed

During CPU rewrite mode (EW0/EW1 mpde), set the BCLK as shown below using the main clock

divide ratio select bit (bit 6 at address 000616 and bits 6 and 7 at address 000716):

10.0 MHz or less when wait bit (bit 7 at address 000516) = 1 (with internal access wait state)

Note : Always perform it with a condition mentioned above.

(2) Instructions inhibited against use

The instructions listed below cannot be used during EW0 mode because they refer to the internal data

of the flash memory:

UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

(3) Interrupts inhibited against use

The address match interrupt cannot be used during EW0 mode because they refer to the internal data

of the flash memory. If interrupts have their vector in the variable vector table, they can be used by

transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be used to

automatically initialize the flash identification register and flash memory control register 0 to “0”, then

return to normal operation. However, these two interrupts' jump addresses are located in the fixed

vector table and there must exsist a routine to be executed. Since the rewrite operation is halted when

an NMI or watchdog timer interrupts occurs, you must reset the CPU rewite mode select bit to “1” and

the perform the erase/program operation again.

(4) How to access

For EW0 mode select bit and lock bit disable select bit to be set to “1”, the user needs to write a “0” and

then a “1” to it in succession. When it is not this procedure, it is not enacted in “1”. This is necessary

to ensure that no interrupt or DMA transfer will be executed during the interval. Also only when NMI

pin is “H” level.

(5) Writing in the user ROM area

If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite

mode, those blocks may not be correctly rewritten and it is possible that the flash memory can no

longer be rewritten after that. Therefore, it is recommended to use the standard serial I/O mode or

parallel I/O mode to rewrite these blocks.

(6) STOP/WAIT

Both instructions disrupt erase/program operation, and the state of the blocks operated upon is not

guaranteed. Inhibit these instructions when in CPU rewrite mode.

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Software Commands

Table 1.20.1 lists the software commands available with the M16C/26 (flash memory version).

After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or

program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.

The content of each software command is explained below.

The first bus cycle commands must be written to an even address in the user ROM area.

Table 1.20.1. List of software commands (CPU rewrite mode)

First bus cycle

Address

S

econd bus cycle

Address

Command

Read array

Data

to D

Data

to D7)

Mode

Read

(D

0

7

)

(D

0

Write

X

FF16

7016

5016

4016

2016

X

Read status register

Clear status register

Program

SRD^{(Note 2)}

X

(Note 3)

(Note 4)

(Note 3)

WA

X

WD

Write

WA

BA

Block erase

D016

Note 1: When a software command is input, the high-order byte of data (D8 to D15) is ignored.

Note 2: SRD = Status Register Data (Set an address to even address in the user ROM area)

Note 3: WA = Write Address (even address), WD = Write Data (16-bit data)

Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)

Note 5: X denotes a given address in the user ROM area (that is an even address).

Read Array Command (FF16)

The read array mode is entered by writing the command code “FF16” in the first bus cycle. When an

even address to be read is input in one of the bus cycles that follow, the content of the specified

address is read out at the data bus (D0–D15), 16 bits at a time.

The read array mode is retained intact until another command is written.

However, please begin to read data in the following procedures when a user uses read array com-

mand after program command.

(1) Set FF16, FF16, FF16, FF16 to arbitrary continuing four address beforehand

(2) Input the top address which FF16 was set at (in read array mode)

(3) Input the top address till FFFF16 agrees with the value that begins to have been read

(4) Input top address +2

(5) Input top address +2 till FFFF16 agrees with the value that begins to have been read

(6) Input an arbitrary address

Read Status Register Command (7016)

When the command code “7016” is written in the first bus cycle, the content of the status register is

read out at the data bus (D0–D7) by a read in the second bus cycle (Set an address to even address

in the user ROM area).

The status register is explained in the next section.

In EW1 mode, cannot use read status register command.

Clear Status Register Command (5016)

This command is used to clear the bits SR4 and SR5 of the status register after they have been set.

These bits indicate that operation has ended in an error. To use this command, write the command

code “5016” in the first bus cycle.

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Program Command (4016)

Program operation starts when the command code “4016” is written in the first bus cycle. Then, if the

address and data to program are written in the 2nd bus cycle, program operation (data programming

and verification) will start. Make an address in the first bus cycle same as an address to program by

the second bus cycle.

Whether the write operation is completed can be confirmed by reading the status register or the RY/

BY status flag. When the program starts, the read status register mode is accessed automatically and

the content of the status register is read into the data bus (D0 - D7). The status register bit 7 (SR7) is

set to 0 at the same time the write operation starts and is returned to 1 upon completion of the write

operation. In this case, the read status register mode remains active until the Read Array command

(FF16) is written.

The RY/BY status flag is 0 during write operation and 1 when the write operation is completed as is

the status register bit 7.

At program end, program results can be checked by reading the status register.

Figure 1.20.3 shows an example of a program flowchart.

Each block of the flash memory can be write protected by using a lock bit. For details, refer to the

section where the data protect function is detailed.

Additional writes to the already programmed pages are prohibited.

Do a command to use in right after of program command as follows

Make an address in the first bus cycle same as an address to program by the second bus cycle of

program command.

Start

(Set an address to even address in the

Write 4016

user ROM area when write 4016

)

Write data to target

address

(Set an address to even address in the user

ROM area when reading the status register)

Status register

read

SR7=1?

or

RY/BY=1?

NO

YES

Program

error

SR4=0?

YES

Program

completed

Figure 1.20.3. Program flowchart

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Block Erase Command (2016/D016)

By writing the command code “2016” in the first bus cycle and the confirmation command code “D016”

in the second bus cycle that follows to the block address of a flash memory block, the system initiates

an auto erase (erase and erase verify) operation.

Whether the auto erase operation is completed can be confirmed by reading the status register or the

flash memory control register 0. At the same time the auto erase operation starts, the read status

register mode is automatically entered, so the content of the status register can be read out. The

status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned

to 1 upon completion of the auto erase operation. In this case, the read status register mode remains

active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the

flash memory is reset using its reset bit.

The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1

when the auto erase operation is completed as is the status register bit 7.

After the auto erase operation is completed, the status register can be read out to know the result of

the auto erase operation. For details, refer to the section where the status register is detailed.

Figure 1.20.4 shows an example of a block erase flowchart.

Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer

to the section where the data protect function is detailed.

During EW1 mode, do not execute this command on blocks in which the control program is stored.

Start

(Set an address to even address in the

Write 2016

user ROM area when write 2016

)

Write D016

Block address

(Set an address to even address in the user

ROM area when reading the status register)

Status register

read

SR7=1?

or

RY/BY=1?

NO

YES

Error

Check full status check

(Note 1)

Erase error (Note 2)

Block erase

completed

Note 1: Refer to Figure 1.20.6

Note 2: If the error occurs, try to execute clear status register command,

then block erase command at least three times until erase error

disappears.

Figure 1.20.4. Block erase flowchart

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CPU Rewrite Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(EW0 mode)

Start

Interrupt (Note 3)

FMR41=1

FMR40=1

Write 'XX2016' (Note 1)

NO

FMR46=1?

Write 'XXD016' to the

uppermost address

(Note 1)

YES

Access to Flash Memory

NO

FMR41=0

REIT

FMR00=1?

YES

Full Status Check

(Note 2, 4)

Block erase

completed

(EW1 mode)

Start

Interrupt

Access to Flash Memory

REIT

FMR40=1

Write 'XX2016' (Note 1)

Write 'XXD016' to the

uppermost address

(Note 1)

FMR41=0

NO

FMR00=1?

YES

Full Status Check

(Note 2, 4)

Block erase

completed

Note 1: Write value to highest even address within the block.

Note 2: If the error occurs, try to execute Clear Status Register command then

Block Erase command at least three times until erase error disappears.

Note 3: Please set interrupt vector table on RAM region with EW0 mode.

Note 4: Please refer to Figure 1.20.6, "Full status check flowchart and remedial

procedure for errors".

Figure 1.20.5. Block erase flowchart with erase suspend function

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CPU Rewrite Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Status Register

The status register shows the operating state of the flash memory and whether erase operations and

programs ended successfully or in error. It can be read only in the EW0 mode, in the following ways. The

status cannot be read out in the EW1 mode and during suspend.

(1) By reading an arbitrary even address from the user ROM area after writing the read status register

command (7016)

(2) By reading an arbitrary even address from the user ROM area in the period from when the program

starts or erase operation starts to when the read array command (FF16) is input

Table 1.20.2 shows the status register.

In the EW1 mode, the status corresponding to the below is stored in the flash memory control register 0.

Read this register for status check.

Also, the status register can be cleared in the following way.

(1) By writing the clear status register command (5016)

After a reset, the status register is set to “8016”.

Each bit in this register is explained below.

Sequencer status (SR7) / FMR00

After power-on, the sequencer status is set to 1(ready).

The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy)

during write or erase operation and is set to “1” upon completion of these operations.

Erase status (SR5) / FMR07

The erase status informs the operating status of erase operation to the CPU. When an erase error

occurs, it is set to “1”.

The erase status is reset to “0” when cleared.

Program status (SR4)

The program status informs the operating status of write operation to the CPU. When a write error

occurs, it is set to “1”.

The program status is reset to “0” when cleared.

When an erase command is in error (which occurs if the command entered after the block erase

command (2016) is not the confirmation command (D016), both the program status and erase status

(SR5) are set to “1”.

When the program status or erase status =“1”, only the following flash commands will be accepted:

Read Array, Read Status Register, and Clear Status Register.

Also, in one of the following cases, both SR4 and SR5 are set to 1 (command sequence error):

(1) When the valid command is not entered correctly

(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase

(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is

entered, read array is assumed and the command that has been set up in the first bus cycle is

canceled.

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CPU Rewrite Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Table 1.20.2. Definition of each bit in status register

Definition

Each SRD bit

Status name

“1”

“0”

SR7 (D )

Write state machine (WSM)

Reserved

Ready

Busy

7

SR6 (D )

_

6

SR5 (D )

Erase status

Terminated in error

Terminated normally

5

SR4 (D )

Program status

Program status after program

Reserved

Terminated in error

Terminated normally

4

SR4 (D )

Terminated in error

Terminated normally

3

SR2 (D )

_

2

SR1 (D )

Reserved

1

SR0 (D )

Reserved

0

Full Status Check

By performing full status check, it is possible to know the execution results of erase and program

operations. Figure 1.20.6 shows a full status check flowchart and the action to be taken when each

error occurs.

(Set an address to even when reading the status register)

Read status register

SR4=1/FMR06

and

SR5=1/FMR07?

YES

(1) Execute the Clear Status Register command (5016) to clear

Command

sequence error

the status register.

(2) Try performing the operation one more time after confirming

that the command is entered correctly.

NO

(1) Execute the Clear Status Register command to set the erase

SR5=0?/FMR07?

Block erase error

Program error

status flag to "0".

.

(2) Re-execute the Block Erase command.

(3) Until erase error disappears, please retry (1) and (2) at least

3 times.

YES

Note 1: If the error still occurs, the block in error cannot be used.

[During programming]

(1) Execute the Clear Status Register command to set the

program status flag to "0".

(2) Re-execute the Program command.

Note 2: If the error still occurs, the block in error cannot be used.

SR4=0?/FMR06?

YES

End (block erase, program)

Note: When one of SR5 to SR4 is set to 1, neither program nor block erase commands

are accepted. Execute the clear status register command (50¹⁶) before executing

these commands.

Figure 1.20.6. Full status check flowchart and remedial procedure for errors

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Functions to Inhibit Rewriting Flash Memory Version

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Functions To Inhibit Rewriting Flash Memory Version

To prevent the contents of the flash memory version from being read out or rewritten easily, the device

incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for

use in standard serial I/O mode.

ROM code protect function

The ROM code protect function is used to prohibit reading out or modifying the contents of the flash

memory during parallel I/O mode and is set by using the ROM code protect control address register

(0FFFFF16). Figure 1.21.1 shows the ROM code protect control address (0FFFFF16). (This address

exists in the user ROM area.)

If either bit of ROMCP1 is set to '0', ROM code protect level 1 is turned on, so that the contents of the flash

memory are protected against readout and modification.

If either bit of ROMCP2 is set to '0', ROM code protect level 2 is turned on, enabling additional protection

against readout and modification (such as by a production LSI tester). If both level 1 and level 2 are

enabled, level 2 is selected by default.

If both of the two ROM code protect reset bits are set to “00,” ROM code protect is turned off, so that the

contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,

the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/

O or some other mode to rewrite the contents of the ROM code protect reset bits.

ROM code protect control address

b7 b6 b5 b4 b3 b2 b1 b0

Symbol

ROMCP

Address

0FFFFF16

When reset

FF16

1

Bit symbol

Bit name

Function

Always set this bit to 1.

Reserved bit

b3 b2

ROM code protect level 2

set bit (Note 1, 2)

ROMCP2

ROMCR

ROMCP1

00: Protect enabled

01: Protect enabled

10: Protect enabled

11: Protect disabled

b5 b4

ROM code protect reset

bit (Note 3)

00: Protect removed

01: Protect set bit effective

10: Protect set bit effective

11: Protect set bit effective

b7 b6

ROM code protect level

1 set bit (Note 1)

00: Protect enabled

01: Protect enabled

10: Protect enabled

11: Protect disabled

Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against

readout or modification in parallel input/output mode.

Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment inspection

LSI tester, etc. also is inhibited. Customers desiring to use ROM code protect level 2 should

first contact their Renesas technical support representative.

Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and

.

ROM code protect level 2. However, since these bits cannot be changed in parallel input/

output mode, they need to be rewritten in serial input/output or some other mode

Figure 1.21.1. ROM code protect control address

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Functions to Inhibit Rewriting Flash Memory Version

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

ID Code Check Function

Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the

ID code sent from the peripheral unit is compared with the ID code written in the flash memory to see if

they match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted.

The ID code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF16,

0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program which has had

the ID code preset at these addresses to the flash memory.

Address

ID1 Undefined instruction vector

ID2 Overflow vector

0FFFDC16 to 0FFFDF16

0FFFE016 to 0FFFE316

0FFFE416 to 0FFFE716

0FFFE816 to 0FFFEB16

0FFFEC16 to 0FFFEF16

0FFFF016 to 0FFFF316

0FFFF416 to 0FFFF716

0FFFF816 to 0FFFFB16

0FFFFC16 to 0FFFFF16

BRK instruction vector

ID3 Address match vector

ID4 Single step vector

ID5 Watchdog timer vector

ID6 DBC vector

ID7 NMI vector

Reset vector

4 bytes

Figure 1.21.2. ID code store addresses

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Appendix Standard Serial I/O Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Appendix Standard Serial I/O Mode (Flash Memory Version)

Table 1.22.1. Pin functions (Flash memory standard serial I/O mode)

Name

Power input

I/O

Description

V

CC,VSS

Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.

CNVSS

RESET

CNVSS

I

Connect to Vcc pin.

Reset input

Reset input pin. While reset is "L" level, a 20 cycle or longer clock

must be input to XIN pin.

Connect a ceramic resonator or crystal oscillator between XIN and

X

IN

OUT

Clock input

I

O

I

X

OUT pins. To input an externally generated clock, input it to XIN pin

and open XOUT pin.

X

Clock output

Connect AVss to Vss and AVcc to Vcc, respectively

This pin must be left unconnected.

Enter the reference voltage for AD from this pin.

Input "H" or "L" level signal or open

Input "H" or "L" level signal or open.

Analog power supply input

AVCC, AVSS

IVCC

Power supply

I

V

REF

Reference voltage input

Input port P1

Input port P6

P1

0

to P1

7

3

I

P6

to P6

Standard serial I/O mode 1: BUSY signal output pin

Standard serial I/O mode 2: Monitors the boot program operation

check signal output pin.

BUSY output

O

P6

4

Standard serial I/O mode 1: Serial clock input pin

Standard serial I/O mode 2: Input "L".

SCLK input

I

5

RxD input

I

P6

6

7

Serial data input pin

TxD output

Input port P7

O

Serial data output pin

Input "H" or "L" level signal or open.

P70 to P7

P80 to P8

P86, P8

7

I

3,

Input "H" or "L" level signal or open.

Input "H" level signal.

Input port P8

7

CE input

I

P8

6

Input port P9

Input port P10

Input "H" or "L" level signal or open.

P90 to P9

7

I

P100 to P10

7

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Appendix Standard Serial I/O Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

27 26 25

28

29

35 34 33 32 31 30

36

37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

P10

7

6

5

/AN

7

6

5

/KI

3

2

1

P7

1

/RXD

2

/SCL/TA0IN

/TA1OUT/V

/RTS /TA1IN/V

*

P72

/CLK

/CTS

/TA2OUT

/TA2IN

/TA3OUT

/TA3IN

/TA4OUT/U

/TA4IN/U

/INT

2

P73

2

P10

4

/AN

AVSS

/AN

4

/KI

0

P74

3

P75

M16C/26 Group

(Flash Memory Version)

2

P7

P8

6

7

0

1

P10

1

P10

0

V

REF

2

0

Vss

Vcc

V

P9

CC

3

1

3

IVCC (This pin must be

left unconnected.)

1

2

3

4

5

6

8 9 10 11 12

7

Package: 48P6Q-A

Mode setup method

Signal

Value

CNVss

Vcc

CE

RESET

Vcc

Vss to Vcc

Connect

oscillator

circuit.

Figure 1.22.1. Pin connections for serial I/O mode (1)

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Appendix Standard Serial I/O Mode (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Standard Serial I/O mode

The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to

operate (read, program, erase, etc.) the internal flash memory using the serial I/O port UART1. The serial

I/O mode transfers the data serially in 8-bit units.

The standard serial I/O mode is different from the parallel I/O mode in that the CPU executes a control

program for flash memory rewrite (using the CPU's rewrite mode), rewrite data input and so forth. It is

started when both the P86(CE) pin and the CNVss pin are in “H” level after the reset is released. (In normal

operation mode, set CNVss pin to “L” level.)

Figure 1.22.1 shows the pin connections for the standard serial I/O mode.

There are actually two standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which

is asynchronized. Standard serial I/O switches between mode 1 (clock synchronous) and mode 2 (clock

asynchronous) depending on the level of CLK1 pin when the reset is released.

To use standard serial I/O mode 1 (clock synchronous), set the CLK1 pin to “H” level and release the reset.

The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer

clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The

RTS1 (BUSY) pin outputs an “L” level when ready for reception and an "H" level when reception starts. In

mode 1, be sure the TXD1 (P67) pin is at high before reset being deasserted.

To use standard serial I/O mode 2 (clock asynchronous), set the CLK1 pin to “L” level and release the reset.

The operation uses the two UART1 pins RxD1 and TxD1.

In the standard serial I/O mode, only the user ROM area indicated in Figure 1.19.1 can be rewritten. In

addition, a 7-byte ID code exists to protect the device. When there is data in the flash memory, commands

sent from the peripheral unit are not accepted unless the ID code matches.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Overview of standard serial I/O mode 1 (clock synchronous)

In standard serial I/O mode 1, software commands, addresses and data are input and output between

the microcomputer and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/

O (UART1). Standard serial I/O mode 1 is entered by releasing the reset with the P65 (CLK1) pin “H” level

(and P86 (CE) pin and the CNVss pin are in “H” level).

When receiving software commands, addresses and program data are synchronized with the rising edge

of the transfer clock that is input to the CLK1 pin, and are then input to the RXD1 pin. When transmitting,

read data and status are synchronized with the falling edge of the transfer clock, and output from the

TxD1 pin. The data transfer is in 8-bit units with LSB first.

The TxD1 pin is a CMOS level output.

When the device is busy, such as during transmission, reception, erasing or program execution, the

RTS1 (BUSY) pin is “H” level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is “L”

level.

Also, data and status registers in memory can be read after inputting software commands. Status, such

as the operating state of the flash memory or whether a program or erase operation ended successfully

or not, can be checked by reading the status register. The following table shows the software com-

mands, status registers, etc. in serial I/O mode 1.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software Commands

Table 1.22.2 lists the software commands, and their descriptions, in standard serial I/O mode 1. Erase

operations, programming, reading status, etc. are controlled by transferring software commands via the

RxD1 pin.

Table 1.22.2. Software commands (Standard serial I/O mode 1) (Note 1)

5th

Byte

6th

Byte

1st Byte

Transfer

2nd

Byte

3rd

Byte

4th

Byte

... nth

Byte

When ID is

not verified

Control Command

Page read (Note 2)

1

Data

output to

259th byte

Address

(middle)

Address

(high)

Not

acceptable

Data

output

Data

output

FF16

4116

20¹⁶

Data

output

Data

input to

259th byte

Not

acceptable

2

3

Data

input

Data

input

Page program

Block erase

Address

(middle)

Data

input

Address

(high)

Not

acceptable

Address

(middle)

Address

(high)

D016

Not

acceptable

4

5

Erase all code blocks (Note 4)

Read status register (Notes 2,3)

D016

A7¹⁶

7016

Acceptable

SRD

output

SRD1

output

Not

acceptable

6

Clear status register

ID check function

Download function

50¹⁶

Address

(high)

Acceptable

Address

(low)

Address

(middle)

ID1

ID size

To ID7

7

8

9

F516

FA¹⁶

FB¹⁶

Not

acceptable

To required

no. of times

Size

(low)

Size

(high)

Data

input

Checksum

Version data output function

(Note 2)

Version

data

output

Version

data

output

Acceptable

Version

data

output

Version

data output

to 9th byte

Version

data

output

Version

data

output

10

Read check data (Note 2)

Not

acceptable

Check

data

FD16

Check

data

(high)

(low)

Note 1:All commands can be accepted when the flash memory is totally blank.

Note 2:Shaded area indicates transfer from flash memory microcomputer to peripheral unit. All other data is

transferred from the peripheral unit to the flash memory microcomputer.

Note 3:SRD refers to status register data. SRD1 refers to status register 1 data.

Note 4: The 'erase all' command does not erase the Flash data blocks.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page read command as explained here following.

(1) Transfer the “FF16” command code with the 1st byte.

(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to

A23 will be output sequentially from the smallest address first in sync with the fall of the clock.

CLK1

A

8

to

A16 to

A23

RxD1

(M16C reception data)

FF16

A15

TxD1

(M16C transmit data)

data0

data255

RTS1(BUSY)

Figure 1.22.2. Timing for page read

Read Status Register Command

This command reads status information. When the “7016” command code is sent with the 1st byte, the

contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1

(SRD1) specified with the 3rd byte are read.

CLK1

RxD1

7016

(M16C reception data)

SRD

output

SRD1

output

TxD1

(M16C transmit data)

RTS1(BUSY)

Figure 1.22.3. Timing for reading the status register

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clear Status Register Command

This command clears the bits (SR4, SR5) which are set when the status register operation ends in error.

When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared. When the

clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level.

CLK1

RxD1

5016

(M16C reception data)

TxD1

(M16C transmit data)

RTS1(BUSY)

Figure 1.22.4. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the “4116” command code with the 1st byte.

(2) Transfer addresses A

(3) From the 4th byte onward, as write data (D

to A23 is input sequentially from the smallest address first, that page is automatically written.

8

to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

0

–D ) for the page (256 bytes) specified with addresses

7

A

8

When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to

the “L” level. The result of the page program can be known by reading the status register. For more

information, see the section on the status register.

Each block can be write-protected with the lock bit. For more information, see the section on the data

protection function. Additional writing is not allowed with already programmed pages.

CLK1

RxD1

(M16C reception data)

A

8

to

A16 to

A23

4116

data0

data255

A15

TxD1

(M16C transmit data)

RTS1(BUSY)

Figure 1.22.5. Timing for the page program

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Block Erase Command

This command erases the data in the specified block. Execute the block erase command as explained

here following.

(1) Transfer the “2016” command code with the 1st byte.

(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

(3) Transfer the verifycommand code “D016” with the 4th byte. With the verify command code, the

erase operation will start for the specified block in the flash memory. Write the highest address of

the specified block for addresses A8 to A23.

When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. After block

erase ends, the result of the block erase operation can be known by reading the status register. For

more information, see the section on the status register.

Each block can be erase-protected with the lock bit. For more information, see the section on the data

protection function.

CLK1

RxD1

(M16C reception data)

A

8

to

A16 to

A23

2016

D016

A15

TxD1

(M16C transmit data)

RTS1(BUSY)

Figure 1.22.6. Timing for block erasing

Erase All Code Blocks Command

This command erases the content of all code blocks. Execute the erase all code blocks command as

explained here following.

(1) Transfer the “A716” command code with the 1st byte.

(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the

erase operation will start and continue for all code blocks in the flash memory.

When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of

the erase operation can be known by reading the status register.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CLK1

RxD1

A716

D016

(M16C reception data)

TxD1

(M16C transmit data)

RTS1(BUSY)

Figure 1.22.7. Timing for erasing all code blocks.

Download Command

This command downloads a program to the RAM for execution. Execute the download command as

explained here following.

(1) Transfer the “FA16” command code with the 1st byte.

(2) Transfer the program size with the 2nd and 3rd bytes.

(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th

byte onward.

(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.

The size of the program will vary according to the internal RAM.

CLK1

Program

data

RxD1

(M16C reception data)

Check

sum

Program

data

FA16

Data size (low)

TxD1

Data size (high)

(M16C transmit data)

RTS1(BUSY)

Figure 1.22.8. Timing for download

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Version Information Output Command

This command outputs the version information of the control program. Execute

the version information output command as explained here following.

(1) Transfer the “FB16” command code with the 1st byte.

(2) The version information will be output from the 2nd byte onward. This data is composed of 8

ASCII code characters.

CLK1

RxD1

FB16

(M16C reception data)

TxD1

(M16C transmit data)

'V'

'E'

'R'

'X'

RTS1(BUSY)

Figure 1.22.9. Timing for version information output

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

ID Check

This command checks the ID code. Execute the boot ID check command as explained here following.

(1) Transfer the “F516” command code with the 1st byte.

(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,

3rd and 4th bytes respectively.

(3) Transfer the number of data sets of the ID code with the 5th byte.

(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

CLK1

RxD1

ID size

ID1

ID7

F516

DF16

FF16

0F16

(M16C reception

data)

TxD1

(M16C transmit

data)

RTS1(BUSY)

Figure 1.22.10. Timing for the ID check

ID Code

When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written

in the flash memory are compared to see if they match. If the codes do not match, the command sent

from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,

addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write

a program into the flash memory, which already has the ID code set for these addresses.

Address

ID1 Undefined instruction vector

ID2 Overflow vector

0FFFDC16 to 0FFFDF16

0FFFE016 to 0FFFE316

0FFFE416 to 0FFFE716

0FFFE816 to 0FFFEB16

0FFFEC16 to 0FFFEF16

0FFFF016 to 0FFFF316

0FFFF416 to 0FFFF716

0FFFF816 to 0FFFFB16

0FFFFC16 to 0FFFFF16

BRK instruction vector

ID3 Address match vector

ID4 Single step vector

ID5 Watchdog timer vector

ID6 DBC vector

ID7 NMI vector

Reset vector

4 bytes

Figure 1.22.11. ID code storage addresses

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page

program command, was successfully received.

(1) Transfer the "FD16" command code with the 1st byte.

(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.

Next, execute the page program command the required number of times. After that, when the read

check command is executed again, the check data for all of the read data that was sent with the page

program command during this time is read. The check data is the result of CRC operation of write data.

CLK1

RxD1

FD16

(M16C reception data)

TxD1

(M16C transmit data)

Check data (high)

Check data (low)

RTS1(BUSY)

Figure 1.22.12. Timing for the read check data

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Status Register (SRD)

The status register indicates operating status of the flash memory and status such as whether an erase

operation or a program ended successfully or in error. It can be read by writing the read status register

command (7016). Also, the status register is cleared by writing the clear status register command (5016).

Table 1.22.3 gives the definition of each status register bit. After clearing the reset, the status register

outputs “8016”.

Table 1.22.3. Status register (SRD)

Definition

SRD0 bits

Status name

“1”

“0”

Sequencer status

Reserved

Ready

Busy

SR7 (bit7)

SR6 (bit6)

SR5 (bit5)

SR4 (bit4)

SR3 (bit3)

SR2 (bit2)

SR1 (bit1)

SR0 (bit0)

-

Erase status

Program status

Reserved

Terminated in error

Terminated normally

Terminated in error

Terminated normally

-

Reserved

Sequencer status (SR7)

After power-on, the sequencer status is set to 1(ready).

The sequencer status indicates the operating status of the device. This status bit is set to “0” (busy)

during write or erase operation and is set to 1 upon completion of these operations.

Erase Status (SR5)

The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is

set to “1”. When the erase status is cleared, it is set to “0”.

Program Status (SR4)

The program status reports the operating status of the auto write operation. If a write error occurs, it is

set to “1”. When the program status is cleared, it is set to “0”.

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Status Register 1 (SRD1)

Status register 1 indicates the status of serial communications, results from ID checks and results from

check sum comparisons. It can be read after the SRD by writing the read status register command (7016).

Also, status register 1 is cleared by writing the clear status register command (5016).

Table 1.22.4 gives the definition of each status register 1 bit. “0016” is output when power is turned ON

and the flag status is maintained even after the reset.

Table 1.22.4. Status register 1 (SRD1)

Definition

SRD1 bits

Status name

"1"

"0"

Not update

DINOR

-

SR15 (bit7)

SR14 (bit6)

SR13 (bit5)

SR12 (bit4)

SR11 (bit3)

SR10 (bit2)

Boot update completed bit

Flash identification value

Reserved

Update completed

HND

-

Check sum match bit

ID check completed bits

Match

Mismatch

00

01

10

11

Not verified

Verification mismatch

Reserved

Verified

Time out

-

SR9 (bit1)

SR8 (bit0)

Data receive time out

Reserved

Normal operation

-

Boot Update Completed Bit (SR15)

This flag indicates whether the control program was downloaded to the RAM or not, using the down-

load function.

Flash Identification Value (SR14)

This flag indicates whether the flash memor type is HND or DINOR.

Check Sum Match Bit (SR12)

This flag indicates whether the check sum matches or not when a program, is downloaded for execu-

tion using the download function.

ID Check Completed Bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commands cannot be accepted without an ID check.

Data Receive Time Out (SR9)

This flag indicates when a time out error is generated during data reception. If this flag is attached during

data reception, the received data is discarded and the microcomputer returns to the command wait state.

d

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development

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Full Status Check

Results from executed erase and program operations can be known by running a full status check.

Figure 1.22.13 shows a flowchart of the full status check and explains how to remedy errors which occur.

Read status register

YES

Execute the clear status register command (5016

to clear the status register. Try performing the

operation one more time after confirming that the

command is entered correctly.

)

Command

sequence error

SR4=1 and SR5

=1 ?

NO

Should a block erase error occur, the block in error

cannot be used.

Block erase error

Program error

SR5=0?

YES

Execute the read lock bit status command (7116

)

SR4=0?

YES

to see if the block is locked. After removing lock,

execute write operation in the same way. If the

error still occurs, the page in error cannot be

used.

End (block erase, program)

Note: When one of SR5 to SR4 is set to 1, none of the program, erase all blocks, and

block erase commands is accepted. Execute the clear status register command

(5016) before executing these commands.

Figure 1.22.13. Full status check flowchart and remedial procedure for errors

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development

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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Example Circuit Application for The Standard Serial I/O Mode 1

The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary

according to programmer, therefore see the peripheral unit manual for more information.

Clock input

BUSY output

Data input

CLK1

RTS1(BUSY)

R

XD1

TXD1

Data output

M16C/26 Group

(Flash memory version)

CNVss

P86(CE)

(1) Control pins and external circuitry will vary according to peripheral unit.

For more information, see the peripheral unit manual.

(2) In this example, the microprocessor mode and standard serial I/O mode

are switched via a switch.

Figure 1.22.14. Example circuit application for the standard serial I/O mode 1

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Overview of standard serial I/O mode 2 (clock asynchronized)

In standard serial I/O mode 2, software commands, addresses and data are input and output between the

microcomputer and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O

(UART1). Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin “L” level

and P86 (CE) pin and the CNVss pin are in “H” level).

The TxD1 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.

After the reset is released, connections can be established at 9,600 bps when initial communications

(Figure 1.23.1) are made with a peripheral unit that requires a main clock with a minimum 2 MHz input

oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by

executing software commands. However, if communication errors due to the oscillation frequency of the

main clock, change the main clock's oscillation frequency and the baud rate.

After executing commands from a peripheral unit that requires time, i.e. erase, or write (program) data,

allow sufficient time to pass or execute the read status command to check the device status, before execut-

ing the next command.

Data and status registers in memory can be read after transmitting software commands. Status, such as

the operating state of the flash memory or whether a program or erase operation ended successfully or not,

can be checked by reading the status register. The following describes the initial communications with

peripheral units, how frequency is identified, and software commands.

Initial communications with peripheral units

After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-

quency of the main clock, by sending the code as prescribed by the protocol for initial communications

with peripheral units (Figure 1.23.1).

(1) Transmit “B016” from a peripheral unit. If the oscillation frequency input by the main clock is 10 or 16

MHz, the microcomputer with internal flash memory outputs the “B016” check code. If the oscillation

frequency is anything other than 10 or 16 MHz, the microcomputer does not output anything.

(2) Transmit “0016” from a peripheral unit 16 times. (The microcomputer with internal flash memory sets the

bit rate generator so that “0016” can be successfully received.)

(3) The microcomputer with internal flash memory outputs the “B016” check code and initial communica-

1

tions end successfully * . Initial communications must be transmitted at a speed of 9,600 bps and a

transfer interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600

bps.

*1. If the peripheral unit cannot receive “B016” successfully, change the oscillation frequency of the main clock.

Microcomputer with

Peripheral unit

internal flash memory

Reset

(1) Transfer "B016

"

"B016

"

If the oscillation frequency input

by the main clock is 10 or 16 MHz,

the microcomputer outputs "B016".

If other than 10 or 16 MHz, the

microcomputer does not output

anything.

(2) Transfer "0016" 16 times

"0016

"

1st

At least 15ms

transfer interval

2nd

"0016

"

15 th

16th

"B016

"

(3) Transfer check code "B016"

The bit rate generator setting completes (9600bps)

Figure 1.23.1. Peripheral unit and initial communication

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

How frequency is identified

When “0016” data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the

bit rate generator is set to match the operating frequency (2 - 20 MHz). The highest speed is taken from

the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit

rate generator value for a baud rate of 9,600 bps.

Baud rate cannot be attained with some operating frequencies. Table 1.23.1 gives the operation fre-

quency and the baud rate that can be attained for.

Table 1.23.1 Operation frequency and the baud rate

Operation frequency

(MH

Baud rate

9,600bps

Baud rate

19,200bps

Baud rate

38,400bps

Baud rate

57,600bps

Z

)

20MH

Z

ꢀ

–

ꢀ

16MH

12MH

11MH

10MH

ꢀ

–

Z

–

ꢀ

–

ꢀ

8MH

Z

–

7.3728MH

Z

ꢀ

–

6MH

5MH

Z

ꢀ

–

4.5MH

4.194304MH

4MH

3.58MH

Z

–

ꢀ

–

Z

ꢀ

–

Z

ꢀ

–

ꢀ

3MH

2MH

Z

ꢀ

–

: Communications possible

ꢀ

– : Communications not possible

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software Commands

Table 1.23.2 lists software commands. In the standard serial I/O mode 2, erase operations, programs

and reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O

mode 2 adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the soft-

ware commands of standard serial I/O mode 1. Software commands are explained here below.

Table 1.23.2. Software commands (Standard serial I/O mode 2) (Note 1)

5th

Byte

6th

Byte

1st Byte

Transfer

2nd

Byte

3rd

Byte

4th

Byte

... nth

Byte

When ID is

not verified

Control Command

Page read (Note 2)

1

Data

output to

259th byte

Address

(middle)

Address

(high)

Not

acceptable

Data

output

Data

output

FF16

4116

20¹⁶

Data

output

Data

input to

259th byte

Not

acceptable

2

3

Data

input

Data

input

Page program

Block erase

Address

(middle)

Data

input

Address

(high)

Not

acceptable

Address

(middle)

Address

(high)

D0¹⁶

Not

acceptable

4

5

Erase all code blocks (Note 4)

Read status register (Notes 2,3)

D016

A7¹⁶

7016

Acceptable

SRD

output

SRD1

output

Not

acceptable

6

Clear status register

ID check function

Download function

50¹⁶

Address

(high)

Acceptable

Address

(low)

Address

(middle)

ID1

ID size

To ID7

7

8

9

F5¹⁶

FA¹⁶

FB16

Not

acceptable

To required

no. of times

Size

(low)

Size

(high)

Data

input

Checksum

Version data output function

(Note 2)

Version

data

output

Version

data

output

Acceptable

Version

data

output

Version

data output

to 9th byte

Version

data

output

Version

data

output

10

Read check data (Note 2)

Check

data

Check

data

Not

acceptable

FD16

(low)

(high)

11

12

13

14

Baud rate 9600 (Note 2)

B016

B116

B016

B116

Acceptable

Baud rate 19200 (Note 2)

Baud rate 38400 (Note 2)

Baud rate 57600 (Note 2)

B216

B316

B216

B316

Note 1:All commands can be accepted when the flash memory is totally blank.

Note 2:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is

transferred from the peripheral unit to the flash memory microcomputer.

Note 3:SRD refers to status register data. SRD1 refers to status register 1 data.

Note 4: The 'erase all' command does not erase the Flash data blocks.

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page read command as explained here following.

(1) Transfer the “FF16” command code with the 1st byte.

(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to

A23 will be output sequentially from the smallest address first.

A

8

to

A16 to

A23

RxD1

(M16C reception data)

FF16

A15

TxD1

(M16C transmit data)

data0

data255

Figure 1.23.2. Timing for page read

Read Status Register Command

This command reads status information. When the “7016” command code is sent with the 1st byte, the

contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1

(SRD1) specified with the 3rd byte are read.

RxD1

7016

(M16C reception data)

SRD

output

SRD1

output

TxD1

(M16C transmit data)

Figure 1.23.3. Timing for reading the status register

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clear Status Register Command

This command clears the bits (SR4, SR5) which are set when the status register operation ends in

error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.

RxD1

5016

(M16C reception data)

TxD1

(M16C transmit data)

Figure 1.23.4. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the “4116” command code with the 1st byte.

(2) Transfer addresses A

(3) From the 4th byte onward, as write data (D

to A23 is input sequentially from the smallest address first, that page is automatically written.

8

to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

0

–D ) for the page (256 bytes) specified with addresses

7

A

8

The result of the page program can be known by reading the status register. For more information,

see the section on the status register.

Each block can be write-protected with the lock bit. For more information, see the section on the data

protection function. Additional writing is not allowed with already programmed pages.

RxD1

(M16C reception data)

A

8

to

A16 to

A23

4116

data0

data255

A15

TxD1

(M16C transmit data)

Figure 1.23.5. Timing for the page program

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Block Erase Command

This command erases the data in the specified block. Execute the block erase command as explained

here following.

(1) Transfer the “2016” command code with the 1st byte.

(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.

(3) Transfer the verify command code “D016” with the 4th byte. With the verify command code, the

erase operation will start for the specified block in the flash memory. Write the highest address of

the specified block for addresses A8 to A23.

After block erase ends, the result of the block erase operation can be known by reading the status

register. For more information, see the section on the status register.

Each block can be erase-protected with the lock bit. For more information, see the section on the data

protection function.

RxD1

(M16C reception data)

A

8

to

A16 to

A23

2016

D016

A15

TxD1

(M16C transmit data)

Figure 1.23.6. Timing for block erasing

Erase All Code Blocks Command

This command erases the content of all code blocks. Execute the erase all code blocks command as

explained here following.

(1) Transfer the “A716” command code with the 1st byte.

(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the

erase operation will start and continue for all code blocks in the flash memory.

The result of the erase operation can be known by reading the status register.

.

RxD1

(M16C reception data)

A716

D016

TxD1

(M16C transmit data)

Figure 1.23.7. Timing for erasing all code blocks.

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Download Command

This command downloads a program to the RAM for execution. Execute the download command as

explained here following.

(1) Transfer the “FA16” command code with the 1st byte.

(2) Transfer the program size with the 2nd and 3rd bytes.

(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th

byte onward.

(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.

The size of the program will vary according to the internal RAM.

Program

data

RxD1

(M16C reception data)

Check

sum

Program

data

FA16

Data size (low)

TxD1

Data size (high)

(M16C transmit data)

Figure 1.23.8. Timing for download

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Version Information Output Command

This command outputs the version information of the control program. Execute the version informa-

tion output command as explained here following.

(1) Transfer the “FB16” command code with the 1st byte.

(2) The version information will be output from the 2nd byte onward. This data is composed of 8

ASCII code characters.

RxD1

FB16

(M16C reception data)

TxD1

(M16C transmit data)

'V'

'E'

'R'

'X'

Figure 1.23.9. Timing for version information output

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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

ID Check

This command checks the ID code. Execute the boot ID check command as explained here following.

(1) Transfer the “F516” command code with the 1st byte.

(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,

3rd and 4th bytes respectively.

(3) Transfer the number of data sets of the ID code with the 5th byte.

(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

RxD1

ID size

ID1

ID7

F516

DF16

FF16

0F16

(M16C reception

data)

TxD1

(M16C transmit

data)

Figure 1.23.10. Timing for the ID check

ID Code

When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written

in the flash memory are compared to see if they match. If the codes do not match, the command sent

from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,

addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write

a program into the flash memory, which already has the ID code set for these addresses.

Address

ID1 Undefined instruction vector

ID2 Overflow vector

0FFFDC16 to 0FFFDF16

0FFFE016 to 0FFFE316

0FFFE416 to 0FFFE716

0FFFE816 to 0FFFEB16

0FFFEC16 to 0FFFEF16

0FFFF016 to 0FFFF316

0FFFF416 to 0FFFF716

0FFFF816 to 0FFFFB16

0FFFFC16 to 0FFFFF16

BRK instruction vector

ID3 Address match vector

ID4 Single step vector

ID5 Watchdog timer vector

ID6 DBC vector

ID7 NMI vector

Reset vector

4 bytes

Figure 1.23.11. ID code storage addresses

228

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page

program command, was successfully received.

(1) Transfer the "FD16" command code with the 1st byte.

(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.

Next, execute the page program command the required number of times. After that, when the read

check command is executed again, the check data for all of the read data that was sent with the page

program command during this time is read. The check data is the result of CRC operation of write

data.

RxD1

FD16

(M16C reception data)

TxD1

(M16C transmit data)

Check data (high)

Check data (low)

Figure 1.23.12. Timing for the read check data

Baud Rate 9600

This command changes baud rate to 9,600 bps. Execute it as follows.

(1) Transfer the "B016" command code with the 1st byte.

(2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.

RxD1

B016

(M16C reception data)

TxD1

B016

(M16C transmit data)

Figure 1.23.13. Timing of baud rate 9600

229

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Baud Rate 19200

This command changes baud rate to 19,200 bps. Execute it as follows.

(1) Transfer the "B116" command code with the 1st byte.

(2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.

RxD1

B116

(M16C reception data)

TxD1

B116

(M16C transmit data)

Figure 1.23.14. Timing of baud rate 19200

Baud Rate 38400

This command changes baud rate to 38,400 bps. Execute it as follows.

(1) Transfer the "B216" command code with the 1st byte.

(2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.

RxD1

B216

(M16C reception data)

TxD1

B216

(M16C transmit data)

Figure 1.23.15. Timing of baud rate 38400

Baud Rate 57600

This command changes baud rate to 57,600 bps. Execute it as follows.

(1) Transfer the "B316" command code with the 1st byte.

(2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.

RxD1

B316

(M16C reception data)

TxD1

B316

(M16C transmit data)

Figure 1.23.16. Timing of baud rate 57600

230

Renesas Technology Corp.

Preliminary Specifications Rev. 0.9

Under

Specifications in this manual are tentative and subject to change.

development

M16C/26 Group

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Example Circuit Application for The Standard Serial I/O Mode 2

The below figure shows a circuit application for the standard serial I/O mode 2.

CLK1

RTS1(BUSY)

RXD1

BUSY output

Data input

TXD1

Data output

M16C/26 Group

(Flash memory version)

CNVss

P86(CE)

(1) Control pins and external circuitry will vary according to peripheral unit.

For more information, see the peripheral unit manual.

(2) In this example, the microprocessor mode and standard serial I/O mode

are switched via a switch.

Figure 1.23.17. Example circuit application for the standard serial I/O mode 2

231

Renesas Technology Corp.

RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER

HARDWARE MANUAL

M16C/26 Group Rev.0.90

Editioned by

Committee of editing of RENESAS Semiconductor Hardware Manual

This book, or parts thereof, may not be reproduced in any form without permission

of Renesas Technology Corporation.

M16C/26 Group

Hardware Manual

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan


型号：	M16C26
厂家：	RENESAS TECHNOLOGY CORP
描述：	16-BIT CMOS SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/20 SERIES 16位CMOS单片机M16C族/ M16C / 20系列计算机
文件：	总239页 (文件大小：14084K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M16C26 [RENESAS]

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