M16CM6T-XXXFP [RENESAS]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机
| 型号： | M16CM6T-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 文件： | 总172页 (文件大小：2398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or
56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions
featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of execut-
ing instructions at high speed.
The M30201 group includes a wide range of products with different internal memory types and sizes and
various package types.
Features
• Basic machine instructions ..................Compatible with the M16C/60 series
• Memory capacity..................................ROM/RAM (See figure 1.4. ROM expansion.)
• Shortest instruction execution time ......100ns (f(XIN)=10MHz)
• Supply voltage .....................................4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version
2.7 to 5.5V (f(XIN)=3.5MHz ):mask ROM version
4.0 to 5.5V (f(XIN)=10MHz) :flash memory version
• Interrupts..............................................13 internal and 3 external interrupt sources, 4 software
(including key input interrupt)
• Multifunction 16-bit timer......................Timer A x 1, timer B x 2, timer X x 3
• Clock output
• Serial I/O..............................................1 channel for UART or clock synchronous, 1 for UART
• A-D converter.......................................10 bits X 8 channels (Expandable up to 13 channels)
• Watchdog timer....................................1 line
• Programmable I/O ...............................43 lines
• LED drive ports ....................................8 ports
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Home appliances, Audio, office equipment, Automobiles
------Table of Contents------
Central Processing Unit (CPU) ..................... 12
Reset............................................................. 15
Clock Generating Circuit ............................... 19
Protection ...................................................... 26
Interrupts ....................................................... 27
Watchdog Timer............................................ 45
Timer ............................................................. 47
Serial I/O ....................................................... 74
A-D Converter ............................................... 88
Programmable I/O Ports ............................... 98
Electric Characteristics ............................... 110
Flash Memory version................................. 124
1
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1 to 1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P6
1
2
/AN
1
2
1
52
AVSS
P6
/AN
2
3
4
51
50
49
P6
0
/AN
0
P6
P6
P6
3
/AN
/AN
/AN
3
VREF
4
4
AVCC
/CKOUT/AN54
/CLKS/AN53
/CLK /AN52
/R /AN51
/AN50
CNVSS
/TB1IN/XCIN
5
5
P5
4
5
6
7
48
47
46
P66
/AN6
7
P5
P5
3
P67
/AN
/KI
2
0
P00
0
8
9
45
44
43
P5
1
XD0
P01
/KI
/KI
1
2
P5
0
/TXD0
10
P02
11
12
42
41
P0
P0
P0
3
4
5
/KI
/KI
/KI
3
4
5
P7
P7
1
0
/TB0IN/XCOUT
13
14
15
40
39
38
RESET
P06
/KI
/KI
6
7
X
V
OUT
SS
P07
P1
0
(LED
0
)
16
17
18
37
36
35
X
IN
P1
P1
P1
1
(LED
(LED
(LED
1
2
)
)
)
VCC
P45/TX2INOUT
2
P4
P4
4
/INT
1
/TX1INOUT
/TX0INOUT
3
4
3
4
19
20
21
34
33
32
3
/INT
0
P1
P1
P1
(LED
(LED
(LED
)
)
)
P4
P4 /TA0OUT
/TA0IN/TXD1
2/RXD1
5
6
5
6
1
22
23
24
31
30
29
P1
7(LED
7
)
P4
0
P3
P3
P3
5
P30
4
3
P31
25
26
28
27
P32
Package: 52P4B
Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)
2
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
PIN CONFIGURATION (top view)
P5
1
/R
X
D
0
/AN51
/AN50
CNVSS
/TB1IN/XCIN
P6
7
/AN
7
1
2
3
42
41
40
P5
0
/T
XD0
N.C.
P0
0
/KI
0
1
P7
1
P0
1
/KI
4
5
6
39
38
37
P7
0
/TB0IN/XCOUT
P0
P0
P0
2
/KI
/KI
/KI
2
3
M30201MX-XXXFP
M30201MXT-XXXFP
M30201F6FP
3
RESET
N.C.
4
4
7
8
36
35
34
X
OUT
P0
P0
P0
5
/KI
/KI
/KI
5
6
6
VSS
9
M30201F6TFP
7
7
XIN
10
11
33
32
31
VCC
P10
(LED
0
)
12
13
14
P1
P1
P1
1
(LED
(LED
(LED
1
)
)
)
P45/TX2INOUT
2
3
2
3
30
29
P4
4
3
/INT
1
0
/TX1INOUT
/TX0INOUT
P4
/INT
Package: 56P6S-A
Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view)
3
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.3 is a block diagram of the M30201 group.
8
6
8
2
6
8
5
I/O ports
Port P0
Port P1
Port P3
Port P4
Port P5
Port P6
Port P7
Internal peripheral functions
Timer
System clock generator
A-D converter
(10 bits
X 8 channels
X
IN-XOUT
Expandable up to 13 channels)
X
CIN-XCOUT
Timer TA0 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TX0 (16 bits)
Timer TX1 (16 bits)
Timer TX2 (16 bits)
UART/clock synchronous SI/O
(8 bits
(8 bits
X 1 channel)
UART
1 channel)
X
M16C/60 series16-bit CPU core
Memory
Registers
ROM
(Note 1)
Program counter
Watchdog timer
(15 bits)
R0H
R0H
R1H
R2
R3
A0
A1
FB
R0L
R0L
R1L
PC
RAM
(Note 2)
Vector table
INTB
Stack pointer
ISP
USP
Multiplier
SB
FLG
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.3. Block diagram for the M30201 group
4
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1 is performance outline of M30201 group.
Table 1.1. Performance outline of M30201 group
Item
Performance
Number of basic instructions
91 instructions
100ns (f(XIN)=10MHz
Shortest instruction execution time
Memory
capacity
I/O port
ROM
(See figure 4. ROM expansion.)
(See figure 4. ROM expansion.)
43 lines
RAM
P0 to P7
Multifunction TA0
16 bits x 1
timer
TB0, TB1
16 bits x 2
TX0, TX1, TX2
UART0
16 bits x 3
Serial I/O
A-D converter
(UART or clock synchronous) x 1
UART x 1
UART1
10 bits x 8 channels (Expandable up to 13 channels)
15 bits x 1 (with prescaler)
Watchdog timer
Interrupt
13 internal and 3 external sources, 4 software sources
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or
quartz oscillator)
Clock generating circuit
Supply voltage
4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version
2.7 to 5.5V (f(XIN)=3.5MHz) :mask ROM version
4.0 to 5.5V (f(XIN)=10MHz) :flash memory version
11mW (f(XIN)=3.5MHz , Vcc=3V) :mask ROM version
95mW (f(XIN)=10MHz, Vcc=5V) :flash memory version
5V
Power consumption
I/O
I/O withstand voltage
characteristics Output current
Device configuration
Package
5mA (15mA:LED drive port)
CMOS silicon gate
52-pin plastic mold SDIP
56-pin plastic mold QFP
5
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Mitsubishi plans to release the following products in the M30201 group:
(1) Support for mask ROM version and flash memory version
(2) ROM capacity
(3) Package
52P4B
: Plastic molded SDIP (mask ROM version and flash memory version)
: Plastic molded QFP (mask ROM version and flash memory version)
56P6S-A
Apr. 2001
RAM Size
(Byte)
M30201F6SP/FP
M30201F6TFP
M30201M6-XXXFP
M30201M6T-XXXFP
2K
M30201M4-XXXSP/FP
M30201M4T-XXXFP
1K
512
ROM Size
(Byte)
16K
48K
32K
Figure 1.4. ROM expansion
Type No.
M 3 0 2 0 1 M 4 T – X X X S P
Package type:
SP : Package 52P4B
FP : Package 56P6S-A
ROM No.
Omitted for flash memory version
Shows difference of characteristics
and usage etc:
Nothing : Common
T
: Automobiles
ROM capacity:
4 : 32K bytes
6 : 48K bytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows pin count, etc
(The value itself has no specific meaning)
M30201 Group
M16C Family
Figure 1.5. Type No., memory size, and package
6
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
Signal name
I/O type
Function
Power supply
input
V
CC, VSS
Supply 2.7 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
CNVSS
RESET
CNVSS
Input
Connect it to the VSS pin.
Reset input
Input
A “L” on this input resets the microcomputer.
X
IN
OUT
Clock input
Input
These pins are provided for the main clock generating circuit.
Connect a ceramic resonator or crystal between the XIN and the
X
Clock output
Output
XOUT pins. To use an externally derived clock, input it to the
IN pin and leave the XOUT pin open.
X
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect
it to VCC
AVCC
AVSS
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect
it to VSS
.
Reference
voltage input
V
REF
Input
This pin is a reference voltage input for the A-D converter.
P0
0
to P0
7
7
I/O port P0
Input/output This is an 8-bit CMOS I/O port. It has an input/output port
direction register that allows the user to set each pin for input or
output individually. When set for input, the user can specify in
units of four bits via software whether or not they are tied to a
pull-up resistor.
P10
to P1
I/O port P1
Input/output This is an 8-bit I/O port equivalent to P0.
Input/output This is a 6-bit I/O port equivalent to P0.
P3
0
0
to P3
to P4
5
5
I/O port P3
I/O port P4
This is a 6-bit I/O port equivalent to P0. The P4
with timer A0 input and serial I/O output TxD1. The P4
shared with timer A0 output. The P4 pin is shared with serial
I/O input RxD1. The P4 pin is shared with external interrupt
INT0 and timer X0 input/output TX0INOUT. The P4 pin is
shared with external interrupt INT1 and timer X1 input/output
TX1INOUT. The P4 pin is shared with timer X2 input/output
TX2INOUT
0
pin is shared
P4
Input/output
1
pin is
2
3
4
5
.
This is a 5-bit I/O port equivalent to P0. The P5
P5 pins are shared with serial I/O pins TxD , RxD
and CLKS. The P5 pin is shared with clock output CLKOUT
Also, these pins are shared with analog input pins AN50
through AN54
0
, P5
1, P52, and
P5
0
to P5
4
I/O port P5
Input/output
3
0
0, CLK
0,
4
.
.
This is an 8-bit I/O port equivalent to P0. These pins are shared
with analog input pins AN through AN
P6
0
to P6
7
I/O port P6
I/O port P7
Input/output
Input/output
0
7.
This is a 2-bit I/O port equivalent to P0 . These pins are used
for input/output to and from the oscillator circuit for the clock.
Connect a crystal oscillator between the XCIN and the XCOUT
pins.
P70 to P71
7
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M30201 accommodates certain units in a single chip. These units include ROM and RAM to store
instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also
included are peripheral units such as timers, serial I/O, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.6 is a memory map of the M30201. The address space extends the 1M bytes from address
0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30201M4-XXXSP, there is 32K
bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are
mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address
of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the
section on interrupts for details.
From 0040016 up is RAM. For example, in the M30201M4-XXXSP, there is 1K byte of internal RAM from
0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subrou-
tines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not
occupied is reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
0000016
SFR area
For details, see
Figures 1.7 to 1.8
FFE0016
0040016
Internal RAM area
Special page
vector table
YYYYY16
Address
YYYYY16
RAM size
007FF16
1K bytes
2K bytes
FFFDC16
Undefined instruction
00BFF16
Overflow
BRK instruction
Address match
Single step
Address
XXXXX16
ROM size
32K bytes
Watchdog timer
XXXXX16
FFFFF16
F800016
DBC
Internal ROM area
48K bytes
F400016
Reset
FFFFF16
Figure 1.6. Memory map
8
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
004016
004116
004216
004316
004416
004516
004616
004716
004816
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
004916
004A16
004B16
004C16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
004D16 Key input interrupt control register (KUPIC)
004E16
A-D conversion interrupt control register (ADIC)
004F16
005016
Address match interrupt register 0 (RMAD0)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer X0 interrupt control register (TX0IC)
Timer X1 interrupt control register (TX1IC)
Timer X2 interrupt control register (TX2IC)
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Address match interrupt register 1 (RMAD1)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
Note: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
Figure 1.7. Location of peripheral unit control registers (1)
9
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
038016
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
A-D register 0 (AD0)
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
Timer A0 (TA0)
Timer X0 (TX0)
Timer X1 (TX1)
Timer X2 (TX2)
A-D register 6 (AD6)
A-D register 7 (AD7)
Clock divided counter (CDC)
Timer B0 (TB0)
Timer B1 (TB1)
A-D control register 2 (ADCON2)
Timer A0 mode register (TA0MR)
Timer X0 mode register (TX0MR)
Timer X1 mode register (TX1MR)
Timer X2 mode register (TX2MR)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
Port P0 (P0)
Port P1 (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 (P2) (Reserved)
Port P3 (P3)
Port P2 direction register (PD2) (Reserved)
Port P3 direction register (PD3)
Port P4 (P4)
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
Port P5 (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 (P6)
Port P7 (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Flash memory control register 0 (FCON0) (Note1)
Flash memory control register 1 (FCON1) (Note1)
Flash command register (FCMD) (Note)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Port P1 drive control register (DRR)
Note 1: This register is only exist in flash memory version.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.8. Location of peripheral unit control registers (2)
10
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these have two register banks.
b15
b15
b15
b15
b15
b15
b15
b8 b7
b8 b7
b0
b0
b0
b0
b0
b0
b0
R0(Note)
R1(Note)
R2(Note)
R3(Note)
A0(Note)
A1(Note)
FB(Note)
L
L
H
H
b19
b19
b0
PC
Program counter
Data
registers
b0
b0
Interrupt table
register
INTB
H
L
b15
b15
b15
b15
User stack pointer
USP
ISP
SB
b0
b0
b0
Interrupt stack
pointer
Address
registers
Static base
register
FLG
Frame base
registers
Flag register
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.9. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H),
and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0, R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
12
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
Flag register (FLG)
U
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.10. Flag register (FLG)
13
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.11 shows the example reset circuit. Figure 1.12 shows the reset sequence.
5V
VCC
5V
VCC
4.0V
4.0V
VCC
RESET
VCC
RESET
Power source voltage
detection circuit
0V
5V
0V
5V
RESET
0V
RESET
0V
0.8V
Example when VCC = 5V.
Figure 1.11. Example reset circuit
X
IN
More than 20 cycles are needed
RESET
BCLK 24cycles
BCLK
(Internal clock)
Content of reset vector
FFFFC16
FFFFE16
Address
(Internal address
signal)
Figure 1.12. Reset sequence
14
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(33) Timer B0 mode register
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Processor mode register 0
(039B16)···
(039C16)···
(03A016)···
(03A416)···
(03A516)···
(03A816)···
(03AC16)···
(03AD16)···
(03B016)···
(000416)···
(000516)···
(000616)···
(000716)···
(000916)···
(000A16)···
(000F16)···
(001016)···
(001116)···
(001216)···
(001416)···
(001516)···
(001616)···
(004D16)···
(004E16)···
(005116)···
(005216)···
(005316)···
(005416)···
(005516)···
(005616)···
(005716)···
(005816)···
(005A16)···
(005B16)···
(005D16)···
(005E16)···
(038016)···
(038116)···
(038216)···
(038316)···
(038416)···
(039616)···
(039716)···
(039816)···
(039916)···
0
0
0 0
0
0
0
?
0
0
0
0
0 0
0 0
(34) Timer B1 mode register
0
0
0
0
0
0
0 ?
Processor mode register 1
UART0 transmit/receive mode
(35)
System clock control register 0
0016
1
0
0
1
0
0
0
register
UART0 transmit/receive control
(36)
System clock control register 1
0
0
0 0
0
0
1 0 0 0
0
0
1 0
0 0
register 0
UART0 transmit/receive control
(37)
Address match interrupt
enable register
0
0
0
0
1
0
0
0
0
0
?
register 1
UART1 transmit/receive mode
(38)
0016
Protect register
0
register
UART1 transmit/receive control
(39)
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
?
?
0016
0016
? ?
Watchdog timer control register
register 0
UART1 transmit/receive control
(40)
Address match interrupt
register 0
register 1
UART transmit/receive control
(41)
0 0 0 0
register 2
Flash memory control register 0
(42)
0
0 0
0
(03B416)···
(03B516)···
(03B616)···
(03D416)···
0
0
0
0
0
0 0
(Note )
Flash memory control register 1
(43)
Address match interrupt
register 1
0016
(9)
0
0
(Note)
Flash command register
A-D control register 2
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
0016
0
0016
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 0
A-D control register 0
Key input interrupt control register
(10)
(03D616)··0
(03D716)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
(03EA16)···
(03EB16)···
(03EE16)···
(03EF16)···
(03FC16)···
(03FD16)···
(03FE16)···
0
0 0 0 ?
0016
? ?
?
A-D conversion interrupt
control register
A-D control register 1
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
?
UART0 transmit interrupt control
register
UART0 receive interrupt control
register
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Pull-up control register 0
Pull-up control register 1
?
0016
?
0016
UART1 transmit interrupt control
register
?
0
0 0 0 0 0 0
UART1 receive interrupt control
register
?
0 0 0 0 0 0
Timer A0 interrupt control register
Timer X0 interrupt control register
Timer X1 interrupt control register
Timer X2 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
INT0 interrupt control register
INT1 interrupt control register
Count start flag
?
0
0 0
0
0
0 0
0 0
0
0
? 0
0016
?
?
?
?
?
?
0
0
0
0
0
0
0
0
0
0
0016
0016
0016
0 0
Port P1 drive capacity control
register
0 0
0 0
0
0
0
0
0
0
0
Data registers (R0/R1/R2/R3)
Address registers (A0/A1)
Frame base register (FB)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
000016
000016
000016
0 0
0
Clock prescaler reset flag
0000016
000016
000016
000016
000016
(26)One-shot start flag
(27)Trigger select flag
(28)Up-down flag
0
0
0 0
0016
0
0
(29)Timer A0 mode register
(30)Timer X0 mode register
(31)Timer X1 mode register
0016
0016
0016
0016
Timer X2 mode register
(32)
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: This register is only exist in flash memory version.
Figure 1.13. Device's internal status after a reset is cleared
15
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
Figure 1.14 shows the processor mode register 0 and 1.
Processor mode register 0 (Note)
Symbol
PM0
Address
000416
When reset
XXXX0000
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0
0
R W
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
The device is reset when this bit
is set to “1”. The value of this bit
is “0” when read.
PM03
Software reset bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Processor mode register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
0XXXXXX0
2
0
0
0
R W
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Must always be set to “0”
Reserved bit
Note: Set bit 1 of the protect register (address 000A16) to “1” when writing new values
to this register.
Figure 1.14. Processor mode register 0 and 1.
16
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.2. Main clock and sub-clock generating circuits
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic or crystal oscillator
XIN, XOUT
Sub clock generating circuit
• CPU’s operating clock source
• Timer A/B/X’s count clock
source
Use of clock
Usable oscillator
Crystal oscillator
XCIN, XCOUT
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit,
and the other one using an externally derived clock for input. Figure 1.16 shows some examples of sub-
clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived
clock for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values
recommended by the manufacturer of your oscillator.
Note: Insert a damping resistor if
M30201
(Built-in feedback resistor)
M30201
(Built-in feedback resistor)
required. The resistance will
vary depending on the
oscillator and the oscillation
drive capacity setting. Use the
value recommended by the
maker of the oscillator.
X
IN
XOUT
X
IN
XOUT
Open
(Note)
When the oscillation drive
capacity is set to low, check
that oscillation is stable. Also,
if the oscillator manufacturer's
data sheet specifies that a
feedback resistor be added
external to the chip, insert a
feedback resistor between XIN
and XOUT following the
R
d
Externally derived clock
Vcc
Vss
CIN
C
OUT
instruction.
Figure 1.15. Examples of main clock
Note: Insert a damping resistor if
required. The resistance will
vary depending on the oscillator
and the oscillation drive
M30201
M30201
(Built-in feedback resistor)
(Built-in feedback resistor)
X
CIN
XCOUT
X
CIN
XCOUT
capacity setting. Use the value
recommended by the maker of
the oscillator.
Open
(Note)
R
Cd
When the oscillation drive
capacity is set to low, check that
oscillation is stable. Also,
if the oscillator manufacturer's
data sheet specifies that a
feedback resistor be added
external to the chip, insert a
feedback resistor between
Externally derived clock
CCIN
CCOUT
Vcc
Vss
X
CIN and XCOUT following the
instruction.
Figure 1.16. Examples of sub-clock
17
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.17 shows the block diagram of the clock generating circuit.
X
CIN
X
COUT
fC32
1/32
f
1
CM04
f
AD
fC
f8
Sub clock
CM10 “1”
Write signal
f
32
S Q
R
X
IN
XOUT
b
c
CM07=0
a
d
Divider
RESET
Software reset
f
C
Main clock
CM02
BCLK
CM07=1
CM05
Interrupt request
level judgment output
S Q
R
WAIT instruction
c
b
1/2
1/2
1/2
1/2
1/2
a
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
CM06=0
CM17,CM16=00
Details of divider
Figure 1.17. Clock generating circuit
18
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-
tained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be
selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the
sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation
mode to stop mode, the value before stop mode is retained.
(4) Peripheral function clock (f1, f8, f32, fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.
19
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.18 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
Bit name
Function
R W
b1 b0
Clock output function
select bit
0 0 : I/O port P5
0 1 : f
1 0 : f
4
C
output
output
8
CM01
CM02
CM03
1 1 : Clock divide counter output
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
WAIT peripheral function
clock stop bit
X
CIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port X
C
select bit
0 : I/O port
1 : XCIN-XCOUT generation
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 3,4,5)
)
0 : On
1 : Off
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
bit 0 (Note 7)
1 : Division by 8 mode
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when shifting to stop mode and at a reset.
Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with XIN
after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock
select bit (CM07) to “1” before setting this bit to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to
OUT (“H”) via the feedback resistor.
X
Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock
oscillating before setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting
from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0
0
0
Bit symbol
CM10
Bit name
Function
R W
All clock stop control bit
(Note 4)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Reserved bit
Always set to “0”
Always set to “0”
Always set to “0”
Reserved bit
Reserved bit
Always set to “0”
0 : LOW
1 : HIGH
b7 b6
X
IN-XOUT drive capacity
CM15
select bit (Note 2)
0 0 : No division mode
Main clock division
select bit 1 (Note 3)
CM16
CM17
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting
from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state.
Figure 1.18. Clock control registers 0 and 1
20
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
The clock output function select bit allows you to choose the clock from f8, fc, or a divide-by-n clock that is
output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and
its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output.
Clock source
selection
P54
f
f
8
P54/CKOUT
C
1/2
Clock divided couter (8)
f32
Division n+1 n=0016 to FF16
Reload register (8)
Example:
When f(XIN)=10MHz
Address 038E16
n=0716
n=2616
n=4D16
n=9B16
:
:
:
:
approx. 19.5kHz
approx. 4.0kHz
approx. 2.0kHz
approx. 1.0kHz
Low-order 8 bits
Data bus low-order bits
Figure 1.19. Block diagram of clock output
21
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Stop Mode, Wait Mode
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains
above 2V.
Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as
the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate
provided that the event counter mode is set to an external pulse, and UART0 functions provided an external
clock is selected. Table 1.3 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 1.3. Port status during stop mode
Pin
States
Port
Retains status before stop mode
“H”
CLKOUT
When fC selected
When f8, clock devided Retains status before stop mode
counter output selected
Wait Mode
When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function
clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral
functions, allowing power dissipation to be reduced. However, peripheral function clock fC32 does not stop
so that the peripherals using fC32 do not contribute to the power saving. When the MCU running in low-
speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table 1.4 shows the
status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the
microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the
WAIT instruction was executed.
Table 1.4. Port status during wait mode
Pin
States
Port
Retains status before wait mode
Does not stop
CLKOUT
When fC selected
When f8, clock devided Does not stop when the WAIT
counter output selected peripheral function clock stop bit is “0”.
When the WAIT peripheralfunction
clock stop bit is “1”,the status immedi-
ately prior to entering wait mode is
maintained.
22
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
StatusTransitionofBCLK
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.5 shows the operating modes corresponding to the settings of system clock control regis-
ters 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address
000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 1.5. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
Operating mode of BCLK
Division by 2 mode
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
Invalid
1
Invalid
1
1
0
0
0
0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Low-speed mode
1
Low power dissipation mode
23
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PowerSaving
Power Saving
There are three power save modes.
(1) Normal operating mode
• High-speed mode
In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral
functions operate on the clocks specified for each respective function.
• Medium-speed mode
In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the
BCLK. The peripheral functions operated on the clocks specified for each respective function.
• Low-speed mode
In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the
subclock. The peripheral functions operate on the clocks specified for each respective function.
• Low power-dissipation mode
This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on
the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the
subclock was selected as the count source continue to run.
(2) Wait mode
CPU operation is halted in this mode. The oscillator continues to run.
(3) Stop mode
All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving
modes, power savings are greatest in this mode.
Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3).
24
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PowerSaving
Transition of stop mode, wait mode
Reset
All oscillators stopped
CPU operation stopped
WAIT
instruction
CM10 = “1”
Interrupt
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
High-speed/medium-
speed mode
CM10 = “1”
Stop mode
Wait mode
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
CM10 = “1”
Interrupt
Low-speed/low power
dissipation mode
Stop mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
Main clock is oscillating
Sub clock is oscillating
CM04 = “0”
Medium-speed mode
(divided-by-2 mode)
High-speed mode
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN
CM07 = “1”
)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM07 = “1”
(Note 2)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM07 = “1” (Note 2)
CM05 = “1”
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
BCLK : f(XCIN
CM07 = “1”
)
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM06 = “0”
(Notes 1,3)
BCLK : f(XIN)/4
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 1.20. Clock transition
25
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716) and port P4 direction register
(address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. There-
fore, important outputs can be allocated to port P4.
If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX000
2
Bit symbol
PRC0
Bit name
Function
0 : Write-inhibited
R W
Enables writing to system clock
control registers 0 and 1 (addresses
1 : Write-enabled
000616 and 000716
)
Enables writing to processor mode
registers 0 and 1 (addresses 000416
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC2
and 000516
)
Enables writing to port P4 direction
register (address 03EA16) (Note
0 : Write-inhibited
1 : Write-enabled
)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.21. Protect register
26
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Overview of Interrupt
Type of Interrupts
Figure 1.22 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
INT instruction
Interrupt
Reset
________
DBC
Watchdog timer
Single step
Special
Address matched
Hardware
Peripheral I/O*1
*1 Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.22. Classification of interrupts
• Maskable interrupt
: An interrupt which can be enabled (disabled) by the interrupt enable flag (I
flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
27
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”.
The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the
INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so
executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt
does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select
the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the
interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So
far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
28
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an “L” is input to the RESET pin.
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag
(D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is
the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O
interrupts are maskable interrupts.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt
This is an interrupts that timer A0 generates.
• Timer B0 and timer B2 interrupt
These are interrupts that timer B generates.
• Timer X0 to timer X2 interrupt
These are interrupts that timer X generates.
________
________
• INT0 and INT1 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for
specifying interrupt vector addresses.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Low address
Mid address
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 1.23. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.6 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table 1.6. Interrupt and fixed vector address
Interrupt source
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Interrupt on UND instruction
Undefined instruction
Overflow
Interrupt on INTO instruction
BRK instruction
If the vector is filled with FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
FFFF416 to FFFF716
Single step (Note)
Watchdog timer
________
DBC (Note)
Do not use
-
-
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
Reset
Note: Interrupts used for debugging purposes only.
30
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the
first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the
INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes.
Set the first address of the interrupt routine in each vector table. Table 1.7 shows the interrupts assigned
to the variable vector tables and addresses of vector tables.
Table 1.7. Interrupt causes (variable interrupt vector addresses)
Vector table address
Software interrupt number
Software interrupt number 0
Interrupt source
BRK instruction
Remarks
Address (L) to address (H)
+0 to +3 (Note)
Cannot be masked by I flag
Software interrupt number 11
Software interrupt number 12
Software interrupt number 13
Software interrupt number 14
+44 to +47 (Note)
+48 to +51 (Note)
+52 to +55 (Note)
+56 to +59 (Note)
Key input interrupt
A-D
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
Software interrupt number 23
Software interrupt number 24
Software interrupt number 25
Software interrupt number 26
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
Software interrupt number 32
+68 to +71 (Note)
+72 to +75 (Note)
+76 to +79 (Note)
+80 to +83 (Note)
+84 to +87 (Note)
+88 to +91 (Note)
+92 to +95 (Note)
+96 to +99 (Note)
+100 to +103 (Note)
+104 to +107 (Note)
+108 to +111 (Note)
+112 to +115 (Note)
+116 to +119 (Note)
+120 to +123 (Note)
+124 to +127 (Note)
+128 to +131 (Note)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer X0
Timer X1
Timer X2
Timer B0
Timer B1
INT0
INT1
to
to
Software interrupt
Cannot be masked by I flag
Software interrupt number 63
+252 to +255 (Note)
Note : Address relative to address in interrupt table register (INTB).
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select
bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indi-
cated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are
located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL
are located in the flag register (FLG).
Figure 1.24 shows the interrupt control registers.
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Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt control register (Note 2)
Symbol
KUPIC
ADIC
SiTIC(i=0, 1)
SiRIC(i=0, 1)
TAiIC(i=0)
TXiIC(i=0 to 2)
TBiIC(i=0, 1)
Address
When reset
004D16
004E16
005116, 005316
005216, 005416
005516
005616 to 005816
005A16, 005B16
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
ILVL0
Bit name
Interrupt priority level
select bit
Function
R
W
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
0 : Interrupt not requested
1 : Interrupt requested
Interrupt request bit
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Symbol
INTiIC(i=0, 1)
Address
005D16, 005E16 XX00X000
When reset
b7 b6 b5 b4 b3 b2 b1 b0
2
0
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
(Note 1)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Always set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed
for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that dose not
generate the interrupt request for that register. For details, see the
precautions for interrupts.
Figure 1.24. Interrupt control register
33
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Enable Flag
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to “0” by software. (Do not set this bit to "1").
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.8 shows the settings of interrupt priority levels and Table 1.9 shows the interrupt levels enabled,
according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.8. Settings of interrupt priority levels
Table 1.9. Interrupt levels enabled according
to the contents of the IPL
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
IPL
Enabled interrupt priority levels
b2 b1 b0
IPL2 IPL1 IPL0
Level 0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
(interrupt disabled)
Level 1
Low
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
High
34
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Changing the Interrupt Control Register
< Program examples >
The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
AND.B
NOP
I
; Disable interrupts.
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
; Four NOP instructions are required when using HOLD function.
NOP
FSET
I
; Enable interrupts.
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B
#00h, 0055h
; Clear TA0IC int. priority level and int. request bit.
; Dummy read.
MOV.W MEM, R0
FSET
I
; Enable interrupts.
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
AND.B
POPC
I
#00h, 0055h
FLG
; Clear TA0IC int. priority level and int. request bit.
; Enable interrupts.
The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and
2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten
due to effects of the instruction queue.
If changing the interrupt control register using an instruction other than the instructions listed hear, and
if an interrupt occurs associated with this register during execution of the instruction, there can be
instances in which the interrupt request bit is not set. To avoid this problem, use one of the instruc-
tions given below to change the register.
Following instructions: AND, OR, BCLR or BSET
35
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 0000016. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U
flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt
numbers 32 through 63, is executed).
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.25. Interrupt response time
36
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.10.
Table 1.10. Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value
16-bit bus, without wait
8-bit bus, without wait
Even
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
000016
Address bus
Data bus
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
R
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.26. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.11 is set in the IPL.
Table 1.11. Relationship between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
Watchdog timer
7
0
Reset
Other
Not changed
37
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 low-
order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the
program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Stack area
Stack area
Address
MSB
Address
MSB
LSB
LSB
[SP]
New stack
pointer value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
Program counter (PC
Program counter (PC
L
)
M
)
Flag register (FLG )
L
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
Stack pointer
value before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 1.27. State of stack before and after acceptance of interrupt request
38
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the
content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.28 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer
indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Sequence in which order
registers are saved
Address
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
Program counter (PC )
L
(2) Saved simultaneously,
all 16 bits
Program counter (PC
Flag register (FLG
M
)
L
)
(1) Saved simultaneously,
all 16 bits
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
Program counter (PC )
L
(3)
(4)
Program counter (PC
Flag register (FLG
M
)
Saved simultaneously,
all 8 bits
L
)
(1)
(2)
Program
counter (PC )
Flag register
(FLG
H
H
)
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.28. Operation of saving registers
39
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program that
was being executed before the acceptance of the interrupt request, so that the suspended process re-
sumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar in-
struction before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.29 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Interrupt Priority Level Judge Circuit
This circuit selects the interrupt with the highest priority level when two or more interrupts are generated
simultaneously.
Figure 1.30 shows the interrupt resolution circuit.
40
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Reset > _D__B___C__ > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.29. Hardware interrupts priorities
Priority level of each interrupt
Level 0 (initial value)
INT1
Timer B0
High
Timer X2
Timer X0
INT0
Timer B1
Timer X1
UART1 reception
UART0 reception
A-D conversion
Timer A0
Priority of peripheral I/O
interrupts
(if priority levels are same)
UART1 transmission
UART0 transmission
Key input interrupt
Low
Processor interrupt priority level
(IPL)
Interrupt request level judgment output
Interrupt
request
accepted
Interrupt enable flag (I flag)
Address match
Watchdog timer
DBC
Reset
Figure 1.30. Interrupt resolution circuit
41
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
KeyInput Interrupt
Key Input Interrupt
If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input
interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the
wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L”
level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an
interrupt.
Port P0
bit
4-P07 pull-up select
Pull-up
Key input interrupt control register
(address 004D16
)
transistor
Port P0
register
7
direction
Port P0
7
direction register
P0
7
/KI
7
6
Port P0
register
6 direction
Pull-up
transistor
Key input interrupt
request
Interrupt control
circuit
P0
6
/KI
Pull-up
transistor
Port P0
register
1
direction
direction
P01/KI1
Port P0
register
0
Pull-up
transistor
P00/KI0
Figure 1.31. Block diagram of key input interrupt
42
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
AddressMatch Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value
of the program counter (PC) that is saved to the stack area varies depending on the instruction being
executed.
Figure 1.32 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
Function
R W
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
b0
Function
Values that can be set
R W
Address setting register for address match interrupt
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read,
turns out to be indeterminate.
Figure 1.32. Address match interrupt-related registers
43
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the
stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset,
generating any interrupts is prohibited.
(3) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
and INT1 regardless of the CPU operation clock.
________
________
• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the
______
interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT inter-
rupt request.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
______
Figure 1.33. Switching condition of INT interrupt request
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
44
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is
a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog
timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the
BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by
16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7
of the watchdog timer control register (address 000F16).
When XIN is selected in BCLK
Prescaler division ratio (16 or 128) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK
When XCIN is selected in BCLK
Prescaler division ratio (2) x watchdog timer count (32768)
Watchdog timer cycle =
BCLK
For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is
approximately 52.4 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). In stop mode and wait mode the watchdog
timer and prescaler are stopped. Counting is resumed from the held value when the modes are released.
Figure 1.34 shows the block diagram of the watchdog timer. Figure 1.35 shows the watchdog timer-related
registers.
Prescaler
“CM07 = 0”
“WDC7 = 0”
1/16
“CM07 = 0”
“WDC7 = 1”
Watchdog timer
interrupt request
1/128
1/2
BCLK
Watchdog timer
“CM07 = 1”
Write to the watchdog timer
start register
Set to
“7FFF16
(address 000E16
)
”
RESET
Figure 1.34. Block diagram of watchdog timer
45
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
0
0
000XXXXX
2
Bit symbol
Bit name
Function
R W
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Must always be set to “0”
Reserved bit
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
R W
this register. The watchdog timer value is always initialized to “7FFF16
regardless of whatever value is written.
”
Figure 1.35. Watchdog timer control and start registers
46
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Timer
There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and
timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers.
Clock prescaler
f
f
1
8
X
IN
1/32
Reset
fC32
X
CIN
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
1/4
f
32
f1 f8 f32 fc32
• Timer mode
• One-shot mode
• PWM mode
Timer A0
Timer A0
Noise
filter
TA0IN
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
Timer X0
Timer X0
Noise
filter
TX0INOUT
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
Timer X1
Timer X1
Noise
filter
TX1INOUT
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
• Pulse width measuring mode
Timer X2
Timer B0
Timer B1
Timer X2
Noise
filter
TX2INOUT
TB0IN
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
TB1IN
Timer B1
• Event counter mode
Figure 1.36. Timer block diagram
47
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.37 shows the block diagram of timer A. Figures 1.38 to 1.40 show the timer A-related registers.
Use the timer A0 mode register bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f
1
Low-order
8 bits
High-order
8 bits
f8
• Timer
(gate function)
f
32
Reload register (16)
f
C32
• Event counter
Clock selection
Counter (16)
Polarity
selection
Up count/down count
TA0IN
Always down count except
in event counter mode
Count start flag
Down count
TB1 overflow
TX0 overflow
External
trigger
Up/down flag
TX2 overflow
Pulse output
TA0OUT
Toggle flip-flop
Figure 1.37. Block diagram of timer A
Timer A0 mode register
Symbol
TA0MR
Address
039616
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TMOD0
Bit name
Function
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.38. Timer A-related registers (1)
48
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A0 register (Note 1)
(b15)
b7
(b8)
b0 b7
Symbol
TA0
Address
038716,038616
When reset
Indeterminate
b0
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts an internal count source
• Event counter mode
000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
(Note 2)
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
(Note 2)
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FF16(Note 2)
(Both high-order
and low-order
addresses)
Note 1: Read and write data in 16-bit units.
Note 2: Use MOV instruction to write to this register.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
000X00002
Bit symbol
TA0S
Bit name
Function
R W
Timer A0 count start flag
Timer X0 count start flag
Timer X1 count start flag
Timer X2 count start flag
0 : Stops counting
1 : Starts counting
TX0S
TX1S
TX2S
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
TB0S
TB1S
CDCS
Timer B0 count start flag
Timer B1 count start flag
Clock devided count start flag
0 : Stops counting
1 : Starts counting
Up/down flag (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
038416
When reset
XXX0XXX02
R W
Bit symbol
TA0UD
Bit name
Function
Timer A0 up/down flag
0 : Down count
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Timer A0 two-phase
pulse signal processing
select bit
TA0P
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note : Use MOV instruction to write to this register.
Figure 1.39. Timer A-related registers (2)
49
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Address
038216
When reset
XXXX0000
2
R W
Bit symbol
Bit name
Function
1 : Timer start
Timer A0 one-shot start flag
Timer X0 one-shot start flag
Timer X1 one-shot start flag
Timer X2 one-shot start flag
TA0OS
TX0OS
TX1OS
TX2OS
When read, the value is “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out
to be indeterminate.
Trigger select register
Symbol
TRGSR
Address
038316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0TGL
Bit name
Function
R W
b1 b0
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX2 overflow is selected
1 1 : TX0 overflow is selected
TA0TGH
TX0TGL
b3 b2
Timer X0 event/trigger
select bit
0 0 : Input on TX0INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TX1 overflow is selected
TX0TGH
TX1TGL
TX1TGH
b5 b4
Timer X1 event/trigger
select bit
0 0 : Input on TX1INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX0 overflow is selected
1 1 : TX2 overflow is selected
b7 b6
Timer X2 event/trigger
select bit
TX2TGL
TX2TGH
0 0 : Input on TX2INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX1 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.40. Timer A-related registers (3)
50
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.12.) Figure 1.41 shows
the timer A0 mode register in timer mode.
Table 1.12. Specifications of timer mode
Item
Count source
Specification
f1, f8, f32, fc32
• Down count
Count operation
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer A0 register
• When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Select function
Counting can be started and stopped by the TA0IN pin’s input signal
• Pulse output function
Each time the timer underflows, the TA0OUT pin’s polarity is reversed
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR
Address
039616
When reset
0016
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 2): Gate function not available
(TA0IN pin is a normal port pin)
1 0 : Timer counts only when TA0IN pin
is held “L” (Note 3)
1 1 : Timer counts only when TA0IN pin
is held “H” (Note 3)
MR3
0 (Must always be “0” in timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.41. Timer A0 mode register in timer mode
51
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a
single-phase and a two-phase external signal. Table 1.13 lists timer specifications when counting a
single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode.
Table 1.14 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the
timer A0 mode register in event counter mode.
Table 1.13. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
External signals input to TA0IN pin (effective edge can be selected by software)
• TB1 overflow, TX0 overflow, TX2 overflow
Count operation
Divide ratio
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer A0 register
• When counting stopped
When a value is written to timer A0 register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TA0OUT pin’s polarity isreversed
Note: This does not apply when the free-run function is selected.
Timer A0 mode register (When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR
Address
039616
When reset
0016
0
0 1
R W
Bit symbol
Bit name
Function
TMOD0
TMOD1
MR0
b1 b0
Operation mode select bit
0 1 : Event counter mode
Pulse output function
select bit
0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
MR1
MR2
Count polarity
select bit (Note 2)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 3)
MR3
0 (Must always be “0” in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK1
Two-phase pulse operation 0 : Normal processing operation
select bit (Note 4)
1 : Multiply-by-4 processing operation
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: This bit is valid when only counting an external signal.
Note 3: Set the corresponding port direction register to “0” (input mode).
Note 4: When performing two-phase pulse signal processing, make sure the two-phase
pulse signal processing operation select bit (address 038416) is set to “1” and
event/trigger select bits (addresses 038316) to “00”.
Figure 1.42. Timer A0 mode register in event counter mode
52
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.14. Timer specifications in event counter mode (when processing two-phase pulse signal)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TA0IN or TA0OUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Divide ratio
• 1/ (FFFF16 - n + 1) for up count
• 1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing Timer overflows or underflows
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
Two-phase pulse input
Two-phase pulse input
Count value can be read out by reading timer A0 register
• When counting stopped
When a value is written to timer A0 register, it is written to both reload regis-
ter and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload regis-
ter. (Transferred to counter at next reload time.)
• Normal processing operation
Select function
The timer counts up rising edges or counts down falling edges on the TA0IN
pin when input signal on the TA0OUT pin is “H”
TA0OUT
TA0IN
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
• Multiply-by-4 processing operation
If the phase relationship is such that the TA0IN pin goes “H” when the input
signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges
on the TA0OUT and TA0IN pins. If the phase relationship is such that the
TA0IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer
counts down rising and falling edges on the TA0OUT and TA0IN pins.
TA0OUT
Count down all edges
Count down all edges
Count up all edges
TA0IN
Count up all edges
Note: This does not apply when the free-run function is selected.
53
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A0 mode register
(When using two-phase pulse signal processing)
Symbol
TA0MR
Address
039616
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 1
Bit name
Operation mode select bit
Function
0 1 : Event counter mode
R W
b1 b0
TMOD0
TMOD1
0 (Must always be “0” when using two-phase pulse signal
processing)
MR0
0 (Must always be “0” when using two-phase pulse signal
processing)
MR1
MR2
1 (Must always be “1” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR3
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse
processing operation
select bit (Note)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note: When performing two-phase pulse signal processing, make sure the two-phase
pulse signal processing operation select bit (address 038416) is set to “1”. Also,
always be sure to set the event/trigger select bit (addresses 038316) to “00”.
Figure 1.43. Timer A0 mode register in event counter mode
54
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.15.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot
timer mode.
Table 1.15. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer A0 register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer A0 register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer A0 register, it is written to only reload register
(Transferred to counter at next reload time)
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR
Address
039616
When reset
0016
0
1 0
Bit symbol
TMOD0
TMOD1
MR0
Bit name
R W
Function
b1 b0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TA0OUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TA0OUT pin is a pulse output pin)
MR1
MR2
0 : Falling edge of TA0IN pin's input signal (Note 3)
1 : Rising edge of TA0IN pin's input signal (Note 3)
External trigger select
bit (Note 2)
0 : One-shot start flag is valid
1 : Selected by event/trigger select
register
Trigger select bit
MR3
0 (Must always be “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: Valid only when the TA0IN pin is selected by the event/trigger select bit
(addresses 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.44. Timer A0 mode register in one-shot timer mode
55
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.16.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer
A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates.
Table 1.16. Timer specifications in pulse width modulation mode
Item
Count source
Specification
f1, f8, f32, fc32
Count operation
•
•
The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width
• Cycle time
n / fi n : Set value
(2 -1) / fi fixed
16
8-bit PWM
• High level width n (m+1) / fi n : values set to timer A0 register’s high-order address
• Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address
• External trigger is input
Count start condition
• The timer overflows
• The count start flag is set (= 1)
Count stop condition
• The count start flag is reset (= 0)
8 bits PWM
• Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
• Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116
Interrupt
request
generation 16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
timing
• Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116
Programmable I/O port or trigger input
Pulse output
When timer A0 register is read, it indicates an indeterminate value
• When counting stopped :When a value is written to timer A0 register, it is
written to both reload register and counter
TA0IN pin function
TA0OUT pin function
Read from timer
Write to timer
• When counting in progress : When a value is written to timer A0 register, it is
written to only reload register (Transferred to counter at next reload time)
Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.
Timer A0 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR
Address
039616
When reset
0016
1 1
1
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
MR0
MR1
1 (Must always be “1” in PWM mode)
External trigger select
bit (Note 1)
0: Falling edge of TA0IN pin's input signal (Note 2)
1: Rising edge of TA0IN pin's input signal (Note 2)
MR2
MR3
0: Count start flag is valid
1: Selected by event/trigger select register
Trigger select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: Valid only when the TA0IN pin is selected by the event/trigger select bit
(addresses 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0” (input mode).
Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output.
Figure 1.45. Timer A0 mode register in pulse width modulation mode
56
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition : Reload register = 000316, when external trigger
(rising edge of TA0IN pin input signal) is selected
1 / fi X
(216 – 1)
Count source
“H”
“L”
TA0IN pin
input signal
Trigger is not generated by this signal
1 / f
i
X n
“H”
“L”
PWM pulse output
from TA0OUT pin
“1”
“0”
Timer A0 interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
1
8
)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFF16
.
Figure 1.46. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TA0IN pin input signal) is selected
1 / fi
X (m + 1) X (28 – 1)
Count source (Note1)
TA0IN pin input signal
“H”
“L”
1 / fi X (m + 1)
“H”
“L”
Underflow signal of
8-bit prescaler (Note2)
1 / fi X (m + 1) X n
“H”
“L”
PWM pulse output
from TA0OUT pin
“1”
“0”
Timer A0 interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
Cleared to “0” when interrupt request is accepted, or cleaerd by software
1
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FF16
.
Figure 1.47. Example of how an 8-bit pulse width modulator operates
57
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.48 shows the block diagram of timer B. Figures 1.49 and 1.50 show the timer B-related registers.
Use the timer Bi mode register (i = 0, 1) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode
: The timer counts an internal count source.
• Event counter mode
: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f1
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f8
f32
fC32
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0, 1)
Counter reset circuit
Can be selected in only
event counter mode
TBj overflow
(j = 1 when i = 0,
j = 0 when i = 1)
Figure 1.48. Block diagram of timer B
Timer Bi mode register
Symbol
TBiMR(i = 0, 1)
Address
039B16, 039C16
When reset
00XX0000
b7 b6 b5 b4 b3 b2 b1 b0
2
R
W
Bit symbol
TMOD0
Function
Bit name
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
1 1 : Inhibited
TMOD1
MR0
MR1
MR2
Function varies with each operation mode
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0.
Note 2: Timer B1.
Figure 1.49. Timer B-related registers (1)
58
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Symbol
TB0
TB1
Address
039116, 039016 Indeterminate
039316, 039216 Indeterminate
When reset
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
b0
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts the timer's period
• Event counter mode
000016 to FFFF16
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note1: Read and write data in 16-bit units.
Count start flag
Symbol
TABSR
Address
038016
When reset
000X0000
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
TA0S
Bit name
Function
R W
Timer A0 count start flag
Timer X0 count start flag
Timer X1 count start flag
Timer X2 count start flag
0 : Stops counting
1 : Starts counting
TX0S
TX1S
TX2S
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out
to be indeterminate.
TB0S
TB1S
CDCS
Timer B0 count start flag
Timer B1 count start flag
Clock devided count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Clock prescaler reset flag
Figure 1.50. Timer B-related registers (2)
59
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.17.) Figure 1.51 shows
the timer Bi mode register in timer mode.
Table 1.17. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBiMR(i=0, 1)
Address
039B16 to 039C16
When reset
00XX0000
2
0 0
Bit symbol
R
W
Bit name
Function
0 0 : Timer mode
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
Invalid in timer mode
Can be “0” or “1”
MR1
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
Invalid in timer mode.
MR3
In an attempt to write to this bit, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1
8
1 1 : fC32
Figure 1.51. Timer Bi mode register in timer mode
60
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.18.) Figure
1.52 shows the timer Bi mode register in event counter mode.
Table 1.18. Timer specifications in event counter mode
Item
Specification
Count source
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i=0, 1)
039B16 to 039C16
00XX0000
2
0
1
R
W
Bit symbol
Bit name
Function
TMOD0
TMOD1
MR0
b1 b0
Operation mode select bit
0 1 : Event counter mode
b3 b2
Count polarity select
bit (Note 1)
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
MR1
1 0 : Counts external signal's
falling and rising edges
1 1 : Inhibited
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
Invalid in event counter mode.
MR3
In an attempt to write to this bit, write “0”. The value, if read in
event counter mode, turns out to be indeterminate.
Invalid in event counter mode.
TCK0
Can be “0” or “1”.
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow
Event clock select
TCK1
( j = 1 when i = 0,
j = 0 when i = 1)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Set the corresponding port direction register to “0” (input mode).
Figure 1.52. Timer Bi mode register in event counter mode
61
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.19.)
Figure 1.53 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.54 shows the operation timing when measuring a pulse period. Figure 1.55 shows the operation timing
when measuring a pulse width.
Table 1.19. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input(Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. The timer Bi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Bi mode register.)
TBiIN pin function
Read from timer
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result)(Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBiMR(i=0 , 1)
Address
039B16 , 039C16
When reset
00XX0000
2
1
0
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Timer Bi overflow
flag ( Note)
0 : Timer did not overflow
1 : Timer has overflowed
MR3
b7 b6
TCK0
TCK1
Count source
select bit
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note : The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the
timer Bi mode register. This flag cannot be set to “1” by software.
Figure 1.53. Timer Bi mode register in pulse period/pulse width measurement mode
62
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Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.54. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.55. Operation timing when measuring a pulse width
63
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer X
Figure 1.56 shows the block diagram of timer X. Figures 1.57 to 1.59 show the timer X-related registers.
Use the timer Xi mode register bits 0 and 1 to choose the desired mode.
Timer X has the five operation modes listed as follows:
• Timer mode
: The timer counts an internal count source.
• Event counter mode
• One-shot timer mode
: The timer counts pulses from an external source or a timer overflow.
: The timer stops counting when the count reaches “000016”.
• Pulse period/pulse width measuring mode
: The timer measures an external signal's pulse period or
pulse width.
• Pulse width modulation (PWM) mode
: The timer outputs pulses of a given width.
Data bus high-order bits
Data bus low-order bits
Clock source
• Timer
selection
• One shot
• PWM
f
f
f
1
Low-order
8 bits
High-order
8 bits
• Pulse period/pulse width measurement
8
32
• Timer
(gate function)
Reload register (16)
f
C32
TXiINOUT
(i=0 to 2)
• Event counter
Clock selection
Counter (16)
Polarity
switching and
edge pulse
Count start flag
Counter reset circuit
TB1 overflow
*1
External
trigger
*1 = TA0, *2 = TX1 when TX0
*1 = TX0, *2 = TX2 when TX1
*1 = TX1, *2 = TA0 when TX2
*2
Pulse output
Toggle flip-flop
Figure 1.56. Block diagram of timer X
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TXiMR(i = 0 to 2) 039716 to 039916
R
W
Bit symbol
Function
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode or pulse period/
pulse width measurement mode
Bit name
b1 b0
TMOD0
Operation mode
select bit
TMOD1
1 1 : Pulse width modulation (PWM) mode
MR0
MR1
Function varies with each operation mode
MR2
MR3
TCK0
Count source select bit
(Function varies with each operation mode)
TCK1
Figure 1.57. Timer X-related registers (1)
64
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Timer Xi register (Note 1)
Symbol
TX0
TX1
Address
When reset
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
038916,038816
038B16,038A16
038D16,038C16
b0
TX2
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts an internal count source
• Event counter mode
000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
(Note 2)
• Pulse period / pulse width measurement mode
Measures a pulse period or width
000016 to FFFE16
(Note 2)
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
0016 to FF16(Note 2)
(High-order
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
addresses)
0016 to FF16 (Note 2)
(Low-order
addresses)
Note 1: Read and write data in 16-bit units.
Note 2: Use MOV instruction to write to this register.
Count start flag
Symbol
TABSR
Address
038016
When reset
000X0000
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
TA0S
Bit name
Function
R W
Timer A0 count start flag
Timer X0 count start flag
Timer X1 count start flag
Timer X2 count start flag
0 : Stops counting
1 : Starts counting
TX0S
TX1S
TX2S
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
TB0S
TB1S
CDCS
Timer B0 count start flag
Timer B1 count start flag
Clock devided count start flag
0 : Stops counting
1 : Starts counting
Figure 1.58. Timer X-related registers (2)
65
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
One-shot start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Address
038216
When reset
XXXX0000
2
R W
Bit symbol
Bit name
Function
1 : Timer start
Timer A0 one-shot start flag
Timer X0 one-shot start flag
Timer X1 one-shot start flag
Timer X2 one-shot start flag
TA0OS
TX0OS
TX1OS
TX2OS
When read, the value is “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out
to be indeterminate.
Trigger select register
Symbol
TRGSR
Address
038316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0TGL
Bit name
Function
R W
b1 b0
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX2 overflow is selected
1 1 : TX0 overflow is selected
TA0TGH
TX0TGL
b3 b2
Timer X0 event/trigger
select bit
0 0 : Input on TX0INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TX1 overflow is selected
TX0TGH
TX1TGL
TX1TGH
b5 b4
Timer X1 event/trigger
select bit
0 0 : Input on TX1INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX0 overflow is selected
1 1 : TX2 overflow is selected
b7 b6
Timer X2 event/trigger
select bit
TX2TGL
TX2TGH
0 0 : Input on TX2INOUT is selected (Note)
0 1 : TB1 overflow is selected
1 0 : TX1 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to “0”(input mode).
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.59. Timer X-related registers (3)
66
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.20.) Figure 1.60 shows
the timer Xi mode register in timer mode.
Table 1.20. Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TXiINOUT pin function
Read from timer
Write to timer
Programmable I/O port, gate input or pulse output
Count value can be read out by reading timer Xi register
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Gate function
Counting can be started and stopped by the TXiINOUT pin’s input signal
• Pulse output function
Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TXiMR(i = 0 to 2) 039716 to 039916
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TXiINOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TXiINOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 2): Gate function not available
(TXiINOUT pin is a normal port pin)
1 0 : Timer counts only when TXiINOUT
pin is held “L” (Note 3)
1 1 : Timer counts only when TXiINOUT
pin is held “H” (Note 3)
MR3
0 (Must always be fixed to “0” in timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). Gate function
cannot be selected when pulse output function is selected.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output
function cannot be selected when gate function is selected.
Figure 1.60. Timer Xi mode register in timer mode
67
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.21.) Figure
1.61 shows the timer Xi mode register in event counter mode.
Table 1.21. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
External signals input to TXiINOUT pin (effective edge can be selected by software)
• TB1 overflow, TA0 overflow, TXi overflow
• Down count
Count operation
• When the timer underflows, it reloads the reload register contents before
continuing counting (Note)
Divide ratio
1/ (n + 1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TXiINOUT pin function
Read from timer
Write to timer
Programmable I/O port, count source input or pulse output
Count value can be read out by reading timer Xi register
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer underflows, the TXiINOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
0
0 1
TXiMR(i = 0 to 2) 039716 to 039916
R W
Bit symbol
Bit name
Function
TMOD0
TMOD1
MR0
b1 b0
Operation mode select bit
0 1 : Event counter mode (Note 1)
Pulse output function
select bit
0 : Pulse is not output
(TXiINOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TXiINOUT pin is a pulse output pin)
MR1
MR2
Count polarity
select bit (Note 3)
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Invalid in event counter mode.
Can be “0” or “1”.
MR3
0 (Must always be “0” in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
Invalid in event counter mode.
Can be “0” or “1”.
TCK1
Note 1: Count source is selected by event/trigger select bit(address 038316) in event counter mode.
Note 2: Set the corresponding port direction register to “1” (output mode). TXiINOUT pin input is not
selected as count source when pulse output function is selected.
Note 3: This bit is valid when only counting an external signal.
Figure 1.61. Timer Xi mode register in event counter mode
68
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.22.) When a trigger occurs, the timer starts up and
continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode.
Table 1.22. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TXiINOUT pin function
Read from timer
Write to timer
Programmable I/O port, trigger input or pulse output
When timer Xi register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Xi register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TXiMR(i = 0 to 2) 039716 to 039916
0
1 0
Bit symbol
Bit name
R W
Function
b1 b0
TMOD0
Operation mode
select bit
1 0 : One-shot timer mode or pulse period /
pulse width measurement mode
TMOD1
MR0
0 : Pulse is not output
(TXiINOOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
Pulse output function
select bit
(TXiINOOUT pin is a pulse output pin)
External trigger select
bit (Note 2)
MR1
MR2
0 : Falling edge of TXiINOOUT pin's input signal (Note 3)
1 : Rising edge of TXiINOOUT pin's input signal (Note 3)
Trigger select bit
0 : One-shot start flag is valid
1 : Selected by event/trigger select register (Note 4)
MR3
0 (Must always be “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected
as count start condition when pulse output function is selected.
Note 2: Valid only when the TXiINOUT pin is selected by the event/trigger select bit (addresses 038316). If
timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0” (input mode).
Note 4: Pulse output function cannot be selected when TXiINOUT pin is selected by the event/trigger select bit
(addresses 038316).
Figure 1.62. Timer Xi mode register in one-shot timer mode
69
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(4) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.23.)
Figure 1.63 shows the timer Xi mode register in pulse period/pulse width measurement mode. Figure
1.64 shows the operation timing when measuring a pulse period. Figure 1.65 shows the operation timing
when measuring a pulse width.
Table 1.23. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fc32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Xi overflow flag
changes to “1”. The timer Xi overflow flag changes to “0” when the count
start flag is “1” and a value is written to the timer Xi mode register.)
TXiINOUT pin function
Read from timer
Measurement pulse input
When timer Xi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
00
1
0
1
TXiMR(i = 0 to 2) 039716 to 039916
2
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : One-shot timer mode or pulse period /
pulse width measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Inhibited
Timer Xi overflow
flag (Note)
0 : Timer did not overflow
1 : Timer has overflowed
MR
2
MR3
1 (Must always be “1” in pulse period / pulse width measurement mode)
b7 b6
TCK0
TCK1
Count source
select bit
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note: The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to
the timer Xi mode register. This flag cannot be set to “1” by software.
Figure 1.63. Timer Xi mode register in pulse period/pulse width measurement mode
70
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Xi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Xi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.64. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Xi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Xi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.65. Operation timing when measuring a pulse width
71
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
(5) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.24.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer
Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates.
Table 1.24. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• Down counts (operating as an 8-bit or a 16-bit pulse width modulator)
•
• The timer is not affected by a trigger that occurs when counting
• "H" level width n / fi
n : Set value
16-bit PWM
16
• Cycle time
(2 -1) / fi fixed
•
•
"H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address
Cycle time (2 -1) (m+1) / fi m : values set to timer Xi register’s low-order address
8-bit PWM
8
• The timer overflows
Count start condition
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
Count stop condition
• Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”
• Set value of "H" level width is FF16, 0016 : Timing that count value goes to 0116
• Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”
• Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 000116
Pulse output
Interrupt
request
generation
timing
8 bits PWM
16 bits PWM
TXiINOUT pin function
Read from timer
Write to timer
When timer Xi register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Xi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Xi register, it is written to only reload register
(Transferred to counter at next reload time)
Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.
Timer Xi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TXiMR(i = 0 to 2) 039716 to 039916
1 1
1
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
MR0
MR1
MR2
1 (Must always be “1” in PWM mode)
Invalid in PWM mode. Can be “0” or “1”.
0: Count start flag is valid
Trigger select bit
(Note 1)
1: Selected by event/trigger select register
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
MR3
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f1
0 1 : f8
1 0 : f32
1 1 : fC32
Note 1: TXiINOUT pin inout cannot be selected by the event/trigger select bit(addresses 038316).
Note 2: Set the corresponding port direction register to “1” (output mode).
Figure 1.66. Timer Xi mode register in pulse width modulation mode
72
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
Condition : Reload register = 000316, when trigger (timer overflow) is selected
1 / fi X (216 – 1)
Count source
“H”
“L”
Trigger signal
Trigger is not generated by this signal
1 / fi X
n
“H”
“L”
PWM pulse output
from TXiINOUT pin
“1”
“0”
Timer Xi interrupt
request bit
fi
: Frequency of count source
(f , f
1
8, f32, fC32)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note1: n = 000016 to FFFF16
.
Figure 1.67. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
Trigger (timer overflow) is selected
1 / f
X (m + 1) X (28 – 1)
i
Count source (Note1)
Trigger signal
“H”
“L”
1 / f X (m + 1)
i
“H”
“L”
Underflow signal of
8-bit prescaler (Note2)
1 / f X (m + 1) X n
i
“H”
“L”
PWM pulse output
from TXiINOUT pin
“1”
“0”
Timer Xi interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
Cleared to “0” when interrupt request is accepted, or cleaerd by software
1
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FF16
.
Figure 1.68. Example of how an 8-bit pulse width modulator operates
73
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as two channels: UART0 and UART1.
UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate indepen-
dently of each other.
Figure 1.69 shows the block diagram of UART0 and UART1. Figure 1.70 shows the block diagram of the
transmit/receive unit.
UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/
O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016 and
03A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART.
UART1 is used as a UART only.
Figures 1.71 through 1.73 show the registers related to UARTi.
(UART0)
RxD0
Clock source selection
TxD0
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock synchronous type
Bit rate generator
1 / (m+1)
f1
f8
Internal
Transmit
clock
UART transmission
f32
fC
1/16
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK0
CLKS
CLK
polarity
reversing
circuit
Clock output pin
select switch
(UART1)
RxD1
TxD1
Receive
clock
Clock source selection
f1
Transmit/
receive
unit
Reception
control circuit
1/16
1/16
Bit rate generator
1 / (n+1)
f8
f32
Transmit
clock
Transmission
control circuit
fC
m : Values set to UART0 bit rate generator (BRG0)
n : Values set to UART1 bit rate generator (BRG1)
Figure 1.69. Block diagram of UARTi (i = 0, 1)
74
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous
type
Clock
synchronous
type
UART (7 bits)
UART (8 bits)
UARTi receive register
UART (7 bits)
PAR
disabled
1SP
2SP
PAR
SP
SP
RxDi
UART
PAR
enabled
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D
8
D
7
D
6
D5
D
4
D
3
D2
D1
D
0
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D7
D6
D
5
D4
D
3
D
2
D1
D
0
D8
UART (8 bits)
UART (9 bits)
Clock
synchronous
type
UART (9 bits)
PAR
enabled
UART
Clock
2SP
1SP
PAR
SP
SP
TxDi
PAR
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
synchronous
type
disabled
Clock
synchronous
type
SP: Stop bit
PAR: Parity bit
“0”
Note: UART1 cannot be used in clock synchronous serial I/O.
Figure 1.70. Block diagram of transmit/receive unit
75
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register (Note)
Symbol
U0TB
U1TB
Address
03A316, 03A216
03AB16, 03AA16
When reset
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
b0
R W
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note : Use MOV instruction to write to this register.
UARTi receive buffer register
(b8)
b0 b7
(b15)
b7
Symbol
U0RB
U1RB
Address
03A716, 03A616
03AF16, 03AE16
When reset
Indeterminate
Indeterminate
b0
Function (During clock
synchronous serial I/O
mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Receive data
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Overrun error flag
(Note)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
OER
FER
PER
SUM
Framing error flag Invalid
(Note)
0 : No framing error
1 : Framing error found
Parity error flag
(Note)
Invalid
Invalid
0 : No parity error
1 : Parity error found
Error sum flag
(Note)
0 : No error
1 : Error found
Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set
to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, and 03AE16) is
read out.
UARTi bit rate generator (Note 1, 2)
Symbol
U0BRG
U1BRG
Address
03A116
03A916
When reset
Indeterminate
Indeterminate
b7
b0
R W
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the
count source by n + 1
Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.
Figure 1.71. Serial I/O-related registers (1)
76
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Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
b2 b1 b0
SMD0
Serial I/O mode select bit
(Note 1)
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit (Note 2)
0 : Internal clock (Note 3)
1 : External clock (Note 4)
0 : Internal clock (Note 3)
1 : External clock (Note 4)
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Sleep select bit
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Must always be “0”
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: UART1 can use only internal clock. Must set this bit to “1”.
Note 3: Set the corresponding port direction register to “1” (output mode).
Note 4: Set the corresponding port direction register to “0” (input mode).
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
03A416, 03AC16
When reset
0816
1
0
Function (Note)
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
R W
Bit name
symbol
CLK0
CLK1
b1 b0
b1 b0
BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : fc is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : fc is selected
Set this bit to “0”.
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
Set this bit to “1”.
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
NCH
Data output select bit
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
UFORM Transfer format select bit
Must always be “0”
Note: UART1 cannot be used in clock synchronous serial I/O.
Figure 1.72. Serial I/O-related registers (2)
77
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
03A516 03AD16
When reset
0216
,
Function (Note 1)
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
(Note 2)
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when
RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then
receive operation starts immediately.
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
XX000000
2
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit
R W
symbol
name
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty
(Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
Set this bit to “0”.
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
U0RRM UART0 continuous
receive mode enable bit
Must always be “0”
Set this bit to “0”.
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Must always be “0”
Must always be “0”
CLKMD1 CLK/CLKS select
bit 1 (Note 2)
0 : Normal mode
(CLK output is CLK0 only)
1 : Transfer clock output
from multiple pins
function selected
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.
Note 1: UART1 cannot be used in clock synchronous serial I/O.
Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART0 internal/external clock select bit (bit 3 at address 03A016) = “0”.
Figure 1.73. Serial I/O-related registers (3)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clocksynchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table
1.25.) Figure 1.65 shows the UART0 transmit/receive mode register.
Table 1.25. Specifications of clock synchronous serial I/O mode
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1)
fi = f1, f8, f32, fc
• When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin
• To start transmission, the following requirements must be met:
Transmission start
condition
_
Transmit enable bit (bit 0 at address 03A516) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_
CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”
_
CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
Reception start
conditio
• To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at address 03A516) = “1”
_
Transmit enable bit (bit 0 at address 03A516) = “1”
_
Transmit buffer empty flag (bit 1 at address 03A516) = “0”
• Furthermore, if external clock is selected, the following requirements must also be met:
_
CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”
_
CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”
Interrupt request
generation timing
• When transmitting
_
Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts re-
quested when data transfer from UART0 transfer buffer register to UART0 transmit
register is completed
_
Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts re-
quested when data transmission from UART0 transfer register is completed
• When receiving
_
Interrupts requested when data transfer from UART0 receive register to U A R T 0
receive buffer register is completed
Error detection
Select function
• Overrun error (Note 2)
This error occurs when the next data is ready before contents of UART0 receive
buffer register are read out
• CLK polarity selection
Whether transmit data is output/input at the rising edge or falling edge of the trans-
fer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection
UART0 transfer clock can be chosen by software to be output from one of the two
pins set
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the
UART0 receive interrupt request bit does not change.
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Clock synchronous serial I/O mode
UART0 transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR
Address
03A016
When reset
0
0 0 1
0016
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock (Note 1)
1 : External clock (Note 2)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be “0” in clock synchronous serial I/O mode)
Note 1: Set the corresponding port direction register to “1” (output mode).
Note 2: Set the corresponding port direction register to “0” (input mode).
Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode
Table 1.26 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that
for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin
outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 1.26. Input/output pin functions in clock synchronous serial I/O mode
Pin name
Function
Method of selection
TxD0
Serial data output
Port P5
0
direction register (bit 0 at address 03EB16)= “1”
(P5
0)
(Outputs dummy data when performing reception only)
RxD0
(P51)
Serial data input
Port P5 direction register (bit 1 at address 03EB16)= “0”
(Can be used as an input port when performing transmission only)
1
CLK0
(P5
Transfer clock output
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016) = “0”
Internal/external clock select bit (bit 3 at address 03A016) = “1”
2
)
Port P52 direction register (bit 2 at address 03EB16) = “0”
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Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
bit (TE)
Data is set in UART0 transmit buffer
register
“0”
“1”
“0”
Transmit buffer
empty flag (Tl)
Transferred from UART0 transmit buffer register to UART0
transmit register
TCLK
Stopped pulsing because transfer enable bit = “0”
CLK0
TxD0
D7
D7
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
D0 D1 D2 D3 D4 D5 D6
Transmit
register empty
flag (TXEPT)
“1”
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CLK polarity select bit = “0”.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRG0 count source (f
n: value set to BRG0
1, f8, f32, fc)
• Transmit interrupt cause select bit = “0”.
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
“1”
“0”
Dummy data is set in UART0 transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UART0 transmit buffer register to UART0 transmit register
1 / fEXT
CLK0
RxD0
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D0
D
1
D
2
D4
D5
D
7
D3
Transferred from UART0 receive register
to UART0 receive buffer register
Read out from UART0 receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
The above timing applies to the following settings:
• External clock is selected.
• CLK polarity select bit = “0”.
• Receive enable bit “1”
• Dummy data write to UART0 transmit buffer register
fEXT: frequency of external clock
Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(a) Polarity select function
As shown in Figure 1.76, the CLK polarity select bit (bit 6 at addresses 03A416) allows selection of the
polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK0
Note 1: The CLK0 pin level when not
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
TXD0
RXD0
transferring data is “H”.
• When CLK polarity select bit = “1”
CLK0
Note 2: The CLK0 pin level when not
transferring data is “L”.
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
TXD0
RXD
0
Figure 1.76. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.77, when the transfer format select bit (bit 7 at addresses 03A416) = “0”, the
transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK0
D0
D
1
D
2
D
3
D
D
4
4
D
5
D
6
D7
TXD0
LSB first
D
1
D
2
D
3
D
5
D
6
D7
D0
RXD0
• When transfer format select bit = “1”
CLK0
D
7
7
D
6
D
5
D
4
D
D
3
3
D
2
D
1
D0
TXD0
MSB first
D
6
D
5
D
4
D
2
D
1
D0
D
RXD0
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.77. Transfer format
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Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.78.) The
multiple pins function is valid only when the internal clock is selected for UART0.
Microcomputer
TXD0 (P50)
CLKS (P5
3
)
)
CLK (P5
0
2
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.78. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is
placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit
simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer
register back again.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. (See Table 1.27.) Figure 1.79 shows the UARTi transmit/receive mode register.
Table 1.27. Specifications of UART Mode
Item
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
Transfer data format
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32, fC
Transfer clock
• When external clock is selected (bit 3 at addresses 03A016=“1”) :
fEXT/16(n+1) (Note 1) (Note 2)
Transmission start
condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”
- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”
- Start bit detection
Reception start condi-
tion
Interrupt request gen-
eration timing
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”:
Interrupts requested when data transfer from UARTi transfer buffer register
to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”:
Interrupts requested when data transmission from UARTi transfer register is
completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 3)
Error detection
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Select function
• Sleep mode selection
This mode is used to transfer data to and from one of multiple slave micro-
computers
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
84
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
UiMR(i=0,1)
03A016, 03A816
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit (Note 1)
0 : Internal clock (Note 2)
1 : External clock (Note 3)
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Note 1: UART1 can use only internal clock. Must set this bit to “1”.
Note 2: Set the corresponding port direction register to “1” (output mode).
Note 3: Set the corresponding port direction register to “0” (input mode).
Figure 1.79. UARTi transmit/receive mode register in UART mode
Table 1.28 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 1.28. Input/output pin functions in UART mode
Pin name
TxDi
(P5 , P4
Function
Method of selection
Port P5
address 03EA16)= “1”
1
and P4
2
direction register (bit 0 at address 03EB16, bit 0 at
Serial data output
0
0)
(Can be used as an input port when performing reception only)
RxDi
(P5 , P42)
Serial data input
Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at
address 03EA16)= “0”
1
(Can be used as an input port when performing transmission only)
CLK0
(P5
Programmable I/O port
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016) = “0”
Internal/external clock select bit (bit 3 at address 03A016) = “1”
2
)
85
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
Start
bit
Parity Stop
bit bit
Stopped pulsing because transmit enable bit = “0”
ST
TxDi
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
“1”
“0”
Transmit register
empty flag
(TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
1, f8, f32, fc)
• One stop bit.
f
EXT : frequency of BRGi count source (external clock)
• Transmit interrupt cause select bit = “1”.
n : value set to BRGi
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UARTi transmit buffer register
“0”
“1”
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
“1”
“0”
Transmit register
empty flag
(TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
1, f8, f32)
• Two stop bits.
f
EXT : frequency of BRGi count source (external clock)
• Transmit interrupt cause select bit = “0”.
n : value set to BRGi
Figure 1.80. Typical transmit timings in UART mode
86
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
Start bit
D1
D7
RxDi
D0
Sampled “L”
Receive data taken in
Transfer clock
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Receive
complete flag
“0”
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
Figure 1.81. Typical receive timing in UART mode
(a) Sleep mode
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
87
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P60 to P67, and P50 to P54 also function as the analog signal input pins. The
direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit
5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference
voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the
resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D
conversion only after setting bit 5 of 03D716 to connect VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.29 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D
converter, and Figures 1.83 and 1.84 show the A-D converter-related registers.
Table 1.29. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 5V
fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
VCC = 3V
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V
• Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
±3LSB
VCC = 3V
• Without sample and hold function (8-bit resolution)
±2LSB
Operating modes
Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 5 pins (AN50 to AN54)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles
• With sample and hold function
8-bit resolution: 28 AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the AD frequency to 250kHz min.
With the sample and hold function, set the AD frequency to 1MHz min.
φ
,
10-bit resolution: 59 AD cycles
φ
φ
,
10-bit resolution: 33 φAD cycles
φ
φ
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
CKS1=1
CKS0=1
CKS0=0
φ
AD
f
AD
1/2
1/2
A-D conversion rate
selection
CKS1=0
V
REF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716
)
)
A-D control register 0 (address 03D616
Addresses
(03C116, 03C016
(03C316, 03C216
(03C516, 03C416
)
)
)
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
V
ref
(03C716, 03C616
(03C916, 03C816
(03CB16, 03CA16
(03CD16, 03CC16
(03CF16, 03CE16
)
Decoder
)
A-D register 4(16)
)
A-D register 5(16)
A-D register 6(16)
Comparator
V
IN
)
)
A-D register 7(16)
Data bus high-order
Data bus low-order
Port P6 group
CH2,CH1,CH0=000
CH2,CH1,CH0=001
P6
P6
P6
0
1
2
/AN
/AN
/AN
0
1
2
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
ADGSEL0=0
P6
3
/AN
3
P6
P6
P6
4
5
6
/AN
/AN
/AN
4
5
6
CH2,CH1,CH0=111
P6
7
/AN
7
Port P5 group
CH2,CH1,CH0=000
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
P5
P5
P5
P5
P5
0
1
2
3
4
/AN50
/AN51
/AN52
/AN53
/AN54
ADGSEL0=1
CH2,CH1,CH0=100
Figure 1.82. Block diagram of A-D converter
89
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
0
R W
Bit symbol
Bit name
Function
b2 b1 b0
CH0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected
Analog input pin select bit
CH1
CH2
MD0
MD1
(Note 2, 3)
b4 b3
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1 (Note 2)
Set this bit to “0”.
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
Bit symbol
Bit name
Function
R W
When single sweep and repeat sweep
mode 0 are selected
b1 b0
A-D sweep pin select bit
SCAN0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
1 1 : AN0 to AN7 (8 pins)
When repeat sweep mode 1 is selected
SCAN1
MD2
b1 b0
0 0 : AN0 (1 pin)
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins)
(Note 2, 3)
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Vref not connected
1 : Vref connected
VCUT
Set this bit to “0”.
0 : Port P6 group is selected
1 : Port P5 group is selected
ADGSEL0 A-D input group select bit
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
If port P5 group is selected, do not select 8 pins sweep mode.
Figure 1.83. A-D converter-related registers (1)
90
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D416
When reset
XXXX0000
2
0
0 0
Bit symbol
SMP
Bit name
Function
R W
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
Reserved bit
Always set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminate.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi(i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
The value, if read, turns out to be indeterminate.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be indeterminate.
Figure 1.84. A-D converter-related registers (2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. (See Table 1.30.) Figure 1.85 shows the A-D control register in one-shot mode.
Table 1.30. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected (Note)
Read A-D register corresponding to selected pin
Reading of result of A-D converter
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
03D616
When reset
00000XXX2
ADCON0
0
0 0
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
Analog input pin select bit
1
is selected
is selected
is selected
is selected
is selected
is selected
is selected
2
3
4
5
6
7
(Note 2, 3)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
Set this bit to “0”.
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
1
0
Bit symbol
Bit name
Function
R W
SCAN0
SCAN1
A-D sweep pin select bit
Invalid in one-shot mode
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
MD2
BITS
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
VCUT
1 : Vref connected
Set this bit to “0”.
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
ADGSEL0
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 1.85. A-D conversion register in one-shot mode
92
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
(See Table 1.31.) Figure 1.86 shows the A-D control register in repeat mode.
Table 1.31. Repeat mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for repeated A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
One of AN0 to AN7, as selected (Note)
Read A-D register corresponding to selected pin (at any time)
Reading of result of A-D converter
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
03D616
When reset
00000XXX2
ADCON0
0
0 1
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
Analog input pin select bit
1
is selected
is selected
is selected
is selected
is selected
is selected
is selected
2
3
4
5
6
7
(Note 2, 3)
(Note 2)
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 1 : Repeat mode
Set this bit to “0”.
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: When changing A-D operation mode, set analog input pin again.
Note 3: AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
1
0
Bit symbol
Bit name
Function
R W
SCAN0
A-D sweep pin select bit
Invalid in repeat mode
SCAN1
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
MD2
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
BITS
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Vref connect bit
1 : Vref connected
VCUT
Set this bit to “0”.
0 : Port P6 group is selected
1 : Port P5 group is selected
ADGSEL0 A-D input group select bit
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 1.86. A-D conversion register in repeat mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. (See Table 1.32.) Figure 1.87 shows the A-D control register in single sweep mode.
Table 1.32. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion
Writing “1” to A-D converter start flag
Start condition
Stop condition
• End of A-D conversion (A-D conversion start flag changes to “0”.)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
03D616
When reset
00000XXX
ADCON0
2
0
1 0
R W
Bit symbol
Bit name
Function
CH0
CH1
CH2
Invalid in single sweep mode
Analog input pin select bit
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 0 : Single sweep mode
Set this bit to “0”.
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
1
0
Bit symbol
Bit name
Function
R W
A-D sweep pin select bit
When single sweep and repeat sweep
mode 0 are selected
b1 b0
SCAN0
SCAN1
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
(Note 2, 3)
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
MD2
BITS
CKS1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
VCUT
Set this bit to “0”.
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
ADGSEL0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
If port P5 group is selected, do not select 8 pins sweep mode.
Figure 1.87. A-D conversion register in single sweep mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. (See Table 1.33.) Figure 1.88 shows the A-D control register in repeat sweep mode 0.
Table 1.33. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D616
When reset
00000XXX
2
0
1 1
R W
Bit symbol
Bit name
Function
CH0
CH1
CH2
Invalid in repeat sweep mode 0
Analog input pin select bit
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
Set this bit to “0”.
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
1
0
Bit symbol
Bit name
Function
R W
A-D sweep pin select bit
When single sweep and repeat sweep
mode 0 are selected
b1 b0
SCAN0
SCAN1
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
(Note 2, 3)
A-D operation mode
select bit 1
Set this bit to “0” in this mode.
MD2
BITS
CKS1
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
1 : Vref connected
VCUT
Set this bit to “0”.
A-D input group select bit
0 : Port P6 group is selected
1 : Port P5 group is selected
ADGSEL0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.
If port P5 group is selected, do not select 8 pins sweep mode.
Figure 1.88. A-D conversion register in repeat sweep mode 0
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A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the
A-D sweep pin select bit. (See Table 1.34.) Figure 1.89 shows the A-D control register in repeat sweep mode 1.
Table 1.34. Repeat sweep mode 1 specifications
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or
pins selected by the A-D sweep pin select bit
Example : AN0 selected AN0
AN1
AN0
AN2
AN0
AN3, etc
Start condition
Stop condition
Writing “1” to A-D conversion start flag
Writing “0” to A-D conversion start flag
Interrupt request generation timing None generated
Input pin
AN0
(1 pin), AN
0
and AN
1
(2 pins), AN
0
to AN
2
(3 pins), AN
0
to AN
3
(4 pins) (Note)
Reading of result of A-D converter
Read A-D register corresponding to selected pin (at any time)
Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.
A-D control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
03D616
When reset
00000XXX
ADCON0
2
0
1 1
R W
Bit symbol
Bit name
Function
CH0
CH1
CH2
Invalid in repeat sweep mode 1
Analog input pin select bit
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 1
Set this bit to “0”.
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
1
1
Bit symbol
Bit name
Function
R W
A-D sweep pin select bit
When single sweep and repeat sweep
mode 1 are selected
b1 b0
SCAN0
SCAN1
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pins)
, AN
1
(2 pins)
to AN
to AN
2
3
(3 pins)
(4 pins)
(Note 2)
A-D operation mode
select bit 1
Set “1” in this mode.
MD2
BITS
CKS1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
Frequency select bit 1
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
Vref connect bit
1 : Vref connected
VCUT
Set this bit to “0”.
0 : Port P6 group is selected
1 : Port P5 group is selected
ADGSEL0 A-D input group select bit
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN50 to AN54 can be used in the same way as for AN0 to AN4.
Figure 1.89. A-D conversion register in repeat sweep mode 1
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A-D Converter
• Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is
achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
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Programmable I/O Port
Programmable I/O Ports
There are 43 programmable I/O ports: P0 to P7. Each port can be set independently for input or output
using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the
drive capacity of its N-channel output transistor to be set as necessary.
Figures 1.90 to 1.92 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs
regardless of the contents of the direction registers. See the descriptions of the respective functions for how
to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.93 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
(2) Port registers
Figure 1.94 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
(3) Pull-up control registers
Figure 1.95 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
(4) Port P1 drive capacity control register
Figure 1.95 shows a structure of the port P1 drive capacity control register.
This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in
this register corresponds one for one to the port pins.
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Programmable I/O Port
Pull-up selection
Direction register
P30 to P35
Data bus
Port latch
Pull-up selection
P00 to P07, P42, P71
Direction register
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection
Direction register
P41, P70
output
Data bus
Port latch
Pull-up selection
Direction register
P40, P43, P44, P45
output
Data bus
Port latch
Input to respective peripheral functions
Figure 1.90. Programmable I/O ports (1)
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Programmable I/O Port
Pull-up selection
Direction register
P10 to P17
Data bus
Port latch
Drive capacity control register
Pull-up selection
Direction register
P5
1
Port latch
Data bus
Analog input
Serial I/O input
Pull-up selection
Direction register
P50, P53, P54
output
Data bus
Port latch
Analog input
Pull-up selection
Direction register
P5
2
output
Data bus
Port latch
Analog input
Serial clock input
Figure 1.91. Programmable I/O ports (2)
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Programmable I/O Port
Pull-up selection
Direction register
P60 to P67
Data bus
Port latch
Analog input
Figure 1.92. Programmable I/O ports (3)
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Programmable I/O Port
Port Pi direction register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
PDi (i = 0 to 7)
03E216, 03E316, 03E716, 03EA16
,
0016
0016
03EB16, 03EE16, 03EF16
Bit symbol
PDi_0
Bit name
direction register
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
1
direction register
direction register
direction register
direction register
direction register
direction register
2
3
(Functions as an output port)
(i = 0 to 7 except 2)
4
Port Pi
Port Pi
Port Pi
5
6
7
PDi_7
direction register
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to the
port P4 direction register.
Note 2: Nothing is assigned in direction register of P3
P7 to P7 . These bits can either be set nor reset. When read, its contents
are indeterminate.
6, P37, P46, P47, P55 to p57,
2
7
Figure 1.93. Direction register
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register
Symbol
Pi (i = 0 to 7)
Address
03E016, 03E116, 03E516, 03E816
When reset
Indeterminate
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
,
03E916, 03EC16, 03ED16
Bit symbol
Bit name
register
register
register
register
register
Function
R W
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Port Pi
0
1
2
3
4
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
Port Pi
Port Pi
Port Pi
Port Pi
1 : “H” level data
(i = 0 to 7 except 2)
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
6
7
register
register
register
Note: Nothing is assigned in direction register of P36, P37, P46, P47, P55 to p57, P72 to
P7 . This bit can either be set nor reset. When read, its content is indeterminate.
7
Figure 1.94. Port register
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Programmable I/O Port
Pull-up control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When reset
0016
Bit symbol
PU00
Bit name
Function
R W
P0
P0
P1
P1
0
to P0
to P0
to P1
to P1
3
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU01
PU02
PU03
4
0
4
7
3
7
1 : Pulled high
PU06
PU07
P3
0
to P3
3
pull-up
pull-up
P3
4
to P3
5
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When reset
0016
R W
Bit symbol
PU10
Bit name
Function
P4
0
4
to P4
3
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU11
PU12
PU13
PU14
PU15
P4
to P4
7
P5
P5
P6
P6
0
4
0
4
to P5
3
1 : Pulled high
pull-up
to P6
to P6
to P7
3
7
pull-up
pull-up
pull-up
PU16
P7
0
1
Port P1 drive capacity control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DRR
Address
03FE16
When reset
0016
Bit symbol
Bit name
Function
R W
DRR0
Port P1
0
drive capacuty
Set P1 N-channel output
transistor drive capacity
0 : LOW
DRR1
Port P1
1
drive capacuty
DRR2
DRR3
Port P1
Port P1
2
3
drive capacuty
drive capacuty
1 : HIGH
DRR4
DRR5
DRR6
DRR7
Port P1
Port P1
Port P1
4
5
6
drive capacuty
drive capacuty
drive capacuty
drive capacuty
Port P1
7
Figure 1.95. Pull-up control register
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Programmable I/O Port
Example connection of unused pins
Table 1.36. Example connection of unused pins
Pin name
Connection
Ports P0, P1, P3 to P7
After setting for input mode, connect every pin to VSS (pull-down); or
after setting for output mode, leave these pins open.
XOUT (Note)
Open
Connect to VCC
Connect to VSS
AVCC
AVSS, VREF
Note: With external clock input to XIN pin.
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Usage precaution
Usage Precaution
Timer A (timer mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16”. Reading
the timer A0 register after setting a value in the timer A0 register with a count halted but before the
counter starts counting gets a proper value.
Timer A (event counter mode)
(1) Reading the timer A0 register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer A0 register with the reload timing gets “FFFF16” by under-
flow or “000016” by overflow. Reading the timer A0 register after setting a value in the timer A0
register with a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer A (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TA0OUT pin outputs “L” level.
• The interrupt request generated and the timer A0 interrupt request bit goes to “1”.
(2) The timer A0 interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0”
after the above listed changes have been made.
Timer A (pulse width modulation mode)
(1) The timer A0 interrupt request bit becomes “1” if setting operation mode of the timer in compliance
with any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer A0 interrupt (interrupt request bit), set timer A0 interrupt request bit to “0”
after the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TA0OUT pin is outputting an “H” level in this instance, the output level goes to “L”,
and the timer A0 interrupt request bit goes to “1”. If the TA0OUT pin is outputting an “L” level in this
instance, the level does not change, and the timer A0 interrupt request bit does not becomes “1”.
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Usage precaution
Timer B (timer mode, event counter mode)
(1) Reading the timer Bi register while a count is in progress allows reading , with arbitrary timing, the
value of the counter. Reading the timer Bi register with the reload timing gets “FFFF16”. Reading the
timer Bi register after setting a value in the timer Bi register with a count halted but before the counter
starts counting gets a proper value.
Timer B (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Bi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Bi interrupt request is not generated.
Timer X (timer mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16”. Reading the
timer A0 register after setting a value in the timer Xi register with a count halted but before the counter
starts counting gets a proper value.
Timer X (event counter mode)
(1) Reading the timer Xi register while a count is in progress allows reading, with arbitrary timing, the
value of the counter. Reading the timer Xi register with the reload timing gets “FFFF16” by underflow
or “000016” by overflow. Reading the timer Xi register after setting a value in the timer Xi register with
a count halted but before the counter starts counting gets a proper value.
(2) When stop counting in free run type, set timer again.
Timer X (one-shot timer mode)
(1) Setting the count start flag to “0” while a count is in progress causes as follows:
• The counter stops counting and a content of reload register is reloaded.
• The TXiINOUT pin outputs “L” level.
• The interrupt request generated and the timer Xi interrupt request bit goes to “1”.
(2) The timer Xi interrupt request bit goes to “1” if the timer's operation mode is set using any of the
following procedures:
• Selecting one-shot timer mode after reset.
• Changing operation mode from timer mode to one-shot timer mode.
• Changing operation mode from event counter mode to one-shot timer mode.
Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after
the above listed changes have been made.
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Usage precaution
Timer X (pulse width modulation mode)
(1) The timer Xi interrupt request bit becomes “1” if setting operation mode of the timer in compliance with
any of the following procedures:
• Selecting PWM mode after reset.
• Changing operation mode from timer mode to PWM mode.
• Changing operation mode from event counter mode to PWM mode.
Therefore, to use timer Xi interrupt (interrupt request bit), set timer Xi interrupt request bit to “0” after
the above listed changes have been made.
(2) Setting the count start flag to “0” while PWM pulses are being output causes the counter to stop
counting. If the TXiINOUT pin is outputting an “H” level in this instance, the output level goes to “L”, and
the timer Xi interrupt request bit goes to “1”. If the TXiINOUT pin is outputting an “L” level in this
instance, the level does not change, and the timer Xi interrupt request bit does not becomes “1”.
Timer X (pulse period/pulse width measurement mode)
(1) If changing the measurement mode select bit is set after a count is started, the timer Xi interrupt
request bit goes to “1”.
(2) When the first effective edge is input after a count is started, an indeterminate value is transferred to
the reload register. At this time, timer Xi interrupt request is not generated.
A-D Converter
(1) Write to each bit (except bit 6) of A-D control register 0, to each bit of A-D control register 1, and to bit
0 of A-D control register 2 when A-D conversion is stopped (before a trigger occurs).
In particular, when the Vref connection bit is changed from “0” to “1”, start A-D conversion after an
elapse of 1 µs or longer.
(2) When changing A-D operation mode, select analog input pin again.
(3) Using one-shot mode or single sweep mode
Read the correspondence A-D register after confirming A-D conversion is finished. (It is known by A-
D conversion interrupt request bit.)
(4) Using repeat mode, repeat sweep mode 0 or repeat sweep mode 1
Use the undivided main clock as the internal CPU clock.
Stop Mode and Wait Mode
____________
(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock
oscillation is stabilized.
(2) When shifting to WAIT mode or STOP mode, the program stops after reading 8 bytes from the WAIT
instruction and the instruction that sets all clock stop bits to “1” in the instruction queue. Therefore,
insert a minimum of 8 NOPs after the WAIT instruction and the instruction that sets all clock stop bits
to “1”.
(3) When the MCU running in low-speed or low power dissipation mode, do not enter WAIT mode with
WAIT peripheral function clock stop bit set to “1”.
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Usage precaution
Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Reading address 0000016 by software sets enabled highest priority interrupt source request bit to
“0”.
Though the interrupt is generated, the interrupt routine may not be executed.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an inter-
rupt before setting a value in the stack pointer may become a factor of runaway. Be sure to set a
value in the stack pointer before accepting an interrupt.
Concerning the first instruction immediately after reset, generating any interrupt is prohibited.
(3) External interrupt
________
________
• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear
the interrupt request bit after changing the polarity.
(4) Changing interrupt control register
See "Changing Interrupt Control Register".
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Electrical characteristics
Electrical characteristics
Table 1.36. Absolute maximum ratings
Symbol
Vcc
AVcc
Parameter
Condition
Rated value
Unit
Supply voltage
Analog supply voltage
- 0.3 to 6.5 (Note 1)
- 0.3 to 6.5 (Note 1)
V
V
VI
RESET, CNVss,P0
0
to P0
7
, P1
0
to P17, P3
0
to P3
5
,
Input voltage
- 0.3 to Vcc + 0.3
(Note 2)
V
P40
0
to P4
5
, P5
0
to P54, P6
0
to P67,
P7
, P7
1
, VREF, XIN
VO
Output voltage
P0
0
to P0
to P54, P6
7
, P1
0
to P17, P3
0
to P3
5
, P4
0
to P45,
- 0.3 to Vcc + 0.3
V
P50
0
to P6 , P7
7
0
, P71, VREF, XIN
P
d
Ta = 25 °C
Power dissipation
1000 (Note 3)
mW
°C
T
opr
- 20 to 85 (Note 4)
Operating ambient temperature
Storage temperature
T
stg
- 40 to 150 (Note 5)
°C
Note 1: Flash memory version: –0.3 to 7 (V) .
Note 2: When writing to flash MCU, CNVss is –0.3 to 13 (V) .
Note 3: Flat package (56P6S-A) is 300 mW.
Note 4: Extended operating temperature version: -40 to 85 °C. When flash memory version is program/erase mode: 25±5 °C.
Note 5: Extended operating temperature version: -65 to 150 °C.
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Electrical characteristics
Table 1.37. Recommended operating conditions (Note 1)
Standard
Unit
Symbol
Vcc
Parameter
Min
2.7
Typ.
5.0
Max.
5.5
Supply voltage
Mask ROM version
V
4.0
5.0
5.5
Flash memory version
Analog supply voltage
Supply voltage
Vcc
0
V
V
AVcc
Vss
Analog supply voltage
AVss
0
V
V
P0
0
to P0
to P54, P6
to P0 , P1
to P54, P6
to P0
to P54, P6
to P0 , P3
to P54, P6
7
, P1
0
to P17, P3
to P6 , P7
to P17, P3
to P67, P70, P71,
to P17, P3 to P3
to P6 , P7
to P3 to P4
to P6 , P7
0
to P3
, P7 , XIN, RESET, CNVSS
to P3
5, P40 to P45,
V
IH
HIGH input voltage
Vcc
0.8Vcc
0
P5
0
0
7
0
1
,
P0
0
0
7
0
0
5
, P4
0
to P4
to P4
5
5
,
,
LOW input voltage
VIL
0.2Vcc
- 10.0
V
P5
0
0
XIN, RESET, CNVSS
P0
7
, P1
0
0
5
, P40
HIGH peak output
current
IOH (peak)
mA
P5
0
0
0
7
, P7
0
1
IOL (peak)
P00
7
0
5
, P4
0
5
,
LOW peak output
current
mA
10.0
P5
0
7
, P7
0
1
HIGHPOWER
LOWPOWER
P1
0
to P1
7
LOW peak output
current
30.0
10.0
IOL (peak)
IOH (avg)
mA
mA
P00
to P0
7
, P1
0
to P17, P3
0
to P3
, P7
5, P40 to P45,
HIGH average output
current
- 5.0
P5
0
to P54, P6
0
to P6 , P7
7
0
1
P0
0
to P0
7
, P3
0
to P3
5
, P4
0
to P4
, P7
5,
LOW average output
current
IOL (avg)
5.0
mA
P5
0
to P54, P6
0
to P6
7
, P7
0
1
HIGHPOWER
IOL (avg)
LOW average output
current
15.0
P10 to P17
mA
LOWPOWER
5.0
10
V
cc=4.0V to 5.5V
Main clock input oscillation
frequency
0
0
0
MHz
MHz
Mask ROM version
f (XIN
)
5 x VCC
- 10.000
V
cc=2.7V to 4.0V
cc=4.0V to 5.5V
Flash memory version
V
10
50
MHz
kHz
Subclock oscillation frequency
f (XcIN
)
32.768
Note 1: Unless otherwise noted: VCC = 2.7V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to
85oC). Flash version: VCC = 4.0V to 5.5V, Vss = 0V, Ta = – 20 to 85oC (Extended operating temperature version:– 40 to 85oC.)
Note 2: The average output current is an average value measured over 100ms.
Note 3: Keep output current as follows:
The sum of port P3 and P4 IOL (peak) is under 40 mA. The sum of port P1 IOL (peak) is under 60 mA. The sum of port P1, P3
and P4 IOH (peak) is under 40 mA. The sum of port P0, P5, P6 and P7 IOL (peak) is under 80 mA. The sum of port P0, P5, P6
and P7 IOH (peak) is under 80 mA.
Note 4: Relationship between main clock oscillation frequency and supply voltage.
Main clock input oscillation frequency
(Without wait)
10.0
5 x Vcc - 10.000MHz
3.5
0.0
2.7
4.0
5.5
Power supply voltage [V]
(Main clock : no division)
111
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.38. Electrical characteristics (Note1)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
V
P0
P4
0
0
to P0
to P4
7
,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
,
HIGH output
voltage
VOH
I
I
OH = - 5 mA
3.0
5,P5
to P5
4
7
P70,P71
VOH
P0
P4
0
0
to P0
to P4
7
,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
,
HIGH output
voltage
V
4.7
OH = - 200 µA
5,P5
to P5
4
7
P70,P71
I
I
OH = - 1 mA
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
3.0
3.0
3.0
1.6
HIGH output
voltage
V
OH
OH
X
OUT
V
OH = - 0.5 mA
No load
No load
HIGH output
voltage
V
XCOUT
V
V
V
V
OL
P0
P5
0
0
to P0
to P5
7
,P3
0
0
to P3
5
,P4
,P7
0
to P4
,P7
to P4
,P7
5
LOW output
voltage
I
I
OL = 5 mA
2.0
4,P6
to P6
7
0
1
P0
P5
0
to P0
to P5
7,P3
0
to P3
5
,P4
0
5
VOL
LOW output
voltage
OL = 200 µA
0.45
2.0
0
4,P6
0
to P6
7
,P7
0
1
HIGHPOWER
LOWPOWER
I
I
OL = 15mA
OL = 5 mA
LOW output
voltage
V
OL
P10 to P17
V
V
2.0
LOW output
voltage
HIGHPOWER
LOWPOWER
I
I
OL = 200 µA
OL = 200 µA
0.3
P10 to P17
V
OL
OL
0.45
LOW output
voltage
HIGHPOWER
LOWPOWER
I
I
OH = 1 mA
2.0
X
OUT
OUT
V
V
V
OH = 0.5 mA
2.0
LOW output
voltage
HIGHPOWER
LOWPOWER
No load
No load
0
X
V
OL
0
Hysteresis
V
T+ -VT-
TA0IN,TX0INOUT,TX1INOUT,TX2INOUT
TB0IN,TB1IN INT ,INT ,CLK ,KI to KI
0.8
0.2
0
1
0
0
7
V
V
RxD
0
, RxD
1
VT+ -VT-
Hysteresis
1.8
0.2
RESET
P0
P4
P7
0
0
0
to P0
to P4
7
,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
I
IH
HIGH input
current
5,P5
to P5
4
7
µA
5.0
V
I
= 5V
= 0V
,P71, RESET, CNVss
I
IL
P0
P4
P7
0
to P0
to P4
7
,P1
,P5
0
0
to P1
7
,P3
,P6
0
to P3
5,
LOW input
current
V
I
0
5
to P5
4
0
to P67,
-5.0
µA
0
,P71, RESET, CNVss
R
PULLUP
Pull-up
resistor
P0
P4
0
0
to P0
to P4
7
,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
V
I
= 0V
30.0
2.0
50.0 167.0
kΩ
5,P5
to P5
4
7,
P7
0,P71
RXIN
X
IN
CIN
1.0
6.0
MΩ
Feedback resistor
Feedback resistor
RXCIN
X
MΩ
V
When clock is stopped
f(XIN)=10MHz
RAM retention voltage
Power supply current
VRAM
19.0
90.0
38.0
mA
Square wave, no division
f(XCIN)=32kHz
Square wave
µA
I/O pin
has no
load
f(XCIN)=32kHz
When a WAIT instruction
is executed (Note 2)
Icc
4.0
µA
µA
Ta=25 C when clock is
stopped
1.0
Ta=85 C when clock is
stopped
20.0
o
Note 1: Unless otherwise noted: VCC = 5V, VSS = 0V at Ta = -20 to 85 C, f(XIN) = 10MHz
o
(Extended operating temprature version; -40 to 85 C)
Note 2: With one timer operated using fC32.
112
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
Table 1.39. A-D conversion characteristics (Note)
Standard
Min. Typ. Max.
Symbol
Parameter
Unit
Measuring condition
Resolution
Absolute
accuracy
Bits
LSB
LSB
–
–
V
REF =VCC
10
±3
±3
V
REF =VCC = 5V
Sample & hold function not available
Sample & hold function available(10bit)
V
REF =VCC= 5V
REF = VCC = 5V
LSB
V
±2
Sample & hold function available(8bit)
V
REF =VCC
40
10
Ladder resistance
R
LADDER
CONV
CONV
kohm
Conversion time(10bit)
µs
µs
µs
V
t
3.3
2.8
0.3
Conversion time(8bit)
Sampling time
t
t
SAMP
Reference voltage
V
REF
2
0
V
CC
Analog input voltage
VIA
V
V
REF
o
Note : Unless otherwise noted: VCC =AVCC = VREF =5V, VSS =AVSS = 0V at Ta = -25 C, f(XIN) = 10MHz
113
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
o
(*)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85 C unless otherwise
specified)
* Extended operating temprature version; -40 to 85oC
Table 1.40. External clock input
Standard
Unit
Symbol
Parameter
Min.
Max.
External clock input cycle time
ns
ns
ns
ns
ns
t
c
100
40
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(H
)
t
w(L)
40
tr
15
15
t
f
External clock fall time
Table 1.41. Timer A input (counter input in event counter mode)
Standard
Unit
ns
Symbol
Parameter
Min.
Max.
t
c(TA)
TA0IN input cycle time
100
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
t
w(TAH)
ns
ns
40
40
t
w(TAL)
Table 1.42. Timer A input (gating input in timer mode)
Standard
Min.
Unit
Symbol
Parameter
Max.
t
t
c(TA)
ns
ns
ns
TA0IN input cycle time
400
200
200
w(TAH)
TA0IN input HIGH pulse width
t
w(TAL)
TA0IN input LOW pulse width
Table 1.43. Timer A input (external trigger input in one-shot timer mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
c(TA)
ns
ns
ns
TA0IN input cycle time
200
100
100
TA0IN input HIGH pulse width
t
w(TAH)
t
w(TAL)
TA0IN input LOW pulse width
Table 1.44. Timer A input (external trigger input in pulse width modulation mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
w(TAH)
ns
ns
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
100
100
t
w(TAL)
Table 1.45. Timer A input (up/down input in event counter mode)
Standard
Unit
ns
Parameter
Symbol
Min.
Max.
t
c(UP)
TA0OUT input cycle time
2000
1000
TA0OUT input HIGH pulse width
t
w(UPH)
ns
ns
ns
ns
t
w(UPL)
su(UP-TIN
h(TIN-UP)
TA0OUT input LOW pulse width
TA0OUT input setup time
TA0OUT input hold time
1000
400
t
)
t
400
114
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
o
(*)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85 C unless otherwise
specified)
* Extended operating temprature version; -40 to 85oC
Table 1.46. Timer B input (counter input in event counter mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
c(TB)
w(TBH)
100
ns
ns
TBiIN input cycle time (counted on one edge)
t
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
40
40
t
w(TBL)
ns
ns
ns
ns
t
t
c(TB)
200
80
w(TBH)
t
w(TBL)
80
TBiIN input LOW pulse width (counted on both edges)
Table 1.47. Timer B input (pulse period measurement mode)
Standard
Min.
Unit
Symbol
Parameter
Max.
Max.
Max.
Max.
TBiIN input cycle time
t
c(TB)
400
200
200
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.48. Timer B input (pulse width measurement mode)
Standard
Unit
Symbol
Parameter
Min.
400
200
200
t
t
c(TB)
TBiIN input cycle time
ns
ns
w(TBH)
TBiIN input HIGH pulse width
t
w(TBL)
ns
TBiIN input LOW pulse width
Table 1.49. Timer X input (counter input in event counter mode)
Standard
Min.
100
Unit
Symbol
Parameter
t
t
c(TX)
ns
ns
ns
TXiINOUT input cycle time
40
40
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
Table 1.50. Timer X input (gate input in timer mode)
Standard
Min.
Unit
Symbol
Parameter
t
t
c(TX)
400
200
ns
ns
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
200
t
w(TXL)
ns
TXiINOUT input LOW pulse width
Table 1.51. Timer X input (external trigger input in one-shot timer mode)
Standard
Unit
Symbol
Parameter
Min.
200
100
Max.
t
t
c(TX)
ns
ns
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
100
t
w(TXL)
ns
115
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
o
(*)
Timing requirements (referenced to VCC = 5V, VSS = 0V at Ta = -20 to 85 C unless otherwise
specified)
* Extended operating temprature version; -40 to 85oC
Table 1.52. Timer X input (pulse period measurement mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
t
c(TX)
400
200
200
ns
ns
ns
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
Table 1.53. Timer X input (pulse width measurement mode)
Standard
Unit
Symbol
Parameter
Min.
400
200
200
Max.
t
t
c(TX)
ns
ns
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
ns
Table 1.54. Serial I/O
Standard
Unit
Symbol
Parameter
Min.
Max.
t
c(CK)
ns
ns
ns
CLK0 input cycle time
CLK0 input HIGH pulse width
CLK0 input LOW pulse width
TxDi output delay time
TxDi hold time
200
t
w(CKH)
100
100
t
w(CKL)
t
d(C-Q)
h(C-Q)
ns
ns
80
t
0
t
su(D-C)
ns
ns
RxDi input setup time
RxDi input hold time
30
t
h(C-D)
90
_______
Table 1.55. External interrupt INTi inputs
Standard
Min.
Unit
Symbol
Parameter
Max.
t
w(INH)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
250
250
tw(INL)
116
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 5V)
VCC = 5V
tc(TA)
tw(TAH)
TA0IN input
t
w(TAL)
tc(UP)
tw(UPH)
TA0OUT input
tw(UPL)
TA0OUT input
(Up/down input)
During event counter mode
TA0IN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TA0IN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(TX)
tw(TXH)
TXiINOUT input
tw(TXL)
tc(CK)
tw(CKH)
CLK0
tw(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
tw(INL)
INTi input
tw(INH)
117
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.56. Electrical characteristics (Note 1)
Standard
Unit
Symbol
Parameter
Measuring condition
Min. Typ. Max.
P0
P4
0
0
to P0
to P4
7
,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
,
HIGH output
voltage
V
OH
I
OH = - 1mA
V
V
2.5
5,P5
to P5
4
7
P70,P71
I
I
OH = - 1 mA
2.5
2.5
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
HIGH output
voltage
V
OH
OH
X
X
OUT
OH = - 50 µA
No load
No load
3.0
1.6
HIGH output
voltage
V
COUT
V
V
P0
P5
0
0
to P0
to P5
7
,P3
0
0
to P3
to P6
5
,P4
,P7
0
to P4
5
V
V
OL
OL
LOW output
voltage
I
OL = 1 mA
0.5
4
,P6
7
0
,P7
1
HIGHPOWER
LOWPOWER
I
I
OL = 3 mA
OL = 1 mA
0.5
0.5
0.5
LOW output
voltage
P1
0
to P1
7
V
V
V
LOW output
voltage
HIGHPOWER
LOWPOWER
I
I
OH = 0.1 mA
VOL
X
OUT
OUT
OH = 50 µA
0.5
LOW output
voltage
HIGHPOWER
LOWPOWER
No load
No load
0
0
V
OL
X
Hysteresis
TA0IN,TX0INOUT,TX1INOUT,TX2INOUT
TB0IN,TB1IN INT ,INT ,CLK ,KI to KI7
V
T+ -VT-
0.2
0.2
0.8
V
0
1
0
0
RxD
0
, RxD
1
V
T+ -VT-
Hysteresis
1.8
4.0
RESET
V
P0
P4
0
0
to P0
to P4
7,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
I
IH
HIGH input
current
µA
5,P5
to P5
4
7,
V
I
= 3V
= 0V
= 0V
P70,P71, RESET, CNVss
I
IL
P0
P4
P7
0
to P0
to P4
7,P1
0
0
to P1
7
,P3
,P6
0
to P3
5,
LOW input
current
VI
0
5,P5
to P5
4
0
to P67,
-4.0
µA
0
,P71, RESET, CNVss
RPULLUP
P0
P4
0
0
to P0
to P4
7,P1
0
0
to P1
7
,P3
,P6
0
0
to P3
to P6
5
,
,
Pull-up
resistor
V
I
66.0 120.0 500.0 kΩ
5,P5
to P5
4
7
P70,P71
R
XIN
XIN
X
X
IN
IN
3.0
MΩ
Feedback resistor
Feedback resistor
R
10.0
MΩ
When clock is stopped
f(XIN)=3.5MHz
2.0
V
RAM retention voltage
VRAM
3.5
7.0
mA
Square wave, no division
f(XCIN)=32kHz
Square wave
µA
40.0
f(XCIN)=32kHz
When a WAIT instruction
is executed
Oscillation capacity HIGH (Note 2)
2.8
0.9
µA
µA
I/O pin
has no
load
Icc
Power supply current
f(XCIN)=32kHz
When a WAIT instruction
is executed
Oscillation capacity LOW (Note 2)
Ta=25 C when
clock is stopped
1.0
20.0
µA
Ta=85 C when clock
is stopped
o
Note 1: Unless otherwise noted: VCC = 3V, VSS = 0V at Ta = -20 to 85 C, f(XIN) = 3.5MHz)
o
(Extended operating temprature version; -40 to 85 C)
Note 2: With one timer operated using fC32.
118
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
Table 1.57. A-D conversion characteristics (Note)
Standard
Min. Typ. Max.
Symbol
Parameter
Unit
Measuring condition
Resolution
Absolute
accuracy
Bits
–
–
V
REF =VCC
10
±2
LSB
Sample & hold function not available
(8bit)
VREF =VCC = 3V,
ØAD = fAD
Ladder resistance
Conversion time(8bit)
Reference voltage
Analog input voltage
40
10
R
LADDER
CONV
REF
IA
VREF =VCC
kohm
µs
14.0
t
V
V
2.7
0
V
CC
V
V
V
REF
o
Note : Unless otherwise noted: VCC =AVCC = VREF =3V, VSS =AVSS = 0V at Ta = 25 C, f(XIN) = 3.5MHz.
119
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
o
(*)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85 C unless otherwise
specified)
* Extended operating temprature version; -40 to 85oC
Table 1.58. External clock input
Standard
Unit
Symbol
Parameter
Min.
Max.
External clock input cycle time
ns
ns
ns
ns
ns
t
c
286
120
120
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(H
)
t
w(L)
tr
18
18
t
f
External clock fall time
Table 1.59. Timer A input (counter input in event counter mode)
Standard
Unit
ns
Symbol
Parameter
Min.
Max.
t
c(TA)
TA0IN input cycle time
300
120
120
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
t
w(TAH)
ns
ns
t
w(TAL)
Table 1.60. Timer A input (gating input in timer mode)
Standard
Unit
Symbol
Parameter
Min.
1200
600
Max.
t
t
c(TA)
ns
ns
ns
TA0IN input cycle time
w(TAH)
TA0IN input HIGH pulse width
t
w(TAL)
600
TA0IN input LOW pulse width
Table 1.61. Timer A input (external trigger input in one-shot timer mode)
Standard
Unit
Symbol
Parameter
Min.
600
Max.
t
c(TA)
ns
ns
ns
TA0IN input cycle time
TA0IN input HIGH pulse width
t
w(TAH)
300
300
t
w(TAL)
TA0IN input LOW pulse width
Table 1.62. Timer A input (external trigger input in pulse width modulation mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
w(TAH)
ns
ns
TA0IN input HIGH pulse width
TA0IN input LOW pulse width
300
300
t
w(TAL)
Table 1.63. Timer A input (up/down input in event counter mode)
Standard
Unit
ns
Parameter
Symbol
Min.
6000
3000
Max.
t
c(UP)
TA0OUT input cycle time
t
w(UPH)
TA0OUT input HIGH pulse width
TA0OUT input LOW pulse width
TA0OUT input setup time
ns
ns
ns
ns
t
w(UPL)
su(UP-TIN
h(TIN-UP)
3000
1200
t
)
1200
t
TA0OUT input hold time
120
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics (Vcc = 3V)
VCC = 3V
o
(*)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85 C unless otherwise
specified)
* Extended operating temprature version; -40 to 85oC
Table 1.64. Timer B input (counter input in event counter mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
c(TB)
w(TBH)
ns
ns
TBiIN input cycle time (counted on one edge)
300
t
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
120
120
600
320
320
t
w(TBL)
ns
ns
ns
ns
t
t
c(TB)
w(TBH)
t
w(TBL)
TBiIN input LOW pulse width (counted on both edges)
Table 1.65. Timer B input (pulse period measurement mode)
Standard
Min.
Unit
Symbol
Parameter
Max.
Max.
Max.
Max.
TBiIN input cycle time
t
c(TB)
ns
ns
ns
1200
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
600
600
t
w(TBL)
Table 1.66. Timer B input (pulse width measurement mode)
Standard
Min.
Unit
Symbol
Parameter
t
t
c(TB)
TBiIN input cycle time
ns
ns
1200
600
w(TBH)
TBiIN input HIGH pulse width
t
w(TBL)
ns
TBiIN input LOW pulse width
600
Table 1.67. Timer X input (counter input in event counter mode)
Standard
Unit
Symbol
Parameter
Min.
300
120
120
t
t
c(TX)
ns
ns
ns
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
Table 1.68. Timer X input (gate input in timer mode)
Standard
Min.
Unit
Symbol
Parameter
t
t
c(TX)
ns
ns
TXiINOUT input cycle time
1200
600
w(TXH)
TXiINOUT input HIGH pulse width
t
w(TXL)
ns
TXiINOUT input LOW pulse width
600
Table 1.69. Timer X input (external trigger input in one-shot timer mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
t
c(TX)
ns
ns
600
300
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
ns
300
121
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Electrical characteristics (Vcc = 3V)
VCC = 3V
o
(*)
Timing requirements (referenced to VCC = 3V, VSS = 0V at Ta = -20 to 85 C unless otherwise
specified)
* Extended operating temprature version; -40 to 85oC
Table 1.70. Timer X input (pulse period measurement mode)
Standard
Unit
Symbol
Parameter
Min.
Max.
t
t
c(TX)
ns
ns
ns
1200
600
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
600
Table 1.71. Timer X input (pulse width measurement mode)
Standard
Unit
Symbol
Parameter
Min.
1200
600
Max.
t
t
c(TX)
ns
ns
TXiINOUT input cycle time
w(TXH)
TXiINOUT input HIGH pulse width
TXiINOUT input LOW pulse width
t
w(TXL)
ns
600
Table 1.72. Serial I/O
Standard
Unit
Symbol
Parameter
Min.
300
150
150
Max.
t
c(CK)
ns
ns
ns
CLK0 input cycle time
CLK0 input HIGH pulse width
CLK0 input LOW pulse width
TxDi output delay time
TxDi hold time
t
w(CKH)
tw(CKL)
t
d(C-Q)
h(C-Q)
ns
ns
160
t
0
t
su(D-C)
ns
ns
RxDi input setup time
RxDi input hold time
50
t
h(C-D)
90
_______
Table 1.73. External interrupt INTi inputs
Standard
Unit
Symbol
Parameter
Min.
Max.
t
w(INH)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
380
380
tw(INL)
122
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Electrical characteristics (Vcc = 3V)
VCC = 3V
tc(TA)
tw(TAH)
TA0IN input
t
w(TAL)
tc(UP)
tw(UPH)
TA0OUT input
tw(UPL)
TA0OUT input
(Up/down input)
During event counter mode
TA0IN input
(When count on falling
edge is selected)
th(TIN–UP)
tsu(UP–TIN)
TA0IN input
(When count on rising
edge is selected)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(TX)
tw(TXH)
TXiINOUT input
tw(TXL)
tc(CK)
tw(CKH)
CLK0
tw(CKL)
t
h(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
tw(INL)
INTi input
tw(INH)
123
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash memory version)
Outline Performance
Table 1.74 shows the outline performance of the M30201 (flash memory version).
Table 1.74. Outline Performance of the M30201 (flash memory version)
Item
Performance
4.0V to 5.5 V (f(XIN)=10MHz)
Power supply voltage
V
PP=12V ± 5% (f(XIN)=10MHz, Ta=25±5°C)
CC=5V ± 10% (f(XIN)=10MHz, Ta=25±5°C)
Program/erase voltage
V
Three modes (parallel I/O, standard serial I/O, CPU
rewrite)
Flash memory operation mode
Erase block
See Figure 1.96
User ROM area
division
Boot ROM area
One division (3.5 Kbytes) (Note)
In units of byte
Program method
Erase method
Collective erase
Program/erase control method
Number of commands
Program/erase control by software command
6 commands
100 times
Program/erase count
Parallel I/O mode is supported.
ROM code protect
Note: The boot ROM area contains a standard serial I/O mode control program which is stored in it
when shipped from the factory. This area can be erased and programmed in only parallel I/O
mode.
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Description (Flash memory version)
Flash Memory
The M30201 (flash memory version) contains the NOR type of flash memory that requires a high-voltage
VPP power supply for program/erase operations, in addition to the VCC power supply for device operation.
For this flash memory, three flash memory modes are available in which to read, program, and erase:
parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program-
mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit
(CPU). Each mode is detailed in the pages to follow.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and
standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored
in it when shipped from the factory. However, the user can write a rewrite control program in this area that
suits the user’s application system. This boot ROM area can be rewritten in only parallel I/O mode.
CPU rewrite mode
Microcomputer mode
Parallel I/O mode
Standard serial I/O mode
0000016
SFR
SFR
SFR
0040016
RAM
RAM
RAM
YYYYY16
DF00016
DFDFF16
XXXXX16
Collective
erasable/
programmable
area
Boot ROM
area
(3.5K bytes)
Boot ROM
area
(3.5K bytes)
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
User ROM
area
User ROM
area
User ROM
area
FFFFF16
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Type No.
XXXXX16
F400016
YYYYY16
00BFF16
M30201F6
Figure 1.96. Block diagram of flash memory version
125
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CPU Rewrite Mode (Flash memory version)
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control
of the Central Processing Unit (CPU). In CPU rewrite mode, the flash memory can be operated on by
reading or writing to the flash memory control register and flash command register. Figure 1.97, Figure 1.98
show the flash memory control register, and flash command register respectively.
Also, in CPU rewrite mode, the CNVSS pin is used as the VPP power supply pin. Apply the power supply
voltage, VPPH, from an external source to this pin.
In CPU rewrite mode, only the user ROM area shown in Figure 1.96 can be rewritten; the boot ROM area
cannot be rewritten. Make sure the program and block commands are issued for only the user ROM area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to internal RAM before it can be executed.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FCON0
Address
03B416
When reset
00100000
2
0
1
0
0
R
W
Bit name
Function
Bit symbol
FCON00
CPU rewrite mode
select bit
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
This bit can not write. The value, if
read, turns out to be indeterminate.
Reserved bit
CPU rewrite mode
monitor flag
0: CPU rewrite mode is invalid
1: CPU rewrite mode is valid
FCON02
Reserved bit
Reserved bit
Must always be set to "0".
Must always be set to "1".
Nothing is assigned. In an attempt to write this bit, write "0". The value,
if read, turns out to be "0".
Reserved bit
Must always be set to "0".
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FCON1
Address
03B516
When reset
XXXXXX00
2
0
0
R
W
Bit name
Function
Must always be set to "0".
Bit symbol
Reserved bit
Nothing is assigned. In an attempt to write these bits, write "0". The
value, if read, turns out to be indeterminate.
Figure 1.97. Flash memory control register
Flash command register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FCMD
Address
03B616
When reset
0016
R
W
Function
Writing of software command
<Software command name>
•Read command
<Command code>
"0016
"4016
"
"
•Program command
•Program verify command
•Erase command
•Erase verify command
•Reset command
"C016
"2016" +"2016
"A016
"FF16" +"FF
"
"
"
6
"
Figure 1.98. Flash command register
126
Mitsubishi microcomputers
M30201 Group
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CPU Rewrite Mode (Flash memory version)
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O mode becomes unusable.)
See Figure 1.96 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low
(VSS). In this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P52 pin high (VCC), the CNVSS pin high(VPPH), the CPU
starts operating using the control program in the boot ROM area. This mode is called the “boot” mode.
The control program in the boot ROM area can also be used to rewrite the user ROM area.
CPU rewrite mode operation procedure
The internal flash memory can be operated on to program, read, verify, or erase it while being placed on-
board by writing commands from the CPU to the flash memory control register (addresses 03B416,
03B516) and flash command register (address 03B616). Note that when in CPU rewrite mode, the boot
ROM area cannot be accessed for program, read, verify, or erase operations. Before this can be accom-
plished, a CPU write control program must be written into the boot ROM area in parallel input/output
mode. The following shows a CPU rewrite mode operation procedure.
<Start procedure (Note 1)>
(1) Apply VPPH to the CNVSS/VPP pin and VCC to the port P52 pin for reset release. Or the user can
jump from the user ROM area to the boot ROM area using the JMP instruction and execute the CPU
write control program. In this case, set the CPU write mode select bit of the flash memory control
register to “1” before applying VPPH to the CNVSS/VPP pin.
(2) After transferring the CPU write control program from the boot ROM area to the internal RAM, jump
to this control program in RAM. (The operations described below are controlled by this program.)
(3) Set the CPU rewrite mode select bit to “1”.
(4) Read the CPU rewrite mode monitor flag to see that the CPU rewrite mode is enabled.
(5) Execute operation on the flash memory by writing software commands to the flash command regis-
ter.
Note 1: In addition to the above, various other operations need to be performed, such as for entering the
data to be written to flash memory from an external source (e.g., serial I/O), initializing the ports, and
writing to the watchdog timer.
<Clearing procedure>
(1) Apply VSS to the CNVSS/VPP pin.
(2) Set the CPU rewrite mode select bit to “0”.
127
Mitsubishi microcomputers
M30201 Group
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CPU Rewrite Mode (Flash memory version)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During erase/program mode, set BCLK to 5 MHz or less by changing the divide ratio.
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
No interrupts can be used that look up the fixed vector table in the flash memory area. Maskable
interrupts may be used by setting the interrupt vector table in a location outside the flash memory
area.
128
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CPU Rewrite Mode (Flash memory version)
Software Commands
Table 1.75 lists the software commands available with the M30201 (flash memory version).
When CPU rewrite mode is enabled, write software commands to the flash command register to specify
the operation to erase or program.
The content of each software command is explained below.
Table 1.75. List of Software Commands (CPU Rewrite Mode)
First bus cycle
Second bus cycle
Command
Data
(D to D
Data
to D7)
Mode Address
Mode
Address
0
7)
(D0
Read
Write
Write
03B616
03B616
0016
4016
Program
Write
Read
Program
address
Program
data
Program verify
03B616
C016
Write
Verify
address
Verify
data
Erase
2016
A016
03B616
03B616
Write
Write
2016
Write
Read
03B616
Erase verify
Verify
address
Verify
data
Reset
FF16
FF16
Write
Write
03B616
03B616
Read Command (0016)
The read mode is entered by writing the command code “0016” to the flash command register in the
first bus cycle. When an address to be read is input in one of the bus cycles that follow, the content of
the specified address is read out at the data bus (D0–D7), 8 bits at a time.
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” to the flash command register in
the first bus cycle. When the user execute an instruction to write byte data to the desired address (e.g.,
STE instruction) in the second bus cycle, the flash memory control circuit executes the program op-
eration. The program operation requires approximately 20 µs. Wait for 20 µs or more before the user
go to the next processing.
During program operation, the watchdog timer remains idle, with the value “7FFF16” set in it.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure 1.99 for an example of a programming flowchart.
129
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CPU Rewrite Mode (Flash memory version)
Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” to the flash command
register in the first bus cycle. When the user execute an instruction (e.g., LDE instruction) to read byte
data from the address to be verified (the previously programmed address) in the second bus cycle,
the content that has actually been written to the address is read out from the memory.
The CPU compares this read data with the data that it previously wrote to the address using the
program command. If the compared data do not match, the user need to execute the program and
program-verify operations one more time.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” to the
flash command register in the first bus cycle and the same command code to the flash command
register again in the second bus cycle. The erase operation requires approximately 20 ms. Wait for 20
ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands. During erase operation, the
watchdog timer remains idle, with the value “7FFF16 set in it.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure 1.99 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” to the flash command register
in the first bus cycle. When the user execute an instruction to read byte data from the address to be
verified (e.g., LDE instruction) in the second bus cycle, the content of the address is read out.
The CPU must sequentially erase-verify memory contents one address at a time, over the entire area
erased. If any address is encountered whose content is not “FF16” (not erased), the CPU must stop
erase-verify at that point and execute erase and erase-verify operations one more time.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
130
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CPU Rewrite Mode (Flash memory version)
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice to the flash command register, write
command code “FF16” to the flash command register in the first bus cycle and the same command
code to the flash command register again in the second bus cycle. The program command or erase
command is disabled, with the flash memory placed in read mode.
Program
Erase
Start
Start
Address = first location
Loop counter : X=0
All bytes =
"0016"?
YES
NO
Program all bytes =
Write : 4016
Write program command
"0016
"
Address = First address
Loop counter X=0
Write program data/
address
Write : Program data
Duration = 20 µs
Write:2016
Write:2016
Write erase command
Write erase command
Loop counter : X=X+1
Duration = 20ms
Write program verify
command
Write : C016
Loop counter X=X+1
Write erase verify
command/address
Write:A016
Duration = 6 µs
Duration = 6µs
YES
X=25 ?
NO
YES
X=1000 ?
NO
PASS
FAIL
NO
Verify
OK ?
Verify
OK ?
FAIL
NO
Read:
expect value=FF16
Verify
OK?
Verify
OK?
PASS
PASS
FAIL
PASS
FAIL
Last
address ?
Last
address?
Next address ?
Next address
Write:0016
Write read command
PASS
Write read command
FAIL
Write read command
PASS
Write read command
FAIL
Write : 0016
Figure 1.99. Program and erase execution flowchart in the CPU rewrite mode
131
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M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash memory version)
Description of Pin Function (Flash Memory Parallel I/O Mode)
Function
Signal name
Power supply input
CNVSS
I/O
Pin name
CC,VSS
Apply 5 V ± 10 % to the Vcc pin and 0 V to the Vss pin.
V
I
CNVSS
RESET
Apply 12 V ± 5 % to the CNVSS pin.
Connect this pin to VSS
.
I
I
Reset input
Clock input
X
IN
OUT
AVCC, AVSS
REF
Connect a ceramic or crystal resonator between the XIN and XOUT pins.
When entering an externally derived clock, enter it from XIN and leave
O
X
Clock output
XOUT open.
Connect AVSS to Vss and AVcc to Vcc, respectively.
Analog power supply input
Reference voltage input
V
I
Connect this pin to VSS
These are data D –D
.
0
7
input/output pins.
P00 to P07
Data I/O D
0 to D7
I/O
These are address A
8
–A15 input pins.
P1
P3
P3
0
0
4
to P1
to P3
to P3
7
3
5
Address input A
8
to A15
to A7
I
I
These are address A
4
–A input pins.
7
Address input A
4
I
I
I
I
I
I
I
Input port P3
Enter low signals to these pins.
This is a WE input pin.
This is a OE input pin.
P4
0
1
WE input
OE input
P4
This is a CE input pin.
P4
3
CE input
Enter high signals or low signals to these pins.
This is address A17 input pin.
Input port P4
P4
2
, P44, P45
P5
0
1
Address input A17
RFY input
Apply VIH (5 V) to this pin when VPP = VPPH (12 V), or VIL (0 V) when VPP
= VPPL (5 V).
P5
V
I
I
I
I
P5
2
Input port P5
Input port P5
Enter low signal to this pin.
Enter high signals or low signals to these pins.
P5
P6
P6
P7
3
, P54
These are address A0–A3 input pins.
0
4
0
to P6
to P6
to P7
3
7
1
Address input A
0 to A3
Input port P6
Enter high signals or low signals to these pins.
Enter high signals or low signals to these pins.
Input port P7
I
132
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Appendix Parallel I/O Mode (Flash memory version)
Parallel I/O Mode
The parallel I/O mode is entered by making connections shown in Figures 1.101 and 1.102 and then turning
the VPPH power supply on. In this mode, the M30201 (flash memory version) operates in a manner similar
to the NOR flash memory M5M28F101 from Mitsubishi. Note, however, that there are some differences
with regard to the functions not available with the microcomputer (function of read device identification
code) and matters related to memory capacity.
Table 1.76 shows pin relationship between the M30201 and M5M28F101 in parallel I/O mode.
Table 1.76. Pin relationship in parallel I/O mode
M30201(flash memory version)
M5M28F101
V
CC
V
CC
V
CC
SS
A0 to A15, A17
V
SS
V
SS
V
Address input
P6
P1
0
0
to P6
to P1
3
, P3
, P5
0
0
to P33,
7
Data I/O
OE input
CE input
WE input
P0
0
to P0
7
D0 to D7
P4
P4
P4
P5
1
3
0
1
OE
CE
WE
V
RFY input (Note)
Note: The VRFY input only selects read-only or read/write mode, and does not have any pin
associated with it on the M5M28F101.
CPU rewrite mode
Microcomputer mode
Parallel I/O mode
Standard serial I/O mode
0000016
SFR
SFR
SFR
0040016
RAM
RAM
RAM
YYYYY16
DF00016
DFDFF16
XXXXX16
Collective
erasable/
programmable
area
Boot ROM
area
(3.5K bytes)
Boot ROM
area
(3.5K bytes)
Collective
erasable/
programmable
area
Collective
erasable/
programmable
area
User ROM
area
User ROM
area
User ROM
area
FFFFF16
Note 1: In CPU rewrite and standard serial I/O modes, the user ROM is the only erasable/programmable area.
Note 2: In parallel I/O mode, the area to be erased/programmed can be selected by the address A17 input.
The user ROM area is selected when this address input is high and the boot ROM area is selected
when this address input is low.
Type No.
XXXXX16
F400016
YYYYY16
00BFF16
M30201F6
Figure 1.100. Block diagram of flash memory version
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Appendix Parallel I/O Mode (Flash memory version)
AVSS
1
P6
P6
P6
1
/AN
/AN
/AN
1
A1
A3
52
51
50
A0
P60/AN0
2
2
A2
2
3
V
AVCC
REF
3
3
P6
P6
4
5
/AN4
/AN5
49
48
47
4
5
6
P5
4
/CKOUT/AN54
P5
3/CLKS/AN53
P6
6
/AN6
7
P5
2
/CLK
/R
/T
0
/AN52
/AN51
P6
P0
7
/AN
0
46
45
44
7
8
9
V
V
RFY
PPH
/KI0
P5
P5
1
X
D0
D0
D2
D4
0
X
D0
/AN50
CNVSS
/TB1IN/XCIN
P0
P0
1
2
/KI
/KI
1
2
A17
D1
D3
43
42
41
10
11
12
P7
1
P0
P0
3
4
/KI
/KI
3
4
P70
/TB0IN/XCOUT
RESET
P0
5
/KI
5
D5
D7
A9
40
39
38
13
14
15
XOUT
P0
P0
6
/KI6
/KI7
D6
A8
7
Connect oscillator circuit.
CC
VSS
P1
0
(LED
0
)
X
IN
37
36
16
17
18
VCC
P1
P1
P1
1
2
3
(LED
(LED
(LED
1
2
3
)
)
)
V
P45/TX2INOUT
A10
A12
35
34
33
P4
4
/INT
P43
1
/TX1INOUT
0/TX0INOUT
A11
A13
A15
A5
19
20
21
CE
/INT
P1
P1
P1
P1
P3
4
5
6
7
0
(LED
(LED
(LED
(LED
4
5
6
7
)
)
)
)
P4
P4 /TA0OUT
/TA0IN/T
2/RXD1
32
31
30
1
OE
22
23
24
A14
A4
P4
0
X
D
1
5
4
WE
P3
P3
P3
29
28
27
P3
P3
1
2
25
26
A7
3
A6
V
SS
Figure 1.101. Pin connection diagram in parallel I/O mode (1)
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Appendix Parallel I/O Mode (Flash memory version)
1
2
P6
7
/AN
7
P5
P5
1
/R
/T
X
D
0
/AN51
/AN50
CNVSS
/TB1IN/XCIN
V
RFY
42
41
0
XD0
A17
N.C.
V
PPH
3
4
5
40
39
38
P00
/KI
0
D0
D2
D4
P7
1
P0
P0
P0
1
/KI
/KI
/KI
1
2
D1
D3
D5
P70
/TB0IN/XCOUT
2
RESET
6
7
8
37
36
35
3
3
N.C.
P0
P0
P0
4
/KI
/KI
/KI
4
5
M30201F6FP
M30201F6TFP
X
OUT
5
Connect oscillator
circuit.
9
10
V
SS
34
33
32
6
7
6
7
D6
A8
XIN
P0
/KI
D7
A9
VCC
11
12
13
P1
P1
P1
0
(LED
(LED
(LED
0
)
)
)
V
CC
31
30
29
P4
5
/TX2INOUT
1
2
1
2
A10
P4
P4
4
3
/INT
/INT
1
/TX1INOUT
/TX0INOUT
14
P1
3
(LED
3
)
A11
0
CE
Figure 1.102. Pin connection diagram in parallel I/O mode (2)
135
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Appendix Parallel I/O Mode (Flash memory version)
User ROM and Boot ROM Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.100 can be rewritten.
In the boot ROM area, an erase block operation is applied to only one 3.5 K byte block. The boot ROM
area has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi
factory. Therefore, using the device in standard serial input/output mode, the user does not need to write
to the boot ROM area.
Functional Outline (Parallel I/O Mode)
In parallel I/O mode, bus operation modes—Read, Output Disable, Standby, and Write—are selected by
_____ _____ _____
the status of the CE, OE, WE, VRFY, and CNVSS input pins.
The contents of erase, program, and other operations are selected by writing a software command. The
data in memory can only be read out by a read after software command input.
Program and erase operations are controlled using software commands.
Table 1.77. Relationship between control signals and bus operation modes
Pin name
D0 to D7
CE
OE
WE
V
RFY
VPP
Mode
Data output
Read
V
IL
IL
V
IL
V
IH
IH
V
IL
IL
IL
V
V
V
PPH
PPH
PPH
Read
only
Output disabled
Stand by
V
V
IH
V
V
V
Hi-Z
Hi-Z
V
IH
X
X
Read
Data output
Hi-Z
V
IL
IL
V
IL
V
V
IH
IH
V
IH
IH
V
V
V
V
PPH
PPH
PPH
PPH
Read/
Write
Output disabled
Stand by
Write
V
V
IH
V
X
X
Hi-Z
V
IH
V
V
IH
IH
Data input
V
IH
V
IL
VIL
Note: X can be VIL or VIH
.
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Appendix Parallel I/O Mode (Flash memory version)
The following explains about bus operation modes, software commands, and status register.
Bus Operation Modes
Read-only mode is entered by applying VPPH to the CNVSS pin and a low voltage to the VRFY pin.
Read-only mode has three states: Read, Output Disable, and Standby which are selected by
_____ _____
______
setting the CE, OE, and WE pins high or low.
Read-write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin.
Read-write mode has four states: Read, Output Disable, Standby, and Write which are selected by
_____ _____
______
setting the CE, OE, and WE pins high or low.
Read
______
_____
_____
The Read mode is entered by pulling the WE pin high when the CE and OE pins are low. In Read
mode, the data corresponding to each software command entered is output from the data I/O pins
D0–D7.
Output Disable
_____
_____
_____
The Output Disable mode is entered by pulling the CE pin low and the WE and OE pins high. Also,
the data I/O pins are placed in the high-impedance state.
Standby
_____
The Standby mode is entered by driving the CE pin high. Also, the data I/O pins are placed in the
high-impedance state.
Write
The Write mode is entered by applying VPPH to the CNVSS pin and a high voltage to the VRFY pin
_____
_____
_____
and then pulling the WE pin low when the CE pin is low and OE pin is high. In this mode, the device
accepts the software commands or write data entered from the data I/O pins. A program, erase, or
some other operation is initiated depending on the content of the software command entered here.
_____
The input data such as address is latched at the falling edge of WE pin. The input data such as
_____
software command is latched at the rising edge of WE pin.
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Appendix Parallel I/O Mode (Flash memory version)
Software Commands
Table 1.78 lists the software commands available with the M30201 (flash memory version). By entering a
software command from the data I/O pins (D0–D7) in Write mode, specify the content of the operation,
such as erase or program operation, to be performed.
The following explains the content of each software command.
Table 1.78. Software command list (parallel I/O mode)
First bus cycle
Address
Second bus cycle
Command
Data
(D to D
Data
to D7)
Mode Address
Mode
0
7)
(D
0
Read
Write
Write
0016
4016
x
x
Program
Write
Read
Program
address
Program
data
x
x
x
Program verify
C016
Write
Verify
data
Erase
2016
A016
x
x
Write
Write
2016
Write
Read
Erase verify
Verify
address
Verify
data
x
x
Reset
FF16
FF16
Write
Write
Read Command (0016)
The read mode is entered by writing the command code “0016” in the first bus cycle. When an address
to be read is input in one of the bus cycles that follow, the content of the specified address is read out
at the data I/O pins (D0–D7).
The read mode is retained intact until another command is written.
After reset and after the reset command is executed, the read mode is set.
Program Command (4016)
The program mode is entered by writing the command code “4016” in the first bus cycle. When an
address and data to be program is write in the second bus cycle, the flash memory control circuit
executes the program operation. The program operation requires approximately 20 µs. Wait for 20 µs
or more before the user go to the next processing.
Note 1: The write operation is not completed immediately by writing a program command once. The
user must always execute a program-verify command after each program command executed. And if
verification fails, the user need to execute the program command repeatedly until the verification
passes. See Figure 1.103 for an example of a programming flowchart.
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Appendix Parallel I/O Mode (Flash memory version)
Program-verify command (C016)
The program-verify mode is entered by writing the command code “C016” in the first bus cycle and the
verify data is output from the data I/O pins (D0–D7) in the second bus cycle.
Erase command (2016 + 2016)
The flash memory control circuit executes an erase operation by writing command code “2016” in the
first bus cycle and the same command code again in the second bus cycle. The erase operation
requires approximately 20 ms. Wait for 20 ms or more before the user go to the next processing.
Before this erase command can be performed, all memory locations to be erased must have had data
“0016” written to by using the program and program-verify commands.
Note 1: The erase operation is not completed immediately by writing an erase command once. The
user must always execute an erase-verify command after each erase command executed. And if
verification fails, the user need to execute the erase command repeatedly until the verification passes.
See Figure 1.103 for an example of an erase flowchart.
Erase-verify command (A016)
The erase-verify mode is entered by writing the command code “A016” in the first bus cycle and the
verify data is output from the data I/O pins (D0–D7) in the second bus cycle.
Note 1: If any unerased memory location is encountered during erase-verify operation, be sure to
execute erase and erase-verify operations one more time. In this case, however, the user does not
need to write data “0016” to memory before erasing.
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Appendix Parallel I/O Mode (Flash memory version)
Reset command (FF16 + FF16)
The reset command is used to stop the program command or the erase command in the middle of
operation. After writing command code “4016” or “2016” twice, write command code “FF16” in the first
bus cycle and the same command code again in the second bus cycle. The program command or
erase command is disabled, with the flash memory placed in read mode.
Program
Erase
Start
Start
Address = first location
Loop counter : X=0
All bytes =
"0016"?
YES
NO
Program all bytes =
Write : 4016
Write program command
"0016
"
Address = First address
Loop counter X=0
Write program data/
address
Write : Program data
Write:2016
Write:2016
Duration = 20 µs
Write erase command
Write erase command
Loop counter : X=X+1
Duration = 20ms
Write program verify
command
Write : C016
Loop counter X=X+1
Write erase verify
command/address
Write:A016
Duration = 6 µs
Duration = 6µs
YES
X=25 ?
NO
YES
X=1000 ?
NO
PASS
FAIL
NO
Verify
OK ?
Verify
OK ?
FAIL
NO
Read:
expect value=FF16
Verify
OK?
Verify
OK?
PASS
PASS
FAIL
PASS
FAIL
Last
address ?
Last
address?
Next address ?
Next address
Write:0016
Write read command
PASS
Write read command
FAIL
Write read command
PASS
Write read command
FAIL
Write : 0016
Figure 1.103. Program and erase execution flowchart in the CPU rewrite mode
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Appendix Parallel I/O Mode (Flash memory version)
Protect function
In parallel I/O mode, the internal flash memory has the “protect function” available. This function protects
the flash memory contents from being read or rewritten easily.
Depending on the content at the protect control address (FFFFF16) in parallel I/O mode, this function
inhibits the flash memory contents against read or modification. The protect control address (FFFFF16) is
shown in Figure 1.104. (This address exists in the user ROM area.)
The protect function is enabled by setting one of the two protect set bits to “0”, so that the internal flash
memory contents are inhibited against read or modification. The protect function is disabled by setting
both of the two protect reset bits to “00”, so that the internal flash memory contents can be read or
modified. Once the protect function is set, the user cannot change settings of the protect clear bits while
in parallel I/O mode. Settings of the protect reset bits can only be changed in CPU rewrite mode.
Protect control address
Symbol
ROMCP
Address
FFFFF16
When shipping
FF16
b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1
Bit symbol
Bit name
Function
Always set to "1".
Reserved bit
b5 b4
ROMCR
Protect reset bit
Protect set bit
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
ROMCP
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When protect is turned on, the flash memory version is protected against readout or modification
in parallel I/O mode.
Note 2: The protect reset bits can be used to turn off protect . However, since these bits cannot be
changed in parallel I/O mode, they need to be rewritten in CPU rewrite mode.
Figure 1.104. Protect control address
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Pin functions (Flash memory standard serial I/O mode)
Pin
Name
Description
I/O
Apply 5V ± 10 % to Vcc pin and 0 V to Vss pin.
Power input
V
CC,VSS
Mode entry pin. Apply 12V ± 5 % to this pin.
CNVSS
CNVSS
RESET
I
I
Reset input
Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to XIN pin.
X
IN
OUT
AVCC, AVSS
REF
Connect a ceramic resonator or crystal oscillator between XIN and
Clock input
I
XOUT pins. To input an externally generated clock, input it to XIN pin
X
Clock output
and open XOUT pin.
O
Connect AVSS to Vss and AVcc to Vcc, respectively.
Analog power supply input
Reference voltage input
Input port P0
V
Enter the reference voltage for AD from this pin.
Input "H" or "L" level signal or open.
I
P0
P1
P3
P4
0
0
0
0
to P0
to P1
to P3
to P4
7
7
5
5
I
I
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input port P1
Input port P3
I
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
Input port P4
Input port P5
I
I
P5
P5
P5
P5
4
0
1
2
TxD output
RxD input
SCLK input
Serial data output pin.
Serial data input pin.
O
I
Mode entry pin. Supply "H" level when powering on MCU.
When startup is completed this pin serves the serial input clock.
I
This pin sets the type of serial flash programming mode.
P53
BUSY
•An "H" level input (mode 1) sets the mode to clock synchronous.
•An "L" level input (mode 2) sets the mode to clock asynchronous.
This pin changes to "output" after entry into standard serial I/O mode.
I -> O
I
I
P6
0
to P6
7
Input port P6
Input port P7
Input "H" or "L" level signal or open.
Input "H" or "L" level signal or open.
P70 to P71
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Mode setup method
Signal
Value
CNVSS
VPPH
RESET
SCLK
V
SS
VCC
V
CC (Note)
Note: Apply VCC when powering
on MCU.
P6
1
2
/AN
/AN
1
2
V
V
SS
CC
AVSS
52
1
2
P6
0
/AN
0
P6
51
50
49
VREF
P6
P6
P6
3
/AN
/AN
/AN
3
4
3
4
5
AVCC
/CKOUT/AN54
/CLKS/AN53
/CLK /AN52
/R /AN51
/AN50
CNVSS
/TB1IN/XCIN
4
P5
4
5
5
48
47
P5
3
BUSY
P66
/AN6
7
6
7
8
P5
P5
2
0
P67
/AN
/KI
SCLK
46
45
44
RXD
1
XD0
P00
0
P5
0
/TXD0
T
XD
P01
/KI
/KI
1
2
9
P02
CNVSS
43
42
41
10
11
P7
1
P03
P04
P05
/KI
/KI
/KI
3
4
5
P7
0
/TB0IN/XCOUT
RESET
12
13
14
RESET
Connect oscillator circuit.
40
39
38
X
OUT
SS
P06
/KI
/KI
6
7
V
SS
P07
V
15
16
17
XIN
P1
0
(LED
0
)
37
36
35
V
CC
V
CC
P1
P1
P1
1
(LED
(LED
(LED
1
2
)
)
)
P4
5
/TX2INOUT
2
18
19
20
P44
/INT
1
/TX1INOUT
/TX0INOUT
3
4
3
4
34
33
P43
/INT
0
P1
P1
P1
(LED
(LED
(LED
)
)
)
P4
P4 /TA0OUT
/TA0IN/TXD1
2/RXD1
5
6
5
6
32
31
30
21
22
23
1
P4
0
P1
7
(LED
7
)
P3
P3
P3
5
P30
29
28
27
24
25
26
4
3
P31
P32
Figure 1.105. Pin connections for standard serial I/O mode (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mode setup method
Value
Signal
CNVSS
VPPH
RESET
SCLK
V
SS
VCC
V
CC (Note)
Note: Apply VCC when powering
on MCU.
RXD
P6
7
/AN
7
P5
P5
1
/R
/T
X
D
0
/AN51
/AN50
CNVSS
/TB1IN/XCIN
1
2
42
41
T
X
D
0
XD0
N.C.
CNVSS
P00
/KI
0
3
40
39
38
P7
1
4
P0
P0
P0
1
/KI
/KI
/KI
1
2
P70
/TB0IN/XCOUT
2
5
RESET
RESET
3
3
6
37
36
35
N.C.
7
P0
P0
P0
4
/KI
/KI
/KI
4
5
M30201F6FP
M30201F6TFP
5
XOUT
8
6
7
6
7
V
SS
9
34
33
32
V
SS
XIN
10
P0
/KI
V
CC
VCC
P1
P1
P1
0
(LED
(LED
(LED
0
)
)
)
11
12
13
1
2
1
2
P4
5/TX2INOUT
31
30
29
P4
P4
4
3
/INT
/INT
1
0
/TX1INOUT
/TX0INOUT
P13
(LED
3
)
14
Figure 1.106. Pin connections for serial I/O mode (2)
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Mitsubishi microcomputers
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Appendix Standard Serial I/O Mode (Flash Memory Version)
Standard serial I/O mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
leased, which is done when the P52 (SCLK) pin is "H" level, the CNVss pin "VppH" level. (In the ordinary
command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figures 1.105 and 1.106 show the pin connections for the standard serial
I/O mode. Serial data I/O uses UART0 and transfers the data serially in 8-bit units. Standard serial I/O
switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of
P53 (BUSY) pin when the reset is released.
To use standard serial I/O mode 1 (clock synchronized), set the P53 (BUSY) pin to "H" level and release the
reset. The operation uses the four UART0 pins CLK0, RxD0, TxD0 and P53 (BUSY). The CLK0 pin is the
transfer clock input pin through which an external transfer clock is input. The TxD0 pin is for CMOS output.
The P53 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.
To use standard serial I/O mode 2 (clock asynchronized), set the P53 (BUSY) pin to "L" level and release
the reset. The operation uses the two UART0 pins RxD0 and TxD0.
In the standard serial I/O mode, only the user ROM area indicated in Figure 1.96 can be rewritten. The boot
ROM cannot.
In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit are not accepted unless the ID code matches.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Overview of standard serial I/O mode 1 (clock synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using clock-synchronized serial I/O (UART0) and P53
(BUSY). Standard serial I/O mode 1 is engaged by releasing the reset with the P53 (BUSY) pin "H" level.
In reception, software commands, addresses and program data are synchronized with the rise of the
transfer clock that is input to the CLK0 pin, and are then input to the MCU via the RxD0 pin. In transmis-
sion, the read data and status are synchronized with the fall of the transfer clock, and output from the
TxD0 pin.
The TxD0 pin is for CMOS output. Transfer is in 8-bit units with LSB first.
When busy, such as during transmission, reception, erasing or program execution, the P53 (BUSY) pin is
"H" level. Accordingly, always start the next transfer after the P53 (BUSY) pin is "L" level.
Also, data and status registers in memory can be read after inputting software commands. Status, such
as the operating state of the flash memory or whether a program or erase operation ended successfully or
not, can be checked by reading the status register. Here following are explained software commands,
status registers, etc.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.79 lists software commands. In the standard serial I/O mode 1, erase operations, programs and
reading are controlled by transferring software commands via the RxD0 pin. Software commands are
explained here below.
Table 1.79. Software commands (Standard serial I/O mode 1)
When ID is
not verificate
Not
Control command
Page read
2nd byte 3rd byte 4th byte 5th byte 6th byte
Address
(high)
Data
output
Data
output
Data
Data
1
2
FF16
4116
Address
(middle)
output output to
259th byte
acceptable
Address
(high)
Data
input
Data
input
Data
input
Data
input to
Page program
Address
(middle)
Not
acceptable
259th byte
3
4
5
6
Erase all unlocked blocks
Read status register
Clear status register
Read lockbit status
A716
7016
5016
7116
D016
Not
acceptable
Acceptable
SRD1
output
SRD
output
Not
acceptable
Not
Address Lock bit
(high)
Address
(middle)
data
acceptable
output
Address Address ID size
ID1
To ID7
7
8
ID check function
Download function
F516
FA16
Address
(low)
Size
Acceptable
(middle)
Size
(high)
Check-
sum
Data
input
To
Not
acceptable
(high)
required
number
of times
(low)
Version
data
output
Address
(high)
Version Version Version
9
Version data output function FB16
Version
data
output
Address
(middle)
Acceptable
Version
data output
to 9th byte
Data
output to
259th byte
data
output
Data
data
output
Data
data
output
Data
10 Boot area output function
FC16
Not
acceptable
output
output
output
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register 1 data.
Note 3:All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the rise of the clock.
CLK0
A8 to
A15
A16 to
A23
FF16
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
data0
data255
P53(BUSY)
Figure 1.107. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
CLK0
RxD0
(M16C reception data)
7016
SRD
output
SRD1
output
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.108. Timing for reading the status register
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command
This command clears the bits (SR3–SR4) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the P53 (BUSY) signal changes from the “H” to the “L”
level.
CLK0
RxD0
(M16C reception data)
5016
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.109. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
0
–D ) for the page (256 bytes) specified with addresses
7
A
8
When reception setup for the next 256 bytes ends, the P53 (BUSY) signal changes from the “H” to the
“L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
CLK0
A
8
to
A
16 to
RxD0
(M16C reception data)
4116
data0
data255
A
15
A23
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.110. Timing for the page program
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the P53 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register.
CLK0
A716
D016
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.111. Timing for erasing all unlocked blocks
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of
the specified block for addresses A8 to A23.
The M30201 (flash memory version) does not have the lock bit, so the read value is always “1” (block
unlock).
CLK0
A
8
to
A16 to
A23
7116
RxD0
A
15
(M16C reception data)
DQ6
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.112. Timing for reading lock bit status
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
CLK0
Program
data
Check
sum
Program
data
FA16
Data size (low)
RxD0
(M16C reception data)
Data size (high)
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.113. Timing for download
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK0
FB16
RxD0
(M16C reception data)
TxD0
'V'
'E'
'R'
'X'
(M16C transmit data)
P53(BUSY)
Figure 1.114. Timing for version information output
Boot ROM Area Output Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first, in sync with the fall of the clock.
CLK0
A
8
to
A
16 to
FC16
RxD0
(M16C reception data)
A
15
A23
TxD0
data0
data255
(M16C transmit data)
P53(BUSY)
Figure 1.115. Timing for boot ROM area output
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK0
ID size
ID1
ID7
F516
DF16
FF16
0F16
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
P53(BUSY)
Figure 1.116. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write
a program into the flash memory, which already has the ID code set for these addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Watchdog timer vector
ID6 DBC vector
ID7
Reset vector
4 bytes
Figure 1.117. ID code storage addresses
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 1.80 gives the definition of each status register bit. After clearing the reset, the status register
outputs “8016”.
Table 1.80. Status register (SRD)
Definition
SRD0 bits
Status name
"1"
Ready
"0"
Busy
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Status bit
Reserved
Erase bit
Program bit
Reserved
Reserved
Reserved
Reserved
-
-
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Status bit (SR7)
The status bit indicates the operating status of the flash memory. When power is turned on, “1” (ready)
is set for it. The bit is set to “0” (busy) during an auto write or auto erase operation, but it is set back to
“1” when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to “1”. When the erase status is cleared, it is set to “0”.
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to “1”. When the program status is cleared, it is set to “0”.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 1.81 gives the definition of each status register 1 bit. “0016” is output when power is turned ON and
the flag status is maintained even after the reset.
Table 1.81. Status register 1 (SRD1)
Definition
SRD1 bits
Status name
"1"
"0"
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Not update
Update completed
-
-
-
Reserved
-
Checksum match bit
ID check completed bits
Mismatch
Match
00
01
10
11
Not verified
Verification mismatch
Reserved
Verified
SR9 (bit1)
SR8 (bit0)
Data receive time out
Reserved
Normal operation
-
Time out
-
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
Check Sum Consistency Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Reception Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
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Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Example Circuit Application for The Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary
according to programmer, therefore see the peripheral unit manual for more information.
Clock input
P5 output
CLK0
P5 (BUSY)
3
3
R
XD0
Data input
T
XD0
Data output
M30201 Flash
memory version
V
PP
CNVss
(1) Control pins and external circuitry will vary according to peripheral unit. For more
information, see the peripheral unit manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched
via a switch.
Figure 1.118. Example circuit application for the standard serial I/O mode 1
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Overview of standard serial I/O mode 2 (clock asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART0).
Standard serial I/O mode 2 is engaged by releasing the reset with the P53 (BUSY) pin "L" level.
The TxD0 pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.
After the reset is released, connections can be established at 9,600 bps when initial communications (Fig-
ure 1.119) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz input
oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps by
executing software commands. However, communication errors may occur because of the oscillation fre-
quency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate.
After executing commands from a peripheral unit that requires time to erase and write data, as with erase
and program commands, allow a sufficient time interval or execute the read status command and check
how processing ended, before executing the next command.
Data and status registers in memory can be read after transmitting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or not,
can be checked by reading the status register. Here following are explained initial communications with
peripheral units, how frequency is identified and software commands.
Initial communications with peripheral units
After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-
quency of the main clock, by sending the code as prescribed by the protocol for initial communications
with peripheral units (Figure 1.119).
(1) Transmit "B016" from a peripheral unit. If the oscillation frequency input by the main clock is 10 MHz,
the MCU with internal flash memory outputs the "B016" check code. If the oscillation frequency is
anything other than 10 MHz, the MCU does not output anything.
(2) Transmit "0016" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit
rate generator so that "0016" can be successfully received.)
(3) The MCU with internal flash memory outputs the "B016" check code and initial communications end
1
successfully * . Initial communications must be transmitted at a speed of 9,600 bps and a transfer
interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps.
*1. If the peripheral unit cannot receive "B016" successfully, change the oscillation frequency of the main clock.
MCU with internal
Peripheral unit
flash memory
Reset
(1) Transfer "B016
"
"B016
"B016
"
"
If the oscillation frequency input
by the main clock is 10 MHz, the
MCU outputs "B016". If other than
10 MHz, the MCU does not
output anything.
(2) Transfer "0016" 16 times
"0016
"
"
1st
At least 15ms
transfer interval
2nd
"0016
"0016
"
"
15 th
16th
"0016
"B016
"
(3) Transfer check code "B016"
The bit rate generator setting completes (9600bps)
Figure 1.119. Peripheral unit and initial communication
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
How frequency is identified
When "0016" data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the
bit rate generator is set to match the operating frequency (2 - 10 MHz). The highest speed is taken from
the first 8 transmissions and the lowest from the last 8. These values are then used to calculate the bit
rate generator value for a baud rate of 9,600 bps.
Baud rate cannot be attained with some operating frequencies. Table 1.82 gives the operation frequency
and the baud rate that can be attained for.
Table 1.82 Operation frequency and the baud rate
Operation frequency
(MH
Baud rate
9,600bps
Baud rate
19,200bps
Baud rate
38,400bps
Baud rate
57,600bps
Z
)
√
√
√
–
–
√
–
–
√
–
–
10MH
8MH
7.3728MH
Z
–
–
√
√
–
–
√
–
√
√
–
√
√
√
√
√
√
√
√
√
√
–
√
√
√
√
√
√
√
√
√
√
√
Z
Z
6MH
5MH
Z
Z
4.5MH
4.194304MH
4MH
3.58MH
Z
Z
Z
Z
3MH
2MH
Z
Z
√ : Communications possible
– : Communications not possible
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Commands
Table 1.83 lists software commands. In the standard serial I/O mode 2, erase operations, programs and
reading are controlled by transferring software commands via the RxD0 pin. Standard serial I/O mode 2
adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software com-
mands of standard serial I/O mode 1. Software commands are explained here below.
Table 1.83. Software commands (Standard serial I/O mode 2)
1st byte
transfer
When ID is
not verified
Not
Control command
Page read
2nd byte 3rd byte 4th byte 5th byte 6th byte
Address Address
(middle) (high)
Data
output
Data
output output
Data
Data
output to
259th byte
Data
1
2
FF16
4116
acceptable
Address Address
Data
input
Data
input
Data
input
Not
acceptable
Page program
(middle)
(high)
input to
259th byte
D016
Not
acceptable
Acceptable
3
4
5
6
Erase all unlocked blocks
Read status register
Clear status register
Read lock bit status
A716
7016
5016
7116
SRD
output
SRD1
output
Not
acceptable
Not
Address Address Lock bit
(middle)
(high)
data
output
acceptable
Address Address Address
7
8
Code processing function
Download function
ID size
ID1
To
To ID7
Acceptable
F516
FA16
(low)
(middle)
Size
(high)
Check-
sum
Not
acceptable
Size (low)
(high)
Data required
input number
of times
Version
data
output
Version Version Version Version
Version
data
output to
9th byte
Data
output to
259th byte
9
Version data output function
FB16
FC16
data
data
data
data
Acceptable
output
output
output output
Address Address
(middle)
Data
Data
Data
Not
acceptable
10 Boot ROM area output
function
(high)
output
output output
11 Baud rate 9600
12 Baud rate 19200
13 Baud rate 38400
14 Baud rate 57600
B016
B116
B216
B316
B016
B116
B216
B316
Acceptable
Acceptable
Acceptable
Acceptable
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register 1 data.
Note 3:All commands can be accepted when the flash memory is totally blank.
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the “FF16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first in sync with the fall of the clock.
A8 to
A15
A16 to
A23
FF16
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
data0
data255
Figure 1.120. Timing for page read
Read Status Register Command
This command reads status information. When the “7016” command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
RxD0
(M16C reception data)
7016
SRD
output
SRD1
output
TxD0
(M16C transmit data)
Figure 1.121. Timing for reading the status register
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Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clear Status Register Command
This command clears the bits (SR3–SR4) which are set when the status register operation ends in
error. When the “5016” command code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the RTS1 (BUSY) signal changes from the “H” to the
“L” level.
RxD0
(M16C reception data)
5016
TxD0
(M16C transmit data)
Figure 1.122. Timing for clearing the status register
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the “4116” command code with the 1st byte.
(2) Transfer addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
0
–D ) for the page (256 bytes) specified with addresses
7
A
8
When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the “H” to
the “L” level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
A
8
to
A
16 to
RxD0
(M16C reception data)
4116
data0
data255
A
15
A23
TxD0
(M16C transmit data)
Figure 1.123. Timing for the page program
161
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the “A716” command code with the 1st byte.
(2) Transfer the verify command code “D016” with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS1 (BUSY) signal changes from the “H” to the “L” level. The result of the
erase operation can be known by reading the status register.
A716
D016
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
Figure 1.124. Timing for erasing all unlocked blocks
162
Mitsubishi microcomputers
M30201 Group
Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the “7116” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. Write the highest address of
the specified block for addresses A8 to A23.
The M30201 (flash memory version) does not have the lock bit, so the read value is always “1” (block
unlock).
A
8
to
A16 to
A23
7116
RxD0
A
15
(M16C reception data)
DQ6
TxD0
(M16C transmit data)
Figure 1.125. Timing for reading lock bit status
Download Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the “FA16” command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
Program
data
Check
sum
Program
data
FA16
Data size (low)
RxD0
(M16C reception data)
Data size (high)
TxD0
(M16C transmit data)
Figure 1.126. Timing for download
163
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Version Information Output Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the “FB16” command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
FB16
RxD0
(M16C reception data)
TxD0
'V'
'E'
'R'
'X'
(M16C transmit data)
Figure 1.127. Timing for version information output
Boot ROM Area Output Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the “FC16” command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0–D7) for the page (256 bytes) specified with addresses A8 to
A23 will be output sequentially from the smallest address first.
A
8
to
A
16 to
FC16
RxD0
(M16C reception data)
A
15
A23
TxD0
data0
data255
(M16C transmit data)
Figure 1.128. Timing for boot ROM area output
164
Mitsubishi microcomputers
M30201 Group
Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
ID Check
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the “F516” command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
ID size
ID1
ID7
F516
DF16
FF16
0F16
RxD0
(M16C reception data)
TxD0
(M16C transmit data)
Figure 1.129. Timing for the ID check
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write
a program into the flash memory, which already has the ID code set for these addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Watchdog timer vector
ID6 DBC vector
ID7
Reset vector
4 bytes
Figure 1.130. ID code storage addresses
165
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Baud Rate 9600
This command changes baud rate to 9,600 bps. Execute it as follows.
(1) Transfer the "B016" command code with the 1st byte.
(2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD0
B016
(M16C reception data)
TxD0
B016
(M16C transmit data)
Figure 1.131. Timing of baud rate 9600
166
Mitsubishi microcomputers
M30201 Group
Appendix Standard Serial I/O Mode 2 (Flash Memory Version) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Baud Rate 19200
This command changes baud rate to 19,200 bps. Execute it as follows.
(1) Transfer the "B116" command code with the 1st byte.
(2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD0
B116
(M16C reception data)
TxD0
B116
(M16C transmit data)
Figure 1.132. Timing of baud rate 19200
Baud Rate 38400
This command changes baud rate to 38,400 bps. Execute it as follows.
(1) Transfer the "B216" command code with the 1st byte.
(2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD0
B216
(M16C reception data)
TxD0
B216
(M16C transmit data)
Figure 1.133. Timing of baud rate 38400
Baud Rate 57600
This command changes baud rate to 57,600 bps. Execute it as follows.
(1) Transfer the "B316" command code with the 1st byte.
(2) After the "B316" check code is output with the 2nd byte, change the baud rate to 57,600 bps.
RxD0
B316
(M16C reception data)
TxD0
B316
(M16C transmit data)
Figure 1.134. Timing of baud rate 57600
167
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Example Circuit Application for The Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
CLK0
P53(BUSY)
R
XD0
Data input
T
XD0
Data output
M30201 Flash
memory version
V
PP
CNVss
(1) Control pins and external circuitry will vary according to peripheral unit. For more
information, see the peripheral unit manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched
via a switch.
Figure 1.135. Example circuit application for the standard serial I/O mode 2
168
Mitsubishi microcomputers
M30201 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Revision History
Version
Revision
date
Contents for change
Pages 1, 5
internal interrupt 9 ->13
Pages 1, 5
REV.E
01.4.12
2.7 to 5.5V (f(XIN)=7MHz with software one-wait):mask ROM version
->2.7 to 5.5V (f(XIN)=3.5MHz ):mask ROM version
Page 5
Power consumption 18mA (f(XIN)=7MHz with software one-wait, VCC=3V)
->11mA (f(XIN)=3.5MHz , VCC=3V)
Page 6
M30201M2-XXXSP/FP, M30201M2T-XXXSP/FP ->Delete
M30201M4T-XXXSP, M30201F6T-XXXSP ->Delete
M30201M6-XXXFP, M30201M6T-XXXFP ->Addition
Pages 9, 10
Figures 1.7 and 1.8 are partly revised.
Page 14
Figure 1.11 is partly revised.
Page 16
Figure 1.14 is partly revised (Bit 7 of the processor mode register 1).
Wait bit ->Reserved bit
Page 17
Software wait
Page 20
Figure 1.18 is partly revised (Note 8 is partly revised).
Page 21
Figure 1.19 is partly revised (n=0716 : approx. 16.5kHz -> 19.5kHz).
Page 33
Figure 1.24 is partly revised (Note 2 is added).
Page 49
Figure 1.39 is partly revised.
Page 77
Figure 1.72 is partly revised (UARTi transmit/receive mode register).
Page 78
Figure 1.73 is partly revised.
Page 80
Figure 1.74 is partly revised.
Page 85
Figure 1.79 is partly revised.
Pages 90 to 96
Figures 1.83 to 1.89 are partly revised.
Pages 110 to 113, 118 to 122
Tables 1.36 to 1.39 and 1.56 to 1.71 are partly revised.
Page 124
Table 1.74 is partly revised (Boot ROM area 4 K bytes -> 3.5 K bytes) .
Page 142 to 168
Standard serial I/O mode 2 is added.
Revision history
M30201 Group data sheet
169
Keep safety first in your circuit designs!
●
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble may
occur with them. Trouble with semiconductors may lead to personal injury, fire or
property damage. Remember to give due consideration to safety when making your
circuit designs, with appropriate measures such as (i) placement of substitutive,
auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any
malfunction or mishap.
Notes regarding these materials
●
●
●
These materials are intended as a reference to assist our customers in the selection
of the Mitsubishi semiconductor product best suited to the customer's application;
they do not convey any license under any intellectual property rights, or any other
rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or
infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in
these materials.
All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication
of these materials, and are subject to change by Mitsubishi Electric Corporation
without notice due to product improvements or other reasons. It is therefore
recommended that customers contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical
errors. Mitsubishi Electric Corporation assumes no responsibility for any damage,
liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation
by various means, including the Mitsubishi Semiconductor home page (http://
www.mitsubishichips.com).
●
●
When using any or all of the information contained in these materials, including
product data, diagrams, charts, programs, and algorithms, please be sure to evaluate
all information as a total system before making a final decision on the applicability of
the information and products. Mitsubishi Electric Corporation assumes no
responsibility for any damage, liability or other loss resulting from the information
contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human life is
potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized
Mitsubishi Semiconductor product distributor when considering the use of a product
contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint
or reproduce in whole or in part these materials.
●
●
If these products or technologies are subject to the Japanese export control
restrictions, they must be exported under a license from the Japanese government
and cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan
and/or the country of destination is prohibited.
●
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semicon
ductor product distributor for further details on these materials or the products con
tained therein.
MITSUBISHI SEMICONDUCTORS
M30201 Group DATA SHEET REV.E
April First Edition 1998
July Second Edition 1998
February Third Edition 1999
May Fourth Edition 1999
April Fifth Edition 2001
Editioned by
Committee of editing of Mitsubishi Semiconductor DATA SHEET
Published by
Mitsubishi Electric Corp., Kitaitami Works
This book, or parts thereof, may not be reproduced in any form without
permission of Mitsubishi Electric Corporation.
©2001 MITSUBISHI ELECTRIC CORPORATION
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