M30260M8A-XXXGP#X1 [RENESAS]
MICROCONTROLLER;
| 型号： | M30260M8A-XXXGP#X1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | MICROCONTROLLER 外围集成电路 |
| 文件： | 总30页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1.
2.
All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.
Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights
of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3.
4.
You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5.
When exporting the products or technology described in this document, you should comply with the applicable export control
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7.
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does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
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expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”:
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; safety equipment; and medical equipment not specifically designed for life support.
“Specific”:
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8.
9.
You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
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control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
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manufactured by you.
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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0071-0051
Rev.0.51
Jul.25, 2006
1. Overview
The M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) is a single-chip control MCU, fabricated using
high-performance silicon gate CMOS technology, embedding the M16C/60 Series CPU core. The M16C/
26A Group (M16C/26A, M16C/26B, M16C/26T) is housed in 42-pin and 48-pin plastic molded packages.
With a 1M byte address space, this MCU combines advanced instruction manipulation capabilities to pro-
cess complex instructions by less bytes and execute instructions at higher speed. The M16C/26A Group
(M16C/26A, M16C/26B, M16C/26T) has a multiplier and DMAC adequate for office automation, communi-
cation devices and industrial equipment, and other high-speed processing applications.
1.1 Applications
Audio, cameras, office/communications/portable/ equipment, air-conditioning equipment, home appli-
ances, etc.
page 1
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.2 Performance Outline
Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/
26T).
Table 1.1. M16C/26A Group(M16C/26A, M16C/26B, M16C/26T) Performance (48-Pin Package)
Item
Specification
CPU
Basic instructions
Minimun instruction
execution time
91 instructions
(4)
41.7 ns (f(BCLK) = 24MH
Z
, VCC = 4.2 to 5.5 V)
, VCC = 3.0 to 5.5 V)
100 ns (f(BCLK) = 10MH , VCC = 2.7 to 5.5 V)
50 ns (f(BCLK) = 20MH
(M16C/26B)
(M16C/26A, M16C/26B, M16C/26T(T-ver.))
(M16C/26A , M16C/26B)
50 ns (f(BCLK) = 20MH
Z
Z
Z
, VCC = 4.2 to 5.5 V -40 to 105°C)
, VCC = 4.2 to 5.5 V -40 to 125°C)
(M16C/26T(V-ver.))
(M16C/26T(V-ver.))
62.5 ns (f(BCLK) = 16MH
Single-chip mode
1 Mbyte
Z
Operating mode
Address space
Memory capacity
I/O ports
See 1.4 Product Information
Peripheral
Function
39 I/O pins
Multifunction timers
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase motor control timer
Serial I/O
2 channels (UART, clock synchronous serial I/O)
2
(1)
(2)
1 channel (UART, clock synchronous, I C bus , or IEBus
10 bit A/D Converter : 1 circuit, 12 channels
2 channels
)
A/D converter
DMAC
CRC calcuration circuit
Watchdog timer
Interrupts
1 circuit (CRC-CCITT and CRC-16) with MSB/LSB selectable
15 bits x 1 channel (with prescaler)
20 internal and 8 external sources, 4 software sources,
Interrupt priority level: 7
Clock generation circuit
4 circuits
Main clock oscillation circuit(*), Sub-clock oscillation circuit(*)
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resister.
Oscillation stop detection
Voltage detection circuit
Power supply voltage
Main clock oscillation stop, re-oscillation detection function
On-chip (M16C/26A, M16C/26B), not on-chip (M16C/26T)
Electrical
VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)(4)
VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ)
VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)
VCC = 3.0 to 5.5 V
(M16C/26B)
Characteristics
(M16C/26A, M16C/26B)
(M16C/26T(T-ver.))
(M16C/26T(V-ver.))
VCC = 4.2 to 5.5 V
Power consumption
16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (Vcc = 3 V, in stop mode)
Flash Memory Programming /erasure
2.7 to 5.5 V (M16C/26A, M16C/26B)
Version
voltage
3.0 to 5.5 V (M16C/26T(T-ver.)) 4.2 to 5.5 V (M16C/26T(V-ver.))
100 times (all area) or 1,000 times (block 0 to 3)
/ 10,000 times (block A, block B)(3)
Programming /erasure
endurance
Operating Ambient Temperature
-20 to 85°C / -40 to 85°C (3)
(M16C/26A , M16C/26B)
(M16C/26T(T-ver.))
(M16C/26T(V-ver.))
-40 to 85°C
-40 to 105°C / -40 to 125°C
48-pin plastic molded QFP
Package
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.7 Product Code for the program and erase endurance, and operating ambient temperature.
4. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.
page 2
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.2. Performance outline of M16C/26A group (M16C/26A, M16C/26B) (42-pin device)
Item
Performance
CPU
Basic instructions
Minimun instruction
execution time
91 instructions
41.7 ns (f(BCLK) = 24 MHz (4), VCC = 4.2 to 5.5 V
50 ns (f(BCLK) = 20 MH , VCC = 3.0 to 5.5 V)
, VCC = 2.7 to 5.5 V)
(M16C/26B)
Z
(M16C/26A, M16C/26B)
(M16C/26A, M16C/26B)
100 ns (f(BCLK) = 10 MH
Single-chip mode
1M byte
Z
Operation mode
Address space
Memory capacity
Port
See 1.4 Product Information
Peripheral
function
33 I/O pins
Multifunction timer
Timer A: 16 bits x 5 channels, Timer B: 16 bits x 3 channels
Three-phase motor control timer
Serial I/O
1 channel (UART, clock synchronous serial I/O)
1 channel (UART, clock synchronous, I2C bus(1) , or IEBus(2)
10 bit A/D converter: 1 circuit, 10 channels
2 channels
)
A/D converter
DMAC
CRC calcuration circuit
Watchdog timer
Interrupt
1 circuits (CRC-CCITT and CRC-16) with MSB/LSB selectable
15 bits x 1 channel (with prescaler)
18 internal and 8 external sources, 4 software sources,
Interrupt priority level: 7
Clock generation circuit
4 circuits
Main clock(*), Sub-clock(*)
On-chip oscillator, PLL frequency synthesizer
(*)Equipped with a built-in feedback resister.
Main clock oscillation stop, re-oscillation detection function
On-chip
Oscillation stop detection
Voltage detection circuit
Supply voltage
Electrical
VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)(4)
VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ)
VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)
16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)
25 µA (f(XCIN) = 32 KHz on RAM)
(M16C/26B)
(M16C/26A, M16C/26B)
Characteristics
Power Consumption
3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)
0.7 µA (Vcc = 3 V, in stop mode)
2.7 to 5.5 V
Flash memory Programming/erasure
voltage
Programming/erasure
endurance
100 times (all area) or 1,000 times (block 0 to 3)
/ 10,000 times (block A, block B)(3)
-20 to 85°C / -40 to 85°C (3)
Operating Ambient Temperature
Package
42-pin plastic molded SSOP
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. See Table 1.7 Product Code for the program and erase endurance, and operating ambient temperature.
4. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.
page 3
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.3 Block Diagram
Figure 1.1 and 1.2 show block diagrams of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 48-
pin package and 42-pin package.
3
8
8
8
4
8
Port P9
Port P8
Port P7
Port P10
Port P6
Port P1
Peripheral functions
Clock generation circuit
Timer (16-bit)
Output (timer A): 5channels
Input (timer B): 3 channels
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
XIN-XOUT
XCIN-XCOUT
On-Chip Oscillator
PLL frequency synthesizer
Three-phase motor
control circuit
10-bit A/D converter
12 channels
M16C/60 series CPU core
Memory
R0H
R1H
R0L
R1L
SB
ROM(1)
RAM(2)
Watchdog timer
(15 bits)
USP
ISP
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
FB
Multiplier
CRC calculation circuit
(CCITT, CRC-16 )
NOTES:
1: ROM size depends on the MCU type.
2: RAM size depends on the MCU type.
Figure 1.1 Block Diagram(48-pin Package)
page 4
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3
4
8
8
2
8
Port P9
Port P8
Port P7
Port P10
Port P6
Port P1
Peripheral functions
Clock generation circuit
Timer (16-bit)
Output (timer A): 5channels
Input (timer B): 3 channels
UART or
clock synchronous serial I/O
(8 bits X 2 channels)
XIN-XOUT
XCIN-XCOUT
On-Chip Oscillator
PLL frequency synthesizer
Three-phase motor
control circuit
10-bit A/D converter
10 channels
M16C/60 series CPU core
Memory
R0H
R1H
R0L
R1L
ROM(1)
RAM(2)
SB
Watchdog timer
(15 bits)
USP
ISP
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
FB
Multiplier
CRC calculation circuit
(CCITT, CRC-16 )
NOTES:
1: ROM size depends on the MCU type.
2: RAM size depends on the MCU type.
Figure 1.2 Block Diagram( 42-pin Package)
page 5
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.4 Product List
Tables 1.3 to 1.6 lists product information, Figure 1.3 shows a product numbering system, Table 1.7 lists
the product code, and Figure 1.4 shows the marking.
Table 1.3 M16C/26A
Current as of Jul., 2006
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30260F3AGP
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
(N)
24K + 4K
48K + 4K
64K + 4K
24K + 4K
48K + 4K
64K + 4K
24K
1K
2K
2K
1K
2K
2K
1K
2K
2K
1K
2K
2K
M30260F6AGP
PLQP0048KB-A (48P6Q-A)
U3, U5, U7, U9
M30260F8AGP
Flash
memory
M30263F3AFP
M30263F6AFP
PRSP0042GA-B (42P2R)
PLQP0048KB-A (48P6Q-A)
PRSP0042GA-B (42P2R)
U5, U9
U3, U5
U5
M30263F8AFP
M30260M3A-XXXGP
M30260M6A-XXXGP
M30260M8A-XXXGP
M30263M3A-XXXFP
M30263M6A-XXXFP
M30263M8A-XXXFP
48K
64K
Mask ROM
24K
48K
64K
(N): New
Table 1.4 M16C/26B
Current as of Jul., 2006
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30260F8BGP
M30263F8BFP
(D)
(D)
64K + 4K
64K + 4K
2K
2K
PLQP0048KB-A (48P6Q-A)
PRSP0042GA-B (42P2R)
U7
U9
Flash
memory
(D): Under development
Table 1.5 M16C/26T T-ver.
Current as of Jul., 2006
ROM
Capacity
RAM
Capacity
Type Number
Package Type
Remarks
Product Code
M30260F3TGP
M30260F6TGP
M30260F8TGP
NOTE:
24K + 4K
48K + 4K
64K + 4K
1K
2K
2K
Flash
memory
PLQP0048KB-A (48P6Q-A)
U3, U7
1. Please contact Renesas Technolog Corp. for details on Mask ROM version.
Table 1.6 M16C/26T V-ver.
Current as of Jul., 2006
ROM
Capacity
RAM
Capacity
Type Number
Package
Remarks
Product Code
M30260F3VGP
24K + 4K
48K + 4K
64K + 4K
1K
2K
2K
Flash
memory
PLQP0048KB-A (48P6Q-A)
U3, U7
M30260F6VGP
M30260F8VGP
NOTE:
1. Please contact Renesas Technolog Corp. for details on Mask ROM version.
page 6
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Type No. M 3 0 2 6 0 M 8 A - XXX G P - U3
Product code:
See Tables 1.7 to 1.10
Package type:
GP: PLQP0048KB-A (48P6Q) (M16C/26A, M16C/26B, M16C/26T)
FP: PRSP0042GA-B (42P2R) (M16C/26A, M16C/26B)
ROM number:
ROM number is omitted in flash memory version
Version:
A
B
T
V
: M16C/26A
: M16C/26B
: M16C/26T T-ver.
: M16C/26T V-ver.
ROM / RAM capacity:
3: (24K+4K) bytes (Note 1) / 1K bytes
6: (48K+4K) bytes (Note 1) / 2K bytes
8: (64K+4K) bytes (Note 1) / 2K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Memory type:
M: Mask ROM version
F: Flash memory version
Pin count (The value itself has no specific meaning)
M16C/26A Group
M16C Family
Figure 1.3 Product Numbering System
page 7
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.7 Product Code (Flash Memory Version) - M16C/26A, M16C/26B
Internal ROM
(User Program Space)
Internal ROM
(Data Space)
Product
Code
Operating Ambient
Package
Lead free
Program and
Erase
Endurance
Program and
Erase
Endurance
Temperature
Temperature
Range
Temperature
Range
U3
-40 to 85ºC
-20 to 85ºC
-40 to 85ºC
-20 to 85ºC
100
100
0 to 60ºC
U5
U7
U9
0 to 60ºC
-40 to 85ºC
-20 to 85ºC
1,000
10,000
Table 1.8 Product Code (Mask ROM Version - M16C/26A)
Product
Code
Operating Ambient
Temperature
Package
Lead free
U3
-40ºC to 85ºC
-20ºC to 85ºC
U5
NOTE:
1. The lead contained products, D3, D5, D7, and D9 are put together with U3, U5, U7, and U9 respectively.
Lead-free products can be mounted by both conventional Sn-Pb paste and Lead-free paste (Sn-Ag-Cu
plating).
Table 1.9 Product Code (Flash Memory Version) - M16C/26T T-ver.
Internal ROM
(User Program Space)
Internal ROM
(Data Space)
Product
Code
Operating Ambient
Temerature
Package
Lead free
Programming
Temperature
and erasure
range
Programming
and erasure
endurance
Temperature
range
endurance
U3
U7
100
100
0ºC to 60ºC
1,000
-40ºC to 85ºC
-40ºC to 85ºC
10,000
Table 1.10 Product Code (Flash Memory Version) - M16C/26T V-ver.
Internal ROM
(User Program Space)
Internal ROM
(Data Space)
Product
Code
Operating Ambient
Temerature
Package
Lead free
Programming
Temperature
and erasure
range
Programming
and erasure
endurance
Temperature
range
endurance
U3
U7
100
100
0ºC to 60ºC
1,000
-40ºC to 125ºC
-40ºC to 125ºC
10,000
page 8
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26A, M16C/26B
Product Name : indicates M30260F8AGP
0260F8A
A U3
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXX
U3 : Indicates Product code (see Table 1.7 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
(2) Flash memory version, PRSP0042GA-B (42P2R), M16C/26A, M16C/26B
Product Name : indicates M30263F8AFP
M30263F8AFP
A U3
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXXXX
U3 : Indicates Product code (see Table 1.7 Product Code)
Date Code (7 digits) fi indicates manufacturing management code
(3) MASK ROM version, PLQP0048KB-A (48P6Q), M16C/26A
Product Name : indicates M30260M8AGP
0260M8A
001A U3
XXXXX
ROM number, Chip Version and Product Code:
001: Indicates ROM Number
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates Product code (see Table 1.8 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
(4) MASK ROM version, PRSP0042GA-B (42P2R), M16C/26A
Product Name and ROM number
M30263M8A and FP are indicated of Produnct name
001 is indicated of ROM number
M30263M8A-001FP
A U3
Chip Version and Product Code:
A : Indicates chip version
The first edition is shown to be blank and continues
with A and B.
XXXXXXX
U3 : Indicates Product code (see Table 1.8 Product Code)
Date Code (7 digits) fi indicates manufacturing management code
Figure 1.4 Marking Diagram (M16C/26A , M16C/26B)
page 9
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T T-ver.
0260F8T
Product Name : indicates M30260F8TGP
A U3
Chip Version and Product Code:
A : Indicates chip version
XXXXX
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates product code (see Table 1.9 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
(2) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T V-ver.
0260F8V
A U3
Product Name : indicates M30260F8VGP
Chip Version and Product Code:
A : Indicates chip version
XXXXX
The first edition is shown to be blank and continues
with A and B.
U3 : Indicates product code (see Table 1.10 Product Code)
Date Code (5 digits) fi indicates manufacturing management code
Figure 1.5 Marking Diagram (M16C/26T)
page 10
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.5 Pin Assignments
Figures 1.6 and 1.7 show the Pin Assignments (top view).
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
P71/RxD2/TA0IN/SCL2/CLK1
P72/CLK2/TA1OUT/V/RxD1
P73/CTS2/RTS2/TA1IN/V/TxD1
P74/TA2OUT/W
P104/AN4/KI0
P103/AN3
P102/AN2
P101/AN1
P75/TA2IN/W
P76/TA3OUT
P77/TA3IN
AVss
P80/TA4OUT/U
P100/AN0
VREF
P81/TA4IN/U
P82/INT0
P83/INT1
AVcc
P93/AN24
P84/INT2/ZP
Note. Set PACR2 to PACR0 bit in the PACR register
to "100 " before you input and output it after
2
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: PLQP0048KB-A (48P6Q)
Figure 1.6 Pin Assignment for 48-Pin Package (Top View)
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REJ03B0071-0051
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.11 Pin Characteristics for 48-Pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Port
Timer Pin
UART Pin
Analog Pin
1
2
P92
P91
P90
TB2IN
AN3
AN3
AN3
2
1
0
TB1IN
TB0IN
3
CLKOUT
4
CNVss
5
X
CIN
P8
7
6
6
X
COUT
P8
7
RESET
8
XOUT
9
Vss
10
XIN
11 Vcc
12
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
NMI
SD
ZP
13
INT
INT
INT
2
1
0
14
15
16
TA4IN / U
TA4OUT / U
TA3IN
17
18
19
TA3OUT
20
TA2IN / W
TA2OUT / W
TA1IN / V
TA1OUT / V
TA0IN
21
22
CTS
2
/ RTS
2
/ T
X
D1
23
CLK
2
/ RX
D1
24
RX
D2
/ SCL
2
/ CLK
1
25
P70
P67
P66
P65
P64
P63
P62
P61
P60
P17
P16
P15
TA0OUT
T
T
X
X
D
2
1
/ SDA2 / RTS1 / CTS1 / CTS0 / CLKS1
26
D
27
RXD1
28
CLK
1
1
29
RTS
/ CTS
/ CTS
1
/ CTS0 / CLKS1
30
TXD0
31
RXD0
32
CLK
0
0
33
RTS
0
34
INT
INT
INT
5
4
3
IDU
IDW
IDV
35
36
ADTRG
37
P10
P10
P10
P10
P10
P10
P10
7
6
5
4
3
2
1
KI
KI
KI
KI
3
2
1
0
AN
AN
AN
AN
AN
AN
AN
7
6
5
4
3
2
1
38
39
40
41
42
43
44 AVss
45
P10
0
AN0
46
VREF
47 AVcc
48
P93
AN24
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
P10
P10
P10
P10
P10
P10
P10
1
/AN
/AN
/AN
/AN
/AN
/AN
/AN
1
AVSS
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
2
2
P100/AN0
V
REF
3
3
3
AVCC
1/TB1IN/AN31
4
4
/KI
/KI
/KI
/KI
0
4
5
5
1
P9
5
P9
0
/TB0IN/AN30/CLKout
CNVSS
6
6
2
6
7
7
3
7
P15
/INT
3
/ADTRG/IDV
P8
7
/XCIN
8
P1
P1
6
7
/INT
/INT
4
5
/IDW
/IDU
P86
/XCOUT
9
RESET
10
11
12
13
14
15
16
17
18
19
20
21
P64
/CTS
1
/RTS
1
/CTS
0
/CLKS
1
X
V
OUT
SS
P65
/CLK
1
XIN
P66
/RxD
1
P6
P7
P7
7
/TxD
/TxD
/RxD
/CLK
/CTS
/TA2OUT/W
1
V
CC
0
2
/SDA
/SCL
/TA1OUT/V/RxD
/RTS /TA1IN/V/TxD
2
/TA0OUT/CTS
1/RTS1/CTS0/CLKS1
P8
5
/NMI/SD
P84
/INT /ZP
2
1
2
2
/TA0IN/CLK
1
P8
P8
3
/INT
1
0
P72
2
1
2/INT
P73
2
2
1
P81
/TA4IN/U
/TA4OUT/U
P7 /TA3IN
P7
P7
P7
4
P8
0
5
/TA2IN/W
7
6
/TA3OUT
Note. Set PACR2 to PACR0 bit in the PACR register
to "001 " before you input and output it after
2
resetting to each pin. When the PACR register
isn't set up, the input and output function of
some of the pins are disabled.
Package: PRSP0042GA-B (42P2R)
Figure 1.7 Pin Assignment for 42-Pin Package (Top View)
page 13
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.12 Pin Characteristics for 42-Pin Package
Pin
No.
Control
Pin
Interrupt
Pin
Port
Timer Pin
UART Pin
Analog Pin
1
2
3
4
5
6
7
8
9
AVss
P10
0
AN
0
VREF
AVCC
P9
1
0
TB1IN
AN3
1
0
P9
TB0IN
CLKOUT
AN3
CNVss
XCIN
P8
7
6
XCOUT
P8
10 RESET
11
12 Vss
XOUT
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
X
IN
VCC
P85
P84
P83
P82
P81
P80
P77
P76
P75
P74
P73
P72
P71
NMI
SD
ZP
INT
INT
INT
2
1
0
TA4IN / U
TA4OUT / U
TA3IN
TA3OUT
TA2IN / W
TA2OUT / W
TA1IN / V
TA1OUT / V
TA0IN
CTS
2
/ RTS
2
/ T
X
D
1
CLK
2
/ RX
D1
RX
D2
/ SCL
2
/ CLK
1
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
P7
P6
P6
P6
P6
P1
P1
P1
0
7
6
5
4
7
6
5
TA0OUT
T
T
X
X
D
2
1
/ SDA2 / RTS1 / CTS1 / CTS0 / CLKS1
D
RXD1
CLK
1
1
RTS
/ CTS1/ CTS0 / CLKS1
INT
INT
INT
5
4
3
IDU
IDW
IDV
ADTRG
P10
P10
P10
P10
P10
P10
P10
7
6
5
4
3
2
1
KI
KI
KI
KI
3
2
1
0
AN
AN
AN
AN
AN
AN
AN
7
6
5
4
3
2
1
page 14
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
1.6 Pin Description
Table 1.13 Pin Description (48-Pin and 42-Pin Packages)
Classification Pin Name I/O Type
Description
Power Supply
I
Apply 0V to the Vss pin. Apply following voltage to the Vcc pin.
VCC, VSS
2.7 to 5.5 V (M16C/26A, M16C/26B), 3.0 to 5.5 V (M16C/26T T-ver.), 4.2
to 5.5 V (M16C/26T V-ver.)
Analog Power
Supply
Supplies power to the A/D converter. Connect the AVCC pin to VCC and
AVCC
I
the AVSS pin to VSS
AVSS
___________
____________
Reset Input
CNVSS
RESET
CNVSS
XIN
The MCU is in a reset state when "L" is applied to the RESET pin
Connect the CNVSS pin to VSS
I
I
I
Main Clock
Input
I/O pins for the main clock oscillation circuit. Connect a ceramic resonator
or crystal oscillator between XIN and XOUT. To apply external clock, apply
it to XIN and leave XOUT open. If XIN is not used (for external oscillator or
external clock), connect XIN pin to VCC and leave XOUT open
I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator
between XCIN and XCOUT
Main Clock
Output
XOUT
O
Sub Clock Input XCIN
I
Sub Clock Output
XCOUT
O
O
I
Clock Output
CLKOUT
Outputs the clock having the same frequency as f1, f8, f32, or fC
______
________
INT Interrupt
INT0 to INT5
Input pins for the _I_N__T__ interrupt. INT2 can be used for Timer A Z-phase
________
________
Input
function
_______
_N__M___I_ interrupt input pin. _N__M___I_ cannot be used as I/O port while the three-phase
motor control is enabled. Apply a stable "H" to _N__M___I_ after setting it's direction
register to "0" when the three-phase motor control is enabled
Input pins for the key input interrupt
_______
NMI Interrupt
Input
NMI
I
_____
_____
Key Input Interrupt
KI0 to KI3
TA0OUT to
TA4OUT
TA0IN to
TA4IN
I
Timer A
I/O pins for the timer A0 to A4
I/O
Input pins for the timer A0 to A4
I
Input pin for Z-phase
ZP
I
I
Timer B
TB0IN to
TB1IN
Timer B0 to B1 input pins
___
___
Three-Phase
Output pins for the three-phase motor control timer
I/O pins for the three-phase motor control timer
U, U, V, V,
O
___
Motor Control W, W
Timer Output
Serial I/O
IDU, IDW,
_____
I/O
IDV, SD
_________
_________
Input pins to control data transmission
Output pins to control data reception
Inputs and outputs the transfer clock
Inputs serial data
CTS1 to CTS2
I
O
I/O
I
_________
_________
RTS1 to RTS2
CLK1 to CLK2
RxD1 to RxD2
TxD1 to TxD2
CLKS1
Outputs serial data
O
O
I
Output pin for transfer clock
Reference
VREF
Applies reference voltage to the A/D converter
Voltage Input
A/D Converter
Analog input pins for the A/D converter
AN0 to AN7
I
AN30 to AN31
___________
ADTRG
I
Input pin for an external A/D trigger
I/O Ports
I/O ports for CMOS. Each port can be programmed for input or output
under the control of the direction register. An input port can be set, by
program, for a pull-up resistor available or for no pull-up resister available
in 3-bit units
P15 to P17
I/O
I/O ports for CMOS. Each port can be programmed for input or output
under the control of the direction register. An input port can be set, by
program, for a pull-up resistor available or for no pull-up resister available
in 4-bit units
P64 to P67
P70 to P77
P80 to P87
I/O
P10
0 to P107
P90 to P91
I : Input
O : Output
I/O : Input and output
page 15
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1. Overview
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Table 1.13 Pin Description ( 48-pin packages only) (Continued)
Classification Pin Name I/O Type
Description
_________
Serial I/O
CTS0
I
O
I/O
I
Inputs pin to control data transmission
Output pin to control data reception
Inputs and outputs the transfer clock
Inputs serial data
_________
RTS0
CLK0
RxD0
TxD0
TB2IN
O
I
Outputs serial data
Timer B
Timer B2 input pin
A/D Converter AN24
AN32
I
Analog input pins for the A/D converter
I/O ports for CMOS. Each port can be programmed for input or output
under the control of the direction register. An input port can be set, by
program, for a pull-up resistor available or for no pull-up resister available
in 4-bit units
I/O Ports
P60 to P63
P92 to P93
I/O
I : Input
O : Output
I/O : Input and output
page 16
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REJ03B0071-0051
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
2. CPU
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3,
A0, A1 and FB) out of 13 registers. There are two sets of register bank.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1
FB
Address registers (Note)
Frame base registers (Note)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. CPU Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-
ter relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as
A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
page 17
Rev. 0.51 Jul.25, 2006
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2. CPU
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0.
2.8.3 Zero Flag (Z Flag)
This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.
2.8.4 Sign Flag (S Flag)
This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)
This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1.
The I flag is cleared to 0 when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0; USP is selected when the U flag is 1.
The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write 0. When read, its content is undefined.
page 18
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M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3. Memory
3. Memory
Figure 3.1 is a memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The M16C/26A
Group provides 1-Mbyte address space addresses 0000016 to FFFFF16.
The internal ROM is allocated lower address, beginning with address FFFFF16. For example, a 64-Kbyte
internal ROM area is allocated in addresses F000016 to FFFFF16. The flash memory version has two sets
of 2-Kbyte internal ROM area, block A and block B, for data space. These blocks are allocated addresses
F00016 to FFFF16.
The fixed interrupt vectors are allocated addresses FFFDC16 to FFFFF16 and they store the start address
of each interrupt routine.
The internal RAM is allocated higher addresses, beginning with address 0040016. For example, a 1-Kbyte
internal RAM area is allocated in addresses 0040016 to 007FF16. The internal RAM is used for temporarily
storing data. The area is also used as stacks when subroutines are called or interrupt requests are ac-
knowledged.
The SFR is allocated addresses 0000016 to 003FF16. The peripheral function control registers are allo-
cated here. All blank spaces within SFR location are reserved and cannot be accessed by users.
The special page vectors are allocated addresses FFE0016 to FFFDB16. They are used for the JMPS
instruction and JSRS instruction. Refer to the Renesas publication M16C/60 and M16C/20 Series Soft-
ware Manual for details.
0000016
SFR
FFE0016
0040016
Internal RAM
XXXXX16
0F00016
0FFFF16
Special page
vector table
Reserved
Internal ROM
Internal RAM
(1)
Size
Address XXXXX16
007FF16
Internal ROM
(Data space)
Size
Address YYYYY16
FA00016
1K bytes
2K bytes
24K bytes
FFFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
00BFF16
48K bytes
64K bytes
F400016
F000016
Reserved
YYYYY16
FFFFF16
Watchdog timer
Internal ROM(2)
(Program space)
DBC
NMI
Reset
FFFFF16
NOTE:
1. Block A (2 Kbytes) and block B (2 Kbytes).
2. Do not write to the internal ROM in Mask ROM version.
Figure 3.1 Memory Map
page 19
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3. Memory
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
4. Special Function Register (SFR)
(1)
Table 4.1 SFR Information(1)
Address
Register
Symbol
After reset
000016
000116
000216
000316
000416
000516
000616
Processor mode register 0
Processor mode register 1
System clock control register 0
PM0
PM1
CM0
0016
00001000
010010002(M16C/26A)
011010002(M16C/26T)
2
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
System clock control register 1
CM1
001000002
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register(2)
CM2
0X000000
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
XX16
00XXXXXX2 (3)
0016
0016
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1 (4, 5)
Voltage detection register 2 (4, 5)
VCR1
VCR2
00001000
0016
2
PLL control register 0
PLC0
0001X0102
Processor mode register 2
Low voltage detection interrupt register(5)
PM2
D4INT
SAR0
XXX00000
0016
2
002016 DMA0 source pointer
XX16
002116
XX16
002216
XX16
002316
002416 DMA0 destination pointer
002516
DAR0
XX16
XX16
XX16
002616
002716
002816 DMA0 transfer counter
002916
TCR0
XX16
XX16
002A16
002B16
002C16 DMA0 control register
002D16
DM0CON
SAR1
00000X002
002E16
002F16
003016 DMA1 source pointer
003116
XX16
XX16
XX16
003216
003316
003416 DMA1 destination pointer
003516
DAR1
XX16
XX16
XX16
003616
003716
003816 DMA1 transfer counter
003916
TCR1
XX16
XX16
003A16
003B16
003C16 DMA1 control register
DM1CON
00000X002
003D16
003E16
003F16
NOTES:
1. The blank spaces are reserved. No access is allowed.
2. Bits CM27, CM21, and CM20 do not change at oscillation stop detection reset.
3. The WDC5 bit is 0 (cold start) immediately after power-on. It can only be set to 1 by program. The WDC5 bit cannot be used in
M16C/26T.
4. The VCR1 and VCR2 registers do not change at software reset, watchdog timer reset, and oscillation stop detection reset.
5. Registers VCR1, VCR2, and D4INT cannot be used in M16C/26T.
X : Undefined
page 20
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3. Memory
(1)
Table 4.2 SFR Information(2)
Address
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
Register
Symbol
INT3IC
After reset
XX00X000
INT3 interrupt control register
2
INT5 interrupt control register
INT4 interrupt control register
INT5IC
INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00X000
XX00X000
2
2
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
TimerA0 interrupt control register
TimerA1 interrupt control register
TimerA2 interrupt control register
TimerA3 interrupt control register
TimerA4 interrupt control register
TimerB0 interrupt control register
TimerB1 interrupt control register
TimerB2 interrupt control register
INT0 interrupt control register
XX00X000
XX00X000
XX00X000
2
INT1 interrupt control register
INT2 interrupt control register
2
2
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
NOTE:
1. Blank spaces are reserved. No access is allowed.
X: Undefined
page 21
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
3. Memory
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Table 4.3 SFR Information(3)
Address
008016
008116
008216
008316
008416
008516
008616
Register
Symbol
After reset
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash memory control register 4
(Note 2)
(Note 2)
(Note 2)
FMR4
FMR1
FMR0
010000002
Flash memory control register 1
Flash memory control register 0
000XXX0X
0116
2
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Three phase protect control register
TPRC
0016
On-chip oscillator control register
Pin assignment control register
Peripheral clock select register
ROCR
PACR
PCLKR
00000101
0016
00000011
2
2
~
~
~
~
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
NMI digital debounce register
NDDR
P17DDR
FF16
FF16
Port1
7
digital debounce register
NOTES:
1. Blank spaces are reserved. No access is allowed.
2. This register is included in the flash memory version.
X: Undefined
page 22
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3. Memory
(1)
Table 4.4 SFR Information(4)
Address
Register
Symbol
After reset
034016
034116
034216
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
3F16
3F16
Three phase PWM control register 0
Three phase PWM control register 1
Three phase output buffer register 0
Three phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
XX16
XX16
XXXX0000
Timer B2 Interrupt occurrence frequency set counter
Position-data-retain function control register
ICTB2
PDRF
2
Port function control register
PFCR
001111112
Interrupt request cause select register 2
Interrupt request cause select register
IFSR2A
IFSR
XXXXXXX0
0016
2
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate register
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
X0000000
X0000000
0016
XX16
XXXXXXXX
XXXXXXXX
00001000
00000010
2
2
2
U2BRG
U2TB
UART2 transmit buffer register
2
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
2
2
XXXXXXXX
XXXXXXXX
2
2
NOTE:
1. Blank spaces are reserved. No access is allowed.
X : Undefined
page 23
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
3. Memory
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
(1)
Table 4.5 SFR Information(5)
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B216
03B316
03B416
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
Register
Symbol
After reset
Count start flag
TABSR
CPSRF
ONSF
TRGSR
UDF
0016
0XXXXXXX
0016
0016
0016
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-dowm flag
2
Timer A0 register
Timer A1 register
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Timer B2 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
XX16
0016
0016
0016
0016
0016
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00XX0000
00XX0000
00XX0000
2
2
2
Timer B2 special mode register
X00000002
UART0 transmit/receive mode register
UART0 bit rate register
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
XX16
XXXXXXXX
XXXXXXXX
2
2
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
2
2
XXXXXXXX
XXXXXXXX
0016
XX16
XXXXXXXX
2
2
UART1 transmit/receive mode register
UART1 bit rate register
UART1 transmit buffer register
U1MR
U1BRG
U1TB
2
2
XXXXXXXX
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
00001000
00000010
2
2
XXXXXXXX
XXXXXXXX
2
2
UART transmit/receive control register 2
UCON
X0000000
2
CRC snoop address register
CRC mode register
CRCSAR
CRCMR
DM0SL
DM1SL
CRCD
XX16
00XXXXXX
0XXXXXX0
2
2
DMA0 request cause select register
DMA1 request cause select register
CRC data register
0016
0016
XX16
XX16
XX16
CRC input register
CRCIN
NOTE:
1. Blank spaces are reserved. No access is allowed.
X : Undefined
page 24
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
3. Memory
(1)
Table 4.6 SFR Information(6)
Address
03C016 A/D register 0
Register
Symbol
AD0
After Reset
XXXXXXXX
2
03C116
XXXXXXXX
2
03C216 A/D register 1
03C316
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXXXXXXX2
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
2
2
2
2
2
2
2
2
2
2
2
2
2
03C416 A/D register 2
03C516
03C616 A/D register 3
03C716
03C816 A/D register 4
03C916
03CA16 A/D register 5
03CB16
03CC16 A/D register 6
03CD16
03CE16 A/D register 7
03CF16
03D016
03D116
03D216 A/D trigger control register
03D316 A/D status register 0
03D416 A/D control register 2
ADTRGCON
ADSTAT0
ADCON2
0016
00000X00
0016
2
03D516
03D616 A/D control register 0
03D716 A/D control register 1
ADCON0
ADCON1
00000XXX
0016
2
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
Port P1 register
P1
XX16
0016
03E216
03E316
Port P1 direction register
PD1
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
P6
P7
PD6
PD7
P8
XX16
XX16
0016
0016
XX16
03ED16
03EE16
03EF16
03F016
Port P8 register
03F116
Port P9 register
Port P8 direction register
Port P9 direction register
Port P10 register
P9
XXXXXXXX
0016
2
03F216
PD8
PD9
P10
03F316
XXXX0000
XX16
2
03F416
03F516
03F616
Port P10 direction register
PD10
0016
03F716
03F816
03F916
03FA16
03FB16
03FC16
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
03FD16
03FE16
03FF16
NOTE:
1. Blank spaces are reserved. No access is allowed.
X: Undefined
page 25
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
Package
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)
Package
JEITA Package Code
P-LQFP48-7x7-0.50
RENESAS Code
PLQP0048KB-A
Previous Code
48P6Q-A
MASS[Typ.]
0.2g
HD
*1
D
36
25
NOTE)
1. DIMENSIONS " 1" AND " 2"
37
24
2. DIMENSION " 3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
D
E
Terminal cross section
48
13
A
HD
8.8 9.0 9.2
8.8
E
1
12
1.7
0.1 0.2
0.17 0.22 0.27
0.20
Index mark
ZD
A1
0
F
p
b1
c
0.145
0.125
0.09
0.20
L
c1
L1
0
8
e
x
0.5
y
*3
Detail F
0.08
0.10
p
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
JEITA Package Code
RENESAS Code
PRSP0042GA-B
Previous Code
42P2R-E
MASS[Typ.]
0.6g
P-SSOP42-8.4x17.5-0.80
42
F
NOTE)
1. DIMENSIONS "1" AND "2"
2. DIMENSION " 3" DOES NOT
INCLUDE TRIM OFFSET.
1
A2
A1
Index mark
Reference
Symbol
*2
Min Nom Max
D
D
E
17.3 17.5 17.7
8.2 8.4 8.6
A2
A
2.0
2.4
A1
bp
c
0.05
0.25
0.13 0.15
bp
e
y
0.3 0.4
Detail F
0.2
HE
e
y
11.63 11.93 12.23
0.8
0.65
0.95
0.15
0.3 0.5 0.7
L
page 26
Rev. 0.51 Jul.25, 2006
REJ03B0071-0051
of 26
REVISION HISTORY
M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Shortsheet
Rev.
Date
Description
Summary
Page
-
0.51 07/25/06
First edition
A-1
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
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Tel: <65> 6213-0200, Fax: <65> 6278-8001
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Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .6.0
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