M30281F6HP-D5 [RENESAS]
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64;
| 型号： | M30281F6HP-D5 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 时钟 外围集成电路 |
| 文件： | 总28页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M16C/28 Group
REJ03B0026-0040Z
Rev.0.40
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2004.06.15
1. Overview
The M16C/28 group of single-chip microcomputers is built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and is packaged in a 64-pin and 80-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and a DMAC which combined with fast instruction pro-
cessing capability, makes it suitable for control of various OA, communication, and industrial equipment
which requires high-speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, office/communications/portable/industrial equipment,
home appliances (inverter solution), etc
Specifications written in this manual are believed to be accurate, but are
not guaranteed to be entirely free of error. Specifications in this manual
may be changed for functional or performance improvements. Please make
sure your manual is the latest edition.
Rev.0.40 2004.06.15 page 1 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.2 Performance Outline
Table 1.2.1 lists performance outline of M16C/28 group 80-pin device.
Table 1.2.2 lists performance outline of M16C/28 group 64-pin device.
Table 1.2.1. Performance outline of M16C/28 group (80-pin device)
Item
Performance
Number of basic instructions
Shortest instruction execution time
91 instructions
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C)
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C)
(See the product list)
(Normal-ver./T-ver.)
(Normal-ver.)
(V-ver.)
(V-ver.)
Memory
capacity
I/O port
ROM
RAM
(See the product list)
71 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
:
16bit base timer x 1 channel (Input/Output x 8 channels)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
2
1
2
UART, clock synchronous, I C bus , or IEBus
2 channels (SI/O3, SI/O4)
Clock synchronous
1 channel (Multi-Master I C bus )
2
1
A/D converter
DMAC
10 bits x 24 channels(Normal-ver.) 27channels(T-ver./V-ver.)
2 channels (trigger: 31 sources)
CRC calcuration circuit
Watchdog timer
Interrupt
2 polynomial (CRC-CCiTT and CRC-16) with MSB/LSB selectable(T-ver./V-ver.)
15 bits x 1 (with prescaler)
25 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Clock generation circuit
(These circuits contain a built-in feedback
• Main clock
resistor and external ceramic/quartz oscillator)
• Sub-clock
•
On-chip oscillator (main-clock oscillation stop detect function)
• PLL frequency synthesizer
Low voltage detection circuit
Power supply voltage
Available (Normal-ver.) Not available (T-ver./V-ver.)
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
(Normal-ver.)
(T-ver.)
(V-ver.)
VCC=4.2V to 5.5V
Flash memory Program/erase voltage
Number of program/erase
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
100 times ( Block A ,Block B : 10,000 times(option ) )
3
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, in wait mode)
0.7 µA (Vcc=3V, when stop mode)
4
Operating ambient temperature
Package
-20 to 85°C / -40 to 85°C
-40 to 85°C
(Normal-ver.)
(T-ver.)
-40 to 105°C / -40 to 125°C
80-pin plastic mold QFP
(V-ver.)
Notes:
2
1. I C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option,please so specify.
4. See Table 1.4.4 for the operating ambient temperature.
Rev.0.40 2004.06.15 page 2 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.2.2. Performance outline of M16C/28 group (64-pin device)
Item
Performance
Number of basic instructions
Shortest instruction execution time
91 instructions
50 ns (f(BCLK)= 20MHZ, VCC= 3.0V to 5.5V)
100 ns (f(BCLK)= 10MHZ, VCC= 2.7V to 5.5V)
50 ns (f(BCLK)= 20MHZ, VCC= 4.2V to 5.5V -40 to 105°C)
62.5 ns (f(BCLK)= 16MHZ, VCC= 4.2V to 5.5V -40 to 125°C)
(See the product list)
(Normal-ver./T-ver.)
(Normal-ver.)
(V-ver.)
(V-ver.)
Memory
capacity
I/O port
ROM
RAM
(See the product list)
55 lines
Multifunction timer
TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels
Three-phase Motor Control Timer
TimerS (Input Capture/Output Compare)
: 16bit base timer x 1 channel (Input/Output x 8 channels
)
Serial I/O
2 channels (UART0, UART1)
UART, clock synchronous
1 channel (UART2)
2
1
2
UART, clock synchronous, I C bus , or IEBus
1 channel (SI/O3)
Clock synchronous
1 channel (Multi-Master I C bus )
2
1
A/D converter
DMAC
10 bits x 13 channels(Normal-ver.) 16 channels(T-ver./V-ver.)
2 channels (trigger: 30 sources)
CRC calcuration circuit
Watchdog timer
Interrupt
2 polynomial (CRC-CCiTT and CRC-16) with MSB/LSB selectable(T-ver./V-ver.)
15 bits x 1 (with prescaler)
24 internal and 8 external sources, 4 software sources, 7 levels
4 circuits
Clock generation circuit
(These circuits contain a built-in feedback
resistor and external ceramic/quartz oscillator)
• Sub-clock
On-chip oscillator (main-clock oscillation stop detect function)
• Main clock
•
• PLL frequency synthesizer
Low voltage detection circuit
Power supply voltage
Available (Normal-ver.) Not available (T-ver./V-ver.)
VCC=3.0V to 5.5V (f(BCLK)=20MHZ)
VCC=2.7V to 5.5V (f(BCLK)=10MHZ)
VCC=3.0V to 5.5V
(Normal-ver.)
(T-ver.)
(V-ver.)
VCC=4.2V to 5.5V
Flash memory Program/erase voltage
Number of program/erase
2.7V to 5.5V (Normal-ver.) 3.0V to 5.5V (T-ver.) 4.2V to 5.5V (V-ver.)
100 times ( Block A ,Block B : 10,000 times (option ) )
3
Power consumption
16mA (Vcc=5V, f(BCLK)=20MHz)
25 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz on RAM)
1.8 µA (Vcc=3V, f(BCLK)=f(XCIN)=32KHz, in wait mode)
0.7 µA (Vcc=3V, when stop mode)
4
Operating ambient temperature
Package
-20 to 85°C / -40 to 85°C
-40 to 85°C
(Normal-ver.)
(T-ver.)
-40 to 105°C / -40 to 125°C
64-pin plastic mold QFP
(V-ver.)
Notes:
2
1. I C bus is a trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a trademark of NEC Electronics Corporation.
3. If you desire this option,please so specify.
4. See Table 1.4.4 for the operating ambient temperature.
Rev.0.40 2004.06.15 page 3 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.3 Block Diagram
Figure 1.3.1 is a block diagram of the M16C/28 group, 80-pin device.
8
8
8
8
8
8
8
7
8
I/O
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Ports
Internal Peripheral Functions
Timer
Timer S
Serial Ports
System Clock Generator
Timer A0 (16 bits)
U(S)ART/SIO (channel 0)
Xin-Xout
Xcin-Xcout
PLL frequency synthesizer
Input Capture (8 channels)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I2C bus/IEBus
(channel 2)
Output Compare (8 channels)
On-chip Oscillator
A/D converter
(10bits x 24 channels(Normal-ver.))
(10bits x 27 channels(T-ver./V-ver.))
SIO (channel 3)
Watchdog Timer
SIO (channel 4)
Multi-master I2C bus
3-phase PWM
DMAC (2 channels)
CRC arithmetic circuit
(CCITT, CRC-16)(T-ver./V-ver.)
M16C/60 series 16-bit CPU Core
Memory
Program Counter
PC
Flash ROM
Registers
R0H
R0H
R1H
R0L
R0L
R1L
Stack Pointers
ISP
Flash ROM
(Data Flash)
R2
R3
A0
A1
FB
USP
Vector Table
INTB
RAM
Flag Register
FLG
Multiplier
SB
Figure 1.3.1. M16C/28 Group, 80-pin Block Diagram
Rev.0.40 2004.06.15 page 4 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Figure 1.3.2 is a block diagram of the M16C/28 group, 64-pin device.
4
3
8
4
8
8
8
4
8
I/O
Port P0
Port P1
Port P2
Port P3
Port P6
Port P7
Port P8
Port P9
Port P10
Ports
Internal Peripheral Functions
Timer
Timer S
Serial Ports
System Clock Generator
Timer A0 (16 bits)
U(S)ART/SIO (channel 0)
Xin-Xout
Xcin-Xcout
PLL frequency synthesizer
Input Capture (8 channels)
Timer A1 (16 bits)
Timer A2 (16 bits)
Timer A3 (16 bits)
Timer A4 (16 bits)
Timer B0 (16 bits)
Timer B1 (16 bits)
Timer B2 (16 bits)
U(S)ART/SIO (channel 1)
U(S)ART/SIO/I2C bus/IEBus
(channel 2)
Output Compare (8 channels)
On-chip Oscillator
A/D converter
(10bits x 13 channels(Normal-ver.))
(10bits x 16 channels(T-ver./V-ver.))
SIO (channel 3)
Watchdog Timer
Multi-master I2C bus
3-phase PWM
DMAC (2 channels)
CRC arithmetic circuit
(CCITT, CRC-16)(T-ver./V-ver.)
M16C/60 series 16-bit CPU Core
Memory
Program Counter
PC
Flash ROM
Registers
R0H
R0H
R1H
R0L
R0L
R1L
Stack Pointers
ISP
Flash ROM
(Data Flash)
R2
R3
A0
A1
FB
USP
Vector Table
INTB
RAM
Flag Register
FLG
Multiplier
SB
Figure 1.3.2. M16C/28 Group, 64-pin Block Diagram
Rev.0.40 2004.06.15 page 5 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.4 Product List
Tables 1.4.1 to 1.4.3 list the M16C/28 group products and Figure 1.4.1 shows the type numbers, memory
sizes and packages.
Table 1.4.1. Product List (1) -Normal-ver.
As of Jun 2004
Type No.
M30280F6HP
ROM capacity
(D) 48K + 4K byte
(D) 64K + 4K byte
(D) 96K + 4K byte
(D) 48K + 4K byte
(D) 64K + 4K byte
(D) 96K + 4K byte
(P) 64K byte
RAM capacity
4K byte
4K byte
8K byte
4K byte
4K byte
8K byte
4K byte
8K byte
4K byte
8K byte
Package type
80P6Q-A
Remarks
M30280F8HP
M30280FAHP
Flash ROM Version
Mask ROM Version
M30281F6HP
M30281F8HP
64P6Q-A
M30281FAHP
M30280M8-XXXHP
M30280MA-XXXHP
M30281M8-XXXHP
M30281MA-XXXHP
(P) : under planning
80P6Q-A
64P6Q-A
(P) 96K byte
(P) 64K byte
(P) 96K byte
(D) : under development
Table 1.4.2. Product List (2) -T-ver.
Type No. ROM capacity
M30280FATHP
M30281FATHP
As of Jun 2004
RAM capacity
8K byte
Package type
80P6Q-A
Remarks
(D) 96K + 4K byte
(D) 96K + 4K byte
Flash ROM Version
Mask ROM Version
8K byte
64P6Q-A
M30280M8T-XXXHP (P) 64K byte
M30280MAT-XXXHP (P) 96K byte
M30281M8T-XXXHP (P) 64K byte
M30281MAT-XXXHP (P) 96K byte
4K byte
80P6Q-A
64P6Q-A
8K byte
4K byte
4K byte
(P) : under planning
(D) : under development
NOTES: Specification of T-ver. partly varies from the one of Normal-ver.
Table 1.4.3. Product List (3) -V-ver.
As of Jun 2004
Type No.
M30280FAVHP
M30281FAVHP
ROM capacity
(D) 96K + 4K byte
(D) 96K + 4K byte
RAM capacity
8K byte
Package type
80P6Q-A
Remarks
Flash ROM Version
Mask ROM Version
8K byte
64P6Q-A
M30280M8V-XXXHP (P) 64K byte
M30280MAV-XXXHP (P) 96K byte
M30281M8V-XXXHP (P) 64K byte
M30281MAV-XXXHP (P) 96K byte
4K byte
80P6Q-A
64P6Q-A
8K byte
4K byte
8K byte
(P) : under planning
(D) : under development
NOTES: Specification of V-ver. partly varies from the one of Normal-ver.
Rev.0.40 2004.06.15 page 6 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Type No.
M 3 0 2 8 0 F 8 T H P - D3
Product code
Package type:
HP : Package 80P6Q, 64P6Q
Version:
(no): Normal-ver.
T
V
: T-ver.
: V-ver.
ROM capacity / RAM capacity:
6: (48K+4K) bytes (Note 1)/4K bytes
8: (64K+4K) bytes (Note 1)/4K bytes
A: (96K+4K) bytes (Note 1)/8K bytes
Note 1: Only flash memory version exists in "+4K bytes"
Memory type:
M: Mask ROM version
F: Flash memory version
Shows pin count
(The value itself has no specific meaning)
M16C/28 Group
M16C Family
Figure 1.4.1. Type No., Memory Size, and Package
Table 1.4.4. Product code (Flash memory version, Normal-ver.)
Internal ROM Block (0 to 4)
Internal ROM Block (A, B)
Microcomputer
Product
Code
operating
Package
Temperature
E/W cycles
Temperature
range
temperature
E/W cycles
100
range
D3
D5
D7
D9
U3
U5
U7
U9
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
100
0°C to 60°C
non-LEAD
free
-40°C to 85°C
-20°C to 85°C
10,000
100
1,000
0°C to 60°C
100
0°C to 60°C
LEAD free
-40°C to 85°C
1,000
10,000
-20°C to 85°C -20°C to 85°C
Rev.0.40 2004.06.15 page 7 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
(1) Flash ROM Version, 80P6Q-A, Normal-ver.
M16C
M30280FAHP
Product Name : indicates M30280FAHP
Chip Version and Product Code:
A D3
XXXXXXX
A
indicates chip version (Note 1)
The first edition is shown to be blank and continues
with A and B.
D3
indicates product code (see Table 1.4.4)
Date Code (7 digits)
indicates manufacturing management code
(2) Flash ROM Version, 64P6Q-A, Normal-ver.
30281FA
A D3
Product Name : indicates M30281FAHP
Chip Version and Product Code:
A
indicates chip version (Note 1)
The first edition is shown to be blank and continues
with A and B.
XXXXXXX
D3
indicates product code (see Table 1.4.4)
Date Code (7 digits)
indicates manufacturing management code
Note 1. The product of the first edition and version A do not support
the following functions
Delayed trigger mode 0 of A/D conversion
Delayed trigger mode 1 of A/D conversion
Figure 1.4.2. Product Marking (top view)
Rev.0.40 2004.06.15 page 8 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.5 Pin Configuration
Figures 1.5.1 and 1.5.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
P63/TXD0
P06/AN06
61
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P30/CLK3
P05/AN05
P04/AN04
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P31/SIN3
P32/SOUT3
P03/AN03
P02/AN02
P33
P01/AN01
P34
P35
P00/AN00
P36
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P37
P64/RTS1/CTS1/CTS0/CLKS1
P65/CLK1
P66/RXD1
P103/AN3
P102/AN2
P67/TXD1
P70/TXD2/SDA/TA0OUT
P101/AN1
{
/RTS1/CTS
1/CTS0/CLKS1
P71/RXD2/SCL/TA 0IN/CLK1
P72/CLK2/TA1OUT/V/RXD1
P73/CTS2/RTS2/TA1IN/V/TXD1
P74/TA2OUT/W
AVss
P100/AN0
VREF
AVcc
P97/AN27/SIN4
P75/TA2IN/W
P96/AN26/SOUT4
P76/TA3OUT
Package: 80P6Q-A
Note 1. Set PACR2 to PACR0 bit in the PACR register to "0112" before you input and output
it after resetting to each pin. When the PACR register isn’t set up, the input and output
function of some of the pins are disabled.
Note 2. The 3 to 5 pins are shown as P92/TB2IN, P91/TB1IN and P90/TB0IN for Normal-ver.
Figure 1.5.1. Pin Configuration (Top View) of M16C/28 Group, 80-pin Package
Rev.0.40 2004.06.15 page 9 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
PIN CONFIGURATION (top view)
P02/AN02
P01/AN01
P30/CLK3
P31/SIN3
P32/SOUT3
P33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
0
P0 /AN00
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P103/AN3
P64/RTS1/CTS1/CTS0/CLKS1
P65/CLK1
P66/RXD1
P67/TXD1
P70/TXD2/SDA/TA0OUT
P102/AN2
{
/RTS1/CTS1/CTS0/CLKS1
P101/AN1
P71/RXD2/SCL/TA0IN/CLK1
P72/CLK2/TA1OUT/V/RXD1
P73/CTS2/RTS2/TA1IN/V/TXD1
AVss
59
60
61
62
63
64
P100/AN0
P74/TA2OUT/W
P75/TA2IN/W
P76/TA3OUT
P77/TA3IN
VREF
AVcc
P93/AN24
P9 /AN32/TB
2IN(Note 2)
2
Package: 64P6Q-A
Note1. Set PACR2 to PACR0 bit in the PACR register to "0102" before you input and output
it after resetting to each pin. When the PACR register isn’t set up, the input and output
function of some of the pins are disabled.
Note 2. The 64, 1 and 2 pins are shown as P92/TB2IN, P91/TB1IN and P90/TB0IN for Normal-ver.
Figure 1.5.2. Pin Configuration (Top View) of M16C/28 Group, 64-pin Package
Rev.0.40 2004.06.15 page 10 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
1.6 Pin Description
Table 1.6.1 and 1.6.2 describes the available pins.
Table 1.6.1 Pin Description(1)
Pin name Signal name
I/O type
Function
VCC,VSS
Power supply
input
Apply 0V to the Vss pin, and the following voltage to the Vcc pin.
2.7 to 5.5V (Normal-ver.)
3.0 to 5.5V (T-ver.)
4.2 to 5.5V (V-ver.)
CNVSS
CNVSS
Input
Connect this pin to Vss.
____________
RESET
XIN
Reset input
Clock input
Clock output
Input
"L" on this input resets the microcomputer.
These pins are provided for the main clock generating circuit input/
output. Connect a ceramic resonator or crystal between the XIN and
the XOUT pins. To use an externally derived clock, input it to the XIN
pin and leave the XOUT pin open. If XIN is not used (for external
oscillator or external clock) connect XIN pin to VCC and leave XOUT
pin open.
Input
XOUT
Output
AVCC
Analog power
supply input
Analog power
supply input
Reference
This pin is a power supply input for the A/D converter. Connect this
pin to VCC.
AVSS
This pin is a power supply input for the A/D converter. Connect this
pin to VSS.
VREF
Input
This pin is a reference voltage input for the A/D converter.
Voltage input
I/O port P0
P00~P07
Input/output
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input, a pull-up resister option can be
selected for the entire group of four pins.Software can also select
this port to function as A/D converter input pins. P04~P07 are not
available in the 64 pin version.
P10~P17
I/O port P1
Input/output
This is an 8-bit I/O port equivalent to P0. Additional software-select
able secondary functions are: 1) P10 to P13 can act as A/D converter
input pins; 2) P15 to P17 can be configured as external interrupt pins;
3) P15 to P17 can be configured as position-data-retain function
input pins,and; 4) P15 can input a trigger for the A/D converter.
P10~P14 are not available in the 64 pin version.
P20~P27
P30~P37
I/O port P2
I/O port P3
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. Software can also select
this port to perform as I/O for the Timer S (all pins), and MultiMaster
2
I C Bus (P20 and P21 only)
This is an 8-bit I/O port equivalent to P0. P30 to P32 also function as
SIO3 I/O, as selected by software. P34~P37 are not available in the
64 pin version.
P60~P67
P70~P77
I/O port P6
I/O port P7
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also func-
tion as UART0 and UART1 I/O, as selected by software.
This is an 8-bit I/O port equivalent to P0. P7 can also function as I/O
for timer A0-A3, as selected by software. Additional programming
options are: P70 to P73 can assume UART1 or UART2 I/O capa-
bilities, and P72 to P75 can function as output pins for the three-
phase motor control timer.
Rev.0.40 2004.06.15 page 11 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
1. Overview
Table 1.6.2 Pin Description(2)
Pin name Signal name I/O type
I/O port P8
Function
P80~P87
Input/output
This is an 8-bit I/O port equivalent to P0. Additional software-select
able secondary functions are: 1) P80 and P81 can act as either I/O
for Timer A4, or as output pins for the three-phase motor control
timer; 2) P82 to P84 can be configured as external interrupt pins.
P84 can be used for Timer A Zphase function; 3) P85 can be used
_______ _____
as NMI/SD. P85 can not be used as I/O port while the three-phase
motor control is enabled. Apply a stable "H" to P85 after setting the
direction register for P85 to "0" when the three-phase motor control
is enabled, and; 4) P86 and P87 can serve as I/O pins for the
sub-clock generation circuit. In this latter case, a quartz oscillator
must be connented between P86 (XCOUT pin) and P87 (XCIN pin).
This is an 7-bit I/O port equivalent to P0. Additional software-select
able secondary functions are: 1) P90 to P92 can act as Timer B0~B2
input pins, or as A/D converter input pins for T-ver./V-ver.; 2) P90
outputs a no division, divide-by-8 or divide-by-32 clock of XIN or a
clock of the same frequency as XCIN as selected by program for
T-ver./V-ver.; 3) P93, P95 to P97 can act as A/D converter input pins,
and; 4) P95 to P97 can assume SI/O4 I/O.
P90~P93, I/O port P9
P95~P97
Input/output
P95 to P97 are not available in the 64 pin version.
P100~P107 I/O port P10
Input/output
This is an 8-bit I/O port equivalent to P0. This port can also function
as A/D converter input pins, as selected by software. Furthermore,
P104-P107 can also function as input pins for the key input interrupt
function.
Rev.0.40 2004.06.15 page 12 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
2. Central Processing Unit(CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H(R0's high bits) R0L(R0's low bits)
R1H(R1's high bits)R1L(R1's low bits)
Data registers (Note)
R2
R3
A0
A1
FB
Address registers (Note)
Frame base registers (Note)
b19
b15
b0
INTBH
INTBL
Interrupt table register
Program counter
The upper 4 bits of INTB are INTBH and
the lower 16 bits of INTB are INTBL.
b19
b0
b0
PC
b15
USP
User stack pointer
Interrupt stack pointer
Static base register
ISP
SB
b15
b0
b0
FLG
Flag register
b15
b8 b7
IPL
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note: These registers comprise a register bank. There are two register banks.
Figure 2.1. Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-
bit data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Rev.0.40 2004.06.15 page 13 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
2. Central Processing Unit(CPU)
M16C/28 Group
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”
.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I
flag is cleared to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for
software interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from
level 0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write "0". When read, its content is indeterminate.
Rev.0.40 2004.06.15 page 14 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
3. Memory
M16C/28 Group
3. Memory
Figure 3.1 is a memory map of the M16C/28 group. The linear address space of 1M bytes extends from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30280F8HP,there are
64 Kbytes of internal ROM from F000016 to FFFFF16.
The vector table for fixed interrupts, such as Reset and NMI, is mapped from FFFDC16 to FFFFF16. The
starting address of the interrupt routine is stored here.
The address of the vector table for timer interrupts,etc.,can be set as desired using the interrupt table
register(INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30280FAHP, 4K bytes of internal RAM is mapped to the
space from 0040016 to 013FF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
These devices also contain two blocks of Flash ROM as Data Flash memory to store data. These two
blocks of 2K bytes are located from 0F00016 to 0FFFF16 on all versions.
The SFR area is mapped from 0000016 to 003FF16. This area accommodates the control registers for
peripheral devices such as I/O ports, A/D converter, serial I/O, and timers, etc. Any part of the SFR area
that is not occupied is reserved and cannot be used for other purposes.
The special page vector table is allocated to the address from FFE0016 to FFFDB16. This vector is used by
the JMPS or JSRS instruction. For details, refer to the "M16C/60 and M16C/20 Series Software Manual".
Internal RAM area
Internal ROM area
Memory size
Memory size
XXXXX16
013FF16
023FF16
YYYYY16
F400016
F000016
E800016
4K byte
8K byte
48K byte
0000016
0040016
64K byte
96K byte
SFR area
Internal RAM area
FFE0016
FFFDC16
FFFFF16
XXXXX16
0F00016
0FFFF16
RESERVED
Special page
vector table
Internal ROM area
(data area)
(Note1)
Undefined instruction
Overflow
RESERVED
BRK instruction
Address match
Single step
Watchdog timer
YYYYY16
FFFFF16
DBC
Internal ROM area
(program area)
(Note2)
NMI
Reset
Note 1 : The block A (2K bytes) and block B (2K bytes) are shown
(only flash memory)
Note 2 : When using the masked ROM version, write nothing to
internal ROM area.
Figure 3.1. Memory Map
Rev.0.40 2004.06.15 page 15 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
4. Special Function Register (SFR) Map
Address
Register Name
Acronym
Value after Reset
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
Processor mode register 0
Processor mode register 1
System clock control register 0
System clock control register 1
PM0
PM1
CM0
CM1
0016
00001000
01001000
00100000
2
2
2
Address match interrupt enable register
Protect register
AIER
PRCR
XXXXXX00
XX000000
2
2
Oscillation stop detection register
(Note 2)
CM2
0X000010
2
Watchdog timer start register
Watchdog timer control register
Address match interrupt register 0
WDTS
WDC
RMAD0
??16
00??????
0016
0016
2(Note 3)
X016
Address match interrupt register 1
RMAD1
0016
0016
X016
Voltage detection register 1
Voltage detection register 2
(Note 4,5)
(Note 4,5)
VCR1
VCR2
00001000
0016
2
PLL control register 0
PLC0
0001X0102
Processor mode register 2
Voltage down detection interrupt register
DMA0 source pointer
PM2
D4INT
SAR0
XXX00000
0016
??16
2
001F16
002016
(Note 5)
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
??16
X?16
DMA0 destination pointer
DMA0 transfer counter
DMA0 control register
DMA1 source pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 control register
DAR0
TCR0
??16
??16
X?16
??16
??16
DM0CON
SAR1
00000?002
??16
??16
X?16
DAR1
??16
??16
X?16
TCR1
??16
??16
DM1CON
00000?002
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
Note 3: Tjhe WDC5 bit is "0" (cold start) immediately after power-on. It can only be set to "1" in a program. It is set to "0" when the input
voltage at the Vcc pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to "1"(RAM retention limit detection
circuit enable).
Note 4: This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
Note 5: This register can not use for T-ver. and V-ver.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.1. SFR Map (1 of 7)
Rev.0.40 2004.06.15 page 16 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Value after Reset
Address
004016
004116
004216
004316
004416
Acronym
INT3 interrupt control register
INT3IC
ICOC0IC
ICOC1IC, IICIC
BTIC, SCLDAIC
S4IC, INT5IC
S3IC, INT4IC
BCNIC
XX00?0002
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
IC/OC 0 interrupt control register
XXXX?000
XXXX?000
XXXX?000
2
2
2
IC/OC 1 interrupt control register, I2C-BUS interface interrupt control register
IC/OC base timer interrupt control register, SCLSDA interrupt control register
SI/O4 interrupt control register, INT5 interrupt control register
SI/O3 interrupt control register, INT4 interrupt control register
UART2 Bus collision detection interrupt control register
DMA0 interrupt control register
DMA1 interrupt control register
Key input interrupt control register
A/D conversion interrupt control register
UART2 transmit interrupt control register
UART2 receive interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
XX00?000
XX00?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
XXXX?000
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DM0IC
DM1IC
KUPIC
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
INT0IC
INT1IC
INT2IC
XX00?000
XX00?000
XX00?000
2
2
2
INT1 interrupt control register
INT2 interrupt control register
006016
006116
006216
006316
006416
006516
006616
006716
006816
006916
006A16
006B16
006C16
006D16
006E16
006F16
007016
007116
007216
007316
007416
007516
007616
007716
007816
007916
007A16
007B16
007C16
007D16
007E16
007F16
Note 1: The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.2. SFR Map (2 of 7)
Rev.0.40 2004.06.15 page 17 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
Address
008016
008116
008216
008316
008416
008516
008616
~
~
~
~
01B016
01B116
01B216
01B316
01B416
01B516
01B616
01B716
01B816
01B916
01BA16
01BB16
01BC16
01BD16
01BE16
01BF16
Flash memory control register 4
Flash memory control register 1
Flash memory control register 0
(Note 2)
(Note 2)
(Note 2)
FMR4
FMR1
FMR0
01000000
000???0?
0116
2
2
~
~
~
~
025016
025116
025216
025316
025416
025516
025616
025716
025816
025916
025A16
025B16
025C16
025D16
025E16
025F16
Three-phase protect control register
(Note 3)
TPRC
0016
On-chip oscillator control register
Pin assignment control register
Peripheral clock select register
ROCR
PACR
PCLKR
00000101
0016
00000011
2
2
~
~
~
~
I2C0 data shift register
S00
??16
02E016
02E116
02E216
02E316
02E416
02E516
02E616
02E716
02E816
02E916
02EA16
I2C0 address register
S0D0
S1D0
S20
S2D0
S3D0
S4D0
S10
0016
0016
0016
00011010
00110000
0016
I2C0 control register 0
I2C0 clock control register
I2C0 start/stop condition control register
I2C0 control register 1
2
2
I2C0 control register 2
I2C0 status register
0001000X2
~
~
~
~
02FE16
02FF16
Note 1:The blank areas are reserved and cannot be accessed by users.
Note 2:This register is included in the flash memory version.
Note 3:This register is included in T-ver. and V-ver.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.3. SFR Map (3 of 7)
Rev.0.40 2004.06.15 page 18 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
Address
030016
TM, WG register 0
TM, WG register 1
TM, WG register 2
TM, WG register 3
TM, WG register 4
TM, WG register 5
TM, WG register 6
TM, WG register 7
G1TM0,G1PO0
G1TM1,G1PO1
G1TM2,G1PO2
G1TM3,G1PO3
G1TM4,G1PO4
G1TM5,G1PO5
G1TM6,G1PO6
G1TM7,G1PO7
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0X00XX00
0016
030116
030216
030316
030416
030516
030616
030716
030816
030916
030A16
030B16
030C16
030D16
030E16
030F16
031016
031116
031216
031316
031416
031516
031616
031716
031816
031916
031A16
031B16
031C16
031D16
031E16
031F16
WG control register 0
WG control register 1
WG control register 2
WG control register 3
WG control register 4
WG control register 5
WG control register 6
WG control register 7
TM control register 0
TM control register 1
TM control register 2
TM control register 3
TM control register 4
TM control register 5
TM control register 6
TM control register 7
Base timer register
G1POCR0
G1POCR1
G1POCR2
G1POCR3
G1POCR4
G1POCR5
G1POCR6
G1POCR7
G1TMCR0
G1TMCR1
G1TMCR2
G1TMCR3
G1TMCR4
G1TMCR5
G1TMCR6
G1TMCR7
G1BT
2
2
2
2
2
2
2
2
0016
0016
0016
0016
0016
0016
0016
??16
032016
032116
032216
032316
032416
032516
032616
032716
032816
032916
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
??16
0016
0016
0016
0016
0016
0016
??16
Base timer control register 0
Base timer control register 1
TM prescale register 6
G1BCR0
G1BCR1
G1TPR6
G1TPR7
G1FE
TM prescale register 7
Function enable register
Function select register
Base timer reset register
G1FS
G1BTRR
??16
0016
Divider register
G1DV
Interrupt request register
Interrupt enable register 0
Interrupt enable register 1
G1IR
G1IE0
G1IE1
??16
0016
0016
NMI digital debounce register
P17 digital debounce register
NDDR
P17DDR
FF16
FF16
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.4. SFR Map (4 of 7)
Rev.0.40 2004.06.15 page 19 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
Address
034016
034116
034216
Timer A1-1 register
Timer A2-1 register
Timer A4-1 register
TA11
TA21
TA41
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
??16
X?16
034316
034416
034516
034616
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
035316
035416
035516
035616
035716
035816
035916
035A16
035B16
035C16
035D16
035E16
035F16
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
037516
037616
037716
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 interrupt occurrence frequency set counter
Position-data-retain function contol register
ICTB2
PDRF
XXXX0000
2
Port function control register
(Note 3)
PFCR
001111112
Interrupt request cause select register 2
Interrupt request cause select register
SI/O3 transmit/receive register
IFSR2A
IFSR
S3TRR
00XXXXX0
0016
??16
2 (Note 2)
SI/O3 control register
SI/O3 bit rate generator
SI/O4 transmit/receive register
S3C
S3BRG
S4TRR
01000000
??16
??16
2
2
SI/O4 control register
SI/O4 bit rate generator
S4C
S4BRG
01000000
??16
UART2 special mode register 4
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
UART2 transmit/receive mode register
UART2 bit rate generator
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
0016
000X0X0X
X0000000
X0000000
0016
??16
????????
XXXXXXX?
2
2
2
U2BRG
U2TB
UART2 transmit buffer register
2
2
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
UART2 receive buffer register
U2C0
U2C1
U2RB
00001000
00000010
????????
2
2
2
?????XX?
2
Note 1: The blank areas are reserved and cannot be accessed by users.
Note 2: Write "1" to bit 0 after reset.
Note 3:This register is included in T-ver. and V-ver.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.5. SFR Map (5 of 7)
Rev.0.40 2004.06.15 page 20 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Register Name
Acronym
Value after Reset
0016
Address
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
Count start flag
TABSR
CPSRF
ONSF
TRGSR
UDF
Clock prescaler reset flag
One-shot start flag
Trigger select register
Up-down flag
0XXXXXXX
2
0016
0016
0016
Timer A0 register
Timer A1 register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
??16
0016
0016
0016
0016
0016
038A16 Timer A2 register
038B16
038C16 Timer A3 register
038D16
038E16 Timer A4 register
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
Timer B0 register
Timer B1 register
Timer B2 register
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
039A16 Timer A4 mode register
039B16 Timer B0 mode register
039C16 Timer B1 mode register
039D16 Timer B2 mode register
039E16 Timer B2 special mode register
039F16
00??0000
2
00?X0000
00?X0000
X0000000
2
2
2
03A016
UART0 transmit/receive mode register
UART0 bit rate generator
UART0 transmit buffer register
U0MR
U0BRG
U0TB
0016
??16
????????
03A116
03A216
2
03A316
XXXXXXX?
2
03A416
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART0 receive buffer register
U0C0
U0C1
U0RB
00001000
00000010
????????
2
2
2
03A516
03A616
03A716
?????XX?
0016
??16
2
03A816
UART1 transmit/receive mode register
UART1 bit rate generator
UART1 transmit buffer register
U1MR
U1BRG
U1TB
03A916
03AA16
????????
2
03AB16
XXXXXXX?
2
03AC16
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART1 receive buffer register
U1C0
U1C1
U1RB
00001000
00000010
????????
2
2
2
03AD16
03AE16
03AF16
?????XX?
2
03B016
UART transmit/receive control register 2
UCON
X0000000
2
03B116
03B216
03B316
03B416
CRC snoop address register
(Note 2)
(Note 2)
CRCSAR
CRCMR
DM0SL
DM1SL
CRCD
??16
00XXXX??
0XXXXXX0
03B516
2
2
03B616
CRC mode register
03B716
03B816
DMA0 request cause select register
0016
0016
03B916
03BA16
DMA1 request cause select register
03BB16
03BC16
CRC data register
(Note 2)
(Note 2)
??16
??16
??16
03BD16
03BE16
CRC input register
CRCIN
03BF16
Note 1:The blank areas are reserved and cannot be accessed by users.
Note 2:This register is included in T-ver. and V-ver.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.6. SFR Map (6 of 7)
Rev.0.40 2004.06.15 page 21 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
4. Special Function Register (SFR) MAP
Address
Register Name
Acronym
Value after Reset
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
????????
XXXXXX??
03C016
A/D register 0
A/D register 1
A/D register 2
A/D register 3
A/D register 4
A/D register 5
A/D register 6
A/D register 7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
2
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A/D trigger control register
A/D convert status register 0
A/D control register 2
ADTRGCON
ADSTAT0
ADCON2
XXXX00002
00000X00
0016
2
A/D control register 0
A/D control register 1
ADCON0
ADCON1
00000???
0016
2
Port P0 register
Port P1 register
Port P0 direction register
Port P1 direction register
Port P2 register
Port P3 register
Port P2 direction register
Port P3 direction register
P0
P1
PD0
PD1
P2
P3
PD2
PD3
??16
??16
0016
0016
??16
??16
0016
0016
Port P6 register
Port P7 register
Port P6 direction register
Port P7 direction register
Port P8 register
P6
P7
PD6
PD7
P8
??16
??16
0016
0016
??16
Port P9 register
P9
???X????
0016
000X0000
??16
2
2
Port P8 direction register
Port P9 direction register
Port P10 register
PD8
PD9
P10
Port P10 direction register
PD10
0016
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
PUR0
PUR1
PUR2
PCR
0016
0016
0016
0016
Note 1:The blank areas are reserved and cannot be accessed by users.
X : Noting is mapped to this bit
? : Value indeterminate at reset
Figure 4.7. SFR Map (7 of 7)
Rev.0.40 2004.06.15 page 22 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/28 Group
5. Package
5. Package
Recommended
64P6Q-A
Plastic 64pin 10✕10mm body LQFP
EIAJ Package Code
LQFP64-P-1010-0.5
JEDEC Code
–
Weight(g)
Lead Material
Cu Alloy
MD
HD
D
48
33
I
2
Recommended Mount Pad
Dimension in Millimeters
49
32
Symbol
Min
–
0
Nom
–
0.1
Max
1.7
0.2
–
A
A
A
1
2
–
1.4
b
0.13
0.105
9.9
9.9
–
0.18
0.125
10.0
10.0
0.5
0.28
0.175
10.1
10.1
–
64
17
c
D
E
e
1
16
A
H
H
L
D
11.8
11.8
0.3
–
12.0
12.0
0.5
12.2
12.2
0.7
–
F
E
e
L1
1.0
L1
Lp
A3
x
0.45
–
–
–
0°
–
1.0
–
0.6
0.25
–
–
–
0.225
–
10.4
10.4
0.75
–
0.08
0.1
10°
–
–
–
–
y
y
L
b
b2
x
M
Lp
I
2
Detail F
M
M
D
E
–
Recommended
80P6Q-A
Plastic 80pin 12✕12mm body LQFP
EIAJ Package Code
LQFP80-P-1212-0.5
JEDEC Code
Weight(g)
0.47
Lead Material
Cu Alloy
M
D
–
HD
D
80
61
l
2
1
60
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0
0.1
2
–
1.4
b
0.13
0.105
11.9
11.9
–
0.18
0.125
12.0
12.0
0.5
0.28
0.175
12.1
12.1
–
c
D
E
e
20
41
21
40
H
H
L
D
13.8
13.8
0.3
–
0.45
–
–
–
0°
–
14.0
14.0
0.5
1.0
0.6
0.25
–
–
14.2
14.2
0.7
–
0.75
–
0.08
0.1
10°
–
A
E
L
1
F
L1
e
Lp
A3
x
y
–
b
y
x
M
L
b2
0.225
–
12.4
12.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
Rev.0.40 2004.06.15 page 23 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Functional differences
M16C/28 Group
6. Functional differences
6.1 Functional differences between Normal-ver. and T-ver./V-ver. of M16C/28 group(Note1)
Item
Detailed Item
M16C/28(Normal-ver.)
M16C/28(T-ver./V-ver.)
Available
Clock
Clock Output Function Not available
(b1-b0 bit of CM0 register) (reserved bit)
Voltage Detection Circuit Available
(Clock output function select bit)
Not available
Reset
(Function of 001916, 001A16, (Power supply detection register 1, (Reserved register)
001F16
)
Power supply detection register 2,
Power supply down detection
interrupt register)
Three-Phase Motor Three-phase/Port Output Not available
Control Timer Switch Function (035816) (Nothing is assigned)
Available
(Port function control register)
27 channels
A/D ConversionAnalog Input pins
24 channels
(AN30 to AN32 not available)
(AN30 to AN32 available)
Delayed trigger mode 0 The product of the first edition Available
and version A do not available
Delayed trigger mode 1 The product of the first edition Available
and version A do not available
CRC Calculation CRC-CCITT and CRC-16 Not available
Available
(Related registers are not assigned) (1 curcuit)
Pin Function
3 pin (80 pin version)
64 pin (64 pin version)
4 pin (80 pin version)
1 pin (64 pin version)
5 pin (80 pin version)
2 pin (64 pin version)
P92/TB2IN
P91/TB1IN
P90/TB0IN
P92/AN32/TB2IN
P91/AN31/TB1IN
P90/AN30/TB0IN/CLKOUT
Note 1. Since the emulator between the M16C/28 and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/28 group, do not access to the SFR which is not
built in M16C/28 group.
Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.40 2004.06.15 page 24 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Functional differences
M16C/28 Group
6.2 Functional differences between M16C/28 group and M16C/29 group (Normal-ver.) (Note 1)
Item
Detailed Item
M16C/28(Normal-ver.)
M16C/29(Normal-ver.)
Available
Clock
Clock Output Function Not available
(reserved bit)
(Clock output function select bit)
Enable write to CM0, CM1,
CM2, POCR, PLC0, PCLKR,
CCLKR registers
Protect
PRC0 bit function
Enable wrtite to CM0, CM1,
CM2, POCR, PLC0, PCLKR
registers
Interrupt
IFSR20 bit of IFSR2A
register
Must be set to "1"
Must be set to "0"
b1 bit of IFSR2A register Nothing is assigned
(When write, set to "0")
Interrupt request cause select bit
(0:A/D conversion 1:Key input)
Interrupt request cause select bit
(0:CAN0 wakeup/error)
CAN0 error
b2 bit of IFSR2A register Nothing is assigned
(When write, set to "0")
Interrupr source of software Key input interrupt
interrupt number 13
Interrupr source of software A/D conversion interrupt
interrupt number 14
A/D conversion/Key input interrupt
Three-Phase Motor Three-phase/Port Output Not available
Control Timer Switch Function (035816) (Nothing is assigned)
Available
(Port function control register)
27 channels
A/D Conversion Analog Input pins
24 channels
(AN30 to AN32 not available)
(AN30 to AN32 available)
Delayed trigger mode 0 The product of the first edition Available
and version A do not available
Delayed trigger mode 1 The product of the first edition Available
and version A do not available
CAN Module 2.0B BOSCH compliant Not available
Available
(Related registers are not assigned) (1channel)
CRC Calculation CRC-CCITT and CRC-16 Not available
Available
(Related registers are not assigned) (1 curcuit)
Pin Function
2 pin (80 pin version)
62 pin (64 pin version)
3 pin (80 pin version)
64 pin (64 pin version)
4 pin (80 pin version)
1 pin (64 pin version)
5 pin (80 pin version)
2 pin (64 pin version)
P93/AN24
P92/TB2IN
P91/TB1IN
P90/TB0IN
P93/AN24/CTX
P92/AN32/TB2IN/CRX
P91/AN31/TB1IN
P90/AN30/TB0IN/CLKOUT
Note 1. Since the emulator between the M16C/28 and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/28 group, do not access to the SFR which is not
built in M16C/28 group.
Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.40 2004.06.15 page 25 of 26
REJ03B0026-0040Z
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
6. Functional differences
M16C/28 Group
6.3 Functional differences between M16C/28 group and M16C/29 group (T-ver./V-ver.)(Note 1)
Item
Protect
Detailed Item
M16C/28(T-ver./V-ver.)
Enable wrtite to CM0, CM1,
CM2, POCR, PLC0, PCLKR
registers
M16C/29(T-ver./V-ver.)
Enable write to CM0, CM1,
CM2, POCR, PLC0, PCLKR,
CCLKR registers
PRC0 bit function
Interrupt
IFSR20 bit of IFSR2A
register
Must be set to "1"
Must be set to "0"
b1 bit of IFSR2A register Nothing is assigned
(When write, set to "0")
Interrupt request cause select bit
(0:A/D conversion 1:Key input)
Interrupt request cause select bit
(0:CAN0 wakeup/error)
CAN0 error
b2 bit of IFSR2A register Nothing is assigned
(When write, set to "0")
Interrupr source of software Key input interrupt
interrupt number 13
Interrupr source of software A/D conversion interrupt
interrupt number 14
A/D conversion/Key input interrupt
CAN Module 2.0B BOSCH compliant Not available
Available
(Related registers are not assigned) (1channel)
Pin Function
2 pin (80 pin version)
62 pin (64 pin version)
3 pin (80 pin version)
64 pin (64 pin version)
P93/AN24
P92/TB2IN
P93/AN24/CTX
P92/AN32/TB2IN/CRX
Note 1. Since the emulator between the M16C/28 and M16C/29 group are same, all functions of M16C/29
are built in the emulator. When evaluating M16C/28 group, do not access to the SFR which is not
built in M16C/28 group.
Refer to Hardware Manual about detail and electrical characteristics.
Rev.0.40 2004.06.15 page 26 of 26
REJ03B0026-0040Z
REVISION HISTORY
M16C/28 Short Sheet
Rev.
Date
Description
Summary
Page
0.20 Dec/ 01/ 03
0.40 Jun/15/04
First edition
2,3
4,5
6
Table 1.2.1 and 1.2.2 are partly revised, and integrated descriptions.
Figure 1.3.1 and 1.3.2 are integrated descriptions.
Table 1.4.1 to 1.4.3 are partly revised.
7
Figure 1.4.1 and Table 1.4.4 are partly revised.
Table 1.4.5 is deleted.
8
Figure 1.4.2 is added.
9, 10
11,12
15
Figure 1.5.1 and 1.5.2 are partly revised.
Table 1.6.1 and 1.6.2 are partly revised and integrated descriptions.
The Chapter ”3. Memory” and Figure 3.1 are integrated descriptions and partly r evised.
Note 2 in Figure 3.1 is revised.
16
17,18
18
Figure 4.1 is partly revised.
Figure 4.2 and 4.3 are integrated descriptions.
“Three-phase protect control register” is added.
Figure 4.4 and 4.5 are partly revised.
19,20
20
“Port function control register” is added.
Registers of the CRC arithmetic circuit are added.
Figure 4.7 is integrated descriptions.
21
22
23
64P6Q-A package is revised.
24 to 26 The Chapter “6. Functional differences” is added.
A-1
M16C/26A Group
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
相关型号：
M30281F6HP-D9
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
RENESAS
M30281F6HP-U5
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-64
RENESAS
M30281F6HP-U7
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-64
RENESAS
M30281F6HP-U9
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-64
RENESAS
M30281F6THP
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
RENESAS
M30281F8HP-D5
16-BIT, FLASH, 20MHz, MICROCONTROLLER, PQFP64, 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
RENESAS
©2020 ICPDF网 联系我们和版权申明