M30302MCL-XXXFP [RENESAS]
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER; 单芯片16位CMOS微机型号: | M30302MCL-XXXFP |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
文件: | 总166页 (文件大小:2520K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Rev.1.0
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M16C/30L group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, low voltage (2.2V to 3.6V), they are capable of executing
instructions at high speed. They also feature a built-in multiplier and DMAC, making them ideal for control-
ling office, communications, industrial equipment, and other high-speed processing applications.
The M16C/30L group includes a wide range of products with different internal memory sizes and various
package types.
Features
• Memory capacity..................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 2K to 3K bytes
• Shortest instruction execution time ......62.5ns (f(XIN)=16MHZ, VCC=3.0V to 3.6V)
142.9ns (f(XIN)=7MHZ, VCC=2.4V to 3.6V without software wait)
• Supply voltage .....................................3.0V to 3.6V (f(XIN)=16MHZ, without software wait)
2.4V to 3.6V (f(XIN)=7MHZ, without software wait)
2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait)
• Low power consumption ......................34.0mW (VCC = 3V, f(XIN)=10MHZ, without software wait)
66.0mW (VCC = 3.3V, f(XIN)=16MHZ, without software wait)
• Interrupts..............................................16 internal and 5 external interrupt sources, 4 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer......................3 output timers + 2 input timers
• Serial I/O..............................................3 channels (3 for UART or clock synchronous)
• DMAC ..................................................1 channels (trigger: 14 sources)
• A-D converter.......................................10 bits X 8 channels (Expandable up to 10 channels)
• Watchdog timer....................................1 line
• Programmable I/O port ........................87 lines
_______
• Input port..............................................1 line (P85 shared with NMI pin)
• Memory expansion ..............................Available (to a maximum of 1M bytes)
• Chip select output ................................4 lines
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment
------Table of Contents------
Central Processing Unit (CPU) ..................... 11
Reset............................................................. 14
Processor Mode ............................................ 21
Clock Generating Circuit ............................... 34
Protection ...................................................... 43
Interrupt......................................................... 44
Watchdog Timer............................................ 64
DMAC ........................................................... 66
Timer ............................................................. 75
Serial I/O ....................................................... 93
A-D Converter ............................................. 130
Programmable I/O Ports ............................. 136
Electrical characteristics ............................. 146
1
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4
4
/CS0
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
P0
7/D7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P45
P06
/D6
/D5
/D4
P4
P4
6
7
P05
P04
P03
P5
P5
P5
0
/D
/D
/D
/D
3
1
2
P0
P0
P0
/AN
/AN
/AN
/AN4/KI
/AN
2
2
1
1
0
0
3
P5
P5
P5
P5
3
/BCLK
/HLDA
/HOLD
/ALE
P10
P10
7
7
/KI
/KI
/KI
4
5
6
6
6
2
P10
5
5
1
0
3
M16C/30L Group
P57/RDY/CLKOUT
P10
4
P60
/CTS
/CLK
/RxD
/T
/CTS
0
/RTS
0
P10
3
P6
P6
1
2
0
P10
2
/AN
/AN
2
1
0
P10
1
P6
P6
P6
3
X
D0
AVSS
4
1
1
1
/RTS
1
/CLKS1
P100/AN
0
5
/CLK
/RxD
V
REF
P66
AVcc
7/ADTRG
P6
7
/TXD1
P9
1
2
3
4
5
6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note: P7
0
and P7
1
are N channel open-drain output pin.
Package: 100P6S-A
Figure 1.1.1. Pin configuration (top view)
2
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P12/D10
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4
P4
2
/A18
P11
P10
P07
/D9
/D8
/D7
3
/A19
P4
4/CS0
P45
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
/BCLK
/HLDA
/HOLD
P0
6
/D
6
5
4
3
2
1
P46
P0
P0
P0
P0
P0
5
/D
/D
/D
/D
/D
P47
4
3
2
1
P50
P51
P5
P5
2
3
P0
0
/D
/KI
/KI
/KI
0
3
2
P5
P5
P5
P5
4
P10
P10
P10
P10
7
/AN
7
5
6
/AN
6
6
/ALE
/RDY/CLKOUT
M16C/30L Group
5
/AN
5
1
0
3
7
4
/AN4/KI
P6
P6
0
/CTS
/CLK
/RxD
/T
/CTS
/CLK
0
/RTS
0
P10
P10
3
/AN
/AN
/AN
AVSS
1
0
2
2
P6
2
0
P10
1
1
P6
3
XD
0
P6
P6
P6
4
1/RTS
1
/CLKS1
P100/AN
0
5
1
6
/RxD
1
VREF
AVcc
7/ADTRG
/ANEX1
/ANEX0
P6
P7
P7
P7
7
/T
/T
/RxD
/CLK
XD
1
0
X
D
2
/SDA/TA0OUT (Note)
/SCL/TA0IN (Note)
2/TA1OUT
P9
P9
P9
1
2
6
2
5
1
2
3
4
5
6
7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Note: P70 and P71 are N channel open-drain output pin.
Package: 100P6Q-A
Figure 1.1.2. Pin configuration (top view)
3
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/30L group.
8
8
Port P2
8
8
8
8
8
I/O ports
Port P0
Port P1
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
Timer
System clock generator
A-D converter
(10 bits
X 8 channels
X
IN-XOUT
Expandable up to 10 channels)
X
CIN-XCOUT
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
UART/clock synchronous SI/O
(8 bits X 3 channels)
M16C/60 series16-bit CPU core
Memory
ROM
(Note 1)
Registers
Program counter
R0H
R0H
R1H
R2
R3
A0
A1
FB
R0L
R0L
R1L
PC
Watchdog timer
(15 bits)
RAM
(Note 2)
Stack pointer
ISP
USP
DMAC
(1 channel)
Vector table
INTB
Multiplier
Flag register
FLG
SB
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Figure 1.1.3. Block diagram of M16C/30L group
4
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1.1 is a performance outline of M16C/30L group.
Table 1.1.1. Performance outline of M16C/30L group
Item
Performance
Number of basic instructions
91 instructions
62.5ns(f(XIN)=16MHZ,
Shortest instruction execution time
V
CC=3.0V to 3.6V
)
142.9ns(f(XIN)=7MH
Z, VCC=2.4V to 3.6V, without software wait)
Memory
capacity
I/O port
ROM
(See the figure 1.1.4. ROM Expansion)
2K to 3K bytes
RAM
P0 to P10 (except P85)
P85
8 bits x 10, 7 bits x 1
Input port
1 bit x 1
Multifunction TA0, TA1, TA2
16 bits x 3
timer
TB1, TB2
16 bits x 2
Serial I/O
A-D converter
DMAC
UART0, UART1, UART2
(UART or clock synchronous) x 3
10 bits x (8+2) channels
1 channels (trigger: 14 sources)
15 bits x 1 (with prescaler)
Watchdog timer
Interrupt
16 internal and 5 external sources, 4 software sources, 7 levels
2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
3.0V to 3.6V (f(XIN)=16MHZ, without software wait)
2.4V to 3.6V (f(XIN)=7MHZ, without software wait)
2.2V to 3.6V (f(XIN)=7MHZ, with software one-wait)
34.0mW (VCC=3V, f(XIN)=10MHZ, without software wait)
Clock generating circuit
Supply voltage
Power consumption
66.0mW (VCC=3.3V, f(XIN)=16MHZ, without software wait)
I/O
I/O withstand voltage
3.3V
1mA
characteristics Output current
Memory expansion
Device configuration
Package
Available (to a maximum of 1M bytes)
CMOS high performance silicon gate
100-pin plastic mold QFP
5
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Mitsubishi plans to release the following products in the M16C/30L group:
(1) Support for mask ROM version
(2) ROM capacity
(3) Package
100P6S-A : Plastic molded QFP
100P6Q-A : Plastic molded QFP
ROM Size
(Byte)
128K
M30302MCL-XXXFP/GP
M30302MAL-XXXFP/GP
96K
64K
M30302M8L-XXXFP/GP
Mask ROM version
Figure 1.1.4. ROM expansion
The M16C/30L group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/30L group
June, 2002
Remarks
Type No.
ROM capacity
64K byte
Package type
RAM capacity
2K byte
M30302M8L-XXXFP
M30302M8L-XXXGP
100P6S-A
100P6Q-A
**
**
**
**
*
M30302MAL-XXXFP
M30302MAL-XXXGP
100P6S-A
100P6Q-A
Mask ROM version
96K byte
3K byte
M30302MCL-XXXFP
M30302MCL-XXXGP
100P6S-A
100P6Q-A
128K byte
*
**: Under development
* : New product
6
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Type No.
M 3 0 3 0 2 M 8 L – X X X G P
Package type:
FP : Package 100P6S-A
GP :
100P6Q-A
ROM No.
ROM capacity:
8 : 64K bytes
A : 96K bytes
C : 128K bytes
Memory type:
M : Mask ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/30 Group
M16C Family
Figure 1.1.5. Type No., memory size, and package
7
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
CC, VSS
Signal name
I/O type
Function
Power supply
input
V
Supply 2.2V to 3.6 V to the VCC pin. Supply 0 V to the VSS pin.
CNVSS
CNVSS
Input
This pin switches between processor modes. Connect this pin to the
SS pin when after a reset you want to start operation in single-chip
V
mode (memory expansion mode) or the VCC pin when starting
operation in microprocessor mode.
RESET
Reset input
Input
A “L” on this input resets the microcomputer.
X
IN
OUT
Clock input
Input
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the XIN and the XOUT pins. To
use an externally derived clock, input it to the XIN pin and leave the
X
Clock output
Output
XOUT pin open.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. Connect this
pin to the VSS pin when not using external data bus.
BYTE
External data Input
bus width
select input
AVCC
AVSS
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VCC
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS
.
V
REF
Input
Reference
voltage input
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.
P00
to P0
7
I/O port P0
Input/output
D
0
to D
7
Input/output When set as a separate bus, these pins input and output data (D
Input/output This is an 8-bit I/O port equivalent to P0.
0–D7).
P1
0
to P1
7
7
I/O port P1
I/O port P2
D
8
to D15
to P2
Input/output When set as a separate bus, these pins input and output data (D
8–D15).
P2
0
Input/output This is an 8-bit I/O port equivalent to P0.
A
0
to A7
Output
These pins output 8 low-order address bits (A0–A7).
A
0/D
0
to
Input/output If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D –D ) and output 8 low-order address bits
(A –A ) separated in time by multiplexing.
A7
/D7
0
7
0
7
Output
Input/output
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D –D ) and output address (A –A ) separated
in time by multiplexing. They also output address (A ).
A
A
0
1
0
6
1
7
/D
to A
0
0
7/D
6
P3
0
to P3
7
I/O port P3
I/O port P4
Input/output This is an 8-bit I/O port equivalent to P0.
A
8
to A15
/D
Output
These pins output 8 middle-order address bits (A8–A15).
A
8
7,
Input/output If the external bus is set as a 16-bit wide multiplexed bus, these pins
A
9
to A15
Output
input and output data (D7) and output address (A
8) separated in time
–A15).
by multiplexing. They also output address (A
9
P40
to P4
7
Input/output This is an 8-bit I/O port equivalent to P0.
Output
Output
These pins output A16–A19 and CS
0
–CS
3 signals. A16–A19 are 4 high-
A
16 to A19
,
order address bits. CS0–CS3 are chip select signals used to specify an
access space.
CS to CS
0
3
8
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Pin Description
Pin name
P5 to P5
Signal name
I/O port P5
I/O type
Function
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
0
7
Input/output
Output
Output
Output
Output
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
HOLD,
ALE,
RDY
Output
Input
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
P6
0
to P6
7
I/O port P6
Input/output
Input/output
This is an 8-bit I/O port equivalent to P6 (P70 and P71 are N channel
open-drain output). Pins in this port also function as timer A0–A2, or
UART2 I/O pins as selected by software.
P70
to P7
7
I/O port P7
I/O port P8
P8
P8
0
6
to P8
4
,
Input/output
Input/output
P8
Using software, they can be made to function as the I/O pins for the
input pins for external interrupts. P8 and P8 can be set using
software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
pin) and P8 (XCIN pin). P8 is an input-only port that also functions
0 to P84, P86, and P87 are I/O ports with the same functions as P6.
,
6
7
P87
,
Input/output
Input
6
(XCOUT
P85
I/O port P85
7
5
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
P90
to P9
7
I/O port P9
Input/output This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as, timer B1, B2 input pins, A-D converter extended input pins, or A-D
trigger input pins as selected by software.
P100
to P10
7
I/O port P10
Input/output This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins as selected by software. Furthermore, P10
4
–P107 also function as input pins for the key input interrupt function.
9
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/30L group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, DMAC, A-D converter, and I/O ports.
The following explains each unit.
Memory
Figure 1.3.1 is a memory map of the M16C/30L group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30302MCL-XXXGP,
there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as
_______
the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is
stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 0040016 up is RAM. For example, in the M30302MCL-XXXGP, 3K bytes of internal RAM is mapped
to the space from 0040016 to 00FFF16. In addition to storing data, the RAM also stores the stack used when
calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30302MCL-XXXGP, the following spaces cannot be used.
• The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes)
• The space between D000016 and DFFFF16 (Memory expansion mode)
0000016
SFR area
For details, see Figures
1.6.1 to 1.6.3
FFE0016
0040016
Internal RAM area
Special page
vector table
XXXXX16
Internal reserved
area (Note 1)
0400016
RAM size
2K bytes
3K bytes
Address XXXXX16
00BFF16
FFFDC16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
External area
00FFF16
Internal reserved
area (Note 2)
D000016
ROM size
Address YYYYY16
Watchdog timer
YYYYY16
64K bytes
96K bytes
128K bytes
F000016
E800016
E000016
DBC
NMI
Reset
Internal ROM area
FFFFF16
FFFFF16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Figure 1.3.1. Memory map
10
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
b15
b15
b15
b15
b15
b15
b15
b8 b7
b8 b7
b0
b0
b0
b0
b0
b0
b0
R0(Note)
R1(Note)
R2(Note)
R3(Note)
A0(Note)
A1(Note)
FB(Note)
L
L
H
H
b19
b19
b0
PC
Program counter
Data
registers
b0
b0
Interrupt table
register
INTB
H
L
b15
b15
b15
b15
User stack pointer
USP
ISP
SB
b0
b0
b0
Interrupt stack
pointer
Address
registers
Static base
register
FLG
Frame base
registers
Flag register
IPL
U
I O B S Z D C
Note: These registers consist of two register banks.
Figure 1.4.1. Central processing unit register
(1) Data registers (R0, R1, R1H, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Register R0 can be used as separate 8-bit data registers, R0H and R0L. Register R1 can be used as
separate 8-bit data registers, R1H and R1L. In some instructions, registers R2 and R0, as well as R3 and
R1 can use as 32-bit data registers (R2R0 or R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
(6) Stack pointer (USP or ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”
.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
12
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
Flag register (FLG)
U
I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.4.2. Flag register (FLG)
13
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
The RAM is undefined at power on. The initial value must therefore be set. When a reset signal is applied
while the CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the
CPU access.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.
3V
2.4V
VCC
0V
3V
V
CC
RESET
RESET
0V
0.48V
More than 20 cycles of XIN are needed.
Example when VCC = 3V
.
Figure 1.5.1. Example reset circuit
XIN
More than 20 cycles are needed
BCLK 28cycles
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
Content of reset vector
FFFFC16
FFFFD16
FFFFE16
WR
CS0
Microprocessor
mode BYTE = “L”
Content of reset vector
FFFFC16
FFFFE16
Address
RD
WR
CS0
Single chip
mode
FFFFC16
Content of reset vector
Address
FFFFE16
Figure 1.5.2. Reset sequence
14
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.5.1. Pin status when RESET pin level is “L”
Status
CNVSS = VCC
Pin name
CNVSS = VSS
BYTE = VSS
Data input (floating)
BYTE = VCC
Data input (floating)
P0
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
P1
Data input (floating)
Input port (floating)
P2, P3, P4
0
to P4
3
Address output (undefined)
Address output (undefined)
P4
4
5
CS0 output (“H” level is output) CS0 output (“H” level is output)
P4
to P4
7
Input port (floating)
(pull-up resistor is on)
Input port (floating)
(pull-up resistor is on)
Input port (floating)
P5
0
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
WR output (“H” level is output) WR output (“H” level is output)
BHE output (undefined) BHE output (undefined)
RD output (“H” level is output) RD output (“H” level is output)
BCLK output BCLK output
P5
P5
P5
1
2
3
HLDA output (The output value HLDA output (The output value
P54
Input port (floating)
depends on the input to the
HOLD pin)
depends on the input to the
HOLD pin)
P5
P5
P5
5
6
7
Input port (floating)
Input port (floating)
Input port (floating)
HOLD input (floating)
HOLD input (floating)
ALE output (“L” level is output) ALE output (“L” level is output)
RDY input (floating)
Input port (floating)
RDY input (floating)
Input port (floating)
P6, P7, P8
0 to P84,
Input port (floating)
P8 , P8 , P9, P10
6
7
15
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(1) Processor mode register 0 (Note)
(2) Processor mode register 1
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
(6) Address match interrupt enable register
(7) Protect register
(000416)···
(000516)··· 0
(000616)··· 0
(000716)··· 0
(000816)··· 0
(000916)···
(000A16)···
(000F16)··· 0
(001016)···
(001116)···
(001216)···
(001416)···
(001516)···
(001616)···
(002C16)··· 0
(004A16)···
(004B16)···
(004D16)···
(004E16)···
0016
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(20)
(21)
(22)
(23)
(24)
(25)
(26)
UART1 transmit interrupt control register (005316)···
0
1
0
0
0
0
1
0
0
0
0
0
0 0
0
0
0
1
0
0
?
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
(005416)···
(005516)···
(005616)···
(005716)···
(005B16)···
(005C16)···
(005D16)···
(005E16)···
(005F16)···
(035F16)···
(037516)···
(037616)···
(037716)···
(037816)···
1 0
0 0
0 0
0
0
0
0
0
?
0
(8)
Watchdog timer control register
Address match interrupt register 0
0
0
?
? ?
0
0
0
0
0
0
(27)
(28)
(9)
0016
0016
INT1 interrupt control register
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
INT2 interrupt control register
0 0
0
0
Interrupt cause select register
UART2 special mode register 3
UART2 special mode register 2
UART2 special mode register
0016
0016
0016
(10)Address match interrupt register 1
0016
0016
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8016
0016
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
DMA0 control register
0
0
0
0 ?
? 0
? 0
? 0
? 0
? 0
? 0
? 0
UART2 transmit/receive mode register
0
0
0
0
0
0
0
0
1 0
0 0
0
1
0
0
Bus collision detection interrupt
control register
DMA0 interrupt control register
UART2 transmit/receive control register 0 (037C16)···
UART2 transmit/receive control register 1 (037D16)···
Count start flag
(038016)···
0016
Key input interrupt control register
A-D conversion interrupt control register
Clock prescaler reset flag
One-shot start flag
Trigger select flag
Up-down flag
(038116)··· 0
(038216)··· 0
(038316)···
0
0
0 0
0
0
UART2 transmit interrupt control register (004F16)···
UART2 receive interrupt control register (005016)···
UART0 transmit interrupt control register (005116)···
UART0 receive interrupt control register (005216)···
0016
0016
(038416)···
?
0 0 0
x : Nothing is mapped to this bit
? : Undefined
The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.
The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the
CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access.
Note: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Figure 1.5.3. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
(72)
(73)
(74)
(75)
(76)
(77)
(78)
(79)
(80)
(42) Timer A0 mode register
(039616)···
(039716)···
(039816)···
(039C16)···
0016
0016
0016
0
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Port P8 direction register
Port P9 direction register
Port P10 direction register
Pull-up control register 0
Pull-up control register 1(Note)
Pull-up control register 2
Port control register
(03EA16)···
(03EB16)···
(03EE16)···
(03EF16)···
(03F216)··· 0
(03F316)···
(03F616)···
(03FC16)···
(03FD16)···
(03FE16)···
(03FF16)···
0016
0016
0016
0016
Timer A1 mode register
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
Timer A2 mode register
Timer B1 mode register
0
0 ?
0
0
0 0
0 0
Timer B2 mode register
(039D16)··· 0 0 ?
(03A016)···
0
0
0 0 0 0 0
UART0 transmit/receive mode register
0016
0016
0016
0016
0016
0016
0016
UART0 transmit/receive control register 0 (03A416)··· 0 0 0
UART0 transmit/receive control register 1 (03A516)··· 0 0 0
0
0
1
0
0
0
0 0
1 0
UART1 transmit/receive mode register
(03A816)···
0016
UART1 transmit/receive control register 0 (03AC16)··· 0 0 0
UART1 transmit/receive control register 1 (03AD16)··· 0 0 0
0
0
0
1
0
0
0
0
0
0 0
1 0
0 0
UART transmit/receive control register 2 (03B016)···
0 0
Data registers (R0/R1/R2/R3)
Address registers (A0/A1)
Frame base register (FB)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
000016
000016
000016
0000016
000016
000016
000016
000016
DMA0 cause select register
A-D control register 2
(03B816)···
(03D416)··· 0 0 0
0016
0
0
?
0
?
?
0
?
A-D control register 0
(03D616)···
(03D716)···
(03E216)···
(03E316)···
(03E616)···
(03E716)···
0
0 0
? ?
A-D control register 1
0016
0016
0016
0016
0016
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
x : Nothing is mapped to this bit
? : Undefined
The content of other registers are undefined when the microcomputer is reset. The initial values must therefore be set.
The RAM is undefined at power on. The initial values must therefore be set. When a reset signal is applied while the
CPU is writing a value to the RAM, the value may be set as unknown due to the termination of the CPU access.
Note: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Figure 1.5.4. Device's internal status after a reset is cleared
17
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
000016
000116
000216
000316
000416
004016
004116
004216
004316
004416
004516
004616
004716
004816
Processor mode register 0 (PM0)
000516 Processor mode register 1(PM1)
000616 System clock control register 0 (CM0)
000716 System clock control register 1 (CM1)
000816 Chip select control register (CSR)
000916 Address match interrupt enable register (AIER)
000A16 Protect register (PRCR)
000B16
004916
004A16
Bus collision detection interrupt control register (BCNIC)
000C16
000D16
004B16 DMA0 interrupt control register (DM0IC)
000E16
004C16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
004D16
004E16
004F16
005016
005116
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006116
006216
006316
006416
006516
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
DMA0 source pointer (SAR0)
INT2 interrupt control register (INT2IC)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
032A16
032B16
032C16
032D16
032E16
032F16
033016
033116
033216
033316
033416
033516
033616
033716
033816
033916
033A16
033B16
033C16
033D16
033E16
033F16
DMA0 control register (DM0CON)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.1. Location of peripheral unit control registers (1)
18
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
034016
Count start flag (TABSR)
034116
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
034216
034316
034416
034516
034616
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
034716
034816
034916
034A16
034B16
034C16
034D16
034E16
034F16
035016
035116
035216
Timer B1 register (TB1)
Timer B2 register (TB2)
035316
035416
035516
035616
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
035716
035816
035916
035A16
035B16
035C16
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
035D16
035E16
035F16 Interrupt cause select register (IFSR)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
036016
036116
036216
036316
036416
036516
036616
036716
036816
036916
036A16
036B16
036C16
036D16
036E16
036F16
037016
037116
037216
037316
037416
UART0 transmit buffer register (U0TB)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
UART1 transmit buffer register (U1TB)
UART1 transmit/receive control register 0 (U1C0)
03AD16 UART1 transmit/receive control register 1 (U1C1)
03AE16
UART1 receive buffer register (U1RB)
03AF16
03B016 UART transmit/receive control register 2 (UCON)
03B116
03B216
03B316
03B416
03B516
UART2 special mode register 3(U2SMR3)
UART2 special mode register 2(U2SMR2)
UART2 special mode register (U2SMR)
037516
03B616
037616
03B716
037716
03B816 DMA0 request cause select register (DM0SL)
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
037816
037916
037A16
037B16
037C16
037D16
037E16
037F16
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1)
UART2 receive buffer register (U2RB)
Note : Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
Figure 1.6.2. Location of peripheral unit control registers (2)
19
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D116
03D216
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DE16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03F816
03F916
03FA16
03FB16
03FC16
03FD16
03FE16
03FF16
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D register 7 (AD7)
A-D control register 2 (ADCON2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
Port P0 register (P0)
Port P1 register (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 register (P2)
Port P3 register (P3)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 register (P4)
Port P5 register (P5)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 register (P6)
Port P7 register (P7)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 register (P8)
Port P9 register (P9)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 register (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
Note : Locations in the SFR area where nothing is allocated are reserved
areas. Do not access these areas for read or write.
Figure 1.6.3. Location of peripheral unit control registers (3)
20
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.
Processor Mode
(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. However, after the reset has been released and the operation of shifting from the micropro-
cessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed
even if the CPU shifts to the single-chip mode.
Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral
functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the
operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the
internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus width and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Do not change the
processor mode bits simultaneously with other bits when changing the processor mode bits “012” or
“112”. Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from
the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
21
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Figure 1.7.1 shows the processor mode register 0 and 1.
Figure 1.7.2 shows the memory maps in each processor modes.
Processor mode register 0 (Note 1)
Symbol
PM0
Address
000416
When reset
0016 (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
R
W
Bit symbol
PM00
Bit name
Function
b1 b0
Processor mode bit
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Must not be set
1 1: Microprocessor mode
PM01
PM02
0 : RD,BHE,WR
1 : RD,WRH,WRL
R/W mode select bit
Software reset bit
PM03
PM04
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
b5 b4
Multiplexed bus space
select bit
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
PM05
PM06
0 : Address output
1 : Port function
(Address is not output)
Port P40 to P43 function
select bit (Note 3)
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
PM07
BCLK output disable bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new
values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to “1”.)
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-
bit width.The processor operates using the separate bus after reset is revoked, so the entire
space multiplexed bus cannot be chosen in microprocessor mode.
P3
1 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can
be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
000000X0
2
0
0
0
0
0
R
W
Bit symbol
Bit name
Function
Must always be set to “0”
Reserved bit
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
0 : Interrupt
1 : Reset (Note 2)
PM12
Watchdog timer function
select bit
(Note 2)
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
Reserved bit
Reserved bit
Reserved bit
Reserved bit
PM17
0 : No wait state
1 : Wait state inserted
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16) to “1” when writing new values to this register.
Note 2: This bit can only be set to “1”.
Figure 1.7.1. Processor mode register 0 and 1
22
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Single-chip mode
Memory expansion mode
SFR area
Microprocessor mode
0000016
0040016
SFR area
SFR area
Internal
RAM area
Internal
RAM area
Internal
RAM area
XXXXX16
0400016
Internally
reserved area
Internally
reserved area
External
area
External
area
Inhibited
D000016
Internally
reserved area
YYYYY16
Internal
ROM area
Internal
ROM area
FFFFF16
Address XXXXX16
00BFF16
RAM size
2K bytes
3K bytes
Address YYYYY16
F000016
ROM size
64K bytes
96K bytes
128K bytes
External area : Accessing this area allows the user to
access a device connected externally
to the microcomputer.
E800016
00FFF16
E000016
Figure 1.7.2. Memory maps in each processor modes
23
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings.
Table 1.8.1 shows the factors used to change the bus settings.
Table 1.8.1. Factors for switching bus settings
Bus setting
Switching factor
Bit 6 of processor mode register 0
BYTE pin
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0
is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address
bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set
to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the
address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With the BYTE pin = “H”, the 8 bits from D0 to
D7 are multiplexed with A0 to A7.
With the BYTE pin = “L”, the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not
multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the
microcomputer’s even addresses (every 2nd address). To access these external devices, access the
even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
24
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Table 1.8.2. Pin functions for each processor mode
Single-chip
Memory
expansion mode
Processor mode
Memory expansion mode/microprocessor modes
mode
“01”, “10”
“00”
“11” (Note 1)
multiplexed
bus for the
entire
Multiplexed bus
space select bit
Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus
(separate bus)
space
Data bus width
BYTE pin level
16 bits
“L”
8 bits
“H”
8 bits
“H”
16 bits
“L”
8 bit
“H”
P0
0
to P0
7
I/O port
Data bus
Data bus
Data bus
Data bus
I/O port
P1
0
to P1
7
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
P2
0
Address bus
/data bus(Note 2)
Address bus
Address bus
Address bus
Address bus
Address bus
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
Address bus
/data bus
P2
P3
1
0
to P2
7
Address bus
/data bus(Note 2) /data bus(Note 2)
Address bus
Address bus
/data bus
Address bus
Address bus
I/O port
Address bus
/data bus(Note 2)
A8/D7
P3
P4
1
to P3
7
Address bus
I/O port
I/O port
I/O port
0
to P4
3
Port P4
0
to P43
function select bit = 1
P4
0
to P4
3
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
Port P4
0
to P43
function select bit = 0
P4
P5
P5
P5
4
0
4
5
to P4
7
3
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
to P5
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
P5
P5
6
7
RDY
RDY
RDY
RDY
RDY
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
P31 to P37 become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used
in each chip select.
Note 2: Address bus when in separate bus mode.
25
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
When a change is made from single-chip mode to memory expansion mode, the value of the address
bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
_______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______
_______
celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1
shows the external memory areas specified using the chip select signal.
Table 1.9.1. External areas specified by the chip select signals
Chip select signal
Processor mode
CS0
CS1
CS2
CS3
3000016 to
CFFFF16
(640K bytes)
Memory expansion mode
Microprocessor mode
0800016 to
27FFF16
(128K bytes)
0400016 to
07FFF16
(16K bytes)
2800016 to
2FFFF16
(32K bytes)
3000016 to
FFFFF16
(832K bytes)
26
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Chip select control register
Symbol
CSR
Address
000816
When reset
0116
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
CS0
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Wait state inserted
1 : No wait state
Figure 1.9.1. Chip select control register
The timing of the chip select signal changing to “L”(active) is synchronized with the address bus. But the
timing of the chip select signal changing to “H” depends on the area which will be accessed in the next
cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal.
27
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Example 2) After access the external area, only the chip select signal
changes in the next cycle (the address bus does not change).
Example 1) After access the external area, both the address signal and
the chip select signal change concurrently in the next cycle.
In this example, an access to the internal ROM or the internal RAM in the
next cycle will occur, after access to the external area. In this case, the
chip select signal changes between the two cycles, but the address does
not change.
In this example, after access to the external area(i), an access to the area
indicated by the other chip select signal(j) will occur in the next cycle. In
this case, both the address bus and the chip select signal change between
the two cycles.
Access to the
External Area( i ) External Area( j )
Access to the Other
Access to the
External Area
Internal ROM/RAM
Access
BCLK
BCLK
Read/Write
signal
Read/Write
signal
Data bus
Data bus
Data
Data
Address
Address bus
Address bus
Chip select
Address
Chip select
(CS i)
Chip select
(CS j)
Example 3) After access the external area, only the address bus changes
in the next cycle (the chip select signal does not change).
Example 4) After access the external area, either the address signal and
the chip select signal do not change in the next cycle.
In this example, after access to the external area(i), an access to the area
indicated by the same chip select signal(i) will occur in the next cycle. In
this case, the address bus changes between the two cycles, but the chip
select signal does not change.
In this example, any access to any area does not occur in the next cycle
(either instruction prefetch does not occur). In this case,either the address
bus and chip select signal do not change between the two cycles.
Access to the
External Area( i ) External Area( i )
Access to the Same
Access to the
No Access
External Area
BCLK
BCLK
Read/Write
signal
Read/Write
signal
Data bus
Data bus
Data
Address
Data
Address bus
Address bus
Chip select
Address
Chip select
(CS i)
Note : These examples show the address bus and chip select signal within the successive two cycles.
According to the combination of these examples, the chip select can be elongated to over 2cycles.
Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without
Wait)
28
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
_____ ________
______
_____ ________
_________
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE
_____ ______
_______
pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals.
_____ ______
________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________
_________
Table 1.9.3. Operation of RD, WRL, and WRH signals
Data bus width
Status of external data bus
RD
L
WRL
H
L
WRH
H
H
L
Read data
H
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
16-bit
(BYTE = “L”)
H
H
L
H
L
_____ ______
________
Table 1.9.4. Operation of RD, WR, and BHE signals
Data bus width
A0
H
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
RD
H
L
WR
L
BHE
L
H
L
L
H
16-bit
(BYTE = “L”)
H
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
H
L
Not used
Not used
H / L
H / L
8-bit
(BYTE = “H”)
H
Read 1 byte of data
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “L”
ALE
When BYTE pin = “H”
ALE
A
0
Address
Data (Note 1)
Address
Data (Note 1)
D0/A0 to D7/A7
D0/A1 to D7/A8
Address
A8 to A19
Address (Note 2)
A9 to A19
Address
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.3. ALE signal and address/data bus
29
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(5) The _R__D___Y__ signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in
________
Figure 1.9.4, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
________
an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5
shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example
____
________
in which the RD signal is prolonged by the RDY signal.
________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
________
chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to
________
all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as
properly as in non-using.
Table 1.9.5. Microcomputer status in wait state (Note)
Item
Status
Oscillation
On
___
_____
________
R/W signal, address bus, data bus, CS
Maintain status when RDY signal received
__________
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
_____
________
Figure 1.9.4. Example of RD signal extended by RDY signal
30
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 1.9.6
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 1.9.5. Bus-using priorities
Table 1.9.6. Microcomputer status in hold state
Item
Status
Oscillation
ON
___
_____ _______
R/W signal, address bus, data bus, CS, BHE
Floating
Floating
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Maintains status when hold signal is received
Output “L”
__________
HLDA
Internal peripheral circuits
ALE signal
ON (but watchdog timer stops)
Undefined
(7) External bus status when the internal area is accessed
Table 1.9.7 shows the external bus status when the internal area is accessed.
Table 1.9.7. External bus status when the internal area is accessed
Item
SFR accessed
Address output
Internal ROM/RAM accessed
Maintain status before accessed
address of external area
Floating
Address bus
Data bus
When read
When write
Floating
Output data
Undefined
RD, WR, WRL, WRH
BHE
RD, WR, WRL, WRH output
BHE output
Output “H”
Maintain status before accessed
status of external area
Output “H”
CS
Output “H”
Output “L”
ALE
Output “L”
31
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(8) BCLK output
The user can choose the BCLK output by use of bit 7 of processor mode register 0 (000416) (Note).
When set to “1”, the output floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, a wait is applied to all memory areas (two or three BCLK
cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring
to the recommended operating conditions (main clock input oscillation frequency) of the electric character-
________
istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register’s
bits 4 to 7 must be set to “0”.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in
one BCLK cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits
default to “0” after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
insert a software wait if using the multiplex bus to access the external memory area.
Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when
using software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 1.9.8. Software waits and bus cycles
Bits 4 to 7 of chip select
Bus cycle
2 BCLK cycles
Area
SFR
Bus status
Wait bit
control register
Invalid
0
Invalid
Invalid
1 BCLK cycle
Internal
ROM/RAM
1
0
0
Invalid
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
Separate bus
Separate bus
Separate bus
1
0
External
memory
area
1
0
1
0 (Note)
0
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
Multiplex bus
Multiplex bus
0 (Note)
Note: When using the RDY signal, always set to “0”.
32
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
< Separate bus (no wait) >
Bus cycle (Note 1) Bus cycle (Note 1)
BCLK
Write signal
Read signal
Output
Input
Data bus
Address bus (Note 2)
Address
Address
Chip select (Note 2)
< Separate bus (with wait) >
Bus cycle (Note 1)
Bus cycle (Note 1)
BCLK
Write signal
Read signal
Input
Output
Data bus
Address
Address
Address bus (Note 2)
Chip select (Note 2)
< Multiplexed bus >
Bus cycle (Note 1)
Bus cycle (Note 1)
BCLK
Write signal
Read signal
ALE
Address
Address
Address bus (Note 2)
Address bus/
Address
Input
Data output
Address
Data bus
Chip select (Note 2)
Note 1: These example timing charts indicate bus cycle length.
After this bus cycle sometimes come read and write cycles in succession.
Note 2: The address bus and chip select may be extended depending on the CPU status
such as that of the instruction queue buffer.
Figure 1.9.6. Typical bus timings using software wait
33
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.10.1. Main clock and sub-clock generating circuits
Main clock generating circuit
• CPU’s operating clock source
• Internal peripheral units’
operating clock source
Ceramic or crystal oscillator
XIN, XOUT
Sub-clock generating circuit
• CPU’s operating clock source
• Timer A/B’s count clock
source
Use of clock
Usable oscillator
Crystal oscillator
XCIN, XCOUT
Pins to connect oscillator
Oscillation stop/restart function
Oscillator status immediately after reset
Other
Available
Available
Oscillating
Stopped
Externally derived clock can be input
Example of oscillator circuit
Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples
of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
Vcc
Vss
CIN
C
OUT
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 1.10.1. Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
CIN
XCOUT
X
CIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XCIN
and XCOUT following the instruction.
Figure 1.10.2. Examples of sub-clock
34
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Control
Figure 1.10.3 shows the block diagram of the clock generating circuit.
X
CIN
X
COUT
f
C32
1/32
f
1
CM04
f
1SIO2
8SIO2
f
AD
f
C
f
f
8
Sub clock
f
32SIO2
CM10 “1”
Write signal
f
32
S
R
Q
X
IN
X
OUT
b
c
CM07=0
a
d
Divider
RESET
Software reset
NMI
BCLK
f
C
Main clock
CM02
CM07=1
CM05
Interrupt request
level judgment
output
S Q
R
WAIT instruction
c
b
1/2
1/2
1/2
1/2
1/2
a
CM06=0
CM17,CM16=11
CM06=1
CM06=0
CM17,CM16=10
d
CM06=0
CM17,CM16=01
CM06=0
CM17,CM16=00
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
WDCi : Bit i at address 000F16
Details of divider
Figure 1.10.3. Clock generating circuit
35
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power
dissipation mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed
mode, the value before high-speed/medium-speed mode is retained.
(2) Sub-clock
The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.
After oscillation is started using the port XC select bit (bit 4 at address 000616), the sub-clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub-clock oscillation has fully stabilized before switching.
After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when the port XC select bit (bit 4 at address 000616) is set to “0” , shifting to stop mode and
at a reset.
When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
(3) BCLK
The BCLK is the clock that drives the CPU, and is fC or the clock is derived by dividing the main clock by
1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can
be output from BCLK pin by the BCLK output disable bit (bit 7 at address 000416) in the memory expan-
sion and the microprocessor modes.
The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-
speed/medium-speed to stop mode, shifting to low power dissipation mode and at reset. When shifting
from high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed
mode is retained.
(4) Peripheral function clock(f1, f8, f32, f1SIO2, f8SIO2,f32SIO2,fAD)
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
(5) fC32
This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.
36
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.10.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
Bit name
Function
R W
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P5
0 1 : f
1 0 : f
1 1 : f32 output
7
C
output
output
8
CM01
CM02
CM03
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port X
(Note 10)
C
select bit
0 : I/O port
1 : XCIN-XCOUT generation (Note 9)
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 3, 4, 5)
)
0 : On
1 : Off
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
bit 0 (Note 7)
1 : Division by 8 mode
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: Changes to “1” when the port X select bit (CM04) is set to “0”, shiffing to stop mode and at a reset.
C
Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the sub clock
oscillation is stable, set system clock select bit (CM07) to “1” before setting this bit to “1”. The main clock division select bit 0
(CM06) and the XIN-XOUT drive capacity select bit (CM15) change to “1” when this bit is set to “1”.
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to “1”, XOUT turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to XOUT
(“H”) via the feedback resistor.
Note 6: Set port XC select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting this bit from “0” to “1”. Do not write to
both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock oscillating before
setting this bit from “1” to “0”.
Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation
mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained.
Note 8: fC32 is not included. Do not set to “1” when using low-speed or low power dissipation mode.
Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
Note10: The XCIN-XCOUT drive capacity select bit changes to “1” when this bit is set to “0”.
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0
0
0
Bit symbol
CM10
Bit name
Function
R W
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
CM15
select bit (Note 2)
b7 b6
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
CM16
CM17
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register.
Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode, shifting to low power dissipation
mode and at a reset. When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8.
Note 4: If this bit is set to “1”, XOUT turns “H”, and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-impedance state.
Figure 1.10.4. Clock control registers 0 and 1
37
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to “1”, the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation , BCLK, f1 to f32, f1SIO2 to f32SIO2, fC, fC32, and fAD stops in stop mode, peripheral
functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B
operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2) functions
provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel
must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a
_______
hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to
0, then shift to stop mode.
The main clock division select bit 0 (bit 6 at address 000616) changes to “1” when shifting from high-speed/
medium-speed mode to stop mode, shifting to low power dissipation mode and at reset. When shifting from
high-speed/medium-speed mode to low-speed mode, the value before high-speed/medium-speed mode is
retained.
Table 1.10.2. Port status during stop mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before stop mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
__________
“H”
HLDA, BCLK
“H”
“H”
ALE
Port
Retains status before stop mode Retains status before stop mode
Valid only in single-chip mode “H”
CLKOUT
When fc selected
When f8, f32 selected
Valid only in single-chip mode Retains status before stop mode
38
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral
function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32
does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU
running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to “1”. Table
1.10.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that
interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must
have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set
to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware
_______
reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift
to wait mode.
Table 1.10.3. Port status during wait mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before wait mode
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
__________
“H”
HLDA,BCLK
“H”
ALE
Port
“H”
Retains status before wait mode
Retains status before wait mode
CLKOUT
When fC selected
Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is “0”.
When the WAIT peripheral
function clock stop bit is “1”,
the status immediately prior
to entering wait mode is main-
tained.
39
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition of BCLK
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address
000616) and the XIN-XOUT drive capacity select bit (bit 5 at address 000716) change to “1” when shifting
from high-speed/medium-speed mode to stop mode, shifting to low power dissipation mode and at a reset.
When shifting from high-speed/medium-speed mode to low-speed mode, the value before high-speed/
medium-speed mode is retained. The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption
mode, make sure the sub-clock is oscillating stably.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before
transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-
clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately
after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1
CM17
CM16
CM07
CM06
CM05
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
Operating mode of BCLK
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
Division by 2 mode
0
Division by 4 mode
Division by 8 mode
Division by 16 mode
No-division mode
Invalid
1
Invalid
1
1
0
0
0
0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
Low-speed mode
1
Low power dissipation mode
CM1i : Bit i of the address 000716
CM0i : Bit i of the address 000616
40
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
Power control
The following is a description of the three available power control modes:
Modes
Power control is available in three modes.
(a) Normal operation mode
• High-speed mode
Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK.
Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its as-
signed clock.
• Low-speed mode
fC becomes the BCLK. The CPU operates according to the fC clock. The fC clock is supplied by the
subclock. Each peripheral function operates according to its assigned clock.
• Low power dissipation mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fC
clock. The fC clock is supplied by the subclock. The only peripheral functions that operate are those
with the subclock selected as the count source.
(b) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(c) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in decreasing power consumption.
Figure 1.10.5 is the state transition diagram of the above modes.
41
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power control
Transition of stop mode, wait mode
Reset
WAIT
instruction
All oscillators stopped
CPU operation stopped
CM10 = “1”
Interrupt
Medium-speed mode
(divided-by-8 mode)
Stop mode
Wait mode
Interrupt
Interrupt
WAIT
instruction
All oscillators stopped
CPU operation stopped
High-speed/medium-
speed mode
CM10 = “1”
Stop mode
Wait mode
Interrupt
Low power
dissipation
mode
Low-speed
mode
All oscillators stopped
CPU operation stopped
WAIT
instruction
CM10 = “1”
Interrupt
Low-speed/low power
dissipation mode
Stop mode
Wait mode
Interrupt
Normal mode
(Refer to the following for the transition of normal mode.)
Transition of normal mode
Main clock is oscillating
Sub clock is stopped
Medium-speed mode
(divided-by-8 mode)
CM06 = “1”
BCLK : f(XIN)/8
CM07 = “0” CM06 = “1”
CM07 = “0” (Note 1)
CM06 = “1”
CM04 = “0”
CM04 = “1”
(Notes 1, 3)
Main clock is oscillating
Sub clock is oscillating
CM04 = “0”
Medium-speed mode
(divided-by-2 mode)
High-speed mode
Main clock is oscillating
Sub clock is oscillating
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
Medium-speed mode
(divided-by-8 mode)
Low-speed mode
CM07 = “0”
(Note 1, 3)
BCLK : f(XIN)/8
CM07 = “0”
CM06 = “1”
BCLK : f(XCIN
CM07 = “1”
)
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM07 = “1”
(Note 2)
BCLK : f(XIN)/4
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM05 = “0”
CM05 = “1”
CM04 = “0”
CM04 = “1”
Main clock is oscillating
Sub clock is stopped
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
Medium-speed mode
(divided-by-2 mode)
High-speed mode
CM07 = “1” (Note 2)
CM05 = “1”
BCLK : f(XIN
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “0”
)
BCLK : f(XIN)/2
CM07 = “0” CM06 = “0”
CM17 = “0” CM16 = “1”
BCLK : f(XCIN
)
CM07 = “1” CM06 = “1”
CM15 = “1”
CM07 = “0” (Note 1)
CM06 = “0” (Note 3)
CM04 = “1”
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
CM06 = “0”
(Notes 1,3)
BCLK : f(XIN)/4
BCLK : f(XIN)/16
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “0”
CM07 = “0” CM06 = “0”
CM17 = “1” CM16 = “1”
CM03 = “1”
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.
Figure 1.10.5. State transition diagram of Power control mode
42
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.10.6 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716), port P9 direction register (ad-
dress 03F316) can only be changed when the respective bit in the protect register is set to “1”. Therefore,
important outputs can be allocated to port P9.
If, after “1” (write-enabled) has been written to the port P9 direction register write-enable bit (bit 2 at address
000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the
system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and
1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an
address. The program must therefore be written to return these bits to “0”.
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX000
2
Bit symbol
PRC0
Bit name
Function
0 : Write-inhibited
R W
Enables writing to system clock
control registers 0 and 1 (addresses
1 : Write-enabled
000616 and 000716
)
Enables writing to processor mode
registers 0 and 1 (addresses 000416
0 : Write-inhibited
1 : Write-enabled
PRC1
PRC2
and 000516
)
Enables writing to port P9 direction
register (address 03F316) (Note
0 : Write-inhibited
1 : Write-enabled
)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
Note: Writing a value to an address after “1” is written to this bit returns the bit
to “0” . Other bits do not automatically return to “0” and they must therefore
be reset by the program.
Figure 1.10.6. Protect register
43
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Overview of Interrupt
Type of Interrupts
Figure 1.11.1 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
INT instruction
Interrupt
Reset
_______
NMI
________
DBC
Special
Watchdog timer
Single step
Hardware
Address matched
Peripheral I/O (Note)
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.11.1. Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
44
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to
“1”. The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-
ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-
rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/
O interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and
select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from
the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-
quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a
shift.
45
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an “L” is input to the RESET pin.
_______
• NMI interrupt
_______
_______
An NMI interrupt occurs if an “L” is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer. Write to the watchdog timer start register after the watchdog timer
interrupt occurs (initialize watchdog timer).
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by
the address match interrupt register is executed with the address match interrupt enable bit set to “1”.
If an address other than the first address of the instruction in the address match interrupt register is set,
no address match interrupt occurs.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt
This is an interrupts that DMA generates.
• Key-input interrupt
___
A key-input interrupt occurs if an “L” is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A2 interrupt
These are interrupts that timer A generates
• Timer B1, timer B2 interrupt
These are interrupts that timer B generates.
________
________
• INT0 interrupt through INT2 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.
46
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for
specifying the address.
Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Low address
Mid address
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 1.11.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector
tables and addresses of vector tables.
Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Vector table addresses
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Remarks
Undefined instruction
Overflow
Interrupt on UND instruction
Interrupt on INTO instruction
BRK instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
FFFF416 to FFFF716
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
Single step (Note)
Watchdog timer
________
DBC (Note)
Do not use
_______
_______
NMI
External interrupt by input to NMI pin
Reset
Note: Interrupts used for debugging purposes only.
47
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user’s settings. Indicate
the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-
dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises
four bytes. Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the
interrupts assigned to the variable vector tables and addresses of vector tables.
Table 1.11.2. Interrupts assigned to the variable vector tables and addresses of vector tables
Vector table address
Software interrupt number
Software interrupt number 0
Interrupt source
BRK instruction
Remarks
Address (L) to address (H)
+0 to +3 (Note 1)
Cannot be masked I flag
Software interrupt number 10
Software interrupt number 11
+40 to +43 (Note 1)
+44 to +47 (Note 1)
Bus collision detection
DMA0
Software interrupt number 13
Software interrupt number 14
Software interrupt number 15
Software interrupt number 16
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
Software interrupt number 23
+52 to +55 (Note 1)
+56 to +59 (Note 1)
+60 to +63 (Note 1)
+64 to +67 (Note 1)
+68 to +71 (Note 1)
+72 to +75 (Note 1)
+76 to +79 (Note 1)
+80 to +83 (Note 1)
+84 to +87 (Note 1)
+88 to +91 (Note 1)
+92 to +95 (Note 1)
Key input interrupt
A-D
UART2 transmit/NACK (Note 2)
UART2 receive/ACK (Note 2)
UART0 transmit
UART0 receive
UART1 transmit
UART1 receive
Timer A0
Timer A1
Timer A2
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
Software interrupt number 32
+108 to +111 (Note 1)
+112 to +115 (Note 1)
+116 to +119 (Note 1)
+120 to +123 (Note 1)
+124 to +127 (Note 1)
+128 to +131 (Note 1)
Timer B1
Timer B2
INT0
INT1
INT2
to
to
Software interrupt
Cannot be masked I flag
Software interrupt number 63
+252 to +255 (Note 1)
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: When IIC mode is selected, NACK and ACK interrupts are selected.
48
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the
priority to be accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level selec-
tion bit, or processor interrupt priority level (IPL). Whether an interrupt request is present or absent is
indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit
are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the
IPL are located in the flag register (FLG).
Figure 1.11.3 shows the memory map of the interrupt control registers.
49
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt control register (Note 2)
Symbol
BCNIC
DM0IC
KUPIC
Address
When reset
004A16
004B16
004D16
004E16
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
ADIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 2)
TBiIC(i=1, 2)
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005716
b7 b6 b5 b4 b3 b2 b1 b0
005B16, 005C16
Bit symbol
Bit name
Function
R
W
Interrupt priority level
select bit
ILVL0
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
0 : Interrupt not requested
1 : Interrupt requested
Interrupt request bit
(Note 1)
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INTiIC(i=0 to 2)
Address
005D16 to 005F16 XX00X000
When reset
0
2
R
W
Bit symbol
ILVL0
Bit name
Function
Interrupt priority level
select bit
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL1
ILVL2
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
(Note 1)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the
interrupt request for that register. For details, see the precautions for interrupts.
Figure 1.11.3. Interrupt control registers
50
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set
to “0” after reset.
Interrupt Request Bit
The interrupt request bit is set to “1” by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to “0” by hardware. The
interrupt request bit can also be set to “0” by software. (Do not set this bit to “1”).
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = “1”
· interrupt request bit = “1”
· interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.11.4. Interrupt levels enabled according
to the contents of the IPL
Table 1.11.3. Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
IPL
Enabled interrupt priority levels
b2 b1 b0
IPL
2
IPL1
IPL0
Level 0 (interrupt disabled)
0
0
0
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0
0
0
1
1
0
Low
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
High
51
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Rewrite the interrupt control register
To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When changing an interrupt control register in a sate of interrupts being disabled, please read the
following precautions on instructions used before changing the register.
Changing a non-interrupt request bit
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
register is being executed, there is a case that the interrupt request bit is not set and consequently the
interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instruc-
tions to change the register.
Instructions : AND, OR, BCLR, BSET
Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : MOV
52
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 0000016. After this, the corresponding interrupt request bit becomes “0”.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence
in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to
“0” (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt response time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.11.4. Interrupt response time
53
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.5.
Table 1.11.5. Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
0000
Address bus
Data bus
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
R
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.11.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is Accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.11.6 is set in the IPL.
Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
_______
Watchdog timer, NMI
7
0
Reset
Other
Not changed
54
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the
interrupt request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
Stack area
Stack area
Address
MSB
Address
MSB
LSB
LSB
[SP]
New stack
pointer value
m – 4
m – 3
m – 2
m – 1
m
m – 4
m – 3
m – 2
m – 1
m
Program counter (PC
Program counter (PC
L
)
M
)
Flag register (FLG )
L
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
Stack pointer
value before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 1.11.6. State of stack before and after acceptance of interrupt request
55
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If
the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.11.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer
indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Sequence in which order
registers are saved
Address
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
Program counter (PC )
L
(2) Saved simultaneously,
all 16 bits
Program counter (PC
Flag register (FLG
M
)
L
)
(1) Saved simultaneously,
all 16 bits
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
Program counter (PC )
L
(3)
(4)
Program counter (PC
Flag register (FLG
M
)
Saved simultaneously,
all 8 bits
L
)
(1)
(2)
Program
counter (PC )
Flag register
(FLG
H
H
)
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.11.7. Operation of saving registers
56
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter
(PC), both of which have been saved in the stack area. Then control returns to the program that was being
executed before the acceptance of the interrupt request, so that the suspended process resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-
tion before executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level
select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware
priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.11.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset > _N__M___I_ > _D__B___C__ > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.11.8. Hardware interrupts priorities
Interrupt resolution circuit
When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest
priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level.
57
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Priority level of each interrupt
INT1
Level 0 (initial value)
High
Timer B2
Timer A1
INT2
INT0
Timer B1
Timer A2
UART1 reception
UART0 reception
Priority of peripheral I/O interrupts
(if priority levels are same)
UART2 reception/ACK
A-D conversion
Bus collision detection
Timer A0
UART1 transmission
UART0 transmission
UART2 transmission/NACK
Key input interrupt
DMA0
Low
Interrupt request level judgment output
to clock generating circuit (Fig.1.10.3)
Processor interrupt priority level (IPL)
Interrupt enable flag (I flag)
Interrupt
request
accepted
Address match
Watchdog timer
DBC
NMI
Reset
Figure 1.11.9. Maskable interrupts priorities (peripheral I/O interrupts)
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Mitsubishi microcomputers
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______
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
INT Interrupt
______
INT Interrupt
________
________
INT0 to INT2 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge
by setting “1” in the INTi interrupt polarity switching bit of the interrupt request cause select register
(035F16). To select both edges, set the polarity switching bit of the corresponding interrupt control register
to ‘falling edge’ (“0”).
Figure 1.11.10 shows the Interrupt request cause select register.
Interrupt request cause select register
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
0
Symbol
IFSR
Address
035F16
When reset
0016
R
W
Bit symbol
Bit name
Function
IFSR0
IFSR1
IFSR2
INT0 interrupt polarity
switching bit
0 : One edge
1 : Two edges
INT1 interrupt polarity
switching bit
0 : One edge
1 : Two edges
INT2 interrupt polarity
switching bit
0 : One edge
1 : Two edges
Reserved bit
Must always be set to “0”
Must always be set to “0”
Must always be set to “0”
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Must always be set to “0”
Must always be set to “0”
Figure 1.11.10. Interrupt request cause select register
59
Mitsubishi microcomputers
M16C / 30L Group
_N___M___I_ Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from “H” to “L”. The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.11.11 shows the block diagram of the key input interrupt. Note that if an
“L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Port P10
4-P107 pull-up
select bit
Pull-up
Key input interrupt control register
(address 004D16
)
transistor
Port P10
register
7 direction
Port P10
7
direction register
P10
7
/KI
3
2
Port P10
register
6 direction
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
P10
6
/KI
Pull-up
transistor
Port P10
register
5
direction
direction
P105/KI1
Port P10
register
4
Pull-up
transistor
P104/KI0
Figure 1.11.11. Block diagram of key input interrupt
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Mitsubishi microcomputers
M16C / 30L Group
Address Match Interrupt
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value
of the program counter (PC) that is saved to the stack area varies depending on the instruction being
executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot
be used for external area.
Figure 1.11.12 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
Function
R W
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
b0
Function
Values that can be set
R W
Address setting register for address match interrupt
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be indeterminated.
Figure 1.11.12. Address match interrupt-related registers
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”.
Even if the address 0000016 is read out by software, “0” is set to the enabled highest priority interrupt
source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in
_______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack
pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat-
_______
ing any interrupts including the NMI interrupt is prohibited.
(3) The _N__M___I_ interrupt
_______
_______
•The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if
unused. Be sure to work on it.
_______
• The NMI pin also serves as P85, which is exclusively input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
_______
when the NMI interrupt is input.
_______
• Do not attempt to go into stop mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI being in the “L” state, the CM10 is fixed to “0”, so attempting to go into stop mode is turned
down.
_______
• Do not attempt to go into wait mode with the input to the NMI pin being in the “L” state. With the input to
_______
the NMI pin being in the “L” state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
_______
• Signals input to the NMI pin require “L” level and “H” level of 2 clock +300ns or more, from the operation
clock of the CPU.
(4) External interrupt
________
• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT2 regardless of the CPU operation clock.
________
________
• When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to “1”.
After changing the polarity, set the interrupt request bit to “0”. Figure 1.11.13 shows the procedure for
______
changing the INT interrupt generate factor.
Clear the interrupt enable flag to “0”
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
NOP X 2
Clear the interrupt request bit to “0”
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to “1”
(Enable interrupt)
Note: Execute the setting above individually. Don't execute two or
more settings at once(by one instruction).
______
Figure 1.11.13. Switching condition of INT interrupt request
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(5) Watchdog timer interrupt
• Write to the watchdog timer start register after the watchdog timer interrupt occurs (initialize watchdog
timer).
(6) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for
that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1:
INT_SWITCH1:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
NOP
NOP
FSET
; Four NOP instructions are required when using HOLD function.
; Enable interrupts.
I
Example 2:
INT_SWITCH2:
FCLR
I
; Disable interrupts.
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
MOV.W MEM, R0
; Dummy read.
; Enable interrupts.
FSET
I
Example 3:
INT_SWITCH3:
PUSHC FLG
; Push Flag register onto stack
; Disable interrupts.
FCLR
I
AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit.
POPC FLG ; Enable interrupts.
The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When changing an interrupt control register in a sate of interrupts being disabled, please read the
following precautions on instructions used before changing the register.
Changing a non-interrupt request bit
If an interrupt request for an interrupt control register is generated during an instruction to rewrite the
register is being executed, there is a case that the interrupt request bit is not set and consequently the
interrupt is ignored. This will depend on the instruction. If this creates problems, use the below instruc-
tions to change the register.
Instructions : AND, OR, BCLR, BSET
Changing the interrupt request bit
When attempting to clear the interrupt request bit of an interrupt control register, the interrupt request bit
is not cleared sometimes. This will depend on the instruction. If this creates problems, use the below
instructions to change the register.
Instructions : MOV
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Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. Whether a watchdog timer
interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. When the
watchdog timer interrupt is selected, write to the watchdog timer start register after the watchdog timer
interrupt occurs (initialize watchdog timer). Watchdog timer interrupt is selected when bit 2 (PM12) of the
processor mode register 1 (address 000516) is "0" and reset is selected when PM12 is "1". No value other
than "1" can be written in PM12. Once when reset is selected (PM12="1"), watchdog timer interrupt cannot
be selected by software.
When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the
prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for
division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16). Thus the watchdog
timer's period can be calculated as given below. The watchdog timer's period is, however, subject to an
error due to the prescaler.
With XIN chosen for BCLK
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
Watchdog timer period =
BCLK
With XCIN chosen for BCLK
prescaler dividing ratio (2) X watchdog timer count (32768)
Watchdog timer period =
BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when
a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state, the
watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or
state are released.
Also PM12 is initialized only when reset. The watchdog timer interrupt is selected after reset is cancelled.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Prescaler
1/16
“CM07 = 0”
“WDC7 = 0”
“PM12 = 0”
Watchdog timer
interrupt request
“CM07 = 0”
“WDC7 = 1”
BCLK
HOLD
1/128
1/2
Watchdog timer
Reset
“PM12 = 1”
“CM07 = 1”
Write to the watchdog timer
start register
(address 000E16
Set to
“7FFF16
)
”
RESET
Figure 1.12.1. Block diagram of watchdog timer
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
000XXXXX
0
0
2
Bit symbol
Bit name
Function
R W
High-order bit of watchdog timer
Reserved bit
Must always be set to “0”
Must always be set to “0”
Reserved bit
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
The watchdog timer is initialized and starts counting after a write instruction to
R W
this register. The watchdog timer value is always initialized to “7FFF16
regardless of whatever value is written.
”
Figure 1.12.2. Watchdog timer control and start registers
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Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAC
This microcomputer has one DMAC (direct memory access controller) channel that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this
account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-
bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram
of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers
used by the DMAC.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
)
(addresses 002616 to 002416
)
DMA0 transfer counter reload register TCR0 (16)
DMA0 forward address pointer (20) (Note)
(addresses 002916, 002816
)
DMA0 transfer counter TCR0 (16)
DMA latch high-order bits DMA latch low-order bits
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.13.1. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request
signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA
transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Table 1.13.1. DMAC specifications
Item
No. of channels
Transfer memory space
Specification
2 (cycle steal method)
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA-related registers [002016 to 003F16] cannot be accessed)
Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
________
DMA request factors (Note)
Falling edge of INT0 or both edge
Timer A0 to timer A2 interrupt requests
Timer B1 and timer B2 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
A-D conversion interrupt requests
Software triggers
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to
“0”, and the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.
The DMAC remains active unless a “0” is written to the DMA enable bit.
DMA interrupt request generation timing When an underflow occurs in the transfer counter
Active
When the DMA enable bit is set to “1”.
When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.
Inactive
• When the DMA enable bit is set to “0”.
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer, and the value
of the transfer counter reload register is reloaded to the transfer counter.
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is “0”.
Reload timing for forward
address pointer and transfer
counter
Writing to register
Reading the register
Can be read at any time.
However, when the DMA enable bit is “1”, reading the register set up as the
forward register is the same as reading the value of the forward address pointer.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable
flag (I flag) nor by the interrupt priority level.
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Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA0 request cause select register
Symbol
DM0SL
Address
03B816
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Function
Bit symbol
DSEL0
Bit name
R
W
b6 b5 b4 b3 b2 b1 b0
(DMS)
DMA request cause
select bit
0 0 0 0 0 0 0 : Falling edge of INT0 pin
0 0 0 0 0 0 1 : Software trigger
0 0 0 0 0 1 0 : Timer A0
0 0 0 0 0 1 1 : Timer A1
0 0 0 0 1 0 0 : Timer A2
0 0 0 0 1 0 1 : Must not be set
0 0 0 0 1 1 0 : Must not be set
0 0 0 0 1 1 1 : Must not be set
0 0 0 1 0 0 0 : Timer B1
DSEL1
DSEL2
DSEL3
DSEL4
DSEL5
DMS
0 0 0 1 0 0 1 : Timer B2
0 0 0 1 0 1 0 : UART0 transmit
0 0 0 1 0 1 1 : UART0 receive
0 0 0 1 1 0 0 : UART2 transmit
0 0 0 1 1 0 1 : UART2 receive
0 0 0 1 1 1 0 : A-D conversion
0 0 0 1 1 1 1 : UART1 transmit
1 0 0 0 1 1 0 : Two edges of INT0 pin
Must not be set except the above.
If software trigger is selected, a
DMA request is generated by
setting this bit to “1” (When read,
the value of this bit is always “0”)
Software DMA
request bit
DSR
Figure 1.13.2. DMAC register (1)
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Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA0 control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
Address
002C16
When reset
00000X002
Bit symbol
Bit name
Function
R
W
Transfer unit bit select bit 0 : 16 bits
1 : 8 bits
DMBIT
DMASL
DMAS
DMAE
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
DMA request bit (Note 1)
DMA enable bit
(Note 2)
0 : Disabled
1 : Enabled
Source address direction
select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Destination address
direction select bit (Note 3)
0 : Fixed
1 : Forward
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to “0”.
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to “1” simultaneously.
Figure 1.13.3. DMAC register (2)
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Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA0 source pointer
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
Address
002216 to 002016
When reset
Indeterminate
Transfer address
specification
Function
R W
• Source pointer
Stores the source address
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMA0 destination pointer
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
Address
002616 to 002416
When reset
Indeterminate
Transfer address
specification
Function
R W
• Destination pointer
Stores the destination address
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
DMA0 transfer counter
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
Address
002916, 002816
When reset
Indeterminate
Transfer count
specification
Function
R W
• Transfer counter
Set a value one less than the transfer count
000016 to FFFF16
Figure 1.13.4. DMAC register (3)
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = “H”) in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destina-
tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.
In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-
tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure
1.13.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the
source read cycle and the destination write cycle.
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Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1 Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.13.5. Example of the transfer cycles for a source read
72
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.13.2. No. of DMAC transfer cycles
Single-chip mode
Memory expansion mode
Microprocessor mode
Transfer unit
Bus width
Access address
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
(BYTE= “L”)
8-bit
Even
Odd
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
8-bit transfers
(DMBIT= “1”)
Even
Odd
—
—
1
—
—
1
(BYTE = “H”)
16-bit
Even
Odd
16-bit transfers
(DMBIT= “0”)
(BYTE = “L”)
8-bit
2
2
Even
Odd
—
—
—
—
(BYTE = “H”)
Coefficient j, k
Internal memory
External memory
Separate bus Separate bus Multiplex
Internal ROM/RAM Internal ROM/RAM
SFR area
2
No wait
1
With wait
2
No wait
1
With wait
2
bus
3
73
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA enable bit
Setting the DMA enable bit to “1” makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the
forward direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting “1” to the DMA enable bit with the DMAC being active carries out the operations given
above, so the DMAC operates again from the initial state at the instant “1” is overwritten to the DMA
enable bit.
DMA request bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors.
DMA request factors include the following.
* Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
* External factors effected by utilizing the input from external interrupt signals.
For the selection of DMA request factors, see the descriptions of the DMA0 factor selection register.
The DMA request bit turns to “1” if the DMA transfer request signal occurs regardless of the DMAC's state
(regardless of whether the DMA enable bit is set to “1” or “0”). It turns to “0” immediately before data
transfer starts.
In addition, it can be set to “0” by use of a program, but cannot be set to “1”.
There can be instances in which a change in DMA request factor selection bit causes the DMA request bit
to turn to “1”. So be sure to set the DMA request bit to “0” after the DMA request factor selection bit is
changed.
The DMA request bit turns to “1” if a DMA transfer request signal occurs, and turns to “0” immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be “0” in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to “1” due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to “1” due to several factors.
Turning the DMA request bit to “0” due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors
________
An external factor is a factor caused to occur by the leading edge of input from the INT0 pin.
________
Selecting the INT0 pins as external factors using the DMA request factor selection bit causes input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to “1” when an external factor is selected synchronizes with the
signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes
________
with the trailing edge of the input signal to INT0 pin, for example).
With an external factor selected, the DMA request bit is timed to turn to “0” immediately before data
transfer starts similarly to the state in which an internal factor is selected.
74
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Timer
There are five 16-bit timers. These timers can be classified by function into timers A (three) and timers B
(two). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers.
Clock prescaler
f
f
1
8
fC32
XIN
1/32
Reset
X
CIN
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
f
32
1/4
f1 f8 f32 fC32
• Timer mode
• One-shot timer mode
• PWM mode
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A0
Noise
filter
TA0IN
TA1IN
TA2IN
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A1
Noise
filter
• Event counter mode
• Timer mode
• One-shot timer mode
• PWM mode
Timer A2
Noise
filter
• Event counter mode
Timer B2 overflow
Note : The TA0IN pin (P71) is shared with RxD2, so be careful.
Figure 1.14.1. Timer A block diagram
75
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Clock prescaler
f
f
1
8
fC32
XIN
1/32
Reset
X
CIN
1/8
Clock prescaler reset flag (bit 7
at address 038116) set to “1”
f
32
1/4
f1 f8 f32 fC32
• Timer mode
• Pulse width measuring mode
Timer B1 interrupt
Noise
filter
TB1IN
TB2IN
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B2 interrupt
Timer A
Noise
filter
Timer B2
• Event counter mode
Figure 1.14.2. Timer B block diagram
76
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related
registers.
Except in event counter mode, timers A0 through A2 all have the same function. Use the timer Ai mode
register (i = 0 to 2) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• One-shot timer mode: The timer stops counting when the count reaches “000016”.
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f
1
Low-order
8 bits
High-order
8 bits
Clock selection
f8
• Timer
(gate function)
f
32
Reload register (16)
f
C32
• Event counter
Counter (16)
Polarity
selection
Up count/down count
Clock selection
TAiIN
Always down count except
in event counter mode
(i = 0 to 2)
Count start flag
(Address 038016
)
TAi
Addresses
TAj
TAk
Timer A0 038716 038616 Must not be set
Timer A1
Timer A2
Must not be set
TB2 overflow
TAj overflow
To external
trigger circuit
Timer A1 038916 038816
Timer A2 038B16 038A16
Timer A0
Timer A1
Down count
(j = i – 1. Note, however, must not be set when i = 0)
Up/down flag
TAk overflow
(k = i + 1. Note, however, must not be set when i = 2)
(Address 038416
)
Pulse output
TAiOUT
(i = 0 to 2)
Toggle flip-flop
Figure 1.14.3. Block diagram of timer A
Timer Ai mode register
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i=0 to 2) 039616 to 039816
R W
Bit symbol
TMOD0
Bit name
Function
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.14.4. Timer A-related registers (1)
77
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai register (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA0
TA1
Address
When reset
Indeterminate
Indeterminate
Indeterminate
038716,038616
038916,038816
038B16,038A16
TA2
Values that can be set
R W
Function
• Timer mode
000016 to FFFF16
Counts an internal count source
• Event counter mode
000016 to FFFF16
Counts pulses from an external source or timer overflow
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
(Note 2,4)
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
(Note 3,4)
0016 to FE16
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
(High-order address)
0016 to FF16
(Low-order address)
(Note 3,4)
Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to “000016”, the counter does not
operate and the timer Ai interrupt request is not generated. When the
pulse is set to output, the pulse does not output from the TAiOUT pin.
Note 3: When the timer Ai register is set to “000016”, the pulse width modulator
does not operate and the output level of the TAiOUT pin remains “L”
level, therefore the timer Ai interrupt request is not generated. This also
occurs in the 8-bit pulse width modulator mode when the significant 8
high-order bits in the timer Ai register are set to “0016”.
Note 4: Use MOV instruction to write to this register.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
Symbol
TABSR
Address
038016
When reset
0016
Bit symbol
TA0S
Bit name
Function
0 : Stops counting
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
1 : Starts counting
TA1S
TA2S
Reserved bit
Must always be set to “0”
TB1S
TB2S
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Up/down flag (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
038416
When reset
0016
0
0
0 0
R W
Bit symbol
TA0UD
Bit name
Function
0 : Down count
Timer A0 up/down flag
1 : Up count
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
TA1UD
TA2UD
Timer A1 up/down flag
Timer A2 up/down flag
Reserved bit
Must always be set to “0”
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled (Note 2)
Timer A2 two-phase pulse
signal processing select bit
TA2P
When not using the two-phase
pulse signal processing function,
set the select bit to “0”
Reserved bit
Must always be set to “0”
Note 1: Use MOV instruction to write to this register.
Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers to “0”.
Figure 1.14.5. Timer A-related registers (2)
78
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
Symbol
ONSF
Address
038216
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00X00000
2
0
0
R W
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
TA0OS
TA1OS
TA2OS
1 : Timer start
When read, the value is “0”
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
b7 b6
TA0TGL
TA0TGH
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : Must not be set
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to “0”.
Trigger select register
Symbol
TRGSR
Address
038316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0
0
0
0
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : Must not be set
TA2TGH
Reserved bit
Must always be set to “0”
Note: Set the corresponding port direction register to “0”.
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is “0”)
Figure 1.14.6. Timer A-related registers (3)
79
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7
shows the timer Ai mode register in timer mode.
Table 1.14.1. Specifications of timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Down count
•
When the timer underflows, it reloads the reload register contents before continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing When the timer underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
• Gate function
Select function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i=0 to 2) 039616 to 039816
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held “L” (Note 3)
1 1 : Timer counts only when TAiIN pin is
held “H” (Note 3)
MR3
0 (Must always be “0” in timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register
are invalid.
Note 2: The bit can be “0” or “1”.
Note 3: Set the corresponding port direction register to “0”.
Figure 1.14.7. Timer Ai mode register in timer mode
80
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer’s overflow. Timers A0 and A1 can
count a single-phase external signal. Timer A2 can count a single-phase and a two-phase external
signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal. Figure
1.14.8 shows the timer Ai mode register in event counter mode.
Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.9 shows
the timer Ai mode register in event counter mode.
Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
External signals input to TAiIN pin (effective edge can be selected by software)
• TB2 overflow, TAj overflow
Count operation
• Up count or down count can be selected by external signal or software
• When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
1/ (FFFF16 - n + 1) for up count
Divide ratio
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
• Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
0
0 1
TAiMR(i = 0 to 2) 039616 to 039816
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode (Note 1)
0 : Pulse is not output
Pulse output function
select bit
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
Count polarity
select bit (Note 3)
MR1
MR2
0 : Counts external signal's falling edge
1 : Counts external signal's rising edge
Up/down switching
cause select bit
0 : Up/down flag's content
1 : TAiOUT pin's input signal (Note 4)
MR3
0 (Must always be “0” in event counter mode)
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
TCK1
Invalid when not using two-phase pulse signal processing
Can be “0” or “1”
Note 1: In event counter mode, the count source is selected by the event / trigger select bit
(addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an “L” signal is input to the TAiOUT pin, the downcount is activated. When “H”,
the upcount is activated. Set the corresponding port direction register to “0”.
Figure 1.14.8. Timer Ai mode register in event counter mode
81
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.14.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timer A2)
Item
Specification
Count source
• Two-phase pulse signals input to TA2IN or TA2OUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note)
Count operation
Divide ratio
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
Count start flag is set (= 1)
Count start flag is reset (= 0)
n : Set value
Count start condition
Count stop condition
Interrupt request generation timing Timer overflows or underflows
TA2IN pin function
TA2OUT pin function
Read from timer
Write to timer
Two-phase pulse input (Set the TA2IN pin correspondent port direction register to “0”.)
Two-phase pulse input (Set the TA2OUT pin correspondent port direction register to “0”.)
Count value can be read out by reading timer A2 register
• When counting stopped
When a value is written to timer A2 register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer A2 register, it is written to only reload
register. (Transferred to counter at next reload time.)
• Normal processing operation
Select function
The timer counts up rising edges or counts down falling edges on the TA2IN
pin when input signal on the TA2OUT pin is “H”.
TA2OUT
TA2IN
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
Note: This does not apply when the free-run function is selected.
82
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai mode register
(When using two-phase pulse signal processing) (Note)
Symbol
TA2MR
Address
039816
When reset
0016
b6 b5 b4 b3 b2 b1 b0
0
0 1 0 0 0 1
Bit name
Operation mode select bit
Function
0 1 : Event counter mode
R W
b1 b0
TMOD0
TMOD1
MR0
0 (Must always be “0” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR1
MR2
1 (Must always be “1” when using two-phase pulse signal
processing)
0 (Must always be “0” when using two-phase pulse signal
processing)
MR3
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
0 (Must always be “0” when using two-phase pulse signal
processing)
TCK1
Note : When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to “1”. Also, always be
sure to set the event/trigger select bit (address 038316) to “00”.
Figure 1.14.9. Timer Ai mode register in event counter mode
83
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.14.10 shows the timer Ai mode register in one-shot
timer mode.
Table 1.14.4. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down
• When the count reaches 000016, the timer stops counting after reloading a new count
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide ratio
1/n
n : Set value
Count start condition
• An external trigger is input
• The timer overflows
• The one-shot start flag is set (= 1)
• A new count is reloaded after the count has reached 000016
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing The count reaches 000016
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Programmable I/O port or pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 0 to 2) 039616 to 039816
0
1 0
Bit symbol
Bit name
R W
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
MR2
0 : Falling edge of TAiIN pin's input signal (Note 3)
1 : Rising edge of TAiIN pin's input signal (Note 3)
External trigger select
bit (Note 2)
0 : One-shot start flag is valid
1 : Selected by event/trigger select
bits
Trigger select bit
MR3
0 (Must always be “0” in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
1
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 3: Set the corresponding port direction register to “0”.
Figure 1.14.10. Timer Ai mode register in one-shot timer mode
84
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the
counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure
1.14.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.12 shows the
example of how a 16-bit pulse width modulator operates. Figure 1.14.13 shows the example of how an 8-
bit pulse width modulator operates.
Table 1.14.5. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
The timer reloads a new count at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs when counting
• High level width n / fi n : Set value
(2 -1) / fi fixed
•
16-bit PWM
16
(m+1) / fi
• Cycle time
•
•
8-bit PWM
High level width
Cycle time
n
(2
n : values set to timer Ai register’s high-order address
-1) (m+1) / fi m : values set to timer Ai register’s low-order address
8
Count start condition
• External trigger is input
• The timer overflows
• The count start flag is set (= 1)
• The count start flag is reset (= 0)
Count stop condition
Interrupt request generation timing PWM pulse goes “L”
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
1
1
1
TAiMR(i=0 to 2) 039616 to 039816
R W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 1 : PWM mode
MR0
MR1
1 (Must always be “1” in PWM mode)
External trigger select
bit (Note 1)
0: Falling edge of TAiIN pin's input signal (Note 2)
1: Rising edge of TAiIN pin's input signal (Note 2)
MR2
MR3
0: Count start flag is valid
1: Selected by event/trigger select bits
Trigger select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit
(addresses 038216 and 038316). If timer overflow is selected, this bit can be “1” or “0”.
Note 2: Set the corresponding port direction register to “0”.
Figure 1.14.11. Timer Ai mode register in pulse width modulation mode
85
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition : Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X
(216 – 1)
Count source
“H”
“L”
TAiIN pin
input signal
Trigger is not generated by this signal
1 / f
i
X n
“H”
“L”
PWM pulse output
from TAiOUT pin
“1”
“0”
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
1
8
)
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16
.
Figure 1.14.12. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi X (m + 1) X (28 – 1)
Count source (Note1)
“H”
TAiIN pin input signal
“L”
1 / fi X (m + 1)
“H”
Underflow signal of
8-bit prescaler (Note2)
“L”
1 / fi X (m + 1) X n
“H”
PWM pulse output
from TAiOUT pin
“L”
“1”
Timer Ai interrupt
request bit
“0”
fi
: Frequency of count source
(f , f , f32, fC32
Cleared to “0” when interrupt request is accepted, or cleaerd by software
1
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 0016 to FF16; n = 0016 to FE16
.
Figure 1.14.13. Example of how an 8-bit pulse width modulator operates
86
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.14.14 shows the block diagram of timer B. Figures 1.14.15 and 1.14.16 show the timer B-related
registers.
Use the timer Bi mode register (i = 1, 2) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f
1
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f
f
8
Clock selection
32
fC32
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 1, 2)
(address 038016
)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
TBj overflow
(j = i – 1. Note, however,
must not be set when i = 1)
Timer B1 039316 039216 Must not be set
Timer B2 039516 039416 Timer B1
Figure 1.14.14. Block diagram of timer B
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i = 1, 2)
039C16, 039D16
00XX00002
R
W
Bit symbol
TMOD0
Function
Bit name
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
TMOD1
1 1 : Must not be set.
MR0
MR1
Function varies with each operation mode
Nothing is assigned.
In an attempt to write to these bits, write “0”.
The value, if read, turns out to be indeterminate.
Function varies with each operation mode
MR3
TCK0
Count source select bit
(Function varies with each operation mode)
TCK1
Figure 1.14.15. Timer B-related registers (1)
87
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer Bi register (Note)
(b15)
b7
(b8)
b0 b7
Symbol
TB1
TB2
Address
When reset
039316, 039216 Indeterminate
039516, 039416 Indeterminate
b0
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts the timer's period
• Event counter mode
000016 to FFFF16
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
Symbol
TABSR
Address
038016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0
R W
Bit symbol
TA0S
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
Reverved bit
Must always be set to “0”
TB1S
TB2S
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
b7 b6 b5 b4 b3 b2 b1 b0
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be indeterminate.
0 : No effect
1 : Prescaler is reset
(When read, the value is “0”)
CPSR
Clock prescaler reset flag
Figure 1.14.16. Timer B-related registers (2)
88
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.6.) Figure 1.14.17
shows the timer Bi mode register in timer mode.
Table 1.14.6. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
Symbol
TBiMR(i=1, 2)
Address
039C16, 039D16
When reset
00XX0000
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0
Bit symbol
R
W
Bit name
Function
0 0 : Timer mode
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
Invalid in timer mode
Can be “0” or “1”
MR1
Nothing is assiigned.
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
Invalid in timer mode.
MR3
In an attempt to write to this bit, write “0”. The value, if read in
timer mode, turns out to be indeterminate.
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
1
8
0 1 : f
1 0 : f32
1 1 : fC32
Figure 1.14.17. Timer Bi mode register in timer mode
89
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.7.)
Figure 1.14.18 shows the timer Bi mode register in event counter mode.
Table 1.14.7. Timer specifications in event counter mode
Item
Specification
• External signals input to TBiIN pin
Count source
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
Count operation
• Counts down
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= 1)
Count start flag is reset (= 0)
Interrupt request generation timing The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i=1, 2)
039C16, 039D16
00XX0000
2
0
1
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
Operation mode select bit
0 1 : Event counter mode
TMOD1
b3 b2
Count polarity select
bit (Note 1)
MR0
MR1
0 0 : Counts external signal's
falling edges
0 1 : Counts external signal's
rising edges
1 0 : Counts external signal's
falling and rising edges
1 1 : Must not be set.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read,
turns out to be indeterminate.
Invalid in event counter mode.
MR3
In an attempt to write to this bit, write “0”. The value, if read in
event counter mode, turns out to be indeterminate.
Invalid in event counter mode.
TCK0
Can be “0” or “1”.
0 : Input from TBiIN pin (Note 2)
1 : TBj overflow
Event clock select
TCK1
(j = i – 1; however, must not be set,
when i = 1)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer's overflow is selected, this bit can be “0” or “1”.
Note 2: Set the corresponding port direction register to “0”.
Figure 1.14.18. Timer Bi mode register in event counter mode
90
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.8.)
Figure 1.14.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.14.20 shows the operation timing when measuring a pulse period. Figure 1.14.21 shows the operation
timing when measuring a pulse width.
Table 1.14.8. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f1, f8, f32, fC32
• Up count
• Counter value “000016” is transferred to reload register at measurement
pulse's effective edge and the timer continues counting
Count start flag is set (= 1)
Count start condition
Count stop condition
Count start flag is reset (= 0)
Interrupt request generation timing • When measurement pulse's effective edge is input (Note 1)
• When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to “1”. Assume that the count start flag condition is “1” and then the
timer Bi overflow flag becomes “1”. If the timer Bi mode register has a write-
access after next count cycle of the timer from the above condition, the timer
Bi overflow flag becomes “0”.)
TBiIN pin function
Read from timer
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input
after the timer has started counting.
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBiMR(i=1, 2)
Address
039C16, 039D16
When reset
00XX0000
2
1
0
R
W
Bit symbol
Bit name
Function
b1 b0
TMOD0
TMOD1
Operation mode
select bit
1 0 : Pulse period / pulse width
measurement mode
b3 b2
MR0
MR1
Measurement mode
select bit
0 0 : Pulse period measurement (Interval between
measurement pulse's falling edge to falling edge)
0 1 : Pulse period measurement (Interval between
measurement pulse's rising edge to rising edge)
1 0 : Pulse width measurement (Interval between
measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)
1 1 : Must not be set.
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
Timer Bi overflow
flag (Note)
0 : Timer did not overflow
1 : Timer has overflowed
MR3
b7 b6
TCK0
TCK1
Count source
select bit
0 0 : f
0 1 : f
1 0 : f32
1 1 : fC32
1
8
Note: It is indeterminate when reset. Assume that the count start flag condition is “1” and then the timer Bi
overflow flag becomes “1”. If the timer Bi mode register has a write access after next count cycle of
the timer from the above condition, the timer
to “1” by software.
Bi overflow flag becomes “0”. This flag cannot be set
Figure 1.14.19. Timer Bi mode register in pulse period/pulse width measurement mode
91
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
“H”
“L”
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.14.20. Operation timing when measuring a pulse period
Count source
“H”
Measurement pulse
“L”
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches “000016
”
“1”
“0”
Count start flag
“1”
“0”
Timer Bi interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software.
“1”
“0”
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.14.21. Operation timing when measuring a pulse width
92
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as three channels: UART0, UART1, UART2.
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show
the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 037816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.
UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous
serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if
the TxD pin and the RxD pin are different in level.
Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 to 1.16.9
show the registers related to UARTi.
Note: SIM : Subscriber Identity Module
Table 1.16.1. Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
Possible
CLK polarity selection
Possible
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
Possible (Note 1)
(Note 1)
(Note 2)
(Note 1)
LSB first / MSB first selection
Possible
Possible
Possible
Impossible
Possible
Impossible
Possible
Continuous receive mode selection
Possible
Transfer clock output from multiple
pins selection
Impossible
Impossible
Possible
Serial data logic switch
Sleep mode selection
Impossible
(Note 4)
(Note 3) Possible (Note 3)
Impossible
TxD, RxD I/O polarity switch
TxD, RxD port output format
Parity error signal output
Bus collision detection
Impossible
N-channel open-drain
output
CMOS output
Impossible
Impossible
CMOS output
Impossible
Impossible
Possible
Possible
(Note 4)
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
93
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
(UART0)
RxD0
TxD0
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
f
f
f
1
Internal
(address 03A116
)
8
Transmit
clock
UART transmission
32
1 / (n0+1)
1/16
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
RTS
0
CTS0 / RTS0
Vcc
CTS/RTS disabled
CTS
0
(UART1)
RxD1
TxD
1
UART reception
Receive
clock
1/16
Transmit/
receive
unit
Reception
control circuit
Clock source selection
Bit rate generator
(address 03A916
Clock synchronous type
f
1
)
Internal
f
8
UART transmission
1/16
Transmit
clock
1 / (n1+1)
f
32
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
External
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK1
CTS/RTS disabled
CTS/RTS selected
RTS
1
CTS
1
/ RTS
1
/
V
CC
CLKS
1
Clock output pin
select switch
CTS/RTS disabled
CTS
1
(UART2)
TxD
RxD polarity
reversing circuit
polarity
reversing
circuit
RxD
2
TxD
2
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
(address 037916
f
f
f
1
Internal
)
8
UART transmission
1/16
Transmit
clock
32
1 / (n2+1)
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
(when internal clock is selected)
1/2
Clock synchronous type
(when external clock is
selected)
Clock synchronous type
(when internal clock is selected)
CLK
polarity
reversing
circuit
CLK2
CTS/RTS
selected
CTS/RTS disabled
RTS
2
CTS
2
/ RTS
2
Vcc
CTS/RTS disabled
CTS
2
n0 : Values set to UART0 bit rate generator (U0BRG)
n1 : Values set to UART1 bit rate generator (U1BRG)
n2 : Values set to UART2 bit rate generator (U2BRG)
Figure 1.16.1. Block diagram of UARTi (i = 0 to 2)
94
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous type
UART (7 bits)
UART (8 bits)
Clock
UARTi receive register
synchronous
type
UART (7 bits)
PAR
disabled
1SP
2SP
SP
SP
PAR
RxDi
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D
8
D7
D
6
D5
D
4
D
3
D2
D
1
D0
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTi transmit
buffer register
D7
D
6
D
5
D4
D
3
D
2
D1
D0
D8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (9 bits)
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
TxDi
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
SP: Stop bit
PAR: Parity bit
“0”
Clock synchronous
type
Figure 1.16.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
95
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
No reverse
Reverse
RxD data
reverse circuit
RxD2
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
type
UART2 receive register
PAR
disabled
UART(7 bits)
1SP
SP
PAR
SP
2SP
Clock
synchronous type
PAR
enabled
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UART2 receive
buffer register
0
0
0
0
0
0
0
D8
D7
D
6
D5
D4
D3
D2
D1
D
0
Address 037E16
Address 037F16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2 transmit
buffer register
D7
D6
D5
D4
D3
D
2
D1
D0
D8
Address 037A16
Address 037B16
UART
(8 bits)
UART
(9 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
UART
2SP
SP
SP
PAR
1SP
Clock
synchronous
type
PAR
disabled
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART2 transmit register
“0”
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
TxD2
Reverse
Error signal output
enable
SP: Stop bit
PAR: Parity bit
Figure 1.16.3. Block diagram of UART2 transmit/receive unit
96
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register (Note)
Symbol
U0TB
U1TB
U2TB
Address
When reset
(b15)
b7
(b8)
03A316, 03A216
03AB16, 03AA16
037B16, 037A16
Indeterminate
Indeterminate
Indeterminate
b0 b7
b0
Function
R W
Transmit data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register
(b8)
b0 b7
(b15)
b7
Symbol
U0RB
U1RB
U2RB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
b0
03A716, 03A616
03AF16, 03AE16
037F16, 037E16
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Receive data
Receive data
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Arbitration lost detecting
flag (Note 2)
0 : Not detected
1 : Detected
Invalid
ABT
Overrun error flag (Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
OER
FER
PER
SUM
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
Parity error flag (Note 1)
Error sum flag (Note 1)
Invalid
Invalid
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note 1: Bits 15 through 12 are set to “0” when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016,
03A816 and 037816) are set to “0002” or the receive enable bit is set to “0”.
(Bit 15 is set to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 037E16) is read out.
Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but “0” may be written. Nothing is
assigned in bit 11 of U0RB and U1RB. When write, set “0”. The value, if read, turns out to be “0”.
UARTi bit rate generator (Note 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
037916
When reset
Indeterminate
Indeterminate
Indeterminate
b7
b0
R W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.
Figure 1.16.4. Serial I/O-related registers (1)
97
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must always be “001”
b2 b1 b0
SMD0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
1 1 1 : Must not be set.
SMD1
SMD2
1 1 1 : Must not be set.
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note)
0 : Internal clock
1 : External clock (Note)
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Sleep select bit
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Must always be “0”
Note : Set the corresponding port direction register to “0”.
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
SMD0
Must always be “001”
b2 b1 b0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
0 0 0 : Serial I/O invalid
0 1 0 : (Note 1)
0 1 1 : Must not be set.
1 1 1 : Must not be set.
SMD1
SMD2
1 1 1 : Must not be set.
CKDIR
STPS
PRY
Must always be “0”
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 2)
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = “1”
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
Parity enable bit
Invalid
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
IOPOL
Usually set to “0”
Usually set to “0”
Note 1: Bit 2 to bit 0 are set to “010
2
” when I2C mode is used.
Note 2: Set the corresponding port direction register to “0”.
Figure 1.16.5. Serial I/O-related registers (2)
98
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
03A416, 03AC16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
b1 b0
b1 b0
CLK0 BRG count source
select bit
0 0 : f
0 1 : f
1
8
is selected
is selected
0 0 : f
0 1 : f
1
8
is selected
is selected
1 0 : f32 is selected
1 1 : Must not be set.
1 0 : f32 is selected
1 1 : Must not be set.
CLK1
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
NCH
CTS/RTS disable bit
Data output select bit
(P6
0 and P64 function as
(P6
0 and P64 function as
programmable I/O port)
programmable I/O port)
0 : T
1 : T
X
X
Di pin is CMOS output
Di pin is N-channel
0: T
1: T
X
X
Di pin is CMOS output
Di pin is N-channel
open-drain output
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
UFORM Transfer format select bit
Must always be “0”
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C0
Address
037C16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
R W
Bit name
symbol
b1 b0
b1 b0
CLK0
CLK1
BRG count source
select bit
0 0 : f
0 1 : f
1 0 : f32 is selected
1 1 : Must not be set.
1
8
is selected
is selected
0 0 : f
0 1 : f
1 0 : f32 is selected
1 1 : Must not be set.
1
8
is selected
is selected
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = “0”
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
CTS/RTS disable bit
(P7
3
functions
(P73 functions programmable
programmable I/O port)
I/O port)
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be “0”.
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be “0”
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
Transfer format select bit
(Note 3)
UFORM
Note 1: Set the corresponding port direction register to “0”.
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.16.6. Serial I/O-related registers (3)
99
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
03A516 03AD16
When reset
0216
,
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
TE
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
TI
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
037D16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit name
symbol
R W
TE
TI
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty
0 : Transmit buffer empty
(TI = 1)
cause select bit
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Must always be "0"
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Error signal output
enable bit
Must always be "0"
0 : Output disabled
1 : Output enabled
Figure 1.16.7. Serial I/O-related registers (4)
100
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X0000000
0
2
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
U0RRM UART0 continuous
0 : Continuous receive
mode disabled
Must always be “0”
receive mode enable bit
1 : Continuous receive
mode enable
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Must always be “0”
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = “1”
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Normal mode
Must always be “0”
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = “0”.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
8016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
I2C mode select bit
R W
0 : Normal mode
1 : I2C mode
Must always be “0”
Must always be “0”
IICM
ABC
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
BBS
Bus busy flag
Must always be “0”
Must always be “0”
(Note1)
LSYN SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling
clock select bit
Must always be “0”
Must always be “0”
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ABSCS
ACSE
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of R
Transmit start condition
select bit
SSS
XD2
0 : Must always be “0”
when not using I2C mode
1 : Digital delay output
is selected
Must always be “0”
SDA digital delay select
bit (Note 2)
SDDS
Note 1: Nothing but “0” may be written.
Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this
bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be
read or written to.
Figure 1.16.8. Serial I/O-related registers (5)
101
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART2 special mode register 2 (I2C bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
When reset
0016
Function
Bit
symbol
Bit name
R W
2
(I C bus exclusive use)
2
I C mode select bit 2
Clock-synchronous bit
SCL wait output bit
Refer to Table 1.16.11
IICM2
CSC
0 : Disabled
1 : Enabled
SWC
0 : Disabled
1 : Enabled
ALS
SDA output stop bit
UART2 initialization bit
SCL wait output bit 2
SDA output disable bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
STAC
SWC2
0: UART2 clock
1: 0 output
0: Enabled
SDHI
1: Disabled (high impedance)
1: Set this bit to “1” in I2C mode
(refer to Table 1.16.12)
SHTC
Start/stop condition
control bit
UART2 special mode register 3 (I2C bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
When reset
0016
Function
(I2C bus exclusive use register)
Bit
symbol
Bit name
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
SDA digital delay setup
bit
(Note 1, Note 2, Note 3)
DL0
DL1
DL2
b7 b6 b5
0 0 0 : Must not be set when using I2C mode
0 0 1 : 1 to 2 cycle(s) of 1/f(XIN
)
0 1 0 : 2 to 3 cycles of 1/f(XIN
0 1 1 : 3 to 4 cycles of 1/f(XIN
1 0 0 : 4 to 5 cycles of 1/f(XIN
1 0 1 : 5 to 6 cycles of 1/f(XIN
1 1 0 : 6 to 7 cycles of 1/f(XIN
1 1 1 : 7 to 8 cycles of 1/f(XIN
)
)
)
)
)
)
Digital delay
is selected
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However,
because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0”
is indeterminate.
Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 200 ns, so be sure to take this into account when using the device.
Figure 1.16.9. Serial I/O-related registers (6)
102
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2
and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.10 shows the
UARTi transmit/receive mode register.
Table 1.16.2. Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 037816
= “1”) : Input from CLKi pin
_______
_______
_______
_______
Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable
Transmission start condition • To start transmission, the following requirements must be met:
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_______
_______
_
When CTS function selected, CTS input level = “L”
Furthermore, if external clock is selected, the following requirements must also be met:
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
•
_
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
Reception start condition • To start reception, the following requirements must be met:
_
Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
_
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
• Furthermore, if external clock is selected, the following requirements must
also be met:
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “0”:
CLKi input level = “H”
_
CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16) = “1”:
CLKi input level = “L”
• When transmitting
Interrupt request
generation timing
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_
Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_
Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
• Overrun error (Note 2)
Error detection
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
103
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Table 1.16.3. Specifications of clock synchronous serial I/O mode (2)
Item
Specification
Select function
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge
of the transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected.
• TxD, RxD I/O polarity reverse (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
104
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be “0” in clock synchronous serial I/O mode)
Note : Set the corresponding port direction register to “0”.
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 2)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note 1)
0 : No reverse
1 : Reverse
Note 1: Usually set to “0”.
Note 2: Set the corresponding port direction register to “0”.
Figure 1.16.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode
105
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Table 1.16.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
table shows the pin functions when the transfer clock output from multiple pins function is not selected.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi
pin outputs an “H”. (If the N-channel open-drain is selected, this pin is in floating state.)
Table 1.16.4. Input/output pin functions in clock synchronous serial I/O mode
(when transfer clock output from multiple pins is not selected)
Pin name
TxDi
(P6 , P67, P70)
Function
Method of selection
Serial data output
(Outputs dummy data when performing reception only)
3
Serial data input
RxDi
(P6 , P6
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
2
6
, P7
1
)
)
CLKi
(P6 , P6
Transfer clock output
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “1”
1
5
, P7
2
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = “0”
CTSi/RTSi
(P6 , P6 , P73)
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0”
0
4
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
Port P6 , P6 and P7 direction register (bits 0 and 4 at address 03EE16
0
4
3
,
bit 3 at address 03EF16) = “0”
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
Transmit enable
“0”
“1”
“0”
“H”
Data is set in UARTi transmit buffer register
bit (TE)
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CTSi
CLKi
TCLK
“L”
Stopped pulsing because CTS = “H”
Stopped pulsing because transfer enable bit = “0”
TxDi
D0
D
1
D2
D3
D4
D5
D6
D7
D0
D
1
D2
D3
D4
D5
D
6
D7
D
0
D1
D2
D
3
D
4
D
5
D6
D7
Transmit
register empty
flag (TXEPT)
“1”
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = TCLK = 2(n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
fi: frequency of BRGi count source (f
n: value set to BRGi
1, f8, f32)
• CLK polarity select bit = “0”.
• Transmit interrupt cause select bit = “0”.
• Example of receive timing (when external clock is selected)
“1”
Receive enable
bit (RE)
“0”
“1”
Transmit enable
bit (TE)
“0”
“1”
“0”
“H”
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
CLKi
RxDi
“L”
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D6
D0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
“1”
“0”
Receive complete
flag (Rl)
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = “H”
• Transmit enable bit “1”
• Receive enable bit “1”
• Dummy data write to UARTi transmit buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = “0”.
fEXT: frequency of external clock
Figure 1.16.11. Typical transmit/receive timings in clock synchronous serial I/O mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(a) Polarity select function
As shown in Figure 1.16.12, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 037C16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = “0”
CLK
i
Note 1: The CLKi pin level when not
transferring data is “H”.
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D
0
D
1
D
2
D
D4
D
D
D
RXDi
• When CLK polarity select bit = “1”
CLK
i
Note 2: The CLKi pin level when not
transferring data is “L”.
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Figure 1.16.12. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.16.13, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
037C16) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.
• When transfer format select bit = “0”
CLK
i
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
LSB first
D
1
D
2
D
3
D
D
5
D
6
D7
D0
RXDi
• When transfer format select bit = “1”
CLK
i
D
7
7
D
6
D
5
D
4
D
3
3
D
2
D
1
D0
TXDi
MSB first
D
6
D
5
D
4
D
D
2
D
1
D0
D
RXDi
Note: This applies when the CLK polarity select bit = “0”.
Figure 1.16.13. Transfer format
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.16.14.)
The multiple pins function is valid only when the internal clock is selected for UART1.
Microcomputer
T
X
D1
(P67)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.16.14. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 037D16) is
set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register
is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to
the transmit buffer register back again.
(e) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 037D16) = “1”, and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data
logic switch timing.
•When LSB first
“H”
Transfer clock
“L”
“H”
2
TxD
(no reverse)
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
“L”
“H”
“L”
TxD
2
(reverse)
Figure 1.16.15. Serial data logic switch timing
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.16.5 and 1.16.6 list the specifications of the UART mode. Figure 1.16.16 shows
the UARTi transmit/receive mode register.
Table 1.16.5. Specifications of UART Mode (1)
Item
Specification
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
• Start bit: 1 bit
Transfer data format
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
Transfer clock
•
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 037816 = “0”) :
fi/16(n+1) (Note 1) fi = f1, f8, f32
•
When external clock is selected (bit 3 at addresses 03A016, 03A816 =“1”) :
fEXT/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)
_______
_______
_______
_______
Transmission/reception control • CTS function, RTS function, CTS and RTS function invalid: selectable
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 037D16) = “1”
-
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 037D16) = “0”
_______ _______
- When CTS function selected, CTS input level = “L”
Reception start condition • To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 037D16) = “1”
- Start bit detection
Interrupt request
generation timing
• When transmitting
- Transmit interrupt cause select bits (bits 0,1 at address 03B016, bit4 at
address 037D16) = “0”: Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 037D16) = “1”: Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is
encountered
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit does not change.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 1.16.6. Specifications of UART Mode (2)
Item
Specification
• Sleep mode selection (UART0, UART1)
Select function
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TXD, RXD I/O polarity switch (UART2)
This function is reversing TXD port output and RXD port input. All I/O data
level is reversed.
111
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
0 : Internal clock
1 : External clock (Note)
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Note : Set the corresponding port direction register to “0”.
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
037816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
CKDIR
STPS
PRY
Internal / external clock
select bit
Must always be “0”
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = “1”
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to “0”.
Figure 1.16.16. UARTi transmit/receive mode register in UART mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Table 1.16.7 lists the functions of the input/output pins during UART mode. Note that for a period from
when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an “H”. (If the N-
channel open-drain is selected, this pin is in floating state.)
Table 1.16.7. Input/output pin functions in UART mode
Pin name
TxDi
(P6 , P67, P70)
Function
Method of selection
Serial data output
3
RxDi
(P6 , P6
Serial data input
Port P6
bit 1 at address 03EF16)= “0”
(Can be used as an input port when performing transmission only)
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE16,
2
6
, P7
1
)
)
CLKi
(P6 , P6
Programmable I/O port
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 037816) = “0”
Internal/external clock select bit (bit 3 at address 03A016, 03A816) = “1”
1
5
, P7
2
Port P61, P65 direction register (bits 1 and 5 at address 03EE16) = “0”
(Do not set external clock for UART2)
CTSi/RTSi
(P6 , P6 , P73)
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) =“0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “0”
CTS input
0
4
Port P60, P64 and P73 direction register (bits 0 and 4 at address 03EE16,
bit 3 at address 03EF16) = “0”
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “0”
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 037C16) = “1”
RTS output
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 037C16) = “1”
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is “H” when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to “L”.
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
“0”
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
“H”
“L”
CTSi
Stopped pulsing because transmit enable bit = “0”
Start
bit
Parity Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
The above timing applies to the following settings :
• Parity is enabled.
1, f8, f32)
fEXT : frequency of BRGi count source (external clock)
• One stop bit.
n : value set to BRGi
• CTS function is selected.
• Transmit interrupt cause select bit = “1”.
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UARTi transmit buffer register
“0”
“1”
Transmit buffer
empty flag(TI)
“0”
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
Tc = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of BRGi count source (f
1, f8, f32)
• Two stop bits.
fEXT : frequency of BRGi count source (external clock)
• CTS function is disabled.
n : value set to BRGi
• Transmit interrupt cause select bit = “0”.
Figure 1.16.17. Typical transmit timings in UART mode(UART0,UART1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
Data is set in UART2 transmit buffer register
“0”
“1”
Note
Transmit buffer
empty flag(TI)
“0”
Transferred from UART2 transmit buffer register to UARTi transmit register
Parity
bit
Stop
bit
Start
bit
TxD
2
ST
D
0
D1
D2
D3
D4
D5
D6
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
“1”
“0”
Transmit register
empty flag (TXEPT)
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Tc = 16 (n + 1) / fi
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “1”.
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 1.16.18. Typical transmit timings in UART mode(UART2)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
“1”
Receive enable bit
“0”
Stop bit
Start bit
D
1
D7
RxDi
D0
Sampled “L”
Receive data taken in
Transfer clock
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
“1” is generated by falling edge of start bit
Receive
complete flag
“0”
“H”
“L”
RTSi
Receive interrupt
request bit
“1”
“0”
Cleared to “0” when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Figure 1.16.19. Typical receive timing in UART mode
(a) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when
the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.
(b) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 of address 037D16) is assigned “1”, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the ex-
ample of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
“H”
Transfer clock
“L”
“H”
TxD
2
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse)
“L”
“H”
“L”
TxD
2
(reverse)
ST : Start bit
P : Even parity
SP : Stop bit
Figure 1.16.20. Timing for switching serial data logic
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(c) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TXD pin output and RXD pin input. The level of any data to be input or output
(including the start bit, stop bit(s), and parity bit) is reversed. Set this function to “0” (not to reverse) for
usual use.
(d) Bus collision detection function (UART2)
This function is to sample the output level of the TXD pin and the input level of the RXD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.16.21
shows the example of detection timing of a bus collision (in UART mode).
“H”
Transfer clock
“L”
“H”
TxD
2
2
ST
ST
SP
SP
“L”
“H”
“L”
RxD
Bus collision detection
interrupt request signal
“1”
“0”
Bus collision detection
interrupt request bit
“1”
“0”
ST : Start bit
SP : Stop bit
Figure 1.16.21. Detection timing of a bus collision (in UART mode)
117
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(3) Clock-asynchronous serial I/O mode (used for the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some
extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table
1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).
Table 1.16.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 through bit 0 of address 037816 = “1012”)
• One stop bit (bit 4 of address 037816 = “0”)
• With the direct format chosen
Set parity to “even” (bit 5 and bit 6 of address 037816 = “1” and “1” respectively)
Set data logic to “direct” (bit 6 of address 037D16 = “0”).
Set transfer format to LSB (bit 7 of address 037C16 = “0”).
• With the inverse format chosen
Set parity to “odd” (bit 5 and bit 6 of address 037816 = “0” and “1” respectively)
Set data logic to “inverse” (bit 6 of address 037D16 = “1”)
Set transfer format to MSB (bit 7 of address 037C16 = “1”)
Transfer clock
• With the internal clock chosen (bit 3 of address 037816 = “0”) : fi / 16 (n + 1) (Note 1) : fi=f1, f8, f32
(Do not set external clock)
_______
_______
Transmission / reception control • Disable the CTS and RTS function (bit 4 of address 037C16 = “1”)
Other settings • The sleep mode select function is not available for UART2
•
Set transmission interrupt factor to “transmission completed” (bit 4 of address 037D16 = “1”)
Transmission start condition • To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 of address 037D16) = “1”
- Transmit buffer empty flag (bit 1 of address 037D16) = “0”
Reception start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 of address 037D16) = “1”
- Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 transmit register is completed
(bit 4 of address 037D16 = “1”)
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
- On the reception side, an “L” level is output from the TXD2 pin by use of the parity error
signal output function (bit 7 of address 037D16 = “1”) when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RXD2 pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART2 bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also
that the UART2 receive interrupt request bit does not change.
118
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Tc
Transfer clock
“1”
Transmit enable
bit(TE)
“0”
“1”
Note 1
Data is set in UART2 transmit buffer register
Transmit buffer
empty flag(TI)
“0”
Transferred from UART2 transmit buffer register to UART2 transmit register
Start
bit
Parity
bit
Stop
bit
TxD
2
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P
P
SP
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P
SP
RxD
2
An “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 2)
ST
D
0
D1
D
2
D
3
D
4
D5
D
7
P
SP
The level is
D
6
ST
D0
D1
D2
D3
D4
D5
D6
D7
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
“1”
Transmit register
empty flag (TXEPT)
“0”
“1”
“0”
Transmit interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
1, f8, f32)
• Transmit interrupt cause select bit = “1”.
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock
“1”
Receive enable
bit (RE)
“0”
Parity
bit
Stop
bit
Start
bit
SP
RxD
2
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
SP
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
6
D6
TxD2
An “L” level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 2)
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D
0
D
1
D
2
D
3
D
4
D
5
D7
D6
D6
“1”
Receive complete
flag (RI)
“0”
Read to receive buffer
Read to receive buffer
“1”
“0”
Receive interrupt
request bit (IR)
Cleared to “0” when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
Tc = 16 (n + 1) / fi
fi : frequency of BRG2 count source (f
n : value set to BRG2
1, f8, f32)
• Transmit interrupt cause select bit = “0”.
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface)
119
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
(a) Function for outputting a parity error signal
During reception, with the error signal output enable bit (bit 7 of address 037D16) assigned “1”, you
can output an “L” level from the TXD2 pin when a parity error is detected. And during transmission,
comparing with the case in which the error signal output enable bit (bit 7 of address 037D16) is as-
signed “0”, the transmission completion interrupt occurs in the half cycle later of the transfer clock.
Therefore parity error signals can be detected by a transmission completion interrupt program. Figure
1.16.23 shows the output timing of the parity error signal.
• LSB first
“H”
Transfer
“L”
clock
“H”
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxD
2
“L”
“H”
“L”
Hi-Z
TxD
2
“1”
“0”
Receive
complete flag
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 1.16.23. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted
and output from TxD2.
Figure 1.16.24 shows the SIM interface format.
Transfer
clcck
TxD2
(direct)
D0
D7
D1
D6
D2
D5
D3
D4
D4
D3
D5
D2
D6
D1
D7
D0
P
P
TxD2
(inverse)
P : Even parity
Figure 1.16.24. SIM interface format
120
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O (UART) mode
Figure 1.16.25 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply
pull-up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 1.16.25. Connecting the SIM interface
121
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
UART2 Special Mode Register
The UART2 special mode register (address 037716) is used to control UART2 in various ways.
Figure 1.16.26 shows the UART2 special mode register.
2
Bit 0 of the UART2 special mode register (037716) is used as the I C mode select bit.
2
2
2
Setting “1” in the I C mode select bit (bit 0) goes the circuit to achieve the I C bus (simplified I C bus)
interface effective.
2
Table 1.16.9 shows the relation between the I C mode select bit and respective control workings.
Since this function uses clock-synchronous serial I/O mode, set this bit to “0” in UART mode.
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
037716
When reset
8016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit
name
R W
I2C mode select bit
0 : Normal mode
1 : I2C mode
Must always be “0”
Must always be “0”
IICM
ABC
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
BBS
Bus busy flag
Must always be “0”
Must always be “0”
(Note1)
LSYN SCL L sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling clock select bit
Must always be “0”
Must always be “0”
Must always be “0”
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ABSCS
ACSE
Auto clear function
select bit of transmit
enable bit
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
0 : Ordinary
1 : Falling edge of RxD
Transmit start condition
select bit
SSS
2
0 : Must always be “0”
when not using I2C mode
1 : Digital delay output
is selected
SDA digital delay select
bit (Note 2)
Must always be “0”
SDDS
Note 1: Nothing but “0” may be written.
Note 2: When not in I2C mode, do not set this bit by writing a “1”. During normal mode, fix it to “0”. When this
bit = “0”, UART2 special mode register 3 (U2SMR3 at address 037516) bits 7 to 5 (DL2 to DL0 = SDA
digital delay setup bits) are initialized to “000”. Also, when SDDS = “0”, the U2SMR3 register cannot be
read or written to.
UART2 special mode register 3 (I2C bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR3
Address
037516
When reset
0016
Function
(I2 C bus exclusive use register)
Bit
symbol
Bit name
R W
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate. However, when SDDS = “1”, the value “0” is read out (Note 1)
SDA digital delay setup
bit
(Note 1, Note 2, Note 3)
DL0
DL1
DL2
b7 b6 b5
0 0 0 : Must not be set when using I2C mode
0 0 1 : 1 to 2 cycle(s) of 1/f(XIN
)
0 1 0 : 2 to 3 cycles of 1/f(XIN
0 1 1 : 3 to 4 cycles of 1/f(XIN
1 0 0 : 4 to 5 cycles of 1/f(XIN
1 0 1 : 5 to 6 cycles of 1/f(XIN
1 1 0 : 6 to 7 cycles of 1/f(XIN
1 1 1 : 7 to 8 cycles of 1/f(XIN
)
)
)
)
)
)
Digital delay
is selected
Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 037716) bit
7 (SDDS: SDA digital delay select bit) = “1”. When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = “1”, the value is “0016”. When writing to UART2 special mode
register 3 (U2SMR3) after setting SDDS = “1”, be sure to write 0's to bits 0–4. When SDDS = “0”,
this register cannot be written to; when read, the value is indeterminate.
Note 2: These bits are initialized to “000” when SDDS = “0”. After a reset, these bits are set to “000”. However,
because these bits can be read only when SDDS = “1”, the value read from these bits when SDDS = “0”
is indeterminate.
Note 3: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the
amount of delay increases by about 200 ns, so be sure to take this into account when using the device.
Figure 1.16.26. UART2 special mode register
122
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M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
P70
through P7
2
conforming to the simplified I 2C bus
P70/TxD2/SDA
Timer
I/O
To DMA0
Selector
UART2
IICM=0
or IICM2=1
UART2 transmission/
NACK interrupt request
SDDS=0
or DL=000
UART2
Transmission
register
IICM=1
and IICM2=0
Digital delay
(Divider)
SDDS=1 and
DL 000
SDHI
ALS
D
Q
Arbitration
T
Noize
Filter
Timer
To DMA0
IICM=1
IICM=0
or IICM2=1
UART2 reception/ACK interrupt
request
Reception register
UART2
IICM=0
IICM=1
and IICM2=0
Start condition
detection
S
Q
Bus busy
R
Stop condition
detection
NACK
D
Q
L-synchronous
output enabling
bit
Falling edge
detection
T
D
Q
P71/RxD2/SCL
I/O
(Port P7
R
ACK
T
Q
Data bus
output data latch)
9th pulse
1
Selector
Bus collision/start, stop condition
detection interrupt request
IICM=1
IICM=0
Internal clock
UART2
IICM=1
Bus collision
detection
UART2
SWC2
CLK
control
IICM=1
Noize
Filter
External clock
Noize
Filter
Falling edge of 9 bit
SWC
IICM=0
Port reading
UART2
IICM=0
*
With IICM set to 1, the port terminal is to be readable
even if 1 is assigned to P7 of the direction register.
P72/CLK2
1
Selector
I/O
Timer
Figure 1.16.27. Functional block diagram for I2C mode
2
Table 1.16.9. Features in I C mode
2
Function
Normal mode
I C mode (Note 1)
Start condition detection or stop
condition detection
Bus collision detection
1
Factor of interrupt number 10 (Note 2)
2
3
4
5
6
7
Factor of interrupt number 15 (Note 2)
Factor of interrupt number 16 (Note 2)
UART2 transmission output delay
UART2 transmission
UART2 reception
Not delayed
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Delayed (digital delay)
P7
0
1
at the time when UART2 is in use
at the time when UART2 is in use
at the time when UART2 is in use
TxD
2
(output)
(input)
SDA (input/output) (Note 3)
SCL (input/output)
P7
RxD
2
2
P72
CLK
P72
8
9
Noise filter width
Reading P7
15ns
200ns
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of the
value of the direction register
1
H level (when 0 is assigned to
the CLK polarity select bit)
The value set in latch P7
selected
0 when the port is
10 Initial value of UART2 output
2
Note 1: Make the settings given below when I C mode is in use.
Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
123
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
2
2
Figure 1.16.27 shows the functional block diagram for I C mode. Setting “1” in the I C mode select bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock input-
output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission output,
so the SDA output changes after SCL fully goes to “L”. The amount of delay can be selected in the range
of 2 cycles to 8 cycles of f1 using UART2 special mode register 3 (at address 037516). Delay circuit select
conditions are shown in Table 1.16.10.
Table 1.16.10. Delay circuit select conditions
Register value
Contents
IICM SDDS DL
001
to
Digital delay is
selected
Digital delay is added
1
0
1
0
111
When IICM = “0”, no delay circuit is selected. When IICM = “0”,
however, always make sure SDDS = “0”.
(000)
No delay
An attempt to read Port P71 (SCL) results in getting the terminal’s level regardless of the content of the
port direction register. The initial value of SDA transmission output goes to the value set in port P70. The
interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and of UART2
reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-detection in-
terrupt, and acknowledgment detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying “H”. The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the SCL
terminal (P71) staying “H”. The bus busy flag (bit 2 of the UART2 special mode register) is set to “1” by the
start condition detection, and set to “0” by the stop condition detection.
The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal
level is detected still staying “H” at the rising edge of the 9th transmission clock. The acknowledgment
detection interrupt refers to the interrupt that occurs when SDA terminal’s level is detected already went
to “L” at the 9th transmission clock.
Bit 1 of the UART2 special mode register (037716) is used as the arbitration lost detecting flag control bit.
Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal
data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception
buffer register (037F16, 037E16), and “1” is set in this flag when nonconformity is detected. Use the
arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by
byte. When setting this bit to “1” and updated the flag byte by byte if nonconformity is detected, the
arbitration lost detecting flag is set to “1” at the falling edge of the 9th transmission clock.
If update the flag byte by byte, must judge and clear (“0”) the arbitration lost detecting flag after complet-
ing the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting
this bit to “1” goes the P71 data register to “0” in synchronization with the SCL terminal level going to “L”.
124
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
Some other functions added are explained here. Figure 1.16.28 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The
bus collision detect interrupt occurs when the RXD2 level and TXD2 level do not match, but the nonconfor-
mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to “0”. If
this bit is set to “1”, the nonconformity is detected at the timing of the overflow of timer A0 rather than at
the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to “1” automatically resets the transmit enable bit to “0” when “1” is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit
to “1” starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK
TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK
TxD
Enabling transmission
With "1: falling edge of RxD2" selected
CLK
TxD
RxD
Figure 1.16.28. Some other functions added
125
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
UART2 Special Mode Register 2
UART2 special mode register 2 (address 037616) is used to further control UART2 in I C mode. Figure
1.16.29 shows the UART2 special mode register 2.
2
UART2 special mode register 2 (I2C bus exclusive use register)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
037616
When reset
0016
Bit
symbol
Bit name
R W
Function
2
I C mode select bit 2
Clock-synchronous bit
SCL wait output bit
Refer to Table 1.16.11
IICM2
CSC
0 : Disabled
1 : Enabled
SWC
0 : Disabled
1 : Enabled
ALS
SDA output stop bit
UART2 initialization bit
SCL wait output bit 2
SDA output disable bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
STAC
SWC2
0: UART2 clock
1: 0 output
0: Enabled
SDHI
1: Disabled (high impedance)
1: Set this bit to “1” in I2C mode
(refer to Table 1.16.12)
SHTC
Start/stop condition
control bit
Figure 1.16.29. UART2 special mode register 2
126
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
2
Bit 0 of the UART2 special mode register 2 (address 037616) is used as the I C mode select bit 2. Table
2
2
1.16.11 shows the types of control to be changed by I C mode select bit 2 when the I C mode select bit
is set to “1”. Table 1.16.12 shows the timing characteristics of detecting the start condition and the stop
2
condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to “1” in I C
mode.
2
Table 1.16.11. Functions changed by I C mode select bit 2
Function
IICM2 = 0
IICM2 = 1
1
2
3
Factor of interrupt number 15
No acknowledgment detection (NACK)
UART2 transmission (the rising edge
of the final bit of the clock)
UART2 reception (the falling edge
of the final bit of the clock)
Factor of interrupt number 16
Acknowledgment detection (ACK)
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
4
Timing for generating a UART2
reception/ACK interrupt request
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
Table 1.16.12. Timing characteristics of detecting the start condition and the stop condition (Note 1)
3 to 6 cycles < duration for setting-up (Note 2)
3 to 6 cycles < duration for holding (Note 2)
Note 1 : When the start/stop condition control bit SHTC is “1” .
Note 2 : “Cycles” is in terms of the input oscillation frequency f(XIN) of the main clock.
Duration for
setting up
Duration for
holding
SCL
SDA
(Start condition)
SDA
(Stop condition)
127
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
P70
through P7
2
conforming to the simplified I 2C bus
P70/TxD2/SDA
Timer
I/O
To DMA0
Selector
UART2
IICM=0
or IICM2=1
UART2 transmission/
NACK interrupt request
SDDS=0
or DL=000
UART2
Transmission
register
IICM=1
and IICM2=0
Digital delay
(Divider)
SDDS=1 and
DL 000
SDHI
ALS
D
Q
Arbitration
T
Noize
Filter
Timer
To DMA0
IICM=1
IICM=0
or IICM2=1
UART2 reception/ACK interrupt
request
Reception register
UART2
IICM=0
IICM=1
and IICM2=0
Start condition
detection
S
Q
Bus busy
R
Stop condition
detection
NACK
D
Q
L-synchronous
output enabling
bit
Falling edge
detection
T
D
Q
P71/RxD2/SCL
I/O
(Port P7
R
ACK
T
Q
Data bus
output data latch)
9th pulse
1
Selector
Bus collision/start, stop condition
detection interrupt request
IICM=1
IICM=0
Internal clock
UART2
IICM=1
Bus collision
detection
UART2
SWC2
CLK
control
IICM=1
Noize
Filter
External clock
Noize
Filter
Falling edge of 9 bit
SWC
IICM=0
Port reading
With IICM set to 1, the port terminal is to be readable
UART2
IICM=0
*
P72/CLK2
even if 1 is assigned to P71 of the direction register.
Selector
I/O
Timer
2
Figure 1.16.30. Functional block diagram for I C mode
2
Functions available in I C mode are shown in Figure 1.16.30 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 037616) is used as the SDA output stop bit. Setting
this bit to “1” causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the
instant when the arbitration lost detecting flag is set to “1”.
Bit 1 of the UART2 special mode register 2 (address 037616) is used as the clock synchronization bit.
With this bit set to “1” at the time when the internal SCL is set to “H”, the internal SCL turns to “L” if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the “L” interval. When the internal SCL changes from “L” to “H” with the SCL pin set to “L”, stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to “H”. Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit. Setting this bit to
“1” causes the SCL pin to be fixed to “L” at the falling edge of the ninth bit of the clock. Setting this bit to
“0” frees the output fixed to “L”.
128
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
Bit 4 of the UART2 special mode register 2 (address 037616) is used as the UART2 initialization bit.
Setting this bit to “1”, and when the start condition is detected, the microcomputer operates as follows.
(1) The transmission shift register is initialized, and the content of the transmission register is transferred
to the transmission shift register. This starts transmission by dealing with the clock entered next as the
first bit. The UART2 output value, however, doesn’t change until the first bit data is output after the
entrance of the clock, and remains unchanged from the value at the moment when the microcomputer
detected the start condition.
(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the
clock entered next as the first bit.
(3) The SCL wait output bit turns to “1”. This turns the SCL pin to “L” at the falling edge of the ninth bit of
the clock.
Starting to transmit/receive signals to/from UART2 using this function doesn’t change the value of the
transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.
Bit 5 of the UART2 special mode register 2 (037616) is used as the SCL wait output bit 2. Setting this bit
to “1” with the serial I/O specified allows the user to forcibly output an “1” from the SCL pin even if UART2
is in operation. Setting this bit to “0” frees the “L” output from the SCL pin, and the UART2 clock is input/
output.
Bit 6 of the UART2 special mode register 2 (037616) is used as the SDA output disable bit. Setting this bit
to “1” forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit
at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting
flag is turned on.
129
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling
amplifier. Pins P10 to P10 , P9 , and P9 also function as the analog signal input pins. The direction registers of
0
7
5
6
these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be
used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D
converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power
dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF
.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low
8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the
A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers.
Table 1.17.1. Performance of A-D converter
Item
Performance
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC)
Operating clock φAD (Note 2) VCC = 3.3V fAD/divide-by-2 of fAD/divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
VCC = 3.3V • Without sample and hold function
±5LSB
Absolute precision
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN7 input : ±5LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : ±7LSB
Operating modes
Analog input pins
One-shot mode
8pins (AN0 to AN7) + 2pins (ANEX0 and ANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to “1”
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is “1” and the
ADTRG/P97 input changes from “H” to “L”
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles 10-bit resolution: 59
• With sample and hold function
8-bit resolution: 28 AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide the fAD if f(XIN) exceeds 10MH , and make φAD frequency equal to or less than 10MHz. And
divide the fAD if VCC is less than 3.0V, and make φAD frequency equal to or lower than fAD/2.
φ
,
φAD cycles
φ
, 10-bit resolution: 33 φAD cycles
Z
Without sample and hold function, set the
With the sample and hold function, set the
φ
AD frequency to 250kHZ min.
φ
AD frequency to 1MHZ min.
130
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
CKS1=1
CKS1=0
CKS0=1
CKS0=0
φ
AD
f
AD
1/2
1/2
A-D conversion rate
selection
V
REF
VCUT=0
Resistor ladder
AVSS
VCUT=1
Successive conversion register
A-D control register 1 (address 03D716
)
)
A-D control register 0 (address 03D616
Addresses
(03C116, 03C016
(03C316, 03C216
(03C516, 03C416
)
)
)
A-D register 0(16)
A-D register 1(16)
A-D register 2(16)
A-D register 3(16)
V
ref
(03C716, 03C616
(03C916, 03C816
(03CB16, 03CA16
(03CD16, 03CC16
(03CF16, 03CE16
)
Decoder
)
A-D register 4(16)
)
A-D register 5(16)
A-D register 6(16)
Comparator
V
IN
)
)
A-D register 7(16)
Data bus high-order
Data bus low-order
CH2,CH1,CH0=000
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
CH2,CH1,CH0=001
CH2,CH1,CH0=010
CH2,CH1,CH0=011
CH2,CH1,CH0=100
CH2,CH1,CH0=101
CH2,CH1,CH0=110
CH2,CH1,CH0=111
OPA1,OPA0=0,0
OPA1, OPA0
0
0
1
1
0 : Normal operation
1 : ANEX0
0 : ANEX1
1 : External op-amp mode
OPA1,OPA0=1,1
OPA0=1
OPA1=1
ANEX0
ANEX1
OPA1,OPA0=0,1
Figure 1.17.1. Block diagram of A-D converter
131
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00000XXX
2
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
b4 b3
Analog input pin select bit
1
is selected
is selected
is selected
is selected
is selected
is selected
is selected
2
3
4
5
6
7
A-D operation mode
select bit 0
MD0
MD1
TRG
0 0 : One-shot mode
Must not be set except “00”
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
ADST
CKS0
0 : fAD/4 is selected
1 : fAD/2 is selected
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
0
0
0
Bit symbol
Reserved bit
Bit name
Function
R W
Must always be set to “0”
8/10-bit mode select bit
Frequency select bit 1
Vref connect bit
0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
0 : Vref not connected
1 : Vref connected
VCUT
OPA0
OPA1
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Figure 1.17.2. A-D converter-related registers (1)
132
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
Symbol
ADCON2
Address
03D416
When reset
0000XXX0
b7 b6 b5 b4 b3 b2 b1 b0
2
0
0 0
Bit symbol
SMP
Bit name
Function
R W
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
Reserved bit
Must always be set to “0”
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to
be “0”.
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi(i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if
read, turns out to be “0”.
Figure 1.17.3. A-D converter-related registers (2)
133
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.17.2. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing “1” to A-D conversion start flag
Start condition
Stop condition
•
End of A-D conversion (A-D conversion start flag changes to “0”, except
when external trigger is selected)
• Writing “0” to A-D conversion start flag
Interrupt request generation timing End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Read A-D register corresponding to selected pin
Reading of result of A-D converter
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Bit symbol
Bit name
Function
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
R W
b2 b1 b0
Analog input pin select
bit
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
b4 b3
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0: fAD/4 is selected
1: fAD/2 is selected
Frequency select bit 0
Note : If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D control register 1 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0 0 0
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
R W
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
0 : fAD/2 or fAD/4 is selected
1 : fAD is selected
CKS1
Frequency select bit1
Vref connect bit
VCUT
OPA0
1 : Vref connected
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Figure 1.17.4. A-D conversion register in one-shot mode
134
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 AD cycle is
achieved with 8-bit resolution and 33 AD with 10-bit resolution. Sample and hold can be selected in all
φ
φ
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “0”, input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is “0” and bit 7 is “1”, input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is “1” and bit 7 is “1”, input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.17.5 is an example of how to
connect the pins in external operation amp mode.
Resistor ladder
Successive conversion register
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
Analog
input
AN7
ANEX0
ANEX1
Comparator
External op-amp
Figure 1.17.5. Example of external op-amp connection mode
135
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Ports
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P85 is
an input-only port and has no built-in pull-up resistance.
Figures 1.20.1 to 1.20.4 show the programmable I/O ports. Figure 1.20.5 shows the I/O pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When pins are to be
used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.20.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding direction register of pins
_______
_______ _____ ________ ______ ________ _______
_______ __________ _________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.20.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding port register of pins A0 to
_______
________ _____ ________ ______ ________ ________
_______ __________ _________
A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be
modified.
(3) Pull-up control registers
Figure 1.20.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3,
P40 to P43, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not
connected.
(4) Port control register
Figure 1.20.9 shows the port control register.
The bit 0 of port control register is used to read port P1 as follows:
0 : When port P1 is input port, port input level is read.
When port P1 is output port , the contents of port P1 register is read.
1 : The contents of port P1 register is read always.
This register is valid in the following:
• External bus width is 8 bits in microprocessor mode or memory expansion mode.
• Port P1 can be used as a port in multiplexed bus for the entire space.
136
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P0
P3
P5
0
0
0
to P0
to P3
to P5
7, P2
7, P4
4, P5
0
0
6
to P2
to P4
7
7
,
,
Data bus
Port latch
(Note)
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Data bus
Port latch
(Note)
(Note)
(Note)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Data bus
Port latch
Input to respective peripheral functions
Pull-up selection
Direction register
P5
P7
7
2
, P6
, P7
0
3
, P6
, P7
1
4
, P64, P65,
"1"
Output
Data bus
Port latch
Input to respective peripheral functions
Note:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 1.20.1. Programmable I/O ports (1)
137
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P82
to P8
4
Data bus
Port latch
(Note1)
Input to respective peripheral functions
Pull-up selection
Direction register
P7
6
0
, P7
, P9
7
3
, P8
, P9
0
4
, P81,
P9
(inside dotted-line not included)
Data bus
Port latch
P5
5
1
, P6
, P9
2
2
, P6
, P9
6
7
, P75,
P9
(Note1)
(inside dotted-line included)
Input to respective peripheral functions
(Note 2)
Pull-up selection
Direction register
P63, P67
"1"
Output
Data bus
Port latch
(Note1)
P85
Data bus
Note 1:
(Note1)
NMI interrupt input
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2: In a part of port, the input to a respective peripheral functions
does not exist, but schmitt circuit exists.
Figure 1.20.2. Programmable I/O ports (2)
138
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Direction register
Port latch
P70, P71
"1"
Output
Data bus
(Note 2)
Input to respective peripheral functions
Pull-up selection
Direction register
P9
(inside dotted-line not included)
P9 , P10 to P10
(inside dotted-line included)
6, P100 to P103
5
4
7
Data bus
Port latch
(Note 1)
Analog input
Input to respective peripheral functions
Note 1:
Note 2:
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
symbolizes a parasitic diode.
Figure 1.20.3. Programmable I/O ports (3)
139
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P8
7
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Direction register
Rd
P86
"1"
Output
Data bus
Port latch
(Note)
Note :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 1.20.4. Programmable I/O ports (4)
BYTE
BYTE signal input
(Note)
(Note)
(Note)
CNVSS
CNVSS signal input
RESET
RESET signal input
Note :
symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each pin.
Figure 1.20.5. I/O pins
140
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi direction register (Note 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PDi (i = 0 to 10, except 8)
Address
When reset
0016
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
0016
Bit symbol
PDi_0
Bit name
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
direction register
direction register
direction register
3 direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
PDi_1
1
PDi_2
2
(Functions as an output port)
PDi_3
(i = 0 to 10 except 8)
PDi_4
PDi_5
PDi_6
PDi_7
4
direction register
direction register
direction register
direction register
Port Pi
Port Pi
Port Pi
5
6
7
Note 1: Set bit 2 of protect register (address 000A16) to “1” before rewriting to
the port P9 direction register.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi direction register of pins A
CS to CS
BCLK cannot be modified.
0
to A19, D0 to D15,
0
3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
R W
Port P8
Port P8
Port P8
0
direction register
direction register
direction register
direction register
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_1
PD8_2
PD8_3
PD8_4
1
2
(Functions as an output port)
Port P8
Port P8
3
4
Nothing is assigned.
In an attempt to write to this bit, write “0”. The value, if read, turns out to be
indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
Port P8
6
direction register
direction register
7
(Functions as an output port)
Figure 1.20.6. Direction register
141
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register (Note 2)
Symbol
Pi (i = 0 to 10, except 8)
Address
When reset
03E016, 03E116, 03E416, 03E516, 03E816 Indeterminate
03E916, 03EC16, 03ED16, 03F116, 03F416 Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
Pi_0
Bit name
register
register
register
register
register
Function
R W
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
0
1
2
3
4
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : “L” level data
Pi_1
Pi_2
Pi_3
1 : “H” level data (Note 1)
Pi_4
(i = 0 to 10 except 8)
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
6
7
register
register
register
Note 1: Since P7
0
and P71 are N-channel open drain ports, the data is high-impedance.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi register of pins A to A19, D to D15, CS to CS3,
0
0
0
RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F016
When reset
Indeterminate
Bit symbol
P8_0
Bit name
Function
R W
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
0
1
2
3
4
5
6
7
register
register
register
register
register
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : “L” level data
1 : “H” level data
P8_1
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Figure 1.20.7. Port register
142
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When reset
0016
Bit symbol
PU00
Bit name
Function
R W
P0
P0
P1
P1
P2
P2
P3
P3
0
to P0
to P0
to P1
to P1
to P2
to P2
to P3
to P3
3
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU01
PU02
PU03
PU04
PU05
PU06
PU07
4
0
4
0
4
0
4
7
3
7
3
7
3
7
1 : Pulled high
Note : In memory expansion and microprocessor mode, the content of this register
can be changed, but the pull-up resistance is not connected.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When reset
0016 (Note 2)
R W
Bit symbol
PU10
Bit name
Function
P4
0
4
to P4
3
pull-up (Note 3)
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU11
PU12
PU13
PU14
PU15
P4
to P4
7
pull-up
P5
P5
P6
P6
0
4
0
4
to P5
to P5
to P6
to P6
3
7
3
7
pull-up (Note 3)
pull-up (Note 3)
pull-up
1 : Pulled high
pull-up
PU16
PU17
P7
2
to P7
3
pull-up (Note 1)
pull-up
P7
4
to P7
7
Note 1: Since P7
0
and P71 are N-channel open drain ports, pull-up is not available for them.
Note 2: When the VCC level is being impressed to the CNVSS terminal, this register becomes
to 0216 when reset (PU11 becomes to “1”).
Note 3: In memory expansion and microprocessor mode, the content of these bits can be
changed, but the pull-up resistance is not connected.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
PU20
Bit name
Function
R W
P8
0
4
to P8
3
pull-up
The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
PU21
P8
to P8
7
pull-up
5)
(Except P8
P9 to P9
P9 to P9
P10
P10
1 : Pulled high
PU22
0
3
pull-up
PU23
PU24
PU25
4
7 pull-up
0
to P10
3
pull-up
4
to P10
7 pull-up
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be “0”.
Figure 1.20.8. Pull-up control register
143
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbpl
PCR
Address
03FF16
When reset
0016
R W
Bit symbol
PCR0
Bit name
Function
Port P1 control register
0 : When input port, read port
input level. When output port,
read the contents of port P1
register.
1 : Read the contents of port P1
register though input/output
port.
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be “0”.
Figure 1.20.9. Port control register
144
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Table 1.20.1. Example connection of unused pins in single-chip mode
Pin name
Connection
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
Ports P0 to P10
(excluding P8
5
)
XOUT (Note)
Open
Connect via resistor to VCC (pull-up)
Connect to VCC
NMI
AVCC
AVSS, VREF, BYTE
Connect to VSS
Note: With external clock input to XIN pin.
Table 1.20.2. Example connection of unused pins in memory expansion mode and microprocessor mode
Pin name
Connection
Ports P6 to P10
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
(excluding P8
5)
Set ports to input mode, set output enable bits of CS1 through CS3 to
0, and connect to Vcc via resistors (pull-up).
P4 / CS1 to P47 / CS3
5
Open
BHE, ALE, HLDA,
OUT (Note 1), BCLK (Note 2)
X
Connect via resistor to VCC (pull-up)
Connect to VCC
HOLD, RDY, NMI
AVCC
AVSS, VREF
Connect to VSS
Note 1: With external clock input to XIN pin.
Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up).
Microcomputer
Microcomputer
Port P6 to P10 (except for P85)
Port P0 to P10 (except for P85)
(Input mode)
(Input mode)
·
·
·
·
·
·
·
·
·
·
·
·
(Input mode)
(Input mode)
(Output mode)
(Output mode)
Open
Open
NMI
NMI
BHE
HLDA
ALE
Port P4
5 / CS1
to P4 / CS3
7
XOUT
Open
Open
V
CC
X
OUT
V
CC
AVCC
BYTE
AVSS
BCLK (Note)
HOLD
RDY
V
REF
AVCC
AVSS
V
REF
V
SS
V
SS
In single-chip mode
In memory expansion mode or
in microprocessor mode
Note : When the BCLK output disable bit (bit 7 at address 000416) is set to “1”, connect to VCC via a resistor (pull-up).
Figure 1.20.10. Example connection of unused pins
145
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Electrical characteristics
Table 1.26.1. Absolute maximum ratings
Symbol
Vcc
Parameter
Condition
Rated value
- 0.3 to 4.2
Unit
V
Supply voltage
Analog supply voltage
V
V
CC=AVCC
CC=AVCC
AVcc
- 0.3 to 4.2
V
CNVSS, BYTE,
RESET,
P0 to P0
P3 to P3
P6
P9
Input
voltage
0
7
, P1
0
to P1
7
, P2
, P5
, P8
0 to P27,
0
7
,P4
0
to P4
7
0
to P5
7,
VI
- 0.3 to Vcc + 0.3
V
0
to P6
7
, P7
2
to P7
7
0
to P87,
0
to P9
7
, P10
0
to P10
7
,
V
REF, XIN
V
V
P7
0
, P7
to P0
to P3
to P6
, P8 , P9
1
- 0.3 to 4.2
Output
voltage
P0
0
7
, P1
0
to P1
to P4
to P7
to P9 , P10
7
, P2
0
to P2
to P57
7
,
P3
0
7
, P4
0
7, P5
0
,
- 0.3 to Vcc + 0.3
V
O
d
P60
P8
6
7
, P7
2
7, P8
0
to P84,
to P107,
7
0
7
0
X
OUT
P7
0
, P7
1
- 0.3 to 4.2
300
V
mW
C
P
Power dissipation
C
Topr=25
Operating ambient temperature
Storage temperature
- 20 to 85 / -40 to 85 (Note)
- 65 to 150
T
opr
stg
T
C
Note: Specify a product of -40°C to 85°C to use it.
146
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 1.26.2. Recommended operating conditions (referenced to VCC = 2.2V to 3.6V at Topr = – 20°C
o
o
to 85 C / – 40°C to 85 C(Note 3) unless otherwise specified)
Standard
Parameter
Unit
Symbol
Typ.
3.3
Vcc
0
Min.
2.2
Max.
3.6
Supply voltage
Vcc
V
AVcc
Vss
Analog supply voltage
Supply voltage
V
V
AVss
Analog supply voltage
0
V
P3
P7
1
2
to P3
to P7
7
, P4
0
0
to P4
7
, P5
, P9
0
0
0
7,
HIGH input
voltage
7, P8
to P8
7
0.8Vcc
Vcc
V
X
IN, RESET, CNVSS, BYTE
V
V
IH
P7
P0
P0
0
0
0
, P7
1
0.8Vcc
0.8Vcc
4.2
V
V
to P0
to P0
7
, P1
0
0
to P1
7
, P2
, P2
0
0
to P2
to P2
7
, P3
, P3
0
0
(during single-chip mode)
Vcc
7, P1
to P1
7
7
0.5Vcc
Vcc
V
(data input function during memory expansion and microprocessor modes)
P3
P7
1
0
to P3
to P7
7, P4
0
0
to P4
7
, P5
, P9
0
0
to P57, P6
to P9
0
to P67,
LOW input
voltage
7, P8
to P8
7
7, P10
0
to P107,
0
0.2Vcc
V
X
IN, RESET, CNVSS, BYTE
IL
P0
0
to P0
7
, P1
0
to P1
7
, P2
0
to P2
to P2
7
, P3
, P3
0
0
(during single-chip mode)
0
0
0.2Vcc
V
V
P0
0
to P0
7, P1
0
to P1
7
, P2
0
7
0.16Vcc
(data input function during memory expansion and microprocessor modes)
P0
P4
P8
0
0
0
to P0
to P4
to P8
7
7
4
, P1
, P5
0
0
to P1
to P5
7
, P2
0
0
to P2
7
, P3
, P7
0
2
to P3
to P7
7
,
,
HIGH peak output
current
IOH (peak)
7, P6
to P6
7
7
- 10.0
- 5.0
10.0
mA
mA
mA
, P8
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P0
P4
P8
0
0
0
to P0
to P4
to P8
7
7
4
, P1
, P5
, P8
0
0
to P1
7
, P2
, P6
0
0
to P2
7
, P3
, P7
0
to P3
7
,
,
HIGH average output
current
IOH (avg)
to P5
7
to P6
7
2
to P77
6
, P8
7
, P9
0
to P9
7
, P10
0
to P10
7
P0
P4
P8
0
0
0
to P0
to P4
to P8
7
7
4
, P1
, P5
0
0
to P1
to P5
7
, P2
, P6
0
0
to P2
to P6
7
, P3
, P7
0
to P3
7
,
,
LOW peak output
current
IOL (peak)
7
7
0 to P7
to P10
7
, P8
6
, P8
7
, P9
0
to P9
7
, P10
0
7
P0
P4
P8
0
0
0
to P0
to P4
to P8
7
7
4
, P1
, P5
0
0
to P1
to P5
7
, P2
0
0
to P2
7
, P3
, P7
0
to P3
to P7
7
,
LOW average
output current
IOL (avg)
5.0
16
mA
7, P6
to P6
7
0
7,
, P86, P87, P90 to P97, P100 to P107
Vcc=3.0V to 3.6V
0
MHz
15 X Vcc
- 29
Vcc=2.4V to 3.0V
Vcc=2.2V to 2.4V
Vcc=3.0V to 3.6V
Vcc=2.4V to 3.0V
Vcc=2.2V to 2.4V
0
0
0
MHz
MHz
MHz
MHz
No wait
Main clock input
oscillation frequency
(Note 4)
17.5 X Vcc
- 35
16
f (XIN
)
11.25 X Vcc
- 17.75
11.25 X Vcc
- 17.75
With wait
0
0
MHz
kHz
f (XcIN
)
50
Subclock oscillation frequency
32.768
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P86, P87, P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
P2, P86, P87, P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P80 to P84 must be
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P72 to P77, and P80 to P84 must be 80mA max.
Note 3: Specify a product of -40°C to 85°C to use it.
Note 4: Relationship between main clock oscillation frequency and supply voltage.
Main clock input oscillation frequency (No wait)
Main clock input oscillation frequency (With wait)
11.25 X VCC –17.75MH
Z
16.0
16.0
15 X VCC –29MH
Z
9.25
7.0
17.5 X VCC–35MH
Z
7.0
3.5
0.0
0.0
2.2
2.4
3.0
3.6
2.2
2.4
3.0
3.6
Supply voltage[V]
(BCLK: no division)
Supply voltage[V]
(BCLK: no division)
147
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
o
Table 1.26.3. Electrical characteristics (referenced to VCC = 3.0V to 3.6V, VSS = 0V at Topr = – 20 C to
o
o
o
85 C / – 40 C to 85 C (Note 1), f(XIN) = 16MHZ unless otherwise specified)
Standard
Min Typ. Max.
Measuring condition
Symbol
Parameter
Unit
HIGH output P0
0
0
to P0
to P3
to P6
7
, P1
, P4
, P7
0
to P1
to P4
to P7
7
, P2
, P5
, P8
0
0
to P2
to P5
to P8
7
,
,
voltage
P3
P6
P8
7
0
7
7
VOH
V
I
OH = -1mA
CC = 3.3V
2.8
0
6
7
2
7
0
4,
V
, P8
7, P9
0
to P9
7, P10
0
to P10
7
HIGHPOWER
LOWPOWER
I
I
OH = -0.1mA, VCC = 3.3V
2.8
2.8
2.8
1.6
HIGH output voltage
HIGH output voltage
X
OUT
VOH
V
V
OH = -50µA, VCC = 3.3V
HIGHPOWER
LOWPOWER
With no load applied, VCC = 3.3V
With no load applied, VCC = 3.3V
XCOUT
P0
P3
P6
P8
0
0
0
6
to P0
to P3
to P6
7
7
7
,P1
0
to P1
7
, P2
0
to P2
to P5
to P8
7,
LOW output
voltage
, P4
0
0
to P4
7
, P5
, P8
0
0
7,
V
OL
OL
I
OL = 1mA
CC = 3.3V
0.5
V
, P7
to P7
7
4,
V
, P87, P9
0
to P9
7, P10
0
to P10
7
HIGHPOWER
LOWPOWER
I
I
OL = 0.1mA, VCC = 3.3V
0.5
V
V
V
X
OUT
LOW output voltage
LOW output voltage
OL = 50µA, VCC = 3.3V
0.5
With no load applied, VCC = 3.3V
With no load applied, VCC = 3.3V
HIGHPOWER
LOWPOWER
0
0
X
COUT
Hysteresis
HOLD, RDY, TA0IN to TA2IN
TB1IN, TB2IN, INT to INT , NMI,
ADTRG, CTS to CTS
CLK to CLK ,TA2OUT
KI to KI , RxD
,
0
2
V
T+-
T+-
V
T-
T-
0
2
, SCL, SDA
0.2
0.2
0.8
V
0
2
,
0
3
0
to RxD
2
V
CC = 3.3V
CC = 3.3V
V
V
V
V
Hysteresis
RESET
1.8
4.0
HIGH input
current
P0
P3
P6
P9
0
0
0
0
to P0
to P3
to P6
to P9
7
7
7
7
, P1
, P4
, P7
0
to P1
to P4
to P7
7
7
7
, P20 to P27,
0
0
,P50
to P57,
I
IH
VI
= 3V
µA
, P8
0
to P8
7,
, P100 to P107,
VCC = 3.3V
XIN, RESET, CNVss, BYTE
P0
P3
P6
P9
0
0
0
0
to P0
to P3
to P6
to P9
7
7
7
7
, P1
, P4
, P7
0
0
0
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7,
7,
7,
LOW input
current
I IL
V
I
= 0V
-4.0
µA
, P100 to P107,
VCC = 3.3V
XIN, RESET, CNVss, BYTE
R PULLUP
Pull-up
resistance
P0
P3
P6
P8
0
0
0
6
to P0
to P3
to P6
7
7
7
, P1
, P4
, P7
0
0
2
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7
7
4
,
,
,
V
I
= 0V
20.0
2.0
100.0 500.0
kΩ
VCC = 3.3V
, P87, P9
0
to P9
7
,P10
0
to P10
7
R fXIN
R fXCIN
VRAM
Feedback resistance
Feedback resistance
RAM retention voltage
X
IN
3.0
MΩ
MΩ
V
XCIN
10.0
When clock is stopped
f(XIN) = 16MHz,
Square wave, no division
In single-chip
mode, the
output pins are
open and other
pins are VSS
mA
12.5
40.0
25.0
f(XCIN) = 32kHz, VCC = 3.3V
Square wave
µA
f(XCIN) = 32kHz, VCC = 3.3V
When a WAITinstruction
is executed.
Oscillation capacity High (Note 2)
5.8
2.7
µA
µA
µA
Icc
Power supply current
f(XCIN) = 32kHz, VCC = 3.3V
When a WAIT instruction
is executed.
Oscillation capacity Low (Note 2)
Topr = 25°C, VCC = 3.3V
when clock is stopped
0.1
0.4
2.0
Topr = 85°C, VCC = 3.3V
when clock is stopped
100
Note 1: Specify a product of -40°C to 85°C to use it.
Note 2: With one timer operated using fC32
.
148
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Table 1.26.4. A-D conversion characteristics (referenced to VCC = AVCC = VREF = 2.4V to 3.6V, VSS = AVSS = 0V,
o
o
o
o
at Topr = – 20 C to 85 C / – 40 C to 85 C (Note 4), f(XIN) =16MH
Z
unless otherwise specified)
Standard
Symbol
Paramete
Measuring condition
Unit
10 Bits
Min. Typ. Max.
V
REF
=
V
CC
Resolution
Absolute Sample & hold function not available
accuracy
V
REF = VCC = 3.3V
REF=VCC AN to AN
ANEX0, ANEX1 input
REF = VCC = 3.3V
LSB
LSB
LSB
LSB
±2
±2
±5
±5
±7
±2
40
V
0
7 input
Sample & hold function available(10bit)
= 3.3V
Sample & hold function available(8bit)
V
R
LADDER
Ladder resistance
Conversion time(10bit)
Conversion time(8bit)
Sampling time
V
REF
=
V
CC
10
3.3
2.8
0.3
2.4
kΩ
µs
t
t
t
CONV
CONV
µs
µs
V
SAMP
V
V
REF
IA
V
CC
Reference voltage
0
V
REF
V
Analog input voltage
Note 1: Do f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating
conditions of table 1.26.2. Divide the fAD if f(XIN) exceeds 10MHz, and make AD operation clock frequency
(ØAD) equal to or lower than 10MHz. And divide the fAD if VCC is less than 3.0V, and make AD operation
clock frequency (ØAD) equal to or lower than fAD/2.
Note 2: A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in
addition to a limit of Note 1.
A case with sample & hold function turn AD operation clock frequency (ØAD) into 1MHz or more in addition
to a limit of Note 1.
Note 3: Connect AVCC pin to VCC pin and apply the same electric potential.
Note 4: Specify a product of -40°C to 85°C to use it.
149
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Timing requirements
o
o
o
o
(referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20 C to 85 C / – 40 C to 85 C (*) unless otherwise specified)
* : Specify a product of -40°C to 85°C to use it.
Table 1.26.8. External clock input
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
tc
ns
ns
ns
ns
ns
External clock input cycle time
tw(H)
tw(L)
tr
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
25
15
15
tf
External clock fall time
Table 1.26.9. Memory expansion and microprocessor modes
Standard
Symbol
Parameter
Unit
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
Data input access time (no wait)
ns
ns
ns
(Note)
(Note)
(Note)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
tsu(DB-RD)
50
50
100
0
ns
ns
ns
ns
ns
ns
ns
tsu(RDY-BCLK )
tsu(HOLD-BCLK )
th(RD-DB)
RDY input setup time
HOLD input setup time
Data input hold time
th(BCLK -RDY)
th(BCLK-HOLD )
0
RDY input hold time
0
HOLD input hold time
HLDA output delay time
td(BCLK-HLDA )
40
Note: Calculated according to the BCLK frequency as follows:
109
f(BCLK) X 2
– 90
t
t
t
ac1(RD – DB) =
ac2(RD – DB) =
ac3(RD – DB) =
[ns]
3 X 109
f(BCLK) X 2
– 90
– 90
[ns]
[ns]
3 X 109
f(BCLK) X 2
150
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Timing requirements
o
o
o
o
(referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20 C to 85 C / – 40 C to 85 C (*) unless otherwise specified)
* : Specify a product of –40°C to 85°C to use it.
Table 1.26.10. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 1.26.11. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
400
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.12. Timer A input (external trigger input in one-shot timer mode)
Standard
Min. Max.
200
Symbol
Parameter
Unit
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
100
100
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.13. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.26.14. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
t
c(UP)
ns
ns
ns
ns
ns
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
t
h(TIN-UP)
400
151
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
Timing requirements
o
o
o
o
(referenced to VCC = 3.3V, VSS = 0V, at Topr = – 20 C to 85 C / – 40 C to 85 C (*) unless otherwise specified)
* : Specify a product of –40°C to 85°C to use it.
Table 1.26.15. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 1.26.16. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.26.17. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.26.18. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 1.26.19. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
100
0
50
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
_______
Table 1.26.20. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
152
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
o
o
o
Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20 C to 85 C / – 40 C to
o
85 C (Note 3), CM15 = “1” unless otherwise specified)
Table 1.26.21. Memory expansion and microprocessor modes (with no wait)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
ns
Min.
Max.
50
t
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
0
0
ns
ns
h(RD-AD)
t
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
d(BCLK-CS)
50
40
40
40
50
4
t
t
h(BCLK-CS)
d(BCLK-ALE)
Chip select output hold time (BCLK standard)
ALE signal output delay time
ns
ns
–4
t
h(BCLK-ALE)
ALE signal output hold time
ns
Figure 1.26.1
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output delay time
RD signal output hold time
ns
ns
0
0
t
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
WR signal output hold time
ns
ns
t
t
d(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
ns
ns
h(BCLK-DB)
4
(Note1)
t
t
d(DB-WR)
h(WR-DB)
Data output delay time (WR standard)
ns
ns
Data output hold time (WR standard)(Note2)
0
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) =
– 50
[ns]
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC
)
= 6.7ns.
Note 3: Specify a product of -40°C to 85°C to use it.
P0
P1
P2
P3
30pF
P4
P5
P6
P7
P8
P9
P10
Figure 1.26.1. Port P0 to P10 measurement circuit
153
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
o
o
o
Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20 C to 85 C / – 40 C to
o
85 C (Note 3), CM15 = “1” unless otherwise specified)
Table 1.26.22. Memory expansion and microprocessor modes
(when accessing external memory area with wait)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
50
t
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
Address output hold time (BCLK standard)
4
0
0
t
t
h(RD-AD)
Address output hold time (RD standard)
Address output hold time (WR standard)
ns
ns
h(WR-AD)
50
40
40
40
50
t
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
ns
ns
4
– 4
0
ns
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
t
ns
ns
Figure 1.26.1
t
d(BCLK-RD)
h(BCLK-RD)
t
t
RD signal output hold time
WR signal output delay time
ns
ns
d(BCLK-WR)
t
t
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
0
ns
ns
4
t
t
t
h(BCLK-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
ns
ns
ns
(Note1)
d(DB-WR)
h(WR-DB)
0
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) =
– 50
[ns]
f(BCLK)
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t = –CR X ln (1 – VOL / VCC
by a circuit of the right figure.
)
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC
)
= 6.7ns.
Note 3: Specify a product of -40°C to 85°C to use it.
154
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical characteristics
o
o
o
Switching characteristics (referenced to VCC = 3.3V, VSS = 0V at Topr = – 20 C to 85 C / – 40 C to
o
85 C (Note 2), CM15 = “1” unless otherwise specified)
Table 1.26.23. Memory expansion and microprocessor modes
(when accessing external memory area with wait, and select multiplexed bus)
Standard
Measuring condition
Symbol
Parameter
Address output delay time
Unit
Min.
Max.
50
t
d(BCLK-AD)
h(BCLK-AD)
ns
ns
ns
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
(Note1)
t
h(RD-AD)
(Note1)
t
h(WR-AD)
Address output hold time (WR standard)
ns
t
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
50
40
ns
ns
ns
ns
ns
ns
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
4
(Note1)
th(RD-CS)
(Note1)
t
h(WR-CS)
t
t
d(BCLK-RD)
h(BCLK-RD)
RD signal output hold time
0
0
Figure 1.26.1
t
t
t
d(BCLK-WR)
WR signal output delay time
40
50
ns
ns
ns
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
t
h(BCLK-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
4
ns
ns
(Note1)
t
d(DB-WR)
h(WR-DB)
(Note1)
t
Data output hold time (WR standard)
ns
ns
ns
ns
t
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
40
– 4
(Note1)
t
d(AD-ALE)
h(ALE-AD)
t
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
30
0
ns
ns
td(AD-RD)
t
d(AD-WR)
Post-address WR signal output delay time
Address output floating start time
0
ns
ns
t
dZ(RD-AD)
8
Note 1: Calculated according to the BCLK frequency as follows:
109
th(RD – AD) =
+ 0
+ 0
[ns]
f(BCLK) X 2
109
th(WR – AD) =
th(RD – CS) =
[ns]
[ns]
f(BCLK) X 2
109
+ 0
f(BCLK) X 2
109
th(WR – CS) =
td(DB – WR) =
+ 0
[ns]
[ns]
f(BCLK) X 2
9 X 3
10
f(BCLK) X 2
– 50
+ 0
109
th(WR – DB) =
td(AD – ALE) =
[ns]
[ns]
f(BCLK) X 2
109
– 40
f(BCLK) X 2
Note 2: Specify a product of -40°C to 85°C to use it.
155
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
tc(TA)
tw(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
t
su(UP–TIN)
t
h(TIN–UP)
(When count on falling
edge is selected)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
tw(TBH)
TBiIN input
tw(TBL)
t
c(AD)
tw(ADL)
ADTRG input
t
c(CK)
tw(CKH)
CLKi
TxDi
t
w(CKL)
t
h(C–Q)
t
su(D–C)
t
d(C–Q)
t
h(C–D)
RxDi
t
w(INL)
INTi input
t
w(INH)
Figure 1.26.2. Timing diagram (1)
156
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
Memory Expansion Mode and Microprocessor Mode
(Valid only with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Valid with or without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
td(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
• VCC=3.3V
• Input timing voltage : Determined with VIL=0.66V, VIH=2.64V
• Output timing voltage : Determined with VOL=1.65V, VOH=1.65V
Figure 1.26.3. Timing diagram (2)
157
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
Memory Expansion Mode and Microprocessor Mode
(With no wait)
Read timing
BCLK
t
d(BCLK–CS)
50ns.max
t
h(BCLK–CS)
4ns.min
CSi
t
h(RD–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
50ns.max
4ns.min
ADi
BHE
t
d(BCLK–ALE)
40ns.max
t
h(BCLK–ALE)
t
h(RD–AD)
0ns.min
–4ns.min
ALE
RD
DB
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
40ns.max
t
ac1(RD–DB)
Hi–Z
t
SU(DB–RD)
50ns.min
t
h(RD–DB)
0ns.min
Write timing
BCLK
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
50ns.max
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK-AD)
4ns.min
50ns.max
ADi
BHE
0ns.min
th(WR–AD)
t
h(BCLK–ALE)
t
d(BCLK–ALE)
–4ns.min
40ns.max
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
40ns.max
WR,WRL,
WRH
t
d(BCLK–DB)
50ns.max
Hi-Z
t
h(BCLK–DB)
4ns.min
DB
t
h(WR–DB)
0ns.min
t
d(DB–WR)
(tcyc/2–50)ns.min
Figure 1.26.4. Timing diagram (3)
158
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait)
Read timing
BCLK
CSi
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
50ns.max
t
h(RD–CS)
0ns.min
tcyc
t
d(BCLK–AD)
50ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
40ns.max
td(BCLK–ALE)
t
h(BCLK–ALE)
–4ns.min
t
h(RD–AD)
0ns.min
ALE
RD
DB
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
40ns.max
tac2(RD–DB)
Hi–Z
t
h(RD–DB)
0ns.min
t
SU(DB–RD)
50ns.min
Write timing
BCLK
t
d(BCLK–CS)
50ns.max
t
h(BCLK–CS)
4ns.min
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
50ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
d(BCLK–ALE)
40ns.max
t
h(WR–AD)
0ns.min
t
h(BCLK–ALE)
–4ns.min
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
40ns.max
WR,WRL,
WRH
t
d(BCLK–DB)
50ns.max
t
h(BCLK–DB)
4ns.min
DBi
t
h(WR–DB)
0ns.min
t
d(DB–WR)
(tcyc–50)ns.min
Measuring conditions :
• VCC=3.3V
• Input timing voltage : Determined with: VIL=0.52V, VIH=1.65V
• Output timing voltage : Determined with: VOL=1.65V, VOH=1.65V
Figure 1.26.5. Timing diagram (4)
159
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
tcyc
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
50ns.max
t
h(RD–CS)
(tcyc/2)ns.min
CSi
t
d(AD–ALE)
(tcyc/2-40)ns.min
t
h(ALE–AD)
30ns.min
ADi
Address
Data input
Address
t
h(RD–DB)
0ns.min
/DBi
t
ac3(RD–DB)
t
dz(RD–AD)
8ns.max
t
SU(DB–RD)
50ns.min
t
d(AD–RD)
0ns.min
t
d(BCLK–AD)
50ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
–4ns.min
t
h(RD–AD)
(tcyc/2)ns.min
40ns.max
ALE
RD
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
40ns.max
Write timing
BCLK
t
h(BCLK–CS)
tcyc
t
d(BCLK–CS)
50ns.max
4ns.min
t
h(WR–CS)
(tcyc/2)ns.min
CSi
t
h(BCLK–DB)
4ns.min
t
d(BCLK–DB)
50ns.max
Data output
ADi
Address
Address
/DBi
t
d(DB–WR)
t
h(WR–DB)
t
d(AD–ALE)
(tcyc/2–40)ns.min
(tcyc*3/2–50)ns.min
(tcyc/2)ns.min
t
d(BCLK–AD)
50ns.max
t
h(BCLK–AD)
4ns.min
ADi
BHE
t
h(BCLK–ALE)
–4ns.min
t
d(AD–WR)
0ns.min
t
d(BCLK–ALE)
40ns.max
t
h(WR–AD)
(tcyc/2)ns.min
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
40ns.max
WR,WRL,
WRH
Measuring conditions :
• VCC=3.3V
• Input timing voltage : Determined with VIL=0.52V, VIH=1.65V
• Output timing voltage : Determined with VOL=1.65V, VOH=1.65V
Figure 1.26.6. Timing diagram (5)
160
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Package Outline
Package Outline
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
JEDEC Code
Weight(g)
1.58
Lead Material
Alloy 42
M
D
QFP100-P-1420-0.65
–
HD
D
100
81
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
b
c
D
E
e
30
51
31
50
HD
A
L1
HE
L
L1
x
y
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
x
M
I
2
–
–
–
Detail F
y
M
M
D
E
–
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
0.63
Lead Material
Cu Alloy
M
D
LQFP100-P-1414-0.50
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
A
1
0
0.1
2
–
1.4
b
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
c
D
E
e
25
51
H
H
L
D
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
E
A
L
1
L1
F
e
Lp
A3
x
y
–
b
x
y
L
M
b2
0.225
–
14.4
14.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
161
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR difference between M16C/62N and M16C/30L
SFR difference between M16C/62N and M16C/30L
Address
Symbol
M16C/62N
M16C/30L
0005
PM1
Processor mode register 1
bit0:Reserved bit
Processor mode register 1
bit0:Reserved bit
bit1:Nothing is assigned
bit2:Nothing is assigned
PM13:Internal reserved area expansion bit
PM14:Memory area expantion bit
PM15:
bit1:Nothing is assigned
bit2:Nothing is assigned
bit3:Reserved bit
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
bit6:Reserved bit
PM17:Wait bit
PM17:Wait bit
000A
PRCR
Protect register
Protect register
PRC0:Enables writing to system clock control registers 0
and 1
PRC0:Enables writing to system clock control registers 0
and 1
PRC1:Enables writing to processor mode registers 0 and 1
PRC2:Enables writing to port P9 direction register
and SI/O control register
PRC1:Enables writing to processor mode registers 0 and 1
PRC2:Enables writing to port P9 direction register
bit3-bit7:Nothing is assigned
bit3-bit7:Nothing is assigned
000B
0030
0031
0032
0034
0035
0036
0038
0039
003C
0044
0045
0046
0047
0048
0049
004C
0058
0059
005A
0340
0342
0343
0344
0345
0346
0347
0348
0349
034A
034B
034C
034D
0350
0351
0352
0353
0354
0355
035B
035C
035D
DBR
Data bank register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Don't access a Reserved register.
SAR1
SAR1
SAR1
DAR1
DAR1
DAR1
TCR1
TCR1
DM1CON
INT3IC
TB5IC
TB4IC
TB3IC
S4IC/INT5IC
S3IC/INT4IC
DM1IC
TA3IC
TA4IC
TB0IC
TBSR
TA11
DMA1 source pointer
DMA1 source pointer
DMA1 source pointer
DMA1 destination pointer
DMA1 destination pointer
DMA1 destination pointer
DMA1 transfer counter
DMA1 transfer counter
DMA1 control register
INT3 interrupt control register
Timer B5 interrupt control register
Timer B4 interrupt control register
Timer B3 interrupt control register
SI/O4,INT5 interrupt control register
SI/O3,INT4 interrupt control register
DMA1 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B3, 4, 5 count start flag
Timer A1-1 register
TA11
Timer A1-1 register
TA21
Timer A2-1 register
TA21
Timer A2-1 register
TA41
Timer A4-1 register
TA41
Timer A4-1 register
INVC0
INVC1
IDB0
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Dead time timer
IDB1
DTT
ICTB2
TB3
Timer B2 interrupt occurrence frequency set counter
Timer B3 register
TB3
Timer B3 register
TB4
Timer B4 register
TB4
Timer B4 register
TB5
Timer B5 register
TB5
Timer B5 register
TB3MR
TB4MR
TB5MR
Timer B3 mode register
Timer B4 mode register
Timer B5 mode register
162
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR difference between M16C/62N and M16C/30L
SFR difference between M16C/62N and M16C/30L
Address
035F
Symbol
M16C/62N
M16C/30L
IFSR
Interrupt cause select register
Interrupt cause select register
IFSR0:INT0 interrupt polarity switching bit
IFSR1:INT1 interrupt polarity switching bit
IFSR2:INT2 interrupt polarity switching bit
IFSR3:INT3 interrupt polarity switching bit
IFSR4:INT4 interrupt polarity switching bit
IFSR5:INT5 interrupt polarity switching bit
IFSR6:Interrupt request cause select bit
IFSR7:Interrupt request cause select bit
IFSR0:INT0 interrupt polarity switching bit
IFSR1:INT1 interrupt polarity switching bit
IFSR2:INT2 interrupt polarity switching bit
bit3:Reserved bit
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
bit7:Reserved bit
0360
0362
0363
0364
0366
0367
S3TRR
S3C
SI/O3 transmit/receive register
SI/O3 control register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
Reserved register
S3BRG
S4TRR
S4C
SI/O3 bit rate generator
SI/O4 transmit/receive register
SI/O4 control register
S4BRG
SI/O4 bit rate generator
0380
TABSR
Count start flag
Count start flag
TA0S:Timer A0 count start flag
TA1S:Timer A1 count start flag
TA2S:Timer A2 count start flag
TA3S:Timer A3 count start flag
TA4S:Timer A4 count start flag
TB0S:Timer B0 count start flag
TB1S:Timer B1 count start flag
TB2S:Timer B2 count start flag
TA0S:Timer A0 count start flag
TA1S:Timer A1 count start flag
TA2S:Timer A2 count start flag
bit3:Reserved bit
bit4:Reserved bit
bit5:Reserved bit
TB1S:Timer B1 count start flag
TB2S:Timer B2 count start flag
0382
ONSF
One-shot start flag
One-shot start flag
TA0OS:Timer A0 one-shot start flag
TA1OS:Timer A1 one-shot start flag
TA2OS:Timer A2 one-shot start flag
TA3OS:Timer A3 one-shot start flag
TA4OS:Timer A4 one-shot start flag
bit5:Nothing is assigned
TA0OS:Timer A0 one-shot start flag
TA1OS:Timer A1 one-shot start flag
TA2OS:Timer A2 one-shot start flag
bit3:Reserved bit
bit3:Reserved bit
bit5:Nothing is assigned
TA0TGL:Timer A0 event/trigger select bit
TA0TGH: "00","01","10"and"11" can be chosen.
TA0TGL:Timer A0 event/trigger select bit
TA0TGH: "00 ","01"and"11" can be chosen. "10" can't be
chosen.
0383
TRGSR
Trigger select register
Trigger select register
TA1TGL:Timer A1 event/trigger select bit
TA1TGH: "00","01","10"and"11" can be chosen.
TA2TGL:Timer A2 event/trigger select bit
TA2TGH: "00","01","10"and"11" can be chosen.
TA1TGL:Timer A1 event/trigger select bit
TA1TGH: "00","01","10"and"11" can be chosen.
TA2TGL:Timer A2 event/trigger select bit
TA2TGH: "00","01"and"10" can be chosen. "11" can't be
chosen.
TA3TGL:Timer A3 event/trigger select bit
TA3TGH: "00","01","10"and"11" can be chosen.
TA4TGL:Timer A4 event/trigger select bit
TA4TGH: "00","01","10"and"11" can be chosen.
bit4:Reserved bit
bit5:Reserved bit
bit6:Reserved bit
bit7:Reserved bit
0384
UDF
Up-down flag
Up-down flag
TA0UD:Timer A0 up/down flag
TA1UD:Timer A1 up/down flag
TA2UD:Timer A2 up/down flag
TA3UD:Timer A3 up/down flag
TA4UD:Timer A4 up/down flag
TA2P:Timer A2 two-phase pulse signal processing select bit
TA0UD:Timer A0 up/down flag
TA1UD:Timer A1 up/down flag
TA2UD:Timer A2 up/down flag
bit3:Reserved bit
bit4:Reserved bit
TA2P:Timer A2 two-phase pulse signal processing select bit
TA3P:Timer A3 two-phase pulse signal processing select bit6:Reserved bit
bit
TA4P:Timer A4 two-phase pulse signal processing select bit7:Reserved bit
bit
038C
038D
038E
038F
0390
0391
0399
039A
039B
TA3
Timer A3
Reserved register
TA3
Timer A3
Reserved register
TA4
Timer A4
Reserved register
TA4
Timer A4
Reserved register
TB0
Timer B0
Reserved register
TB0
Timer B0
Reserved register
TA3MR
TA4MR
TB0MR
Timer A3 mode register
Timer A4 mode register
Timer B0 mode register
Reserved register
Reserved register
Reserved register
Don't access a Reserved register.
163
Mitsubishi microcomputers
M16C / 30L Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR difference between M16C/62N and M16C/30L
SFR difference between M16C/62N and M16C/30L
Address
039C
Symbol
M16C/62N
M16C/30L
TB1MR
Timer B1 mode register
Timer B1 mode register
Event counter mode
Event counter mode
TMOD0:Operation mode select bit
TMOD0:Operation mode select bit
TMOD1:
TMOD1:
MR0:Count polarity select bit
MR0:Count polarity select bit
MR1:
MR1:
MR2:Nothing is assigned
MR2:Nothing is assigned
MR3:Invalid
MR3:Invalid
TCK1:Event clock select "0 " can be chosen. "1" can't be
chosen.
TCK1:Event clock select "0" and "1" can be chosen.
03B4
FIDR
Flash identification register
Reserved register
Reserved register
03B7
03B8
FMR0
Flash memory control register 0
DM0SL
DMA0 request cause select register
DMA0 request factors
Falling edge of INT0 pin
Software trigger
Timer A0
DMA0 request cause select register
DMA0 request factors
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A1
Timer A2
Timer A2
Timer A3
Timer A4
two edges of INT0 pin
Timer B0
two edges of INT0 pin
Timer B1
Timer B1
Timer B2
Timer B2
Timer B3
Timer B4
Timer B5
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
UART1 transmit
A-D conversion
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
UART1 transmit
A-D conversion
03BA
03BC
03BD
03BE
DM1SL
CRCD
CRCIN
CRCIN
DMA1 request cause select register
CRC data register
Reserved register
Reserved register
Reserved register
Reserved register
CRC data register
CRC input register
03D4
ADCON2
A-D control register 2
A-D control register 2
SMP:A-D conversion method select bit
bit1:Reserved bit
SMP:A-D conversion method select bit
ADGSL0:Analog input group select bit
ADGSL1:
bit2:Reserved bit
bit3:Reserved bit
bit3:Reserved bit
bit4-bit7:Nothing is assigned
bit4-bit7:Nothing is assigned
03D6
ADCON0
A-D control register 0
CH0:Analog input pin select bit
CH1:
A-D control register 0
CH0:Analog input pin select bit
CH1:
CH2:
CH2:
MD0:A-D operation mode select bit 0
MD1: "00","01","10"and"11" can be chosen
MD0:A-D operation mode select bit 0
MD1: "00 " can be chosen. "01","10"and"11" can't be
chosen.
TRG:Trigger select bit
ADST:A-D conversion start flag
CKS0:Frequency select bit 0
TRG:Trigger select bit
ADST:A-D conversion start flag
CKS0:Frequency select bit 0
03D7
ADCON1
A-D control register 1
A-D control register 1
bit0:Reserved bit
SCAN0:A-D sweep pin select bit
SCAN1:
bit1:Reserved bit
MD2:A-D operation mode select bit 1
BITS:8/10-bit mode select bit
CKS1:Frequency select bit 1
VCUT:Vref connect bit
OPA0:External op-amp connection mode bit
OPA1:
bit2:Reserved bit
BITS:8/10-bit mode select bit
CKS1:Frequency select bit 1
VCUT:Vref connect bit
OPA0:External op-amp connection mode bit
OPA1:
03D8
03DA
03DC
DA0
D-A register 0
Reserved register
DA1
D-A register 1
Reserved register
DACON
D-A control register
Reserved register
Don't access a Reserved register.
164
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
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© 2002 MITSUBISHI ELECTRIC CORP.
Printed in Japan (ROD) II
New publication, effective June. 2002.
Specifications subject to change without notice.
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