M30622SPGP-U5_技术文档

M16C/62P Group (M16C/62P, M16C/62PT)

REJ03B0001-0230Z

Rev.2.30

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Sep 01, 2004

1. Overview

The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high-

performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin,

100-pin and 128-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated

instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are ca-

pable of executing instructions at high speed. In addition, this microcomputer contains a multiplier and

DMAC which combined with fast instruction processing capability, makes it suitable for control of various

OA, communication, and industrial equipment which requires high-speed arithmetic/logic operations.

1.1 Applications

Audio, cameras, television, home appliance, office/communications/portable/industrial equipment,

automobile, etc

Specifications written in this manual are believed to be accurate, but are

not guaranteed to be entirely free of error. Specifications in this manual

may be changed for functional or performance improvements. Please make

sure your manual is the latest edition.

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

1.2 Performance Outline

Table 1.1 to table 1.3 list performance outline of M16C/62P group (M16C/62P, M16C/62PT).

Table 1.1 Performance Outline of M16C/62P group (M16C/62P) (128-pin version)

Item

Performance

M16C/62P

Number of Basic Instructions

91 instructions

CPU

Minimum Instruction Execution Time

41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation Mode

Memory Space

Single-chip, memory expansion and microprocessor mode

1 Mbyte (Available to 4 Mbytes by memory space

expansion function)

Memory Capacity

Port

See Table 1.4 and 1.5 Product List

Input/Output : 113 pins, Input : 1 pin

Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels

Three phase motor control circuit

3 channels

Peripheral

Function

Multifunction Timer

Serial I/O

Clock synchronous, UART,

I²C bus ⁽¹⁾, IEBus ⁽²⁾

2 channels

Clock synchronous

A/D Converter

D/A Converter

DMAC

10-bit A/D converter: 1 circuit, 26 channels

8 bits x 2 channels

2 channels

CRC Calculation Circuit

Watchdog Timer

Interrupt

CCITT-CRC

15 bits x 1 channel (with prescaler)

Internal: 29 sources, External: 8 sources, Software: 4 sources,

Priority level: 7 levels

Clock Generation Circuit

4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

On-chip oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Stop detection of main clock oscillation, re-oscillation detection

function

Oscillation Stop Detection Function

Voltage Detection Circuit

Supply Voltage

Available (option ⁽⁴⁾

)

VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1 (f(BCLK)=10MHz)

14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)

8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)

1.8 µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)

0.7 µ A (VCC1=VCC2=3V, stop mode)

3.3 ± 0.3 V or 5.0 ± 0.5 V

Electric

Characteris-

tics

Power Consumption

Program/Erase Supply Voltage

Program and Erase Endurance

Flash Memory

Version

100 times (all area)

or 1,000 times (user ROM area without block 1)

/ 10,000 times (block A, block 1) ⁽³⁾

–20 to 85^oC

Operating Ambient Temperature

–40 to 85^oC ⁽³⁾

Package

NOTES:

128-pin plastic mold LQFP

1. I²C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.

In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.

4. All options are on request basis.

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.2 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (100-pin version)

Item

Performance

M16C/62PT^{(Note 4)}

M16C/62P

CPU

Number of Basic Instructions 91 instructions

Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation Mode

Single-chip, memory expansion and Single-chip mode

microprocessor mode

Memory Space

1 Mbyte (Available to 4 Mbytes by 1 Mbyte

memory space expansion function)

See Table 1.4 to 1.7 Product List

Input/Output : 87 pins, Input : 1pin

Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels

Three phase motor control circuit

3 channels

Memory Capacity

Port

Peripheral

function

Multifunction Timer

Serial I/O

Clock synchronous, UART,

I²C bus ⁽¹⁾, IEBus ⁽²⁾

2 channels

Clock synchronous

A/D Converter

D/A Converter

DMAC

10-bit A/D converter: 1 circuit, 26 channels

8 bits x 2 channels

2 channels

CRC Calculation Circuit

Watchdog Timer

Interrupt

CCITT-CRC

15 bits x 1 channel (with prescaler)

Internal: 29 sources, External: 8 sources, Software: 4 sources,

Priority level: 7 levels

Clock Generation Circuit

4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

On-chip oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function

Voltage Detection Circuit

Supply Voltage

Available (option ⁽⁵⁾

)

Absent

Electric

characteris-

tics

VCC1=3.0 to 5.5V, VCC2=2.7V to VCC1 VCC1=VCC2=4.0V to 5.5 V

(f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, VCC2=2.7V to VCC1

(f(BCLK)=10MHz)

Power Consumption

14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)

8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=VCC2=5V,

1.8 µA (VCC1=VCC2=3V,

f(XCIN)=32kHz, wait mode)

0.7 µ A (VCC1=VCC2=3V, stop mode)

3.3 ± 0.3 V or 5.0 ± 0.5 V

f(XCIN)=32kHz, wait mode)

0.8 µ A (VCC1=VCC2=5V, stop mode)

Flash memory

Version

Program/Erase Supply Voltage

Program and Erase Endurance

5.0 ± 0.5 V

100 times (all area)

or 1,000 times (user ROM area without block 1)

/ 10,000 times (block A, block 1) ⁽³⁾

Operating Ambient Temperature

–20 to 85^oC

–40 to 85^oC ⁽³⁾

T version : –40 to 85^oC

V version : –40 to 125^oC

Package

NOTES:

100-pin plastic mold QFP, LQFP

1. I²C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature.

In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.

4. Use the M16C/62PT on VCC1 = VCC2.

5. All options are on request basis.

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.3 Performance outline of M16C/62P group (M16C/62P, M16C/62PT) (80-pin version)

Item

Performance

M16C/62P

M16C/62PT

CPU

Number of Basic Instructions 91 instructions

Minimum Instruction Execution Time 41.7ns(f(BCLK)=24MHz, VCC1=3.0 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)

100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)

Operation Mode

Memory Space

Memory Capacity

Port

Single-chip mode

1 Mbyte

See Table 1.4 to 1.7 Product List

Input/Output : 70 pins, Input : 1pin

Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer)

Timer B : 16 bits x 6 channels (Timer B1 is internal timer)

2 channels

Peripheral

function

Multifunction Timer

Serial I/O

Clock synchronous, UART,

I²C bus⁽¹⁾, IEBus⁽²⁾

1 channel

Clock synchronous,

I²C bus⁽¹⁾, IEBus⁽²⁾

2 channels

Clock synchronous (1 channel is only for transmission)

10-bit A/D converter: 1 circuit, 26 channels

8 bits x 2 channels

A/D Converter

D/A Converter

DMAC

2 channels

CRC Calculation Circuit

Watchdog Timer

Interrupt

CCITT-CRC

15 bits x 1 channel (with prescaler)

Internal: 29 sources, External: 5 sources, Software: 4 sources,

Priority level: 7 levels

Clock Generating Circuit

4 circuits

Main clock generation circuit (*),

Subclock generation circuit (*),

On-chip oscillator, PLL synthesizer

(*)Equipped with a built-in feedback resistor.

Oscillation Stop Detection Function Stop detection of main clock oscillation, re-oscillation detection function

Voltage Detection Circuit

Supply Voltage

Available (option ⁽⁴⁾

)

Absent

Electric

characteris-

tics

VCC1=3.0 to 5.5V, (f(BCLK)=24MHz) VCC1=4.0 to 5.5V, (f(BCLK)=24MHz)

VCC1=2.7 to 5.5V, (f(BCLK)=10MHz)

Power Consumption

14 mA (VCC1=5V, f(BCLK)=24MHz) 14 mA (VCC1=5V, f(BCLK)=24MHz)

8 mA (VCC1=3V, f(BCLK)=10MHz) 2.0 µA (VCC1=5V,

1.8 µA (VCC1=3V,

f(XCIN)=32kHz, wait mode)

0.7 µ A (VCC1=3V, stop mode)

0.8 µ A (VCC1=5V, stop mode)

Flash

Program/Erase Supply Voltage 3.3 ± 0.3 V or 5.0 ± 0.5 V

Program and Erase Endurance 100 times (all area)

5.0 ± 0.5 V

memory

Version

or 1,000 times (user ROM area without block 1)

/ 10,000 times (block A, block 1) ⁽³⁾

Operating Ambient Temperature

–20 to 85^oC

–40 to 85^oC(option)

T version : –40 to 85^oC

V version : –40 to 125^oC

Package

NOTES :

80-pin plastic mold QFP

1. I²C bus is a registered trademark of Koninklijke Philips Electronics N. V.

2. IEBus is a registered trademark of NEC Electronics Corporation.

3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient temperature.

In addition 1,000 times/10,000 times are under development as of Sep., 2004. Please inquire about a release schedule.

4. All options are on request basis.

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

1.3 Block Diagram

Figure 1.1 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin ver-

sion, figure 1.2 is a block diagram of the M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version.

8

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

<VCC2 ports>⁽⁴⁾

<VCC1 ports>⁽⁴⁾

Internal peripheral functions

Timer (16-bit)

System clock

generation circuit

A/D converter

(10 bits

X 8 channels

Expandable up to 26 channels)

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Output (timer A): 5

Input (timer B): 6

UART or

clock synchronous serial I/O

(8 bits

X 3 channels)

Three-phase motor

control circuit

CRC arithmetic circuit (CCITT )

Clock synchronous serial I/O

16

12

5

(Polynomial : X +X +X +1)

(8 bits

X

2 channels)

M16C/60 series16-bit CPU core

Memory

(1)

SB

USP

ISP

INTB

PC

FLG

R0H

R1H

R0L

R1L

ROM

Watchdog timer

(15 bits)

R2

R3

(2)

RAM

DMAC

(2 channels)

A0

A1

FB

D/A converter

(8 bits X 2 channels)

Multiplier

<VCC1 ports>⁽⁴⁾

<VCC2 ports>⁽⁴⁾

Port P11

Port P14

Port P13

Port P12

(3)

8

2

8

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

3. Ports P11 to P14 exist only in 128-pin version.

4. Use M16C/62PT on VCC1= VCC2.

Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

8

4

8

Port P0

Port P2

Port P3

Port P4

Port P5

Port P6

(4)

Internal peripheral functions

Timer (16-bit)

System clock

generation circuit

A/D converter

(10 bits

X 8 channels

Expandable up to 26 channels)

XIN-XOUT

XCIN-XCOUT

PLL frequency synthesizer

On-chip oscillator

Output (timer A): 5

Input (timer B): 6

UART or

clock synchronous serial I/O (2 channels)

UART

(1 channel)

(3)

Clock synchronous serial I/O

(8 bits

X

2 channels)

CRC arithmetic circuit (CCITT )

(Polynomial : X +X +X +1)

16

12

5

Memory

M16C/60 series16-bit CPU core

Watchdog timer

(15 bits)

R0H

R1H

R0L

R1L

SB

(1)

ROM

USP

R2

R3

DMAC

(2 channels)

ISP

(2)

RAM

INTB

PC

FLG

A0

A1

FB

D/A converter

(8 bits X 2 channels)

Multiplier

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).

4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.

Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

1.4 Product List

Tables 1.4 to 1.7 list the product list, figure 1.3 shows the type numbers, memory sizes and packages, table

1.8 lists the product code of flash memory version and ROMless version for M16C/62P, and table 1.9 lists

the product code of flash memory version for M16C/62PT. Figure 1.4 shows the marking diagram of flash

memory version and ROMless version for M16C/62P, and figure 1.5 shows the marking diagram of flash

memory version for M16C/62PT. Please specify the mark of the mask ROM version at the time of ROM

order.

Table 1.4 Product List (1) (M16C/62P)

As of Sep. 2004

Remarks

Type No.

ROM Capacity

Package Type

100P6S-A

RAM Capacity

4 Kbytes

M30622M6P-XXXFP

100P6Q-A

48 Kbytes

M30622M6P-XXXGP

M30623M6P-XXXGP

M30622M8P-XXXFP

M30622M8P-XXXGP

M30623M8P-XXXGP

(D)

80P6S-A

100P6S-A

100P6Q-A

80P6S-A

4 Kbytes

5 Kbytes

64 Kbytes

96 Kbytes

100P6S-A

100P6Q-A

M30622MAP-XXXFP

M30622MAP-XXXGP

M30623MAP-XXXGP

M30620MCP-XXXFP

M30620MCP-XXXGP

80P6S-A

(D)

100P6S-A

128 Kbytes

192 Kbytes

10 Kbytes

12 Kbytes

100P6Q-A

80P6S-A

M30621MCP-XXXGP

M30622MEP-XXXFP

100P6S-A

100P6Q-A

M30622MEP-XXXGP

M30623MEP-XXXGP

128P6Q-A

100P6S-A

Mask ROM version

M30622MGP-XXXFP

M30622MGP-XXXGP

M30623MGP-XXXGP

100P6Q-A

128P6Q-A

100P6S-A

100P6Q-A

128P6Q-A

100P6S-A

100P6Q-A

128P6Q-A

100P6S-A

100P6Q-A

128P6Q-A

100P6S-A

100P6Q-A

128P6Q-A

(D)

256 Kbytes

M30624MGP-XXXFP

M30624MGP-XXXGP

M30625MGP-XXXGP

20 Kbytes

16 Kbytes

24 Kbytes

31 Kbytes

M30622MWP-XXXFP

M30622MWP-XXXGP

M30623MWP-XXXGP

M30624MWP-XXXFP

M30624MWP-XXXGP

M30625MWP-XXXGP

M30626MWP-XXXFP

M30626MWP-XXXGP

M30627MWP-XXXGP

320 Kbytes

(D)

(D): Under development

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.5 Product List (2) (M16C/62P)

As of Sep. 2004

Remarks

Type No.

ROM Capacity ROM Capacity Package Type

100P6S-A

M30622MHP-XXXFP

M30622MHP-XXXGP

M30623MHP-XXXGP

16 Kbytes

100P6Q-A

128P6Q-A

100P6S-A

100P6Q-A

128P6Q-A

(D)

M30624MHP-XXXFP

M30624MHP-XXXGP

M30625MHP-XXXGP

384 Kbytes

24 Kbytes

31 Kbytes

(D)

Mask ROM version

M30626MHP-XXXFP

M30626MHP-XXXGP

100P6S-A

100P6Q-A

128P6Q-A

M30627MHP-XXXGP

M30626MJP-XXXFP

M30626MJP-XXXGP

M30627MJP-XXXGP

(P)

100P6S-A

100P6Q-A

128P6Q-A

31 Kbytes

4 Kbytes

512 Kbytes

(P)

M30622F8PFP

M30622F8PGP

100P6S-A

100P6Q-A

80P6S-A

64K+4 Kbytes

M30623F8PGP

M30620FCPFP

M30620FCPGP

(D)

100P6S-A

100P6Q-A

80P6S-A

128K+4 Kbytes 10 Kbytes

256K+4 Kbytes 20 Kbytes

384K+4 Kbytes 31 Kbytes

M30621FCPGP

M30624FGPFP

100P6S-A

M30624FGPGP

M30625FGPGP

100P6Q-A

128P6Q-A

Flash memory version

M30626FHPFP

M30626FHPGP

M30627FHPGP

100P6S-A

100P6Q-A

128P6Q-A

M30626FJPFP

M30626FJPGP

M30627FJPGP

(P)

100P6S-A

100P6Q-A

128P6Q-A

100P6S-A

100P6Q-A

(P) 512K+4 Kbytes 31 Kbytes

(P)

M30622SPFP

M30622SPGP

4 Kbytes

ROMless version

M30620SPFP

M30620SPGP

100P6S-A

100P6Q-A

10 Kbytes

(D): Under development

(P): Under planning

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.6 Product List (3) (T version (M16C/62PT))

As of Sep. 2004

Remarks

ROM Capacity

Type No.

RAM Capacity

Package Type

100P6S-A

100P6Q-A

80P6S-A

(D)

(P)

(D)

M3062CM6T-XXXFP

M3062CM6T-XXXGP

M3062EM6T-XXXGP

M3062CM8T-XXXFP

48 Kbytes

4 Kbytes

100P6S-A

64 Kbytes

96 Kbytes

4 Kbytes

5 Kbytes

100P6Q-A

M3062CM8T-XXXGP

(P)

80P6S-A

M3062EM8T-XXXGP

M3062CMAT-XXXFP

Mask ROM

version

100P6S-A

(D)

(P)

(D)

(P)

(D)

100P6Q-A

80P6S-A

M3062CMAT-XXXGP

M3062EMAT-XXXGP

T Version

(High reliability

85 °C Version)

100P6S-A

M3062AMCT-XXXFP

M3062AMCT-XXXGP

M3062BMCT-XXXGP

M3062CF8TFP

128 Kbytes

64 Kbytes

10 Kbytes

4 Kbytes

100P6Q-A

80P6S-A

100P6S-A

100P6Q-A

100P6S-A

M3062CF8TGP

M3062AFCTFP

M3062AFCTGP

M3062BFCTGP

M3062JFHTFP

M3062JFHTGP

Flash memory

version

128K+4 Kbytes 10 Kbytes

384K+4 Kbytes 31 Kbytes

100P6Q-A

80P6S-A

(P)

(D)

100P6S-A

100P6Q-A

(D): Under development

(P): Under planning

Table 1.7 Product List (4) (V version (M16C/62PT))

As of Sep. 2004

Type No.

ROM Capacity RAM Capacity

Remarks

Package Type

M3062CM6V-XXXFP

M3062CM6V-XXXGP

M3062EM6V-XXXGP

M3062CM8V-XXXFP

M3062CM8V-XXXGP

M3062EM8V-XXXGP

(P)

100P6S-A

100P6Q-A

(P) 48 Kbytes

(P)

4 Kbytes

5 Kbytes

80P6S-A

(P)

100P6S-A

100P6Q-A

(P) 64 Kbytes

(P)

80P6S-A

M3062CMAV-XXXFP

M3062CMAV-XXXGP

M3062EMAV-XXXGP

(P)

100P6S-A

100P6Q-A

Mask ROM

version

V Version

(P) 96 Kbytes

(High reliability

125 °C Version)

(P)

80P6S-A

M3062AMCV-XXXFP

(D)

100P6S-A

100P6Q-A

80P6S-A

M3062AMCV-XXXGP

M3062BMCV-XXXGP

(D) 128 Kbytes

10 Kbytes

(P)

(D)

M3062AFCVFP

M3062AFCVGP

M3062BFCVGP

M3062JFHVFP

M3062JFHVGP

100P6S-A

100P6Q-A

128K+4 Kbytes 10 Kbytes

384K+4 Kbytes 31 Kbytes

(D)

Flash memory

version

80P6S-A

(P)

100P6S-A

100P6Q-A

(D): Under development

(P): Under planning

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Type No.

M 3 0 6 2 6 M H P – X X X F P

Package type:

FP : Package 100P6S-A

GP : Package 80P6Q-A, 100P6Q-A, 128P6Q-A

ROM No.

Omitted for flash memory version and

ROMless version

Classification

P : M16C/62P

T : T version (M16C/62PT)

V : V version (M16C/62PT)

ROM capacity:

6: 48 Kbytes

8: 64 Kbytes

A: 96 Kbytes

C: 128 Kbytes

E: 192 Kbytes

G: 256 Kbytes

W: 320 Kbytes

H: 384 Kbytes

J: 512 Kbytes

Memory type:

M: Mask ROM version

F: Flash memory version

S: ROMless version

Shows RAM capacity, pin count, etc

Numeric : M16C/62P

Alphabet : M16C/62PT

M16C/62P Group

M16C Family

Figure 1.3 Type No., Memory Size, and Package

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P

Internal ROM

(User ROM Area

(Block A, Block 1)

Operating

Ambient

Temperature

Product

Code

Without Block 1)

Package

Program

and Erase

Endurance

Temperature

Range

Temperature

Range

Program

and Erase

Endurance

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

-40°C to 85°C

-20°C to 85°C

D3

D5

D7

D9

U3

U5

U7

U9

D3

D5

U3

U5

0°C to 60°C

100

10,000

100

Lead-included

Lead-free

-40°C to 85°C

-20°C to 85°C

1,000

Flash Memory

Version

0°C to 60°C

100

-40°C to 85°C

-20°C to 85°C

1,000

10,000

Lead-included

Lead-free

ROMless Version

M 1 6 C

Type No. (See Figure 1.3 Type No., Memory Size, and Package)

M 3 0 6 2 6 F H P F P

B D 5

Chip version and product code

B

: Shows chip version.

Henceforth, whenever it changes a version, it continues with B, C, and D.

X X X X X X X

D5 : Shows Product code. (See table 1.8 Product Code)

Date code seven digits

The product without marking of chip version of the flash memory version and the ROMless version

corresponds to the chip version “A”.

Figure 1.4 Marking Diagram of Flash Memory version and ROMless version for M16C/62P (Top View)

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

Table 1.9 Product Code of Flash Memory version for M16C/62PT

Internal ROM

(User ROM Area

Without Block 1)

Internal ROM

(Block A, Block 1)

Operating

Ambient

Temperature

Product

Code

Package

Program

and Erase

Endurance

Temperature

Range

Temperature

Program

and Erase

Endurance

Range

T Version

V Version

T Version

V Version

T Version

V Version

T Version

V Version

-40°C to 85°C

-40°C to 125°C

-40°C to 85°C

B

100

0°C to 60°C

Lead-included

Lead-free

-40°C to 85°C

B7

U

1,000

100

10,000

100

Flash

Memory

Version

-40°C to 125°C -40°C to 125°C

0°C to 60°C

-40°C to 85°C

0°C to 60°C

-40°C to 125°C

-40°C to 85°C

U7

1,000

10,000

-40°C to 125°C -40°C to 125°C

M 1 6 C

M 3 0 6 2 J F H T F P

Y YY X X X X X XX

Type No. (See Figure 1.3 Type No., Memory Size, and Package)

Date code seven digits

Product code. (See table 1.9 Product Code)

“

” : Product code “B”

“ P B F ” : Product code “U”

“ B 7

“ U 7

” : Product code “B7”

” : Product code “U7”

NOTES:

1.

: Blank

Figure 1.5 Marking Diagram of Flash Memory version for M16C/62PT (Top View)

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

1.5 Pin Configuration

Figures 1.6 to 1.9 show the pin configurations (top view).

PIN CONFIGURATION (top view)

102 101

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

P1_0/D8

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P11_7

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

P12_5

P12_6

P12_7

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P13_0

P13_1

P13_2

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

<VCC2> ⁽²⁾

P11_6

P11_5

P11_4

P11_3

P11_2

P11_1

P11_0

P13_3

P5_4/HLDA

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P13_4

P13_5

P13_6

P13_7

M16C/62P Group (M16C/62P)

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

<VCC1> ⁽²⁾

VSS

P10_0/AN0

1

2

3

4

5

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/62PT on VCC1 = VCC2.

Package: 128P6Q-A

Figure 1.6 Pin Configuration (Top View)

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

PIN CONFIGURATION (top view)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

P4_4/CS0

P4_5/CS1

P4_6/CS2

P4_7/CS3

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

<VCC2> ⁽²⁾

M16C/62P Group

(M16C/62P, M16C/62PT)

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

AVCC

P9_7/ADTRG/SIN4

<VCC1> ⁽²⁾

P6_7/TXD1/SDA1

1

2

3

4

5

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NOTES:

Package: 100P6S-A

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/62PT on VCC1 = VCC2.

Figure 1.7 Pin Configuration (Top View)

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Rev. 2.30 Sep 01, 2004

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

PIN CONFIGURATION (top view)

56 55 54 53 52 51

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57

P1_2/D10

P1_1/D9

P1_0/D8

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

76

77

78

79

P4_2/A18

P4_3/A19

P4_4/CS0

P4_5/CS1

P4_6/CS2

<VCC2> ⁽²⁾

P0_7/AN0_7/D7

P0_6/AN0_6/D6

P0_5/AN0_5/D5

P0_4/AN0_4/D4

P0_3/AN0_3/D3

P0_2/AN0_2/D2

P0_1/AN0_1/D1

P0_0/AN0_0/D0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

80

81

P4_7/CS3

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

P5_0/WRL/WR

P5_1/WRH/BHE

P5_2/RD

P5_3/BCLK

P5_4/HLDA

M16C/62P Group

(M16C/62P, M16C/62PT)

P5_5/HOLD

P5_6/ALE

P5_7/RDY/CLKOUT

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

P6_6/RXD1/SCL1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P10_0/AN0

VREF

P6_7/TXD1/SDA1

P7_0/TXD2/SDA2/TA0OUT

AVCC

P9_7/ADTRG/SIN4

P9_6/ANEX1/SOUT4

P9_5/ANEX0/CLK4

(1)

<VCC1> ⁽²⁾

(1)

P7_1/RXD2/SCL2/TA0IN/TB5IN

P7_2/CLK2/TA1OUT/V

26

1

2

3

4

5

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Package: 100P6Q-A

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

2. Use the M16C/62PT on VCC1 = VCC2.

Figure 1.8 Pin Configuration (Top View)

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1. Overview

M16C/62P Group (M16C/62P, M16C/62PT)

PIN CONFIGURATION (top view)

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

40

61

62

63

P4_3

P0_6/AN0_6

P0_5/AN0_5

P0_4/AN0_4

P0_3/AN0_3

P0_2/AN0_2

39

38

P5_0

P5_1

64

65

66

67

68

37

36

P5_2

P5_3

35

34

33

32

P0_1/AN0_1

P0_0/AN0_0

P10_7/AN7/KI3

P10_6/AN6/KI2

P10_5/AN5/KI1

P10_4/AN4/KI0

P10_3/AN3

P10_2/AN2

P10_1/AN1

AVSS

P5_4

P5_5

P5_6

69

70

71

72

73

74

P5_7/CLKOUT

P6_0/CTS0/RTS0

P6_1/CLK0

P6_2/RXD0/SCL0

P6_3/TXD0/SDA0

31

30

29

M16C/62P Group

(M16C/62P, M16C/62PT)

28

27

26

P6_4/CTS1/RTS1/CTS0/CLKS1

P6_5/CLK1

75

76

25

24

23

P10_0/AN0

VREF

P6_6/RXD1/SCL1

77

78

79

80

P6_7/TXD1/SDA1

(1)

AVCC

P7_0/TXD2/SDA2/TA0OUT

P7_1/RXD2/SCL2/TA0IN/TB5IN

P7_6/TA3OUT

(1)

22

21

P9_7/ADTRG/SIN4

P9_6/ANEX1/SOUT4

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20

Package: 80P6S-A

NOTES:

1. P7_0 and P7_1 are N channel open-drain output pins.

Figure 1.9 Pin Configuration (Top View)

page 16

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

1.6 Pin Description

Table 1.10 Pin Description (100-pin and 128-pin Version) (1)

Power

Signal Name Pin Name I/O Type

Description

Supply⁽³⁾

Power supply input VCC1, VCC2

VSS

I

-

Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC

apply condition is that VCC1 ≥ VCC2.⁽²⁾

Analog power

supply input

Reset input

CNVSS

AVCC

VCC1

Applies the power supply for the A/D converter. Connect the AVCC pin to

VCC1. Connect the AVSS pin to VSS.

AVSS

____________

RESET

CNVSS

I

VCC1

The microcomputer is in a reset state when applying "L" to the this pin.

Switches processor mode. Connect this pin to VSS to when after a reset to start

up in single-chip mode. Connect this pin to VCC1 to start up in microprocessor

mode.

External data bus

width select input

BYTE

I

VCC1

Switches the data bus in external memory space. The data bus is 16 bits long

when the this pin is held "L" and 8 bits long when the this pin is held "H". Set it

to either one. Connect this pin to VSS when an single-chip mode.

Inputs and outputs data (D0 to D7) when these pins are set as the separate bus.

Inputs and outputs data (D8 to D15) when external 16-bit data bus is set as the

separate bus.

Bus control pins⁽⁴⁾D0 to D7

D8 to D15

I/O

VCC2

A0 to A19

A0/D0 to

A7/D7

O

VCC2

Output address bits (A0 to A19).

I/O

Input and output data (D0 to D7) and output address bits (A0 to A7) by time-

sharing when external 8-bit data bus are set as the multiplexed bus.

Input and output data (D0 to D7) and output address bits (A8 to A15) by time-

sharing when external 16-bit data bus are set as the multiplexed bus.

Output ^_C^___S^__0^__to ^_C^___S^__3^__signals. ^_C^___S^__0^__to ^_C^___S^__3^__are chip-select signals to specify an

external space.

______

A1/D0 to

A8/D7

I/O

O

VCC2

______

CS0 to CS3

________ ______

_________

_______

________ _________

______ ________

_____

________

WRL/WR

O

WRH or BHE and WR

Output WRL, WRH, (WR, BHE), RD signals. WRL and

can be switched by program.

_________

WRH/^_B^__H^___E^__

_____

________

_____

RD

• WRL, ^_W^___R^___H^__and RD are selected

The W^____R^___L^_signal becomes "L" by writing data to an even address in an external

memory space.

The ^_W^___R^___H^__signal becomes "L" by writing data to an odd address in an external

memory space.

_____

The RD pin signal becomes "L" by reading data in an external memory space.

______

_____

• WR, ^_B^__H^___E^__and RD are selected

The W^____R^__signal becomes "L" by writing data in an external memory space.

_____

The RD signal becomes "L" by reading data in an external memory space.

The ^_B^__H^___E^__signal becomes "L" by accessing an odd address.

______

_____

Select WR, ^_B^__H^___E^__and RD for an external 8-bit data bus.

ALE

O

I

VCC2

ALE is a signal to latch the address.

__________

HOLD

While the HOLD pin is held "L", the microcomputer is placed in a hold state.

__________

_________

HLDA

O

I

In a hold state, HLDA outputs a "L" signal.

________

RDY

While applying a "L" signal to the ^_R^__D^___Y^__pin, the microcomputer is placed in a wait

state.

I : Input

O : Output

I/O : Input and output

Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be inter-

faced using the different voltage as VCC1.

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. In M16C/62PT, apply 2.7 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 ≥ VCC2.

3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.

4. Bus control pins in M16C/62Tcannot be used.

page 17

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

Table 1.11 Pin Description (100-pin and 128-pin Version) (2)

Power

Signal Name Pin Name I/O Type

Description

Supply ⁽¹⁾

Main clock input

Main clock output

XIN

I

VCC1

I/O pins for the main clock generation circuit. Connect a ceramic resonator or

crystal oscillator between XIN and XOUT ⁽³⁾. To use the external clock, input the

clock from XIN and leave XOUT open.

XOUT

O

Sub clock input

Sub clock output

XCIN

I

VCC1

I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between

XCIN and XCOUT ⁽³⁾. To use the external clock, input the clock from XCIN and

leave XCOUT open.

XCOUT

O

BCLK output ⁽²⁾

BCLK

O

I

VCC2

VCC1

VCC2

VCC1

Outputs the BCLK signal.

Clock output

CLKOUT

The clock of the same cycle as fC, f8, or f32 is outputted.

Input pins for the ^_I^_N^__T^__interrupt

______

________

INT interrupt input INT0 to ^_I^_N^__T^__2^__

________

INT3 to ^_I^_N^__T^__5^__

I

_______

NMI interrupt input NMI

I

Input pin for the ^_N^__M^___I^_interrupt. Pin states can be read by the P8_5 bit in the P8

register.

_____

Key input interrupt KI0 to ^_K^__I^_3^__

I

I/O

I

VCC1

Input pins for the key input interrupt

input

Timer A

TA0OUT to

TA4OUT

TA0IN to

TA4IN

These are timer A0 to timer A4 I/O pins. (except the output of TAOUT for the N-

channel open drain output.)

These are timer A0 to timer A4 input pins.

ZP

I

VCC1

Input pin for the Z-phase.

Timer B

TB0IN to

TB5IN

These are timer B0 to timer B5 input pins.

__

Three-phase motor U, U, V, V,

O

VCC1

These are Three-phase motor control output pins.

__

control output

Serial I/O

W, W

__________

________

CTS0 to CTS2

I

O

I/O

I

VCC1

These are send control input pins.

________

RTS0 to RTS2

CLK0 to CLK4

RXD0 to RXD2

SIN3, SIN4

TXD0 to

These are receive control output pins.

These are transfer clock I/O pins.

These are serial data input pins.

I

These are serial data input pins.

O

These are serial data output pins. (except TXD2 for the N-channel open drain

output.)

TXD2

SOUT3, SOUT4

CLKS1

O

VCC1

These are serial data output pins.

This is output pin for transfer clock output from multiple pins function.

These are serial data I/O pins. (except SDA2 for the N-channel open drain

output.)

I²C mode

SDA0 to SDA2

I/O

SCL0 to SCL2

I/O

VCC1

These are transfer clock I/O pins. (except SCL2 for the N-channel open drain

output.)

I : Input

O : Output

I/O : Input and output

NOTES:

1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.

2. This pin function in M16C/62PT cannot be used.

3. Ask the oscillator maker the oscillation characteristic.

page 18

Rev. 2.30 Sep 01, 2004

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

Table 1.12 Pin Description (100-pin and 128-pin Version) (3)

Power

Signal Name

Pin Name I/O Type

Description

Supply ⁽¹⁾

Reference voltage VREF

input

I

VCC1

Applies the reference voltage for the A/D converter and D/A converter.

A/D converter

AN0 to AN7,

I

VCC1

Analog input pins for the A/D converter

AN0_0 to AN0_7,

AN2_0 to AN2_7

___________

ADTRG

ANEX0

I

VCC1

This is an A/D trigger input pin.

I/O

This is the extended analog input pin for the A/D converter, and is the

output in external op-amp connection mode.

ANEX1

I

VCC1

VCC2

This is the extended analog input pin for the A/D converter.

This is the Input pin for the D/A converter.

D/A converter

I/O port

DA0, DA1

O

P0_0 to P0_7,

P1_0 to P1_7,

P2_0 to P2_7,

P3_0 to P3_7,

P4_0 to P4_7,

P5_0 to P5_7,

P12_0 to

I/O

8-bit I/O ports in CMOS, having a direction register to select an input or

output.

Each pin is set as an input port or output port. An input port can be set for a

pull-up or for no pull-up in 4-bit unit by program.

P12_7 ⁽²⁾

P13_0 to

P13_7 ⁽²⁾

,

P6_0 to P6_7,

P7_0 to P7_7,

P9_0 to P9_7,

P10_0 to P10_7,

P11_0 to

I/O

VCC1

8-bit I/O ports having equivalent functions to P0.

(except P7_0 and P7_1 for the N-channel open drain output.)

P11_7 ⁽²⁾

P8_0 to P8_4,

P8_6, P8_7,

P14_0, P14_1⁽²⁾

P8_5

I/O

I

VCC1

I/O ports having equivalent functions to P0.

Input port

Input pin for the ^_N^__M^___I^_interrupt.

Pin states can be read by the P8_5 bit in the P8 register.

I : Input

O : Output

I/O : Input and output

NOTES:

1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.

2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used.

page 19

Rev. 2.30 Sep 01, 2004

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

Table 1.13 Pin Description (80-pin Version) (1)

Power

Supply

Signal Name

Pin Name I/O Type

Description

Power supply input VCC1,

VSS

I

-

Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. ⁽²⁾

Analog power

supply input

Reset input

CNVSS

AVCC,

VCC1

Applies the power supply for the A/D converter. Connect the AVCC pin to

VCC1. Connect the AVSS pin to VSS.

AVSS

____________

RESET

CNVSS

(BYTE)

I

VCC1

The microcomputer is in a reset state when applying "L" to the this pin.

Switches processor mode. Connect this pin to VSS to when after a reset to

start up in single-chip mode. Connect this pin to VCC1 to start up in micropro-

cessor mode. As for the BYTE pin of the 80-pin versions, pull-up processing

is performed within the microcomputer.

Main clock input

XIN

I

VCC1

I/O pins for the main clock generation circuit. Connect a ceramic resonator or

crystal oscillator between XIN and XOUT ⁽³⁾. To use the external clock, input

the clock from XIN and leave XOUT open.

Main clock output XOUT

O

Sub clock input

Sub clock output

XCIN

I

VCC1

I/O pins for a sub clock oscillation circuit. Connect a crystal oscillator between

XCIN and XCOUT ⁽³⁾. To use the external clock, input the clock from XCIN

and leave XCOUT open.

XCOUT

O

Clock output

CLKOUT

O

I

VCC2

VCC1

The clock of the same cycle as fC, f8, or f32 is outputted.

Input pins for the ^_I^_N^__T^__interrupt

______

________

INT interrupt input INT0 to ^_I^_N^__T^__2^__

_______

NMI interrupt input NMI

I

Input pin for the ^_N^__M^___I^_interrupt.

Key input interrupt KI0 to ^_K^__I^_3^__

I

Input pins for the key input interrupt

______

input

Timer A

TA0OUT,

TA3OUT,

TA4OUT

TA0IN,

TA3IN,

TA4IN

I/O

I

VCC1

These are timer A0, timer A3 and Timer A4 I/O pins. (except the output of

TAOUT for the N-channel open drain output.)

These are timer A0, timer A3 and Timer A4 input pins.

ZP

I

VCC1

Input pin for the Z-phase.

Timer B

TB0IN,

These are timer B0, timer B2 to timer B5 input pins.

TB2IN to TB5IN

_________ _________

Serial I/O

CTS0, CTS2

I

VCC1

These are send control input pins.

These are receive control output pins.

These are transfer clock I/O pins.

_________ _________

RTS0, RTS2

CLK0, CLK1,

CLK3, CLK4

RXD0 to RXD2

SIN4

O

I/O

I

VCC1

These are serial data input pins.

TXD0 to TXD4

O

These are serial data output pins. (except TXD2 for the N-channel open drain

output.)

SOUT3, SOUT4

CLKS1

O

VCC1

These are serial data output pins.

This is output pin for transfer clock output from multiple pins function.

I²C mode

SDA0 to SDA2

I/O

These are serial data I/O pins. (except SDA2 for the N-channel open drain

output.)

SCL0 to SCL2

I/O

VCC1

These are transfer clock I/O pins. (except SCL2 for the N-channel open drain

output.)

I : Input

O : Output

I/O : Input and output

NOTES:

1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.

2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.

3. Ask the oscillator maker the oscillation characteristic.

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M16C/62P Group (M16C/62P, M16C/62PT)

1. Overview

Table 1.14 Pin Description (80-pin Version) (2)

Power

Supply

Signal Name

Pin Name I/O Type

Description

Reference voltage VREF

input

I

VCC1

Applies the reference voltage for the A/D converter and D/A converter.

A/D converter

AN0 to AN7,

I

VCC1

Analog input pins for the A/D converter

AN0_0 to AN0_7,

AN2_0 to AN2_7

___________

ADTRG

ANEX0

I

VCC1

This is an A/D trigger input pin.

I/O

This is the extended analog input pin for the A/D converter, and is the output

in external op-amp connection mode.

ANEX1

I

VCC1

This is the extended analog input pin for the A/D converter.

This is the Input pin for the D/A converter

D/A converter

I/O port

DA0, DA1

O

P0_0 to P0_7,

P2_0 to P2_7,

P3_0 to P3_7,

P5_0 to P5_7,

P6_0 to P6_7,

P10_0 to P10_7

P8_0 to P8_4,

P8_6, P8_7,

P9_0,

I/O

8-bit I/O ports in CMOS, having a direction register to select an input or

output.

Each pin is set as an input port or output port. An input port can be set for a

pull-up or for no pull-up in 4-bit unit by program.

I/O

VCC1

I/O ports having equivalent functions to P0.

P9_2 to P9_7

P4_0 to P4_3,

P7_0, P7_1,

P7_6, P7_7

P8_5

I/O

I

VCC1

I/O ports having equivalent functions to P0.

(except P7_0 and P7_1 for the N-channel open drain output.)

Input port

I : Input

NOTES:

Input pin for the ^_N^__M^___I^_interrupt.

Pin states can be read by the P8_5 bit in the P8 register.

O : Output

I/O : Input and output

1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

Set the direction bits in these ports to “1” (input mode), and set the output data to “0” (“L”) using the program.

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M16C/62P Group (M16C/62P, M16C/62PT)

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB

comprise a register bank. There are two register banks.

b31

b15

b8b7

b0

R2

R3

R0H

R1H

R0L

R1L

(1)

Data Registers

R2

R3

A0

A1

FB

(1)

Address Registers

(1)

Frame Base Registers

b19

b15

b0

INTBH

INTBL

Interrupt Table Register

Program Counter

b19

b0

PC

b15

USP

User Stack Pointer

Interrupt Stack Pointer

Static Base Register

ISP

SB

b15

b0

FLG

Flag Register

b15

b8 b7

IPL

U

I

O B

S

Z

D C

Carry Flag

Debug Flag

Zero Flag

Sign Flag

Register Bank Select Flag

Overflow Flag

Interrupt Enable Flag

Stack Pointer Select Flag

Reserved Area

Processor Interrupt Priority Level

Reserved Area

NOTES:

1. These registers comprise a register bank. There are two register banks.

Figure 2.1 Central Processing Unit Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-

ter relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

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M16C/62P Group (M16C/62P, M16C/62PT)

2. Central Processing Unit (CPU)

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.

2.8.3 Zero Flag (Z Flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.

2.8.4 Sign Flag (S Flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.

2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

2.8.6 Overflow Flag (O Flag)

This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag

is cleared to “0” when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.

The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for

software interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level

0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write “0”. When read, its content is indeterminate.

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M16C/62P Group (M16C/62P, M16C/62PT)

3. Memory

Figure 3.1 is a memory map of the M16C/62P group. The address space extends the 1M bytes from

address 00000h to FFFFFh.

The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a

64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh.

As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is

mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.

The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the

start address of each interrupt routine here.

The internal RAM is allocated in an upper address direction beginning with address 00400h. For example,

a 10-Kbyte internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data,

the internal RAM also stores the stack used when calling subroutines and when interrupts are generated.

The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are

located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot

be used by users.

The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by

the JMPS or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.

In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be

used by users. Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expan-

sion and microprocessor modes cannot be used.

00000h

SFR

00400h

Internal RAM

XXXXXh

(1)

Reserved area

FFE00h

0F000h

Internal ROM

(data area) ⁽³⁾

0FFFFh

Special page

vector table

10000h

Internal ROM ⁽³⁾

Internal RAM

External area

Size

Address XXXXXh

013FFh

Size

Address YYYYYh

27000h

28000h

4K bytes

5K bytes

48K bytes

64K bytes

F4000h

F0000h

Reserved area

External area

FFFDCh

Undefined instruction

Overflow

BRK instruction

Address match

Single step

017FFh

96K bytes

128K bytes

192K bytes

E8000h

E0000h

D0000h

10K bytes

12K bytes

16K bytes

02BFFh

033FFh

043FFh

80000h

(2)

Reserved area

20K bytes

053FFh

256K bytes

320K bytes

384K bytes

512K bytes

C0000h

B0000h

YYYYYh

Watchdog timer

24K bytes

31K bytes

063FFh

07FFFh

DBC

NMI

Reset

Internal ROM

(program area) ⁽⁵⁾

A0000h

80000h

FFFFFh

NOTES:

1. During memory expansion and microprocessor modes, can not be used.

2. In memory expansion mode, can not be used.

3. As for the flash memory version, 4-Kbyte space (block A) exists.

4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”

and the PM13 bit in the PM1 register is “1”.

5. When using the masked ROM version, write nothing to internal ROM area.

Figure 3.1 Memory Map

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

SFR(Special Function Register) is the control register of peripheral functions. Table 4.1 to 4.6 list the SFR

information.

(1)

Table 4.1 SFR information (1)

Address

Register

Symbol

PM0

After Reset

0000h

0001h

0002h

0003h

0004h

Processor Mode Register 0 ⁽²⁾

00000000b(CNVSS pin is “L”)

00000011b(CNVSS pin is “H”)

Processor Mode Register 1

PM1

CM0

CM1

CSR

AIER

PRCR

00001000b

01001000b

00100000b

00000001b

XXXXXX00b

XX000000b

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

000Ch

000Dh

000Eh

000Fh

0010h

0011h

0012h

0013h

0014h

0015h

0016h

0017h

0018h

0019h

System Clock Control Register 0

System Clock Control Register 1

Chip Select Control Register ⁽⁶⁾

Address Match Interrupt Enable Register

Protect Register

Data Bank Register ⁽⁶⁾

DBR

CM2

00h

0X000000b

Oscillation Stop Detection Register ⁽³⁾

Watchdog Timer Start Register

WDTS

XXh

00XXXXXXb ⁽⁴⁾

00h

X0h

Watchdog Timer Control Register

Address Match Interrupt Register 0

WDC

RMAD0

Address Match Interrupt Register 1

RMAD1

00h

X0h

Voltage Detection Register 1 ^{(5, 6)}

VCR1

VCR2

CSE

00001000b

00h

001Ah Voltage Detection Register 2 ^{(5, 6)}

001Bh

001Ch

001Dh

001Eh

Chip Select Expansion Control Register ⁽⁶⁾

PLL Control Register 0

PLC0

0001X010b

Processor Mode Register 2

PM2

D4INT

SAR0

XXX00000b

00h

XXh

Voltage Down Detection Interrupt Register ⁽⁶⁾

001Fh

0020h

DMA0 Source Pointer

DMA0 Destination Pointer

DMA0 Transfer Counter

DMA0 Control Register

0021h

0022h

0023h

0024h

0025h

0026h

0027h

0028h

0029h

002Ah

002Bh

002Ch

002Dh

002Eh

002Fh

0030h

0031h

0032h

0033h

0034h

0035h

0036h

0037h

0038h

0039h

003Ah

003Bh

003Ch

003Dh

003Eh

003Fh

DAR0

XXh

TCR0

XXh

DM0CON

00000X00b

DMA1 Source Pointer

SAR1

DAR1

XXh

DMA1 Destination Pointer

XXh

DMA1 Transfer Counter

DMA1 Control Register

TCR1

XXh

DM1CON

00000X00b

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.

3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.

4. The WDC5 bit is “0” (cold start) immediately after power-on. It can only be set to “1” in a program. It is set to “0” when the input voltage

at the V^CC1pin drops to Vdet2 or less while the VC25 bit in the VCR2 register is set to “1” (RAM retention limit detection circuit enable

5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.

6. This register in M16C/62PT cannot be used.

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

(1)

Table 4.2 SFR information (2)

Address

Register

Symbol

After Reset

0040h

0041h

0042h

0043h

0044h

INT3 Interrupt Control Register

Timer B5 Interrupt Control Register

INT3IC

TB5IC

XX00X000b

XXXXX000b

0045h

0046h

0047h

0048h

0049h

004Ah

004Bh

004Ch

004Dh

004Eh

004Fh

0050h

0051h

0052h

0053h

0054h

0055h

0056h

0057h

0058h

0059h

005Ah

005Bh

005Ch

005Dh

005Eh

005Fh

Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register

TB4IC, U1BCNIC

Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register

TB3IC, U0BCNIC

SI/O4 Interrupt Control Register (S4IC), INT5 Interrupt Control Register S4IC

,

INT5IC

INT4IC

XX00X000b

SI/O3 Interrupt Control Register, INT4 Interrupt Control Register

UART2 Bus Collision Detection Interrupt Control Register

DMA0 Interrupt Control Register

DMA1 Interrupt Control Register

Key Input Interrupt Control Register

S3IC

,

XX00X000b

XXXXX000b

XX00X000b

BCNIC

DM0IC

DM1IC

KUPIC

ADIC

S2TIC

S2RIC

S0TIC

S0RIC

S1TIC

S1RIC

TA0IC

TA1IC

TA2IC

TA3IC

TA4IC

TB0IC

TB1IC

TB2IC

INT0IC

INT1IC

INT2IC

A/D Conversion Interrupt Control Register

UART2 Transmit Interrupt Control Register

UART2 Receive Interrupt Control Register

UART0 Transmit Interrupt Control Register

UART0 Receive Interrupt Control Register

UART1 Transmit Interrupt Control Register

UART1 Receive Interrupt Control Register

Timer A0 Interrupt Control Register

Timer A1 Interrupt Control Register

Timer A2 Interrupt Control Register

Timer A3 Interrupt Control Register

Timer A4 Interrupt Control Register

Timer B0 Interrupt Control Register

Timer B1 Interrupt Control Register

Timer B2 Interrupt Control Register

INT0 Interrupt Control Register

INT1 Interrupt Control Register

INT2 Interrupt Control Register

0060h

0061h

0062h

0063h

0064h

0065h

0066h

0067h

0068h

0069h

006Ah

006Bh

006Ch

006Dh

006Eh

006Fh

0070h

0071h

0072h

0073h

0074h

0075h

0076h

0077h

0078h

0079h

007Ah

007Bh

007Ch

007Dh

007Eh

007Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

(1)

Table 4.3 SFR information (3)

Address

Register

Symbol

After Reset

0080h

0081h

0082h

0083h

0084h

0085h

0086h

0087h

to

01AFh

01B0h

01B1h

01B2h

01B3h

Flash Identification Register ⁽²⁾

FIDR

FMR1

XXXXXX00b

0X00XX0Xb

01B4h

Flash Memory Control Register 1 ⁽²⁾

01B5h

01B6h

Flash Memory Control Register 0 ⁽²⁾

Address Match Interrupt Register 2

FMR0

RMAD2

00000001b

00h

X0h

XXXXXX00b

00h

X0h

01B7h

01B8h

01B9h

01BAh

01BBh

Address Match Interrupt Enable Register 2

Address Match Interrupt Register 3

AIER2

RMAD3

01BCh

01BDh

01BEh

01BFh

00C0h

to

02AFh

0250h

0251h

0252h

0253h

0254h

0255h

0256h

0257h

0258h

0259h

025Ah

025Bh

025Ch

025Dh

025Eh

Peripheral Clock Select Register

PCLKR

00000011b

025Fh

0260h

to

032Fh

0330h

0331h

0332h

0333h

0334h

0335h

0336h

0337h

0338h

0339h

033Ah

033Bh

033Ch

033Dh

033Eh

033Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

(1)

Table 4.4 SFR information (4)

Address

Register

Symbol

TBSR

After Reset

0340h

0341h

0342h

0343h

0344h

0345h

0346h

0347h

0348h

0349h

034Ah

034Bh

034Ch

034Dh

034Eh

034Fh

0350h

0351h

0352h

0353h

0354h

0355h

0356h

0357h

0358h

0359h

035Ah

035Bh

035Ch

035Dh

035Eh

035Fh

0360h

0361h

0362h

Timer B3, 4, 5 Count Start Flag

Timer A1-1 Register

000XXXXXb

TA11

TA21

TA41

XXh

00h

XXh

Timer A2-1 Register

Timer A4-1 Register

Three-Phase PWM Control Register 0

Three-Phase PWM Control Register 1

Three-Phase Output Buffer Register 0

Three-Phase Output Buffer Register 1

Dead Time Timer

INVC0

INVC1

IDB0

IDB1

DTT

Timer B2 Interrupt Occurrence Frequency Set Counter

ICTB2

Timer B3 Register

Timer B4 Register

Timer B5 Register

TB3

TB4

TB5

XXh

Timer B3 Mode Register

Timer B4 Mode Register

Timer B5 Mode Register

Interrupt Cause Select Register 2

Interrupt Cause Select Register

TB3MR

00XX0000b

TB4MR

TB5MR

IFSR2A

IFSR

00XX0000b

00XXXXXXb

00h

SI/O3 Transmit/Receive Register

S3TRR

XXh

SI/O3 Control Register

S3C

S3BRG

S4TRR

01000000b

XXh

0363h SI/O3 Bit Rate Generator

0364h SI/O4 Transmit/Receive Register

0365h

SI/O4 Control Register

S4C

S4BRG

01000000b

XXh

0366h

0367h

SI/O4 Bit Rate Generator

0368h

0369h

036Ah

036Bh

036Ch

UART0 Special Mode Register 4

UART0 Special Mode Register 3

UART0 Special Mode Register 2

U0SMR4

U0SMR3

U0SMR2

00h

000X0X0Xb

X0000000b

036Dh

036Eh

036Fh

UART0 Special Mode Register

UART1 Special Mode Register 4

UART1 Special Mode Register 3

UART1 Special Mode Register 2

U0SMR

X0000000b

00h

000X0X0Xb

X0000000b

0370h

U1SMR4

U1SMR3

U1SMR2

0371h

0372h

0373h

UART1 Special Mode Register

UART2 Special Mode Register 4

U1SMR

U2SMR4

U2SMR3

U2SMR2

U2SMR

X0000000b

00h

000X0X0Xb

X0000000b

0374h

0375h UART2 Special Mode Register 3

0376h

UART2 Special Mode Register 2

UART2 Special Mode Register

0377h

0378h

UART2 Transmit/Receive Mode Register

U2MR

00h

0379h

037Ah

UART2 Bit Rate Generator

U2BRG

U2TB

XXh

00001000b

UART2 Transmit Buffer Register

037Bh

UART2 Transmit/Receive Control Register 0

UART2 Transmit/Receive Control Register 1

U2C0

U2C1

037Ch

00000010b

037Dh

037Eh

UART2 Receive Buffer Register

U2RB

XXh

037Fh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

X : Nothing is mapped to this bit

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

(1)

Table 4.5 SFR information (5)

Address

Register

Symbol

After Reset

0380h

Count Start Flag

Clock Prescaler Reset Fag

One-Shot Start Flag

Trigger Select Register

TABSR

CPSRF

ONSF

TRGSR

UDF

00h

0XXXXXXXb

00h

0381h

0382h

0383h

00h

Up-Down Flag

00h ⁽²⁾

0384h

0385h

0386h

Timer A0 Register

TA0

TA1

TA2

TA3

TA4

TB0

XXh

00h

0387h

0388h

Timer A1 Register

0389h

038Ah

Timer A2 Register

038Bh

038Ch

Timer A3 Register

038Dh

038Eh

Timer A4 Register

038Fh

0390h

Timer B0 Register

0391h

0392h

Timer B1 Register

TB1

TB2

0393h

0394h

Timer B2 Register

0395h

0396h

Timer A0 Mode Register

Timer A1 Mode Register

Timer A2 Mode Register

Timer A3 Mode Register

Timer A4 Mode Register

Timer B0 Mode Register

Timer B1 Mode Register

Timer B2 Mode Register

TA0MR

TA1MR

TA2MR

TA3MR

TA4MR

TB0MR

TB1MR

TB2MR

TB2SC

0397h

0398h

0399h

039Ah

00h

039Bh

00XX0000b

039Ch

039Dh

039Eh

Timer B2 Special Mode Register

XXXXXX00b

039Fh

03A0h

UART0 Transmit/Receive Mode Register

UART0 Bit Rate Generator

UART0 Transmit Buffer Register

U0MR

U0BRG

U0TB

00h

XXh

00001000b

00XX0010b

XXh

00h

XXh

00001000b

00XX0010b

XXh

X0000000b

03A1h

03A2h

03A3h

03A4h

UART0 Transmit/Receive Control Register 0

UART0 Transmit/Receive Control Register 1

UART0 Receive Buffer Register

U0C0

U0C1

U0RB

03A5h

03A6h

03A7h

03A8h

UART1 Transmit/Receive Mode Register

UART1 Bit Rate Generator

UART1 Transmit Buffer Register

U1MR

U1BRG

U1TB

03A9h

03AAh

03ABh

03ACh UART1 Transmit/Receive Control Register 0

03ADh

U1C0

U1C1

U1RB

UART1 Transmit/Receive Control Register 1

03AEh

UART1 Receive Buffer Register

03AFh

03B0h

UART Transmit/Receive Control Register 2

UCON

03B1h

03B2h

03B3h

03B4h

03B5h

03B6h

03B7h

03B8h

DMA0 Request Cause Select Register

DM0SL

DM1SL

00h

03B9h

03BAh DMA1 Request Cause Select Register

03BBh

03BCh

CRC Data Register

CRCD

CRCIN

XXh

03BDh

03BEh

CRC Input Register

03BFh

NOTES :

1.The blank areas are reserved and cannot be accessed by users.

2. Bits 7 to 5 in the Up-down flag are “0” by reset. However, The values in these bits when read are indeterminate.

X : Nothing is mapped to this bit

page 29

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M16C/62P Group (M16C/62P, M16C/62PT)

4. Special Function Register (SFR)

(1)

Table 4.6 SFR information (6)

Address

Register

Symbol

After Reset

03C0h

A/D Register 0

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

XXh

03C1h

03C2h

A/D Register 1

03C3h

03C4h

A/D Register 2

03C5h

03C6h

A/D Register 3

03C7h

03C8h

A/D Register 4

03C9h

03CAh

A/D Register 5

03CBh

03CCh

A/D Register 6

03CDh

03CEh

A/D Register 7

03CFh

03D0h

03D1h

03D2h

03D3h

03D4h

A/D Control Register 2

ADCON2

00h

03D5h

03D6h

03D7h

03D8h

03D9h

03DAh

03DBh

03DCh

03DDh

03DEh

03DFh

03E0h

03E1h

03E2h

03E3h

03E4h

03E5h

03E6h

03E7h

03E8h

03E9h

03EAh

03EBh

03ECh

03EDh

03EEh

03EFh

03F0h

03F1h

03F2h

03F3h

03F4h

03F5h

03F6h

03F7h

03F8h

03F9h

03FAh

03FBh

03FCh

03FDh

A/D Control Register 0

A/D Control Register 1

D/A Register 0

ADCON0

ADCON1

DA0

00000XXXb

00h

D/A Register 1

DA1

00h

D/A Control Register

DACON

(3)

Port P14 Control Register

Pull-Up Control Register 3

Port P0 Register

PC14

PUR3

P0

XX00XXXXb

00h

XXh

00h

XXh

00h

XXh

00h

XXh

00h

Port P1 Register

P1

Port P0 Direction Register

Port P1 Direction Register

Port P2 Register

Port P3 Register

Port P2 Direction Register

Port P3 Direction Register

Port P4 Register

Port P5 Register

Port P4 Direction Register

Port P5 Direction Register

Port P6 Register

PD0

PD1

P2

P3

PD2

PD3

P4

P5

PD4

PD5

P6

Port P7 Register

P7

Port P6 Direction Register

Port P7 Direction Register

Port P8 Register

PD6

PD7

P8

00h

XXh

00X00000b

00h

XXh

00h

Port P9 Register

P9

Port P8 Direction Register

Port P9 Direction Register

Port P10 Register

PD8

PD9

P10

P11

PD10

PD11

P12

P13

PD12

PD13

PUR0

PUR1

(3)

Port P11 Register

Port P10 Direction Register

Port P11 Direction Register

Port P12 Register

(3)

00h

XXh

00h

(3)

Port P13 Register

Port P12 Direction Register

Port P13 Direction Register

Pull-Up Control Register 0

Pull-Up Control Register 1

00000000b

(2)

00000010b

00h

Pull-Up Control Register 2

Port Control Register

PUR2

PCR

03FEh

03FFh

NOTES :

1. The blank areas are reserved and cannot be accessed by users.

2. At hardware reset 1 or hardware reset 2, the register is as follows:

• “00000000b” where “L” is inputted to the CNVSS pin

• “00000010b” where “H” is inputted to the CNVSS pin

At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:

• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode)

• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or

“11b” (microprocessor mode)

3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version).

X : Nothing is mapped to this bit

page 30

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

5. Electrical Characteristics

5.1 Electrical Characteristics (M16C/62P)

Table 5.1 Absolute Maximum Ratings

Symbol

Parameter

Condition

Rated Value

-0.3 to 6.5

Unit

V

VCC1, VCC2

Supply Voltage

V

CC1=AVCC

VCC2

-0.3 to VCC1+0.1

-0.3 to 6.5

V

CC2

AVCC

Analog Supply Voltage

V

CC1=AVCC

V

RESET, CNVSS, BYTE,

Input

Voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1,

VREF, XIN

-0.3 to VCC1+0.3 ⁽¹⁾

V

VI

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

-0.3 to V^CC2+0.3 ⁽¹⁾

-0.3 to 6.5

V

P7_0, P7_1

Output

Voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1,

XOUT

-0.3 to VCC1+0.3 ⁽¹⁾

-0.3 to V^CC2+0.3 ⁽¹⁾

V

O

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

V

P7_0, P7_1

-0.3 to 6.5

300

V

Pd

Power Dissipation

-40 °C < T^opr≤ 85 °C

mW

T

opr

Operating Ambient

Temperature

When the Microcomputer is

Operating

-20 to 85 / -40 to 85

°C

Flash Program Erase

0 to 60

stg

Storage Temperature

-65 to 150

NOTES:

1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

page 31

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

Table 5.2 Recommended Operating Conditions (1) ⁽¹⁾

Standard

Unit

Symbol

Parameter

Min.

Typ.

Max.

V

CC1, VCC2 Supply Voltage(VCC1

≥

VCC2

)

2.7

5.0

5.5

V

AVcc

Vss

Analog Supply Voltage

Supply Voltage

V

CC1

0

AVss

Analog Supply Voltage

0

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode)

V

CC2

HIGH Input

Voltage

0.8V^CC2

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(data input during memory expansion and microprocessor modes)

0.5VCC2

V

CC2

V

IH

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1,

XIN, RESET, CNVSS, BYTE

0.8V^CC1

0.8VCC1

V

CC1

V

P7_0 , P7_1

6.5

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode)

LOW Input

Voltage

0

0.2VCC2

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0

(data input during memory expansion and microprocessor modes)

0

V

IL

0.16V^CC2

V

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1,

0

V

0.2VCC1

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

HIGH Peak Output

Current

I

OH (peak)

OH (avg)

-10.0

-5.0

mA

HIGH Average

Output Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

LOW Peak Output P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

Current

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

I

OL (peak)

OL (avg)

10.0

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

LOW Average

Output Current

5.0

mA

MHz

16

V

CC1=3.0 to 5.5V

CC1=2.7 to 3.0V

0

Main Clock Input Oscillation Frequency ⁽⁴⁾

f (XIN)

20 X VCC1-44

f (XCIN)

f (Ring)

Sub-Clock Oscillation Frequency

On-chip Oscillation Frequency

32.768

1

50

2

kHz

MHz

0.5

10

V

CC1=3.0 to 5.5V

CC1=2.7 to 3.0V

24

PLL Clock Oscillation Frequency ⁽⁴⁾

f (PLL)

46.67 X VCC1

-

10

0

116

MHz

f (BCLK)

CPU Operation Clock

24

20

50

V

CC1=5.0V

CC1=3.0V

ms

t

SU(PLL)

PLL Frequency Synthesizer Stabilization Wait Time

NOTES:

1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.

2. The mean output current is the mean value within 100ms.

3. The total IOL (peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max. The total IOL (peak) for

ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH (peak) for ports P0, P1, and P2 must be

-40mA max. The total IOH (peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH (peak) for ports P6, P7, and

P8_0 to P8_4 must be -40mA max. The total IOH (peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be -40mA max.

4. Relationship between main clock oscillation frequency, PLL clock oscillation frequency and supply voltage.

PLL clock oscillation frequency

46.67 x VCC1-116MHz

Main clock input oscillation frequency

20 x VCC1-44MHz

24.0

16.0

10.0

0.0

2.7

3.0

5.5

2.7

3.0

5.5

V

CC1[V] (main clock: no division)

VCC1[V] (PLL clock oscillation)

5. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

(1)

Table 5.3 A/D Conversion Characteristics

Standard

Min. Typ. Max.

10

Symbol

Parameter

Measuring Condition

Unit

Bits

–

Resolution

V

REF =VCC1

AN0 to AN7 input

V

5V

REF

=

AN0_0 to AN0_7 input

AN2_0 to AN2_7 input

ANEX0, ANEX1 input

CC1

±3

±7

LSB

Integral

Non-Linearity

Error

INL

10 bits

External operation amp

connection mode

AN0 to AN7 input

V

REF

=

AN0_0 to AN0_7 input

AN2_0 to AN2_7 input

ANEX0, ANEX1 input

V

CC1

±5

LSB

3.3V

External operation amp

connection mode

±7

±2

LSB

V

REF =VCC1=3.3V

8 bits

AN0 to AN7 input

V

5V

REF

=

AN0_0 to AN0_7 input

AN2_0 to AN2_7 input

ANEX0, ANEX1 input

CC1

±3

±7

LSB

Absolute

Accuracy

–

10 bits

External operation amp

connection mode

AN0 to AN7 input

V

REF

=

AN0_0 to AN0_7 input

AN2_0 to AN2_7 input

ANEX0, ANEX1 input

V

CC1

±5

LSB

3.3V

External operation amp

connection mode

±7

±2

LSB

V

REF =VCC1=3.3V

8 bits

–

DNL

–

Tolerance Level Impedance

Differential Non-Linearity Error

Offset Error

3

kΩ

LSB

kΩ

±1

±3

Gain Error

Ladder Resistance

–

10

40

R

LADDER

VREF =VCC1

10-bit Conversion Time, Sample & Hold

Function Available

2.75

t

CONV

V

REF =VCC1=5V, øAD=12MHz

µs

8-bit Conversion Time, Sample & Hold

Function Available

2.33

0.25

t

V

CONV

SAMP

V

REF =VCC1=5V, øAD=12MHz

µs

Sampling Time

µs

V

REF

IA

Reference Voltage

Analog Input Voltage

2.0

0

V

CC1

V

REF

NOTES:

1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise

specified.

2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.

3. øAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and øAD frequency into 10 MHz

or less.

4. When sample & hold function is disabled, øAD frequency must be 250 kHz or more, in addition to the limitation in Note 3.

When sample & hold function is enabled, øAD frequency must be 1MHz or more, in addition to the limitation in Note 3.

(1)

Table 5.4 D/A Conversion Characteristics

Standard

Min. Typ. Max.

8

Symbol

Parameter

Measuring Condition

Unit

–

Bits

%

Resolution

1.0

3

Absolute Accuracy

t

su

µs

Setup Time

R

O

4

10

20

kΩ

Output Resistance

I

VREF

(NOTE 2)

1.5

mA

Reference Power Supply Input Current

NOTES:

1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = -20 to 85 °C / -40 to 85 °C unless otherwise specified.

2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The

resistor ladder of the A/D converter is not included. Also, when D/A register contents are not “00h,” the IVREF will

flow even if Vref is disconnected by the A/D control register.

page 33

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REJ03B0001-0230Z

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

Table 5.5 Flash Memory Version Electrical Characteristics ⁽¹⁾for 100 cycle products (D3, D5, U3, U5)

Standard

Symbol

-

Parameter

Unit

Min.

100

Typ.

Max.

Program and Erase Endurance ⁽³⁾

Word Program Time (VCC1=5.0V, Topr=25°C)

Lock Bit Program Time

cycle

-

25

200

µs

s

200

-

Block Erase Time

4-Kbyte block

0.3

0.5

0.8

4

(VCC1=5.0V, Topr=25 °C)

8-Kbyte block

32-Kbyte block

64-Kbyte block

4

s

4

s

Erase All Unlocked Blocks Time ⁽²⁾

-

4 X n

s

t

PS

Flash Memory Circuit Stabilization Wait Time

Data Hold Time ⁽⁵⁾

15

µs

-

10

year

(6)

Table 5.6 Flash Memory Version Electrical Characteristics

for 10,000 cycle products (D7, D9,

(7)

U7, U7) (Block A and Block 1

)

Standard

Unit

Symbol

-

Parameter

Min.

10,000 ⁽⁴⁾

Typ.

Max.

Program and Erase Endurance ^{(3, 8, 9)}

cycle

µs

-

Word Program Time (VCC1=5.0V, Topr=25°C)

Lock Bit Program Time

25

µs

-

Block Erase Time

(VCC1=5.0V, Topr=25 °C)

4-Kbyte block

0.3

s

t

PS

Flash Memory Circuit Stabilization Wait Time

Data Hold Time ⁽⁵⁾

15

µs

-

10

year

NOTES :

1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C unless otherwise specified.

2. n denotes the number of block erases.

3. Program and Erase Endurance refers to the number of times a block erase can be performed.

If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.

For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this

counts as one program and erase endurance. Data cannot be written to the same address more than once without

erasing the block. (Rewrite prohibited)

4. Maximum number of E/W cycles for which operation is guaranteed.

5.

Topr = -40 to 85 °C (D3, D7, U3, U7) / -20 to 85 °C (D5, D9, U5, U9).

6. Referenced to VCC1 = 2.7 to 5.5V at Topr = -20 to 85 °C (D9, U9) / -40 to 85 °C (D7, U7) unless otherwise specified.

7. Table 23.6 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 23.5.

8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites,

write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are

used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary.

Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to

track the total number of times erasure is used.

9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase

command at least three times until erase error disappears.

10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7

and U9).

11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.

Table 5.7 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics (at

Topr = 0 to 60^oC)

Flash Program, Erase Voltage

Flash Read Operation Voltage

CC1=2.7 to 5.5 V

V

CC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V

V

page 34

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

(1)

Table 5.8 Low Voltage Detection Circuit Electrical Characteristics

Standard

Typ.

Symbol

Measuring Condition

Parameter

Unit

Min.

3.3

Max.

4.4

V

det4

det3

det4-

Voltage Down Detection Voltage ⁽¹⁾

3.8

2.8

V

Reset Level Detection Voltage ^{(1, 2)}

2.2

3.6

0.3

2.2

V

det3 Electric potential difference of Voltage Down Detection and Reset Level Detection

Low Voltage Reset Retention Voltage

VCC1=0.8 to 5.5V

0.8

4.0

det3s

det3r

Low Voltage Reset Release Voltage ⁽³⁾

2.9

NOTES:

1. Vdet4 > Vdet3

.

2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection voltage, the

operation at f(BCLK) ≤ 10MHz is guaranteed.

3. Vdet3r > Vdet3 is not guaranteed.

Table 5.9 Power Supply Circuit Timing Characteristics

Standard

Typ.

Symbol

Measuring Condition

Parameter

Unit

Min.

Max.

2

ms

t

d(P-R)

Time for Internal Power Supply Stabilization During Powering-On

STOP Release Time

d(R-S)

d(W-S)

d(S-R)

d(E-A)

V

CC1=2.7 to 5.5V

150

µs

Low Power Dissipation Mode Wait Mode Release Time

150

20

µs

6 ⁽¹⁾

V

CC1=Vdet3r to 5.5V

Voltage Down Detection Reset (Hardware Reset 2) Release Wait Time

ms

V

CC1=2.7 to 5.5V

Low Voltage Detection Circuit Operation Start Time

20

µs

NOTES:

1. When VCC1 = 5V.

td(P-R)

Time for Internal Power

Supply Stabilization During

Powering-On

V

CC

t

d(P-R)

CPU clock

Interrupt for

(a) Stop mode release

or

t

d(R-S)

STOP Release Time

(b) Wait mode release

d(W-S)

CPU clock

Low Power Dissipation Mode

Wait Mode Release Time

(a)

(b)

t

d(R-S)

td(W-S)

td(S-R)

Voltage Down Detection

Reset (Hardware Reset 2)

Release Wait Time

Vdet3r

VCC1

td(P-R)

CPU clock

t

d(E-A)

VC26, VC27

Low Voltage Detection Circuit

Operation Start Time

Stop

Operate

td(E-A)

Figure 5.1 Power Supply Circuit Timing Diagram

page 35

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

(1)

Table 5.10 Electrical Characteristics

Standard

Typ.

Symbol

Measuring Condition

Unit

Parameter

Min.

Max.

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

HIGH Output

Voltage

I

OH=-5mA

V

CC1-2.0

V

CC1

CC2

CC1

V

OH

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

V

CC2-2.0

CC1-0.3

I

OH=-5mA ⁽²⁾

OH=-200µA

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

HIGH Output

Voltage

V

OH=-200µA ⁽²⁾

VCC2-0.3

V

CC2

HIGHPOWER

I

OH=-1mA

V

CC1-2.0

V

CC1

HIGH Output Voltage

XOUT

V

LOWPOWER

OH=-0.5mA

V

VOH

With no load applied

2.5

1.6

HIGHPOWER

LOWPOWER

XCOUT

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

LOW Output

Voltage

I

OL=5mA

2.0

V

OL

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

I

OL=5mA ⁽²⁾

LOW Output

Voltage

OL=200µA

0.45

I

OL=200µA ⁽²⁾

I

OL=1mA

2.0

HIGHPOWER

XOUT

V

OL

LOW Output Voltage

V

OL=0.5mA

LOWPOWER

With no load applied

0

HIGHPOWER

LOWPOWER

XCOUT

HOLD, RDY, TA0IN to TA4IN,

Hysteresis

TB0IN to TB5IN, INT0 to INT5, NMI,

VT+-

VT-

0.2

1.0

V

ADTRG, CTS0 to CTS2, SCL0 to SCL2,

SDA0 TO SDA2, CLK0 to CLK4,TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD2, SIN3, SIN4

V

T+-

V

T-

Hysteresis

RESET

XIN

0.2

2.5

0.8

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

XIN, RESET, CNVSS, BYTE

HIGH Input

Current

5.0

µA

I

IH

V

I

=5V

=0V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

XIN, RESET, CNVSS, BYTE

LOW Input

Current

I

IL

V

I

-5.0

170

µA

R

PULLUP

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

Pull-Up

Resistance

VI=0V

30

50

kΩ

R

fXIN

Feedback Resistance XIN

Feedback Resistance XCIN

1.5

15

MΩ

RfXCIN

VRAM

RAM Retention Voltage

At stop mode

2.0

V

NOTES:

1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=24MHz unless otherwise specified.

2. Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on the VCC2 port side.

3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

page 36

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

(1)

Table 5.11 Electrical Characteristics (2)

Standard

Typ.

Symbol

Measuring Condition

Parameter

Unit

Min.

Max.

20

f(BCLK)=24MHz,

No division, PLL operation

In single-chip mode, the output

pins are open and other pins are

Mask ROM

14

mA

VSS

No division, On-chip oscillation

1

f(BCLK)=24MHz,

No division, PLL operation

Flash Memory

18

27

mA

No division, On-chip oscillation

1.8

15

mA

Flash Memory

Program

f(BCLK)=10MHz,

V

CC1=5.0V

f(BCLK)=10MHz,

CC1=5.0V

Flash Memory

Erase

25

mA

V

Mask ROM

f(XCIN)=32kHz,

µA

Low power dissipation mode,

ROM ⁽³⁾

Power Supply Current

(VCC1=4.0 to 5.5V)

I

CC

f(BCLK)=32kHz,

Low power dissipation mode,

RAM ⁽³⁾

Flash Memory

µA

25

f(BCLK)=32kHz

Low power dissipation mode,

Flash memory ⁽³⁾

420

On-chip oscillation,

Wait mode

µA

50

f(BCLK)=32kHz,

(2)

7.5

Wait mode

,

Oscillation capacity High

Mask ROM

Flash Memory

f(BCLK)=32kHz,

µA

2.0

0.8

Wait mode ⁽²⁾

Oscillation capacity Low

,

Stop mode,

3.0

T

opr=25°C

Voltage Down Detection Dissipation Current ⁽⁴⁾

Reset Area Detection Dissipation Current ⁽⁴⁾

0.7

1.2

4

8

µA

I

det4

det3

NOTES:

1. Referenced to VCC1=VCC2= 4.2 to 5.5V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=24MHz unless otherwise specified.

2. With one timer operated using fC32.

3. This indicates the memory in which the program to be executed exists.

4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).

I

det4: VC27 bit in VCR2 register

det3: VC26 bit in VCR2 register

page 37

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Timing Requirements

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.12 External Clock Input (XIN input)

Standard

Symbol

Parameter

External Clock Input Cycle Time

External Clock Input HIGH Pulse Width

External Clock Input LOW Pulse Width

External Clock Rise Time

Unit

Min.

62.5

25

Max.

t

c

ns

t

w(H

)

t

w(L)

25

t

r

15

tf

External Clock Fall Time

Table 5.13 Memory Expansion Mode and Microprocessor Mode

Standard

Symbol

Parameter

Unit

Min.

Max.

tac1(RD-DB)

tac2(RD-DB)

tac3(RD-DB)

Data Input Access Time (for setting with no wait)

ns

(NOTE 1)

Data Input Access Time (for setting with wait)

Data Input Access Time (when accessing multiplex bus area)

Data Input Setup Time

(NOTE 2)

(NOTE 3)

tsu(DB-RD)

40

30

40

0

ns

tsu(RDY-BCLK )

tsu(HOLD-BCLK )

th(RD-DB)

RDY Input Setup Time

HOLD Input Setup Time

Data Input Hold Time

th(BCLK -RDY)

th(BCLK-HOLD )

0

RDY Input Hold Time

HOLD Input Hold Time

0

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 45

[ns]

2. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

– 45

n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait

setting.

f(BCLK)

[ns]

3. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

f(BCLK)

– 45

[ns] n is “2” for 2-wait setting, “3” for 3-wait setting.

page 38

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Timing Requirements

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.14 Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

ns

t

c(TA)

w(TAH)

w(TAL)

TAiIN Input Cycle Time

t

40

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.15 Timer A Input (Gating Input in Timer Mode)

Standard

Min. Max.

Symbol

Parameter

Unit

ns

t

c(TA)

w(TAH)

w(TAL)

400

200

TAiIN Input Cycle Time

t

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.16 Timer A Input (External Trigger Input in One-shot Timer Mode)

Standard

Min. Max.

Symbol

Parameter

Unit

ns

t

c(TA)

200

100

TAiIN Input Cycle Time

t

w(TAH)

w(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.17 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Standard

Min. Max.

100

Symbol

Parameter

Unit

t

w(TAH)

ns

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

w(TAL)

Table 5.18 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

2000

1000

400

Max.

t

c(UP)

ns

TAiOUT Input Cycle Time

t

w(UPH)

w(UPL)

TAiOUT Input HIGH Pulse Width

t

TAiOUT Input LOW Pulse Width

TAiOUT Input Setup Time

TAiOUT Input Hold Time

t

su(UP-TIN)

t

h(TIN UP)

-

400

Table 5.19 Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

800

200

Max.

t

c(TA)

ns

TAiIN Input Cycle Time

TAiOUT Input Setup Time

TAiIN Input Setup Time

t

su(TAIN-TAOUT)

su(TAOUT-TAIN)

t

page 39

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Timing Requirements

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.20 Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t

c(TB)

ns

TBiIN Input Cycle Time (counted on one edge)

t

w(TBH)

w(TBL)

TBiIN Input HIGH Pulse Width (counted on one edge)

TBiIN Input LOW Pulse Width (counted on one edge)

TBiIN Input Cycle Time (counted on both edges)

TBiIN Input HIGH Pulse Width (counted on both edges)

TBiIN Input LOW Pulse Width (counted on both edges)

40

t

c(TB)

w(TBH)

w(TBL)

200

80

t

80

Table 5.21 Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t

c(TB)

TBiIN Input Cycle Time

ns

t

w(TBH)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

t

w(TBL)

Table 5.22 Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t

c(TB)

ns

TBiIN Input Cycle Time

t

w(TBH)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

t

w(TBL)

Table 5.23 A/D Trigger Input

Standard

Symbol

Parameter

Unit

Min.

1000

125

Max.

t

c(AD)

ns

ADTRG Input Cycle Time

t

w(ADL)

ADTRG input LOW Pulse Width

Table 5.24 Serial I/O

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

t

c(CK)

w(CKH)

w(CKL)

ns

CLKi Input Cycle Time

CLKi Input HIGH Pulse Width

CLKi Input LOW Pulse Width

TXDi Output Delay Time

TXDi Hold Time

t

d(C-Q)

h(C-Q)

80

0

70

90

t

su(D-C)

RXDi Input Setup Time

RXDi Input Hold Time

t

h(C-D)

_______

Table 5.25 External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

250

Max.

t

w(INH)

w(INL)

ns

INTi Input HIGH Pulse Width

INTi Input LOW Pulse Width

t

page 40

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Switching Characteristics

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.26 Memory Expansion and Microprocessor Modes (for setting with no wait)

Standard

Measuring condition

Symbol

Parameter

Address Output Delay Time

Unit

Min.

Max.

25

td(BCLK-AD)

t^h(BCLK-AD)

th(RD-AD)

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

4

0

t^h(WR-AD)

(NOTE 2)

t^d(BCLK-CS)

t^h(BCLK-CS)

t^d(BCLK-ALE)

t^h(BCLK-ALE)

t^d(BCLK-RD)

t^h(BCLK-RD)

t^d(BCLK-WR)

t^h(BCLK-WR)

t^d(BCLK-DB)

t^h(BCLK-DB)

t^d(DB-WR)

25

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

4

15

25

40

ns

ALE Signal Output Hold Time

–4

See Figure 5.2

RD Signal Output Delay Time

RD Signal Output Hold Time

0

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK)⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR)⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

ns

t^h(WR-DB)

t^d(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 40

[ns]

f(BCLK) is 12.5MHz or less.

2. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 10

[ns]

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = –CR X ln (1 – VOL / VCC2

)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time

of output “L” level is

t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2

)

= 6.7ns.

P0

P1

P2

P3

P4

30pF

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

Figure 5.2 Ports P0 to P14 Measurement Circuit

page 41

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Switching Characteristics

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.27 Memory Expansion and Microprocessor Modes

(for 1- to 3-wait setting and external area access)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t

d(BCLK-AD)

h(BCLK-AD)

h(RD-AD)

Address Output Delay Time

25

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

4

0

h(WR-AD)

(NOTE 2)

d(BCLK-CS)

h(BCLK-CS)

d(BCLK-ALE)

h(BCLK-ALE)

d(BCLK-RD)

h(BCLK-RD)

d(BCLK-WR)

h(BCLK-WR)

d(BCLK-DB)

h(BCLK-DB)

d(DB-WR)

25

15

25

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

4

ALE Signal Output Hold Time

RD Signal Output Delay Time

–4

See Figure 5.2

RD Signal Output Hold Time

0

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK)⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR)⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

h(WR-DB)

d(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

f(BCLK)

n is “1” for 1-wait setting, “2” for 2-wait

setting and “3” for 3-wait setting.

When n=1, f(BCLK) is 12.5MHz or less.

– 40

[ns]

2. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 10

[ns]

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = –CR X ln (1 – VOL / VCC2

)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time

of output “L” level is

t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2

)

= 6.7ns.

page 42

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Switching Characteristics

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.28 Memory Expansion and Microprocessor Modes

(for 2- to 3-wait setting, external area access and multiplex bus selection)

Standard

Measuring

Condition

Symbol

Parameter

Unit

Min.

Max.

t

d(BCLK-AD)

h(BCLK-AD)

Address Output Delay Time

25

ns

t

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

4

(NOTE 1)

t

h(RD-AD)

t

h(WR-AD)

Address Output Hold Time (in relation to WR)

ns

(NOTE 1)

t

d(BCLK-CS)

h(BCLK-CS)

Chip Select Output Delay Time

25

ns

Chip Select Output Hold Time (in relation to BCLK)

Chip Select Output Hold Time (in relation to RD)

Chip Select Output Hold Time (in relation to WR)

RD Signal Output Delay Time

4

(NOTE 1)

t

h(RD-CS)

t

h(WR-CS)

(NOTE 1)

d(BCLK-RD)

See Figure 5.2

h(BCLK-RD)

RD Signal Output Hold Time

0

t

d(BCLK-WR)

WR Signal Output Delay Time

25

40

ns

h(BCLK-WR)

d(BCLK-DB)

WR Signal Output Hold Time

Data Output Delay Time (in relation to BCLK)

0

t

h(BCLK-DB)

Data Output Hold Time (in relation to BCLK)

Data Output Delay Time (in relation to WR)

4

ns

(NOTE 2)

t

d(DB-WR)

h(WR-DB)

(NOTE 1)

t

Data Output Hold Time (in relation to WR)

HLDA Output Delay Time

ns

d(BCLK-HLDA)

40

15

t

d(BCLK-ALE) ALE Signal Output Delay Time (in relation to BCLK)

h(BCLK-ALE) ALE Signal Output Hold Time (in relation to BCLK)

ns

– 4

(NOTE 3)

t

d(AD-ALE)

ALE Signal Output Delay Time (in relation to Address)

(NOTE 4)

t

h(ALE-AD)

ALE Signal Output Hold Time (in relation to Adderss)

RD Signal Output Delay From the End of Adress

ns

t

d(AD-RD)

0

t

d(AD-WR)

WR Signal Output Delay From the End of Adress

Address Output Floating Start Time

ns

t

dZ(RD-AD)

8

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

–10

[ns]

2. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

–40

[ns]

f(BCLK)

n is “2” for 2-wait setting, “3” for 3-wait setting.

3. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

–25

[ns]

f(BCLK)

4. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

–15

[ns]

f(BCLK)

page 43

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

XIN input

tf

tw(H)

tw(L)

tr

tc

tc(TA)

tw(TAH)

TAiIN input

tw(TAL)

tc(UP)

tw(UPH)

TAiOUT input

tw(UPL)

TAiOUT input

(Up/down input)

During event counter mode

TAiIN input

(When count on falling

edge is selected)

th(TIN–UP)

tsu(UP–TIN)

TAiIN input

(When count on rising

edge is selected)

Two-phase pulse input in

event counter mode

tc(TA)

TAiIN input

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

TAiOUT input

tsu(TAOUT-TAIN)

tc(TB)

tw(TBH)

tw(ADL)

TBiIN input

tw(TBL)

tc(AD)

ADTRG input

Figure 5.3 Timing Diagram (1)

page 44

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

t

c(CK)

t

w(CKH)

CLKi

t

w(CKL)

t

h(C–Q)

TXDi

RXDi

t

su(D–C)

t

d(C–Q)

t

h(C–D)

t

w(INL)

INTi input

t

w(INH)

Figure 5.4 Timing Diagram (2)

page 45

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(Effective for setting with wait)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RD

(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

tsu(RDY–BCLK)

th(BCLK–RDY)

(Common to setting with wait and setting without wait)

BCLK

t

h(BCLK–HOLD)

tsu(HOLD–BCLK)

HOLD input

HLDA output

td(BCLK–HLDA)

t

d(BCLK–HLDA)

P0, P1, P2,

P3, P4,

P5_0 to P5_2 ⁽¹⁾

Hi–Z

NOTES:

1. These pins are set to high-impedance regardless of the input level of the

BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.

Measuring conditions :

• VCC1=VCC2=5V

• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V

• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V

Figure 5.5 Timing Diagram (3)

page 46

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(For setting with no wait)

Read timing

BCLK

t

d(BCLK-CS)

t

h(BCLK-CS)

25ns.max

4ns.min

CSi

tcyc

t

d(BCLK-AD)

t

h(BCLK-AD)

25ns.max

4ns.min

ADi

BHE

td(BCLK-ALE)

t

h(BCLK-ALE)

t

h(RD-AD)

-4ns.min

25ns.max

0ns.min

ALE

RD

t

d(BCLK-RD)

t

h(BCLK-RD)

25ns.max

0ns.min

t

ac1(RD-DB)

(0.5 X tcyc-45)ns.max

Hi-Z

DBi

t

su(DB-RD)

t

h(RD-DB)

40ns.min

0ns.min

Write timing

BCLK

t

d(BCLK-CS)

25ns.max

t

h(BCLK-CS)

4ns.min

CSi

t

cyc

t

d(BCLK-AD)

25ns.max

t

h(BCLK-AD)

4ns.min

ADi

BHE

t

d(BCLK-ALE)

25ns.max

t

h(BCLK-ALE)

-4ns.min

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

ALE

t

d(BCLK-WR)

25ns.max

t

h(BCLK-WR)

0ns.min

WR,WRL,

WRH

t

d(BCLK-DB)

t

h(BCLK-DB)

40ns.max

4ns.min

Hi-Z

DBi

td(DB-WR)

th(WR-DB)

(0.5 X tcyc-10)ns.min

(0.5 X tcyc-40)ns.min

1

t

cyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=5V

• Input timing voltage : VIL=0.8V, VIH=2.0V

• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.6 Timing Diagram (4)

page 47

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(for 1-wait setting and external area access)

Read timing

BCLK

t

d(BCLK-CS)

t

h(BCLK-CS)

25ns.max

4ns.min

CSi

tcyc

t

d(BCLK-AD)

t

h(BCLK-AD)

25ns.max

4ns.min

ADi

BHE

t

h(RD-AD)

t

h(BCLK-ALE)

t

d(BCLK-ALE)

0ns.min

-4ns.min

25ns.max

ALE

RD

t

d(BCLK-RD)

t

h(BCLK-RD)

25ns.max

0ns.min

t

ac2(RD-DB)

(1.5 X tcyc-45)ns.max

Hi-Z

DBi

t

h(RD-DB)

tsu(DB-RD)

0ns.min

40ns.min

Write timing

BCLK

t

d(BCLK-CS)

t

h(BCLK-CS)

25ns.max

4ns.min

CSi

tcyc

t

d(BCLK-AD)

t

h(BCLK-AD)

25ns.max

4ns.min

ADi

BHE

t

d(BCLK-ALE)

t

h(BCLK-ALE)

t

h(WR-AD)

-4ns.min

25ns.max

(0.5 X tcyc-10)ns.min

ALE

t

d(BCLK-WR)

25ns.max

t

h(BCLK-WR)

0ns.min

WR,WRL,

WRH

t

d(BCLK-DB)

t

h(BCLK-DB)

40ns.max

4ns.min

Hi-Z

DBi

t

d(DB-WR)

t

h(WR-DB)

(0.5 X tcyc-40)ns.min

(0.5 X tcyc-10)ns.min

1

t

cyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=5V

• Input timing voltage : VIL=0.8V, VIH=2.0V

• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.7 Timing Diagram (5)

page 48

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(

for 2-wait setting and external area access)

Read timing

t

cyc

BCLK

CSi

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

25ns.max

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

25ns.max

ADi

BHE

t

d(BCLK-ALE)

25ns.max

t

h(RD-AD)

0ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

RD

t

h(BCLK-RD)

0ns.min

t

d(BCLK-RD)

25ns.max

t

ac2(RD-DB)

(2.5 X tcyc-45)ns.max

Hi-Z

DBi

t

SU(DB-RD)

40ns.min

t

h(RD-DB)

0ns.min

Write timing

tcyc

BCLK

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

25ns.max

CSi

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

25ns.max

ADi

BHE

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

t

d(BCLK-ALE)

25ns.max

t

h(BCLK-ALE)

-4ns.min

ALE

t

h(BCLK-WR)

0ns.min

t

d(BCLK-WR)

25ns.max

WR, WRL

WRH

t

d(BCLK-DB)

40ns.max

t

h(BCLK-DB)

4ns.min

Hi-Z

DBi

t

d(DB-WR)

(1.5 X tcyc-40)ns.min

t

h(WR-DB)

(0.5 X tcyc-10)ns.min

1

t

cyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=5V

• Input timing voltage : VIL=0.8V, VIH=2.0V

• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.8 Timing Diagram (6)

page 49

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(

for 3-wait setting and external area access

)

Read timing

t

cyc

BCLK

CSi

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

25ns.max

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

25ns.max

ADi

BHE

t

d(BCLK-ALE)

25ns.max

t

h(RD-AD)

0ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

RD

t

h(BCLK-RD)

0ns.min

t

d(BCLK-RD)

25ns.max

t

ac2(RD-DB)

(3.5 X tcyc-45)ns.max

Hi-Z

DBi

t

su(DB-RD)

40ns.min

t

h(RD-DB)

0ns.min

Write timing

tcyc

BCLK

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

25ns.max

CSi

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

25ns.max

ADi

BHE

t

d(BCLK-ALE)

25ns.max

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

t

h(BCLK-WR)

0ns.min

t

d(BCLK-WR)

25ns.max

WR, WRL

WRH

t

d(BCLK-DB)

40ns.max

t

h(BCLK-DB)

4ns.min

Hi-Z

DBi

t

d(DB-WR)

(2.5 X tcyc-40)ns.min

t

h(WR-DB)

(0.5 X tcyc-10)ns.min

1

t

cyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=5V

• Input timing voltage : VIL=0.8V, VIH=2.0V

• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.9 Timing Diagram (7)

page 50

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(For 1- or 2-wait setting, external area access and multiplex bus selection)

Read timing

BCLK

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

25ns.max

t

h(RD-CS)

(0.5 X tcyc-10)ns.min

tcyc

CSi

t

d(AD-ALE)

(0.5 X tcyc-25)ns.min

t

h(ALE-AD)

(0.5 X tcyc-15)ns.min

ADi

/DBi

Address

Data input

t

dZ(RD-AD)

t

h(RD-DB)

0ns.min

8ns.max

t

ac3(RD-DB)

t

su(DB-RD)

(1.5 X tcyc-45)ns.max

40ns.min

t

d(AD-RD)

0ns.min

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

25ns.max

ADi

BHE

t

d(BCLK-ALE)

25ns.max

t

h(BCLK-ALE)

-4ns.min

t

h(RD-AD)

(0.5 X tcyc-10)ns.min

ALE

RD

t

d(BCLK-RD)

25ns.max

t

h(BCLK-RD)

0ns.min

Write timing

BCLK

t

h(BCLK-CS)

tcyc

t

d(BCLK-CS)

t

h(WR-CS)

4ns.min

25ns.max

(0.5 X tcyc-10)ns.min

CSi

t

h(BCLK-DB)

t

d(BCLK-DB)

4ns.min

40ns.max

ADi

Address

Data output

Address

/DBi

t

d(DB-WR)

t

h(WR-DB)

t

d(AD-ALE)

(1.5 X tcyc-40)ns.min

(0.5 X tcyc-10)ns.min

(0.5 X tcyc-25)ns.min

t

d(BCLK-AD)

t

h(BCLK-AD)

25ns.max

4ns.min

ADi

BHE

t

d(BCLK-ALE)

t

h(BCLK-ALE)

t

d(AD-WR)

t

h(WR-AD)

25ns.max

-4ns.min

0ns.min

(0.5 X tcyc-10)ns.min

ALE

t

d(BCLK-WR)

t

h(BCLK-WR)

25ns.max

0ns.min

WR,WRL,

WRH

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=5V

• Input timing voltage : VIL=0.8V, VIH=2.0V

• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.10 Timing Diagram (8)

page 51

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Memory Expansion Mode, Microprocessor Mode

(

For 3-wait setting, external area access and multiplex bus selection)

Read timing

tcyc

BCLK

th(RD-CS)

(0.5 X tcyc-10)ns.min

th(BCLK-CS)

4ns.min

td(BCLK-CS)

25ns.max

CSi

td(AD-ALE)

(0.5 X tcyc-25)ns.min

th(ALE-AD)

(0.5 X tcyc-15)ns.min

ADi

Data input

Address

/DBi

th(RD-DB)

tdZ(RD-AD)

8ns.max

0ns.min

tac3(RD-DB)

(2.5 X tcyc-45)ns.max

td(BCLK-AD)

25ns.max

tsu(DB-RD)

40ns.min

td(AD-RD)

0ns.min

th(BCLK-AD)

4ns.min

ADi

BHE

(no multiplex)

td(BCLK-ALE)

25ns.max

th(RD-AD)

th(BCLK-ALE)

-4ns.min

(0.5 X tcyc-10)ns.min

ALE

RD

th(BCLK-RD)

0ns.min

td(BCLK-RD)

25ns.max

Write timing

tcyc

BCLK

th(WR-CS)

th(BCLK-CS)

4ns.min

(0.5 X tcyc-10)ns.min

td(BCLK-CS)

25ns.max

CSi

th(BCLK-DB)

4ns.min

td(BCLK-DB)

40ns.max

ADi

/DBi

Address

Data output

td(AD-ALE)

(0.5 X tcyc-25)ns.min

td(DB-WR)

th(WR-DB)

(0.5 X tcyc-10)ns.min

(2.5 X tcyc-40)ns.min

td(BCLK-AD)

25ns.max

th(BCLK-AD)

4ns.min

ADi

BHE

^{(no multiplex)}td(BCLK-ALE)

25ns.max

th(BCLK-ALE)

-4ns.min

th(WR-AD)

(0.5 X tcyc-10)ns.min

td(AD-WR)

0ns.min

ALE

th(BCLK-WR)

0ns.min

td(BCLK-WR)

25ns.max

WR, WRL

WRH

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=5V

• Input timing voltage : VIL=0.8V, VIH=2.0V

• Output timing voltage : VOL=0.4V, VOH=2.4V

Figure 5.11 Timing Diagram (9)

page 52

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

1)

Table 5.29 Electrical Characteristics ⁽

Standard

Typ.

Measuring Condition

Unit

Symbol

Parameter

Min.

Max.

HIGH Output

Voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

V

CC1

I

OH

=

-

1mA

V

CC1

-

0.5

V

OH

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

OH=

1mA ⁽²⁾

CC2-

0.5

V

CC2

V

CC1

HIGHPOWER

V

CC1-

0.5

I

OH=

-

0.1mA

V

XOUT

HIGH Output Voltage

LOWPOWER

OH=

50µA

CC1-

With no load applied

2.5

1.6

HIGHPOWER

LOWPOWER

XCOUT

LOW Output

Voltage

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

I

OL=1mA

0.5

V

OL

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

I

OL=1mA ⁽²⁾

I

OL=0.1mA

0.5

HIGHPOWER

XOUT

LOW Output Voltage

V

LOWPOWER

OL=50µA

With no load applied

0

HIGHPOWER

LOWPOWER

XCOUT

Hysteresis

HOLD, RDY, TA0IN to TA4IN,

TB0IN to TB5IN, INT0 to INT5, NMI,

V

T+-

V

T-

ADTRG, CTS0 to CTS2, SCL0 to SCL2,

0.2

0.8

V

SDA0 to SDA2, CLK0 to CLK4, TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD2, SIN3, SIN4

V

T+-

V

T-

Hysteresis

0.2

(0.7)

1.8

0.8

V

RESET

XIN

HIGH Input

Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

I

IH

V

I

=3V

4.0

µA

XIN, RESET, CNVSS, BYTE

LOW Input

Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

I

IL

V

I

=0V

µA

kΩ

-

XIN, RESET, CNVSS, BYTE

R

PULLUP

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

Pull-Up

Resistance

I

50

100

500

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

R

fXIN

Feedback Resistance

RAM Retention Voltage

XIN

3.0

25

MΩ

V

RfXCIN

XCIN

V

RAM

At stop mode

2.0

NOTES:

1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.

2. VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13.

3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

page 53

Rev. 2.30 Sep 01, 2004

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

1)

Table 5.30 Electrical Characteristics (2) ⁽

Standard

Typ.

Symbol

Measuring Condition

Parameter

Unit

Min.

Max.

11

f(BCLK)=10MHz,

No division

In single-chip mode, the output

pins are open and other pins are

Mask ROM

8

mA

VSS

No division, On-chip oscillation

1

8

f(BCLK)=10MHz,

No division

Flash Memory

13

mA

No division, On-chip oscillation

1.8

12

mA

Flash Memory

Program

f(BCLK)=10MHz,

Vcc1=3.0V

Flash Memory

Erase

f(BCLK)=10MHz,

Vcc1=3.0V

22

25

Mask ROM

f(XCIN)=32kHz,

Low power dissipation mode,

ROM ⁽³⁾

µA

Power Supply Current

(VCC1=2.7 to 3.6V)

I

CC

f(BCLK)=32kHz,

Low power dissipation mode,

RAM ⁽³⁾

Flash Memory

25

µA

f(BCLK)=32kHz,

420

Low power dissipation mode,

Flash memory ⁽³⁾

On-chip oscillation,

Wait mode

µA

45

f(BCLK)=32kHz,

6.0

Wait mode ⁽²⁾

,

Oscillation capacity High

Mask ROM

Flash Memory

f(BCLK)=32kHz,

µA

1.8

0.7

Wait mode ⁽²⁾

Oscillation capacity Low

Stop mode,

,

3.0

T

opr=25°C

0.6

0.4

4

2

µA

Voltage Down Detection Dissipation Current ⁽⁴⁾

Reset Level Detection Dissipation Current ⁽⁴⁾

I

det4

det3

NOTES:

1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS=0V at Topr = -20 to 85 °C / -40 to 85 °C, f(BCLK)=10MHz unless otherwise specified.

2. With one timer operated using fC32.

3. This indicates the memory in which the program to be executed exists.

4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).

I

det4: VC27 bit of VCR2 register

det3: VC26 bit of VCR2 register

page 54

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

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5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Timing Requirements

o

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.31 External Clock Input (XIN Input)

Standard

Symbol

Parameter

External Clock Input Cycle Time

External Clock Input HIGH Pulse Width

External Clock Input LOW Pulse Width

External Clock Rise Time

Unit

Min.

100

40

Max.

t

c

ns

t

w(H

)

t

w(L)

40

t

r

18

t

f

External Clock Fall Time

Table 5.32 Memory Expansion and Microprocessor Modes

Standard

Symbol

Parameter

Unit

Min.

Max.

t

ac1(RD-DB)

Data Input Access Time (for setting with no wait)

ns

(NOTE 1)

t

ac2(RD-DB)

(NOTE 2)

(NOTE 3)

Data Input Access Time (for setting with wait)

Data Input Access Time (when accessing multiplex bus area)

Data Input Setup Time

t

ac3(RD-DB)

t

su(DB-RD)

50

40

50

0

ns

t

su(RDY-BCLK )

su(HOLD-BCLK )

h(RD-DB)

RDY Input Setup Time

HOLD Input Setup Time

Data Input Hold Time

t

h(BCLK -RDY)

0

RDY Input Hold Time

HOLD Input Hold Time

t

h(BCLK-HOLD )

0

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 60

[ns]

2. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

– 60

n is “2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait

setting.

[ns]

f(BCLK)

3. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

f(BCLK)

– 60

[ns]

n is “2” for 2-wait setting, “3” for 3-wait setting.

page 55

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Timing Requirements

o

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.33 Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

60

Max.

ns

t

c(TA)

w(TAH)

w(TAL)

TAiIN Input Cycle Time

t

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

60

Table 5.34 Timer A Input (Gating Input in Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

600

Max.

ns

t

c(TA)

w(TAH)

w(TAL)

TAiIN Input Cycle Time

t

300

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.35 Timer A Input (External Trigger Input in One-shot Timer Mode)

Standard

Symbol

Parameter

Unit

Min.

300

150

Max.

ns

t

c(TA)

TAiIN Input Cycle Time

t

w(TAH)

w(TAL)

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.36 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

t

w(TAH)

w(TAL)

ns

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.37 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

3000

1500

600

Max.

t

c(UP)

ns

TAiOUT Input Cycle Time

t

w(UPH)

w(UPL)

TAiOUT Input HIGH Pulse Width

TAiOUT Input LOW Pulse Width

TAiOUT Input Setup Time

t

su(UP-TIN)

h(TIN-UP)

t

TAiOUT Input Hold Time

600

Table 5.38 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min. Max.

t

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

µs

ns

2

TAiIN Input Cycle Time

TAiOUT Input Setup Time

TAiIN Input Setup Time

t

500

t

page 56

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Timing Requirements

o

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.39 Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

150

Max.

t

c(TB)

w(TBH)

w(TBL)

c(TB)

w(TBH)

w(TBL)

TBiIN Input Cycle Time (counted on one edge)

ns

t

TBiIN Input HIGH Pulse Width (counted on one edge)

TBiIN Input LOW Pulse Width (counted on one edge)

TBiIN Input Cycle Time (counted on both edges)

TBiIN Input HIGH Pulse Width (counted on both edges)

TBiIN Input LOW Pulse Width (counted on both edges)

60

t

300

120

t

Table 5.40 Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

t

c(TB)

w(TBH)

w(TBL)

TBiIN Input Cycle Time

ns

t

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

t

Table 5.41 Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

600

300

Max.

t

c(TB)

ns

TBiIN Input Cycle Time

t

w(TBH)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

t

w(TBL)

Table 5.42 A/D Trigger Input

Standard

Symbol

Parameter

Unit

Min.

1500

200

Max.

t

c(AD)

w(ADL)

ns

ADTRG Input Cycle Time

t

ADTRG Input LOW Pulse Width

Table 5.43 Serial I/O

Standard

Symbol

Parameter

Unit

Min.

300

150

Max.

t

c(CK)

w(CKH)

w(CKL)

ns

CLKi Input Cycle Time

CLKi Input HIGH Pulse Width

CLKi Input LOW Pulse Width

TXDi Output Delay Time

TXDi Hold Time

t

d(C-Q)

h(C-Q)

160

t

0

100

90

t

su(D-C)

RXDi Input Setup Time

RXDi Input Hold Time

t

h(C-D)

_______

Table 5.44 External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

380

Max.

t

w(INH)

w(INL)

ns

INTi Input HIGH Pulse Width

INTi Input LOW Pulse Width

t

page 57

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Switching Characteristics

o

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C unless otherwise specified)

Table 5.45 Memory Expansion, Microprocessor Modes (for setting with no wait)

Standard

Measuring

Condition

Symbol

Parameter

Address Output Delay Time

Unit

Min.

Max.

t

d(BCLK-AD)

h(BCLK-AD)

h(RD-AD)

30

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

4

0

h(WR-AD)

(NOTE 2)

d(BCLK-CS)

h(BCLK-CS)

d(BCLK-ALE)

h(BCLK-ALE)

d(BCLK-RD)

h(BCLK-RD)

d(BCLK-WR)

h(BCLK-WR)

d(BCLK-DB)

h(BCLK-DB)

d(DB-WR)

30

25

30

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

4

See Figure 5.12

ALE Signal Output Hold Time

–4

RD Signal Output Delay Time

RD Signal Output Hold Time

0

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK)⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR)⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

h(WR-DB)

d(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 40

[ns]

f(BCLK) is 12.5MHz or less.

2. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 10

[ns]

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = –CR X ln (1 – VOL / VCC2

)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time

of output “L” level is

t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2

)

= 6.7ns.

P0

P1

P2

P3

P4

30pF

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

Figure 5.12 Ports P0 to P14 Measurement Circuit

page 58

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Switching Characteristics

Table 5.46 Memory expansion and Microprocessor Modes

(for 1- to 3-wait setting and external area access)

Measuring

Standard

Symbol

Parameter

Unit

Condition

Min.

Max.

t

d(BCLK-AD)

h(BCLK-AD)

h(RD-AD)

Address Output Delay Time

30

ns

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

Address Output Hold Time (in relation to WR)

Chip Select Output Delay Time

4

0

h(WR-AD)

(NOTE 2)

d(BCLK-CS)

h(BCLK-CS)

d(BCLK-ALE)

h(BCLK-ALE)

d(BCLK-RD)

h(BCLK-RD)

d(BCLK-WR)

h(BCLK-WR)

d(BCLK-DB)

h(BCLK-DB)

d(DB-WR)

30

25

30

40

Chip Select Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time

4

See Figure 5.12

ALE Signal Output Hold Time

–4

RD Signal Output Delay Time

RD Signal Output Hold Time

0

WR Signal Output Delay Time

WR Signal Output Hold Time

0

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK)⁽³⁾

Data Output Delay Time (in relation to WR)

Data Output Hold Time (in relation to WR)⁽³⁾

HLDA Output Delay Time

4

(NOTE 1)

(NOTE 2)

h(WR-DB)

d(BCLK-HLDA)

40

NOTES:

1. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

f(BCLK)

n is “1” for 1-wait setting, “2” for 2-wait setting

and “3” for 3-wait setting.

– 40

[ns]

When n=1, f(BCLK) is 12.5MHz or less.

2. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

f(BCLK)

– 10

[ns]

3. This standard value shows the timing when the output is off,

and does not show hold time of data bus.

Hold time of data bus varies with capacitor volume and pull-up

(pull-down) resistance value.

Hold time of data bus is expressed in

R

C

DBi

t = –CR X ln (1 – VOL / VCC2

)

by a circuit of the right figure.

For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time

of output “L” level is

t = – 30pF X 1kΩ X ln (1 – 0.2VCC2 / VCC2

)

= 6.7ns.

page 59

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Switching Characteristics

o

(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = – 20 to 85 C / – 40 to 85 C, unless otherwise specified)

Table 5.47 Memory expansion and Microprocessor Modes

(for 2- to 3-wait setting, external area access and multiplex bus selection)

Standard

Measuring

Condition

Symbol

Parameter

Address Output Delay Time

Unit

Min.

Max.

t

d(BCLK-AD)

50

ns

t

h(BCLK-AD)

h(RD-AD)

Address Output Hold Time (in relation to BCLK)

Address Output Hold Time (in relation to RD)

4

(NOTE 1)

t

h(WR-AD)

d(BCLK-CS)

h(BCLK-CS)

h(RD-CS)

Address Output Hold Time (rin relation to WR)

Chip Select Output Delay Time

ns

50

Chip Select Output Hold Time (in relation to BCLK)

Chip Select Output Hold Time (in relation to RD)

Chip Select Output Hold Time (in relation to WR)

RD Signal Output Delay Time

4

(NOTE 1)

h(WR-CS)

d(BCLK-RD)

h(BCLK-RD)

d(BCLK-WR)

h(BCLK-WR)

d(BCLK-DB)

h(BCLK-DB)

d(DB-WR)

40

50

RD Signal Output Hold Time

See Figure 5.12

0

WR Signal Output Delay Time

WR signal Output Hold Time

Data Output Delay Time (in relation to BCLK)

Data Output Hold Time (in relation to BCLK)

Data Output Delay Time (in relation to WR)

4

(NOTE 2)

(NOTE 1)

t

h(WR-DB)

Data Output Hold Time (in relation to WR)

HLDA Output Delay Time

ns

d(BCLK-HLDA)

40

25

d(BCLK-ALE)

h(BCLK-ALE)

d(AD-ALE)

ALE Signal Output Delay Time (in relation to BCLK)

ALE Signal Output Hold Time (in relation to BCLK)

ALE Signal Output Delay Time (in relation to Address)

ALE Signal Output Hold Time (in relation to Adderss)

– 4

(NOTE 3)

h(ALE-AD)

(NOTE 4)

t

d(AD-RD)

d(AD-WR)

dZ(RD-AD)

RD Signal Output Delay From the End of Address

WR Signal Output Delay From the End of Address

Address Output Floating Start Time

0

ns

8

NOTES:

1. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

–10

[ns]

f(BCLK)

2. Calculated according to the BCLK frequency as follows:

(n–0.5) X 10⁹

n is “2” for 2-wait setting, “3” for 3-wait setting.

–50

[ns]

f(BCLK)

3. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

–40

[ns]

f(BCLK)

4. Calculated according to the BCLK frequency as follows:

0.5 X 10⁹

–15

[ns]

f(BCLK)

page 60

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

XIN input

tf

tw(H)

tw(L)

tr

tc

t

c(TA)

tw(TAH)

TAiIN input

tw(TAL)

tc(UP)

t

w(UPH)

TAiOUT input

tw(UPL)

TAiOUT input

(Up/down input)

During Event Counter Mode

TAiIN input

t

h(TIN–UP)

t

su(UP–TIN)

(When count on falling

edge is selected)

TAiIN input

(When count on rising

edge is selected)

Two-Phase Pulse Input in

Event Counter Mode

tc(TA)

TAiIN input

tsu(TAIN-TAOUT)

t

su(TAIN-TAOUT)

tsu(TAOUT-TAIN)

TAiOUT input

tsu(TAOUT-TAIN)

t

c(TB)

tw(TBH)

TBiIN input

t

w(TBL)

tc(AD)

t

w(ADL)

ADTRG input

Figure 5.13 Timing Diagram (1)

page 61

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

t

c(CK)

tw(CKH)

CLKi

t

w(CKL)

t

h(C–Q)

TXDi

RXDi

t

su(D–C)

t

d(C–Q)

th(C–D)

t

w(INL)

INTi input

t

w(INH)

Figure 5.14 Timing Diagram (2)

page 62

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(Effective for setting with wait)

BCLK

RD

(Separate bus)

WR, WRL, WRH

(Separate bus)

RD

(Multiplexed bus)

WR, WRL, WRH

(Multiplexed bus)

RDY input

t

su(RDY–BCLK)

th(BCLK–RDY)

(Common to setting with wait and setting without wait)

BCLK

tsu(HOLD–BCLK)

th(BCLK–HOLD)

HOLD input

HLDA output

td(BCLK–HLDA)

P0, P1, P2,

P3, P4,

P5_0 to P5_2 ⁽¹⁾

Hi–Z

NOTES:

1. These pins are set to high-impedance regardless of the input level of the

BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.

Measuring conditions :

• VCC1=VCC2=3V

• Input timing voltage : Determined with VIL=0.6V, VIH=2.4V

• Output timing voltage : Determined with VOL=1.5V, VOH=1.5V

Figure 5.15 Timing Diagram (3)

page 63

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(for setting with no wait)

Read timing

BCLK

t

d(BCLK-CS)

t

h(BCLK-CS)

30ns.max

4ns.min

CSi

tcyc

t

d(BCLK-AD)

t

h(BCLK-AD)

30ns.max

4ns.min

ADi

BHE

th(BCLK-ALE)

td(BCLK-ALE)

t

h(RD-AD)

-4ns.min

30ns.max

0ns.min

ALE

RD

t

d(BCLK-RD)

t

h(BCLK-RD)

30ns.max

0ns.min

t

ac1(RD-DB)

(0.5 X tcyc-60)ns.max

Hi-Z

DBi

t

su(DB-RD)

t

h(RD-DB)

50ns.min

0ns.min

Write timing

BCLK

t

d(BCLK-CS)

30ns.max

t

h(BCLK-CS)

4ns.min

CSi

t

cyc

t

d(BCLK-AD)

30ns.max

t

h(BCLK-AD)

4ns.min

ADi

BHE

t

d(BCLK-ALE)

30ns.max

t

h(BCLK-ALE)

-4ns.min

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

ALE

t

d(BCLK-WR)

30ns.max

t

h(BCLK-WR)

0ns.min

WR,WRL,

WRH

t

d(BCLK-DB)

t

h(BCLK-DB)

40ns.max

4ns.min

Hi-Z

DBi

t

h(WR-DB)

t

d(DB-WR)

(0.5 X tcyc-10)ns.min

(0.5 X tcyc-40)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=3V

• Input timing voltage : VIL=0.6V, VIH=2.4V

• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.16 Timing Diagram (4)

page 64

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(for 1-wait setting and external area access)

Read timing

BCLK

t

d(BCLK-CS)

t

h(BCLK-CS)

30ns.max

4ns.min

CSi

tcyc

t

d(BCLK-AD)

t

h(BCLK-AD)

30ns.max

4ns.min

ADi

BHE

t

h(RD-AD)

0ns.min

t

h(BCLK-ALE)

t

d(BCLK-ALE)

-4ns.min

30ns.max

ALE

RD

t

d(BCLK-RD)

t

h(BCLK-RD)

30ns.max

0ns.min

t

ac2(RD-DB)

(1.5 X tcyc-60)ns.max

Hi-Z

DBi

th(RD-DB)

t

su(DB-RD)

0ns.min

50ns.min

Write timing

BCLK

t

d(BCLK-CS)

t

h(BCLK-CS)

30ns.max

4ns.min

CSi

tcyc

t

d(BCLK-AD)

t

h(BCLK-AD)

30ns.max

4ns.min

ADi

BHE

t

d(BCLK-ALE)

t

h(BCLK-ALE)

t

h(WR-AD)

30ns.max

-4ns.min

(0.5 X tcyc-10)ns.min

ALE

t

d(BCLK-WR)

30ns.max

t

h(BCLK-WR)

0ns.min

WR,WRL,

WRH

t

d(BCLK-DB)

t

h(BCLK-DB)

40ns.max

4ns.min

Hi-Z

DBi

t

d(DB-WR)

t

h(WR-DB)

(0.5 X tcyc-40)ns.min

(0.5 X tcyc-10)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=3V

• Input timing voltage : VIL=0.6V, VIH=2.4V

• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.17 Timing Diagram (5)

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REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(for 2-wait setting and external area access)

Read timing

tcyc

BCLK

CSi

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

30ns.max

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

30ns.max

ADi

BHE

t

d(BCLK-ALE)

30ns.max

t

h(RD-AD)

0ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

RD

t

h(BCLK-RD)

0ns.min

t

d(BCLK-RD)

30ns.max

t

ac2(RD-DB)

(2.5 X tcyc-60)ns.max

Hi-Z

DBi

t

su(DB-RD)

50ns.min

t

h(RD-DB)

0ns.min

Write timing

t

cyc

BCLK

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

30ns.max

CSi

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

30ns.max

ADi

BHE

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

t

d(BCLK-ALE)

30ns.max

t

h(BCLK-ALE)

-4ns.min

ALE

t

h(BCLK-WR)

0ns.min

t

d(BCLK-WR)

30ns.max

WR, WRL

WRH

t

d(BCLK-DB)

40ns.max

t

h(BCLK-DB)

4ns.min

Hi-Z

DBi

t

d(DB-WR)

(1.5 X tcyc-40)ns.min

t

h(WR-DB)

(0.5 X tcyc-10)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=3V

• Input timing voltage : VIL=0.6V, VIH=2.4V

• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.18 Timing Diagram (6)

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Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(

for 3-wait setting and external area access

)

Read timing

t

cyc

BCLK

CSi

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

30ns.max

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

30ns.max

ADi

BHE

t

d(BCLK-ALE)

30ns.max

t

h(RD-AD)

0ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

RD

t

h(BCLK-RD)

0ns.min

t

d(BCLK-RD)

30ns.max

t

ac2(RD-DB)

(3.5 X tcyc-60)ns.max

Hi-Z

DBi

t

su(DB-RD)

50ns.min

t

h(RD-DB)

0ns.min

Write timing

tcyc

BCLK

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

30ns.max

CSi

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

30ns.max

ADi

BHE

t

d(BCLK-ALE)

30ns.max

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

t

h(BCLK-WR)

0ns.min

t

d(BCLK-WR)

30ns.max

WR, WRL

WRH

t

d(BCLK-DB)

40ns.max

t

h(BCLK-DB)

4ns.min

Hi-Z

DBi

t

d(DB-WR)

(2.5 X tcyc-40)ns.min

t

h(WR-DB)

(0.5 X tcyc-10)ns.min

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=3V

• Input timing voltage : VIL=0.6V, VIH=2.4V

• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.19 Timing Diagram (7)

page 67

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(For 2-wait setting, external area access and multiplex bus selection)

Read timing

BCLK

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

40ns.max

t

h(RD-CS)

(0.5 X tcyc-10)ns.min

t

cyc

CSi

t

d(AD-ALE)

(0.5 X tcyc-40)ns.min

t

h(ALE-AD)

(0.5 X tcyc-15)ns.min

ADi

/DBi

Address

Data input

Address

t

dZ(RD-AD)

t

h(RD-DB)

0ns.min

8ns.max

t

ac3(RD-DB)

tSU(DB-RD)

(1.5 X tcyc-60)ns.max

50ns.min

t

d(AD-RD)

0ns.min

t

h(BCLK-AD)

4ns.min

t

d(BCLK-AD)

40ns.max

ADi

BHE

t

d(BCLK-ALE)

40ns.max

t

h(BCLK-ALE)

-4ns.min

t

h(RD-AD)

(0.5 X tcyc-10)ns.min

ALE

RD

t

d(BCLK-RD)

40ns.max

t

h(BCLK-RD)

0ns.min

Write timing

BCLK

t

h(BCLK-CS)

tcyc

t

d(BCLK-CS)

t

h(WR-CS)

4ns.min

40ns.max

(0.5 X tcyc-10)ns.min

CSi

t

h(BCLK-DB)

t

d(BCLK-DB)

4ns.min

50ns.max

ADi

/DBi

Address

Data output

Address

td(DB-WR)

t

h(WR-DB)

t

d(AD-ALE)

(1.5 X tcyc-50)ns.min

(0.5 X tcyc-10)ns.min

(0.5 X tcyc-40)ns.min

t

d(BCLK-AD)

t

h(BCLK-AD)

40ns.max

4ns.min

ADi

BHE

td(BCLK-ALE)

t

h(BCLK-ALE)

t

d(AD-WR)

t

h(WR-AD)

40ns.max

-4ns.min

0ns.min

(0.5 X tcyc-10)ns.min

ALE

t

d(BCLK-WR)

t

h(BCLK-WR)

0ns.min

40ns.max

WR,WRL,

WRH

1

tcyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=3V

• Input timing voltage : VIL=0.6V, VIH=2.4V

• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.20 Timing Diagram (8)

page 68

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62P)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 3V

Memory Expansion Mode, Microprocessor Mode

(For 3-wait setting, external area access and multiplex bus selection)

Read timing

t

cyc

BCLK

t

h(RD-CS)

(0.5 X tcyc-10)ns.min

t

h(BCLK-CS)

6ns.min

t

d(BCLK-CS)

40ns.max

CSi

td(AD-ALE)

(0.5 X tcyc-40)ns.min

t

h(ALE-AD)

(0.5 X tcyc-15)ns.min

ADi

/DBi

Data input

Address

t

h(RD-DB)

0ns.min

t

dZ(RD-AD)

t

ac3(RD-DB)

t

d(BCLK-AD)

8ns.max

t

su(DB-RD)

50ns.min

td(AD-RD)

t

h(BCLK-AD)

4ns.min

40ns.max

(2.5 X tcyc-60)ns.max

0ns.min

ADi

BHE

(No multiplex)

t

d(BCLK-ALE)

40ns.max

t

h(RD-AD)

(0.5 X tcyc-10)ns.min

t

h(BCLK-ALE)

-4ns.min

ALE

RD

t

h(BCLK-RD)

0ns.min

t

d(BCLK-RD)

40ns.max

Write timing

tcyc

BCLK

t

h(WR-CS)

t

h(BCLK-CS)

4ns.min

t

d(BCLK-CS)

40ns.max

(0.5 X tcyc-10)ns.min

CSi

t

h(BCLK-DB)

4ns.min

t

d(BCLK-DB)

50ns.max

ADi

/DBi

Address

Data output

t

d(AD-ALE)

t

d(DB-WR)

t

h(WR-DB)

(0.5 X tcyc-10)ns.min

(0.5 X tcyc-40)ns.min

(2.5 X tcyc-50)ns.min

t

d(BCLK-AD)

40ns.max

t

h(BCLK-AD)

4ns.min

ADi

BHE

(No multiplex)

t

h(BCLK-ALE)

-4ns.min

t

d(BCLK-ALE)

40ns.max

t

h(WR-AD)

(0.5 X tcyc-10)ns.min

t

d(AD-WR)

0ns.min

ALE

t

h(BCLK-WR)

0ns.min

t

d(BCLK-WR)

40ns.max

WR, WRL

WRH

1

t

cyc=

f(BCLK)

Measuring conditions

• VCC1=VCC2=3V

• Input timing voltage : VIL=0.6V, VIH=2.4V

• Output timing voltage : VOL=1.5V, VOH=1.5V

Figure 5.21 Timing Diagram (9)

page 69

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

5.2 Electrical Characteristics (M16C/62PT)

Table 5.48 Absolute Maximum Ratings

Symbol

Parameter

Condition

CC1=VCC2=AVCC

Rated Value

-0.3 to 6.5

Unit

V

CC1, VCC2 Supply Voltage

V

AVCC Analog Supply Voltage

CC1=VCC2=AVCC

-0.3 to 6.5

V

RESET, CNVSS, BYTE,

Input

Voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,

P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1,

VREF, XIN

-0.3 to VCC1+0.3 ⁽¹⁾

V

I

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

-0.3 to V^CC2+0.3 ⁽¹⁾

-0.3 to 6.5

V

P7_0, P7_1

Output

Voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,

P8_6, P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11 0 to P11_7,

-0.3 to VCC1+0.3 ⁽¹⁾

P14_0, P14_1,

XOUT

V

P

O

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,

P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,

P12_0 to P12_7, P13_0 to P13_7

-0.3 to VCC2+0.3 ⁽¹⁾

-0.3 to 6.5

V

P7_0, P7_1

V

d

Power Dissipation

-40 ºC < T^opr≤ 85 °C

85 ºC < Topr ≤ 125 °C

300

200

mW

-40 to 85 / -40 to 125 ⁽²⁾

T

opr

stg

Operating Ambient

Temperature

When the Microcomputer is

Operating

°C

Flash Program Erase

0 to 60

T

Storage Temperature

-65 to 150

NOTES :

1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

2. T version = -40 to 85 °C, V version = -40 to 125 °C.

page 70

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REJ03B0001-0230Z

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

Table 5.49 Recommended Operating Conditions ⁽¹⁾

Standard

Unit

Symbol

Parameter

Typ.

Max.

Min.

4.0

V

CC1, VCC2

5.5

V

Supply Voltage(VCC1

=

VCC2

)

5.0

AVcc

Analog Supply Voltage

Supply Voltage

V

CC1

Vss

0

AVss

0

Analog Supply Voltage

V

CC2

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode)

0.8V^CC2

HIGH Input

Voltage

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,

P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,

V

IH

V

CC1

0.8VCC1

V

XIN, RESET, CNVSS, BYTE

6.5

P7_0 , P7_1

0.8VCC1

V

P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

0

0.2VCC2

LOW Input

Voltage

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode)

IL

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P14_0, P14_1,

0

V

0.2VCC1

-10.0

XIN, RESET, CNVSS, BYTE

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

HIGH Peak Output

Current

I

OH (peak)

OH (avg)

OL (peak)

mA

HIGH Average

Output Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

-5.0

mA

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

LOW Peak Output

Current

10.0

LOW Average

Output Current

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

OL (avg)

5.0

mA

f (XIN)

0

16

50

MHz

kHz

Main Clock Input Oscillation Frequency

Sub-Clock Oscillation Frequency

On-chip Oscillation Frequency

V

CC1=4.0 to 5.5V

32.768

1

f (XCIN)

f (Ring)

f (PLL)

2

MHz

ms

0.5

10

0

PLL Clock Oscillation Frequency ⁽⁴⁾

CPU Operation Clock

24

20

V

CC1=4.0 to 5.5V

CC1=5.0V

f (BCLK)

t

SU(PLL)

PLL Frequency Synthesizer Stabilization Wait Time

V

NOTES:

1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = -40 to 85 °C / -40 to 125 °C unless otherwise specified.

T version = -40 to 85 °C, V version = -40 to 125 °C.

2. The mean output current is the mean value within 100ms.

3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max. The total IOL(peak)

for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2

must be -40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be -40mA max. The total IOH(peak) for ports

P6, P7, and P8_0 to P8_4 must be -40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0, and P14_1

must be -40mA max.

As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS

4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

.

page 71

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

(1)

Table 5.50 A/D Conversion Characteristics

Standard

Min. Typ. Max.

10

Symbol

Parameter

Measuring Condition

Unit

Bits

–

Resolution

VREF =VCC1

AN0 to AN7 input

V

REF

=

AN0_0 to AN0_7 input

AN2_0 to AN2_7 input

ANEX0, ANEX1 input

V

CC1

±3

LSB

Integral

5V

Non-Linearity

Error

INL

10 bits

8 bits

External operation amp

connection mode

±7

±2

LSB

V^REF=VCC1=5V

AN0 to AN7 input

V

5V

REF

=

AN0_0 to AN0_7 input

AN2_0 to AN2_7 input

ANEX0, ANEX1 input

CC1

±3

LSB

Absolute

Accuracy

–

10 bits

8 bits

External operation amp

connection mode

±7

±2

LSB

V^REF=VCC1=5V

Tolerance Level Impedance

Differential Non-Linearity error

Offset Error

Gain Error

Ladder Resistance

3

kΩ

–

DNL

–

LSB

kΩ

±1

±3

–

10

40

R^LADDER

tCONV

V^REF=VCC1

10-bit Conversion Time, Sample & Hold

Function Available

2.75

V

REF =VCC1=5V, øAD=12MHz

µs

8-bit Conversion Time, Sample & Hold

Function Available

2.33

0.25

V

REF =VCC1=5V, øAD=12MHz

t^CONV

µs

Sampling Time

µs

V

tSAMP

VREF

Reference Voltage

Analog Input Voltage

2.0

0

V^CC1

V^IA

V

VREF

NOTES:

1. Referenced to VCC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = -40 to 85 °C / -40 to 125 °C unless otherwise

specified. T version = -40 to 85 °C, V version = -40 to 125 °C.

2. øAD frequency must be 12 MHz or less.

3. When sample & hold function is disabled, øAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.

When sample & hold function is enabled, øAD frequency must be 1MHz or more, in addition to the limitation in Note 2.

(1)

Table 5.51 D/A Conversion Characteristics

Standard

Min. Typ. Max.

8

Symbol

Parameter

Measuring Condition

Unit

–

Bits

%

Resolution

1.0

3

Absolute Accuracy

Setup Time

t

su

µs

R

O

4

10

20

kΩ

Output Resistance

I

VREF

(NOTE 2)

1.5

mA

Reference Power Supply Input Current

NOTES :

1. Referenced to VCC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = -40 to 85 °C / -40 to 125 °C unless otherwise specified.

T version=-40 to 85 °C, V version=-40 to 125 °C

2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The

resistor ladder of the A/D converter is not included. Also, when D/A register contents are not “00h,” the IVREF will

flow even if Vref is disconnected by the A/D control register.

page 72

Rev. 2.30 Sep 01, 2004

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

(1)

Table 5.52 Flash Memory Version Electrical Characteristics

for 100 cycle products (B, U)

Standard

Unit

Symbol

-

Parameter

Min.

100

Typ.

Max.

Program and Erase Endurance ⁽³⁾

Word Program Time (VCC1=5.0V, Topr=25°C)

Lock Bit Program Time

cycle

-

25

200

µs

s

200

-

Block Erase Time

4-Kbyte block

0.3

0.5

0.8

4

(VCC1=5.0V, Topr=25 °C)

8-Kbyte block

32-Kbyte block

64-Kbyte block

4

s

4

s

Erase All Unlocked Blocks Time ⁽²⁾

-

4 X n

s

t

PS

Flash Memory Circuit Stabilization Wait Time

Data Hold Time ⁽⁵⁾

15

µs

-

10

(6)

year

Table 5.53 Flash Memory Version Electrical Characteristics

(7)

for 10,000 cycle products (Block A and Block 1 ) (B7, U7)

Standard

Symbol

-

Parameter

Unit

Min.

10,000 ⁽⁴⁾

Typ.

Max.

Program and Erase Endurance ^{(3, 8, 9)}

Word Program Time (VCC1=5.0V, Topr=25°C)

Lock Bit Program Time

cycle

µs

-

25

µs

-

Block Erase Time

(VCC1=5.0V, Topr=25 °C)

4-Kbyte block

0.3

s

t

PS

Flash Memory Circuit Stabilization Wait Time

Data Hold Time ⁽⁵⁾

15

µs

-

10

year

NOTES :

1. Referenced to VCC1=4.5 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.

2. n denotes the number of block erases.

3. Program and Erase Endurance refers to the number of times a block erase can be performed.

If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.

For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this

counts as one program and erase endurance. Data cannot be written to the same address more than once without

erasing the block. (Rewrite prohibited)

4. Maximum number of E/W cycles for which operation is guaranteed.

5.

Topr = -40 to 85 °C (T version) / -40 to 125 °C (V version).

6. Referenced to VCC1 = 4.0 to 5.5V at Topr = -40 to 85 °C (T version) / -40 to 125 °C (V version) unless otherwise specified.

7. Table 23.53 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 23.52.

8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites,

write to unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are

used. For example, an 8-word program can be written 256 times maximum before erase becomes necessary.

Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to

track the total number of times erasure is used.

9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase

command at least three times until erase error disappears.

10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (B7 and U7).

11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.

Table 5.54 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics

(at Topr = 0 to 60^oC)

Flash Program, Erase Voltage

Flash Read Operation Voltage

VCC1=5.0 ± 0.5 V

VCC1=4.0 to 5.5 V

page 73

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

Table 5.55 Power Supply Circuit Timing Characteristics

Standard

Typ.

Symbol

Measuring condition

Unit

Parameter

Min.

Max.

2

ms

t

d(P-R)

Time for Internal Power Supply Stabilization During Powering-On

STOP Release Time

VCC1=4.0 to 5.5V

d(R-S)

d(W-S)

150

µs

Low Power Dissipation Mode Wait Mode Release Time

td(P-R)

Time for Internal Power

Supply Stabilization During

Powering-On

V

CC

t

d(P-R)

CPU clock

Interrupt for

d(R-S)

t

(a) Stop mode release

or

STOP Release Time

(b) Wait mode release

d(W-S)

CPU clock

Low Power Dissipation Mode

Wait Mode Release Time

(a)

(b)

t

d(R-S)

t

d(W-S)

Figure 5.22 Power Supply Circuit Timing Diagram

page 74

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

(1

)

Table 5.56 Electrical Characteristics

Standard

Typ.

Symbol

Measuring Condition

Unit

Parameter

Min.

Max.

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

HIGH Output

Voltage

I

OH=-5mA

V

CC1-2.0

V

CC1

CC2

CC1

V

OH

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

OH=-5mA ⁽²⁾

CC2-2.0

CC1-0.3

P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

HIGH Output

Voltage

I

OH=-200µA

V

OH=-200µA ⁽²⁾

V

CC2-0.3

V

CC2

HIGHPOWER

I

OH=-1mA

V

CC1-2.0

V

CC1

HIGH Output Voltage

HIGH Output Voltage XCOUT

XOUT

V

LOWPOWER

OH=-0.5mA

V

OH

With no load applied

2.5

1.6

HIGHPOWER

LOWPOWER

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

LOW Output

Voltage

I

OL=5mA

2.0

V

OL

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4, P8_6, P8_7,

P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P12_0 to P12_7, P13_0 to P13_7

I

OL=5mA ⁽²⁾

LOW Output

Voltage

0.45

OL=200µA

I

OL=200µA ⁽²⁾

I

OL=1mA

2.0

HIGHPOWER

V

OL

LOW Output Voltage

XOUT

V

OL=0.5mA

LOWPOWER

With no load applied

0

HIGHPOWER

LOWPOWER

XCOUT

HOLD, RDY, TA0IN to TA4IN,

Hysteresis

TB0IN to TB5IN, INT0 to INT5, NMI,

V

T+-

V

T-

0.2

1.0

V

ADTRG, CTS0 to CTS2, SCL0 to SCL2,

SDA0 TO SDA2, CLK0 to CLK4, TA0OUT to TA4OUT,

KI0 to KI3, RXD0 to RXD2, SIN3, SIN4

V

T+-

V

T-

Hysteresis

RESET

XIN

0.2

2.5

0.8

V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

XIN, RESET, CNVSS, BYTE

HIGH Input

Current

5.0

µA

I

IH

V

I

=5V

=0V

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,

P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,

P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,

XIN, RESET, CNVSS, BYTE

LOW Input

Current

I

IL

I

-5.0

170

µA

R

PULLUP

P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,

P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,

P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,

P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1

Pull-Up

Resistance

VI=0V

30

50

kΩ

R

fXIN

Feedback Resistance XIN

Feedback Resistance XCIN

RAM Retention Voltage

1.5

15

MΩ

V

RfXCIN

V

RAM

At stop mode

2.0

NOTES:

1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS=0V at Topr = -40 to 85 °C / -40 to 125 °C, f(BCLK)=24MHz unless otherwise specified.

T version = -40 to 85 °C, V version = -40 to 125 °C.

2. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.

page 75

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

(1)

Table 5.57 Electrical Characteristics (2)

Standard

Typ.

Measuring Condition

Unit

Symbol

Parameter

Min.

Max.

20

f(BCLK)=24MHz,

In single-chip mode, the output

pins are open and other pins are

Mask ROM

14

mA

No division, PLL operation

V

SS

No division, On-chip oscillation

1

f(BCLK)=24MHz,

No division, PLL operation

Flash memory

18

27

mA

No division, On-chip oscillation

mA

1.8

15

Flash memory

Program

f(BCLK)=10MHz,

V

CC1=5.0V

f(BCLK)=10MHz,

CC1=5.0V

Flash memory

Erase

25

mA

V

Mask ROM

f(XCIN)=32kHz,

Low power dissipation mode,

ROM ⁽³⁾

µA

Power Supply Current

(V^CC1=4.0 to 5.5V)

I

CC

f(BCLK)=32kHz,

Low power dissipation mode,

RAM ⁽³⁾

Flash memory

25

µA

f(BCLK)=32kHz

Low power dissipation mode,

Flash memory ⁽³⁾

420

On-chip oscillation,

Wait mode

µA

50

f(BCLK)=32kHz,

7.5

Wait mode ⁽²⁾

,

Oscillation capacity High

Mask ROM

Flash memory

f(BCLK)=32kHz,

µA

Wait mode ⁽²⁾

Oscillation capacity Low

,

2.0

Stop mode,

6.0

20

µA

T

opr=25

Stop mode,

opr=85

Stop mode,

opr=125

°C

T

°C

TBD

T

°C

0.7

1.2

4

8

Voltage Down Detection Dissipation Current ⁽⁴⁾

Reset Area Detection Dissipation Current ⁽⁴⁾

µA

I

det4

det3

NOTES:

1. Referenced to VCC1=VCC2= 4.0 to 5.5V, VSS=0V at Topr = -40 to 85 °C / -40 to 125 °C, f(BCLK)=24MHz unless otherwise specified.

T version = -40 to 85 °C, V version = -40 to 125 °C

2. With one timer operated using fC32.

3. This indicates the memory in which the program to be executed exists.

4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).

I

det4: VC27 bit in VCR2 register

det3: VC26 bit in VCR2 register

page 76

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Timing Requirements

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless

otherwise specified)

Table 5.58 External Clock Input (XIN input)

Standard

Symbol

Parameter

External Clock Input Cycle Time

External Clock Input HIGH Pulse Width

External Clock Input LOW Pulse Width

External Clock Rise Time

Unit

Min.

62.5

25

Max.

t

c

ns

t

w(H

)

t

w(L)

25

t

r

15

t

f

External Clock Fall Time

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Timing Requirements

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless

otherwise specified)

Table 5.59 Timer A Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

ns

t

c(TA)

w(TAH)

w(TAL)

TAiIN Input Cycle Time

t

40

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.60 Timer A Input (Gating Input in Timer Mode)

Standard

Min. Max.

400

Symbol

Parameter

Unit

ns

t

c(TA)

w(TAH)

w(TAL)

TAiIN Input Cycle Time

t

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

200

t

Table 5.61 Timer A Input (External Trigger Input in One-shot Timer Mode)

Standard

Min. Max.

Symbol

Parameter

Unit

ns

200

100

t

c(TA)

w(TAH)

w(TAL)

TAiIN Input Cycle Time

t

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

Table 5.62 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t

w(TAH)

ns

TAiIN Input HIGH Pulse Width

TAiIN Input LOW Pulse Width

t

w(TAL)

Table 5.63 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

2000

1000

400

Max.

t

c(UP)

ns

TAiOUT Input Cycle Time

t

w(UPH)

TAiOUT Input HIGH Pulse Width

TAiOUT Input LOW Pulse Width

TAiOUT Input Setup Time

w(UPL)

su(UP-TIN)

400

t

h(TIN

-UP)

TAiOUT Input Hold Time

Table 5.64 Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

800

200

Max.

t

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

ns

TAiIN Input Cycle Time

TAiOUT Input Setup Time

TAiIN Input Setup Time

t

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Timing Requirements

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless

otherwise specified)

Table 5.65 Timer B Input (Counter Input in Event Counter Mode)

Standard

Symbol

Parameter

Unit

Min.

100

Max.

t

c(TB)

ns

TBiIN Input Cycle Time (counted on one edge)

t

w(TBH)

w(TBL)

c(TB)

TBiIN Input HIGH Pulse Width (counted on one edge)

TBiIN Input LOW Pulse Width (counted on one edge)

TBiIN Input Cycle Time (counted on both edges)

TBiIN Input HIGH Pulse Width (counted on both edges)

TBiIN Input LOW Pulse Width (counted on both edges)

40

t

200

80

t

w(TBH)

t

w(TBL)

80

Table 5.66 Timer B Input (Pulse Period Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t

c(TB)

TBiIN Input Cycle Time

ns

t

w(TBH)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

t

w(TBL)

Table 5.67 Timer B Input (Pulse Width Measurement Mode)

Standard

Symbol

Parameter

Unit

Min.

400

200

Max.

t

c(TB)

ns

TBiIN Input Cycle Time

t

w(TBH)

TBiIN Input HIGH Pulse Width

TBiIN Input LOW Pulse Width

t

w(TBL)

Table 5.68 A/D Trigger Input

Standard

Symbol

Parameter

Unit

Min.

1000

125

Max.

t

c(AD)

ns

ADTRG Input Cycle Time

t

w(ADL)

ADTRG Input LOW Pulse Width

Table 5.69 Serial I/O

Standard

Symbol

Parameter

Unit

Min.

200

100

Max.

t

c(CK)

w(CKH)

w(CKL)

ns

CLKi Input Cycle Time

CLKi Input HIGH Pulse Width

CLKi Input LOW Pulse Width

TXDi Output Delay Time

TXDi Hold Time

t

d(C-Q)

h(C-Q)

80

0

70

90

t

su(D-C)

RXDi Input Setup Time

RXDi Input Hold Time

t

h(C-D)

_______

Table 5.70 External Interrupt INTi Input

Standard

Symbol

Parameter

Unit

Min.

250

Max.

t

w(INH)

w(INL)

ns

INTi Input HIGH Pulse Width

INTi Input LOW Pulse Width

t

page 79

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

Switching Characteristics

o

(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = – 40 to 85 C (T version) / – 40 to 125 C (V version) unless

otherwise specified)

P0

P1

P2

30pF

P3

P4

P5

P6

P7

P8

P9

P10

Figure 5.23 Ports P0 to P10 Measurement Circuit

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REJ03B0001-0230Z

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

XIN input

tf

t

w(L)

t

w(H)

tr

tc

t

c(TA)

t

w(TAH)

TAiIN input

tw(TAL)

t

c(UP)

tw(UPH)

TAiOUT input

t

w(UPL)

TAiOUT input

(Up/down input)

During Event Counter Mode

TAiIN input

(When count on falling

edge is selected)

t

h(TIN–UP)

t

su(UP–TIN)

TAiIN input

(When count on rising

edge is selected)

Two-Phase Pulse Input in

Event Counter Mode

t

c(TA)

TAiIN input

tsu(TAIN-TAOUT)

t

su(TAIN-TAOUT)

t

su(TAOUT-TAIN)

TAiOUT input

t

su(TAOUT-TAIN)

t

c(TB)

tw(TBH)

TBiIN input

t

w(TBL)

t

c(AD)

t

w(ADL)

ADTRG input

Figure 5.24 Timing Diagram (1)

page 81

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5. Electrical Characteristics (M16C/62PT)

M16C/62P Group (M16C/62P, M16C/62PT)

VCC1 = VCC2 = 5V

tc(CK)

tw(CKH)

CLKi

tw(CKL)

th(C–Q)

TXDi

RXDi

tsu(D–C)

td(C–Q)

th(C–D)

tw(INL)

INTi input

tw(INH)

Figure 5.25 Timing Diagram (2)

page 82

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

Appendix 1. Package Dimensions

M16C/62P Group (M16C/62P, M16C/62PT)

Package Dimensions

Recommended

128P6Q-A

Plastic 128pin 14✕20mm body LQFP

EIAJ Package Code

JEDEC Code

Weight(g)

Lead Material

Cu Alloy

M

D

LQFP128-P-1420-0.50

–

HD

D

128

103

1

102

l2

Recommended Mount Pad

Dimension in Millimeters

Symbol

A

Min

1.4

0.05

–

Nom

1.5

0.125

1.4

Max

1.7

0.2

–

A

1

A2

b

0.17

0.105

13.9

19.9

–

15.8

21.8

0.35

–

0.45

–

0°

0.22

0.125

14.0

20.0

0.5

16.0

22.0

0.5

1.0

0.6

0.25

–

0.27

0.175

14.1

20.1

–

16.2

22.2

0.65

–

0.75

–

0.08

0.1

8°

c

D

E

e

65

38

HD

HE

39

64

L

1

A

L1

F

Lp

A3

x

e

y

–

L

b2

–

0.225

1.0

–

b

y

x

M

Detail F

I2

Lp

M

D

–

14.4

20.4

–

E

Recommended

100P6S-A

Plastic 100pin 14✕20mm body QFP

EIAJ Package Code

QFP100-P-1420-0.65

JEDEC Code

–

Weight(g)

1.58

Lead Material

Alloy 42

M

D

HD

D

100

81

1

80

I

2

Recommended Mount Pad

Dimension in Millimeters

Symbol

Min

–

0

–

0.25

0.13

13.8

19.8

–

16.5

22.5

0.4

–

0°

–

1.3

–

Nom

–

Max

3.05

0.2

–

0.4

0.2

14.2

20.2

–

17.1

23.1

0.8

–

0.13

0.1

10°

–

A

1

2

0.1

2.8

0.3

0.15

14.0

20.0

0.65

16.8

22.8

0.6

1.4

–

b

c

D

E

e

30

51

31

50

HD

A

L1

HE

L

L1

x

y

–

F

b2

0.35

–

14.6

20.6

e

b

L

x

M

I

2

–

Detail F

y

M

D

E

–

page 83

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

Appendix 1. Package Dimensions

M16C/62P Group (M16C/62P, M16C/62PT)

Recommended

80P6S-A

Plastic 80pin 14✕14mm body QFP

EIAJ Package Code

QFP80-P-1414-0.65

JEDEC Code

Weight(g)

1.11

Lead Material

Alloy 42

M

D

HD

D

80

61

1

60

I

2

Recommended Mount Pad

Dimension in Millimeters

Symbol

Min

–

0

–

0.25

0.13

13.8

–

16.5

0.4

–

0°

–

1.3

–

Nom

–

Max

3.05

0.2

–

0.4

0.2

14.2

–

17.1

0.8

–

0.13

0.1

10°

–

A

1

2

0.1

2.8

0.3

0.15

14.0

0.65

16.8

0.6

1.4

–

b

c

D

E

e

20

41

A

21

40

HD

L1

HE

L

L1

x

y

F

–

b

e

x

M

b2

0.35

–

14.6

y

L

I

2

–

Detail F

M

D

E

–

Recommended

100P6Q-A

Plastic 100pin 14✕14mm body LQFP

EIAJ Package Code

JEDEC Code

Weight(g)

0.63

Lead Material

Cu Alloy

MD

LQFP100-P-1414-0.50

–

HD

D

100

76

l2

Recommended Mount Pad

1

75

Dimension in Millimeters

Symbol

A

Min

–

Nom

–

Max

1.7

0.2

–

A1

0

0.1

A

2

–

1.4

b

0.13

0.105

13.9

–

0.18

0.125

14.0

0.5

0.28

0.175

14.1

–

c

D

E

e

25

51

H

L

D

15.8

0.3

–

0.45

–

0°

–

16.0

0.5

1.0

0.6

0.25

–

16.2

0.7

–

0.75

–

0.08

0.1

10°

–

26

50

E

A

L

1

L1

F

e

Lp

A3

x

y

–

b

x

y

L

M

b2

0.225

–

14.4

I

2

0.9

–

Lp

Detail F

M

D

E

page 84

Rev. 2.30 Sep 01, 2004

REJ03B0001-0230Z

of 84

M16C/62P Group (M16C/62P, M16C/62PT) Data Sheet

REVISION HISTORY

Rev.

Date

Description

Summary

Page

1.10 May 28, 2003

2

4-5

Table 1.1.1 is partly revised.

Table 1.1.2 and 1.1.3 is partly revised.

14-19 SFR is partly revised.

“Note 1” is partly revised.

22

23

Table 1.5.3 is partly revised.

Table 1.5.5 is partly revised.

Table 1.5.6 is added.

24

30

31

Table 1.5.9 is partly revised.

Notes 1 and 2 in Table 1.5.26 is partly revised.

Notes 1 in Table 1.5.27 is partly revised.

30-31 Note 3 is added to “Data output hold time (refers to BCLK)” in Table 1.5.26 and

1.5.27.

32

Note 4 is added to “th(ALE-AD)” in Table 1.5.28.

30-32 Switching Characteristics is partly revised.

36-39 th(WR-AD) and th(WR-DB) in Figure 1.5.5 to 1.5.8 is partly revised.

40-41 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.9 to 1.5.10 is

partly revised.

42

47

48

Note 2 is added to Table 1.5.29.

Notes 1 and 2 in Table 1.5.45 is partly revised.

Notes 1 in Table 1.5.46 is partly revised.

47-48 Note 3 is added to “Data output hold time (refers to BCLK)” in Table 1.5.45 and

1.5.46.

49

Note 4 is added to “th(ALE-AD)” in Table 1.5.47.

47-49 Switching Characteristics is partly revised.

53-56 th(WR-AD) and th(WR-DB) in Figure 1.5.15 to 1.5.18 is partly revised.

57-58 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.19 to 1.5.20 is

partly revised.

-

Since high reliability version is added, a group name is revised.

M16C/62 Group (M16C/62P) → M16C/62 Group (M16C/62P, M16C/62PT)

Table 1.1 to 1.3 are revised.

2.00 Oct 29, 2003

2-4

Note 3 is partly revised.

6

Figure 1.2 Note5 is deleted.

7-9

11

Table 1.4 to 1.7 Product List is partly revised.

Table 1.8 and Figure 1.4 are added.

12-15 Figure 1.5 to 1.9 ZP is added.

17,19 Table 1.10 and 1.12 ZP is added to timer A.

18,20 Table 1.11 and 1.13 VCC1 is added to VREF.

30

Table 5.1 is revised.

31-32 Table 5.2 and 5.3 are revised.

33

Table 5.4 A-D Conversion Characteristics is revised.

Table 5.5 D-A Conversion Characteristics revised.

34,74 Table 5.6 to 5.7 and table 5.54 to 5.55 are revised.

36 Table 5.11 is revised.

38,55 Table 5.14 and 5.33 HLDA output deley time is deleted.

41 Figure 5.1 is partly revised.

41-43, Table 5.27 to 5.29 and table 5.46 to 48 HLDA output deley time is added.

58-60

44

Figure 5.2 Timing Diagram (1) XIN input is added.

A-1

M16C/62P Group (M16C/62P, M16C/62PT) Data Sheet

REVISION HISTORY

Rev.

Date

Description

Summary

Page

47-48 Figure 5.5 to 5.6 Read timing DB --> DBi

49-50 Figure 5.7 to 5.8 Write timing DB --> DBi

52

53

58

61

Figure 5.10 DB --> DBi

Table 5.30 is revised.

Figure 5.11 is partly revised.

Figure 5.12 Timing Diagram (1) XIN input is added.

64-65 Figure 5.15 to 5.16 Read timing DB --> DBi

66-67 Figure 5.17 to 5.18 Write timing DB --> DBi

69

Figure 5.20 DB --> DBi

70-85 Electrical Characteristics (M16C/62PT) is added.

2.10 Nov 07, 2003

8-9

23

71

72

16

Table 1.5 to 1.7 Product List is partly revised. Note 1 is deleted.

Table 3.1 is revised.

Table 5.50 is revised.

Table 5.51 is deleted.

Table 1.9 NOTE 3 VCC1 ≥ VCC2 --> VCC1 > VCC2

2.11 Jan 06, 2004

2.30 Sep 01, 2004

17-18 Table 1.10 to 1.11 NOTE 1 VCC1 ≥ VCC2 --> VCC1 > VCC2

31

12

Table 5.2 Power Supply Ripple Allowable Frequency Unit MHz --> kHz

Table 1.9 and Figure 1.5 are added.

18, 20 Table 1.11 to 1.13 are revised.

19,21 Table 1.12 to 1.14 are revised.

24

Figure 3.1 is partly revised.

Note 3 is added.

25

33

Note 6 is added.

Table 5.3 is revised.

Note 2 in Table 5.4 is added.

Table 5.5 to 5.6 is partly revised.

Table 5.8 is revised.

34

35

Table 5.9 is revised.

37

40

57

70

72

73

74

76

79

Table 5.11 is revised.

Table 5.24 is partly revised.

Table 5.43 is partly revised.

Table 5.48 is partly revised.

Table 5.50 is partly revised.

Table 5.53 is partly revised.

Table 5.55 is revised.

Table 5.57 is partly revised.

Table 5.69 is partly revised.

A-2


型号：	M30622SPGP-U5
厂家：	RENESAS TECHNOLOGY CORP
描述：	16-BIT, 24MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-100 时钟控制器微控制器 ISM频段微控制器和处理器外围集成电路
文件：	总87页 (文件大小：901K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M30622SPGP-U5 [RENESAS]

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