M30626MWP-XXXGP#U3 [RENESAS]
M30626MWP-XXXGP#U3;
| 型号： | M30626MWP-XXXGP#U3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | M30626MWP-XXXGP#U3 时钟 微控制器 外围集成电路 |
| 文件： | 总103页 (文件大小：1107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
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4.
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M16C/62P Group (M16C/62P, M16C/62PT)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
REJ03B0001-0241
Rev.2.41
Jan 10, 2006
1. Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it suitable for control of various OA, communication, and industrial equipment which requires high-
speed arithmetic/logic operations.
1.1
Applications
Audio, cameras, television, home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Please make sure your manual is the latest edition.
Rev.2.41 Jan 10, 2006 Page 1 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
1.2
Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
Table 1.1
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
Item
Performance
M16C/62P
CPU
Number of Basic Instructions
91 instructions
Minimum Instruction Execution 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
Time
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode
Address Space
Single-chip, memory expansion and microprocessor mode
1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
Memory Capacity
Port
See Table 1.4 to 1.5 Product List
Input/Output : 113 pins, Input : 1 pin
Peripheral
Function
Multifunction Timer
Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter
D/A Converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CRC Calculation Circuit
Watchdog Timer
Interrupt
CCITT-CRC
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level: 7 levels
Clock Generation Circuit
4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop Detection
Function
Stop detection of main clock oscillation, re-oscillation detection
function
Voltage Detection Circuit
Supply Voltage
Available (option(4)
)
Electric
Characteristics
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
Power Consumption
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
Flash memory
version
Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
Program and Erase Endurance 100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
-40 to 85°C (3)
Package
NOTES:
128-pin plastic mold LQFP
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006 Page 2 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.2
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item
Performance
M16C/62P
M16C/62PT(4)
CPU
Number of Basic Instructions
91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode
Single-chip, memory expansion
and microprocessor mode
Single-chip
Address Space
1 Mbyte (Available to 4 Mbytes by 1 Mbyte
memory space expansion function)
See Table 1.4 to 1.7 Product List
Input/Output : 87 pins, Input : 1 pin
Memory Capacity
Port
Peripheral
Function
Multifunction Timer
Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface
3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter
D/A Converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
Interrupt
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 8 sources, Software: 4 sources, Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Voltage Detection Circuit Available (option (5)
)
Absent
Electric
Supply Voltage
VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1=VCC2=4.0 to 5.5V
Characteristics
VCC1 (f(BCLK=24MHz)
(f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
Power Consumption
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz) 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz) 2.0 A (VCC1=VCC2=5V, f(XCIN)=32kHz,
1.8 A (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
wait mode) 0.8 A (VCC1=VCC2=5V, stop mode)
0.7 A (VCC1=VCC2=3V, stop mode)
Flash memory Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
µ
µ
µ
µ
5.0±0.5 V
version
Program and Erase
Endurance
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
-40 to 85°C (3)
T version : -40 to 85°C
V version : -40 to 125°C
Package
NOTES:
100-pin plastic mold QFP, LQFP
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Rev.2.41 Jan 10, 2006 Page 3 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.3
Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item
Performance
M16C/62P
M16C/62PT(4)
CPU
Number of Basic Instructions
91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode
Address Space
Memory Capacity
Port
Single-chip mode
1 Mbyte
See Table 1.4 to 1.7 Product List
Input/Output : 70 pins, Input : 1 pin
Peripheral
Function
Multifunction Timer
Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface
2 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
1 channel
Clock synchronous, I2C bus(1), IEBus(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter
D/A Converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits x 2 channels
2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer
Interrupt
15 bits x 1 channel (with prescaler)
Internal: 29 sources, External: 5 sources, Software: 4 sources, Priority level: 7 levels
Clock Generation Circuit 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop
Stop detection of main clock oscillation, re-oscillation detection function
Detection Function
Voltage Detection Circuit Available (option (4)
)
Absent
Electric
Characteristics
Supply Voltage
VCC1=3.0 to 5.5 V, (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz)
VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
14 mA (VCC1=5V, f(BCLK)=24MHz)
2.0µ
A (VCC1=5V, f(XCIN)=32kHz,
1.8µA (VCC1=3V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=5V, stop mode)
wait mode)
0.7µA (VCC1=3V, stop mode)
Flash memory Program/Erase Supply Voltage 3.3 ± 0.3V or 5.0 ± 0.5V
5.0 ± 0.5V
version
Program and Erase
Endurance
100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature
-20 to 85°C,
-40 to 85°C (3)
T version : -40 to 85°C
V version : -40 to 125°C
Package
NOTES:
80-pin plastic mold QFP
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the program and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Rev.2.41 Jan 10, 2006 Page 4 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
1.3
Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram.
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
<VCC2 ports>(4)
<VCC1 ports>(4)
Internal peripheral functions
Timer (16-bit)
A/D converter
System clock
generation circuit
(10 bits X 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Output (timer A): 5
Input (timer B): 6
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
Three-phase motor
control circuit
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Clock synchronous serial I/O
(8 bits X 2 channels)
M16C/60 series16-bit CPU core
Memory
ROM (1)
SB
R0H
R1H
R0L
R1L
Watchdog timer
(15 bits)
USP
ISP
R2
R3
RAM (2)
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
FB
D/A converter
(8 bits X 2 channels)
Multiplier
<VCC1 ports>(4)
<VCC2 ports>(4)
Port P12 Port P13
Port P11
Port P14
(3)
(3)
(3)
(3)
8
2
8
8
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Figure 1.1
M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram
Rev.2.41 Jan 10, 2006 Page 5 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
8
8
8
4
8
8
Port P0
Port P4
Port P6
Port P2
Port P3
Port P5
(4)
System clock
generation circuit
Internal peripheral functions
Timer (16-bit)
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
Output (timer A): 5
Input (timer B): 6
UART or
clock synchronous serial I/O (2 channels)
UART (1 channel)
(3)
Clock synchronous serial I/O
(8 bits X 2 channels)
CRC arithmetic circuit (CCITT )
(Polynomial : X16+X12+X5+1)
Memory
ROM (1)
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
R0H
R1H
R0L
R1L
SB
USP
ISP
R2
R3
DMAC
(2 channels)
RAM (2)
INTB
PC
FLG
A0
A1
FB
D/A converter
(8 bits X 2 channels)
Multiplier
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Figure 1.2
M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Rev.2.41 Jan 10, 2006 Page 6 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
1.4
Product List
Table 1.4 to 1.7 list the product list, Figure 1.3 shows the Type No., Memory Size, and Package, Table 1.8 lists the
Product Code of Flash Memory version and ROMless version for M16C/62P, and Table 1.9 lists the Product Code
of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and
ROM-less version for M16C/62P (Top View), and Figure 1.5 shows the Marking Diagram of Flash Memory
version for M16C/62PT (Top View) at the time of ROM order.
Table 1.4
Product List (1) (M16C/62P)
Type No. ROM Capacity RAM Capacity Package Type
As of Dec. 2005
(1)
Remarks
M30622M6P-XXXFP
M30622M6P-XXXGP
M30622M8P-XXXFP
M30622M8P-XXXGP
M30623M8P-XXXGP
M30622MAP-XXXFP
M30622MAP-XXXGP
M30623MAP-XXXGP
M30620MCP-XXXFP
M30620MCP-XXXGP
M30621MCP-XXXGP
M30622MEP-XXXFP
M30622MEP-XXXGP
M30623MEP-XXXGP
M30622MGP-XXXFP
M30622MGP-XXXGP
M30623MGP-XXXGP
M30624MGP-XXXFP
M30624MGP-XXXGP
M30625MGP-XXXGP
M30622MWP-XXXFP
M30622MWP-XXXGP
M30623MWP-XXXGP
M30624MWP-XXXFP
M30624MWP-XXXGP
M30625MWP-XXXGP
M30626MWP-XXXFP
M30626MWP-XXXGP
M30627MWP-XXXGP
48 Kbytes
4 Kbytes
PRQP0100JB-A
Mask ROM version
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
64 Kbytes
4 Kbytes
96 Kbytes
128 Kbytes
192 Kbytes
256 Kbytes
5 Kbytes
10 Kbytes
12 Kbytes
12 Kbytes
20 Kbytes
16 Kbytes
24 Kbytes
31 Kbytes
320 Kbytes
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
Rev.2.41 Jan 10, 2006 Page 7 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.5
Product List (2) (M16C/62P)
As of Dec. 2005
RAM
Capacity
16 Kbytes
(1)
Type No.
ROM Capacity
384 Kbytes
Package Type
Remarks
M30622MHP-XXXFP
M30622MHP-XXXGP
M30623MHP-XXXGP
M30624MHP-XXXFP
M30624MHP-XXXGP
M30625MHP-XXXGP
M30626MHP-XXXFP
M30626MHP-XXXGP
M30627MHP-XXXGP
M30626MJP-XXXFP
M30626MJP-XXXGP (D)
M30627MJP-XXXGP (D)
M30622F8PFP
M30622F8PGP
M30623F8PGP
M30620FCPFP
M30620FCPGP
M30621FCPGP
(3)
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0080JA-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PLQP0128KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
PRQP0100JB-A
PLQP0100KB-A
Mask ROM version
24 Kbytes
31 Kbytes
31 Kbytes
(D) 512 Kbytes
64K+4 Kbytes 4 Kbytes
128K+4 Kbytes 10 Kbytes
Flash memory
(2)
version
(D) 256K+4 Kbytes 20 Kbytes
(D)
M3062LFGPFP
M3062LFGPGP
M30625FGPGP
M30626FHPFP
M30626FHPGP
M30627FHPGP
M30626FJPFP
M30626FJPGP
M30627FJPGP
M30622SPFP
M30622SPGP
M30620SPFP
M30620SPGP
M30624SPFP
M30624SPGP
M30626SPFP
M30626SPGP
(3)
384K+4 Kbytes 31 Kbytes
512K+4 Kbytes 31 Kbytes
−
4 Kbytes
ROM-less version
10 Kbytes
20 Kbytes
31 Kbytes
(D) −
(D)
(D)
(D)
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
3. Please use M3062LFGPFP and M3062LFGPGP for your new system instead of M30624FGPFP
and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good
for M30624FGPFP and M30624FGPGP.
M30624FGPFP
M30624FGPGP
256K+4 Kbytes 20 Kbytes
PRQP0100JB-A Flash memory version
PLQP0100KB-A
Rev.2.41 Jan 10, 2006 Page 8 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.6
Product List (3) (T version (M16C/62PT))
As of Dec. 2005
RAM
Capacity
(1)
Type No.
ROM Capacity
Package Type
Remarks
M3062CM6T-XXXFP (D) 48 Kbytes
M3062CM6T-XXXGP (D)
4 Kbytes PRQP0100JB-A Mask ROM T Version
version
(Highreliability
PLQP0100KB-A
PRQP0080JA-A
85°C version)
M3062EM6T-XXXGP (P)
M3062CM8T-XXXFP (D) 64 Kbytes
M3062CM8T-XXXGP (D)
4 Kbytes PRQP0100JB-A
PLQP0100KB-A
M3062EM8T-XXXGP (P)
PRQP0080JA-A
M3062CMAT-XXXFP (D) 96 Kbytes
M3062CMAT-XXXGP (D)
5 Kbytes PRQP0100JB-A
PLQP0100KB-A
M3062EMAT-XXXGP (P)
PRQP0080JA-A
M3062AMCT-XXXFP (D) 128 Kbytes
M3062AMCT-XXXGP (D)
10 Kbytes PRQP0100JB-A
PLQP0100KB-A
M3062BMCT-XXXGP (P)
PRQP0080JA-A
M3062CF8TFP
M3062CF8TGP
M3062AFCTFP
M3062AFCTGP
M3062BFCTGP
M3062JFHTFP
M3062JFHTGP
(D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A Flash
memory
version
PLQP0100KB-A
(2)
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
(D)
(P)
PLQP0100KB-A
PRQP0080JA-A
(D) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
(D) PLQP0100KB-A
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006 Page 9 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.7
Product List (4) (V version (M16C/62PT))
As of Dec. 2005
RAM
Capacity
(1)
Type No.
ROM Capacity
Package Type
Remarks
M3062CM6V-XXXFP (P) 48 Kbytes
M3062CM6V-XXXGP (P)
4 Kbytes PRQP0100JB-A Mask ROM V Version
version
(High reliability
PLQP0100KB-A
PRQP0080JA-A
125°C version)
M3062EM6V-XXXGP (P)
M3062CM8V-XXXFP (P) 64 Kbytes
M3062CM8V-XXXGP (P)
4 Kbytes PRQP0100JB-A
PLQP0100KB-A
M3062EM8V-XXXGP (P)
PRQP0080JA-A
M3062CMAV-XXXFP (P) 96 Kbytes
M3062CMAV-XXXGP (P)
5 Kbytes PRQP0100JB-A
PLQP0100KB-A
M3062EMAV-XXXGP (P)
PRQP0080JA-A
M3062AMCV-XXXFP (D) 128 Kbytes
M3062AMCV-XXXGP (D)
10 Kbytes PRQP0100JB-A
PLQP0100KB-A
M3062BMCV-XXXGP (P)
PRQP0080JA-A
M3062AFCVFP
M3062AFCVGP
M3062BFCVGP
M3062JFHVFP
M3062JFHVGP
(D) 128K+4 Kbytes 10 Kbytes PRQP0100JB-A Flash
memory
version
(D)
(P)
PLQP0100KB-A
PRQP0080JA-A
(2)
(P) 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
(P) PLQP0100KB-A
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Rev.2.41 Jan 10, 2006 Page 10 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Type No.
M 3 0 6 2 6 M H P - X X X F P
Package type:
FP : Package PRQP0100JB-A (100P6S-A)
GP : Package PRQP0080JA-A (80P6S-A),
PLQP0100KB-A (100P6Q-A),
PLQP0128KB-A (128P6Q-A),
ROM No.
Omitted for flash memory version and
ROMless version
Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)
ROM capacity:
G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes
Memory type:
M: Mask ROM version
F: Flash memory version
S: ROM-less version
Shows RAM capacity, pin count, etc
Numeric, Alphabet (L) : M16C/62P
Alphabet (L is excluded.) : M16C/62PT
M16C/62(P) Group
M16C Family
Figure 1.3
Type No., Memory Size, and Package
Rev.2.41 Jan 10, 2006 Page 11 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.8
Product Code of Flash Memory version and ROMless version for M16C/62P
Internal ROM
(User ROM Area Without Block A,
Block 1)
Internal ROM
(Block A, Block 1)
Operating
Ambient
Temperature
Product
Code
Package
Program
Temperature
and Erase
Range
Program
and Erase
Endurance
Temperature
Range
Endurance
Flash memory
Version
D3
D5
D7
D9
U3
U5
U7
U9
D3
D5
U3
U5
Lead-
included
100
1,000
100
0°C to 60°C
100
0°C to 60°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
-40°C to 85°C
-20°C to 85°C
10,000
100
-40°C to 85°C
-20°C to 85°C
0°C to 60°C
Lead-free
1,000
10,000
-40°C to 85°C
-20°C to 85°C
−
ROM-less
version
Lead-
included
−
−
−
−
−
−
Lead-free
−
M1 6 C
M3 0 6 2 6 F H P F P
B D 5
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Chip version and product code
B
: Shows chip version.
Henceforth, whenever it changes a version, it continues with B, C, and D.
X X X X X X X
D5 : Shows Product code. (See table 1.8 Product Code)
Date code seven digits
The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.
Figure 1.4
Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View)
Rev.2.41 Jan 10, 2006 Page 12 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.9
Product Code of Flash Memory version for M16C/62PT
Internal ROM
(User ROM Area
Without Block A, Block 1)
Internal ROM
(Block A, Block 1)
Operating
Ambient
Temperature
Product
Code
Package
Program
Temperature
and Erase
Range
Program
and Erase
Endurance
Temperature
Range
Endurance
Flash
memory
Version
T
V
T
V
T
V
T
V
Version
Version
Version
Version
Version
Version
Version
Version
B
B7
U
Lead-
included
100
1,000
100
0°C to 60°C
100
0°C to 60°C -40°C to 85°C
-40°C to 125°C
10,000 -40°C to 85°C -40°C to 85°C
-40°C to 125°C -40°C to 125°C
Lead-free
100
0°C to 60°C -40°C to 85°C
-40°C to 125°C
U7
1,000
10,000 -40°C to 85°C -40°C to 85°C
-40°C to 125°C -40°C to 125°C
M1 6 C
M3 0 6 2 J F HT F P
Y YY X X X X X XX
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits
Product code. (See table 1.9 Product Code)
“
” : Product code “B”
“ P B F ” : Product code “U”
“ B 7
“ U 7
” : Product code “B”
” : Product code “U7”
NOTES:
1.
: Blank
Figure 1.5
Marking Diagram of Flash Memory version for M16C/62PT (Top View)
Rev.2.41 Jan 10, 2006 Page 13 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
1.5
Pin Configuration
Figures 1.6 to 1.9 show the Pin Configuration (Top View).
PIN CONFIGURATION (top view)
102 101
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
P1_0/D8
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P11_7
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P12_5
P12_6
P12_7
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P13_0
P13_1
P13_2
<VCC2> (2)
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
P13_3
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P13_4
P13_5
P13_6
P13_7
M16C/62P Group (M16C/62P)
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
<VCC1> (2)
P10_0/AN0
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Package : PLQP0128KB-A (128P6Q-A)
Figure 1.6
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006 Page 14 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.10
Pin Characteristics for 128-Pin Package (1)
Pin No. Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin Bus Control Pin
1
2
VREF
AVCC
3
P9_7
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
P14_1
P14_0
SIN4
ADTRG
4
SOUT4
CLK4
ANEX1
ANEX0
DA1
5
6
TB4IN
7
TB3IN
TB2IN
TB1IN
TB0IN
DA0
8
SOUT3
SIN3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
CLK3
BYTE
CNVSS
XCIN
P8_7
P8_6
XCOUT
RESET
XOUT
VSS
XIN
VCC1
P8_5
P8_4
P8_3
P8_2
NMI
23
24
25
INT2
INT1
INT0
ZP
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P8_1
P8_0
P7_7
P7_6
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
P7_5
P7_4
TA2IN/W
TA2OUT/W
P7_3
P7_2
P7_1
P7_0
P6_7
TA1IN/V
CTS2/RTS2
CLK2
TA1OUT/V
TA0IN/TB5IN RXD2/SCL2
TA0OUT
TXD2/SDA2
TXD1/SDA1
VCC1
VSS
P6_6
P6_5
RXD1/SCL1
CLK1
P6_4
P6_3
P6_2
P6_1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
P6_0
CTS0/RTS0
P13_7
P13_6
P13_5
P13_4
P5_7
RDY/CLKOUT
Rev.2.41 Jan 10, 2006 Page 15 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.11
Pin Characteristics for 128-Pin Package (2)
Pin No. Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin Bus Control Pin
ALE
51
52
P5_6
P5_5
HOLD
HLDA
53
54
55
56
57
58
59
P5_4
P13_3
P13_2
P13_1
P13_0
P5_3
BCLK
P5_2
P5_1
RD
60
WRH/BHE
WRL/WR
61
62
63
64
65
P5_0
P12_7
P12_6
P12_5
P4_7
P4_6
P4_5
CS3
CS2
CS1
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
P4_4
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
P12_4
P12_3
P12_2
P12_1
P12_0
CS0
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
VCC2
VSS
P3_0
A8(/-/D7)
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
AN2_7
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
96
97
P1_7
P1_6
INT5
INT4
INT3
D15
D14
98
99
P1_5
P1_4
P1_3
D13
D12
D11
100
Rev.2.41 Jan 10, 2006 Page 16 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.12
Pin Characteristics for 128-Pin Package (3)
Pin No. Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin Bus Control Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
P1_2
P1_1
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
P11_7
P11_6
P11_5
P11_4
P11_3
P11_2
P11_1
P11_0
D10
D9
D8
AN0_7
D7
D6
D5
D4
D3
D2
D1
D0
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
120
121
122
P10_7 KI3
P10_6 KI2
P10_5 KI1
AN7
AN6
AN5
123
124
125
126
127
128
P10_4 KI0
P10_3
AN4
AN3
AN2
AN1
P10_2
P10_1
AVSS
P10_0
AN0
Rev.2.41 Jan 10, 2006 Page 17 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
1.Overview
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P4_4/CS0
P4_5/CS1
P4_6/CS2
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
<VCC2> (2)
M16C/62P Group
(M16C/62P, M16C/62PT)
P5_5/HOLD
P5_6/ALE
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
AVCC
P9_7/ADTRG/SIN4
<VCC1> (2)
P6_7/TXD1/SDA1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Package : PRQP0100JB-A (100P6S-A)
Figure 1.7
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006 Page 18 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
1.Overview
56 55 54 53 52 51
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
76
77
78
79
P1_2/D10
P1_1/D9
P1_0/D8
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P4_2/A18
P4_3/A19
P4_4/CS0
P4_5/CS1
P4_6/CS2
<VCC2> (2)
P0_7/AN0_7/D7
P0_6/AN0_6/D6
P0_5/AN0_5/D5
P0_4/AN0_4/D4
P0_3/AN0_3/D3
P0_2/AN0_2/D2
P0_1/AN0_1/D1
P0_0/AN0_0/D0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P4_7/CS3
P5_0/WRL/WR
P5_1/WRH/BHE
P5_2/RD
P5_3/BCLK
P5_4/HLDA
P5_5/HOLD
P5_6/ALE
M16C/62P Group
(M16C/62P, M16C/62PT)
P5_7/RDY/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
VREF
P6_7/TXD1/SDA1
AVCC
P9_7/ADTRG/SIN4
P9_6/ANEX1/SOUT4
P9_5/ANEX0/CLK4
P7_0/TXD2/SDA2/TA0OUT (1)
<VCC1> (2)
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
Package : PLQP0100KB-A (100P6Q-A)
Figure 1.8
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006 Page 19 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.13
Pin Characteristics for 100-Pin Package (1)
Pin No.
Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin Bus Control Pin
FP GP
1
2
99
P9_6
P9_5
P9_4
P9_3
P9_2
P9_1
P9_0
SOUT4
CLK4
ANEX1
ANEX0
DA1
100
TB4IN
3
4
1
2
TB3IN
TB2IN
TB1IN
TB0IN
DA0
5
3
SOUT3
SIN3
6
4
7
5
CLK3
8
6
BYTE
9
7
CNVSS
XCIN
10
11
12
13
14
15
16
17
8
P8_7
P8_6
9
XCOUT
10
RESET
11 XOUT
12 VSS
13 XIN
14 VCC1
15
P8_5
P8_4
P8_3
P8_2
NMI
18
19
20
16
17
18
INT2
INT1
INT0
ZP
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
P8_1
P8_0
P7_7
P7_6
TA4IN/U
TA4OUT/U
TA3IN
TA3OUT
P7_5
P7_4
TA2IN/W
TA2OUT/W
P7_3
P7_2
P7_1
P7_0
P6_7
P6_6
P6_5
TA1IN/V
CTS2/RTS2
CLK2
TA1OUT/V
TA0IN/TB5IN RXD2/SCL2
TA0OUT
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
P6_4
P6_3
P6_2
P6_1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
P6_0
P5_7
P5_6
CTS0/RTS0
39
40
41
42
43
44
45
46
47
48
49
50
37
38
39
40
41
42
43
44
45
46
47
48
RDY/CLKOUT
ALE
P5_5
HOLD
P5_4
P5_3
HLAD
BCLK
P5_2
P5_1
P5_0
P4_7
P4_6
P4_5
P4_4
RD
WRH/BHE
WRL/WR
CS3
CS2
CS1
CS0
Rev.2.41 Jan 10, 2006 Page 20 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.14
Pin Characteristics for 100-Pin Package (2)
Pin No.
Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin Bus Control Pin
FP GP
51
52
49
50
51
52
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
53
54
55
56
57
58
59
60 VCC2
61
P3_0
A8(/-/D7)
62 VSS
63
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
AN2_7
A7(/D7/D6)
A6(/D6/D5)
A5(/D5/D4)
A4(/D4/D3)
A3(/D3/D2)
A2(/D2/D1)
A1(/D1/D0)
A0(/D0/-)
64
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
65
66
67
68
69
70
71
P1_7
P1_6
INT5
INT4
INT3
D15
D14
74
72
75
76
77
78
73
74
75
76
P1_5
P1_4
P1_3
P1_2
D13
D12
D11
D10
79
77
P1_1
D9
80
81
82
83
84
85
86
87
88
89
78
79
80
81
82
83
84
85
86
87
P1_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
D8
D7
D6
D5
D4
D3
D2
D1
D0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
P10_7 KI3
P10_6 KI2
P10_5 KI1
AN7
AN6
AN5
90
91
88
89
92
93
94
95
96
97
98
90
P10_4 KI0
P10_3
AN4
AN3
AN2
AN1
91
92
P10_2
93
P10_1
94 AVSS
95
P10_0
P9_7
AN0
96 VREF
99
97 AVCC
100 98
SIN4
ADTRG
Rev.2.41 Jan 10, 2006 Page 21 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
PIN CONFIGURATION (top view)
1.Overview
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
35
34
33
32
31
30
29
61
62
63
64
65
66
67
68
69
70
71
P4_3
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P5_0
P5_1
P5_2
P5_3
P0_1/AN0_1
P0_0/AN0_0
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P5_4
P5_5
P5_6
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
M16C/62P Group
(M16C/62P, M16C/62PT)
72
73
74
28
27
26
25
24
23
22
21
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
75
76
77
78
79
80
P10_0/AN0
VREF
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_0/TXD2/SDA2/TA0OUT (1)
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
AVCC
P9_7/ADTRG/SIN4
P7_6/TA3OUT
P9_6/ANEX1/SOUT4
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
Package : PRQP0080JA-A (80P6S-A)
Figure 1.9
Pin Configuration (Top View)
Rev.2.41 Jan 10, 2006 Page 22 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.15
Pin Characteristics for 80-Pin Package (1)
Pin No. Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
ANEX0
Bus Control Pin
1
2
P9_5
P9_4
P9_3
P9_2
P9_0
CLK4
TB4IN
DA1
DA0
TB3IN
TB2IN
TB0IN
3
4
5
SOUT3
CLK3
CNVSS
(BYTE)
6
7
XCIN
P8_7
P8_6
8
XCOUT
9
RESET
XOUT
VSS
10
11
12
13
14
XIN
VCC1
P8_5
P8_4
P8_3
P8_2
NMI
15
16
17
INT2
INT1
INT0
ZP
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P8_1
P8_0
P7_7
P7_6
P7_1
P7_0
P6_7
P6_6
P6_5
TA4IN
TA4OUT
TA3IN
TA3OUT
TA0IN/TB5IN RXD2/SCL2
TA0OUT
TXD2/SDA2
TXD1/SDA1
RXD1/SCL1
CLK1
P6_4
P6_3
P6_2
P6_1
CTS1/RTS1/CTS0/CLKS1
TXD0/SDA0
RXD0/SCL0
CLK0
P6_0
P5_7
P5_6
CTS0/RTS0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CLKOUT
P5_5
P5_4
P5_3
P5_2
P5_1
P5_0
P4_3
P4_2
P4_1
P4_0
P3_7
P3_6
P3_5
P3_4
P3_3
P3_2
P3_1
Rev.2.41 Jan 10, 2006 Page 23 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.16
Pin Characteristics for 80-Pin Package (2)
Pin No. Control Pin Port
Interrupt Pin
Timer Pin
UART Pin
Analog Pin
AN2_7
Bus Control Pin
51
52
P3_0
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
P2_1
P2_0
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
AN2_6
AN2_5
AN2_4
AN2_3
AN2_2
AN2_1
AN2_0
AN0_7
AN0_6
AN0_5
AN0_4
AN0_3
AN0_2
AN0_1
AN0_0
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
P10_7 KI3
P10_6 KI2
P10_5 KI1
AN7
AN6
AN5
69
70
71
72
73
74
75
76
77
78
79
80
P10_4 KI0
P10_3
AN4
AN3
AN2
P10_2
P10_1
P10_0
AN1
AVSS
AN0
VREF
AVCC
P9_7
P9_6
SIN4
ADTRG
ANEX1
SOUT4
Rev.2.41 Jan 10, 2006 Page 24 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
1.6
Pin Description
Table 1.17
Signal Name
Pin Description (100-pin and 128-pin Version) (1)
Pin Name
I/O
Power
Description
(3)
Type Supply
Power supply
input
VCC1,VCC2
VSS
I
I
−
Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 ≥ VCC2.
(1, 2)
Analog power AVCC
VCC1 Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
supply input
Reset input
CNVSS
AVSS
RESET
CNVSS
I
I
VCC1 The microcomputer is in a reset state when applying “L” to the this pin.
VCC1 Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
External data
bus width
select input
BYTE
I
VCC1 Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
Bus control
pins
D0 to D7
D8 to D15
A0 to A19
I/O
I/O
VCC2 Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
(4)
VCC2 Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
O
VCC2 Output address bits (A0 to A19).
A0/D0 to
A7/D7
I/O
VCC2 Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
A1/D0 to
A8/D7
I/O
VCC2 Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
CS0 to CS3
O
O
VCC2 Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
WRL/WR
WRH/BHE
RD
VCC2 Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
• WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an external
memory space.
• WR, BHE and RD are selected
The WR signal becomes "L" by writing data in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE
O
I
VCC2 ALE is a signal to latch the address.
HOLD
VCC2 While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
HLDA
RDY
O
I
VCC2 In a hold state, HLDA outputs a "L" signal.
VCC2 While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
I : Input O : Output I/O : Input and output
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
interfaced using the different voltage as VCC1.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
Rev.2.41 Jan 10, 2006 Page 25 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.18
Pin Description (100-pin and 128-pin Version) (2)
Pin Name I/O Power
Type Supply
Signal Name
Description
(1)
Main clock
input
XIN
I
VCC1 I/O pins for the main clock generation circuit. Connect a ceramic
(3)
resonator or crystal oscillator between XIN and XOUT . To use
the external clock, input the clock from XIN and leave XOUT open.
Main clock
output
XOUT
O
VCC1
Sub clock input XCIN
I
VCC1 I/O pins for a sub clock oscillation circuit. Connect a crystal
(3)
oscillator between XCIN and XCOUT . To use the external clock,
input the clock from XCIN and leave XCOUT open.
Sub clock
output
XCOUT
O
VCC1
(2)
BCLK output
Clock output
BCLK
O
O
I
VCC2 Outputs the BCLK signal.
CLKOUT
VCC2 The clock of the same cycle as fC, f8, or f32 is outputted.
INT interrupt
input
INT0 to INT2
NT3 to INT5
NMI
VCC1 Input pins for the INT interrupt.
VCC2
I
I
NMI interrupt
input
VCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5
bit in the P8 register.
Key input
interrupt input
I
I/O
I
VCC1 Input pins for the key input interrupt.
KI0 to KI3
Timer A
TA0OUT to
TA4OUT
VCC1 These are timer A0 to timer A4 I/O pins. (however, output of
TA0OUT for the N-channel open drain output.)
TA0IN to
TA4IN
VCC1 These are timer A0 to timer A4 input pins.
ZP
I
I
VCC1 Input pin for the Z-phase.
Timer B
TB0IN to
TB5IN
VCC1 These are timer B0 to timer B5 input pins.
Three-phase
motor control
output
O
VCC1 These are Three-phase motor control output pins.
U, U, V, V,
W, W
Serial interface
I
VCC1 These are send control input pins.
VCC1 These are receive control output pins.
CTS0 to
CTS2
O
RTS0 to
RTS2
CLK0 to
CLK4
I/O
I
VCC1 These are transfer clock I/O pins.
VCC1 These are serial data input pins.
VCC1 These are serial data input pins.
RXD0 to
RXD2
SIN3, SIN4
I
TXD0 to
TXD2
O
VCC1 These are serial data output pins. (however, output of TXD2 for the
N-channel open drain output.)
SOUT3,
SOUT4
O
O
VCC1 These are serial data output pins.
CLKS1
VCC1 This is output pin for transfer clock output from multiple pins
function.
2
I C mode
SDA0 to
SDA2
I/O
I/O
VCC1 These are serial data I/O pins. (however, output of SDA2 for the N-
channel open drain output.)
SCL0 to
SCL2
VCC1 These are transfer clock I/O pins. (however, output of SCL2 for the
N-channel open drain output.)
I : Input O : Output I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. This pin function in M16C/62PT cannot be used.
3. Ask the oscillator maker the oscillation characteristic.
Rev.2.41 Jan 10, 2006 Page 26 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.19
Pin Description (100-pin and 128-pin Version) (3)
Pin Name I/O Power
Type Supply
Signal Name
Description
(1)
Reference
voltage input
VREF
I
VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
A/D converter AN0 to AN7,
I
VCC1 Analog input pins for the A/D converter.
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
I
VCC1 This is an A/D trigger input pin.
ADTRG
ANEX0
I/O
VCC1 This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
ANEX1
I
VCC1 This is the extended analog input pin for the A/D converter.
VCC1 This is the output pin for the D/A converter.
D/A converter DA0, DA1
O
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
I/O
VCC2 8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
P12_0 to
(2)
P12_7
,
P13_0 to
(2)
P13_7
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
I/O
VCC1
8-bit I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
P10_7,
P11_0 to
(2)
P11_7
P8_0 to P8_4,
P8_6, P8_7,
P14_0,
I/O
I
VCC1 I/O ports having equivalent functions to P0.
(2)
P14_1
Input port
P8_5
VCC1 Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I : Input O : Output I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used.
Rev.2.41 Jan 10, 2006 Page 27 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
(1)
Table 1.20
Pin Description (80-pin Version) (1)
Signal Name
Pin Name
I/O
Power
Description
Apply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin.
Type Supply
(1, 2)
Power supply
input
VCC1, VSS
I
I
−
Analog power AVCC
VCC1 Applies the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
supply input
Reset input
CNVSS
AVSS
RESET
I
I
VCC1 The microcomputer is in a reset state when applying “L” to the this pin.
CNVSS
(BYTE)
VCC1 Switches processor mode. Connect this pin to VSS to when after a
reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode. As for the BYTE pin of the 80-pin
versions, pull-up processing is performed within the microcomputer.
Main clock
input
XIN
I
VCC1 I/O pins for the main clock generation circuit. Connect a ceramic
(3)
resonator or crystal oscillator between XIN and XOUT . To use
the external clock, input the clock from XIN and leave XOUT
open.
Main clock
output
XOUT
O
VCC1
Sub clock input XCIN
I
VCC1 I/O pins for a sub clock oscillation circuit. Connect a crystal
(3)
oscillator between XCIN and XCOUT . To use the external
VCC1
Sub clock
output
XCOUT
O
clock, input the clock from XCIN and leave XCOUT open.
VCC2 The clock of the same cycle as fC, f8, or f32 is outputted.
VCC1 Input pins for the INT interrupt.
Clock output
CLKOUT
O
I
INT interrupt
input
INT0 to INT2
I
NMI interrupt
input
NMI
VCC1 Input pin for the NMI interrupt.
Key input
interrupt input
I
VCC1 Input pins for the key input interrupt.
KI0 to KI3
Timer A
TA0OUT,
TA3OUT,
TA4OUT
I/O
VCC1 These are Timer A0,Timer A3 and Timer A4 I/O pins. (however,
output of TA0OUT for the N-channel open drain output.)
TA0IN,TA3IN,
TA4IN
I
VCC1 These are Timer A0, Timer A3 and Timer A4 input pins.
ZP
I
I
VCC1 Input pin for the Z-phase.
Timer B
TB0IN, TB2IN
to TB5IN
VCC1 These are Timer B0, Timer B2 to Timer B5 input pins.
Serial interface
I
VCC1 These are send control input pins.
VCC1 These are receive control output pins.
VCC1 These are transfer clock I/O pins.
CTS0 to CTS1
RTS0 to RTS1
O
CLK0, CLK1,
CLK3, CLK4
I/O
RXD0 to RXD2
SIN4
I
I
VCC1 These are serial data input pins.
VCC1 This is serial data input pin.
TXD0 to TXD2
O
VCC1 These are serial data output pins. (however, output of TXD2 for
the N-channel open drain output.)
SOUT3,
SOUT4
O
O
VCC1 These are serial data output pins.
CLKS1
VCC1 This is output pin for transfer clock output from multiple pins
function.
2
I C mode
SDA0 to SDA2 I/O
SCL0 to SCL2 I/O
VCC1 These are serial data I/O pins. (however, output of SDA2 for the
N-channel open drain output.)
VCC1 These are transfer clock I/O pins. (however, output of SCL2 for
the N-channel open drain output.)
I : Input O : Output I/O : Input and output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.
3. Ask the oscillator maker the oscillation characteristic.
Rev.2.41 Jan 10, 2006 Page 28 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
1.Overview
Table 1.21
Pin Description (80-pin Version) (2)
Pin Name I/O Power
Type Supply
Signal Name
Description
(1)
Reference
voltage input
VREF
I
VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
A/D converter AN0 to AN7,
I
VCC1 Analog input pins for the A/D converter.
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
I
VCC1 This is an A/D trigger input pin.
ADTRG
ANEX0
I/O
VCC1 This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
ANEX1
I
VCC1 This is the extended analog input pin for the A/D converter.
VCC1 This is the output pin for the D/A converter.
D/A converter DA0, DA1
O
(1)
I/O port
P0_0 to P0_7,
P2_0 to P2_7,
P3_0 to P3_7,
P5_0 to P5_7,
P6_0 to P6_7,
P10_0 to
I/O
VCC1 8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
P10_7
P8_0 to P8_4,
P8_6, P8_7,
P9_0,
I/O
VCC1 I/O ports having equivalent functions to P0.
P9_2 to P9_7
P4_0 to P4_3,
P7_0, P7_1,
P7_6, P7_7
I/O
I
VCC1 I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
Input port
P8_5
VCC1 Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I : Input O : Output I/O : Input and output
NOTES:
1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the
direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Rev.2.41 Jan 10, 2006 Page 29 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
b31
b15
b8b7
b0
R2
R3
R0H
R1H
R0L
R1L
Data Registers (1)
R2
R3
A0
A1
FB
Address Registers (1)
Frame Base Registers (1)
b19
b15
b0
Interrupt Table Register
Program Counter
INTBH
INTBL
b19
b0
b0
PC
b15
USP
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b15
b0
b0
FLG
O B
Flag Register
b15
b8 b7
IPL
U
I
S
Z
D C
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTES:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
Central Processing Unit Register
2.1
Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Rev.2.41 Jan 10, 2006 Page 30 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
2. Central Processing Unit (CPU)
2.2
Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5
Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7
Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8
Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1
Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2
Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3
Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4
Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5
Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6
Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7
Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
Rev.2.41 Jan 10, 2006 Page 31 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
2. Central Processing Unit (CPU)
2.8.8
Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
Rev.2.41 Jan 10, 2006 Page 32 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
3.Memory
3. Memory
Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is mainly for
storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here.
Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instruction. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
In memory expansion and microprocessor modes, some areas are reserved for future use and cannot be used by users.
Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expansion and microprocessor
modes cannot be used
.
00000h
SFR
00400h
Internal RAM
XXXXXh
Reserved area (1)
FFE00h
0F000h
Internal ROM
(data area) (3)
0FFFFh
Special page
vector table
10000h
(3)
Internal RAM
Internal ROM
External area
Size
Address XXXXXh
013FFh
Size
Address YYYYYh
27000h
28000h
4 Kbytes
5 Kbytes
48 Kbytes
64 Kbytes
F4000h
F0000h
Reserved area
External area
FFFDCh
Undefined instruction
Overflow
BRK instruction
017FFh
96 Kbytes
128 Kbytes
192 Kbytes
E8000h
E0000h
D0000h
10 Kbytes
12 Kbytes
16 Kbytes
02BFFh
033FFh
043FFh
Address match
80000h
Reserved area (2)
Single step
20 Kbytes
053FFh
256 Kbytes
320 Kbytes
384 Kbytes
512 Kbytes
C0000h
B0000h
YYYYYh
Watchdog timer
24 Kbytes
31 Kbytes
063FFh
07FFFh
DBC
NMI
Reset
Internal ROM
A0000h
80000h
(program area) (5)
FFFFFh
FFFFFh
NOTES:
1. During memory expansion and microprocessor modes, can be used.
2. In memory expansion mode, can be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”
and the PM13 bit in the PM1 register is “1”.
5. When using the masked ROM version, write nothing to internal ROM area.
Figure 3.1
Memory Map
Rev.2.41 Jan 10, 2006 Page 33 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR
information.
(1)
Table 4.1
SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
Register
Symbol
After Reset
(2)
00000000b(CNVSS pin is “L”)
00000011b(CNVSS pin is “H”)
Processor Mode Register 0
PM0
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM1
CM0
CM1
CSR
AIER
PRCR
DBR
CM2
00001000b
01001000b
00100000b
00000001b
XXXXXX00b
XX000000b
00h
(6)
Chip Select Control Register
Address Match Interrupt Enable Register
Protect Register
(6)
Data Bank Register
(3)
Oscillation Stop Detection Register
0X000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
Address Match Interrupt Register 0
WDTS
WDC
RMAD0
XXh
00XXXXXXb
00h
00h
X0h
(4)
Address Match Interrupt Register 1
RMAD1
00h
00h
X0h
(5, 6)
Voltage Detection Register 1
Voltage Detection Register 2
Chip Select Expansion Control Register
PLL Control Register 0
VCR1
VCR2
CSE
00001000b
00h
00h
(5, 6)
(6)
PLC0
0001X010b
Processor Mode Register 2
Low Voltage Detection Interrupt Register
DMA0 Source Pointer
PM2
D4INT
SAR0
XXX00000b
00h
XXh
XXh
XXh
(6)
DMA0 Destination Pointer
DMA0 Transfer Counter
DMA0 Control Register
DMA1 Source Pointer
DMA1 Destination Pointer
DMA1 Transfer Counter
DMA1 Control Register
DAR0
XXh
XXh
XXh
TCR0
XXh
XXh
DM0CON
SAR1
00000X00b
XXh
XXh
XXh
DAR1
XXh
XXh
XXh
TCR1
XXh
XXh
DM1CON
00000X00b
NOTES:
1.
2.
3.
4.
5.
6.
The blank areas are reserved and cannot be accessed by users.
The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program.
This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
This register in M16C/62PT cannot be used.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 34 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
(1)
Table 4.2
SFR Information (2)
Address
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Register
Symbol
After Reset
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
INT3IC
XX00X000b
TB5IC
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
Timer B4 Interrupt Control Register, UART1 BUS Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register, UART0 BUS Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register, INT5 Interrupt Control Register
SI/O3 Interrupt Control Register, INT4 Interrupt Control Register
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
TB4IC, U1BCNIC
TB3IC, U0BCNIC
S4IC, INT5IC
S3IC, INT4IC
BCNIC
DM0IC
DM1IC
KUPIC
DMA1 Interrupt Control Register
Key Input Interrupt Control Register
A/D Conversion Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
ADIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
TA3IC
TA4IC
TB0IC
TB1IC
TB2IC
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
Timer A3 Interrupt Control Register
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
Timer B1 Interrupt Control Register
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT0IC
INT1IC
INT2IC
INT1 Interrupt Control Register
INT2 Interrupt Control Register
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 35 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
(1)
Table 4.3
SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
to
Register
Symbol
After Reset
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01C0h
to
(2)
Flash Identification Register
FIDR
FMR1
XXXXXX00b
0X00XX0Xb
(2)
Flash Memory Control Register 1
(2)
Flash Memory Control Register 0
Address Match Interrupt Register 2
FMR0
RMAD2
00000001b
00h
00h
XXh
XXXXXX00b
00h
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
AIER2
RMAD3
00h
XXh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
to
Peripheral Clock Select Register
PCLKR
00000011b
032Fh
0330h
0331h
0332h
0333h
0334h
0335h
0336h
0337h
0338h
0339h
033Ah
033Bh
033Ch
033Dh
033Eh
033Fh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. This register is included in the flash memory version.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 36 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
(1)
Table 4.4
SFR Information (4)
Address
0340h
0341h
0342h
0343h
0344h
0345h
0346h
0347h
0348h
0349h
034Ah
034Bh
034Ch
034Dh
034Eh
034Fh
0350h
0351h
0352h
0353h
0354h
0355h
0356h
0357h
0358h
0359h
035Ah
035Bh
035Ch
035Dh
035Eh
035Fh
0360h
0361h
0362h
0363h
0364h
0365h
0366h
0367h
0368h
0369h
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h
0371h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
Register
Symbol
After Reset
000XXXXXb
Timer B3, 4, 5 Count Start Flag
Timer A1-1 Register
TBSR
TA11
TA21
TA41
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
XXh
XXh
Timer A2-1 Register
Timer A4-1 Register
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 Interrupt Occurrence Frequency Set Counter
ICTB2
Timer B3 Register
Timer B4 Register
Timer B5 Register
TB3
TB4
TB5
XXh
XXh
XXh
XXh
XXh
XXh
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Factor Select Register 2
Interrupt Factor Select Register
SI/O3 Transmit/Receive Register
TB3MR
TB4MR
TB5MR
IFSR2A
IFSR
00XX0000b
00XX0000b
00XX0000b
00XXXXXXb
00h
S3TRR
XXh
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
S3C
01000000b
XXh
XXh
S3BRG
S4TRR
SI/O4 Control Register
SI/O4 Bit Rate Generator
S4C
01000000b
XXh
S4BRG
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
U2BRG
U2TB
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
XXh
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 37 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
(1)
Table 4.5
SFR Information (5)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Register
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
After Reset
Count Start Flag
00h
Clock Prescaler Reset Fag
One-Shot Start Flag
Trigger Select Register
Up-Down Flag
0XXXXXXXb
00h
00h
00h
(2)
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
Timer B0 Register
Timer B1 Register
Timer B2 Register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
U0MR
U0BRG
U0TB
00h
XXh
XXh
XXh
UART0 Transmit Buffer Register
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
00001000b
00XX0010b
XXh
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
UART1 Receive Buffer Register
U1C0
U1C1
U1RB
00001000b
00XX0010b
XXh
XXh
UART Transmit/Receive Control Register 2
UCON
X0000000b
DMA0 Request Factor Select Register
DMA1 Request Factor Select Register
CRC Data Register
DM0SL
DM1SL
CRCD
00h
00h
XXh
XXh
XXh
CRC Input Register
CRCIN
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. Bit 5 in the Up-down flag is “0” by reset. However, The values in these bits when read are indeterminate.
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 38 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
4. Special Function Register (SFR)
(1)
Table 4.6
SFR Information (6)
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
Register
Symbol
After Reset
A/D Register 0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
00000XXXb
00h
00h
D/A Register 1
DA1
00h
00h
D/A Control Register
DACON
(3)
(3)
Port P14 Control Register
Pull-Up Control Register 3
Port P0 Register
PC14
PUR3
P0
XX00XXXXb
00h
XXh
XXh
00h
Port P1 Register
P1
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
PD0
PD1
P2
00h
XXh
XXh
00h
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
00h
XXh
XXh
00h
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
PD4
PD5
P6
00h
XXh
XXh
00h
Port P7 Register
P7
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
PD6
PD7
P8
00h
XXh
XXh
00X00000b
00h
Port P9 Register
P9
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
Pull-Up Control Register 0
Pull-Up Control Register 1
PD8
PD9
P10
P11
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
XXh
XXh
00h
(3)
(3)
00h
(3)
XXh
XXh
00h
00h
00h
(3)
(3)
(3)
(2)
00000000b
00000010b
00h
(2)
03FEh
03FFh
Pull-Up Control Register 2
Port Control Register
PUR2
PCR
00h
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
2. At hardware reset 1 or hardware reset 2, the register is as follows:
• “00000000b” where “L” is inputted to the CNVSS pin
• “00000010b” where “H” is inputted to the CNVSS pin
At software reset, watchdog timer reset and oscillation stop detection reset, the register is as follows:
• “00000000b” where the PM01 to PM00 bits in the PM0 register are “00b” (single-chip mode).
• “00000010b” where the PM01 to PM00 bits in the PM0 register are “01b” (memory expansion mode) or “11b” (microprocessor mode).
3. These registers do not exist in M16C/62P (80-pin version), and M16C/62PT (80-pin version).
X : Nothing is mapped to this bit
Rev.2.41 Jan 10, 2006 Page 39 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
5. Electrical Characteristics
5.1
Electrical Characteristics (M16C/62P)
Table 5.1
Absolute Maximum Ratings
Symbol
VCC1, VCC2
VCC2
Parameter
Supply Voltage
Condition
VCC1=AVCC
VCC2
Rated Value
−0.3 to 6.5
Unit
V
Supply Voltage
−0.3 to VCC1+0.1
V
AVCC
Analog Supply Voltage
VCC1=AVCC
−0.3 to 6.5
V
VI
Input Voltage
−0.3 to VCC1+0.3 (1)
V
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
VREF, XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
−0.3 to VCC2+0.3 (1)
V
P7_0, P7_1
−0.3 to 6.5
−0.3 to VCC1+0.3 (1)
V
V
VO
Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
XOUT
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
−0.3 to VCC2+0.3 (1)
V
P7_0, P7_1
−0.3 to 6.5
300
V
Pd
Power Dissipation
−40°C<Topr≤85°C
mW
°C
Topr
Operating
Ambient
When the Microcomputer is Operating
−20 to 85 / −40 to 85
Temperature
Flash Program Erase
0 to 60
Tstg
Storage Temperature
−65 to 150
°C
NOTES:
1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in
80-pin version.
Rev.2.41 Jan 10, 2006 Page 40 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.2
Recommended Operating Conditions (1)
Standard
Unit
Symbol
Parameter
Min.
2.7
Typ.
5.0
VCC1
0
Max.
5.5
VCC1, VCC2 Supply Voltage (VCC1 ≥ VCC2)
V
V
V
V
V
AVCC
VSS
Analog Supply Voltage
Supply Voltage
AVSS
VIH
Analog Supply Voltage
0
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
HIGH Input
Voltage
0.8VCC2
0.8VCC2
0.5VCC2
0.8VCC1
VCC2
VCC2
VCC2
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
V
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
P7_0, P7_1
0.8VCC1
0
6.5
V
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
VIL
LOW Input
Voltage
0.2VCC2
P12_0 to P12_7, P13_0 to P13_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0
0
0.2VCC2
0.16VCC2
0.2VCC
V
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(data input during memory expansion and microprocessor mode)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
HIGH Peak
Output Current
−10.0
−5.0
10.0
5.0
mA
mA
mA
mA
HIGH Average
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
LOW Peak
Output Current
LOW Average
Output Current
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0, and P14_1 must be 80mA max. The total IOL(peak)
for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2
must be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports
P6, P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9, P10, P14_0, and P14_1 must be
−40mA max. Set Average Output Current to 1/2 of peak. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and
P14_1 must be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006 Page 41 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.3
Recommended Operating Conditions (2)
Standard
Unit
Symbol
f(XIN)
Parameter
Min.
0
Typ.
Max.
16
Main Clock Input Oscillation Frequency (2)
MHz
MHz
VCC1=3.0V to 5.5V
VCC1=2.7V to 3.0V
0
20×VCC1
−44
f(XCIN)
f(Ring)
f(PLL)
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency (2)
32.768
1
50
2
kHz
MHz
MHz
0.5
10
10
VCC1=3.0V to 5.5V
VCC1=2.7V to 3.0V
24
46.67×VCC1 MHz
−116
f(BCLK)
tSU(PLL)
CPU Operation Clock
0
24
20
50
MHz
ms
VCC1=5.5V
VCC1=3.0V
PLL Frequency Synthesizer Stabilization
Wait Time
ms
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 5.5V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. Relationship between main clock oscillation frequency, and supply voltage.
PLL clock oscillation frequency
Main clock input oscillation frequency
46.67 x VCC1-116MHz
24.0
20 x VCC1-44MHz
16.0
10.0
0.0
10.0
0.0
2.7
3.0
5.5
2.7
3.0
5.5
VCC1[V] (main clock: no division)
VCC1[V] (PLL clock oscillation)
Rev.2.41 Jan 10, 2006 Page 42 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.4
A/D Conversion Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ.
Max.
10
−
Resolution
VREF=VCC1
Bits
INL
Integral Non-Linearity
Error
10bit
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
±3
LSB
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
±5
LSB
LSB
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
3.3V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
LSB
8bit
VREF=VCC1=5V, 3.3V
±2
±3
LSB
LSB
−
Absolute Accuracy
10bit
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
±5
LSB
LSB
VREF= AN0 to AN7 input,
VCC1 AN0_0 to AN0_7 input,
=3.3V AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
±2
LSB
8bit
VREF=VCC1=5V, 3.3V
LSB
kΩ
−
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
3
DNL
±1
±3
±3
40
LSB
LSB
LSB
kΩ
−
−
Gain Error
RLADDER
tCONV
Ladder Resistance
VREF=VCC1
10
10-bit Conversion Time, Sample & Hold
Available
VREF=VCC1=5V, φAD=12MHz
2.75
µs
tCONV
8-bit Conversion Time, Sample & Hold
Available
VREF=VCC1=5V, φAD=12MHz
2.33
µs
tSAMP
VREF
VIA
Sampling Time
0.25
2.0
0
µs
V
Reference Voltage
Analog Input Voltage
VCC1
VREF
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. If VCC1 > VCC2, do not use AN0_0 to AN0_7 and AN2_0 to AN2_7 as analog input pins.
3. φAD frequency must be 12 MHz or less. And divide the fAD if VCC1 is less than 4.0V, and φAD frequency into 10 MHz or less.
4. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 3.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 3.
Rev.2.41 Jan 10, 2006 Page 43 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.5
D/A Conversion Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
4
Typ.
Max.
8
−
Resolution
Bits
%
−
Absolute Accuracy
1.0
3
tSU
RO
IVREF
Setup Time
µs
Output Resistance
10
20
1.5
kΩ
mA
Reference Power Supply Input Current
(NOTE 2)
NOTES:
1. Referenced to VCC1=VREF=3.3 to 5.5V, VSS=AVSS=0V at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006 Page 44 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Table 5.6
Flash Memory Version Electrical Characteristics (1) for 100 cycle products (D3, D5, U3,
U5)
Standard
Symbol
Parameter
Program and Erase Endurance (3)
Unit
Min.
100
Typ.
Max.
−
cycle
µs
µs
s
−
Word Program Time (VCC1=5.0V)
25
25
200
200
4
−
Lock Bit Program Time
−
Block Erase Time
(VCC1=5.0V)
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
0.3
0.3
0.5
0.8
−
4
s
−
4
s
−
4
s
−
Erase All Unlocked Blocks Time (2)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
4×n
15
s
tPS
−
µs
year
10
(6)
Table 5.7
Flash Memory Version Electrical Characteristics for 10,000 cycle products (D7, D9,
(7)
U7, U9) (Block A and Block 1
)
Standard
Typ.
Symbol
Parameter
Unit
Min.
Max.
−
−
−
−
Program and Erase Endurance (3, 8, 9)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
10,000 (4)
cycle
µs
25
25
µs
Block Erase Time
4-Kbyte block
0.3
s
(VCC1=5.0V)
tPS
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
15
µs
−
10
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (D3, D5, U3, U5) unless otherwise specified.
2. n denotes the number of block erases.
3. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
4. Maximum number of E/W cycles for which operation is guaranteed.
5. Topr = -40 to 85 °C (D3, D7, U3, U7) / -20 to 85 °C (D5, D9, U5, U9).
6. Referenced to VCC1 = 4.5 to 5.5V, 3.0 to 3.6V at Topr = -40 to 85 °C (D7, U7) / -20 to 85 °C (D9, U9) unless otherwise specified.
7. Table 5.7 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.6.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to
unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For
example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the
total number of times erasure is used.
9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command
at least three times until erase error disappears.
10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (D7, D9, U7 and U9).
11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 5.8
Flash Memory Version Program / Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C(D3, D5, U3, U5), Topr = -40 to 85 °C(D7, U7) / Topr =
-20 to 85 °C(D9, U9))
Flash Program, Erase Voltage
VCC1 = 3.3 V ± 0.3 V or 5.0 V ± 0.5 V
Flash Read Operation Voltage
VCC1=2.7 to 5.5 V
Rev.2.41 Jan 10, 2006 Page 45 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Table 5.9
Low Voltage Detection Circuit Electrical Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
VCC1=0.8V to 5.5V
Min.
3.3
2.2
0.3
Typ.
3.8
Max.
4.4
Vdet4
Low Voltage Detection Voltage (1)
Reset Level Detection Voltage (1, 2)
V
V
V
Vdet3
2.8
3.6
Vdet4-Vdet3
Electric potential difference of Low Voltage
Detection and Reset Level Detection
Vdet3s
Vdet3r
Low Voltage Reset Retention Voltage
Low Voltage Reset Release Voltage (3)
0.8
4.0
V
V
2.2
2.9
NOTES:
1. Vdet4 > Vdet3.
2. Where reset level detection voltage is less than 2.7 V, if the supply power voltage is greater than the reset level detection
voltage, the microcomputer operates with f(BCLK) ≤ 10MHz.
3. Vdet3r > Vdet3 is not guaranteed.
4. The voltage detection circuit is designed to use when VCC1 is set to 5V.
Table 5.10
Power Supply Circuit Timing Characteristics
Standard
Typ.
Symbol
td(P-R)
Parameter
Measuring Condition
VCC1=2.7V to 5.5V
Unit
ms
Min.
Max.
2
Time for Internal Power Supply Stabilization
During Powering-On
td(R-S)
td(W-S)
STOP Release Time
150
150
µs
µs
Low Power Dissipation Mode Wait Mode
Release Time
td(S-R)
td(E-A)
Brown-out Detection Reset (Hardware Reset 2) VCC1=Vdet3r to 5.5V
Release Wait Time
6 (1)
20
20
ms
Low Voltage Detection Circuit Operation Start
Time
VCC1=2.7V to 5.5V
µs
NOTES:
1. When VCC1 = 5V.
Rev.2.41 Jan 10, 2006 Page 46 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Recommended
operation voltage
td(P-R)
Time for Internal Power
Supply Stabilization During
Powering-On
VCC1
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
(b) Wait mode release
td(R-S)
STOP Release Time
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
td(S-R)
Low Voltage Detection
Reset (Hardware Reset 2)
Release Wait Time
Vdet3r
VCC1
td(S-R)
CPU clock
td(E-A)
VC26, VC27
Low Voltage Detection Circuit
Operation Start Time
Low Voltage
Detection Circuit
Stop
Operate
td(E-A)
Figure 5.1
Power Supply Circuit Timing Diagram
Rev.2.41 Jan 10, 2006 Page 47 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
(1)
Table 5.11
Electrical Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
HIGH
Output
Voltage
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOH=−5mA
VOH
VCC1−2.0
VCC1
(3)
(3)
V
V
(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−5mA
VCC2−2.0
VCC1−0.3
VCC2−0.3
VCC2
VCC1
VCC2
HIGH
Output
Voltage
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
OH=−200µA
VOH
(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−200µA
HIGH Output Voltage XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOH=−1mA
VOH
VCC1−2.0
VCC1−2.0
VCC1
VCC1
V
V
IOH=−0.5mA
HIGH Output Voltage XCOUT
With no load applied
With no load applied
IOL=5mA
2.5
1.6
LOW
Output
Voltage
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
VOL
2.0
2.0
(3)
(3)
V
V
(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=5mA
LOW
Output
Voltage
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
IOL=200µA
VOL
0.45
0.45
(2)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=200µA
LOW Output Voltage XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOL=1mA
VOL
2.0
V
V
IOL=0.5mA
2.0
LOW Output Voltage XCOUT
With no load applied
With no load applied
0
0
Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
VT+-VT-
0.2
0.2
1.0
2.5
V
V
Hysteresis
RESET
VT+-VT-
IIH
HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, VI=5V
(3)
Current
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
5.0
µA
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
LOW Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, VI=0V
IIL
(3)
Current
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
−5.0 µA
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
Pull-Up
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, VI=0V
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
RPULLUP
Resistance
(3)
30
50
170
kΩ
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
RfXIN
1.5
15
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise
specified.
2. Where the product is used at VCC1 = 5 V and VCC2 = 3 V, refer to the 3 V version value for the pin specified value on VCC2 port
side.
3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006 Page 48 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.12
Electrical Characteristics (2)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
f(BCLK)=24MHz
No division, PLL operation
ICC
Power Supply Current
In single-chip
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
Mask ROM
14
1
20
mA
mA
mA
mA
No division,
On-chip oscillation
other pins are VSS
f(BCLK)=24MHz,
No division, PLL operation
Flash
Memory
18
1.8
27
No division,
On-chip oscillation
f(BCLK)=10MHz,
VCC1=5.0V
Flash Memory
Program
15
25
mA
mA
f(BCLK)=10MHz,
VCC1=5.0V
Flash Memory
Erase
f(XCIN)=32kHz
Mask ROM
Low power dissipation
25
25
µA
µA
(3)
mode, ROM
f(BCLK)=32kHz
Flash Memory
Low power dissipation
(3)
mode, RAM
f(BCLK)=32kHz
Low power dissipation
mode, Flash Memory
420
50
µA
µA
µA
(3)
On-chip oscillation,
Wait mode
f(BCLK)=32kHz
(2)
Mask ROM
Flash Memory
Wait mode
,
7.5
Oscillation capability High
f(BCLK)=32kHz
(2)
Wait mode
,
2.0
0.8
µA
µA
Oscillation capability Low
Stop mode
Topr =25°C
3.0
Idet4
Idet3
Low Voltage Detection Dissipation Current (4)
Reset Area Detection Dissipation Current (4)
0.7
1.2
4
8
µA
µA
NOTES:
1. Referenced to VCC1=VCC2=4.2 to 5.5V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=24MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Rev.2.41 Jan 10, 2006 Page 49 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
(1)
Table 5.13
External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
25
15
15
tf
External Clock Fall Time
NOTES:
1. The condition is VCC1=VCC2=3.0 to 5.0V.
Table 5.14 Memory Expansion Mode and Microprocessor Mode
Standard
Symbol
Parameter
Unit
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data Input Access Time (for setting with no wait)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
Data Input Setup Time
(NOTE 1)
(NOTE 2)
(NOTE 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
40
30
40
0
tsu(RDY-BCLK)
RDY Input Setup Time
tsu(HOLD-BCLK) HOLD Input Setup Time
th(RD-DB)
Data Input Hold Time
RDY Input Hold Time
th(BCLK-RDY)
0
th(BCLK-HOLD) HOLD Input Hold Time
0
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 45[ns]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
(n – 0.5)x10
f(BCLK)
------------------------------------ – 45[ns]
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
(n – 0.5)x10
f(BCLK)
------------------------------------ – 45[ns]
n is “2” for 2-wait setting, “3” for 3-wait setting.
Rev.2.41 Jan 10, 2006 Page 50 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.15
Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
Max.
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
40
Table 5.16
Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.17
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.18
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
Table 5.19
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
tc(UP)
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
ns
ns
ns
ns
ns
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
Table 5.20
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
tsu(TAOUT-TAIN) TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006 Page 51 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.21
Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.22
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
Max.
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.23
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.24
A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
tc(AD)
1000
ns
ns
ADTRG Input Cycle Time
tw(ADL)
125
ADTRG input LOW Pulse Width
Table 5.25
Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
80
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
0
RXDi Input Setup Time
RXDi Input Hold Time
70
90
Table 5.26
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
250
Rev.2.41 Jan 10, 2006 Page 52 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.27
Memory Expansion and Microprocessor Modes (for setting with no wait)
Standard
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
0
th(WR-AD)
(NOTE 2)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
4
−4
0
ALE Signal Output Hold Time
See
Figure 5.2
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
0
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) (3)
HLDA Output Delay Time
4
(NOTE 1)
(NOTE 2)
th(WR-DB)
td(BCLK-HLDA)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 40[ns]
f(BCLK) is 12.5MHz or less.
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
R
C
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
DBi
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
30pF
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 5.2
Ports P0 to P14 Measurement Circuit
Rev.2.41 Jan 10, 2006 Page 53 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.28
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Standard
Symbol
Parameter
Unit
Min.
Max.
25
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
0
th(WR-AD)
(NOTE 2)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
15
25
25
40
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
4
-4
0
ALE Signal Output Hold Time
See
Figure 5.2
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
0
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)(3)
HLDA Output Delay Time
4
(NOTE 1)
(NOTE 2)
th(WR-DB)
td(BCLK-HLDA)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
(n – 0.5)x10
------------------------------------ – 40 [n s ]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
R
C
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
DBi
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Rev.2.41 Jan 10, 2006 Page 54 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.29
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Standard
Symbol
Parameter
Unit
Min.
Max.
25
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
25
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
25
25
40
RD Signal Output Hold Time
0
0
WR Signal Output Delay Time
WR Signal Output Hold Time
See
Figure 5.2
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
40
15
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
−4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdz(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
(n – 0.5)x10
f(BCLK)
------------------------------------ – 40 [n s ]
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 25[ns]
f(BCLK)
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 15[ns]
f(BCLK)
Rev.2.41 Jan 10, 2006 Page 55 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tf
tw(H)
tw(L)
tr
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.3
Timing Diagram (1)
Rev.2.41 Jan 10, 2006 Page 56 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
RXDi
tsu(D-C)
td(C-Q)
th(C-D)
tw(INL)
INTi input
tw(INH)
Figure 5.4
Timing Diagram (2)
Rev.2.41 Jan 10, 2006 Page 57 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA input
td(BCLK−HLDA)
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
Hi−Z
P5_0 to P5_2
(1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
· Measuring conditions :
· VCC1=VCC2=5V
· Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
· Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 5.5
Timing Diagram (3)
Rev.2.41 Jan 10, 2006 Page 58 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
25ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
tac1(RD-DB)
(0.5 × tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 × tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
0ns.min
25ns.max
WR, WRL,
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5 × tcyc-40)ns.min (0.5 × tcyc-10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.6
Timing Diagram (4)
Rev.2.41 Jan 10, 2006 Page 59 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
th(RD-AD)
0ns.min
th(BCLK-ALE)
-4ns.min
td(BCLK-ALE)
25ns.max
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
tac2(RD-DB)
(1.5 × tcyc-45)ns.max
Hi-Z
DBi
th(RD-DB)
0ns.min
tsu(DB-RD)
40ns.min
Write timing
BCLK
td(BCLK-CS)
25ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 × tcyc-10)ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR, WRL,
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
(0.5 × tcyc-40)ns.min
th(WR-DB)
(0.5 × tcyc-10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.7
Timing Diagram (5)
Rev.2.41 Jan 10, 2006 Page 60 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
25ns.max
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
25ns.max
RD
tac2(RD-DB)
(2.5×tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
th(WR-AD)
td(BCLK-ALE)
(0.5×tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
25ns.max
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
25ns.max
WR, WRL
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5×tcyc-10)ns.min
(1.5×tcyc-40)ns.min
1
Tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.8
Timing Diagram (6)
Rev.2.41 Jan 10, 2006 Page 61 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
th(BCLK-ALE)
25ns.max
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
25ns.max
RD
tac2(RD-DB)
(3.5×tcyc-45)ns.max
Hi-Z
DBi
tsu(DB-RD)
40ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
25ns.max
ADi
BHE
td(BCLK-ALE)
th(WR-AD)
th(BCLK-ALE)
25ns.max
(0.5×tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
25ns.max
WR, WRL
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5×tcyc-10)ns.min
(2.5×tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.9
Timing Diagram (7)
Rev.2.41 Jan 10, 2006 Page 62 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
4ns.min
tcyc
(0.5×tcyc-10)ns.min
25ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-25)ns.min
(0.5×tcyc-15)ns.min
ADi
/DBi
Address
Data input
Address
tdZ(RD-AD)
8ns.max
th(RD-DB)
0ns.min
tsu(DB-RD)
40ns.min
tac3(RD-DB)
(1.5×tcyc-45)ns.max
td(AD-RD)
0ns.min
th(BCLK-AD)
td(BCLK-AD)
25ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
th(BCLK-ALE)
25ns.max
−4ns.min
(0.5×tcyc-10)ns.min
ALE
RD
td(BCLK-RD)
25ns.max
th(BCLK-RD)
0ns.min
Write timing
BCLK
th(BCLK-CS)
4ns.min
th(WR-CS)
(0.5×tcyc-10)ns.min
tcyc
td(BCLK-CS)
25ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
40ns.max
ADi
/DBi
Address
Data output
Address
td(DB-WR)
th(WR-DB)
(0.5×tcyc-10)ns.min
td(AD-ALE)
(0.5×tcyc-25)ns.min
(1.5×tcyc-40)ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
25ns.max
td(AD-WR)
0ns.min
th(BCLK-ALE)
th(WR-AD)
(0.5×tcyc-10)ns.min
−4ns.min
ALE
td(BCLK-WR)
25ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.10
Timing Diagram (8)
Rev.2.41 Jan 10, 2006 Page 63 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
th(BCLK-CS)
4ns.min
(0.5×tcyc-10)ns.min
td(BCLK-CS)
25ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-15)ns.min
(0.5×tcyc-25)ns.min
ADi
/DBi
Data input
Address
th(RD-DB)
tdZ(RD-AD)
8ns.max
0ns.min
td(BCLK-AD)
th(BCLK-AD)
4ns.min
tac3(RD-DB)
(2.5×tcyc-45)ns.max
tsu(DB-RD)
40ns.min
td(AD-RD)
25ns.max
0ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
25ns.max
th(RD-AD)
(0.5×tcyc-10)ns.min
th(BCLK-ALE)
-4ns.min
ALE
RD
th(BCLK-RD)
0ns.min
td(BCLK-RD)
25ns.max
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
th(BCLK-CS)
4ns.min
td(BCLK-CS)
25ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
40ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
(0.5×tcyc-25)ns.min
td(DB-WR)
th(WR-DB)
(0.5×tcyc-10)ns.min
(2.5×tcyc-40)ns.min
td(BCLK-AD)
25ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(no multiplex)
td(BCLK-ALE)
25ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
25ns.max
WR, WRL
WRH
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=5V
· Input timing voltage : VIL=0.8V, VIH=2.0V
· Output timing voltage : VOL=0.4V, VOH=2.4V
Figure 5.11
Timing Diagram (9)
Rev.2.41 Jan 10, 2006 Page 64 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
(1)
Table 5.30
Electrical Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
HIGH Output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
IOH=−1mA
VOH
Voltage (3)
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
VCC1−0.5
VCC1
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−1mA (2)
VCC2−0.5
VCC2
HIGH Output Voltage XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOH=−0.1mA
VOH
VCC1−0.5
VCC1−0.5
VCC1
VCC1
V
V
IOH=−50µA
HIGH Output Voltage XCOUT
With no load applied
With no load applied
IOL=1mA
2.5
1.6
LOW Output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
VOL
Voltage (3)
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1
0.5
0.5
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=1mA (2)
LOW Output Voltage XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOL=0.1mA
VOL
0.5
V
V
IOL=50µA
0.5
LOW Output Voltage XCOUT
With no load applied
With no load applied
0
0
Hysteresis
Hysteresis
HOLD, RDY, TA0IN to TA4IN,
TB0IN to TB5IN, INT0 to INT5, NMI,
ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
VT+-VT-
0.2
0.2
0.8
V
V
VT+-VT-
IIH
(0.7)
1.8
4.0
RESET
HIGH Input
Current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
VI=3V
VI=0V
µA
µA
kΩ
XIN, RESET, CNVSS, BYTE
LOW Input
Current (3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
IIL
−4.0
XIN, RESET, CNVSS, BYTE
Pull-Up
Resistance
(3)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 VI=0V
to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to
P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7,
RPULLUP
50
100
500
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
RfXIN
3.0
25
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
NOTES:
1. Referenced to VCC1 = VCC2 = 2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(XIN)=10MHz no wait unless
otherwise specified.
2. VCC1 for the port P6 to P11 and P14, and VCC2 for the port P0 to P5 and P12 to P13
3. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006 Page 65 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.31
Electrical Characteristics (2)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
f(BCLK)=10MHz
No division
ICC
Power Supply Current
In single-chip
(VCC1=VCC2=2.7V to 3.6V) mode, the output
pins are open and
Mask ROM
8
1
11
mA
mA
mA
mA
No division,
On-chip oscillation
other pins are VSS
f(BCLK)=10MHz,
No division
Flash
Memory
8
13
No division,
On-chip oscillation
1.8
f(BCLK)=10MHz,
VCC1=3.0V
Flash Memory
Program
12
22
mA
mA
f(BCLK)=10MHz,
VCC1=3.0V
Flash Memory
Erase
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
Mask ROM
25
25
µA
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
Flash Memory
f(BCLK)=32kHz
Low power dissipation
420
45
µA
µA
µA
mode, Flash Memory (3)
On-chip oscillation,
Wait mode
f(BCLK)=32kHz
Mask ROM
Flash Memory
Wait mode (2)
,
6.0
Oscillation capability High
f(BCLK)=32kHz
Wait mode (2)
Oscillation capability Low
,
1.8
0.7
µA
µA
Stop mode
Topr =25°C
3.0
Idet4
Idet3
Low Voltage Detection Dissipation Current (4)
Reset Area Detection Dissipation Current (4)
0.6
0.4
4
2
µA
µA
NOTES:
1. Referenced to VCC1=VCC2=2.7 to 3.3V, VSS = 0V at Topr = −20 to 85°C / −40 to 85°C, f(BCLK)=10MHz unless otherwise
specified.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
4. Idet is dissipation current when the following bit is set to “1” (detection circuit enabled).
Idet4: VC27 bit in the VCR2 register
Idet3: VC26 bit in the VCR2 register
Rev.2.41 Jan 10, 2006 Page 66 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
(1)
Table 5.32
External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
Max.
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
(NOTE 2)
(NOTE 3)
(NOTE 3)
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
(NOTE 4)
(NOTE 4)
tf
External Clock Fall Time
NOTES:
1. The condition is VCC1=VCC2=2.7 to 3.0V.
2. Calculated according to the VCC1 voltage as follows:
10–6
--------------------------------------- [ns]
20 × VCC2 – 44
3. Calculated according to the VCC1 voltage as follows:
10–6
20 × VCC1 – 44
---------------------------------------
× 0.4 [ns]
4. Calculated according to the VCC1 voltage as follows:
–10 × VCC1 + 45 [ns]
Table 5.33
Memory Expansion Mode and Microprocessor Mode
Standard
Symbol
Parameter
Unit
Min.
Max.
tac1(RD-DB)
tac2(RD-DB)
tac3(RD-DB)
tsu(DB-RD)
Data Input Access Time (for setting with no wait)
Data Input Access Time (for setting with wait)
Data Input Access Time (when accessing multiplex bus area)
Data Input Setup Time
(NOTE 1)
(NOTE 2)
(NOTE 3)
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
40
50
0
tsu(RDY-BCLK)
RDY Input Setup Time
tsu(HOLD-BCLK) HOLD Input Setup Time
th(RD-DB)
Data Input Hold Time
RDY Input Hold Time
th(BCLK-RDY)
0
th(BCLK-HOLD) HOLD Input Hold Time
0
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 60[ns]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
(n – 0.5)x10
f(BCLK)
------------------------------------ – 60 [n s ]
n is ”2” for 1-wait setting, “3” for 2-wait setting and “4” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
(n – 0.5)x10
f(BCLK)
------------------------------------ – 60 [n s ]
n is “2” for 2-wait setting, “3” for 3-wait setting.
Rev.2.41 Jan 10, 2006 Page 67 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.34
Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
Max.
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
60
Table 5.35
Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.36
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
300
150
150
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.37
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
150
150
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
Table 5.38
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
3000
1500
1500
600
Max.
tc(UP)
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
ns
ns
ns
ns
ns
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
600
Table 5.39
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2
Max.
tc(TA)
TAiIN Input Cycle Time
µs
ns
ns
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
tsu(TAOUT-TAIN) TAiIN Input Setup Time
500
500
Rev.2.41 Jan 10, 2006 Page 68 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Timing Requirements
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.40
Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
150
60
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
60
300
120
120
tw(TBH)
tw(TBL)
Table 5.41
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
Max.
Max.
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.42
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
600
300
300
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.43
A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
tc(AD)
1500
ns
ns
ADTRG Input Cycle Time
tw(ADL)
200
ADTRG Input LOW Pulse Width
Table 5.44
Serial Interface
Standard
Symbol
Parameter
Unit
Min.
300
150
150
Max.
160
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
0
RXDi Input Setup Time
RXDi Input Hold Time
100
90
Table 5.45
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
380
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
380
Rev.2.41 Jan 10, 2006 Page 69 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.46
Memory Expansion and Microprocessor Modes (for setting with no wait)
Standard
Symbol
Parameter
Unit
Min.
Max.
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
0
th(WR-AD)
(NOTE 2)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
30
25
30
30
40
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
4
−4
0
ALE Signal Output Hold Time
See
Figure 5.12
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
0
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR) (3)
HLDA Output Delay Time
4
(NOTE 1)
(NOTE 2)
th(WR-DB)
td(BCLK-HLDA)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 40[ns]
f(BCLK) is 12.5MHz or less.
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
R
C
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
DBi
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1k Ω X In(1−0.2VCC2 / VCC2)
= 6.7ns.
P0
P1
P2
P3
30pF
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
Figure 5.12
Ports P0 to P14 Measurement Circuit
Rev.2.41 Jan 10, 2006 Page 70 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.47
Memory Expansion and Microprocessor Modes (for 1- to 3-wait setting and external
area access)
Standard
Symbol
Parameter
Unit
Min.
Max.
30
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
0
th(WR-AD)
(NOTE 2)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
30
25
30
30
40
Chip Select Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time
4
-4
0
ALE Signal Output Hold Time
See
Figure 5.12
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
WR Signal Output Hold Time
0
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK) (3)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)(3)
HLDA Output Delay Time
4
(NOTE 1)
(NOTE 2)
th(WR-DB)
td(BCLK-HLDA)
40
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
n is “1” for 1-wait setting, “2” for 2-wait setting
and “3” for 3-wait setting.
(BCLK) is 12.5MHz or less.
(n – 0.5)x10
------------------------------------ – 40 [n s ]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
R
C
Hold time of data bus is expressed in
t = −CR X ln (1−VOL / VCC2)
by a circuit of the right figure.
DBi
For example, when VOL = 0.2VCC2, C = 30pF, R = 1kΩ, hold time
of output ”L” level is
t = −30pF X 1kΩ X In(1−0.2VCC2 / VCC2)
= 6.7ns.
Rev.2.41 Jan 10, 2006 Page 71 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified)
Table 5.48
Memory Expansion and Microprocessor Modes (for 2- to 3-wait setting, external area
access and multiplex bus selection)
Standard
Symbol
Parameter
Unit
Min.
Max.
50
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
Address Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Output Hold Time (in relation to BCLK)
Address Output Hold Time (in relation to RD)
Address Output Hold Time (in relation to WR)
Chip Select Output Delay Time
4
(NOTE 1)
(NOTE 1)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
50
Chip Select Output Hold Time (in relation to BCLK)
Chip Select Output Hold Time (in relation to RD)
Chip Select Output Hold Time (in relation to WR)
RD Signal Output Delay Time
4
(NOTE 1)
(NOTE 1)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
40
40
50
RD Signal Output Hold Time
0
0
WR Signal Output Delay Time
WR Signal Output Hold Time
See
Figure 5.12
Data Output Delay Time (in relation to BCLK)
Data Output Hold Time (in relation to BCLK)
Data Output Delay Time (in relation to WR)
Data Output Hold Time (in relation to WR)
HLDA Output Delay Time
4
(NOTE 2)
(NOTE 1)
th(WR-DB)
td(BCLK-HLDA)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(AD-ALE)
td(AD-RD)
40
25
ALE Signal Output Delay Time (in relation to BCLK)
ALE Signal Output Hold Time (in relation to BCLK)
ALE Signal Output Delay Time (in relation to Address)
ALE Signal Output Hold Time (in relation to Address)
RD Signal Output Delay From the End of Address
WR Signal Output Delay From the End of Address
Address Output Floating Start Time
−4
(NOTE 3)
(NOTE 4)
0
0
td(AD-WR)
tdz(RD-AD)
8
NOTES:
1. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 10[ns]
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 50[ns]
f(BCLK)
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 40[ns]
f(BCLK)
4. Calculated according to the BCLK frequency as follows:
9
0.5x10
----------------------- – 15[ns]
f(BCLK)
Rev.2.41 Jan 10, 2006 Page 72 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
XIN input
tf
tw(H)
tw(L)
tr
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During Event Counter Mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-Phase Pulse Input in
Event Counter Mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.13
Timing Diagram (1)
Rev.2.41 Jan 10, 2006 Page 73 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
RXDi
tsu(D-C)
td(C-Q)
th(C-D)
tw(INL)
INTi input
tw(INH)
Figure 5.14
Timing Diagram (2)
Rev.2.41 Jan 10, 2006 Page 74 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(Effective for setting with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY−BCLK)
th(BCLK−RDY)
(Common to setting with wait and setting without wait)
BCLK
th(BCLK−HOLD)
tsu(HOLD−BCLK)
HOLD input
HLDA output
td(BCLK−HLDA)
td(BCLK−HLDA)
P0, P1, P2,
P3, P4,
Hi−Z
P5_0 to P5_2 (1)
NOTES:
1. These pins are set to high-impedance regardless of the input level of the
BYTE pin, PM06 bit in PM0 register and PM11 bit in PM1 register.
Measuring conditions :
· VCC1=VCC2=3V
· Input timing voltage : Determined with VIL=0.6V, VIH=2.4V
· Output timing voltage : Determined with VOL=1.5V, VOH=1.5V
Figure 5.15
Timing Diagram (3)
Rev.2.41 Jan 10, 2006 Page 75 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for setting with no wait)
Read timing
BCLK
td(BCLK-CS)
th(BCLK-CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(RD-AD)
0ns.min
ALE
RD
td(BCLK-RD)
30ns.max
th(BCLK-RD)
0ns.min
tac1(RD-DB)
(0.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
BCLK
td(BCLK-CS)
30ns.max
th(BCLK-CS)
4ns.min
CSi
tcyc
td(BCLK-AD)
30ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
30ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5 × tcyc-10)ns.min
ALE
td(BCLK-WR)
th(BCLK-WR)
0ns.min
30ns.max
WR, WRL,
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
th(WR-DB)
(0.5 × tcyc-10)ns.min
td(DB-WR)
(0.5 × tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.16
Timing Diagram (4)
Rev.2.41 Jan 10, 2006 Page 76 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 1-wait setting and external area access)
Read timing
BCLK
td(BCLK−CS)
th(BCLK−CS)
30ns.max
4ns.min
CSi
tcyc
td(BCLK−AD)
30ns.max
th(BCLK−AD)
4ns.min
ADi
BHE
th(RD−AD)
th(BCLK−ALE)
−4ns.min
td(BCLK−ALE)
0ns.min
30ns.max
ALE
RD
td(BCLK−RD)
30ns.max
th(BCLK−RD)
0ns.min
tac2(RD−DB)
(1.5 × tcyc−60)ns.max
Hi−Z
DBi
th(RD−DB)
0ns.min
tsu(DB−RD)
50ns.min
Write timing
BCLK
td(BCLK−CS)
30ns.max
th(BCLK−CS)
4ns.min
CSi
tcyc
td(BCLK−AD)
30ns.max
th(BCLK−AD)
4ns.min
ADi
BHE
td(BCLK−ALE)
30ns.max
th(BCLK−ALE)
−4ns.min
th(WR−AD)
(0.5 × tcyc−10)ns.min
ALE
td(BCLK−WR)
th(BCLK−WR)
30ns.max
0ns.min
WR,WRL,
WRH
td(BCLK−DB)
th(BCLK−DB)
40ns.max
4ns.min
Hi−Z
DBi
td(DB−WR)
(0.5 × tcyc−40)ns.min
th(WR−DB)
(0.5 × tcyc−10)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.17
Timing Diagram (5)
Rev.2.41 Jan 10, 2006 Page 77 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(for 2-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
30ns.max
th(RD-AD)
0ns.min
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
30ns.max
RD
tac2(RD-DB)
(2.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
30ns.max
th(WR-AD)
th(BCLK-ALE)
-4ns.min
(0.5 × tcyc-10)ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
30ns.max
WR, WRL
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5 × tcyc-10)ns.min
(1.5 × tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.18
Timing Diagram (6)
Rev.2.41 Jan 10, 2006 Page 78 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1 = VCC2 = 3V
Memory Expansion Mode, Microprocessor Mode
(for 3-wait setting and external area access)
Read timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
th(RD-AD)
0ns.min
30ns.max
th(BCLK-ALE)
-4ns.min
ALE
th(BCLK-RD)
0ns.min
td(BCLK-RD)
30ns.max
RD
tac2(RD-DB)
(3.5 × tcyc-60)ns.max
Hi-Z
DBi
tsu(DB-RD)
50ns.min
th(RD-DB)
0ns.min
Write timing
tcyc
BCLK
th(BCLK-CS)
4ns.min
td(BCLK-CS)
30ns.max
CSi
th(BCLK-AD)
4ns.min
td(BCLK-AD)
30ns.max
ADi
BHE
td(BCLK-ALE)
th(WR-AD)
30ns.max
th(BCLK-ALE)
(0.5 × tcyc-10)ns.min
-4ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
30ns.max
WR, WRL
WRH
td(BCLK-DB)
40ns.max
th(BCLK-DB)
4ns.min
Hi-Z
DBi
td(DB-WR)
th(WR-DB)
(0.5 × tcyc-10)ns.min
(2.5 × tcyc-40)ns.min
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.19
Timing Diagram (7)
Rev.2.41 Jan 10, 2006 Page 79 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(For 2-wait setting, external area access and multiplex bus selection)
Read timing
BCLK
th(BCLK-CS)
td(BCLK-CS)
th(RD-CS)
4ns.min
tcyc
(0.5×tcyc-10)ns.min
40ns.max
CSi
td(AD-ALE)
th(ALE-AD)
(0.5×tcyc-40)ns.min
(0.5×tcyc-15)ns.min
ADi
/DBi
Address
Address
Data input
tdZ(RD-AD)
8ns.max
th(RD-DB)
0ns.min
tsu(DB-RD)
50ns.min
tac3(RD-DB)
(1.5×tcyc-60)ns.max
td(AD-RD)
0ns.min
th(BCLK-AD)
td(BCLK-AD)
40ns.max
4ns.min
ADi
BHE
td(BCLK-ALE)
th(BCLK-ALE)
-4ns.min
th(RD-AD)
40ns.max
(0.5×tcyc-10)ns.min
ALE
RD
td(BCLK-RD)
40ns.max
th(BCLK-RD)
0ns.min
Write timing
BCLK
th(BCLK-CS)
4ns.min
tcyc
th(WR-CS)
(0.5×tcyc-10)ns.min
td(BCLK-CS)
40ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
50ns.max
Address
ADi
/DBi
Address
Data output
td(DB-WR)
th(WR-DB)
td(AD-ALE)
(0.5×tcyc-40)ns.min
(1.5×tcyc-50)ns.min
(0.5×tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
td(BCLK-ALE)
40ns.max
td(AD-WR)
0ns.min
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
ALE
td(BCLK-WR)
40ns.max
th(BCLK-WR)
0ns.min
WR,WRL,
WRH
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.20
Timing Diagram (8)
Rev.2.41 Jan 10, 2006 Page 80 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=3V
Memory Expansion Mode, Microprocessor Mode
(For 3-wait setting, external area access and multiplex bus selection)
Read timing
tcyc
BCLK
th(RD-CS)
th(BCLK-CS)
6ns.min
(0.5×tcyc-10)ns.min
td(BCLK-CS)
40ns.max
CSi
td(AD-ALE)
(0.5×tcyc-40)ns.min
th(ALE-AD)
(0.5×tcyc-15)ns.min
ADi
Data input
Address
/DBi
th(RD-DB)
tdZ(RD-AD)
8ns.max
0ns.min
td(BCLK-AD)
40ns.max
tac3(RD-DB)
tsu(DB-RD)
50ns.min
th(BCLK-AD)
4ns.min
td(AD-RD)
0ns.min
(2.5×tcyc-60)ns.max
ADi
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max
th(RD-AD)
th(BCLK-ALE)
(0.5×tcyc-10)ns.min
-4ns.min
ALE
RD
th(BCLK-RD)
0ns.min
td(BCLK-RD)
40ns.max
Write timing
tcyc
BCLK
th(WR-CS)
(0.5×tcyc-10)ns.min
th(BCLK-CS)
4ns.min
td(BCLK-CS)
40ns.max
CSi
th(BCLK-DB)
4ns.min
td(BCLK-DB)
50ns.max
ADi
/DBi
Address
Data output
td(AD-ALE)
td(DB-WR)
th(WR-DB)
(0.5×tcyc-40)ns.min
(2.5×tcyc-50)ns.min
(0.5×tcyc-10)ns.min
td(BCLK-AD)
40ns.max
th(BCLK-AD)
4ns.min
ADi
BHE
(No multiplex)
td(BCLK-ALE)
40ns.max
th(BCLK-ALE)
-4ns.min
th(WR-AD)
(0.5×tcyc-10)ns.min
td(AD-WR)
0ns.min
ALE
th(BCLK-WR)
0ns.min
td(BCLK-WR)
40ns.max
WR, WRL
WRH
1
tcyc=
f(BCLK)
Measuring conditions
· VCC1=VCC2=3V
· Input timing voltage : VIL=0.6V, VIH=2.4V
· Output timing voltage : VOL=1.5V, VOH=1.5V
Figure 5.21
Timing Diagram (9)
Rev.2.41 Jan 10, 2006 Page 81 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
5.2
Electrical Characteristics (M16C/62PT)
Table 5.49
Absolute Maximum Ratings
Symbol
VCC1, VCC2
AVCC
Parameter
Supply Voltage
Condition
Rated Value
−0.3 to 6.5
−0.3 to 6.5
Unit
V
VCC1=VCC2=AVCC
VCC1=VCC2=AVCC
Analog Supply Voltage
V
VI
Input Voltage
RESET, CNVSS, BYTE,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
VREF, XIN
−0.3 to VCC1+0.3 (1)
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
−0.3 to VCC2+0.3 (1)
−0.3 to 6.5
V
V
P7_0, P7_1
VO
Output Voltage P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P14_0, P14_1,
−0.3 to VCC1+0.3 (1)
V
XOUT
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
−0.3 to VCC2+0.3 (1)
V
P7_0, P7_1
−0.3 to 6.5
300
V
Pd
Power Dissipation
−40°C<Topr≤85°C
85°C<Topr≤125°C
mW
200
Topr
Operating
Ambient
Temperature
When the Microcomputer is Operating
Flash Program Erase
−40 to 85 / −40 to 125
(2)
°C
°C
0 to 60
Tstg
Storage Temperature
−65 to 150
NOTES:
1. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in
80-pin version.
2. T version = −40 to 85 °C, V version= −40 to 125 °C.
Rev.2.41 Jan 10, 2006 Page 82 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.50
Recommended Operating Conditions (1)
Standard
Unit
Symbol
Parameter
Min.
4.0
Typ.
5.0
VCC1
0
Max.
5.5
VCC1, VCC2 Supply Voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog Supply Voltage
Supply Voltage
AVSS
VIH
Analog Supply Voltage
0
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
HIGH Input
Voltage (4)
0.8VCC2
0.8VCC2
0.8VCC1
VCC2
VCC2
VCC1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
V
V
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
P7_0, P7_1
0.8VCC1
0
6.5
V
V
P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
VIL
LOW Input
Voltage (4)
0.2VCC2
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0
(during single-chip mode)
0
0
0.2VCC2
0.2VCC
V
V
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P14_0, P14_1,
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
HIGH Peak
Output Current
(4)
−10.0
−5.0
10.0
5.0
mA
mA
mA
mA
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
HIGH Average
Output Current
(4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
LOW Peak
Output Current
(4)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1
LOW Average
Output Current
(4)
VCC1=4.0V to 5.5V
f(XIN)
Main Clock Input Oscillation Frequency
Sub-Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency
CPU Operation Clock
0
16
50
2
MHz
kHz
MHz
MHz
MHz
ms
f(XCIN)
f(Ring)
f(PLL)
32.768
1
0.5
10
0
VCC1=4.0V to 5.5V
VCC1=5.5V
24
24
20
f(BCLK)
tSU(PLL)
PLL Frequency Synthesizer Stabilization
Wait Time
NOTES:
1. Referenced to VCC1 = VCC2 = 4.7 to 5.5V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85 °C, V version= −40 to 125 °C.
2. The Average Output Current is the mean value within 100ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10 P1, P14_0 and P14_1 must be 80mA max. The total IOL(peak) for
ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12, and P13 must be 80mA max. The total IOH(peak) for ports P0, P1, and P2 must
be −40mA max. The total IOH(peak) for ports P3, P4, P5, P12, and P13 must be −40mA max. The total IOH(peak) for ports P6,
P7, and P8_0 to P8_4 must be −40mA max. The total IOH(peak) for ports P8_6, P8_7, P9 , P10, P11, P14_0, and P14_1 must
be −40mA max.
As for 80-pin version, the total IOL(peak) for all ports and IOH(peak) must be 80mA. max. due to one VCC and one VSS.
4. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006 Page 83 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.51
A/D Conversion Characteristics
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ.
Max.
10
−
Resolution
VREF=VCC1
Bits
INL
Integral Non-Linearity
Error
10bit
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
±3
LSB
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
LSB
8bit
VREF=VCC1=5V
±2
±3
LSB
LSB
−
Absolute Accuracy
10bit
VREF= AN0 to AN7 input,
VCC1= AN0_0 to AN0_7 input,
5V
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
External operation amp
connection mode
±7
±2
LSB
8bit
VREF=VCC1=5V
LSB
kΩ
−
Tolerance Level Impedance
Differential Non-Linearity Error
Offset Error
3
DNL
±1
±3
±3
40
LSB
LSB
LSB
kΩ
−
−
Gain Error
RLADDER
tCONV
Ladder Resistance
VREF=VCC1
10
10-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC1=5V, φAD=12MHz
2.75
µs
tCONV
8-bit Conversion Time, Sample & Hold
Function Available
VREF=VCC1=5V, φAD=12MHz
2.33
µs
tSAMP
VREF
VIA
Sampling Time
0.25
2.0
0
µs
V
Reference Voltage
Analog Input Voltage
VCC1
VREF
V
NOTES:
1. Referenced to VCC1=AVCC=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified.
T version = −40 to 85°C, V version =−40 to 125°C
2. φAD frequency must be 12 MHz or less.
3. When sample & hold is disabled, φAD frequency must be 250 kHz or more, in addition to the limitation in Note 2.
When sample & hold is enabled, φAD frequency must be 1MHz or more, in addition to the limitation in Note 2.
(1)
Table 5.52
D/A Conversion Characteristics
Standard
Typ.
Symbol
Parameter
Measuring Condition
Unit
Min.
4
Max.
8
−
Resolution
Bits
%
−
Absolute Accuracy
Setup Time
1.0
3
tSU
RO
µs
Output Resistance
Reference Power Supply Input Current
10
20
1.5
kΩ
mA
IVREF
(NOTE 2)
NOTES:
1. Referenced to VCC1=VREF=4.0 to 5.5V, VSS=AVSS=0V at Topr = −40 to 85°C / −40 to 125°C unless otherwise specified. T
version = −40 to 85°C, V version =−40 to 125°C
2. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to “00h”. The resistor
ladder of the A/D converter is not included. Also, when D/A register contents are not “00h”, the IVREF will flow even if Vref id
disconnected by the A/D control register.
Rev.2.41 Jan 10, 2006 Page 84 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Table 5.53
Flash Memory Version Electrical Characteristics (1) for 100 cycle products (B, U)
Standard
Symbol
Parameter
Program and Erase Endurance (3)
Unit
Min.
100
Typ.
Max.
−
cycle
µs
µs
s
−
Word Program Time (VCC1=5.0V)
25
25
200
200
4
−
Lock Bit Program Time
−
Block Erase Time
(VCC1=5.0V)
4-Kbyte block
8-Kbyte block
32-Kbyte block
64-Kbyte block
4
0.3
0.3
0.5
0.8
−
4
s
−
4
s
−
4
s
−
Erase All Unlocked Blocks Time (2)
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
4×n
15
s
tPS
−
µs
year
20
(6)
Table 5.54
Flash Memory Version Electrical Characteristics for 10,000 cycle products (B7, U7)
(7)
(Block A and Block 1
)
Standard
Typ.
Symbol
Parameter
Unit
Min.
Max.
−
−
−
−
Program and Erase Endurance (3, 8, 9)
Word Program Time (VCC1=5.0V)
Lock Bit Program Time
10,000 (4)
cycle
µs
25
25
µs
Block Erase Time
4-Kbyte block
4
0.3
s
(VCC1=5.0V)
tPS
Flash Memory Circuit Stabilization Wait Time
Data Hold Time (5)
15
µs
−
20
year
NOTES:
1. Referenced to VCC1=4.5 to 5.5V at Topr = 0 to 60 °C unless otherwise specified.
2. n denotes the number of block erases.
3. Program and Erase Endurance refers to the number of times a block erase can be performed.
If the program and erase endurance is n (n=100, 1,000, or 10,000), each block can be erased n times.
For example, if a 4 Kbytes block A is erased after writing 1 word data 2,048 times, each to a different address, this counts as
one program and erase endurance. Data cannot be written to the same address more than once without erasing the block.
(Rewrite prohibited)
4. Maximum number of E/W cycles for which operation is guaranteed.
5. Ta (ambient temperature)=55 °C. As to the data hold time except Ta=55 °C, please contact Renesas Technology Corp. or an
authorized Renesas Technology Corp. product distributor.
6. Referenced to VCC1 = 4.5 to 5.5V at Topr = −40 to 85 °C (B7, U7 (T version)) / −40 to 125 °C (B7, U7 (V version)) unless
otherwise specified.
7. Table 5.54 applies for block A or block 1 program and erase endurance > 1,000. Otherwise, use Table 5.53.
8. To reduce the number of program and erase endurance when working with systems requiring numerous rewrites, write to
unused word addresses within the block instead of rewrite. Erase block only after all possible addresses are used. For
example, an 8-word program can be written 256 times maximum before erase becomes necessary.
Maintaining an equal number of erasure between block A and block 1 will also improve efficiency. It is important to track the
total number of times erasure is used.
9. Should erase error occur during block erase, attempt to execute clear status register command, then block erase command
at least three times until erase error disappears.
10. Set the PM17 bit in the PM1 register to “1” (wait state) when executing more than 100 times rewrites (B7 and U7).
11. Customers desiring E/W failure rate information should contact their Renesas technical support representative.
Table 5.55
Flash Memory Version Program/Erase Voltage and Read Operation Voltage
Characteristics (at Topr = 0 to 60 °C(B, U), Topr = −40 to 85 °C (B7, U7 (T version)) / −40
to 125 °C (B7, U7 (V version))
Flash Program, Erase Voltage
VCC1 = 5.0 V ± 0.5 V
Flash Read Operation Voltage
VCC1=4.0 to 5.5 V
Rev.2.41 Jan 10, 2006 Page 85 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
Table 5.56
Power Supply Circuit Timing Characteristics
Standard
Unit
Symbol
td(P-R)
Parameter
Measuring Condition
VCC1=4.0V to 5.5V
Min.
Typ.
Max.
2
Time for Internal Power Supply Stabilization
During Powering-On
ms
td(R-S)
td(W-S)
STOP Release Time
150
150
µs
µs
Low Power Dissipation Mode Wait Mode
Release Time
Recommended
operation voltage
td(P-R)
Time for Internal Power
VCC1
Supply Stabilization During
Powering-On
td(P-R)
CPU clock
Interrupt for
td(R-S)
(a) Stop mode release
or
STOP Release Time
(b)Wait mode release
td(W-S)
Low Power Dissipation
Mode Wait Mode Release
Time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 5.22
Power Supply Circuit Timing Diagram
Rev.2.41 Jan 10, 2006 Page 86 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
(1)
Table 5.57
Electrical Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
HIGH
Output
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
IOH=−5mA
VOH
VCC1−2.0
VCC1
Voltage (2) P11_0 to P11_7, P14_0, P14_1
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOH=−5mA
OH=−200µA
IOH=−200µA
VCC2−2.0
VCC1−0.3
VCC2−0.3
VCC2
VCC1
VCC2
HIGH
Output
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
Voltage (2) P11_0 to P11_7, P14_0, P14_1
VOH
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
HIGH Output Voltage XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOH=−1mA
VOH
VCC1−2.0
VCC1−2.0
VCC1
VCC1
V
V
IOH=−0.5mA
HIGH Output Voltage XCOUT
With no load applied
With no load applied
IOL=5mA
2.5
1.6
LOW
Output
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
VOL
2.0
2.0
Voltage (2) P11_0 to P11_7, P14_0, P14_1
V
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
IOL=5mA
LOW
Output
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
IOL=200µA
IOL=200µA
VOL
0.45
0.45
Voltage (2) P11_0 to P11_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P12_0 to P12_7, P13_0 to P13_7
LOW Output Voltage XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
IOL=1mA
VOL
2.0
V
V
IOL=0.5mA
2.0
LOW Output Voltage XCOUT
With no load applied
With no load applied
0
0
Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN,
INT0 to INT5, NMI, ADTRG, CTS0 to CTS2, CLK0 to CLK4,
TA0OUT to TA4OUT, KI0 to KI3, RXD0 to RXD2,
SCL0 to SCL2, SDA0 to SDA2, SIN3, SIN4
VT+-VT-
0.2
0.2
1.0
2.5
V
V
Hysteresis
RESET
VT+-VT-
IIH
HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, VI=5V
Current (2) P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
5.0
µA
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
LOW Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, VI=0V
Current (2) P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
IIL
−5.0 µA
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, RESET, CNVSS, BYTE
Pull-Up
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, VI=0V
RPULLUP
Resistance P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7,
(2)
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
30
50
170
kΩ
P11_0 to P11_7,P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
Feedback Resistance XIN
Feedback Resistance XCIN
RAM Retention Voltage
RfXIN
1.5
15
MΩ
MΩ
V
RfXCIN
VRAM
At stop mode
2.0
NOTES:
1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise
specified. T version = −40 to 85°C, V version =−40 to 125°C.
2. There is no external connections for port P1_0 to P1_7, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Rev.2.41 Jan 10, 2006 Page 87 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
(1)
Table 5.58
Electrical Characteristics (2)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min.
Typ. Max.
f(BCLK)=24MHz
No division, PLL operation
ICC
Power Supply Current
In single-chip
(VCC1=VCC2=4.0V to 5.5V) mode, the output
pins are open and
Mask ROM
14
1
20
mA
mA
mA
mA
No division,
On-chip oscillation
other pins are VSS
f(BCLK)=24MHz,
No division, PLL operation
Flash
Memory
18
1.8
27
No division,
On-chip oscillation
f(BCLK)=10MHz,
VCC1=5.0V
Flash Memory
Program
15
25
mA
mA
f(BCLK)=10MHz,
VCC1=5.0V
Flash Memory
Erase
f(XCIN)=32kHz
Low power dissipation
mode, ROM (3)
Mask ROM
25
25
µA
µA
f(BCLK)=32kHz
Low power dissipation
mode, RAM (3)
Flash Memory
f(BCLK)=32kHz
Low power dissipation
420
50
µA
µA
µA
mode, Flash Memory (3)
On-chip oscillation,
Wait mode
f(BCLK)=32kHz
Mask ROM
Flash Memory
Wait mode (2)
,
7.5
Oscillation capability High
f(BCLK)=32kHz
Wait mode (2)
Oscillation capability Low
,
2.0
2.0
µA
Stop mode
Topr =25°C
6.0
20
µA
µA
µA
Stop mode
Topr =85°C
Stop mode
Topr =125°C
TBD
NOTES:
1. Referenced to VCC1=VCC2=4.0 to 5.5V, VSS = 0V at Topr = −40 to 85°C / −40 to 125°C, f(BCLK)=24MHz unless otherwise
specified. T version = −40 to 85°C, V version =−40 to 125°C.
2. With one timer operated using fC32.
3. This indicates the memory in which the program to be executed exists.
Rev.2.41 Jan 10, 2006 Page 88 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 5.59
External Clock Input (XIN input)
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
tc
External Clock Input Cycle Time
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
25
15
15
tf
External Clock Fall Time
Rev.2.41 Jan 10, 2006 Page 89 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 5.60
Timer A Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
Max.
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
40
Table 5.61
Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.62
Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 5.63
Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
Table 5.64
Timer A Input (Counter Increment/Decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
tc(UP)
TAiOUT Input Cycle Time
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
TAiOUT Input Hold Time
ns
ns
ns
ns
ns
tw(UPH)
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
Table 5.65
Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tsu(TAIN-TAOUT) TAiOUT Input Setup Time
tsu(TAOUT-TAIN) TAiIN Input Setup Time
Rev.2.41 Jan 10, 2006 Page 90 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Timing Requirements
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
Table 5.66
Timer B Input (Counter Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 5.67
Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
Max.
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.68
Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 5.69
A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
tc(AD)
1000
ns
ns
ADTRG Input Cycle Time
tw(ADL)
125
ADTRG input LOW Pulse Width
Table 5.70
Serial Interface
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
80
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
0
RXDi Input Setup Time
RXDi Input Hold Time
70
90
Table 5.71
External Interrupt INTi Input
Standard
Symbol
Parameter
Unit
Min.
250
Max.
tw(INH)
tw(INL)
ns
ns
INTi Input HIGH Pulse Width
INTi Input LOW Pulse Width
250
Rev.2.41 Jan 10, 2006 Page 91 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
Switching Characteristics
(VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −40 to 85°C (T version) / −40 to 125°C (V version) unless otherwise
specified)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
30pF
Figure 5.23
Ports P0 to P10 Measurement Circuit
Rev.2.41 Jan 10, 2006 Page 92 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
XIN input
tf
tw(H)
tw(L)
tr
tc
tc(TA)
tw(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
th(TIN-UP) tsu(UP-TIN)
TAiIN input
(When count on rising
edge is selected)
Two-phase pulse input in
event counter mode
tc(TA)
TAiIN input
tsu(TAIN-TAOUT)
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tw(ADL)
ADTRG input
Figure 5.24
Timing Diagram (1)
Rev.2.41 Jan 10, 2006 Page 93 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
5. Electrical Characteristics
VCC1=VCC2=5V
tc(CK)
tw(CKH)
CLKi
tw(CKL)
th(C-Q)
TXDi
RXDi
tsu(D-C)
td(C-Q)
th(C-D)
tw(INL)
INTi input
tw(INH)
Figure 5.25
Timing Diagram (2)
Rev.2.41 Jan 10, 2006 Page 94 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 1. Package Dimensions
Appendix 1.Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0128KB-A
Previous Code
128P6Q-A
MASS[Typ.]
0.9g
P-LQFP128-14x20-0.50
HD
*1
D
102
65
103
64
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
2.
bp
b1
Dimension in Millimeters
Reference
Symbol
Terminal cross section
Min
19.9
13.9
Nom
20.0
14.0
1.4
Max
20.1
14.1
D
E
A2
HD
HE
A
128
39
21.8
15.8
22.0
16.0
22.2
16.2
1.7
1
38
ZD
Index mark
A1
bp
b1
c
0.05
0.17
0.125
0.22
0.2
0.27
F
0.20
0.09
0.145
0.125
0.20
c1
L
0
°
8°
L1
*3
y
bp
e
e
x
0.5
x
DetailF
0.10
0.10
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JB-A
Previous Code
100P6S-A
MASS[Typ.]
1.6g
HD
D
*1
80
51
81
50
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
2.
Dimension in Millimeters
Reference
Symbol
Min
19.8
13.8
Nom
20.0
14.0
2.8
Max
20.2
14.2
D
E
100
31
A2
HD
HE
A
22.5
16.5
22.8
16.8
23.1
17.1
3.05
0.2
1
30
ZD
Index mark
F
A1
bp
c
0
0.1
0.3
0.25
0.13
0.4
0.15
0.2
L
0
°
10°
*3
e
bp
y
e
y
0.5
0.65
0.8
Detail F
0.10
ZD
ZE
L
0.575
0.825
0.6
0.4
0.8
Rev.2.41 Jan 10, 2006 Page 95 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62PT)
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0100KB-A
Previous Code
MASS[Typ.]
0.6g
P-LQFP100-14x14-0.50
100P6Q-A / FP-100U / FP-100UV
HD
D
*1
51
75
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
76
50
2.
bp
b1
Dimension in Millimeters
Reference
Symbol
Min
13.9
13.9
Nom
14.0
14.0
1.4
Max
14.1
14.1
D
E
Terminal cross section
A2
HD
HE
A
15.8
15.8
16.0
16.0
16.2
16.2
1.7
100
26
A1
bp
b1
c
0.05
0.15
0.1
0.20
0.15
0.25
1
25
Index mark
ZD
F
0.18
0.09
0.145
0.125
0.20
c1
0
°
8°
e
x
0.5
y
*3
0.08
0.08
L
bp
e
x
y
L1
ZD
ZE
L
1.0
1.0
0.5
1.0
Detail F
0.35
0.65
L1
JEITA Package Code
P-QFP80-14x14-0.65
RENESAS Code
PRQP0080JA-A
Previous Code
80P6S-A
MASS[Typ.]
1.1g
HD
*1
D
60
41
61
40
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
2.
Dimension in Millimeters
Reference
Symbol
80
Min
13.8
13.8
Nom
14.0
14.0
2.8
Max
14.2
14.2
21
D
E
1
20
A2
HD
HE
A
ZD
Index mark
16.5
16.5
16.8
16.8
17.1
17.1
3.05
0.2
F
A1
bp
c
0
0.1
0.3
L
0.25
0.13
0.4
Detail F
0.15
0.2
*3
0
°
10°
bp
e
y
e
y
0.5
0.65
0.8
0.10
ZD
ZE
L
0.825
0.825
0.6
0.4
0.8
Rev.2.41 Jan 10, 2006 Page 96 of 96
REJ03B0001-0241
REVISION HISTORY
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Summary
Rev.
1.10
Date
Page
May 28, 2003
1
2
Applications are partly revised.
Table 1.1.1 is partly revised.
4-5 Table 1.1.2 and 1.1.3 is partly revised.
“Note 1” is partly revised.
22
23
Table 1.5.3 is partly revised.
Table 1.5.5 is partly revised.
Table 1.5.6 is added.
24
30
31
Table 1.5.9 is partly revised.
Notes 1 and 2 in Table 1.5.26 is partly revised.
Notes 1 in Table 1.5.27 is partly revised.
Note 3 is added to “Data output hold time (refers to BCLK)” in Table 1.5.26
and 1.5.27.
30-31
32
Note 4 is added to “th(ALE-AD)” in Table 1.5.28.
30-32 Switching Characteristics is partly revised.
36-39
40-41
th(WR-AD) and th(WR-DB) in Figure 1.5.5 to 1.5.8 is partly revised.
th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.9 to
1.5.10 is partly revised.
Note 2 is added to Table 1.5.29.
42
47
48
Notes 1 and 2 in Table 1.5.45 is partly revised.
Notes 1 in Table 1.5.46 is partly revised.
47-48
Note 3 is added to “Data output hold time (refers to BCLK)” in Table
1.5.45 and 1.5.46.
49
Note 4 is added to “th(ALE-AD)” in Table 1.5.47.
47-48 Switching Characteristics is partly revised.
53-56 th(WR-AD) and th(WR-DB) in Figure 1.5.15 to 1.5.18 is partly revised.
57-58 th(ALE-AD), th(WR-CS), th(WR-DB) and th(WR-AD) in Figure 1.5.19 to
1.5.20 is partly revised.
Since high reliability version is added, a group name is revised.
-
2.00
Oct 29, 2003
M16C/62 Group (M16C/62P) → M16C/62 Group (M16C/62P, M16C/62PT)
2-4
Table 1.1 to 1.3 are revised.
Note 3 is partly revised.
2-4 Table 1.1 to 1.3 are revised.
Note 3 is partly revised.
Figure 1.2 Note5 is deleted.
6
Table 1.4 to 1.7 Product List is partly revised.
Table 1.8 and Figure 1.4 are added.
Figure 1.5 to 1.9 ZP is added.
7-9
11
12-15
17,19
18,20
30
Table 1.10 and 1.12 ZP is added to timer A.
Table 1.11 and 1.13 VCC1 is added to VREF.
Table 5.1 is revised.
31-32
Table 5.2 and 5.3 are revised.
C - 1
REVISION HISTORY
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Summary
Rev.
Date
Page
33
Table 5.4 A-D Conversion Characteristics is revised.
Table 5.5 D-A Conversion Characteristics revised.
34,74 Table 5.6 to 5.7 and table 5.54 to 5.55 are revised.
36 Table 5.11 is revised.
38,55 Table 5.14 and 5.33 HLDA output deley time is deleted.
41 Figure 5.1 is partly revised.
41-43, Table 5.27 to 5.29 and table 5.46 to 48 HLDA output deley time is added.
58-60
44
Figure 5.2 Timing Diagram (1) XIN input is added.
47-48 Figure 5.5 to 5.6 Read timing DB → DBi
49-50 Figure 5.7 to 5.8 Write timing DB → DBi
52
53
58
61
Figure 5.10 DB → DBi
Table 5.30 is revised.
Figure 5.11 is partly revised.
Figure 5.12 Timing Diagram (1) XIN input is added.
64-65 Figure 5.15 to 5.16 Read timing DB → DBi
66-67 Figure 5.17 to 5.18 Write timing DB → DBi
69
Figure 5.20 DB → DBi
70-85 Electrical Characteristics (M16C/62PT) is added.
8-9 Table 1.5 to 1.7 Product List is partly revised. Note 1 is deleted.
2.10
2.11
Nov 07, 2003
Jan 06, 2004
23
Table 3.1 is revised.
71
72
Table 5.50 is revised.
Table 5.51 is deleted.
16
Table 1.9 NOTE 3 VCC1 VCC2 → VCC1 > VCC2
17-18 Table 1.10 to 1.11 NOTE 1 VCC1 VCC2 → VCC1 > VCC2
31
12
Table 5.2 Power Supply Ripple Allowable Frequency Unit MHz → kHz
Table 1.9 and Figure 1.5 are added.
18, 20 Table 1.11 to 1.13 are revised.
19,21 Table 1.12 to 1.14 are revised.
2.30
Sep 01, 2004
24
Figure 3.1 is partly revised.
Note 3 is added.
25
33
Note 6 is added.
Table 5.3 is revised.
Note 2 in Table 5.4 is added.
Table 5.5 to 5.6 is partly revised.
Table 5.8 is revised.
Table 5.9 is revised.
Table 5.11 is revised.
34
35
37
C - 2
REVISION HISTORY
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Summary
Rev.
Date
Page
40
57
70
72
73
74
76
79
Table 5.24 is partly revised.
Table 5.43 is partly revised.
Table 5.48 is partly revised.
Table 5.50 is partly revised.
Table 5.53 is partly revised.
Table 5.55 is revised.
Table 5.57 is partly revised.
Table 5.69 is partly revised.
2.41
Jan 01, 2006
-
voltage down detection reset -> brown-out detection Reset
2-4 Tables 1.1 to 1.3 Performance outline of M16C/62P group are partly
revised.
7
Table 1.4 Product List (1) is partly revised.
Note 1 is added.
8
Table 1.5 Product List (2) is partly revised.
Note 1, 2 and 3 are added.
9
Table 1.6 Product List (3) is partly revised.
Note 1 and 2 are added.
10
11
12
13
14
Table 1.7 Product List (4) is partly revised.
Note 1 and 2 are added.
Figure 1.3 Type No., Memory Size, Shows RAM capacity, and Package is
partly revised
Table 1.8 Product Code of Flash Memory version and ROMless version for
M16C/62P is partly revised.
Table 1.9 Product Code of Flash Memory version for M16C/62P is partly
revised.
Figure 1.6 Pin Configuration (Top View) is partly revised.
15-17 Tables 1.10 to 1.12 Pin Characteristics for 128-Pin Package are added.
18-19 Figure 1.7 and 1.8 Pin Configuration (Top View) are partly revised.
20-21 Tables 1.13 to 1.14 Pin Characteristics for 100-Pin Package are added.
22
Figure 1.9 Pin Configuration (Top View) is partly revised.
23-24 Tables 1.15 to 1.16 Pin Characteristics for 80-Pin Package are added.
25-29 Tables 1.17 to 1.21 are partly revised.
34
43
45
Note 4 of Table 4.1 SFR Information is partly revised.
Table 5.4 A/D Conversion Characteristics is partly revised.
Table 5.6 Flash Memory Version Electrical Characteristics for 100 cycle
products is partly revised.
Table 5.7 Flash Memory Version Electrical Characteristics for 10,000 cycle
products is partly revised.
Table 5.8 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is partly revised.
46
Table 5.9 Low Voltage Detection Circuit Electrical Characteristics is partly
revised.
C - 3
REVISION HISTORY
M16C/62P Group (M16C/62P, M16C/62PT) Hardware Manual
Description
Summary
Rev.
Date
Page
47
48
49
50
67
85
Figure 5.1 Power Supply Circuit Timing Diagram is partly revised.
Table 5.11 Electrical Characteristics (1) is partly deleted.
Table 5.12 Electrical Characteristics (2) is partly revised.
Note 1 of Table 5.13 External Clock Input (XIN input) is added.
Notes 1 to 4 of Table 5.32 External Clock Input (XIN input) are added.
Table 5.53 Flash Memory Version Electrical Characteristics for 100 cycle
products is partly revised. Standard (Min.) is partly revised.
Table 5.54 Flash Memory Version Electrical Characteristics for 10,000
cycle products is partly revised. Standard (Min.) is partly revised.
Note 5 is revised.
Table 23.55 Flash Memory Version Program / Erase Voltage and Read
Operation Voltage Characteristics is partly revised.
87
88
Table 5.57 Electrical Characteristics (1) is partly deleted.
Table 5.58 Electrical Characteristics is partly revised.
C - 4
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's
application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data,
diagrams, charts, programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of
publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is
therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product
information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor
home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to
evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes
no responsibility for any damage, liability or other loss resulting from the information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life
is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a
product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater
use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and
cannot be imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
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Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .3.0
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