M306NAMGT-XXXFP [RENESAS]
16-BIT, MROM, 16MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100;
| 型号： | M306NAMGT-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-BIT, MROM, 16MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, 0.65 MM PITCH, PLASTIC, QFP-100 时钟 微控制器 外围集成电路 |
| 文件： | 总295页 (文件大小：3365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Description
The M16C/6N group of single-chip microcomputers are built using the high-performance silicon gate
CMOS process using a M16C/60 series CPU core and are packaged in a 100-pin plastic molded QFP.
These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-
tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.
They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications,
industrial equipment, and other high-speed processing applications.
The M16C/6N group is consisted of two sub-groups, M16C/6N0 group and M16C/6N1 group. The M16C/
6N0 group has two CAN (Controller Area Network) modules and the M16C/6N1 group has one CAN mod-
ule (See Figure 1.1.4 Memory Expansion). The CAN modules comply with the 2.0B specification. The
M16C/6N group is suited to drive automotive and industrial control systems.
Features
• Memory capacity..................................ROM 128K/256K bytes
RAM 5K/10K bytes
• Shortest instruction execution time ......62.5 ns (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
• Supply voltage .....................................4.2 to 5.5V (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
• Low power dissipation .........................60mA M16C/6N0 group Mask products
65mA M16C/6N0 group Flash products
50mA M16C/6N1 group Mask products
55mA M16C/6N1 group Flash products
(f(XIN) = 16MHz, 1/1 prescaler, without software wait)
• Interrupts..............................................29 internal and 9 external interrupt sources, 4 software
interrupt sources, 7 priority levels (including key input interrupt)
• Multifunction 16-bit timer......................5 output timers + 6 input timers
• Serial I/O..............................................3 channels (UART/clock synchronous, 1 channel clock synchronous)
• DMAC ..................................................2 channels (trigger: 24 sources)
• CAN module ........................................2 channels for M16C/6N0 group
Specifications written in this
manual are believed to be ac-
1 channel for M16C/6N1 group
• A-D converter.......................................10 bits X (8X3+2) channels
• D-A converter.......................................8 bits X 2 channels
• CRC calculation circuit.........................1 circuit
curate, but are not guaranteed
to be entirely free of error.
Specifications in this manual
may be changed for functional
or performance improvements.
Please make sure your manual
is the latest edition.
• Watchdog timer....................................1 15-bit timer
• Programmable I/O ...............................87 lines
______
• Input port..............................................1 line (P85 shared with NMI pin)
• Chip select output ................................4 lines
• Memory expansion ..............................Available (to a maximum of 1M bytes)
• Clock generating circuit .......................3 built-in circuits
Main clock generating circuit, Sub clock generating circuit,
(built-in feedback resistor, and external ceramic or quartz crystal oscillator)
Ring oscillation circuit (with an oscillation stop detection circuit)
Applications
Automotive and industrial control systems
------Table of Contents------
Central Processing Unit (CPU) ..................... 11
Serial I/O ..................................................... 117
A-D Converter ............................................. 157
D-A Converter ............................................. 167
CRC Calculation Circuit .............................. 169
CAN Module................................................ 171
Programmable I/O Port ............................... 196
Electrical Characteristics............................. 207
Flash Memory Version ................................ 224
Reset............................................................. 14
Processor Mode ............................................ 22
Clock Generating Circuit ............................... 36
Protection ...................................................... 52
Interrupt......................................................... 53
Watchdog Timer............................................ 75
DMAC ........................................................... 77
Timer ............................................................. 87
1
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin Configuration
Figures 1.1.1 and 1.1.2 show the pin configuration (top view).
Pin configuration (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4
4/CS0
P0
P0
P0
P0
P0
P0
P0
P0
P10
P10
P10
P10
P10
7
/AN07/D
/AN06/D
/AN05/D
/AN04/D
/AN03/D
/AN02/D
/AN01/D
/AN00/D
/AN /KI
/AN /KI
/AN /KI
/AN4/KI
/AN
7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P45
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
/BCLK
/HLDA
/HOLD
/ALE
6
6
P46
5
5
P47
4
4
P5
P5
P5
0
3
3
1
2
2
2
1
1
0
0
P5
P5
P5
P5
3
7
7
3
4
5
6
6
6
2
M16C/6N0 Group
5
5
1
0
3
P57
/RDY/CLKOUT
/CTS /RTS
4
P60
0
0
3
P61
/CLK
0
P10
P10
2
/AN
/AN
2
P62
/RxD
/T
/CTS
0
1
1
P6
3
XD0
AVSS
P64
1
1
1
/RTS1/CTS0/CLKS1
P10
0
/AN0
P6
5/CLK
V
REF
P66/RxD
P6
AVcc
7/ADTRG
7/TXD1
P9
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note: P71 and P91 are N channel open-drain output pin.
Package: 100P6S-A
Figure 1.1.1. Pin configuration for M16C/6N0 group (top view)
2
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Pin configuration (top view)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
P4
4/CS0
P0
P0
P0
P0
P0
P0
P0
P0
P10
P10
P10
P10
P10
7
/AN07/D
/AN06/D
/AN05/D
/AN04/D
/AN03/D
/AN02/D
/AN01/D
/AN00/D
/AN /KI
/AN /KI
/AN /KI
/AN4/KI
/AN
7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P45
/CS1
/CS2
/CS3
/WRL/WR
/WRH/BHE
/RD
/BCLK
/HLDA
/HOLD
/ALE
6
6
P46
5
5
P47
4
4
P5
P5
P5
0
3
3
1
2
2
2
1
1
0
0
P5
P5
P5
P5
3
7
7
3
4
5
6
6
6
2
M16C/6N1 Group
5
5
1
0
3
P57
/RDY/CLKOUT
4
P60
/CTS /RTS
0
0
3
P61
/CLK
0
P10
P10
2
/AN
/AN
2
P62
/RxD
/T
/CTS
0
1
1
P6
3
XD0
AVSS
P64
1
1
1
/RTS1/CTS0/CLKS1
P10
0
/AN0
P6
5
/CLK
V
REF
P66
/RxD
AVcc
7/ADTRG
P6
7/TXD1
P9
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Note: P71 and P91 are N channel open-drain output pin.
Package: 100P6S-A
Figure 1.1.2. Pin configuration for M16C/6N1 group (top view)
3
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Block Diagram
Figure 1.1.3 is a block diagram of the M16C/6N group.
Block diagram of the M16C/6N group
8
8
8
8
8
8
8
I/O ports
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
Timer
System clock generator
A-D converter
XIN - X
X
-
XOUT
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
RiCnIgNoscCillOaUtoTr
(10 bits X (8X3+2) channels)
UART/clock synchronous SI/O
(8 bits X 3 channels)
Clock synchronous SI/O
(8 bits X 1 channel)
CAN module
(1 or 2 channels)
(Note 2)
CRC arithmetic circuit (CCITT)
16 12
5
(Polynomial : X +X +X +1)
M16C/60 series16-bit CPU core
Memory
Registers
ROM
(Note 1)
Program counter
R0H
R0H
R1H
R2
R3
A0
A1
FB
R0L
R0L
R1L
PC
Watchdog timer
(15 bits)
RAM
(Note 1)
Vector table
INTB
Stack pointer
DMAC
(2 channels)
ISP
USP
Multiplier
Flag register
FLG
D-A converter
(8 bits x 2 channels)
SB
Note 1: Memory sizes depend on MCU type.
Note 2: Number of channels depends on sub-group.
Figure 1.1.3. Block diagram of M16C/6N group
4
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Performance Outline
Table 1.1.1 is a performance outline of the M16C/6N group.
Table 1.1.1. Performance outline of M16C/6N group
Item
Performance
Number of basic instructions
91 instructions
The shortest instruction execution time
62.5 ns (f(XIN) = 16 MHz, 1/1 prescaler, without software wait)
128K / 256K bytes
5K / 10 K bytes
ROM
Memory
capacity
RAM
P0 to P10 (except P8
5)
I/O ports
8-bit x 10, 7-bit x 1
P85
Input port
1-bit x 1
16-bit x 5
TA0, TA1, TA2, TA3, TA4
TB0, TB1, TB2, TB3, TB4, TB5
UART0, UART1, UART2
S I/O3
Multifunction
timer
16-bit x 6
(UART or clock synchronous) x 3
Clock synchronous
Serial I/O
A-D converter
D-A converter
10 bits x (8 x 3 + 2) channels
8 bits x 2 channels
CRC calculation circuit
DMAC
1 circuit CRC-CCITT
2 channels (trigger: 24 sources)
2 channels for M16C/6N0 group
1 channel for M16C/6N1 group
CAN Module
Watch-dog timer
Interrupt
15-bit x 1 (with prescaler)
29 internal and 9 external sources, 4 software sources,
7 priority levels
3 built-in clock generating circuits (built-in feedback resistor,
external ceramic or quartz crystal oscillator, and internal ring oscillator)
Clock generating circuit
Supply voltage
4.2 to 5.5 V (f(XIN) = 16 MHz, 1/1 prescaler, without software wait)
60 mA M16C/6N0 group Mask products
65 mA M16C/6N0 group Flash products
50 mA M16C/6N1 group Mask products
55 mA M16C/6N1 group Flash products
(f(XIN) = 16 MHz, 1/1 prescaler, without software wait)
Power dissipation
5 V
I/O withstand voltage
Output current
I/O
characteristics
5 mA
Operating ambient temperature
Device configuration
-40 to 125 ˚C
CMOS high performance silicon gate
5
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
M16C/6N Group Expansion
Mitsubishi releases the following products in the M16C/6N group.
(1) Supports to mask ROM versions and flash memory versions
(2) ROM size
(3) Package
100P6S-A .....................................Plastic mold QFP (Mask ROM and Flash memory versions)
ROM Size
(Byte)
External
ROM
256K
128K
M306NAMGT-XXXFP
M306NAFGTFP
M306NAMCT-XXXFP
M306NAMCV-XXXFP
M306NBMCT-XXXFP
M306NBMCV-XXXFP
M306NBFCTFP
96K
5 K
10 K
5 K
10 K
RAM Size
(Byte)
Flash memory version
Mask ROM version
Figure 1.1.4. Memory expansion
Mitsubishi supports the types shown in the list below.
Table 1.1.2. M16C/6N group
October 2002
Remarks
ROM size
(Byte)
RAM size CAN module
Type No.
Characteristic
Package type
100P6S-A
(Byte)
(Channel)
M306NAMGT-XXXFP
M306NAMCT-XXXFP
M306NAMCV-XXXFP
M306NAFGTFP
256K
128K
128K
256K
128K
128K
128K
10K
85˚C guaranteed version
5K
5K
Mask ROM version
M16C/6N0
group
2
125˚C guaranteed version(Note 2)
85˚C guaranteed version
10K
5K
Flash memory 5V version
Mask ROM version
Flash memory 5V version
M306NBMCT-XXXFP
M306NBMCV-XXXFP
M306NBFCTFP
85˚C guaranteed version
M16C/6N1
group
5K
1
125˚C guaranteed version(Note 2) 100P6S-A
85˚C guaranteed version
5K
Note 1: It may change in the future.
Note 2: It is difficult from 85˚C guranteed version on operating ambient temperature and terms of the use,
please inguire.
6
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Type No.
M 3 0 6 N A M C T - X X X F P
Package type:
FP : Package 100P6S-A
ROM No.
Omitted for Flash version
Temperature Range
T : Automotive 85˚C guaranteed version
V : Automotive 125˚C guaranteed version
ROM capacity:
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
F : Flash ROM version
Shows the number of CAN module
A : 2 channels
B : 1 channel
(The value itself has no specific meaning)
M16C/6N Group
M16C Family
Figure 1.1.5. Type No., memory size, and package
7
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Table 1.2.1. Pin description of M16C/6N group (1)
Pin name
CC, VSS
Signal name
I/O type
Function
Power supply
input
V
Supply 4.2 to 5.5 V to the VCC pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect it to the
VSS pin to operate in single-chip or memory expansion mode.
Connect it to the VCC pin to operate in microprocessor mode.
CNVSS
RESET
CNVSS
Input
Reset input
Clock input
Clock output
Input
A "L" on this input resets the microcomputer.
These pins are provided for the main clock generating circuit. Connect
a ceramic resonator or quartz crystal between the XIN and the XOUT
pins. To use an externally derived clock, input it to the XIN pin and
leave the XOUT pin open.
X
IN
Input
XOUT
Output
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is "L"; an 8-bit width is selected when this
input is "H". This input must be fixed to either "H" or "L". When
External data
bus width
select input
BYTE
Input
operating in single-chip mode, connect this pin to VSS
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
AVCC
AVSS
pin to VCC
.
Analog power
supply input
This pin is a power supply input for the A-D converter. Connect this
pin to VSS
.
Reference
voltage input
Input
This pin is a reference voltage input for the A-D converter.
V
REF
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input, the user can specify in units of four
bits via software whether or not they are tied to a pull-up resistor.
Pins in this port also function as A-D converter input pins.
P00
to P0
7
I/O port P0
Input/output
D0
to D
7
Input/output When set as a separate bus, these pins input and output data (D0 to D7).
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as external interrupt pins as selected by software.
P1
0
to P1
7
I/O port P1
I/O port P2
Input/output
D8
to D15
to P2
Input/output When set as a separate bus, these pins input and output data (D8 to D15).
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins.
P20
7
Input/output
Output
A
0
to A
7
These pins output 8 low-order address bits (A0 to A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D to D ) and output 8 low-order address bits
(A to A ) separated in time by multiplexing.
A
0/D0
to
Input/output
0
7
A7
/D7
0
7
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D to D ) and output address (A to A ) separated
in time by multiplexing. They also output address (A ).
Output
Input/output
A
0
, A
1
/D
7/D6
0
0
6
1
7
to A
to P3
to A15
/D
0
P3
0
7
I/O port P3
Input/output This is an 8-bit I/O port equivalent to P0.
A
8
Output
These pins output 8 middle-order address bits (A8 to A15).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D ) and output address (A ) separated in time
by multiplexing. They also output address (A to A15).
A
8
A
7,
to A15
Input/output
Output
7
8
9
9
P40
to P4
7
I/O port P4
Input/output This is an 8-bit I/O port equivalent to P0.
These pins output CS0 to CS3 signals and A16 to A19. CS0 to CS3 are
chip select signals used to specify an access space. A16 to A19 are 4
high-order address bits.
CS
A
0
to CS
3
,
Output
Output
16 to A19
8
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Pin Description
Table 1.2.2. Pin description of M16C/6N group (2)
Pin name
P5 to P5
Signal name
I/O port P5
I/O type
Function
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as XCIN as selected by software.
0
7
Input/output
Output
Output
Output
Output
Output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is "L" and to the odd addresses when the WRH
signal is "L". Data is read when RD is "L".
HOLD,
ALE,
RDY
Output
Input
WR, BHE, and RD selected
Data is written when WR is "L". Data is read when RD is "L". Odd
addresses are accessed when BHE is "L". Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is "L", the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a "L"
level. ALE is used to latch the address. While the input level of the
RDY pin is "L", the microcomputer is in the ready state. BCLK outputs
a clock with the same cycle as the internal clock ø.
This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.
P6
0
to P6
7
I/O port P6
Input/output
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
P70
to P7
7
I/O port P7
I/O port P8
as timer A
pins as selected by software.
Port 7 has an n-channel open drain output.
0
to A
3
, timer B5, UART2 I/O or CAN1 transmit/receive data
(Note)
1
P8
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8 and P8 can be set
using software to function as the I/O pins for a sub clock generation circuit.
0 to P84, P86 and P87 are I/O ports with the same functions as P6.
P8
P8
0
6
to P8
4
,
Input/output
Input/output
,
6
7
P87
,
Input/output
P85
Input port P85
Input
In this case, connect a quartz crystal oscillator between P8
and P8 (XCIN pin).
P8 is an input-only port that also functions for NMI. The NMI interrupt
6 (XCOUT pin)
7
5
is generated when the input at this pin changes from "H" to "L". The NMI
function cannot be cancelled using software. P85 is not equipped with
a pull-up transistor.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as S I/O3 I/O pins, Timer B0 to B4 input pins, D-A converter output pins,
A-D converter extended input pins, A-D trigger input pins or CAN0
transmit/receive data pins as selected by software.
P9
0
to P9
7
I/O port P9
Input/output
Input/output
Port 91 has an n-channel open drain output.
P10
0
to P10
7
I/O port P10
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P10 to P10 also function
as input pins for the key input interrupt function.
4
7
Note: Channel CAN1 is not available for M16C/6N1 group.
9
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Memory
Operation of Functional Blocks
The M16C/6N group accommodates several units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as CAN module, timers, serial I/O, D-A converter, DMAC, CRC
calculation circuit, A-D converter, and I/O ports.
Each unit is explained in the following.
Memory
Figure 1.3.1 shows the memory map of the M16C/6N group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. The ROM area is mapped top-aligned up to FFFFF16. The start address
depends on the memory capacity of the device; e.g. 128Kbytes ROM are mapped E000016 up to FFFFF16.
______
The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The
starting addresses of the interrupt routines are stored here. The address of the vector table for timer inter-
rupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details.
The RAM area is mapped bottom-aligned starting from 0040016. The end address depends on the RAM
capacity of the device; e.g. 5Kbytes RAM are mapped to 0040016 to 017FF16. In addition to storing data,
the RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph-
eral devices such as I/O ports, A-D converter, serial I/O, CAN modules and timers, etc. Figure 1.6.1 to 1.6.3
show the locations of peripheral unit control registers. Any part of the SFR area that is not occupied is
reserved and cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be implemented as 2-byte instructions, reducing the number of program steps.
Depending on processor mode setting, a part of the space is reserved and cannot be used. For example, in
the M306NAMCT-XXXFP, the following space cannot be used.
• The space between 0180016 and 03FFF16 (All modes)
• The space between 0400016 and CFFFF16 (Single-chip mode)
• The space between D000016 and DFFFF16 (Single-chip mode and memory expansion mode)
For details on how to enable usage of specific memory areas, see the section "Processor Mode".
0000016
Note 1: Cannot be used in any mode.
Note 2: Cannot be used in single-chip mode.
SFR area
Note 3: Cannot be used in single-chip mode or memory
expansion mode.
FFE0016
FFFDC16
FFFFF16
0040016
Internal RAM area
Special page
vector table
XXXXX16
Internal reserved
area (Note 1)
MMMMM16
Type No.
Address XXXXX16
Address YYYYY16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
M306NBMCT/FCT
M306NAMCT
M306NAMGT
M306NAFGT
017FF16
017FF16
02BFF16
02BFF16
E000016
E000016
C000016
C000016
External area
(Note 2)
NNNNN16
YYYYY16
Internal reserved
area (Note 3)
Address NNNNN16
PM13 (Note)
Address MMMMM16
Oscillation stop detection/Watchdog timer
DBC
NMI
Reset
0
1
0400016
0600016
D000016
C000016
Internal ROM area
Note: PM13 (Internal reserved area expansion bit)
FFFFF16
Figure 1.3.1. Memory map
10
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these registers have two register banks.
b15
b15
b15
b15
b15
b15
b15
b8 b7
b8 b7
b0
b0
b0
b0
b0
b0
b0
R0(Note)
R1(Note)
R2(Note)
R3(Note)
A0(Note)
A1(Note)
FB(Note)
L
L
H
H
b19
b19
b0
PC
Program counter
Data
registers
b0
b0
Interrupt table
register
INTB
H
L
b15
b15
b15
b15
User stack pointer
USP
ISP
SB
b0
b0
b0
Interrupt stack
pointer
Address
registers
Static base
register
FLG
Frame base
registers
Flag register
IPL
U
I
O B S Z D C
Note: These registers consist of two register banks.
Figure 1.4.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can be
used as 32-bit data registers (R2R0/R3R1).
(2) Address rgisters (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
The frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
The program counter (PC) is configured with 20 bits, indicating the address of an instruction to be ex-
ecuted.
(5) Interrupt table register (INTB)
The interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt
vector table.
(6) Stack pointer (USP/ISP)
Stack pointers come in two types: the user stack pointer (USP) and the interrupt stack pointer (ISP), each
configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
The static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
The flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is
cleared to "0" when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to "1" when an arithmetic operation results in 0; otherwise, cleared to "0".
• Bit 3: Sign flag (S flag)
This flag is set to "1" when an arithmetic operation results in a negative value; otherwise, cleared to
"0".
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is
selected when this flag is "1".
• Bit 5: Overflow flag (O flag)
This flag is set to "1" when an arithmetic operation results in overflow; otherwise, cleared to "0".
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared
to "0" when the interrupt is acknowledged.
12
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
The interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected
when this flag is "1".
This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has a priority greater than the processor interrupt priority level (IPL), the inter-
rupt is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b15
b0
IPL
Flag register (FLG)
U
I
O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.4.2. Flag register (FLG)
13
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See "Software Reset" for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level "L" (0.2VCC max.) for at least 20 cycles of f(XIN). When the reset pin level is then returned to
the "H" level while main clock is stable, the reset status is released and program execution resumes from
the address in the reset vector table.
Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.
5V
4.2V
V
CC
0V
5V
V
CC
RESET
RESET
0V
0.8V
Example when VCC = 5V
.
20 cycles or more of XIN are needed.
Figure 1.5.1. Example reset circuit
XIN
More than 20 cycles are needed
BCLK 24cycles
Microprocessor
mode BYTE = "H"
RESET
BCLK
Address
RD
Content of reset vector
FFFFC16
FFFFD16
FFFFE16
WR
"H"
CS0
Microprocessor
mode BYTE = "L"
Content of reset vector
FFFFC16
FFFFE16
Address
RD
WR
"H"
CS0
Single chip
mode
FFFFC16
Content of reset vector
Address
(Note)
FFFFE16
Note: This is the internal address signal.
The address signal is not outputted to the external.
Figure 1.5.2. Reset sequence
14
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
____________
Table 1.5.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.5.3 to 1.5.5
show the internal status of the microcomputer immediately after the reset ha been released.
____________
Table 1.5.1. Pin status when RESET pin level is "L"
Status
CNVSS = VCC
Pin name
CNVSS = VSS
BYTE = VSS
Data input (floating)
BYTE = VCC
Data input (floating)
P0
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
P1
Data input (floating)
Input port (floating)
P2, P3, P4
0
to P4
3
Address output (undefined)
Address output (undefined)
P4
4
5
CS0 output ("H" level is output) CS0 output ("H" level is output)
P4
to P4
7
Input port (floating)
(pull-up resistor is on)
Input port (floating)
(pull-up resistor is on)
Input port (floating)
P5
0
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
WR output ("H" level is output) WR output ("H" level is output)
BHE output (undefined) BHE output (undefined)
RD output ("H" level is output) RD output ("H" level is output)
BCLK output BCLK output
P5
P5
P5
1
2
3
HLDA output (The output value HLDA output (The output value
P54
Input port (floating)
depends on the input to the
HOLD pin)
depends on the input to the
HOLD pin)
P5
P5
P5
5
6
7
Input port (floating)
Input port (floating)
Input port (floating)
HOLD input (floating)
HOLD input (floating)
ALE output ("L" level is output) ALE output ("L" level is output)
RDY input (floating)
Input port (floating)
RDY input (floating)
Input port (floating)
P6, P7, P8
0 to P84,
Input port (floating)
P8 , P8 , P9, P10
6
7
15
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
…
…
…
…
…
…
…
…
…
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
UART2 receive interrupt control register
(1) Processor mode register 0 (Note 1) (000416
)
)
)
)
)
)
)
)
0016
(005016
(005116
(005216
(005316
(005416
(005516
(005616
(005716
(005816
(005916
(005A16
(005B16
)
)
)
)
)
)
)
)
)
)
)
)
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
…
…
…
…
…
…
…
…
(2) Processor mode register 1
(000516
(000616
(000716
(000816
(000916
(000A16
(000C16
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
(3) System clock control register 0
(4) System clock control register 1
(5) Chip select control register
1 0
0 0
0 0
0
0
0
0
0
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT0 interrupt control register
Address match interrupt
enable register
(6)
(7) Protect register
0
(8)
Oscillation stop detect register
Watchdog timer control register
Address match interrupt register 0
0016
…
(9)
(000F16
(001016
(001116
(001216
(001416
(001516
(001616
)
0
0
0
?
? ?
?
0
?
0
…
(10)
)
0016
0016
…
…
…
…
…
)
)
)
)
)
0 0
(11)
(005C16
)
Address match interrupt register 1
DMA0 control register
0016
0016
…
(005D16
)
0
0
0
0
0
0
0
…
INT1 interrupt control register
(005E16
(005F16
(01C016
(01C816
(01C916
(01CA16
(01CB16
(01DB16
)
0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
…
…
…
…
INT2 interrupt control register
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
)
(002C16
)
0
0
0
0
0
0
0
0
0 ?
0 ?
…
…
…
…
…
…
Timer B3,4,5 count start flag
)
)
)
)
)
)
0 0
DMA1 control register
(003C16
)
CAN0/1 wake up interrupt
control register
CAN0 successful reception
interrupt control register
CAN0 successful transmission
interrupt control register
Three-phase PWM control register 0
Three-phase PWM control register 1
Three-phase output buffer register 0
Three-phase output buffer register 1
Timer B3 mode register
0016
0016
(004116
(004216
(004316
)
?
?
0
0
(Note2)
…
…
)
0
0
0
0
0
0 0
0 0
0
0
0
0
)
? 0
…
…
…
…
…
…
…
…
INT3 interrupt control register
(004416
(004516
(004616
(004716
(004816
(004916
(004A16
(004B16
)
0
0
?
?
?
0 0
Timer B5 interrupt control register
Timer B4 interrupt control register
Timer B3 interrupt control register
)
)
)
)
)
)
)
0
0
0
0
0
0
0
0 ?
0 ?
0 ?
0
0
0
0
0 0
0 0
0 0
…
Timer B4 mode register
Timer B5 mode register
(51)
(52)
(01DC16
(01DD16
)
0
0
0
0
0
…
? 0
)
CAN1 successful reception
interrupt control register (Note 2)
CAN1 successful transmission
interrupt control register (Note 2)
Bus collision detection interrupt
control register
…
0 0
?
0
(53) Interrupt cause select register0
(54) Interrupt cause select register1
(01DE16
)
0
0
…
0
0
? 0
? 0
? 0
? 0
? 0
? 0
? 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(01DF16
)
0016
4016
…
(55)
(01E216
)
S I/O3 control register
DMA0 interrupt control register
…
(56)
(01F616
)
)
0016
0016
0016
UART2 special mode register 2
…
…
…
…
…
DMA1 interrupt control register
CAN0/1 error interrupt control
register
A-D conversion interrupt
control register
(004C16
(004D16
(004E16
)
(57)
(01F716
UART2 special mode register
…
…
…
(58)
(01F816
)
)
)
UART2 transmit/receive mode register
(Note 2)
(59)
UART2 transmit/receive control register 0 (01FC16
)
)
0
0
0 0
0 0
0
0
1
0
0
0
0 0
1 0
UART2 transmit interrupt
control register
(60)
UART2 transmit/receive control register 1 (01FD16
(004F16
)
x : Nothing is mapped to this bit
? : Undefined
The RAM is indeterminate at power on. The initial value must therefore be defined. When a reset signal is input while the CPU is writing a value to the RAM,
the value may be changed to an unintended value.
Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at reset.
Note 2: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.5.3. Device's internal status after a reset is cleared
16
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
…
…
…
…
…
…
…
…
…
…
…
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
(61) CAN0 message control register 0
(020016
(020116
(020216
(020316
(020416
(020516
(020616
(020716
(020816
(020916
)
)
)
)
)
)
)
)
)
)
…
(86) CAN1 message control register 0 (Note) (022016
(87) CAN1 message control register 1 (Note) (022116
(88) CAN1 message control register 2 (Note) (022216
(89) CAN1 message control register 3 (Note) (022316
(90) CAN1 message control register 4 (Note) (022416
(91) CAN1 message control register 5 (Note) (022516
(92) CAN1 message control register 6 (Note) (022616
(93) CAN1 message control register 7 (Note) (022716
(94) CAN1 message control register 8 (Note) (022816
(95) CAN1 message control register 9 (Note) (022916
)
)
)
)
)
)
)
)
)
)
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
(62) CAN0 message control register 1
(63) CAN0 message control register 2
(64) CAN0 message control register 3
(65) CAN0 message control register 4
(66) CAN0 message control register 5
(67) CAN0 message control register 6
(68) CAN0 message control register 7
(69) CAN0 message control register 8
(70) CAN0 message control register 9
(71) CAN0 message control register 10
(72) CAN0 message control register 11
(73) CAN0 message control register 12
(74) CAN0 message control register 13
(75) CAN0 message control register 14
(76) CAN0 message control register 15
(77) CAN0 control register
…
…
…
…
…
…
…
…
…
…
(020A16
)
(96) CAN1 message control register 10 (Note) (022A16
)
…
(020B16
)
…
(97) CAN1 message control register 11 (Note) (022B16
)
…
(020C16
)
…
(98) CAN1 message control register 12 (Note) (022C16
)
…
(020D16
)
…
(99) CAN1 message control register 13 (Note) (022D16
)
…
…
…
(020E16
)
…
(100) CAN1 message control register 14 (Note) (022E16
)
(020F16
(021016
(021116
)
…
…
…
(101) CAN1 message control register 15 (Note) (022F16
)
0 0
0
0
0
0
0
0
0 1
0 0
)
(102) CAN1 control register
(Note) (023016
(023116
)
0 0
0
0
0
0
0
0
0 1
0 0
…
)
)
…
0016
(78) CAN0 status register
(021216
(021316
)
…
(103) CAN1 status register
(Note) (023216
(023316
)
0016
…
0 0
0
0
0
0 1
)
…
)
0 0
0
0
0
0 1
…
0016
0016
0016
0016
0016
0016
(79) CAN0 slot status register
(80) CAN0 interrupt control register
(81) CAN0 extended register
(82) CAN0 configuration register
(021416
(021516
(021616
(021716
)
…
(104) CAN1 slot status register
(105) CAN1 interrupt control register
(106) CAN1 extended register
(107) CAN1 configuration register
(Note) (023416)
0016
0016
0016
0016
0016
0016
…
)
…
…
…
(023516
(Note) (023616
(023716
)
…
…
)
)
)
)
…
(021816
(021916
(021A16
)
…
(Note) (023816
)
…
)
…
(023916
)
…
?
?
? ?
? ?
?
?
?
?
?
?
? ?
? ?
)
…
(Note) (023A16
)
?
?
? ?
? ?
?
?
?
?
?
?
? ?
? ?
…
(021B16
(021C16
(021D16
)
…
(023B16
)
…
0016
0016
0016
0016
(83) CAN0 receive error count register
(84) CAN0 transmit error count register
(85) CAN0 time stamp register
)
…
(108) CAN1 receive error count register (Note) (023C16
)
0016
0016
0016
0016
…
…
)
…
(109) CAN1 transmit error count register (Note) (023D16
)
(021E16
)
…
(110) CAN1 time stamp register
(Note) (023E16
)
…
(021F16
)
…
(023F16
)
x : Nothing is mapped to this bit
? : Undefined
The RAM is indeterminate at power on. The initial value must therefore be defined. When a reset signal is input while the CPU is writing a value to the RAM,
the value may be changed to an unintended value.
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.5.4. Device's internal status after a reset is cleared
17
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
…
…
0016
0016
0016
(111) Peripheral function clock select register (025E16
)
0 0 0 0 0 ? ? ?
(138) A-D control register 0
(03D616
)
…
…
…
(112) CAN0/1 clock select register
(Note 3) (025F16
)
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
(139) A-D control register 1
(03D716
)
…
)
(113) Count start flag
(038016
(038116
(038216
(038316
(038416
(039616
(039716
(039816
(039916
(140) D-A control register
(03DC16)
…
…
…
…
…
…
…
…
…
…
…
…
…
…
(114) Clock prescaler reset flag
(115) One-shot start flag
)
)
)
)
)
)
)
)
0
0
(141) Port P0 direction register
(142) Port P1 direction register
(143) Port P2 direction register
(144) Port P3 direction register
(145) Port P4 direction register
(146) Port P5 direction register
(147) Port P6 direction register
(148) Port P7 direction register
(149) Port P8 direction register
(150) Port P9 direction register
(151) Port P10 direction register
(152) Pull-up control register 0
(03E216
(03E316
(03E616
(03E716
)
0
0
0
0
0 0
)
)
)
(116) Trigger select flag
0016
0016
0016
0016
0016
0016
0016
(117) Up-down flag
(118) Timer A0 mode register
(119) Timer A1 mode register
(120) Timer A2 mode register
(121) Timer A3 mode register
(122) Timer A4 mode register
(123) Timer B0 mode register
(124) Timer B1 mode register
(125) Timer B2 mode register
(03EA16
(03EB16
(03EE16
)
…
)
)
…
…
…
…
…
…
(03EF16
)
(039A16
)
0
0
0 0 0 0 0
(03F216
(03F316
(03F616
)
…
)
(039B16
0
0
0
0 ? 0
0 ?
0
0
0
0
0
0
0 0
0 0
0 0
)
)
0016
0016
0016
0016
0016
0016
…
)
(039C16
…
)
(039D16
0 ?
(03FC16)
…
…
…
…
…
…
(126) UART0 transmit/receive mode register (03A016
(127) UART0 transmit/receive control register 0(03A416
(128) UART0 transmit/receive control register 1(03A516
(129) UART1 transmit/receive mode register (03A816
)
)
)
)
0016
(153) Pull-up control register 1 (Note1) (03FD16)
…
0
0
0 0
0 0
0
0
1
0
0
0
0 0
1 0
(154) Pull-up control register 2
(155) Port control register
(03FE16)
…
(03FF16
)
0016
(156) Data registers (R0/R1/R2/R3)
(157) Address registers (A0/A1)
(158) Frame base register (FB)
(159) Interrupt table register (INTB)
(160) User stack pointer (USP)
(161) Interrupt stack pointer (ISP)
(162) Static base register (SB)
(163) Flag register (FLG)
000016
000016
000016
(130) UART1 transmit/receive control register 0(03AC16
)
0
0
0 0
0 0
0 0
0
0
0
1
0
0
0
0
0
0 0
1 0
0 0
…
)
(131) UART1 transmit/receive control register 1(03AD16
…
)
(132) UART transmit/receive control register 2 (03B016
(133) Flash memory control register 1 (Note2) (03B616
(134) Flash memory control register 0 (Note2) (03B716
0000016
000016
000016
000016
000016
…
)
?
? ? ? ? 0 ? ?
…
)
0
0
0
0
0 1
…
)
(135) DMA0 cause select register
(136) DMA1 cause select register
(137) A-D control register 2
(03B816
0016
0016
0
…
)
(03BA16
…
)
0
0
0
(03D416
x : Nothing is mapped to this bit
? : Undefined
The RAM is indeterminate at power on. The initial value must therefore be defined. When a reset signal is input while the CPU is writing a value to the RAM,
the value may be changed to an unintended value.
Note 1: When the VCC level is applied to the CNVSS pin, it is 0216 at a reset.
Note 2: These registers are available on the flash version only.
Note 3: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.5.5. Device's internal status after a reset is cleared
18
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
000016
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001216
001316
001416
001616
001716
001F16
002016
002216
002316
002416
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002F16
003016
003216
003316
003416
003616
003716
003816
003916
003A16
003B16
003C16
003D16
004016
004116
004216
004316
004416
004516
004616
004716
005216
005316
005416
005516
005616
005716
005816
005916
005A16
005B16
005C16
005D16
005E16
005F16
006016
006F16
007016
007F16
008016
008F16
009016
009F16
00A016
00AF16
00B016
00BF16
00C016
00CF16
00D016
00DF16
00E016
00EF16
00F016
00FF16
010016
010F16
011016
011F16
012016
012F16
013016
013F16
014016
014F16
015016
015F16
016016
016516
016616
016B16
016C16
017116
017216
01BF16
01C016
01C116
01C216
01C316
01C416
01C516
01C616
01C716
01C816
01C916
01CA16
01CB16
01CC16
01CD16
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
Processor mode register 0 (PM0)
Processor mode register 1 (PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Oscillation stop detection register (CM2)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
CAN0 message box 0: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 1: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 2: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 3: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 4: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 5: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 6: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 7: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 8: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 9: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 10: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 11: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 12: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 13: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 14: Identifier / DLC, Data Field, Time Stamp
CAN0 message box 15: Identifier / DLC, Data Field, Time Stamp
CAN0 global mask (C0GMR)
Address match interrupt register 1 (RMAD1)
DMA0 source pointer (SAR0)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA1 control register (DM1CON)
CAN0/1 Wake Up interrupt control register (C01WKIC) (Note1)
CAN0 successful reception interrupt control register (C0RECIC)
CAN0 successful transmission interrupt control register (C0TRMIC)
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
CAN1 successful reception interrupt control register (C1RECIC)
INT5 interrupt control register (INT5IC)
CAN1 successful transmission interrupt control register (C1TRMIC)
SIO3 interrupt control register (S3IC)
CAN0 local mask A (C0LMAR)
CAN0 local mask B (C0LMBR)
Timer B3, 4, 5 count start flag (TBSR)
004816
(Note1)
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Timer A4-1 register (TA41)
004916
INT4 interrupt control register (INT4IC)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC)
(Note1)
004A16
004B16
004C16
004D16
DMA1 interrupt control register (DM1IC)
CAN0/1 error interrupt control register (C01ERRIC)
A-D conversion interrupt control register (ADIC)
Key input interrupt control register (KUPIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
(Note1)
Three-phase PWM control register 0 (INVC0)
Three-phase PWM control register 1 (INVC1)
Three-phase output buffer register 0 (IDB0)
Three-phase output buffer register 1 (IDB1)
Dead time timer (DTT)
004E16
004F16
005016
005116
Timer B2 interrupt occurrence frequency set counter (ICTB2)
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.1. Location of peripheral unit control registers (1)
19
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
01CE16
01CF16
01D016
01D116
01D216
01D316
01D416
01D516
01D616
01DA16
01DB16
01DC16
01DD16
01DE16
01DF16
01E016
01E116
01E216
01E316
01E416
01F516
01F616
01F716
01F816
01F916
01FA16
01FB16
01FC16
01FD16
01FE16
01FF16
020016
020116
020216
020316
020416
020516
020616
020716
020816
020916
020A16
020B16
020C16
020D16
020E16
020F16
021016
021116
021216
021316
021416
021516
021616
021716
021816
021916
021A16
021B16
021C16
021D16
021E16
021F16
022016
022116
022216
022316
022416
022516
022616
022716
022816
022916
022A16
022B16
022C16
022D16
022E16
022F16
023016
023116
023216
023316
023416
023516
023616
023716
023816
023916
023A16
023B16
023C16
023D16
023E16
023F16
024016
024116
024216
024316
024416
024516
024616
025D16
025E16
025F16
026016
026F16
027016
027F16
028016
028F16
029016
029F16
02A016
02AF16
02B016
02BF16
02C016
02CF16
02D016
02DF16
02E016
02EF16
02F016
02FF16
030016
030F16
031016
031F16
032016
032F16
033016
033F16
034016
034F16
035016
035F16
CAN1 message control register 5 (C1MCTL5)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
CAN1 message control register 6 (C1MCTL6)
CAN1 message control register 7 (C1MCTL7)
CAN1 message control register 8 (C1MCTL8)
CAN1 message control register 9 (C1MCTL9)
CAN1 message control register 10 (C1MCTL10)
CAN1 message control register 11 (C1MCTL11)
CAN1 message control register 12 (C1MCTL12)
CAN1 message control register 13 (C1MCTL13)
CAN1 message control register 14 (C1MCTL14)
CAN1 message control register 15 (C1MCTL15)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
Interrupt cause select register 0 (IFSR0)
Interrupt cause select register 1 (IFSR1)
S I/O3 transmit/receive register (S3TRR)
CAN1 control register (C1CTLR)
CAN1 status register (C1STR)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
CAN1 slot status register (C1SSTR)
CAN1 interrupt control register (C1SICR)
CAN1 extended register (C1IDR)
CAN1 configuration register (C1CONR)
S I/O3 control register (S3C)
S I/O3 bit rate generator (S3BRG)
UART2 special mode register 2 (U2SMR2)
UART2 special mode register (U2SMR)
UART2 transmit/receive mode register (U2MR)
UART2 bit rate generator (U2BRG)
CAN1 receive error count register (C1RECR)
CAN1 transmit error count register (C1TECR)
(Note1)
(Note1)
UART2 transmit buffer register (U2TB)
CAN1 time stamp register (C1STR)
(Note1)
UART2 transmit/receive mode register 0 (U2C0)
UART2 transmit/receive mode register 1 (U2C1)
UART2 receive buffer register (U2RB)
CAN0 acceptance filter support register (C0AFS)
CAN1 acceptance filter support register (C1AFS)
CAN0 message control register 0 (C0MCTL0)
CAN0 message control register 1 (C0MCTL1)
CAN0 message control register 2 (C0MCTL2)
CAN0 message control register 3 (C0MCTL3)
CAN0 message control register 4 (C0MCTL4)
CAN0 message control register 5 (C0MCTL5)
CAN0 message control register 6 (C0MCTL6)
CAN0 message control register 7 (C0MCTL7)
CAN0 message control register 8 (C0MCTL8)
CAN0 message control register 9 (C0MCTL9)
CAN0 message control register 10 (C0MCTL10)
CAN0 message control register 11 (C0MCTL11)
CAN0 message control register 12 (C0MCTL12)
CAN0 message control register 13 (C0MCTL13)
CAN0 message control register 14 (C0MCTL14)
CAN0 message control register 15 (C0MCTL15)
(Note1)
(Note1)
Peripheral function clock select register (PCLKR)
CAN0/1 clock select register (CCLKR)
CAN1 message box 0: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 1: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 2: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 3: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 4: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 5: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 6: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 7: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 8: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 9: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 10: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 11: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 12: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 13: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 14: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN1 message box 15: Identifier / DLC, Data Field, Time Stamp (Note1)
CAN0 control register (C0CTLR)
CAN0 status register (C0STR)
CAN0 slot status register (C0SSTR)
CAN0 interrupt control register (C0ICR)
CAN0 extended register (C0IDR)
CAN0 configuration register (C0CONR)
CAN0 receive error count register (C0RECR)
CAN0 transmit error count register (C0TECR)
CAN0 time stamp register (C0STR)
CAN1 message control register 0 (C1MCTL0)
CAN1 message control register 1 (C1MCTL1)
CAN1 message control register 2 (C1MCTL2)
CAN1 message control register 3 (C1MCTL3)
CAN1 message control register 4 (C1MCTL4)
(Note1)
(Note1)
(Note1)
(Note1)
(Note1)
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.2. Location of peripheral unit control registers (2)
20
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
SFR
036016
036516
036616
036B16
036C16
037116
037216
037F16
038016
038116
038216
038316
038416
038516
038616
038716
038816
038916
038A16
038B16
038C16
038D16
038E16
038F16
039016
039116
039216
039316
039416
039516
039616
039716
039816
039916
039A16
039B16
039C16
039D16
039E16
039F16
03A016
03A116
03A216
03A316
03A416
03A516
03A616
03A716
03A816
03A916
03AA16
03AB16
03AC16
03AD16
03AE16
03AF16
03B016
03B116
03B516
03B616
03B716
03B816
03B916
03BA16
03BB16
03BC16
03BD16
03BE16
03BF16
03C016
03C116
03C216
03C316
03C416
03C516
03C616
03C716
03C816
03C916
03CA16
03CB16
03CC16
03CD16
03CE16
03CF16
03D016
03D316
03D416
03D516
03D616
03D716
03D816
03D916
03DA16
03DB16
03DC16
03DD16
03DF16
03E016
03E116
03E216
03E316
03E416
03E516
03E616
03E716
03E816
03E916
03EA16
03EB16
03EC16
03ED16
03EE16
03EF16
03F016
03F116
03F216
03F316
03F416
03F516
03F616
03F716
03FB16
03FC16
03FD16
03FE16
03FF16
CAN1 global mask (C1GMR)
CAN1 local mask A (C1LMAR)
CAN1 local mask B (C1LMBR)
(Note1)
(Note1)
(Note1)
CRC data register (CRCD)
CRC input register (CRCIN)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
A-D register 7 (AD7)
Count start flag (TABSR)
Clock prescaler reset flag (CPSRF)
One-shot start flag (ONSF)
Trigger select register (TRGSR)
Up-down flag (UDF)
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
Timer A3 register (TA3)
Timer A4 register (TA4)
Timer B0 register (TB0)
Timer B1 register (TB1)
Timer B2 register (TB2)
A-D control register 2 (ADCON2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
D-A control register (DACON)
Port P0 register (P0)
Port P1 register (P1)
Port P0 direction register (PD0)
Port P1 direction register (PD1)
Port P2 register (P2)
Port P3 register (P3)
UART0 transmit/receive mode register (U0MR)
UART0 bit rate generator (U0BRG)
Port P2 direction register (PD2)
Port P3 direction register (PD3)
Port P4 register (P4)
UART0 transmit buffer register (U0TB)
Port P5 register (P5)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
Port P4 direction register (PD4)
Port P5 direction register (PD5)
Port P6 register (P6)
UART0 receive buffer register (U0RB)
Port P7 register (P7)
UART1 transmit/receive mode register (U1MR)
UART1 bit rate generator (U1BRG)
Port P6 direction register (PD6)
Port P7 direction register (PD7)
Port P8 register (P8)
UART1 transmit buffer register (U1TB)
Port P9 register (P9)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
Port P8 direction register (PD8)
Port P9 direction register (PD9)
Port P10 register (P10)
UART1 receive buffer register (U1RB)
UART transmit/receive control register 2 (UCON)
Port P10 direction register (PD10)
Flash memory control register 1 (FMR1)
Flash memory control register 0 (FMR0)
DMA0 cause select register (DM0SL)
(Note2)
(Note2)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
DMA1 cause select register (DM1SL)
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: These registers are available on the flash version only.
Note 3: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.3. Location of peripheral unit control registers (3)
21
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Software Reset
Software Reset
Writing "1" to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.
Processor Mode
(1) Processor mode types
One of three processor modes can be selected: single-chip mode, memory expansion mode and micro-
processor mode. The functions of some pins, the memory map and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus width and register settings. (See "Bus
Settings" for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus width and register settings. (See "Bus
Settings" for details.)
(2) Setting processor modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to "102".
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Do not change the
processor mode bits simultaneously with other bits when changing the processor mode bits "012" or
"112". Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from
the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing "012" to the processor mode bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.7.1 shows the processor mode register 0 and 1.
Figure 1.7.2 shows the memory maps applicable for each of the modes when memory area dose not be
expanded (normal mode).
22
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 0 (Note 1)
Symbol
PM0
Address
000416
When reset
0016 (Note 2)
b7 b6 b5 b4 b3 b2 b1 b0
R
W
Bit symbol
Bit name
Function
b1 b0
Processor mode bit
PM00
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
PM01
PM02
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
R/W mode select bit
Software reset bit
PM03
PM04
The device is reset when this bit is set
to "1". The value of this bit is "0" when
read.
b5 b4
Multiplexed bus space
select bit
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
PM05
PM06
0 : Address output
1 : Port function
Port P40 to P43 function
select bit (Note 3)
(Address is not output)
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
BCLK output disable bit
(Note 3)
PM07
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new
values to this register.
Note 2: If the VCC voltage is applied to the CNVSS, the value of this register when
reset is 0316. (PM00 and PM01 both are set to "1".)
Note 3: Valid in microprocessor and memory expansion modes. In single-chip mode,
ports P4 to P4 are not used for address output and BCLK is not output.
0
3
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an
8-bit width.The processor operates using the separate bus after reset is revoked,
space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is
chosen, so only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
000516
When reset
00000XX0
2
0
0
0
0
R W
Bit symbol
Reserved bit
Bit name
Function
Must always be set to 0
Nothing is assigned.
In an attempt to write to these bits, write 0 . The value, if read, turns
out to be indeterminate.
0: The same internal reserved
area as that of M16C/60,
M16C/61 and M16C/62 group
1: Expands the internal ROM area
up to 256K bytes respectively.
(Note 2)
PM13
Internal reserved area
expansion bit (Note 2)
Reserved bits
PM17
Must always be set to "0"
0 : No wait state
1 : Wait state inserted
Wait bit
Note 1: Set bit 1 of the protect register (address 000A16 ) to "1" when writing new values
to this register.
Note 2: Be sure to set this bit to 0 except for products whose ROM size exceeds 192K bytes.
Set this bit to "1" for M306NAMG and M306NAFG.
Specify D000016 or a subsequent address as a reset address in the fixed
vector table.
Figure 1.7.1. Processor mode register 0 and 1
23
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Memory maps in each processor mode (Internal reserved area expansion bit PM13 is "0")
Single-chip mode
Memory expansion mode
Microprocessor mode
0000016
0040016
SFR area
SFR area
SFR area
Internal
Internal
Internal
RAM area
RAM area
RAM area
XXXXX16
0400016
Internally reserved
area
Internally reserved
area
External
area
External
area
Inhibited
D000016
YYYYY16
Internally reserved
area (Note)
Internal
Internal
ROM area
ROM area
FFFFF16
Memory maps in each processor mode (Internal reserved area expansion bit PM13 is "1")
Microprocessor mode
Single-chip mode
Memory expansion mode
0000016
0040016
SFR area
SFR area
SFR area
Internal
Internal
Internal
RAM area
RAM area
RAM area
XXXXX16
0600016
Internally reserved
area
Internally reserved
area
External
area
External
area
Inhibited
C000016
YYYYY16
Internally reserved
area
Internal
Internal
ROM area
ROM area
FFFFF16
External area: Accessing this area allows the user to access a device connected
externally to the microcomputer
.
Address XXXXX16
Address YYYYY16
PM13 = 0 PM13 = 1
Type No.
PM13 = 0
PM13 = 1
017FF16
E000016
E000016
D000016
D000016
M306NBMCT/FCT
M306NAMCT
M306NAMGT
M306NAFGT
017FF16
02BFF16
02BFF16
C000016
C000016
Note: When YYYYY16 is lower than D000016 (products with more than 192 Kbytes of ROM),
internal ROM in the range of YYYYY16 to CFFFF16 cannot be accessed when PM13 is "0".
Figure 1.7.2. Memory maps in each processor mode
24
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Internal reserved area expansion bit (PM13) = "0"
Internal reserved area expansion bit (PM13) = "1"
Microprocessor mode
Memory expansion mode
Microprocessor mode
Memory expansion mode
0000016
0000016
SFR area (1 Kbytes)
SFR area (1 Kbytes)
SFR area (1 Kbytes)
SFR area (1 Kbytes)
0040016
0040016
Internal RAM
area
Internal RAM
area
Internal RAM
area
Internal RAM
area
XXXXX16
0400016
XXXXX16
Internal reserved area
Internal reserved area
Internal reserved area
Internal reserved area
0600016
0800016
0800016
2800016
3000016
2800016
3000016
External
area
External
area
External
area
External
area
BFFFF16
C000016
CFFFF16
D000016
Internal reserved area
Internal reserved area
YYYYY16
YYYYY16
Internal ROM
area (Note)
Internal ROM
area
FFFFF16
FFFFF16
External area :
Accessing this area allows the user to
access a device connected externally
to the microcomputer.
Chip
select
PM13
Address range
0
1
3000016 to CFFFF16 (640Kbytes)
3000016 to BFFFF16 (576Kbytes)
2800016 to 2FFFF16 (32Kbytes)
0800016 to 27FFF16 (128Kbytes)
0400016 to 07FFF16 (16Kbytes)
CS0
CS1
CS2
Address XXXXX16
PM13 = 0 PM13 = 1 PM13 = 0
017FF16 E000016
E000016
Address YYYYY16
Type No.
PM13 = 1
0
M306NBMCT/FCT
M306NAMCT
CS3
CS0
1
0
0600016 to 07FFF16
(8Kbytes)
017FF16
02BFF16
02BFF16
3000016 to FFFFF16 (832Kbytes)
3000016 to FFFFF16 (832Kbytes)
2800016 to 2FFFF16 (32Kbytes)
0800016 to 27FFF16 (128Kbytes)
0400016 to 07FFF16 (16Kbytes)
M306NAMGT
M306NAFGT
D000016
D000016
C000016
C000016
1
CS1
CS2
Note: When YYYYY16 is lower than D000016 (products with
more than 192 Kbytes of ROM), internal ROM in the
range of YYYYY16 to CFFFF16 cannot be accessed.
0
1
CS3
0600016 to 07FFF16
(8Kbytes)
Figure 1.7.3. Memory location and chip select area in each processor mode
Internal Reserved Area Expansion Bit (PM13)
This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In
M306NAMGT/FGT, for example, to set this bit to "1" expandes the internal ROM area to 256 Kbytes
respectively. Refer to Figure 1.7.2 and 1.7.3 for the chip select area. When the reset is revoked, this bit is
set to "0". To expand the internal area, set this bit to "1" in user program. And the top of user program
must be allocated to D000016 or subsequent address.
In the case of the product in which the internal ROM is 192 Kbytes or less set this bit to "0" when this
product is used in the memory expansion mode or the microprocessor mode. When the product is used in
the single chip mode, the internal area is not expanded and any action is not affected, even if this bit is set
to "1".
25
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 1.8.1 shows the factors used to change the bus settings.
Table 1.8.1. Factors for switching bus settings
Bus setting
Switching factor
Bit6 of processor mode register0
BYTE pin
Switching external address bus width
Switching external data bus width
Switching between separate and multiplex bus
Bits4 and 5 of processor mode register0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes
address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to
"1", the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to
P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to "0", the
external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is "L", the bus width is set to 16 bits; when "H", it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.) While operating, fix the BYTE pin either to "H" or to "L".
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is "H", the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is "L", the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
"H"), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = "L"), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer's even addresses (every 2nd address). To access these external de-
vices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
______
Before using the multiplex bus for access, always set the CSi wait bit of the chip select control register
to "0".
In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected, address bus range
is 256 bytes in each chip select.
26
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Table 1.8.2. Pin functions for each processor mode
Single-chip
Memory
expansion mode
Processor mode
Memory expansion mode/microprocessor modes
mode
Multiplexed bus and
separate bus
Multiplexed
bus (Note 1)
separate bus
External bus type
Multiplexed bus
space select bit
"01", "10"
Either CS1 or CS2 is for multiplexed
bus and others are for separate bus.
"00"
Separate bus
"11" (Note 2)
Multiplexed bus for
the entire space
Data bus width
BYTE pin level
16 bits
= "L"
8 bits
= "H"
8 bits
= "H"
16 bits
= "L"
8 bits
= "H"
P00
to P0
7
I/O port
Data bus
Data bus
Data bus
Data bus
I/O port
(Note 3)
P1
0
to P1
7
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
Data bus
I/O port
Data bus
I/O port
P2
0
Address bus
/data bus(Note 4)
Address bus
Address bus
Address bus
Address bus
Address bus
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
Address bus
/data bus
P2
1
0
to P2
7
Address bus
/data bus(Note 4) /data bus (Note 4)
Address bus
Address bus
/data bus
P3
Address bus
Address bus
I/O port
Address bus
/data bus (Note 4)
A8/D7
P3
1
to P3
7
Address bus
I/O port
I/O port
I/O port
P4
Port P4
0
to P4
3
0
to P43
function select bit = "1"
P4
0
to P4
3
I/O port
Address bus
Address bus
Address bus
Address bus
I/O port
Port P4
0
to P43
function select bit = "0"
P4
P5
P5
P5
4
0
4
5
to P4
7
3
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
CS (chip select) or programmable I/O port
(For details, refer to "Bus control")
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to "Bus control")
to P5
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
HLDA
HOLD
ALE
P5
6
7
P5
RDY
RDY
RDY
RDY
RDY
Note 1: In memory expansion mode, do not select a 16-bit multiplex bus.
Note 2: In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected, address bus range is 256 bytes
in each chip select.
Note 3: These ports don’t function as A-D converter input pins.
Note 4: Address bus when in separate bus mode.
27
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is "H", the 8 ports D0 to D7 function as
the data bus. When BYTE is "L", the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed. Also,
when a change is made from single-chip mode to memory expansion mode, the value of the address bus
is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select
control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to
P47 function as programmable I/O ports regardless of the value in the chip select control register.
______
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled.
______
______
CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 1.9.1 shows
______
the external memory areas specified using the chip select signal. Note that the address ranges for CS0 and
______
CS3 vary according to processor mode and setting of the internal reserved area expansion bit (PM13).
Table 1.9.1. External areas specified by the chip select signals
Address range
Chip select
CS0
PM13
Memory expansion mode
Microprocessor mode
3000016 to CFFFF16 (640Kbytes)
3000016 to BFFFF16 (576Kbytes)
2800016 to 2FFFF16 (32Kbytes)
0800016 to 27FFF16 (128Kbytes)
3000016 to FFFFF16 (832Kbytes)
3000016 to FFFFF16 (832Kbytes)
2800016 to 2FFFF16 (32Kbytes)
0800016 to 27FFF16 (128Kbytes)
0
1
CS1
CS2
0
1
0400016 to 07FFF16
0600016 to 07FFF16
(16Kbytes)
(8Kbytes)
0400016 to 07FFF16
0600016 to 07FFF16
(16Kbytes)
(8Kbytes)
CS3
28
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Chip select control register
Symbol
CSR
Address
000816
When reset
0116
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
CS0
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Wait state inserted
1 : No wait state
Figure 1.9.1. Chip select control register
The timing of the chip select signal changing to "L" (active) is synchronized with the address bus. But the
timing of the chip select signal changing to "H" depends on the area which will be accessed in the next
cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal.
29
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Example 2) After access the external area, only the chip select signal
Example 1) After access the external area, both the address signal and
changes in the next cycle (the address bus does not change).
the chip select signal change concurrently in the next cycle.
In this example, an access to the internal ROM or the internal RAM in the
next cycle will occur, after access to the external area. In this case, the
chip select signal changes between the two cycles, but the address does
not change.
In this example, after access to the external area(i), an access to the area
indicated by the other chip select signal(j) will occur in the next cycle. In
this case, both the address bus and the chip select signal change between
the two cycles.
Access to the
External Area( i ) External Area( j )
Access to the Other
Access to the
External Area
Internal ROM/RAM
Access
BCLK
BCLK
Read/Write
signal
Read/Write
signal
Data bus
Data bus
Data
Data
Address
Address bus
Address bus
Chip select
Address
Chip select
(CS i)
Chip select
(CS j)
Example 3) After access the external area, only the address bus changes
in the next cycle (the chip select signal does not change).
Example 4) After access the external area, either the address signal and
the chip select signal do not change in the next cycle.
In this example, after access to the external area(i), an access to the area
indicated by the same chip select signal(i) will occur in the next cycle. In
this case, the address bus changes between the two cycles, but the chip
select signal does not change.
In this example, any access to any area does not occur in the next cycle
(either instruction prefetch does not occur). In this case,either the address
bus and chip select signal do not change between the two cycles.
Access to the
External Area( i ) External Area( i )
Access to the Same
Access to the
No Access
External Area
BCLK
BCLK
Read/Write
signal
Read/Write
signal
Data bus
Data bus
Data
Address
Data
Address bus
Address bus
Chip select
Address
Chip select
(CS i)
Note : These examples show the address bus and chip select signal within the successive two cycles.
According to the combination of these examples, the chip select can be elongated to over 2cycles.
Figure 1.9.2. Output examples about address bus and chip select signal (separated bus without
wait)
30
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(3) Read/write signals
With a 16-bit data bus (BYTE pin = "L"), bit 2 of the processor mode register 0 (address 000416) selects
_____ _______
______
_____ ________
_________
the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus
_____ ______
_______
(BYTE pin = "H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode
register 0 (address 000416) to "0".) Tables 1.9.2 and 1.9.3 show the operation of these signals.
_____ ______
_______
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ ________
_________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to "1".
_____ ________
________
Table 1.9.2. Operation of RD, WRL, and WRH signals
Data bus width
Status of external data bus
RD
L
WRL
H
L
WRH
H
H
L
Read data
H
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
16-bit
(BYTE = "L")
H
H
L
H
L
_____ ________
________
Table 1.9.3. Operation of RD, WRL, and BHE signals
Data bus width
A0
H
H
Status of external data bus
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
RD
H
L
WR
L
BHE
L
H
L
L
16-bit
(BYTE = "L")
H
L
H
L
H
L
H
L
H
L
L
L
H
L
L
L
H
L
Not used
Not used
H / L
H / L
8-bit
(BYTE = "H")
H
Read 1 byte of data
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = "L"
When BYTE pin = "H"
ALE
ALE
A0
Address
Data (Note 1)
Address
Data (Note 1)
D0/A0 to D7/A7
A8 to A19
D0/A1 to D7/A8
Address
Address (Note 2)
A9 to A19
Address
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.3. ALE sigal and address/data bus
31
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
_______
(5) RDY signal
The ready signal facilitates access of external devices that require a long time for access. As shown in
_______
Figure 1.9.4, inputting "L" to the RDY pin at the falling edge of BCLK causes the microcomputer to enter
_______
the ready state. Inputting "H" to the RDY pin at the falling edge of BCLK cancels the ready state. Table
_____
1.9.4 shows the microcomputer status in the ready state. Figure 1.9.4 shows the example of the RD
_______
signal being extended using the RDY pin.
_______
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the
_______
chip select control register (address 000816) are set to "0". The RDY signal is invalid when setting "1" to all
_______
bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly
as in non-using.
Table 1.9.4. Microcomputer status in ready state (Note)
Item
Status
On
Oscillation
Maintain status when RDY signal accepted
R/W signal, address bus, data bus, CS
ALE signal, HLDA, programmable I/O ports
On
Internal peripheral circuits
_______
Note: The RDY signal cannot be accepted immediately prior to a software wait.
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
Accept timing of RDY signal
: Wait using RDY signal
: Wait using software
_____
_______
Figure 1.9.4. Example of RD signal extended by RDY signal
32
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to
__________
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
__________
__________
is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 1.9.5
shows the microcomputer status in the hold state.
__________
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.
__________
HOLD > DMAC > CPU
Figure 1.9.5. Bus-using priorities
Table 1.9.5. Microcomputer status in hold state
Item
Status
On
Oscillation
R/W signal, address bus, data bus, CS, BHE
Floating
Floating
Programmable I/O ports
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Maintain status when hold signal is received
Output "L"
HLDA
On (but watchdog timer stops)
Internal peripheral circuits
Undefined
ALE signal
(7) External bus status when the internal area is accessed
Table 1.9.6 shows the external bus status when the internal area is accessed.
Table 1.9.6. External bus status when the internal area is accessed
Item
SFR accessed
Address output
Internal ROM/RAM accessed
Maintain status before accessed
address of external area
Floating
Address bus
Data bus
When read
When write
Floating
Output data
Undefined
RD, WR, WRL, WRH
BHE
RD, WR, WRL, WRH output
BHE output
Output "H"
Maintain status before accessed
status of external area
Output "H"
CS
Output "H"
Output "L"
ALE
Output "L"
(8) BCLK output
The output of the internal clock ø can be selected using bit 7 of the processor mode register 0 (address
000416) (Note). The output is floating when bit 7 is set to "1".
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to "1".
33
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
(9) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle.
When set to "1", each bus cycle is executed in two or three BCLK cycles. After the microcomputer has
been reset, this bit defaults to "0". When set to "1", bits 4 to 7 of the chip select control register are invalid
and a wait is applied to all external memory areas (two or three BCLK cycles).
When the wait bit of the processor mode register 1 is "0", software waits can be set independently for
each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register
_______
_______
correspond to chip selects CS0 to CS3. When one of these bits is set to "1", the bus cycle is executed in
one BCLK cycle. When set to "0", the bus cycle is executed in two or three BCLK cycles. These bits
default to "0" after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
the corresponding bits of the chip select control register must be set to "0" if using the multiplex bus to
access the external memory area.
Table 1.9.7 shows the software wait and bus cycles. Figure 1.9.6 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to "1".
Table 1.9.7. Software waits and bus cycles
Bits 4 to 7 of chip select
Bus cycle
2 BCLK cycles
Area
SFR
Bus status
Wait bit
control register
Invalid
0
Invalid
Invalid
1 BCLK cycle
Internal
ROM/RAM
1
0
0
Invalid
2 BCLK cycles
1 BCLK cycle
2 BCLK cycles
Separate bus
Separate bus
Separate bus
1
0
External
memory
area
1
0
1
0 (Note)
0 (Note)
0 (Note)
2 BCLK cycles
3 BCLK cycles
3 BCLK cycles
Multiplex bus
Multiplex bus
Note: When using the RDY signal, always set to "0".
34
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
< Separate bus (no wait) >
Bus cycle (Note 1) Bus cycle (Note 1)
BCLK
Write signal
Read signal
Output
Input
Data bus
Address bus (Note 2)
Address
Address
Chip select (Note 2)
< Separate bus (with wait) >
Bus cycle (Note 1)
Bus cycle (Note 1)
BCLK
Write signal
Read signal
Input
Output
Data bus
Address
Address
Address bus (Note 2)
Chip select (Note 2)
< Multiplexed bus >
Bus cycle (Note 1)
Bus cycle (Note 1)
BCLK
Write signal
Read signal
ALE
Address
Address
Address bus (Note 2)
Address bus/
Address
Input
Data output
Address
Data bus
Chip select (Note 2)
Note 1: These example timing charts indicate bus cycle length.
After this bus cycle sometimes come read and write cycles in succession.
Note 2: The address bus and chip select may be extended depending on the CPU status
such as that of the instruction queue buffer.
Figure 1.9.6. Typical bus timings using software wait
35
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Generating Circuit
The clock generating circuit contains three oscillator circuits that supply the operating clock sources to the
CPU and internal peripheral units.
Table 1.10.1. Main clock and sub clock generating circuits
Main clock generating circuit
Sub clock generating circuit
CPU’s operating clock source
CPU’s operating clock source
Timer A/B’s count clock source
Use of clock
Internal peripheral unit’s operating clock source
Quartz crystal oscillator
Usable oscillator
Ceramic or quartz crystal oscillator
Pins to connect oscillator
XIN, XOUT
X
CIN, XCOUT
Available
Available
Stopped
Oscillation stop/restart function
Oscillator status immediately after reset
Oscillating
Externally derived clock can be input
Other
Example of Oscillator Circuit
Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the
circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples
of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally
derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use
the values recommended by the manufacturer of your oscillator.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
IN
XOUT
X
IN
XOUT
Open
(Note)
R
d
Externally derived clock
Vcc
Vss
CIN
COUT
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also if the oscillator manufacturer’s
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 1.10.1. Examples of main clock
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
X
CIN
XCOUT
XCIN
XCOUT
Open
(Note)
R
Cd
Externally derived clock
CCIN
CCOUT
Vcc
Vss
Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive
capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also if the oscillator manufacturer’s
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between XIN
and XOUT following the instruction.
Figure 1.10.2. Examples of sub clock
36
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Internal Ring-Oscillator
A ring oscillator is built in the microcomputer. It can be used instead of XIN as a main clock by setup of the
bit 1 of the oscillation stop detect register. Lower power dissipation can be realized because the oscillating
frequency of the ring oscillator is much lower compared to that of XIN.
Clock Control
Figure 1.10.3 shows the block diagram of the clock generating circuit.
C01CLKR
C01CLKR
b
2
b
1
b
0
b6 b5 b4
0
0
0
a
b
c
d
e
0
0
0
a
b
c
d
e
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
1
0
1
1
0
1
0
1
0
fCAN0
(Note)
fCAN1
fCAN0
fCAN1 (Note)
Selector
PCLK0="0"
f2
f8
PCLK0="1"
XCIN
XCOUT
1/32
fC32
CM04
f32
PCLK0="0"
PCLK0="1"
PCLK0="0"
PCLK0="1"
f2AD
fC
f2SIO2
f8SIO2
f32SIO2
Sub clock
CM20
CM10="1"
Write signal
Oscillation stop
detection circuit
S
R
Q
XIN
CM21
f
c
e
b
d
XOUT
CM07=0
a
g
Main clock
switching
circuit
Divider
RESET
software reset
NMI
fC
CM07="1"
Main clock
Internal clock ø
Ring oscillator
CM02
(BCLK)
Interrupt request
level judgment
output
CM05
S Q
R
WAIT instruction
f
b
d
e
c
1/2
1/2
1/2
1/2
1/2
a
CM06="0"
CM17,CM16="11"
CM06="1"
CM06="0"
CM17,CM16="10"
g
CM06="0"
CM17,CM16="01"
CM0i : Bit i at address 000616
CM1i : Bit i at address 000716
CM2i : Bit i at address 000C16
PCLKi : Bit i at address 025E16
CCLKi : Bit i at address 025F16
CM06="0"
CM17,CM16="00"
Details of divider
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.10.3. Clock generating circuit
37
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
The following paragraphs describe the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the
clock, after switching the operating clock source of CPU to the sub clock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the XOUT pin
can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive
capacity of the XOUT pin reduces the power dissipation. This bit defaults to "1" when shifting to stop mode
and after a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value
before stop mode is retained.
You can switch over from the main clock to the ring oscillator by changing the value of the main clock
switch bit (bit 1 at address 000C16).
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the XCOUT pin
can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the
drive capacity of the XCOUT pin reduces the power dissipation. This bit changes to "1" when shifting to
stop mode and at a reset.
When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
(3) BCLK
The BCLK is the clock that drives the CPU and the watchdog timer, i.e. the internal clock ø, and is either
the main clock or fc or is derived by dividing the main clock by 2, 4, 8, or 16. After a reset the BCLK is
derived by dividing the main clock by 8 .
When shifting to stop mode, the main clock division select bit (bit 6 at address 000616) is set to "1".
When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is
retainded.
(4) Peripheral function clocks
• f2, f8, f32, f2SIO2, f8SIO2, f32SIO2
The clock for the peripheral devices is derived by dividing the main clock by 2 (or no division), 8, or 32.
The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral
function clock stop bit (bit 2 at address 000616) to "1" and then executing a WAIT instruction.
As to f2 and f2SIO2, you can select division by 2 or no division by changing the value of the peripheral
function clock select register.
• f2AD
This clock is derived by dividing the main clock by 2 (or no division) and is used for A-D conversion. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at address 000616) to "1" and then executing a WAIT instruction. You can select
division by 2 or no division by changing the value of the peripheral function clock select register.
38
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
• fCAN0, fCAN1 (Note)
These clocks are derived by dividing the main clock by 1, 2, 4, 8 or 16 and they are used for the corre-
sponding CAN module. The peripheral function clock is stopped by stopping the main clock or by setting
the WAIT peripheral function clock stop bit (bit 2 at address 000616) to "1" and then executing a WAIT
instruction. When CAN modules are shifted to sleep mode, these clocks stop at "H".
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It may be selected as the BCLK and for the watchdog
timer.
(7) fRING
This clock is supplied by the ring oscillator circuit. Immediately after a reset, this clock is not supplied. The
ring oscillator oscillation can be set to BCLK when oscillation stop is detected or with the main clock
switch bit (bit 1 at address 000C16).
After the oscillation of the ring oscillator circuit has stabilized, the XIN clock driver can be stopped by
setting the main clock stop bit (bit 5 at address 000616) to "1". This can reduce the power dissipation even
more.
Note: Channel CAN1 is not available for M16C/6N1 group.
39
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.10.4 shows the system clock control registers 0 and 1.
System clock control register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
000616
When reset
4816
Bit symbol
CM00
Bit name
Function
R W
b1 b0
Clock output function
select bit
(Valid only in single-chip
mode)
0 0 : I/O port P5
0 1 : f
1 0 : f
1 1 : f32 output
7
C
output
output
8
CM01
CM02
CM03
WAIT peripheral function
clock stop bit
0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)
X
CIN-XCOUT drive capacity 0 : LOW
select bit (Note 2)
1 : HIGH
Port X
C
select bit
0 : I/O port
1 : XCIN-XCOUT generation (Note 9)
CM04
CM05
Main clock (XIN-XOUT
stop bit (Note 3, 4, 5, 10)
)
0 : On
1 : Off
Main clock division select 0 : CM16 and CM17 valid
CM06
CM07
bit 0 (Note 7)
1 : Division by 8 mode
System clock select bit
(Note 6)
0 : XIN, XOUT
1 : XCIN, XCOUT
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: Changes to "1" when shiffing to stop mode and at a reset.
Note 3: When entering the low power dissipation mode and the ring oscillator mode, main clock stops by using this bit.
To stop the main clock, when the sub clock oscillation is stable, set system clock select bit (CM07) to "1" be-
fore setting this bit to "1".
Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to "1", XOUT turns "H". The built-in feedback resistor remains being connected, so XIN turns
pulled up to XOUT ("H") via the feedback resistor.
Note 6: Set port XC select bit (CM04) to "1" and stabilize the sub clock oscillating before setting this bit from "0" to "1".
Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the
main clock oscillating before setting this bit from "1" to "0".
Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 8: fC32 is not included. Do not set to "1" when using low-speed or low power dissipation mode.
Note 9: When the XCIN/XCOUT is used, set ports P86 and P87 as the input ports without pull-up.
Note10: Setting this bit to "1" disables the main clock buffer. If the oscillation is generated by a quartz crystal or ceramic os-
cillator, oscillation stops. To avoid stopping the MCU, set CM07 to "1" or CM21 to "1" prior to setting this bit to "1".
System clock control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM1
Address
000716
When reset
2016
0
0
0
0
Bit symbol
CM10
Bit name
Function
R W
All clock stop control bit
(Note4)
0 : Clock on
1 : All clocks off (stop mode)
Reserved bits
Must always be set to "0"
X
IN-XOUT drive capacity
0 : LOW
1 : HIGH
CM15
select bit (Note 2)
b7 b6
Main clock division
select bit 1 (Note 3)
0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
CM16
CM17
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing to this register.
Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is "0". If "1", division mode is
fixed at 8.
Note 4: If this bit is set to "1", XOUT turns "H", and the built-in feedback resistor is cut off. XCIN and XCOUT turn high-
impedance state.
Figure 1.10.4. Clock control registers 0 and 1
40
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Figure 1.10.5 shows the peripheral function clock select register and Figure 1.10.6 shows the CAN0/1 clock
select register.
Peripheral function clock select register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCLKR
Address
025E16
When reset
XXXXXX00
2
Bit symbol
Bit name
Function
R W
(f2 and f2AD are)
0: Division by 2 mode
1: Division by 1 mode
TimerA, TimerB, A-D
converter function clock
PCLK0
UART0-2, S I/O3 function (f2SIO2 is)
clock 0: Division by 2 mode
1: Division by 1 mode
PCLK1
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are "0".
Note: Set bit 0 of the protect register (address 000A16) to "1" before writing in this
register.
Figure 1.10.5. Peripheral function clock select register
CAN0/1 clock select register (Note 1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CCLKR
Address
025F16
When reset
0016
0
0
Bit symbol
CCLK0
Bit name
Function
R W
b2 b1 b0
CAN0 Clock select bit
0 0 0: No division mode
0 0 1: Division by 2 mode
0 1 0: Division by 4 mode
0 1 1: Division by 8 mode
1 0 0: Division by 16 mode
1 0 1: Inhibited
CCLK1
CCLK2
1 1 0: Inhibited
1 1 1: Inhibited
Always set to "0"
Reserved bit
b6 b5 b4
CCLK4
CCLK5
CAN1 Clock select bit
(Note3)
0 0 0: No division mode
0 0 1: Division by 2 mode
0 1 0: Division by 4 mode
0 1 1: Division by 8 mode
1 0 0: Division by 16 mode
1 0 1: Inhibited
CCLK6
1 1 0: Inhibited
1 1 1: Inhibited
Reserved bit
Always set to "0"
Note 1: Set bit 0 of the protect register (address 000A16) to "1" before writing in this register.
Note 2: Change the register value only when the CAN module is in Reset/Initialization mode
(the bit 0 of the CAN Control Register (address 021016 and 023016) is "1").
Note 3: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.10.6. CAN0/1 clock select register
41
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
Clock Output
In single-chip mode, the clock output function select bits (bits 0 and 1 at address 000616) enable f8, f32, or
fc to be output from the P57/CLKOUT pin. When the WAIT peripheral function clock stop bit (bit 2 at address
000616) is set to "1", the output of f8 and f32 stops when a WAIT instruction is executed.
Stop Mode
Writing "1" to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcom-
puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC re-
mains above 2V.
Because the oscillation of BCLK, f2 to f32, f1SIO2 to f32SIO2, f2AD, fCAN0, fCAN1, fC32, and fC stop in stop mode,
peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A and
timer B operate provided that the event counter mode is set to an external pulse, and UARTi (i = 0 to 2), S
I/O3 functions provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode.
Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,
that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel
must have been changed to "0". If returning by an interrupt, that interrupt routine is executed. If only a
_______
hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to
"0", then shift to stop mode.
When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division
select bit 0 (bit 6 at address 000616) is set to "1". When shifting from low-speed/low power dissipation mode
to stop mode, the value before stop mode is retained.
Table 1.10.2. Port status during stop mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before stop mode
____
____
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
__________
"H"
____
____
HLDA, BCLK
"H"
"H"
ALE
Port
Retains status before stop mode Retains status before stop mode
Valid only in single-chip mode "H"
CLKOUT
When fc selected
When f8, f32 selected
Valid only in single-chip mode Retains status before stop mode
42
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Wait Mode
Wait Mode
When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this
mode, oscillation continues but the BCLK and the watchdog timer stop. Writing "1" to the WAIT peripheral
function clock stop bit and executing a WAIT instruction also stops the clock being supplied to the internal
peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock fC32
does not stop so that the peripherals using fC32 do not contribute to the power saving. When the MCU
running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to "1". Table
1.10.3 shows the status of the ports in wait mode.
Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that
interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must
have been changed to "0". If returning by an interrupt, the clock in which the WAIT instruction executed is
set to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware
_______
reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to "0", then
shift to wait mode.
Table 1.10.3. Port status during wait mode
Pin
Memory expansion mode
Microprocessor mode
Single-chip mode
_______
_______
Address bus, data bus, CS0 to CS3,
Retains status before wait mode
____
____
________
BHE
_____ ______ ________ _________
RD, WR, WRL, WRH
__________
"H"
____
____
HLDA,BCLK
"H"
ALE
Port
"H"
Retains status before wait mode
Retains status before wait mode
CLKOUT
When fC selected
Valid only in single-chip mode Does not stop
When f8, f32 selected Valid only in single-chip mode Does not stop when the WAIT
peripheral function clock stop
bit is "0".
When the WAIT peripheral
function clock stop bit is "1",
the status immediately prior
to entering wait mode is main-
tained.
43
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition of BCLK
Status Transition of BCLK
Power dissipation can be reduced and low-voltage operation achieved by changing the count source for
BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control
registers 0 and 1.
When reset, the device starts in division by 8 mode. The main clock division select bit 0 (bit 6 at address
000616) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When
shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.
The following shows the operational modes of BCLK.
(1) Division by 2 mode
The main clock is divided by 2 to obtain the BCLK.
(2) Division by 4 mode
The main clock is divided by 4 to obtain the BCLK.
(3) Division by 8 mode
The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this
mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4
mode, the main clock must be oscillating stably. When going to low-speed or low power dissipation mode,
make sure the sub clock is oscillating stable.
(4) Division by 16 mode
The main clock is divided by 16 to obtain the BCLK.
(5) No-division mode
The main clock is divided by 1 to obtain the BCLK.
(6) Low-speed mode
fC is used as BCLK. Note that oscillation of both the main and sub clocks must have stabilized before
transferring from this mode to another or vice versa. 2 to 3 seconds or more are required before the sub
clock is fully stabilized. Therefore, the program must be written to wait until this clock has stabilized
immediately after powering up and after stop mode is cancelled.
(7) Low power dissipation mode
fC is the BCLK and the main clock is stopped.
(8) Ring oscillator mode
BCLK is generated by the ring oscillator. You can use it by dividing it by 2, 4, 8 or 16, and also no division
is possible.
Note: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stable. Allow a wait time in software for
the oscillation to stabilize before switching over the clock.
44
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Status Transition of BCLK
Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1
CM21
CM17
CM16
CM07
CM06
CM05
CM04
Invalid
Invalid
Invalid
Invalid
Invalid
1
Operating mode of BCLK
No division mode
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
Division by 2 mode
Division by 4 mode
Division by 8 mode
0
0
1
0
Invalid
Invalid
Division by 16 mode
Low-speed mode
0
0
0
1
1
0
1
1
0
0
0
0
0
Invalid
Invalid
Invalid
Invalid
Invalid
Invalid
0
Low power dissipation mode
Ring oscillator mode/1
Ring oscillator mode/2
Ring oscillator mode/4
1
1
1
1
1
1
1
0
0
0
0
0
1 (Note)
1 (Note)
1 (Note)
Invalid
Invalid
Invalid
Invalid
Invalid
0
1
1
0
Invalid
Invalid
Ring oscillator mode/8
Ring oscillator mode/16
0
0
1
0
1 (Note)
1 (Note)
1
1
Note: Set CM21 to "1" before setting this bit to "1".
45
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Power Control
The following is a description of the four available power control modes:
Modes
Power control is available in four modes.
(1) Normal operation mode
• High-speed mode
Divide-by 1 frequency of the main clock becomes the BCLK. The CPU operates with the internal
clock selected. Each peripheral function operates according to its assigned clock.
• Medium-speed mode
Divide-by-2, divide by-4 divide-by-8 or divide-by-16 frequency of the main clock becomes the
BCLK. The CPU operates according to the internal clock selected. Each peripheral function oper-
ates according to its assigned clock.
• Low-speed mode
fc becomes the BCLK. The CPU operates according to the fc clock selected. The fc clock is sup-
plied by the sub clock. Each peripheral function operates according to its assigned clock.
• Low power dissipation mode
The main clock operating in low-speed mode is stopped. The CPU operates according to the fc
clock. The fc clock is supplied by the sub clock. The only peripheral functions that operate are
those with the sub clock selected as the count source.
(2) Wait mode
The CPU operation is stopped. The oscillators do not stop.
(3) Stop mode
All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three
modes listed here, is the most effective in reducing power dissipation.
(4) Ring oscillator mode
The ring oscillator replaces XIN. No-division-, divide-by-2-, 4-, 8- or 16 mode can be selected by
changing the values in CM06, CM16 and CM17. The higher the division ratio is, the lower power
dissipation. The clock driver of XIN can be stopped by changing the value of the main clock stop bit
to "0" when the CPU operates using the ring oscillator. Through this the power dissipation will be
still lower.
Figure 1.10.7 shows the state transition of power control modes.
46
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Transition of stop mode, wait mode
Reset
Medium speed mode
(division by 8 mode)
Interrupt
(Note 1)
CM05 = "0"
CM04 = "1"
Main clock is oscillating
CM21 = "0"
Ring oscillator is stopped
Sub clock is oscillating
Interrupt
(Note 2)
Wait instruction
High speed/medium speed mode
Low speed/low power dissipation mode
Ring oscillator mode
Stop mode
Wait mode
CM10 = "1"
Main clock is stopped
CM20 = "0"
Interrupt
All oscillators are stopped
CPU operation is stopped
Oscillation stop detetion
function is disabled
CM21 = "0" (Note 3)
Ring oscillator is stopped
Normal operation mode
Note 1: When the mode returns to normal operation mode again after shifting from high speed/medium speed mode to stop
mode, the mode shifts to division by 8 mode of medium speed mode.
Note 2: When the mode returns to normal operation mode again after shifting from low speed/low power dissipation mode to
stop mode, the mode shifts to low speed/low power dissipation mode.
Note 3: The mode does not shift directly from ring oscillator mode to stop mode.
Transition of normal operation mode
Medium speed mode
CM05 = "0" Main clock is oscillating
CM04 = "0" Sub clock is stopped
CM21 = "0" Ring oscillator is stopped
CM05 = "0" Main clock is oscillating
CM04 = "1" Sub clock is oscillating
CM20 = "0" Oscillation stop detetion function is disabled
CM21 = "0" Ring oscillator is stopped
High speed/medium speed mode
Low speed mode
CM07 = "1"
CM07 = "0"
BCLK : f(XIN)/n n = 1, 2, 4, 8, 16
BCLK : f(XCIN
)
CM07 = "0" System clock is main clock
CM07 = "1" System clock is sub clock
CM20 = "0" Oscillation stop detection function is disabled
CM05 = "0"
Main clock is oscillating
CM04 = "1"
CM05 = "0"
Main clock is oscillating
CM04 = "1"
CM05 = "0"
Main clock is oscillating
CM04 = "1"
Sub clock is oscillating
CM20 = "0"
Oscillation stop detetion
function is disabled
CM21 = "0"
Sub clock is oscillating
CM20 = "0"
Oscillation stop detetion
function is disabled
CM21 = "0"
Sub clock is oscillating
CM21 = "0"
Ring oscillator is stopped
Ring oscillator is stopped
Ring oscillator is stopped (Note 3)
CM05 = "0"
CM05 = "1" (Note 2)
CM04 = "0"
Main clock is oscillating
CM04 = "0"
Sub clock is stopped
CM20 = "0"
Oscillation stop detetion
function is disabled
CM21 = "1"
Sub clock is stopped
CM20 = "1"
Oscillation stop detetion
function is enabled
CM21 = "0"
CM05 = "1"
Main clock is stopped
CM04 = "1"
Sub clock is oscillating
CM21 = "0"
Ring oscillator is oscillating
Ring oscillator is stopped
Ring oscillator is stopped
High speed/medium speed mode
Ring oscillator mode
Low power dissipation mode
BCLK : f(XCIN
CM07 = "1" System clock is sub clock
BCLK : f(XIN)/n n = 1, 2, 4, 8, 16
BCLK : fRING/n n = 1, 2, 4, 8, 16 (Note)
CM07 = "0" System clock is main clock
)
CM07 = "0" System clock is main clock
CM20 = "1" Oscillation stop detection function is enabled
Note 1: Division value of CM06, CM16, CM17.
Mode Division value CM06 CM16 CM17
CM05 = "1" Main clock is stopped
High speed mode Division by 1
Division by 2
0
0
0
1
0
0
1
0
0
0
1
When main clock is stopped, or oscillation stop is detected.
When occuring this shift, an internal reset or the oscil-
lation stop detection interrupt occurs.
Division by 4
Medium speed mode
Division by 8
Invalid Invalid
Division by 16
1
1
Note 2: Be sure to set CM05 = "1", after setting CM21 = "1".
Note 3: Be sure to set CM21 = "0", after setting CM05 = "0"
and the oscillation of the main clock has stabilized.
Figure 1.10.7. State transition diagram of power control mode
47
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Oscillation Stop Detection Function
The oscillation stop detection function detects abnormal stopping of the clock by causes such as opening
and shorting of the XIN oscillation circuit. When oscillation stop is detected, either an internal reset or an
oscillation stop detection interrupt is generated. The selection depends on the value in the bit 7 of the
oscillation stop detection register (address 000C16). When an oscillation stop detection interrupt is gener-
ated, the ring oscillator in the microcomputer operates automatically and is used as the system clock in
place of the XIN clock. This allows interrupt processing.
The oscillation stop detection function can be enabled/disabled with bit 0 of the oscillation stop detection
register. When this bit is set to "1", the function is enabled. After the reset is released, the oscillation stop
detection function becomes invalid because the bit value is "0".
Note that an oscillator input signal that violates the timing or voltage specification for XIN may cause the
CPU to hang. Therefore the oscillation stop detection interrupt may not be processed. Countermeasures
on system level should be taken for the CPU to recover from such kind of status.
Table 1.10.5 gives an specification overview of the oscillation stop detection function.
Table 1.10.5. Specification outlint of the oscillation stop detection function
Specification
Item
XIN : 2MHz or higher
Oscillation stop detectable clock and
frequency range
When the oscillation stop detection bit (bit 0 of address 000C16)
is set to "1"
Enabling condition for oscillation stop
detection function
When internal reset is generated (bit 7 at address 000C16 is
cleared to "0".)
Operation at oscillation stop detection
When oscillation stop detection interrupt is generated (bit 7 at
address 000C16 is set to "1".)
Before setting up the stop mode, write "0" in the oscillation stop
detection valid bit to invalidate the oscillation stop detection func-
tion. Write "1" into the bit again after the stop mode is released.
Notes on STOP mode
Compulsory discharge when CM20="0"
Internal reset
Internal reset
To the CPU
generating cicuit
Charge/discharge
cicuit
Oscillation stop
detection interrupt
generating circuit
Pulse generation
XIN
circuit for clock edge
detection and charge/
discharge control
Watchdog timer
interrupt
CM21
Note
Main clock switch control
Ring oscillator
To the main clock
prescaler
Main clock
Note: When XIN is supplied, this repeats charge and discharge with pulses by XIN edge detection.
When XIN is not supplied, this continues charging. When the charge exceeds a certain
level, it regards the oscillation as stopped.
Figure 1.10.8. Structure of the oscillation stop detection circuit
48
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Oscillation stop detection register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM2
Address
000C16
When reset
0016
0 0 0
Bit symbol
CM20
Bit name
Oscillation stop
detection bit (Note 2)
Function
R W
0: The function is disabled
1: The function is enabled
Main clock source
select bit (Note 3)
CM21
0: Select XIN
1: Select ring oscillator
Oscillation stop detection
interrupt request bit (Note 4)
0: Invalid
CM22
CM23
1: Oscillation stop has been detected
Clock monitor bit (Note 5)
0: XIN is in operation
1: Invalid
Reserved bits
CM27
Action selection on
stop detection (Note 5)
Must be set to "0"
0: Issue internal reset
1: Switch to ring oscillators and
request an interrupt
Note 1: Set bit 0 of the protect register to "1" before writing to this register.
Note 2: Not valid during wait mode with disabled peripheral clocks (CM02 = "1"), main clock
stop (CM10 = "1"), or if the ring oscillator is selected manually (CM21 = "1").
Note 3: If CM07 = "1", the selection of XCIN takes precedence over fRING
Note 4: CM22 may be reset but not set
Note 5: Valid when CM20 = "1".
.
Figure 1.10.9. Structure of the oscillation stop detection register
Oscillation Stop Detection Bit (CM20)
The oscillation stop detection is activated by setting CM20 to "1".
Set this bit to "0" before entering the stop mode. When returning from stop mode, the external oscillator
may be unstable for a period of time. The detection may be enabled again after returning from stop mode.
Set this bit to "0" also before setting main clock stop bit (bit 5 at address 000616).
Do not enable the detection function if XIN is lower than 2MHz.
Main Clock Source Selection Bit (CM21)
The internal ring oscillator may be selected as the main clock source independently of the oscillation stop
detection by setting this bit to "1". The division ratio of the ring oscillator, like that of XIN, is governed by
CM06, CM16, and CM17. Note that the selection of the sub clock (XCIN) takes precedence over the ring
oscillator selection.
Switching to fRING manually disables the oscillation stop detection regardless of CM20.
Oscillation Stop Detection Interrupt Request Bit (CM22)
This bit signals an oscillation stop detection interrupt. The oscillation stop/restart detection and the watch-
dog timer share an interrupt request line. The interrupt service routine can determine which unit re-
quested the interrupt by sampling this bit. Whe an oscillation stop is detected, this bit goes high. It has to
be reset manually during interrupt servicing.
See also Figure 1.10.10.
49
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Clock Monitor Bit (CM23)
The operational status of XIN can be monitored with this bit. When XIN is operating, this bit is "0". After a
clock stop detection, this bit can be polled to check if XIN has restarted. This bit is valid when CM20 is "1".
Reserved Bits (CM24-CM26)
These bits are reserved. They must always remain at "0".
Action Selection (when an oscillation stop is detected) Bit (CM27)
(i) Operation when internal reset is selected (CM27="0")
In case an abnormal stop of XIN is detected when the oscillation stop detection valid bit (CM20) is "1", an
internal reset is generated. The microcomputer stops in reset state, and it does not operate further.
Note: Release from this state is possible by external reset only. However, if XIN clock includes some
errors, further operation cannot be guaranteed.
Table 1.10.6 shows the status of each port after an internal reset is generated.
(ii) Operation when oscillation stop detection interrupt is selected (CM27="1")
In case an abnormal stop of XIN is detected when the oscillation stop detection valid bit (CM20) is "1", an
oscillation stop detection interrupt is generated. In this case, the ring oscillator operates instead of the XIN
stopped abnormally. Further operation can be done to the ring oscillation. Oscillation stop detection inter-
rupt shares the vector table with watchdog timer interrupt. Accordingly, the interrupt factor should be
judged. For this purpose, use the CM22, oscillation stop detection status.
Figure 1.10.10 shows how to judge the factor by the oscillation stop detection interrupt process program.
Stop Mode (CM10="1")
It is recommended the stop detection be disabled before entering stop mode. When returning from stop
mode, the external quartz crystal oscillator is instable for a period of time and may falsely cause a clock
stop to be signalled. It may be enabled again after returning from the stop mode.
Wait Mode (WAIT instruction issued)
When peripheral clocks during wait are enabled (CM02="0"), the oscillation stop/restart detection circuit
can continue to monitor XIN. Should XIN fail, the wait mode is cancelled and an interrupt is generated
(CM27="1"). The microcomputer issues an internal reset if CM27 is "0".
When the wait mode is entered with the peripheral clocks disabled (CM02="1"), the clock stop detection
is disabled. Clock stops will not be detected. The oscillation stop detection circuit will, however, detect
______
and react to a stopped clock if the wait mode is cancelled (for instance by an NMI).
Generally, it is recommended to disable the detection circuit before entering wait mode if the peripheral
clocks are to be disabled during wait.
50
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Power Control
Table1.10.6. Port status after an internal reset is generated
Pin status
Operating mode of BCLK
Pin name
Single chip mode
BYTE = VSS
Data input (floating)
BYTE = VCC
Data input (floating)
P0
P1
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Data input (floating)
Data input (floating)
Address output (indeterminate)
CS0 output ("H" level output)
Input port (floating) (Pull-up resistance is ON.)
WR output ("H" level output)
BHE output (indeterminate)
RD output ("H" level output)
BCLK output
Address output (indeterminate)
CS0 output ("H" level output)
Input port (floating) (Pull-up resistance is ON.)
WR output ("H" level output)
BHE output (indeterminate)
RD output ("H" level output)
BCLK output
P2, P3, P40 to P43
P44
P45
P50
P51
to P4
7
P52
P53
P54
P55
HLDA output (output value depends on HOLD pin input)
HOLD input (floating)
HLDA output (output value depends on HOLD pin input)
HOLD input (floating)
P5
6
7
ALE output ("L" level output)
RDY input (floating)
ALE output ("L" level output)
RDY input (floating)
P5
P6, P7, P8
0 to P84,
Input port (floating)
Input port (floating)
Input port (floating)
P8 , P8 , P9, P10
6
7
Oscillation stop detection interrupt
or watchdog timer interrupt
is generated
Read CM22
NO
CM22 = 1 ?
YES
Jump to the execution program
for oscillation stop detection interrupt
Jump to the execution program
for watchdog timer interrupt
Figure 1.10.10. Flow of the judgment
51
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Protection
Protection
The protection function is provided so that the values in important registers cannot be changed in the event
that the program runs out of control. Figure 1.10.11 shows the protect register. The values in the processor
mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control reg-
ister 0 (address 000616), system clock control register 1 (address 000716), peripheral function clock select
register (address 025E16), CAN0/1 clock select register (address 025F16), S I/O3 control register (address
01E216), oscillation stop detection register (address 000C16) port P7 direction register (address 03EF16)
and port P9 direction register (address 03F316) can only be changed when the respective bit in the protect
register is set to "1". Therefore, important outputs can be allocated to port P7 or port P9.
If, after "1" (write-enabled) has been written to the port P7 or port P9 direction registers write-enable bit (bit
2 at address 000A16), a value is written to any address, the bit automatically reverts to "0" (write-inhibited).
However, the system clock control registers 0 and 1 write-enable bit (bit 0 at address 000A16) and proces-
sor mode register 0 and 1 write-enable bit (bit 1 at address 000A16) do not automatically return to "0" after
a value has been written to an address. The program must therefore be written to return these bits to "0".
Protect register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000A16
When reset
XXXXX000
2
Bit symbol
PRC0
Bit name
Function
R W
Enables writing to the system clock
control registers 0 and 1 (addresses
000616 and 000716), oscillation stop
detection register (address 000C16),
peripheral function clock select regis-
ter (address 025E16), and CAN0/1
Clock register protection bit
clock select register (address 025F16
)
(Note 1)
0 : Write-inhibited
1 : Write-enabled
Enables writing to processor mode
registers 0 and 1 (addresses 000416
PRC1
PRC2
Processor mode register
protection bit
and 000516
)
0 : Write-inhibited
1 : Write-enabled
P7/P9 direction register and
S I/O3 control register
protection bit
Enables writing to port P7/9 direction
register (addresses 03F316 and
03EF16) and S I/O3 control register
(address 01E216) (Note 2)
0 : Write-inhibited
1 : Write-enabled
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note 1: There is only one CAN channel available for M16C/6N1 group.
Note 2: Writing a value to an address after "1" is written to this bit returns the bit
to "0" . Other bits do not automatically return to "0" and they must therefore
be reset by the program.
Figure 1.10.11. Protect register
52
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Overview of Interrupt
Type of Interrupts
Figure 1.11.1 lists the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
Software
INT instruction
Reset
_______
Interrupt
NMI
________
DBC
Special
Oscillation Stop detection
Watchdog timer
Single step
Hardware
Peripheral I/O (Note)
Address matched
Note: Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.
Figure 1.11.1. Classification of interrupts
• Maskable interrupt :
An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag)
or whose interrupt priority can be changed by priority level.
• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
53
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set
to "1". The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the
INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral interrupt I/O inter-
rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O
interrupt does.
The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is
involved.
So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack
pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and select
the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the inter-
rupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as
software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
54
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Hardware Interrupts
Hardware interrupts are classified into two types - special interrupts and peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are non-maskable interrupts.
• Reset
____________
Reset occurs if an "L" is input to the RESET pin.
_______
• NMI interrupt
_______
_______
An NMI interrupt occurs if an "L" is input to the NMI pin.
________
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Oscillation stop detection interrupt
Generated by the oscillation stop detection function.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D
flag) set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by the
address match interrupt register is executed with the address match interrupt enable bit set to "1". If an
address other than the first address of the instruction in the address match interrupt register is no address
match interrupt occurs. For address match interrupt, see "Address match interrupt".
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral functions
are dependent on classes of products, so the interrupt factors too are dependent on classes of products.
The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT
instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 interrupt, DMA1 interrupt
These are interrupts that DMA generates.
• Key-input interrupt
____
A key-input interrupt occurs if an "L" is input to the KI pin.
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1, UART2/NACK, and S I/O3 transmission interrupt
These are interrupts that the serial I/O transmission generates.
55
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
• UART0, UART1, UART2/ACK, and S I/O3 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates.
• Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
________
________
• INT0 interrupt through timer INT5 interrupt
______
______
An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to the INT pin.
• CAN0/1 wake up interrupts (Note)
These interrupts are generated when a falling edge is input to CRX0 ro CRX1 pin.
• CAN0, 1 transmission interrupts (Note)
These are interrupts that a CAN transmission generates.
• CAN0, 1 reception interrupts (Note)
These are interrupts that a CAN reception generates.
• CAN0/1 error interrupts (Note)
These are interrupts that a CAN error generates.
Note: Channel CAN1 is not available for M16C/6N1 group.
Interrupts relating to channel CAN1 are invalid for M16C/6N1 group.
56
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupts and Interrupt Vector Tables
If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for
specifying the address.
__
Two types of interrupt vector tables are available fixed vector table in which addresses are fixed and
variable vector table in which addresses can be varied by the setting.
MSB
LSB
Low address
Mid address
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
0 0 0 0
0 0 0 0
High address
0 0 0 0
Figure 1.11.2. Format for specifying interrupt vector addresses
• Fixed vector tables
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of
interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector tables
and addresses of vector tables.
Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables
Vector table addresse
Interrupt source
Remarks
Interrupt on UND instruction
Address (L) to address (H)
FFFDC16 to FFFDF16
FFFE016 to FFFE316
FFFE416 to FFFE716
Undefined instruction
Overflow
Interrupt on INTO instruction
BRK instruction
If the vector contains FF16, program execution starts from
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Address match
FFFE816 to FFFEB16
FFFEC16 to FFFEF16
FFFF016 to FFFF316
Single step (Note)
Oscillation stop detection/
Watchdog timer
________
DBC (Note)
FFFF416 to FFFF716
Do not use
_______
_______
NMI
FFFF816 to FFFFB16
FFFFC16 to FFFFF16
External interrupt by input to NMI pin
Reset
Note: Interrupts used for debugging purposes only.
57
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
• Variable vector tables
The addresses in the variable vector table can be modified, according to the user's setting. Indicate the
first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the
INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes.
Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the interrupts as-
signed to the variable vector tables and addresses of vector tables.
Table 1.11.2. Interrupt assigned to the variable vector tables and addresses of vector tables
Vector table address
Address (L) to address (H)
Software interrupt number
Interrupt source
Remarks
Software interrupt number 0
+0 to +3 (Note 1)
BRK instr.
(Note 4)
Software interrupt number 1
Software interrupt number 2
Software interrupt number 3
Software interrupt number 4
Software interrupt number 5
+4 to +7 (Note 1)
CAN0/1 Wake Up
CAN0 reception
+8 to +11 (Note 1)
+12 to +15 (Note 1)
+16 to +19 (Note 1)
+20 to +23 (Note 1)
CAN0 transmission
INT3
Timer B5
Software interrupt number 6
Software interrupt number 7
Software interrupt number 8
Software interrupt number 9
Software interrupt number 10
Software interrupt number 11
+24 to +27 (Note 1)
+28 to +31 (Note 1)
+32 to +35 (Note 1,2)
+36 to +39 (Note 1,2)
+40 to +43 (Note 1)
+44 to +47 (Note 1)
Timer B4
Timer B3
(Note 4)
(Note 4)
CAN1 reception, INT5
CAN1 transmission, INT4, S I/O3
Bus collision detection
DMA0
Software interrupt number 12
Software interrupt number 13
Software interrupt number 14
Software interrupt number 15
Software interrupt number 16
Software interrupt number 17
Software interrupt number 18
Software interrupt number 19
Software interrupt number 20
Software interrupt number 21
Software interrupt number 22
+48 to +51 (Note 1)
+52 to +55 (Note 1)
+56 to +59 (Note 1,2)
+60 to +63 (Note 1,3)
+64 to +67 (Note 1,3)
+68 to +71 (Note 1)
+72 to +75 (Note 1)
+76 to +79 (Note 1)
+80 to +83 (Note 1)
+84 to +87 (Note 1)
+88 to +91 (Note 1)
DMA1
(Note 4)
CAN0/1 Error int.
A-D conversion, Key input
UART2 transmission/NACK
UART2 reception/ACK
UART0 transmission
UART0 reception
UART1 transmission
UART1 reception
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
Timer B0
Timer B1
Timer B2
INT0
Software interrupt number 23
Software interrupt number 24
Software interrupt number 25
Software interrupt number 26
Software interrupt number 27
Software interrupt number 28
Software interrupt number 29
Software interrupt number 30
Software interrupt number 31
+92 to +95 (Note 1)
+96 to +99 (Note 1)
+100 to +103 (Note 1)
+104 to +107 (Note 1)
+108 to +111 (Note 1)
+112 to +115 (Note 1)
+116 to +119 (Note 1)
+120 to +123 (Note 1)
+124 to +127 (Note 1)
INT1
INT2
Software interrupt number 32
to
Software interrupt number 63
+128 to +131 (Note 1)
to
+252 to +255 (Note 1)
Software interrupt
Cannot be masked I flag
Note 1: Address relative to address in interrupt table register (INTB).
Note 2: It is selected by interrupt request cause select bits (bit 0 and bit 1 at address 01DE16 and bit 6 and bit 7
at address 01DF16).
Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.
Note 4: Channel CAN1 is not available for M16C/6N1 group.
58
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Control
Descriptions are given here regarding how to enable or disable interrupts and how to set the priority to be
accepted. What is described here does not apply to non-maskable interrupts.
Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority selection bit,
or processor interrupt priority level(IPL). Whether an interrupt request is present or absent is indicated by
the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in
the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located
in the flag register (FLG).
Figure 1.11.3 shows the memory map of the interrupt control registers.
59
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt control register (Note 2)
Symbol
Address
0041
004216, 004316
004516 to 004716
004A16
When reset
XXXXX000
XXXXX000
C01WKIC, (Note 3)
C0RECIC, C0TRMIC
TBiIC(i=3 to 5)
BCNIC
DMiIC(i=0, 1)
C01ERRIC (Note 3)
ADIC/KUPIC
SiTIC(i=0 to 2)
SiRIC(i=0 to 2)
TAiIC(i=0 to 4)
TBiIC(i=0 to 2)
16
2
2
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
XXXXX000
2
2
2
2
2
2
2
2
2
004B16, 004C16
16
004D
004E16
005116, 005316, 004F16
005216, 005416, 005016
005516 to 005916
b7 b6 b5 b4 b3 b2 b1 b0
005A16 to 005C16
Bit symbol
ILVL0
Bit name
Function
R
W
b2 b1 b0
Interrupt priority level
select bit
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
ILVL2
IR
0 : Interrupt not requested
1 : Interrupt requested
Interrupt request bit
(Note1)
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: This bit can only be accessed for reset (= "0"), but cannot be accessed for set (= "1").
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt
request for that register. For details, see the precautions for interrupts.
Note 3: Channel CAN1 is not available for M16C/6N1 group.
Symbol
INT3IC
C1RECIC/INT5IC
C1TRMIC/S3IC/INT4IC (Notes 3, 4)
INTiIC(i=0 to 2)
Address
004416
004816
When reset
b7 b6 b5 b4 b3 b2 b1 b0
XX00X000
XX00X000
XX00X000
XX00X000
2
2
2
2
(Notes 3, 4)
0
004916
005D16 to 005F16
R
W
Bit symbol
Bit name
Function
b2 b1 b0
Interrupt priority level
select bit
ILVL0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
ILVL1
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
ILVL2
1 1 1 : Level 7
IR
Interrupt request bit
Polarity select bit
0: Interrupt not requested
1: Interrupt requested
(Note1)
POL
0 : Selects falling edge
1 : Selects rising edge
Reserved bit
Always set to "0"
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note 1: This bit can only be accessed for reset (= "0"), but cannot be accessed for set (= "1").
Note 2: To rewrite the interrupt control register, do so at a point that dose not generate the interrupt
request for that register. For details, see the precautions for interrupts.
Note 3: Channel CAN1 is not available for M16C/6N1 group.
Note 4: Use IFSR0/ISFR1 (addresses 01DE16 and 01DF16) for interrupt request cause selection.
Figure 1.11.3. Interrupt control registers
60
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this
flag to "1" enables all maskable interrupts; setting to "0" disables all maskable interrupts. This flag is set
to "0" after reset.
Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The
interrupt request bit can also be set to "0" by software. (Do not set this bit to "1".)
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits
of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared
with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.
Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels
enabled, according to the consist of the IPL.
The following are conditions under which an interrupt is accepted.
•interrupt enable flag (I flag) = "1"
•interrupt request bit = "1"
•interrupt priority level > IPL
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are
independent, and they are not affected by one another.
Table 1.11.4. Interrupt levels enabled according
to the contents of the IPL
Table 1.11.3. Settings of interrupt priority
levels
Interrupt priority
level select bit
Interrupt priority
level
Priority
order
Enabled interrupt priority levels
IPL
b2 b1 b0
IPL2
IPL1
IPL0
Level 0 (interrupt disabled)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 4 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
0
0
0
1
1
0
Low
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
High
61
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Rewrite the Interrupt Control Register
To rewrite the interrupt control register, do so at a point when no interrupt request for that register can be
generated. If there is possibility of the interrupt request to occur, rewrite the interrupt control register after
the interrupt is disabled. The program examples are described as follow:
Example 1
INT_SWITCH1:
FCLR
AND.B
NOP
I
;Disable interrupts.
#00h, 0055h
;Clear TA0IC int. priority level and int. request bit.
;Four NOP instructions are required when using HOLD function.
NOP
FSET
I
;Enable interrupts
Example 2
INT_SWITCH2:
FCLR
I
;Disable interrupts.
AND.B
#00h, 0055h
;Clear TA0IC int. priority level and int. request bit.
;Dummy read
MOV.W
MEM, R0
I
FSET
;Enable interrupts
Example 3
INT_SWITCH3:
PUSHC
FLG
;Push Flag register onto stack
;Disable interrupts.
FCLR
I
AND.B
#00h, 0055h
FLG
;Clear TA0IC int. priority level and int. request bit.
;Enable interrupts
POPC
The reason why two NOP instructions (four when using the HOLD function) or dummy read is inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.
When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been
generated. This will depend on the instruction. If this creates problems, use the below instructions to
change the register.
Instructions: AND, OR, BCLR, BSET
62
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Interrupt Sequence
__
An interrupt sequence What are performed over a period from the instant an interrupt is accepted to the
__
instant the interrupt routine is executed is described here.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence from the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the
processor temporarily suspends the instruction being executed, and transfers control to the interrupt se-
quence.
In the interrupt sequence, the processor carries out the following in sequence given:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading
address 0000016. After this, the corresponding interrupt request bit becomes "0".
(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt
sequence †in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag)
to "0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32
through 63, is executed).
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first
instruction within the interrupt routine has been executed. This time comprises the period from the
occurence of an interrupt to the completion of the instruction under execution at that moment (a) and the
time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt responce time.
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
Figure 1.11.4. Interrupt response time
63
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the
DIVX instruction (without wait).
Time (b) is as shown in Table 1.11.5.
Table 1.11.5. Time required for executing the interrupt sequence
Interrupt vector address Stack pointer (SP) value
16-Bit bus, without wait
8-Bit bus, without wait
Even
Even
Odd
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Even
Odd (Note 2)
Odd (Note 2)
Even
Odd
________
Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address coincidence
interrupt or of a single-step interrupt.
Note 2: Locate an interrupt vector address in an even address, if possible.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BCLK
Address
0000
Address bus
Data bus
Indeterminate
Indeterminate
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
R
Indeterminate
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
Figure 1.11.5. Time required for executing the interrupt sequence
Variation of IPL when Interrupt Request is accepted
If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.
If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown
in Table 1.11.6 is set in the IPL.
Table 1.11.6. Relation between interrupts without interrupt priority levels and IPL
Value set in the IPL
Interrupt sources without priority levels
_______
Oscillation stop detection, Watchdog timer, NMI
7
0
Reset
Other
Not changed
64
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC)
are saved in the stack area.
First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8
lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the
program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the interrupt
request, and the state the stack after the acceptance of the interrupt request.
Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM
instruction alone can save all the registers ecept the stack pointer (SP).
Stack area
Stack area
Address
MSB
Address
MSB
LSB
LSB
[SP]
New stack
pointer value
m
m
m
m
m
–
–
–
–
4
3
2
1
m
m
m
m
m
–
–
–
–
4
3
2
1
Program counter (PC
L
)
Program counter (PC
M
)
Flag register (FLG )
L
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
Stack pointer
value before
interrupt occurs
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
m + 1
m + 1
Stack status before interrupt request
is acknowledged
Stack status after interrupt request
is acknowledged
Figure 1.11.6. State of stack before and after acceptance of interrupt request
65
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
The operation of saving registers carried out in the interrupt sequence is dependent on whether the
content of the stack pointer (Note), at the time of acceptance of an interrupt equest, is even or odd. If the
counter of the stack pointer (Note) is even, the counter of the flag register (FLG) and the content of the
program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at
a time. Figure 1.11.7 shows the operation of the saving registers.
Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer
indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).
(1) Stack pointer (SP) contains even number
Sequence in which order
registers are saved
Address
Stack area
[SP] – 5 (Odd)
[SP] – 4 (Even)
[SP] – 3(Odd)
[SP] – 2 (Even)
[SP] – 1(Odd)
Program counter (PC )
L
(2) Saved simultaneously,
all 16 bits
Program counter (PC
M)
Flag register (FLG
L)
(1) Saved simultaneously,
all 16 bits
Flag register
(FLG
Program
counter (PC )
H
)
H
[SP]
(Even)
Finished saving registers
in two operations.
(2) Stack pointer (SP) contains odd number
Address
Stack area
Sequence in which order
registers are saved
[SP] – 5 (Even)
[SP] – 4(Odd)
[SP] – 3 (Even)
[SP] – 2(Odd)
[SP] – 1 (Even)
Program counter (PC )
L
(3)
(4)
Program counter (PC
Flag register (FLG
M
)
Saved simultaneously,
all 8 bits
L
)
(1)
(2)
Program
counter (PC )
Flag register
(FLG
H
H
)
[SP]
(Odd)
Finished saving registers
in four operations.
Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.
After registers are saved, the SP content is [SP] minus 4.
Figure 1.11.7. Operation of saving registers
66
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Returning from an Interrupt Routine
Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register
(FLG) as it was immediately before the start of interrupt sequence and the contents of the program
counter (PC), both of which have been saved in the stack area. Then control returns to the program that
was being executed before the acceptance of the interrupt request, so that the suspendedd process
resumes.
Return the other registers saved by software within the interrupt routine using the POPM or similar
instruction befoere executing the REIT instruction.
Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (checking
whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt aqssigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),
watchdog timer interrupt, etc. are regulated by hardware.
Figure 1.11.8 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
Reset > _N__M___I_ > _D__B___C__ > Oscillation stop detection / Watchdog timer > Peripheral I/O > Single step > Address match
Figure 1.11.8. Hardware interrupts priorities
Interrupt Resolution Circuit
When two or more interupts are generated simultaneously, this circuit selects the interrupt with the
highest priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level.
67
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupt
Priority level of each interrupt
Level 0 (initial value)
INT1
Timer B2
Timer B0
High
Timer A3
Timer A1
UART1 reception
UART0 reception
UART2 reception/ACK
INT2
INT0
Timer B1
Timer A4
Timer A2
Timer A0
UART1 transmission
UART0 transmission
A-D conversion/Key input interrupt
DMA1
Priority of peripheral I/O interrupts
(if priority levels are same)
Bus collision detection
CAN1 reception (Note), INT5
Timer B4
INT3
CAN0 reception
UART2 transmission/NACK
CAN0/1 error (Note)
DMA0
(Note) - - - -
CAN1 transmission, INT4, Serial I/O3
Timer B3
Timer B5
CAN0 transmission
Low
CAN0/1 Wake up (Note)
Processor interrupt priority level (IPL)
Interrupt request level judgement output
to clock generating circuit (Figure 1.10.3)
Interrupt enable flag (I flag)
Interrupt request accepted
Address match
Oscillator stop detection/Watchdog timer
DBC
NMI
Note: Channel CAN1 is not available
for M16C/6N1 group.
Reset
Figure 1.11.9. Maskable interrupts priorities (peripheral I/O interrupts)
68
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
INT Interrupt
______
INT Interrupt
________
________
INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity
select bit.
________
Of interrupt control registers, address 004816 is used both as CAN1 reception and external interrupt INT5
________
input control register, and 004916 is used as S I/O3, CAN1 transmission and as external interrupt INT4 input
control register. Use the interrupt request cause select bits (bit 0 and 1 at address 01DE16 and bit 6 and 7
at address 01DF16) to specify which interrupt request cause to select. After having set an interrupt request
cause, be sure to clear the corresponding interrupt request bit before enabling an interrupt. (Note)
The interrupt control registers (address 004916 and address 004816) have the polarity-switching bit. Be
sure to set this bit to "0" when selecting the S I/O3, CAN1 reseption or CAN1 transmission as the interrupt
request cause. (Note)
As to external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge by
setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register (address
01DF16). To select both edges, set the polarity switching bit of the correponding interrupt control register to
'falling edge' ("0").
Note: Channel CAN1 is not available for M16C/6N1 group.
Figures 1.11.10 and 1.11.11 show the interrupt request cause select registers 0 and 1.
Interrupt request cause select register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR0
Address
01DE16
When reset
XXXXX00016
Bit symbol
IFSR00
R
W
Bit name
Function
Interrupt request cause
select bit
0 : C1TRMIC (Note)
1 : SIO3
0 : AD Converter
1 : Key On Wake Up
Interrupt request cause
select bit
IFSR01
IFSR02
Reserved bit
Always set to "0"
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are
indeterminate.
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.11.10. Interrupt request cause select register 0
Interrupt request cause select register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR1
Address
01DF16
When reset
0016
R
W
Bit symbol
Bit name
Fumction
0 : One edge
1 : Two edges
IFSR10
IFSR11
IFSR12
IFSR13
IFSR14
IFSR15
IFSR16
IFSR17
INT0 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT1 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT2 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT3 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT4 interrupt polarity
swiching bit
0 : One edge
1 : Two edges
INT5 interrupt polarity
swiching bit
Interrupt request cause
select bit
0 : SIO3 / C1TRMIC (Note)
1 : INT4
Interrupt request cause
select bit
0 : C1RECIC (Note)
1 : INT5
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.11.11. Interrupt request cause select register 1
69
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
______
NMI Interrupt
______
NMI Interrupt
______
______
______
An NMI interrupt is generated when the input to the P85/NMI pin changes from "H" to "L". The NMI interrupt
is a non-maskable external interrupt. The pin level can be checked in the port P85 register (bit 5 at address
03F016).
This pin cannot be used as a normal port input.
Key Input Interrupt
If the direction register of any of P104 to P107 is set for input and a falling edge is input to that port, a key
input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-
ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P104 to
P107 as A-D input ports. Figure 1.11.12 shows the block diagram of the key input interrupt. Note that if an
"L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as
an interrupt.
Port P104-P107 pull-up
select bit
Pull-up
Key input interrupt control register
(address 004E16)
transistor
Port P107 direction
register
Port P10
7
direction register
P10
7
/KI
3
2
Port P106 direction
register
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
P10
6
/KI
Pull-up
transistor
Port P10
register
5
direction
direction
P105/KI1
Port P10
register
4
Pull-up
transistor
P104/KI0
Figure 1.11.12. Block diagram of key input interrupt
CAN0/1 Wake up Interrupt
CAN0/1 wake up interrupt occurs when a falling edge is input to CRX0 or CRX1. Use the interrupt in stop/
wait mode or CAN sleep mode. The CAN0/1 wake up interrupt is enabled only when the port is defined as
the CAN port. One interrupt is allocated to CAN0/1. Figure 1.11.13 shows the block diagram of the CAN0/
1 wake up interrupt. (Note)
Please note that the wake up message will be lost.
Note: There is only one CAN channel available for M16C/6N1 group.
CAN0/1 wake up interrupt control register
CAN0 port enable bit
(address 004116
)
P9
5
/CRX0
/CRX1
CAN0/1 wake up
interrupt request
Interrupt control circuit
CAN1 port enable bit
P77
(Note)
Note: Channel CAN1 is not available M16C/6N1 group.
Figure 1.11.13. Block diagram of CAN0/1 wake up interrupt
70
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Address Match Interrupt
Address Match Interrupt
An address match interrupt is generated when the address match interrupt address register contents match
the program counter value. Two address match interrupts can be set, each of which can be enabled and
disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-
rupt enable flag (I flag) and processor interrupt priority level (IPL). The value of the program counter (PC)
for an address match interrupt varies depending on the instruction being executed.
Figure 1.11.14 shows the address match interrupt-related registers.
Address match interrupt enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
000916
When reset
XXXXXX00
2
Bit symbol
AIER0
Bit name
Function
R W
Address match interrupt 0
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Address match interrupt 1
enable bit
AIER1
0 : Interrupt disabled
1 : Interrupt enabled
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.
Address match interrupt register i (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
Symbol
RMAD0
RMAD1
Address
001216 to 001016
001616 to 001416
When reset
X0000016
X0000016
b0
Function
Values that can be set
R W
Address setting register for address match interrupt
0000016 to FFFFF16
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.
Figure 1.11.14. Address match interrupt-related registers
71
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
Precautions for Interrupts
(1) Reading address 0000016
• When maskable interrupt occurs, CPU reads the interrupt information (the interrupt number and
interrupt request level) in the interrupt sequence.
The interrupt request bit of the certain interrupt written in address 0000016 will then be set to "0".
Even if the address 0000016 is read out by software, "0" is set to the enabled highest priority interrupt
source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur.
Do not read address 0000016 by software.
(2) Setting the stack pointer
• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt
before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value for
______
the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack point at
the beginning of a program. Concerning the first instruction immediately after reset, generating any
______
interrupt including the NMI interrupt is prohibited.
72
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
______
(3) The NMI interrupt
______
• As for the NMI pin, an interrupt cannot be disabled. Connect it to the Vcc pin via a resistor (pull-up) if
unused. Be sure to work on it.
______
• The NMI pin also serves as P85, which is exclusively for input. Reading the contents of the P8 register
allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time
______
when the NMI interrupt is input.
______
• Do not reset the CPU with the input to the NMI pin being in the "L" state.
______
• Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to
______
the NMI pin being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned
down.
______
• Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to
______
the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved.
In this instance, the CPU is returned to the normal state by a later interrupt.
______
• Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.
(4) External interrupt
________
• Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT0
________
through INT5 regardless of the CPU operation clock.
________
________
• When the polarity of the INT0 to INT5 pins is changed, the interrupt request bit is sometimes set to "1".
After changing the polarity, set the interrupt request bit to "0". Figure 1.11.15 shows the procedure for
______
changing the INT interrupt generate factor.
Clear the interrupt enable flag to "0"
(Disable interrupt)
Set the interrupt priority level to level 0
(Disable INTi interrupt)
Set the polarity select bit
Clear the interrupt request bit to "0"
Set the interrupt priority level to level 1 to 7
(Enable the accepting of INTi interrupt request)
Set the interrupt enable flag to "1"
(Enable interrupt)
Note: Execute the setting above individually. Don’t execute two or more setting at once (by one instruction).
______
Figure 1.11.15. Switching condition of INT interrupt request
73
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Precautions for Interrupts
(5) Rewrite the interrupt control register
• To rewrite the interrupt control register, do so at a point when no interrupt request for that register can
be generated. If there is possibility of the interrupt request to occur, rewrite the interrupt control register
after the interrupt is disabled. The program examples are described as follow:
Example 1
INT_SWITCH1:
FCLR
AND.B
NOP
I
;Disable interrupts.
#00h, 0055h
;Clear TA0IC int. priority level and int. request bit.
;Four NOP instructions are required when using HOLD function.
NOP
FSET
I
;Enable interrupts
Example 2
INT_SWITCH2:
FCLR
I
;Disable interrupts.
AND.B
#00h, 0055h
;Clear TA0IC int. priority level and int. request bit.
;Dummy read
MOV.W
MEM, R0
I
FSET
;Enable interrupts
Example 3
INT_SWITCH3:
PUSHC
FLG
;Push Flag register onto stack
;Disable interrupts.
FCLR
I
AND.B
#00h, 0055h
FLG
;Clear TA0IC int. priority level and int. request bit.
;Enable interrupts
POPC
The reason why two NOP instructions (four when using the HOLD function) or dummy read is
inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set
before the interrupt control register is rewritten due to effects of the instruction queue.
• When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been
generated. This will depend on the instruction. If this creates problems, use the below instructions to
change the register.
Instructions: AND, OR, BCLR, BSET
74
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer
The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-
mend using the watchdog timer to improve reliability of a system. The watchdog timer is a 15-bit counter
which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is
generated when an underflow occurs in the watchdog timer. When XIN is selected as BCLK, bit 7 of the
watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When
XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer
control register (address 000F16). Thus the watchdog timer's period can be calculated as given below. The
watchdog timer's period is, however, subject to an error due to the prescaler.
With XIN chosen for BCLK
prescaler dividing ratio (16 or 128) X watchdog timer count (32768)
Watchdog timer period =
BCLK
With XCIN chosen for BCLK
prescaler dividing ratio (2) X watchdog timer count (32768)
Watchdog timer period =
BCLK
For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the
prescaler, then the watchdog timer's period becomes approximately 32.8 ms.
The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a
watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is
reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by
writing to the watchdog timer start register (address 000E16). In stop mode, wait mode and hold state, the
watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or
state are released.
Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-
related registers.
Prescaler
CM07 = "0"
WDC7 = "0"
1/16
CM07 = "0"
WDC7 = "1"
BCLK
Watchdog timer
interrupt request
1/128
1/2
Watchdog timer
HOLD
CM07 = "1"
Write to the watchdog timer
start register
Set to
"7FFF16
(address 000E16
)
"
RESET
Figure 1.12.1. Block diagram of watchdog timer
75
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Watchdog Timer
Watchdog Timer during Wait and Clock Stop Modes
The watchdog timer is supplied by the BCLK. If the BCLK stops, the watchdog timer stops also. When
executing a WAIT instruction, the BCLK stops and watchdog timer operation is suspended. The same ap-
plies when entering Stop Mode (CM10 = "1"). Watchdog timer operation recommences when either mode is
cancelled.
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000F16
When reset
000XXXXX2
0 0
Bit symbol
Bit name
Function
R W
High-order bits of watchdog timer
Reserved bit
This bit can neither be set nor reset.
Must always be set to "0"
Reserved bit
WDC7
Prescaler select bit
0 : Divided by 16
1 : Divided by 128
Watchdog timer start register
b7
b0
Symbol
WDTS
Address
000E16
When reset
Indeterminate
Function
R W
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to "7FFF16"
regardless of whatever value is written.
Figure 1.12.2. Watchdog timer control and start registers
76
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAC
This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to
memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a
higher right of using the bus than the CPU, performing the cycle steal method. On this account, the opera-
tion from the occurrence of DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit)
data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram of the DMAC. Table
1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers used by the DMAC.
Address bus
DMA0 source pointer SAR0(20)
(addresses 002216 to 002016
DMA0 destination pointer DAR0 (20)
(addresses 002616 to 002416
DMA0 forward address pointer (20) (Note)
)
)
DMA0 transfer counter reload register TCR0 (16)
DMA1 source pointer SAR1 (20)
(addresses 003216 to 003016
DMA1 destination pointer DAR1 (20)
(addresses 003616 to 003416
DMA1 forward address pointer (20) (Note)
(addresses 002916, 002816
)
)
DMA0 transfer counter TCR0 (16)
)
DMA1 transfer counter reload register TCR1 (16)
(addresses 003916, 003816
)
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter TCR1 (16)
Data bus low-order bits
Data bus high-order bits
Note: Pointer is incremented by a DMA request.
Figure 1.13.1. Block diagram of DMAC
Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer
request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the
interrupt priority level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to "1"), data transfer starts every time a DMA transfer
request signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the
DMA transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the
number of transfers. For details, see the description of the DMA request bit.
77
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
Table 1.13.1. DMAC specifications
Item
No. of channels
Specification
2 (cycle steal method)
Transfer memory space
• From any address in the 1M bytes space to a fixed address
• From a fixed address to any address in the 1M bytes space
• From a fixed address to a fixed address
(Note that DMA related registers [002016 to 003
128K bytes (with 16 bit transfers) or 64K bytes (with 8 bit transfers)
Falling edge of INT or INT (INT can be selected by DMA0, INT by
DMA1) or both edge
F16] cannot be accessed)
Maximum No. of bytes transferred
DMA request factors (Note)
0
1
0
1
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transmission and reception interrupt requests
UART1 transmission and reception interrupt requests
UART2 transmission and reception interrupt requests
Serial I/O3 interrupt request
A-D conversion interrupt requests
Software triggers
Channel priority
DMA0 takes precedence if DMA0 and DMA1 requests are generated
simultaneously
Transfer unit
8 bits or 16 bits
Transfer address direction
forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
Transfer mode
• Single transfer mode
After the transfer counter underflows, the DMA enable bit turns to "0", and
the DMAC turns inactive
• Repeat transfer mode
After the transfer counter underflows, the value of the transfer counter reload
register is reloaded to the transfer counter.
The DMAC remains active unless a "0" is written to the DMA enable bit.
DMA interrupt request generation When an underflow occurs in the transfer counter
timing
When the DMA enable bit is set to "1", the DMAC is active.
When the DMAC is active, data transfer starts every time a DMA transfer
request signal occurs.
Active
Inactive
• When the DMA enable bit is set to "0", the DMAC is inactive.
• After the transfer counter underflows in single transfer mode.
At the time of starting data transfer immediately after turning the DMAC
active, the value of one of source pointer and destination pointer - the one
specified for the forward direction - is reloaded to the forward direction
address pointer, and the value of the transfer counter reload register is
reloaded to the transfer counter.
Reload timing for forward address
pointer and transfer counter
Writing to register
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is "0".
Reading the register
Can be read at any time.
However, when the DMA enable bit is "1", reading the register set up as
the forward register is the same as reading the value of the forward
address pointer.
Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable flag
(I flag) nor by the interrupt priority level.
78
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA0 request cause select register
Symbol
DM0SL
Address
03B816
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Function
Bit symbol
DSEL0
Bit name
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 pin
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)
/two edges of INT0 pin (DMS=1)
0 1 1 1 : Timer B0 (DMS=0)
Timer B3 (DMS=1)
1 0 0 0 : Timer B1 (DMS=0)
Timer B4 (DMS=1)
1 0 0 1 : Timer B2 (DMS=0)
Timer B5 (DMS=1)
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit
DSEL1
DSEL2
DSEL3
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
0 : Normal
1 : Expanded cause
DMA request cause
expansion bit
DMS
DSR
If software trigger is selected, a
DMA request is generated by setting
this bit to "1" (When read, the value
of this bit is always "0")
Software DMA
request bit
Figure 1.13.2. DMAC register (1)
79
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA1 request cause select register
Symbol
DM1SL
Address
03BA16
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit name
Function
Bit symbol
DSEL0
R
W
b3 b2 b1 b0
DMA request cause
select bit
0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)
/serial I/O3 (DMS=1)
0 1 1 0 : Timer A4 (DMS=0)
0 1 1 1 : Timer B0 (DMS=0)
/two edges of INT1 (DMS=1)
1 0 0 0 : Timer B1
DSEL1
DSEL2
DSEL3
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
0 : Normal
1 : Expanded cause
DMA request cause
expansion select bit
DMS
DSR
Software DMA
request bit
If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")
DMAi control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DMiCON(i=0,1)
Address
002C16, 003C16
When reset
00000X002
Bit symbol
DMBIT
Bit name
Function
R W
Transfer unit bit select
bit
0 : 16 bits
1 : 8 bits
Repeat transfer mode
select bit
0 : Single transfer
1 : Repeat transfer
DMASL
DMAS
DMAE
DMA request bit
(Note 1)
0 : DMA not requested
1 : DMA requested
(Note 2)
0 : Disabled
1 : Enabled
DMA enable bit
Source address direc-
tion select bit (Note 3)
0 : Fixed
1 : Forward
DSD
DAD
Destination address direc
tion select bit (Note 3)
0 : Fixed
1 : Forward
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to "0".
Note 3: Source address direction select bit and destination address direction select bit
cannot be set to "1" simultaneously.
Figure 1.13.3. DMAC register (2)
80
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMAi source pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
SAR0
SAR1
Address
002216 to 002016
003216 to 003016
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Source pointer
Stores the source address
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
DMAi destination pointer (i = 0, 1)
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
(b23)
b7
b0
Symbol
DAR0
DAR1
Address
002616 to 002416
003616 to 003416
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Destination pointer
Stores the destination address
0000016 to FFFFF16
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
DMAi transfer counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
002916, 002816
003916, 003816
When reset
Indeterminate
Indeterminate
Transfer count
specification
Function
R W
• Transfer counter
Set a value one less than the transfer count
000016 to FFFF16
Figure 1.13.4. DMAC register (3)
81
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) Transfer cycle
The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area
(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination
write). The number of read and write bus cycles depends on the source and destination addresses. In
memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-
pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.
(a) Effect of source and destination addresses
When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd
addresses, there are one more source read cycle and destination write cycle than when the source
and destination both start at even addresses.
(b) Effect of BYTE pin level
When transferring 16-bit data over an 8-bit data bus (BYTE pin = "H") in memory expansion mode and
microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are
required for reading the data and two are required for writing the data. Also, in contrast to when the
CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal
RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.
(c) Effect of software wait
When the SFR area or a memory area with a software wait is accessed, the number of cycles is
increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.
Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destination
write cycle is shown as one cycle and the source read cycles for the different conditions are shown. In
reality, the destination write cycle is subject to the same conditions as the source read cycle, with the
transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respective
conditions to both the destination write cycle and the source read cycle. For example (2) in Figure 1.13.5, if
data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read
cycle and the destination write cycle.
82
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(1) 8-bit transfers
16-bit transfers and the source address is even.
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(2) 16-bit transfers and the source address is odd
Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination write cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1 Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source + 1
Source
CPU use
Destination
(3) One wait is inserted into the source read under the conditions in (1)
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(4) One wait is inserted into the source read under the conditions in (2)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles).
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
Note: The same timing changes occur with the respective conditions at the destination as at the source.
Figure 1.13.5. Example of the transfer cycles for a source read
83
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 1.13.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 1.13.2. No. of DMAC transfer cycles
Memory expansion mode
Single-chip mode
Microprocessor mode
Transfer unit
Bus width
Access address
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
16-bit
(BYTE= "L")
8-bit
Even
Odd
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
2
2
2
8-bit transfers
(DMBIT= "1")
Even
Odd
—
—
1
—
—
1
(BYTE = "H")
16-bit
Even
Odd
16-bit transfers
(DMBIT= "0")
(BYTE = "L")
8-bit
2
2
Even
Odd
—
—
—
—
(BYTE = "H")
Coefficient j, k
Internal memory
External memory
InternalROM/RAM InternalROM/RAM SFR area Separate bus Separate bus
Multiplex
No wait
1
With wait
2
No wait
1
With wait
2
bus
3
2
84
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
DMA Enable Bit
Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations
at the time data transfer starts immediately after DMAC is turned active.
(1) Reloads the value of the source pointer or the destination pointer - the one specified for the forward
direction - to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations de-
scribed above, so the DMA operates again, beginning from the initial state instantly when "1" is overwrit-
ten to the DMA enable bit.
DMA Request Bit
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of
DMA request factors for each channel.
DMA request factors include the following.
• Factors effected by using the interrupt request signals from the built-in peripheral functions and software
DMA factors (internal factors) effected by a program.
• External factors effected by utilizing the input from external interrupt signals.
The DMA request factor is selected by the DMA request cause select bits (bit 0 to 3 at addresses 03B816
and 03BA16).
The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state
(Whether the DMA enable bit is set to "1" or "0"). It turns to "0" immediately before data transfer starts.
In addition, the DMA request bit can be set to "0" by use of a program, but cannot be set to "1".
There can be instances in which a change in DMA request cause select bits cause the DMA request bit to
turn to "1". So be sure to set the DMA request bit to "0" after the DMA request cause select bits are
changed.
The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately
before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the
DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the
DMAC is active, read the DMA enable bit.
Here follows the timing of changes in the DMA request bit.
(1) Internal factors
Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due
to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to
turn to "1" due to several factors.
Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately before the
transfer starts.
(2) External factors
_______
An external factor is caused to occur by the leading edge of input from the INTi pin (i depends on which
DMAC channel is used).
_______
Selecting the INTi pins as external factors using the DMA request cause select bits cause input from
these pins to become the DMA transfer request signals.
The timing for the DMA request bit to turn to "1" when an external factor is selected, synchronizes with the
signal's edge applicable to the function specified by the DMA request cause select bits (synchronizes with
_______
the trailing edge of the input signal to each INTi pin, for example).
With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data
transfer starts similarly to the state in which an internal factor is selected.
85
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
DMAC
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU after transfer is finished.
An example which shows DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur, is given below.
Figure 1.13.6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
Obtainment
of the bus
right
DMA1
CPU
INT
0
DMA0
request bit
INT
1
DMA1
request bit
Figure 1.13.6. An example of DMA transfer effected by external factors
86
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
Timer
There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B
(six). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers.
PCLK0 = "1"
Clock prescaler
f
2
1/2
X
IN
f
C32
1/32
Reset
X
CIN
PCLK0 = "0"
1/4
f
8
Clock prescaler reset flag (bit 7
at address 038116) set to "1"
f
32
1/4
f
8
f32
f
2
fC32
• Timer mode
• One-shot mode
• PWM mode
Timer A0 interrupt
Timer A0
Noise
filter
TA0IN
(Note)
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A1
Noise
filter
TA1IN
TA2IN
TA3IN
TA4IN
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A2
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A3
Noise
filter
• Event counter mode
• Timer mode
• One-shot mode
• PWM mode
Timer A4
Noise
filter
• Event counter mode
Timer B2 overflow
Note: The TA0IN pin (P7 ) is shared with TB5IN, RxD2 and SCL pin, so to be careful.
1
Figure 1.14.1. Timer A block diagram
87
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M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer
PCLK0 = "1"
PCLK0 = "0"
Clock prescaler
f
2
1/2
X
IN
f
C32
1/32
Reset
X
CIN
f
8
1/4
Clock prescaler reset flag (bit 7
at address 038116) set to "1"
f
32
1/4
f2 f8 f32 fC32
Timer A
• Timer mode
• Pulse width measuring mode
Timer B0 interrupt
Timer B1 interrupt
Noise
filter
TB0IN
TB1IN
Timer B0
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
Timer B1
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B2 interrupt
Noise
filter
TB2IN
Timer B2
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B3 interrupt
Timer B4 interrupt
Noise
filter
TB3IN
TB4IN
Timer B3
• Event counter mode
• Timer mode
• Pulse width measuring mode
Noise
filter
Timer B4
• Event counter mode
• Timer mode
• Pulse width measuring mode
Timer B5 interrupt
Noise
filter
TB5IN
(Note)
Timer B5
• Event counter mode
Note: The TB5IN pin (P71) is shared with TA0IN, RxD2 and SCL pin, so to be careful.
Figure 1.14.2. Timer B block diagram
88
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer A
Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related registers.
Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode
register (i = 0 to 4) bits 0 and 1 to choose the desired mode.
Timer A has the four operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer over flow.
• One-shot timer mode: The timer stops counting when the count reaches "000016".
• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.
Data bus high-order bits
Clock source
selection
Data bus low-order bits
• Timer
• One shot
• PWM
f2
f8
f32
fC32
Low-order
8 bits
High-order
8 bits
• Timer
(gate function)
Reload register (16)
• Event counter
Counter (16)
Polarity
selection
Up count/down count
Clock selection
TAiIN
Always down count except
in event counter mode
(i = 0 to 4)
Count start flag
(Address 038016)
(Note)
TAi
Addresses
TAj
TAk
Down count
Timer A0 038716 038616
Timer A1 038916 038816
Timer A4 Timer A1
Timer A0 Timer A2
TB2 overflow
External
trigger
Up/down flag
Timer A2 038B16 038A16 Timer A1 Timer A3
Timer A3 038D16 038C16 Timer A2 Timer A4
Timer A4 038F16 038E16 Timer A3 Timer A0
TAj overflow
(j = i – 1. Note, however, that j = 4 when i = 0)
(Address 038416)
TAk overflow
(k = i + 1. Note, however, that k = 0 when i = 4)
Pulse output
TAiOUT
(i = 0 to 4)
Toggle flip-flop
Note: The TA0IN pin (P71) is shared with TB5IN, RxD2 and SCL pin, so to be careful.
Figure 1.14.3. Block diagram of timer A
Timer Ai mode register
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i=0 to 4) 039616 to 039A16
R W
Bit symbol
TMOD0
Bit name
Function
b1 b0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation
(PWM) mode
TMOD1
MR0
MR1
MR2
MR3
TCK0
TCK1
Function varies with each operation mode
Count source select bit
(Function varies with each operation mode)
Figure 1.14.4. Timer A-related registers (1)
89
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Timer Ai register (Note 1)
Symbol
TA0
TA1
TA2
TA3
TA4
Address
When reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
(b15)
b7
(b8)
b0 b7
038716,038616
038916,038816
038B16,038A16
038D16,038C16
038F16,038E16
b0
Values that can be set
Function
R W
• Timer mode
Counts an internal count source
000016 to FFFF16
• Event counter mode
Counts pulses from an external source or timer overflow
000016 to FFFF16
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
(Note 2,4)
• Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator
000016 to FFFE16
(Note 3,4)
0016 to FE16
(High-order address)
• Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator
0016 to FF16
(Low-order address)
(Note 3,4)
Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "000016", the counter does not
operate and the timer Ai interrupt request is not generated. When the
pulse is set to output, the pulse does not output from the TAiOUT pin.
Note 3: When the timer Ai register is set to "000016", the pulse width
modulator does not operate and the output level of the TAiOUT pin
remains "L" level, therefore the timer Ai interrupt request is not
generated. This also occurs in the 8-bit pulse width modulator mode
when the significant 8 high-order bits in the timer Ai register are set
to "0016".
Note 4: Use MOV instruction to write to this register.
Count start flag
Symbol
TABSR
Address
038016
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Up/down flag (Note 1)
Symbol
UDF
Address
038416
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
TA0UD
Bit name
Function
Timer A0 up/down flag
0 : Down count
1 : Up count
TA1UD
TA2UD
TA3UD
TA4UD
TA2P
Timer A1 up/down flag
Timer A2 up/down flag
Timer A3 up/down flag
Timer A4 up/down flag
This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause
0 : two-phase pulse signal
processing disabled
1 : two-phase pulse signal
processing enabled (Note 2)
Timer A2 two-phase pulse
signal processing select bit
TA3P
TA4P
Timer A3 two-phase pulse
signal processing select bit
When not using the two-phase
pulse signal processing function,
set the select bit to "0"
Timer A4 two-phase pulse
signal processing select bit
Note 1: Use MOV instruction to write to this register.
Note 2: Set the TAiIN and TAiOUT pins correspondent port direction registers
to "0".
Figure 1.14.5. Timer A-related registers (2)
90
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
One-shot start flag
Symbol
ONSF
Address
038216
When reset
00X000002
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
Timer A0 one-shot start flag
Timer A1 one-shot start flag
Timer A2 one-shot start flag
Timer A3 one-shot start flag
Timer A4 one-shot start flag
TA0OS
TA1OS
TA2OS
TA3OS
TA4OS
1 : Timer start
When read, the value is "0"
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
b7 b6
TA0TGL
TA0TGH
Timer A0 event/trigger
select bit
0 0 : Input on TA0IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected
Note: Set the corresponding port direction register to "0".
Trigger select register
Symbol
TRGSR
Address
038316
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
b3 b2
TA1TGH
Timer A2 event/trigger
select bit
TA2TGL
TA2TGH
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
b5 b4
Timer A3 event/trigger
select bit
TA3TGL
TA3TGH
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
0 : No effect
1 : Prescaler is reset
CPSR
Clock prescaler reset flag
(When read, the value is "0")
Figure 1.14.6. Timer A-related registers (3)
91
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7
shows the timer Ai mode register in timer mode.
Table 1.14.1. Specifications of timer mode
Item
Specification
Count source
f
2, f
8, f32, fc32
Count operation
• Down count
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= "1")
Count start flag is reset (= "0")
Interrupt request
generation timing
When the timer underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or gate input
Programmable I/O port or pulse output
Count value can be read out by reading timer Ai register
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
• Gate function
Counting can be started and stopped by the TAiIN pin’s input signal
• Pulse output function
Each time the timer underflows, the TAiOUT pin’s polarity is reversed
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i=0 to 4) 039616 to 039A16
0
0 0
Bit symbol
Bit name
Function
R W
b1 b0
Operation mode
select bit
TMOD0
TMOD1
MR0
0 0 : Timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
b4 b3
Gate function select bit
MR1
MR2
0 X (Note 2): Gate function not available
(TAiIN pin is a normal port pin)
1 0 : Timer counts only when TAiIN pin is
held "L" (Note 3)
1 1 : Timer counts only when TAiIN pin is
held "H" (Note 3)
MR3
0 (Must always be fixed to "0" in timer mode)
b7 b6
Count source select bit
0 0 : f2
TCK0
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
Note 1: The settings of the corresponding port register and port direction register are
invalid.
Note 2: The bit can be "0" or "1".
Note 3: Set the corresponding port direction register to "0".
Figure 1.14.7. Timer Ai mode register in timer mode
92
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal.
Figure 1.14.8 shows the timer Ai mode register in event counter mode.
Table 1.14.2 lists timer specifications when counting a two-phase external signal. Figure 1.14.9 shows
the timer Ai mode register in event counter mode.
Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)
Item
Specification
Count source
•
•
•
External signals input to TAiIN pin (effective edge can be selected by software)
TB2 overflow, TAj overflow
Up count or down count can be selected by external signal or software
When the timer overflows or underflows, it reloads the reload register con
tents before continuing counting (Note)
Count operation
Divide ratio
•
1/ (FFFF16 - n + 1) for up count
1/ (n + 1) for down count
n : Set value
Count start condition
Count stop condition
Count start flag is set (= "1")
Count start flag is reset (= "0")
Interrupt request
generation timing
The timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or count source input
Programmable I/O port, pulse output, or up/down count select input
Count value can be read out by reading timer Ai register
•
When counting stopped
When a value is written to timer Ai register, it is written to both reload register and counter
•
When counting in progress
When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)
Select function
•
•
Free-run count function
Even when the timer overflows or underflows, the reload register content is not reloaded to it
Pulse output function
Each time the timer overflows or underflows, the TAiOUT pin’s polarity is reversed
Note: This does not apply when the free-run function is selected.
Timer Ai mode register
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TAiMR(i = 0, 1)
Address
039616, 039716
When reset
0016
0
0 1
Bit symbol
Bit name
Function
R W
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
0 1 : Event counter mode (Note 1)
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 2)
(TAiOUT pin is a pulse output pin)
MR1
MR2
Count polarity
select bit (Note 3)
0 : Counts external signal’s falling edge
1 : Counts external signal’s rising edge
Up/down switching
cause select bit
0 : Up/down flag’s content
1 : TAiOUT pin’s input signal (Note 4)
MR3
0 (Must always be fixed to "0" in event counter mode)
TCK0
Count operation type
select bit
0 : Reload type
1 : Free-run type
Invalid in event counter mode
Can be "0" or "1"
TCK1
Note 1: In event counter mode, the count source is selected by the event / trigger select
bit (addresses 038216 and 038316).
Note 2: The settings of the corresponding port register and port direction register
are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an "L" signal is input to the TAiOUT pin, the downcount is activated. When
"H", the upcount is activated. Set the corresponding port direction register to "0".
Figure 1.14.8. Timer Ai mode register in event counter mode
93
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Table 1.14.3. Timer specifications in event counter mode (when processing two-phase pulse
signal with timers A2, A3, and A4)
Item
Count source
Count operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pin
• Up count or down count can be selected by two-phase pulse signal
• When the timer overflows or underflows, the reload register content is
reloaded and the timer starts over again (Note 1)
1/ (FFFF16 -n + 1) for up count
Divide ratio
1/ (n + 1) for down count
n : Set value
Count start condition
Count stop condition
Count start flag is set (= "1")
Count start flag is reset (= "0")
Interrupt request generation timing Timer overflows or underflows
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Two-phase pulse input (Set the TAiIN pin correspondent port direction register to "0")
Two-phase pulse input (Set the TAiOUT pin correspondent port direction register to "0"
Count value can be read out by reading timer A2, A3, or A4 register
• When counting stopped
)
When a value is written to timer A2, A3, or A4 register, it is written to both
reload register and counter
• When counting in progress
When a value is written to timer A2, A3, or A4 register, it is written to only
reload register. (Transferred to counter at next reload time.)
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on the TAiIN
pin when input signal on the TAiOUT pin is "H".
Select function (Note 2)
TAiOUT
TAiIN
(i=2,3)
Up
count
Up
count
Up
Down
Down
count
Down
count
count count
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that the TAiIN pin goes "H" when the input
signal on the TAiOUT pin is "H", the timer counts up rising and falling edges
on the TAiOUT and TAiIN pins. If the phase relationship is such that the
TAiIN pin goes "L" when the input signal on the TAiOUT pin is "H", the timer
counts down rising and falling edges on the TAiOUT and TAiIN pins.
TAiOUT
Count down all edges
Count up all edges
TAiIN
(i=3,4)
Count up all edges
Count down all edges
Note 1: This does not apply when the free-run function is selected.
Note 2: Timer A3 can be selected. Timer A2 is fixed to normal processing operation, and timer A4 is fixed
to multiply-by-4 processing operation.
94
Mitsubishi microcomputers
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Timer A
Timer Ai mode register
(When using two-phase pulse signal processing)
Symbol
Address
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
TAiMR(i = 2 to 4) 039816 to 039A16
0
1 0 0 0 1
Bit symbol
Bit name
Function
0 1 : Event counter mode
R W
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 (Must always be "0" when using two-phase pulse signal
processing)
MR0
MR1
MR2
0 (Must always be "0" when using two-phase pulse signal
processing)
1 (Must always be "1" when using two-phase pulse signal
processing)
0 (Must always be "0" when using two-phase pulse signal
processing)
MR3
Count operation type
select bit
0 : Reload type
1 : Free-run type
TCK0
Two-phase pulse
processing operation
select bit (Note 1)(Note 2)
TCK1
0 : Normal processing operation
1 : Multiply-by-4 processing operation
Note 1: This bit is valid for timer A3 mode register.
Timer A2 is fixed to normal processing operation, and timer A4 is fixed to multiply-
by-4 processing operation.
Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse
signal processing operation select bit (address 038416) is set to "1". Also, always be
sure to set the event/trigger select bit (address 038316) to "00".
Figure 1.14.9. Timer Ai mode register in event counter mode
95
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(3) One-shot timer mode
In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.14.10 shows the timer Ai mode register in one-shot
timer mode.
Table 1.14.4. Timer specifications in one-shot timer mode
Item
Count source
Count operation
Specification
f
2, f
8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width
n / fi n : Set value
•
•
•
•
•
•
Cycle time
High level width
Cycle time
External trigger is input
The timer overflows
(216-1) / fi fixed
8-bit PWM
n
(m+1) / fi
n : values set to timer Ai register’s high-order address
m : values set to timer Ai register’s low-order address
(28
-1) (m+1) / fi
Count start condition
The count start flag is set (= "1")
Count stop condition
Interrupt request
generation timing
• The count start flag is reset (= "0")
PWM pulse goes "L"
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progressWhen a value is written to timer Ai register, it is
written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 0 to 4) 039616 to 039A16
0
1 0
Bit symbol
Bit name
R W
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 0 : One-shot timer mode
Pulse output function
select bit
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output (Note 1)
(TAiOUT pin is a pulse output pin)
MR1
MR2
0 : Falling edge of TAiIN pin’s input signal (Note 3)
1 : Rising edge of TAiIN pin’s input signal (Note 3)
External trigger select
bit (Note 2)
0 : One-shot start flag is valid
1 : Selected by event/trigger select bits
Trigger select bit
MR3
0 (Must always be "0" in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
2
8
0 1 : f
TCK1
1 0 : f32
1 1 : fC32
Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses
038216 and 038316). If timer overflow is selected, this bit can be "1" or "0".
Note 3: Set the corresponding port direction register to "0".
Figure 1.14.10. Timer Ai mode register in one-shot timer mode
96
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
(4) Pulse width modulation (PWM) mode
In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the counter
functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.14.11 shows the timer
Ai mode register in pulse width modulation mode. Figure 1.14.12 shows the example of how a 16-bit pulse width
modulator operates. Figure 1.14.13 shows the example of how an 8-bit pulse width modulator operates.
Table 1.14.5. Timer specifications in pulse width modulation mode
Item
Count source
Count operation
Specification
f
2, f
8, f32, fC32
• The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
•
•
The timer reloads a new count at a rising edge of PWM pulse and continues counting
The timer is not affected by a trigger that occurs when counting
16-bit PWM
• High level width
n / fi n : Set value
•
•
•
•
•
•
Cycle time
High level width
Cycle time
External trigger is input
The timer overflows
(216-1) / fi fixed
8-bit PWM
n
(m+1) / fi
n : values set to timer Ai register’s high-order address
m : values set to timer Ai register’s low-order address
(28
-1) (m+1) / fi
Count start condition
The count start flag is set (= "1")
Count stop condition
Interrupt request
generation timing
• The count start flag is reset (= "0")
PWM pulse goes "L"
TAiIN pin function
TAiOUT pin function
Read from timer
Write to timer
Programmable I/O port or trigger input
Pulse output
When timer Ai register is read, it indicates an indeterminate value
• When counting stopped
When a value is written to timer Ai register, it is written to both reload
register and counter
• When counting in progressWhen a value is written to timer Ai register, it is
written to only reload register
(Transferred to counter at next reload time)
Timer Ai mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
0016
TAiMR(i = 0 to 4) 039616 to 039A16
1
1 1
Bit symbol
Bit name
R W
Function
b1 b0
TMOD0
TMOD1
MR0
Operation mode select bit
1 1 : PWM mode
1 (Must always be "1" in PWM mode)
0: Falling edge of TAiIN pin’s input signal (Note 2)
1: Rising edge of TAiIN pin’s input signal (Note 2)
External trigger select
bit (Note 1)
MR1
MR2
0: Count start flag is valid
1: Selected by event/trigger select register
Trigger select bit
0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator
16/8-bit PWM mode
select bit
MR3
b7 b6
TCK0
Count source select bit
0 0 : f
0 1 : f
1 0 : f32
2
8
TCK1
1 1 : fC32
Note 1: Valid only when the TAiIN pin is selected by the event/trigger select bit (addresses
038216 and 038316). If timer overflow is selected, this bit can be "1" or "0".
Note 2: Set the corresponding port direction register to "0".
Figure 1.14.11. Timer Ai mode register in pulse width modulation mode
97
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer A
Condition: Reload register = 000316, when external trigger
(rising edge of TAiIN pin input signal) is selected
1 / fi X
(216 – 1)
Count source
"H"
"L"
TAiIN pin
input signal
Trigger is not generated by this signal
1 / f
i
X n
"H"
"L"
PWM pulse output
from TAiOUT pin
"1"
"0"
Timer Ai interrupt
request bit
f
i
: Frequency of count source
(f , f , f32, fC32
2
8
)
Cleared to "0" when interrupt request is accepted, or cleared by software
Note: n = 000016 to FFFE16
.
Figure 1.14.12. Example of how a 16-bit pulse width modulator operates
Condition : Reload register high-order 8 bits = 0216
Reload register low-order 8 bits = 0216
External trigger (falling edge of TAiIN pin input signal) is selected
1 / fi
X (m+ 1) X (28 – 1)
Count source (Note1)
TAiIN pin input signal
"H"
"L"
1 / fi X (m + 1)
"H"
"L"
Underflow signal of
8-bit prescaler (Note2)
1 / fi X (m + 1) X n
"H"
"L"
PWM pulse output
from TAiOUT pin
"1"
"0"
Timer Ai interrupt
request bit
fi
: Frequency of count source
(f , f , f32, fC32
Cleared to "0" when interrupt request is accepted, or cleaerd by software
2
8
)
Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler’s underflow signal.
Note 3: m = 0016 to FE16; n = 0016 to FE16
.
Figure 1.14.13. Example of how an 8-bit pulse width modulator operates
98
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Timer B
Figure 1.14.14 shows the block diagram of timer B. Figures 1.14.15 and 1.14.16 show the timer B-related registers.
Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.
Timer B has three operation modes listed as follows:
• Timer mode: The timer counts an internal count source.
• Event counter mode: The timer counts pulses from an external source or a timer overflow.
• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or
pulse width.
Data bus high-order bits
Data bus low-order bits
Clock source selection
High-order 8 bits
Low-order 8 bits
f2
• Timer
Reload register (16)
• Pulse period/pulse width measurement
f8
f32
fC32
Counter (16)
• Event counter
Count start flag
Polarity switching
and edge pulse
TBiIN
(i = 0 to 5)
(address 038016)
Counter reset circuit
Can be selected in only
event counter mode
TBi
Address
TBj
TBj overflow
Timer B0 039116 039016 Timer B2
Timer B1 039316 039216 Timer B0
Timer B2 039516 039416 Timer B1
Timer B3 01D116 01D016 Timer B5
Timer B4 01D316 01D216 Timer B3
Timer B5 01D516 01D416 Timer B4
(j = i – 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)
Figure 1.14.14. Block diagram of timer B
Timer Bi mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 5) 039B16 to 039D16
01DB16 to 01DD16
00XX0000
2
00XX0000
2
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
Operation mode select bit
0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width
measurement mode
TMOD1
1 1 : Must not be set
MR0
MR1
MR2
Function varies with each operation mode
(Note 1)
(Note 2)
MR3
TCK0
TCK1
Count source select bit
(Function varies with each operation mode)
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.14.15. Timer B-related registers (1)
99
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
Symbol
TB0
TB1
TB2
TB3
TB4
TB5
Address
When reset
039116, 039016 Indeterminate
039316, 039216 Indeterminate
039516, 039416 Indeterminate
01D116, 01D016 Indeterminate
01D316, 01D216 Indeterminate
01D516, 01D416 Indeterminate
Timer Bi register (Note)
(b15)
(b8)
b7
b0 b7
b0
Values that can be set
000016 to FFFF16
Function
R W
• Timer mode
Counts the timer’s period
• Event counter mode
000016 to FFFF16
Counts external pulses input or a timer overflow
• Pulse period / pulse width measurement mode
Measures a pulse period or width
Note: Read and write data in 16-bit units.
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
0016
R W
Bit symbol
TA0S
Bit name
Function
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Timer B3, 4, 5 count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBSR
Address
01C016
When reset
000XXXXX
2
R W
Bit symbol
Bit name
Function
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
TB3S
TB4S
TB5S
Timer B3 count start flag
Timer B4 count start flag
Timer B5 count start flag
0 : Stops counting
1 : Starts counting
Clock prescaler reset flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
038116
When reset
0XXXXXXX
2
Bit symbol
Bit name
Function
R W
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
0 : No effect
CPSR
Clock prescaler reset flag
1 : Prescaler is reset
(When read, the value is "0")
Figure 1.14.16. Timer B-related registers (2)
100
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.6.) Figure 1.14.17
shows the timer Bi mode register in timer mode.
Table 1.14.6. Timer specifications in timer mode
Item
Count source
Count operation
Specification
f
2
, f
8, f32, fC32
• Counts down
•
When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1) n : Set value
Count start condition
Count stop condition
Count start flag is set (= "1")
Count start flag is reset (= "0")
Interrupt request
generation timing
The timer underflows
TBiIN pin function
Read from timer
Programmable I/O port
Count value is read out by reading timer Bi register
• When counting stopped
Write to timer
When a value is written to timer Bi register, it is written to both reload register and counter
•
When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
TBiMR(i = 0 to 5) 039B16 to 039D16
01DB16 to 01DD16
00XX0000
2
0
0
00XX0000
2
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
TMOD1
Operation mode select bit 0 0 : Timer mode
Invalid in timer mode
Can be "0" or "1"
MR0
MR1
0 (Fixed to "0" in timer mode ; i = 0, 3)
(Note 1)
(Note 2)
MR2
MR3
Nothing is assiigned (i = 1, 2, 4, 5).
This bit can neither be set nor reset. When read, its content is indeterminate.
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
b7 b6
TCK0
TCK1
0 0 : f
0 1 : f
1 0 : f32
2
8
Count source select bit
1 1 : fC32
Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.
Figure 1.14.17. Timer Bi mode register in timer mode
101
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(2) Event counter mode
In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.7.)
Figure 1.14.18 shows the timer Bi mode register in event counter mode.
Table 1.14.7. Timer specifications in event counter mode
Item
Specification
Count source
• External signals input to TBiIN pin
• Effective edge of count source can be a rising edge, a falling edge, or falling
and rising edges as selected by software
• Counts down
Count operation
• When the timer underflows, it reloads the reload register contents before
continuing counting
Divide ratio
1/(n+1)
n : Set value
Count start condition
Count stop condition
Count start flag is set (= "1")
Count start flag is reset (= "0")
Interrupt request
generation timing
The timer underflows
TBiIN pin function
Read from timer
Write to timer
Count source input
Count value can be read out by reading timer Bi register
• When counting stopped
When a value is written to timer Bi register, it is written to both reload register
and counter
• When counting in progress
When a value is written to timer Bi register, it is written to only reload register
(Transferred to counter at next reload time)
Timer Bi mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 5) 039B16 to 039D16
01DB16 to 01DD16
00XX0000
00XX0000
2
0
1
2
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
TMOD1
Operation mode select bit
0 1 : Event counter mode
b3 b2
Count polarity select
bit (Note 1)
MR0
0 0 : Counts external signal’s
falling edges
0 1 : Counts external signal’s
rising edges
1 0 : Counts external signal’s
falling and rising edges
1 1 : Must not be set
MR1
MR2
0 (Fixed to "0" in event counter mode; i = 0, 3)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
This bit can neither be set nor reset. When read, its content is
indeterminate.
Invalid in event counter mode.
This bit can neither be set nor reset. When read in event
MR3
counter mode, its content is indeterminate.
Invalid in event counter mode.
Can be "0" or "1".
TCK0
TCK1
0 : Input from TBiIN pin (Note 4)
Event clock select
1 : TBj overflow
(j = i – 1; however, j = 2 when i = 0,
j = 5 when i = 3)
Note 1: Valid only when input from the TBiIN pin is selected as the event clock.
If timer’s overflow is selected, this bit can be "0" or "1".
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to "0".
Figure 1.14.18. Timer Bi mode register in event counter mode
102
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
(3) Pulse period/pulse width measurement mode
In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.8.)
Figure 1.14.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure
1.14.20 shows the operation timing when measuring a pulse period. Figure 1.14.21 shows the operation
timing when measuring a pulse width.
Table 1.14.8. Timer specifications in pulse period/pulse width measurement mode
Item
Count source
Count operation
Specification
f
2
, f
8, f32, fc32
• Up count
• Counter value "000016" is transferred to reload register at measurement
pulse’s effective edge and the timer continues counting
Count start condition
Count stop condition
Count start flag is set (= "1")
Count start flag is reset (= "0")
Interrupt request
generation timing
•
•
When measurement pulse’s effective edge is input (Note 1)
When an overflow occurs. (Simultaneously, the timer Bi overflow flag
changes to "1". The timer Bi overflow flag changes to "0" when the count
start flag is "1" and a value is written to the timer Bi mode register.)
TBiIN pin function
Read from timer
Measurement pulse input
When timer Bi register is read, it indicates the reload register’s content
(measurement result) (Note 2)
Write to timer
Cannot be written to
Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.
Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.
Timer Bi mode register
Symbol
Address
When reset
b7 b6 b5 b4 b3 b2 b1 b0
TBiMR(i = 0 to 5) 039B16 to 039D16
01DB16 to 01DD16
00XX0000
2
1
0
00XX0000
2
R
W
Bit symbol
Function
Bit name
b1 b0
TMOD0
TMOD1
Operation mode select bit
1 0 : Pulse period / pulse width
measurement mode
0 0 : Pulse period measurement
(Interval between measure-
ment pulse’s falling edge to
falling edge)
0 1 : Pulse period measurement
(Interval between measure-
ment pulse’s rising edge to
rising edge)
1 0 : Pulse width measurement
(Interval between measure-
ment pulse’s falling edge to
rising edge, and between
rising edge to falling edge)
Measurement mode
select bit
MR0
MR1
1 1 : Must not be set
0 (Fixed to "0" in pulse period/pulse width measurement mode; i = 0, 3
)
(Note 2)
(Note 3)
Nothing is assigned (i = 1, 2, 4, 5).
This bit can neither be set nor reset. When read, its content is
indeterminate.
MR2
MR3
Timer Bi overflow
flag ( Note 1)
0 : Timer did not overflow
1 : Timer has overflowed
b7 b6
TCK0
TCK1
Count source
select bit
0 0 : f
0 1 : f
1 0 : f32
2
8
1 1 : fC32
Note 1: It is indeterminate when reset.The timer Bi overflow flag changes to "0" when the
count start flag is "1" and a value is written to the timer Bi mode register. This flag
cannot be set to "1" by software.
Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Figure 1.14.19. Timer Bi mode register in pulse period/pulse width measurement mode
103
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer B
When measuring measurement pulse time interval from falling edge to falling edge
Count source
"H"
"L"
Measurement pulse
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 2)
Timing at which counter
reaches "000016
"
"1"
"0"
Count start flag
"1"
"0"
Timer Bi interrupt
request bit
Cleared to "0" when interrupt request is accepted, or cleared by software.
"1"
"0"
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.14.20. Operation timing when measuring a pulse period
Count source
"H"
Measurement pulse
"L"
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(Note 1)
(Note 1)
(Note 1) (Note 1)
(Note 2)
Timing at which counter
reaches "000016
"
"1"
"0"
Count start flag
"1"
"0"
Timer Bi interrupt
request bit
Cleared to "0" when interrupt request is accepted, or cleared by software.
"1"
"0"
Timer Bi overflow flag
Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.
Figure 1.14.21. Operation timing when measuring a pulse width
104
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Timer's Functions for Three-Phase Motor Control
Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor
driving waveforms.
Figures 1.15.1 through 1.15.3 show registers related to timers for three-phase motor control.
Three-phase PWM control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
01C816
When reset
0016
R
W
Bit symbol
INV00
Bit name
Description
Effective interrupt output 0: A timer B2 interrupt occurs when the timer
polarity select bit
A1 reload control signal is "1".
1: A timer B2 interrupt occurs when the timer
A1 reload control signal is "0".
Effective only in three-phase mode 1
Effective interrupt output 0: Not specified.
specification bit
(Note 4)
1: Selected by the effective interrupt output
polarity selection bit.
INV01
Effective only in three-phase mode 1
Mode select bit
(Note 2)
0: Normal mode
1: Three-phase PWM output mode
INV02
INV03
Output control bit
0: Output disabled
1: Output enabled
Positive and negative
phases concurrent L
output disable function
enable bit
0: Feature disabled
1: Feature enabled
INV04
0: Not detected yet
1: Already detected
Positive and negative
phases concurrent L
output detect flag
INV05
INV06
(Note 1)
Modulation mode select 0: Triangular wave modulation mode
1: Sawtooth wave modulation mode
bit (Note 3)
1: Trigger generated
The value, when read, is "0".
INV07
Software trigger bit
Note 1: No value other than "0" can be written.
Note 2: Selecting three-phase PWM output mode causes P80, P81, and P72 through P75 to output U, U, V, V, W, and W, and
works the timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for
setting timer B2 interrupt frequency.
Note 3: In triangular wave modulation mode:
The short circuit prevention timer starts in synchronization with the falling edge of timer Ai output.
The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in
synchronization with the transfer trigger signal after writing to the three-phase output buffer register.
In sawtooth wave modulation mode:
The short circuit prevention timer starts in synchronization with the falling edge of timer A output and with the transfer
trigger signal. The data transfer from the three-phase output buffer register to the three-phase output shift register
is made with respect to every transfer trigger.
Note 4:To write "1" to bit 1 (INV01) of the three-phase PWM control register 0, set in advance the contentof the timer B2
interrupt occurrences frequency set counter.
Three-phase PWM control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC1
Address
01C916
When reset
0016
0
R
W
Bit symbol
Bit name
Description
Timer Ai start trigger
signal select bit
0: Timer B2 overflow signal
1: Timer B2 overflow signal,
signal for writing to timer B2
INV10
Timer A1-1, A2-1, A4-1
control bit
0: Three-phase mode 0
1: Three-phase mode 1
INV11
INV12
Short circuit timer count
source select bit
0 : inhibited
1 : f2/2 (Note)
Noting is assigned.
These bits can be set nor reset. When read, their contents are indeterminate.
Reserved bit
Always set to "0"
Noting is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note: To use three-phase PWM output mode, write "1" to INV12.
Figure 1.15.1. Registers related to timers for three-phase motor control
105
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Three-phase output buffer register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0
Address
01CA16
When reset
0016
R
W
Bit Symbol
Bit name
Function
(Note)
DU0
DUB0
DV0
U phase output buffer 0
U phase output buffer 0
V phase output buffer 0
Setting in U phase output buffer 0
Setting in U phase output buffer 0
Setting in V phase output buffer 0
(Note)
(Note)
(Note)
(Note)
(Note)
DVB0
DW0
V phase output buffer 0
Setting in V phase output buffer 0
W phase output buffer 0 Setting in W phase output buffer 0
W phase output buffer 0 Setting in W phase output buffer 0
DWB0
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.
Three-phase output buffer register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB1
Address
01CB16
When reset
0016
R
W
Bit Symbol
DU1
Bit name
Function
U phase output buffer 1
U phase output buffer 1
V phase output buffer 1
V phase output buffer 1
Setting in U phase output buffer 1
Setting in U phase output buffer 1
Setting in V phase output buffer 1
Setting in V phase output buffer 1
(Note)
(Note)
(Note)
DUB1
DV1
DVB1
DW1
(Note)
(Note)
(Note)
W phase output buffer 1 Setting in W phase output buffer 1
W phase output buffer 1 Setting in W phase output buffer 1
DWB1
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.
Dead time timer (Note)
b7
b0
Symbol
DTT
Address
01CC16
When reset
Indeterminate
R
W
Function
Values that can be set
1 to 255
Set dead time timer
Note: Use MOV instruction to write to this register.
Timer B2 interrupt occurrences frequency set counter (Note 1, 2, 3)
b7
b0
Symbol
ICTB2
Address
01CD16
When reset
Indeterminate
R
W
Function
Values that can be set
1 to 15
Set occurrence frequency of timer B2
interrupt request
Note 1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of three-
phase PWM control register 0, do not change the B2 interrupt occurrences frequency
set counter to deal with the timer function for three-phase motor control.
Note 2: Do not write at the timing of an overflow occurrence in timer B2.
Note 3: Use MOV instruction to write to this register.
Figure 1.15.2. Registers related to timers for three-phase motor control
106
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Timer Ai register (Note 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA1
TA2
TA4
TB2
Address
When reset
038916,038816
038B16,038A16
038F16,038E16
039516,039416
Indeterminate
Indeterminate
Indeterminate
Indeterminate
R W
Function
Values that can be set
000016 to FFFF16
• Timer mode
Counts an internal count source
• One-shot timer mode
Counts a one shot width
000016 to FFFF16
(Note 2, 3)
Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "000016", the counter does not
operate and a timer Ai register interrupt does not occur.
Note 3: Use MOV instruction to write to this segister.
Timer Ai-1 register (Note)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TA11
TA21
TA41
Address
When reset
Indeterminate
Indeterminate
Indeterminate
01C316,01C216
01C516,01C416
01C716,01C616
R W
Values that can be set
000016 to FFFF16
Function
Counts an internal count source
Note: Read and write data in 16-bit units.
Trigger select register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
038316
When reset
0016
Bit symbol
TA1TGL
Bit name
Function
R W
b1 b0
Timer A1 event/trigger
select bit
0 0 : Input on TA1IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected
TA1TGH
TA2TGL
b3 b2
Timer A2 event/trigger
select bit
0 0 : Input on TA2IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected
TA2TGH
TA3TGL
TA3TGH
b5 b4
Timer A3 event/trigger
select bit
0 0 : Input on TA3IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected
b7 b6
Timer A4 event/trigger
select bit
TA4TGL
TA4TGH
0 0 : Input on TA4IN is selected (Note)
0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected
Note: Set the corresponding port direction register to "0".
Count start flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
038016
When reset
0016
Bit symbol
TA0S
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Bit name
Function
R W
Timer A0 count start flag
Timer A1 count start flag
Timer A2 count start flag
Timer A3 count start flag
Timer A4 count start flag
Timer B0 count start flag
Timer B1 count start flag
Timer B2 count start flag
0 : Stops counting
1 : Starts counting
Figure 1.15.3. Registers related to timers for three-phase motor control
107
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Three-Phase Motor Driving Waveform Output Mode (three-phase PWM output mode)
Setting "1" in the mode select bit (bit 2 at address 01C816) shown in Figure 1.15.1 - causes three-phase
PWM output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.15.4, set
timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode
using the respective timer mode registers.
Timer Ai mode register
Symbol
TA1MR
TA2MR
TA4MR
Address
039716
039816
039A16
When reset
0016
b7 b6 b5 b4 b3 b2 b1 b0
0
1
0 1 0
0016
0016
Function
Bit symbol
Bit name
R W
b1 b0
TMOD0
TMOD1
MR0
Operation mode
select bit
1 0 : One-shot timer mode
0 : (Must always be "0" in three-phase PWM
output mode)
Pulse output function
select bit
MR1
MR2
External trigger select
bit
Invalid in three-phase PWM output mode
1 : Selected by event/trigger select
register
Trigger select bit
MR3
0 (Must always be "0" in one-shot timer mode)
b7 b6
TCK0
Count source select bit
0 0 : f
0 1 : f
2
8
TCK1
1 0 : f32
1 1 : fC32
Timer B2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2MR
Address
039D16
When reset
00XX0000
2
0
0 0
Bit symbol
R W
Function
Bit name
b1 b0
TMOD0
Operation mode select bit
0 0 : Timer mode
TMOD1
MR0
Invalid in timer mode
Can be "0" or "1"
MR1
0 (Fixed to "0" in timer mode)
Invalid in timer mode.
This bit can neither be set nor reset. When read in timer mode,
its content is indeterminate.
MR2
MR3
b7 b6
Count source select bit
TCK0
TCK1
0 0 : f
0 1 : f
2
8
1 0 : f32
1 1 : fC32
Figure 1.15.4. Timer mode registers in three-phase waveform mode
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Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Figure 1.15.5 shows the block diagram for three-phase PWM output mode. In three-phase PWM output
__
mode, the positive-phase PWM output (U phase, V phase, and W phase) and negative waveforms (U
__
___
phase, V phase, and W phase), six waveforms in total, are output from P80, P81, P72, P73, P74, and P75
__
as active on the "L" level. Of the timers used in this mode, timer A4 controls the U phase and U phase,
__
___
timer A1 controls the V phase and V phase, and timer A2 controls the W phase and W phase respectively;
timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2.
In outputting a waveform, dead time can be set so as to cause the "L" level of the positive waveform
__
output (U phase, V phase, and W phase) not to lap over the "L" level of the negative waveform output (U
__
___
phase, V phase, and W phase).
To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value
from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead
time works as a one-shot timer. If a value is written to the dead timer (address 01CC16), the value is
written to the reload register shared by the three timers for setting dead time.
Any of the timers for setting dead time takes the value of the reload register into its counter, if a start
trigger comes from its corresponding timer, and performs a down count in line with the clock source
selected by the dead time timer count source select bit (bit 2 at address 01C916). The timer can receive
another trigger again before the workings due to the previous trigger are completed. In this instance, the
timer performs a down count from the reload register's content after its transfer, provoked by the trigger,
to the timer for setting dead time.
Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger
comes; it stops outputting pulses as soon as its content becomes 0016, and waits for the next trigger to
come.
__
__
The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V
___
phase, and W phase) in three-phase PWM output mode are output from respective ports by means of
setting "1" in the output control bit (bit 3 at address 01C816). Setting "0" in this bit causes the ports to be
the state of set by port direction register. This bit can be set to "0" not only by use of the applicable
______
instruction, but by entering a falling edge in the NMI terminal or by resetting. Also, if "1" is set in the
positive and negative phases concurrent "L" output disable function enable bit (bit4 at address 01C816)
__
__
___
causes one of the pairs of U phase and U phase, V phase and V phase, and W phase and W phase
concurrently go to "L", as a result, the output control bit become the state of set by port direction register.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Figure 1.15.5. Block diagram for three-phase waveform mode
110
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Triangular Wave Modulation
To generate a PWM waveform of triangular wave modulation, set "0" in the modulation mode select bit (bit
6 at address 01C816). Also, set "1" in the timers A4-1, A1-1, A2-1 control bit (bit 1 at address 01C916). In
this mode, each of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register's
content to the counter every time timer B2 counter's content becomes 000016. If "0" is set to the effective
interrupt output specification bit (bit 1 at address 01C816), the frequency of interrupt requests that occur
every time the timer B2 counter's value becomes 000016 can be set by use of the timer B2 counter (address
01CD16) for setting the frequency of interrupt occurrences. The frequency of occurrences is given by a set
value (≠ 0).
Setting "1" in the effective interrupt output specification bit (bit 1 at address 01C816) provides the means to
choose which value of the timer A1 reload control signal to use, "0" or "1", to cause timer B2's interrupt
request to occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at
address 01C816).
An example of U phase waveform is shown in Figure 1.15.6, and the description of waveform output work-
ings is given below. Set "1" in DU0 bit (bit 0 at address 01CA16). And set "0" in DUB0 bit (bit 1 at address
01CA16). In addition, set "0" in DU1 bit (bit 0 at address 01CB16) and set "1" in DUB1 bit (bit 1 at address
01CB16). Also, set "0" in the effective interrupt output specification bit (bit 1 at address 01C816) to set a
value in the timer B2 interrupt occurence frequency set counter. By this setting, a timer B2 interrupt occurs
when the timer B2 counter's content becomes 000016 as many as (setting) times. Furthermore, set "1" in
the effective interrupt output specification bit (bit 1 at address 01C816), set "0" in the effective interrupt
output polarity select bit (bit 0 at address 01C816) and set "1" in the interrupt occurence frequency set
counter (address 01CD16). These settings cause a timer B2 interrupt to occur every other interval when the
U phase output goes to "H".
When the timer B2 counter's content becomes 000016, timer A4 starts outputting one-shot pulses. In this
instance, the content of DU1 bit (bit 0 at address 01CB16) and that of DU0 bit (bit 0 at address 01CA16) are
set in the three-phase output shift register (U phase), the content of DUB1 bit (bit 1 at address 01CB16) and
__
that of DUB0 bit (bit 1 at address 01CA16) are set in the three-phase output shift register (U phase). After
triangular wave modulation mode is selected, however, no setting is made in the shift register even though
the timer B2 counter's content becomes 000016.
__
The value of DU0 bit and that of DUB0 bit are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (addresses 038F16 and
038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is
shifted one position, and the value of DU1 bit and that of DUB1 bit are output to the U phase output signal
__
and to U phase output signal respectively. At the this time, one-shot pulses are output from the timer for
setting dead time used for setting the time over which the "L" level of the U phase waveform doesn't lap over
__
the "L" level of the U phase waveform, which has the opposite phase of the former. The U phase waveform
output that started from the "H" level keeps its level until the timer for setting dead time finishes outputting
one-shot pulses even though the three-phase output shift register's content changes from "1" to "0" by the
effect of the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0"
already shifted in the three-phase shift register goes effective, and the U phase waveform changes to the
"L" level. When the timer B2 counter's content becomes 000016, the timer A4 counter starts counting the
value written to timer A4-1 (addresses 01C116 and 01C016), and starts outputting one-shot pulses. When
timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one position,
but if the three-phase output shift register's content changes from "0" to "1" as a result of the shift, the output
level changes from "L" to "H" without waiting for the timer for setting dead time to finish outputting one-shot
111
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the three-
__
__
phase output shift register on the U phase side is used, the workings in generating a U phase waveform,
which has the opposite phase of the U phase waveform, are the same as in generating a U phase wave-
form. In this way, a waveform can be picked up from the applicable terminal in a manner in which the "L"
__
level of the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite
phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the values of
__
___
timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases, the latter are
__
of opposite phase of the former, have the corresponding timers work similarly to dealing with the U and U
phases to generate an intended waveform.
A carrier wave of triangular waveform
Carrier wave
Signal wave
Timer B2
Timber B2 interrupt occurres
Rewriting timer A4 and timer A4-1.
Possible to set the number of overflows to generate an
interrupt by use of the interrupt occurrences frequency
set circuit
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
m
m
m
p
n
n
o
Timer A4 output
The three-phase
shift register
shifts in
synchronization
with the falling
edge of timer A4.
Control signal for
timer A4 reload
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to triangular wave modulation mode and to three-phase mode 1
Figure 1.15.6. Timing chart of operation (1)
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Assigning certain values to DU0 bit (bit 0 at address 01CA16) and DUB0 bit (bit 1 at address 01CA16), and
to DU1 bit (bit 0 at address 01CB16) and DUB1 bit (bit 1 at address 01CB16) allows the user to output the
__
waveforms as shown in the Figure 1.15.7, that is, to output the U phase alone, to fix U phase to "H", to fix
__
the U phase to "H", or to output the U phase alone.
A carrier wave of triangular waveform
Carrier wave
Signal wave
Timer B2
Rewriting timer A4 every timer B2 interrupt occurres.
Timer B2 interrupt occurres.
Rewriting three-phase buffer register.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
m
m
m
p
n
n
o
The three-phase
shift register shifts
in synchronization
with the falling edge
of timer A4.
Timer A4 output
Control signal for
timer A4 reload
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to triangular wave modulation mode and to three-phase mode 0.
Figure 1.15.7. Timing chart of operation (2)
113
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
Sawtooth Modulation
To generate a PWM waveform of sawtooth wave modulation, set "1" in the modulation mode select bit
(bit 6 at address 01C816). Also, set "0" in the timers A1-1, A2-1, A4-1 control bit (bit 1 at address
01C916). In this mode, the timer registers of timers A4, A1, and of A2 comprise conventional timers A4,
A1, and A2 alone, and reload the corresponding timer register's content to the counter every time the
timer B2 counter's content becomes 000016. The effective interrupt output specification bit (bit 1 at
address 01C816) and the effective interrupt output polarity selection bit (bit 0 at address 01C816) turn
nullified.
An example of U phase waveform is shown in Figure 1.15.8, and the description of waveform output
workings is given below. Set "1" in DU0 bit (bit 0 at address 01CA16) and set "0" in DUB0 bit (bit 1 at
address 01CA16). In addition, set "0" in DU1 bit (bit 0 at address 01CA16) and set "1" in DUB1 bit (bit 1
at address 01CA16).
When the timer B2 counter's content becomes 000016, timer B2 generates an interrupt, and timer A4
starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase
buffer registers DU1 bit and DU0 bit are set in the three-phase output shift register (U phase), and the
contents of DUB1 bit and DUB0 bit are set in the three-phase output register (U phase). After this, the
three-phase buffer register's content is set in the three-phase shift register every time the timer B2
counter's content becomes 000016.
__
The value of DU0 bit and that of DUB0 bit are output to the U terminal (P80) and to the U terminal (P81)
respectively. When the timer A4 counter counts the value written to timer A4 (addresses 038F16 and
038E16) and when timer A4 finishes outputting one-shot pulses, the three-phase output shift register's
content is shifted one position, and the value of DU1 bit and that of DUB1 bit are output to the U phase
__
output signal and to the U output signal respectively. At the this time, one-shot pulses are output from
the timer for setting dead time used for setting the time over which the "L" level of the U phase waveform
__
doesn't lap over the "L" level of the U phase waveform, which has the opposite phase of the former. The
U phase waveform output that started from the "H" level keeps its level until the timer for setting dead
time finishes outputting one-shot pulses even though the three-phase output shift register's content
changes from "1" to "0" by the effect of the one-shot pulses. When the timer for setting dead time
finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and
the U phase waveform changes to the "L" level. When the timer B2 counter's content becomes 000016,
the contents of the three-phase buffer registers DU1 bit and DU0 bit are set in the three-phase shift
__
register (U phase), and the contents of DUB1 bit and DUB0 bit are set in the three-phase shift register (U
phase) again.
A U phase waveform is generated by these workings repeatedly. With the exception that the three-
__
__
phase output shift register on the U phase side is used, the workings in generating a U phase waveform,
which has the opposite phase of the U phase waveform, are the same as in generating a U phase
waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in which
__
the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the
opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the
__
___
values of timer B2 and timer A4. In dealing with the V and W phases, and V and W phases, the latter are
of opposite phase of the former, have the corresponding timers work similarly to dealing with the U and
__
U phases to generate an intended waveform.
Setting "1" both in DUB0 bit and DUB1 bit provides a means to output the U phase alone and to fix the
__
U phase output to "H" as shown in Figure 1.15.9.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
A carrier wave of sawtooth waveform
Carrier wave
Signal wave
Timer B2
Data transfer is made from the three-
phase buffer register to the three-
phase shift register in step with the
timing of the timer B overflow.
Interrupt occurres.
Rewriting the value of timer A4.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
The three-phase
shift register
n
p
Timer A4 output
m
o
shifts in
synchronization
with the falling
edge of timer A4.
U phase output
signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Figure 1.15.8. Timing chart of operation (3)
115
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer's Functions for Three-Phase Motor Control
A carrier wave of sawtooth waveform
Carrier wave
Signal wave
Timer B2
Interrupt occurres.
Rewriting the value of timer A4.
Interrupt occurres.
Rewriting the value of timer A4.
Data transfer is made from the three-
phase buffer register to the three-
phase shift register in step with the
timing of the timer B overflow.
Trigger signal for
timer Ai start
(timer B2 overflow
signal)
Rewriting three-phase
output buffer register
The three-phase
shift register shifts
in synchronization
Timer A4 output
m
n
o
p
with the falling
edge of timer A4.
U phase
output signal
U phase
output signal
U phase
U phase
Dead time
Note: Set to sawtooth modulation mode and to three-phase mode 0.
Figure 1.15.9. Timing chart of operation (4)
116
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Serial I/O
Serial I/O is configured as four channels: UART0, UART1, UART2 and S I/O3.
UART0 to 2
UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate
independently of each other.
Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show
the block diagram of the transmit/receive unit.
UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous
serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses
03A016, 03A816 and 01F816) determine whether UARTi is used as a clock synchronous serial I/O or as a
UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same func-
tions.
UART2, in particular, is used for the SIM (Subscriber Identity Module) interface with some extra settings
added in clock-asynchronous serial I/O mode (Note). It also has the bus collision detection function that
generates an interrupt request if the TxD pin and the RxD pin are different in level.
Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 through
1.16.8 show the registers related to UARTi.
Table 1.16.1. Comparison of functions of UART0 through UART2
Function
UART0
UART1
UART2
Possible
CLK polarity selection
Possible
Possible
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
(Note 1) Possible (Note 1)
Possible (Note 1)
(Note 1)
(Note 2)
(Note 1)
LSB first / MSB first selection
Possible
Continuous receive mode selection
Possible
Possible
Transfer clock output from multiple
pins selection
Impossible
Possible
Impossible
Impossible
Possible
Separate CTS/RTS pins
Serial data logic switch
Sleep mode selection
Impossible
Impossible
Possible
Impossible
(Note 4)
(Note 3) Possible (Note 3)
Impossible
Impossible
Possible
TxD, RxD I/O polarity switch
TxD port output format
Impossible
N-channel open-drain N-channel open-drain N-channel open-drain
/CMOS output (Note 5) /CMOS output (Note 5) /CMOS output (Note 5)
Parity error signal output
Bus collision detection
Impossible
Impossible
Impossible
Impossible
Possible
Possible
(Note 4)
(Note 6)
Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.
Note 5: When selecting N-channel open-drain output, connect via pull-up resister to VCC outside.
Note 6: Generally, it use in case of IE bus-emulation.
117
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
PCLK
1
1
= "1"
= "0"
f
2SIO2
1/2
XIN
PCLK
1/4
f
f
8SIO2
32SIO2
1/4
(UART0)
RxD0
TxD0
UART reception
Receive
clock
1/16
Reception
Transmit/
receive
unit
Clock source selection
control circuit
Clock synchronous type
Bit rate generator
f
f
f
2SIO2
Internal
8SIO2
(address 03A116
)
Transmit
clock
UART transmission
32SIO2
1/(n0 +1)
1/16
Transmission
control circuit
Clock synchronous type
External
Clock synchronous type
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK
0
CTS/RTS disabled
CTS/RTS selected
RTS
0
CTS0/RTS0
Vcc
CTS/RTS disabled
CTS/RTS separated
CTS
0
CTS0 from UART1
(UART1)
RxD1
TxD1
UART reception
Receive
clock
1/16
Transmit/
receive
unit
Reception
control circuit
Clock source selection
Bit rate generator
(address 03A916
Clock synchronous type
f
f
2SIO2
)
Internal
8SIO2
UART transmission
1/16
Transmit
clock
1 +1)
1/(n
f
32SIO2
Transmission
control circuit
Clock synchronous type
Clock synchronous type
(when internal clock is selected)
1/2
External
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK1
CTS/RTS disabled
CTS/RTS separated
RTS
1
CTS
/CTS
1
0
/ RTS
/ CLKS
1
V
CC
1
Clock output pin
select switch
CTS/RTS disabled
CTS
1
CTS
0
CTS0 to UART0
(UART2)
TxD
RxD polarity
reversing circuit
polarity
reversing
circuit
RxD
2
TxD2
UART reception
Receive
clock
1/16
Reception
control circuit
Transmit/
receive
unit
Clock source selection
Clock synchronous type
Bit rate generator
(address 01F916
f
f
f
2SIO2
Internal
)
8SIO2
UART transmission
1/16
Transmit
clock
+1)
1/(n2
32SIO2
Transmission
control circuit
Clock synchronous type
Clock synchronous type
External
(when internal clock is selected)
1/2
Clock synchronous type
(when internal clock is selected)
Clock synchronous type
(when external clock is
selected)
CLK
polarity
reversing
circuit
CLK2
CTS/RTS
selected
CTS/RTS disabled
RTS
2
CTS2 /RTS2
Vcc
CTS/RTS disabled
CTS
2
n0 : Values set to UART0 bit rate generator (BRG0)
n1 : Values set to UART1 bit rate generator (BRG1)
n2 : Values set to UART2 bit rate generator (BRG2)
Figure 1.16.1. Block diagram of UARTi (i = 0 to 2)
118
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
Clock
synchronous type
UART (7 bits)
UART (8 bits)
Clock
UARTi receive register
synchronous
type
UART (7 bits)
PAR
disabled
1SP
2SP
SP
SP
PAR
RxDi
PAR
enabled
UART
UART (9 bits)
Clock
synchronous type
UART (8 bits)
UART (9 bits)
UARTi receive
buffer register
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address 03A616
Address 03A716
Address 03AE16
Address 03AF16
MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
MSB/LSB conversion circuit
UARTitransmit
buffer register
D7
D6
D5
D4
D3
D2
D1
D0
D8
Address 03A216
Address 03A316
Address 03AA16
Address 03AB16
UART (8 bits)
UART (9 bits)
Clock synchronous
type
UART (9 bits)
PAR
enabled
UART
2SP
1SP
SP
SP
PAR
TxDi
Clock
synchronous
type
PAR
disabled
UART (7 bits)
UARTi transmit register
UART (7 bits)
UART (8 bits)
SP: Stop bit
PAR: Parity bit
"0"
Clock synchronous
type
Figure 1.16.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit
119
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
No reverse
Reverse
RxD data
reverse circuit
RXD2
Clock
synchronous type
UART
(7 bits)
UART
(8 bits)
Clock
synchronous
ype
UART2 receive register
PAR
disabled
UART(7 bits)
1SP
SP
PAR
SP
2SP
Clock
synchronous type
PAR
enabled
UART
UART
(9 bits)
UART
(8 bits)
UART
(9 bits)
UART2 receive
buffer register
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address 01FE16
Address 01FF16
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UART2transmit
buffer register
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address 01FA16
Address 01FB16
UART
(8 bits)
UART
(9 bits)
UART
(9 bits)
Clock
synchronous type
PAR
enabled
UART
2SP
SP
SP
PAR
1SP
Clock
synchronous
type
PAR
disabled
UART
(7 bits)
UART
(8 bits)
UART(7 bits)
UART2 transmit register
"0"
Clock
synchronous type
Error signal output
disable
No reverse
TxD data
reverse circuit
Error signal
output circuit
TXD2
Reverse
Error signal output
enable
SP: Stop bit
PAR: Parity bit
Figure 1.16.3. Block diagram of UART2 transmit/receive unit
120
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit buffer register (Note)
Symbol
U0TB
U1TB
U2TB
Address
When reset
(b15)
b7
(b8)
03A316, 03A216
03AB16, 03AA16
01FB16, 01FA16
Indeterminate
Indeterminate
Indeterminate
b0 b7
b0
Function
R W
Transmit data
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are indeterminate.
Note: Use MOV instruction to write to this register.
UARTi receive buffer register
(b8)
b0 b7
(b15)
b7
Symbol
U0RB
U1RB
U2RB
Address
When reset
Indeterminate
Indeterminate
Indeterminate
b0
03A716, 03A616
03AF16, 03AE16
01FF16, 01FE16
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
Receive data
Receive data
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
Arbitration lost detecting
flag (Note 2)
0 : Not detected
1 : Detected
Invalid
ABT
Overrun error flag (Note 1)
0 : No overrun error
1 : Overrun error found
0 : No overrun error
1 : Overrun error found
OER
FER
PER
SUM
Framing error flag (Note 1) Invalid
0 : No framing error
1 : Framing error found
Parity error flag (Note 1)
Error sum flag (Note 1)
Invalid
Invalid
0 : No parity error
1 : Parity error found
0 : No error
1 : Error found
Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A016
,
03A816 and 01F816) are set to "000 " or the receive enable bit is set to "0".
2
(Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the
lower byte of the UARTi receive buffer register (addresses 03A616, 03AE16 and 01FE16) is read out.
Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is
assigned in bit 11 of U0RB and U1RB. These bits can neither be set or reset. When read, the value
of this bit is "0".
UARTi bit rate generator (Note 1, 2)
Symbol
U0BRG
U1BRG
U2BRG
Address
03A116
03A916
01F916
When reset
Indeterminate
Indeterminate
Indeterminate
b7
b0
R
W
Function
Values that can be set
0016 to FF16
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.
Figure 1.16.4. Serial I/O-related registers (1)
121
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
Must be fixed to 001
b2 b1 b0
SMD0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD1
SMD2
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note)
0 : Internal clock
1 : External clock (Note)
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = "1"
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
SLEP
Parity enable bit
Sleep select bit
Invalid
0 : Sleep mode deselected
1 : Sleep mode selected
Must always be "0"
Note: Set the corresponding port direction register to "0".
UART2 transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
01F816
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
b2 b1 b0
SMD0
Must be fixed to 001
b2 b1 b0
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 0 0 : Serial I/O invalid
0 1 0 : (Note 1)
0 1 1 : Inhibited
SMD1
SMD2
1 1 1 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
CKDIR
STPS
PRY
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 2)
Must always be fixed to "0"
0 : One stop bit
1 : Two stop bits
Stop bit length select bit
Invalid
Valid when bit 6 = "1"
0 : Odd parity
Odd/even parity select bit Invalid
1 : Even parity
0 : Parity disabled
1 : Parity enabled
PRYE
Parity enable bit
Invalid
TxD, RxD I/O polarity
reverse bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
IOPOL
Usually set to "0"
Usually set to "0"
2
Note 1: Bit 2 to bit 0 are set to "010
2
" when I C mode is used.
Note 2: Set the corresponding port direction register to "0".
Figure 1.16.5. Serial I/O-related registers (2)
122
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC0(i=0,1)
Address
03A416, 03AC16
When reset
0816
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
R W
Bit name
(During UART mode)
b1 b0
b1 b0
CLK0 BRG count source
select bit
0 0 : f2SIO2 is selected
0 1 : f8SIO2 is selected
1 0 : f32SIO2 is selected
1 1 : Inhibited
0 0 : f2SIO2 is selected
0 1 : f8SIO2 is selected
1 0 : f32SIO2 is selected
1 1 : Inhibited
CLK1
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P60 and P64 function as
CRD
NCH
CTS/RTS disable bit
Data output select bit
programmable I/O port)
programmable I/O port)
0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel
open-drain output
0: TXDi pin is CMOS output
1: TXDi pin is N-channel
open-drain output
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be "0"
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
UFORM Transfer format select bit
Must always be "0"
Note 1: Set the corresponding port direction register to "0".
Note 2: The settings of the corresponding port register and port direction register are invalid.
UART2 transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C0
Address
01FC16
When reset
0816
Function
Function
(During UART mode)
Bit
symbol
(During clock synchronous
R W
Bit name
serial I/O mode)
b1 b0
b1 b0
CLK0
CLK1
BRG count source
select bit
0 0 : f2SIO2 is selected
0 1 : f8SIO2 is selected
1 0 : f32SIO2 is selected
1 1 : Inhibited
0 0 : f2SIO2 is selected
0 1 : f8SIO2 is selected
1 0 : f32SIO2 is selected
1 1 : Inhibited
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)
CRS
CTS/RTS function
select bit
0 : Data present in transmit
register (during transmission)
1 : No data present in transmit
register (transmission
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit
register (transmission completed)
TXEPT Transmit register empty
flag
completed)
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
CRD
NCH
CTS/RTS disable bit
Data output select bit
(P73
functions
(P73 functions programmable
programmable I/O port)
I/O port)
0 : TXD pin is CMOS output
2
0 : TXD
2
pin is CMOS output
1 : TXD2 pin is N-channel
open-drain output
1 : TXD2 pin is N-channel open-drain
output
(Note 4)
0 : Transmit data is output at
falling edge of transfer clock
and receive data is input at
rising edge
Must always be "0"
CKPOL CLK polarity select bit
1 : Transmit data is output at
rising edge of transfer clock
and receive data is input at
falling edge
0 : LSB first
1 : MSB first
0 : LSB first
1 : MSB first
Transfer format select bit
(Note 3)
UFORM
Note 1: Set the corresponding port direction register to "0".
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.
Figure 1.16.6. Serial I/O-related registers (3)
123
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UARTi transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiC1(i=0,1)
Address
03A516 03AD16
When reset
0216
,
Function
(During clock synchronous
serial I/O mode)
Bit
Function
(During UART mode)
Bit name
symbol
R W
TE
TI
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
Nothing is assigned.
These bits can neither be set nor reset. When read, the value of these bits is "0".
UART2 transmit/receive control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
01FD16
When reset
0216
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
TE
TI
Transmit enable bit
0 : Transmission disabled
1 : Transmission enabled
0 : Transmission disabled
1 : Transmission enabled
Transmit buffer
empty flag
0 : Data present in
0 : Data present in
transmit buffer register
1 : No data present in
transmit buffer register
transmit buffer register
1 : No data present in
transmit buffer register
RE
RI
Receive enable bit
0 : Reception disabled
1 : Reception enabled
0 : Reception disabled
1 : Reception enabled
Receive complete flag
0 : No data present in
receive buffer register
1 : Data present in
0 : No data present in
receive buffer register
1 : Data present in
receive buffer register
receive buffer register
U2IRS UART2 transmit interrupt 0 : Transmit buffer empty
0 : Transmit buffer empty
(TI = 1)
cause select bit
(TI = 1)
1 : Transmit is completed
(TXEPT = 1)
1 : Transmit is completed
(TXEPT = 1)
U2RRM UART2 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Must always be "0"
U2LCH Data logic select bit
0 : No reverse
1 : Reverse
0 : No reverse
1 : Reverse
U2ERE Error signal output
enable bit
Must be fixed to "0"
0 : Output disabled
1 : Output enabled
Figure 1.16.7. Serial I/O-related registers (4)
124
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Serial I/O
UART transmit/receive control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B016
When reset
X0000000
2
Function
(During clock synchronous
serial I/O mode)
Bit
name
Bit
symbol
Function
(During UART mode)
R W
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U0IRS UART0 transmit
interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed
(TXEPT = 1)
U1IRS UART1 transmit
interrupt cause select bit
U0RRM UART0 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enable
Must always be "0"
U1RRM UART1 continuous
receive mode enable bit
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
Must always be "0"
CLKMD0 CLK/CLKS select bit 0
Valid when bit 5 = "1"
0 : Clock output to CLK1
1 : Clock output to CLKS1
Invalid
CLKMD1 CLK/CLKS select
bit 1 (Note)
0 : Normal mode
Must always be "0"
(CLK output is CLK1 only)
1 : Transfer clock output
from multiple pins
function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate CTS/RTS bit
RCSP
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: When using multiple pins to output the transfer clock, the following requirements must be met:
• UART1 internal/external clock select bit (bit 3 at address 03A816) = "0".
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
01F716
When reset
0016
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Bit
name
Function
(During UART mode)
R W
IIC mode selection bit
0 : Normal mode
1 : IIC mode
Must always be "0"
Must always be "0"
IICM
ABC
Arbitration lost detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
BBS
Bus busy flag
Must always be "0"
Must always be "0"
(Note)
LSYN SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling
clock select bit
Must always be "0"
0 : Rising edge of transfer
clock
1 : Underflow signal of timer A0
ABSCS
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
ACSE
Auto clear function
select bit of transmit
enable bit
Must always be "0"
Must always be "0"
0 : Ordinary
1 : Falling edge of RXD2
Transmit start condition
select bit
SSS
Nothing is assigned.
This bit can neither be set nor reset. When read, its content is indeterminate.
Note: Nothing but "0" may be written.
Figure 1.16.8. Serial I/O-related registers (5)
125
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2
and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.9 shows the
UARTi transmit/receive mode register.
Table 1.16.2. Specifications of clock synchronous serial I/O mode (1)
Item
Specification
Transfer data format
Transfer clock
• Transfer data length: 8 bits
• When internal clock is selected (bit 3 at addresses 03A016, 03A816, 01F816
= "0") : fjSIO2/ 2(n+1)(Note 1) j = 2, 8, 32
• When external clock is selected (bit 3 at addresses 03A016, 03A816, 01F816
= "1") : Input from CLKi pin
Transmission/reception
control
•
CTS function/RTS function/CTS, RTS function chosen to be invalid
Transmission start
condition
• To start transmission, the following requirements must be met:
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = "1"
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = "0"
_ When CTS function selected, CTS input level = "L"
•
Furthermore, if external clock is selected, the following requirements must also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = "0":
CLKi input level = "H"
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = "1":
CLKi input level = "L"
Reception start condition • To start reception, the following requirements must be met:
_ Receive enable bit (bit 2 at addresses 03A516, 03AD16, 01FD16) = "1"
_ Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = "1"
_ Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = "0"
• Furthermore, if external clock is selected, the following requirements must
also be met:
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = "0":
CLKi input level = "H"
_ CLKi polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16) = "1":
CLKi input level = "L"
• When transmitting
Interrupt request
generation timing
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 01FD16) = "0": Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
_ Transmit interrupt cause select bit (bits 0, 1 at address 03B016, bit 4 at
address 01FD16) = "1": Interrupts requested when data transmission from
UARTi transfer register is completed
• When receiving
_ Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 2)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
Note 1: "n" denotes the value 0016 to FF16 that is set to the UART bit rate generator.
Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to "1".
126
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
Table 1.16.3. Specifications of clock synchronous serial I/O mode (2)
Item
Specification
Select function
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling edge
of the transfer clock can be selected
• LSB first/MSB first selection
Whether transmission/reception begins with bit 0 or bit 7 can be selected
• Continuous receive mode selection
Reception is enabled simultaneously by a read from the receive buffer register
• Transfer clock output from multiple pins selection (UART1) (Note)
UART1 transfer clock can be chosen by software to be output from one of
the two pins set
• Separate CTS/RTS pins (UART0) (Note)
UART0 CTS and RTS pins each can be assigned to separate pins
• Switching serial data logic (UART2)
Whether to reverse data in writing to the transmission buffer register or
reading the reception buffer register can be selected
• TxD, RxD I/O polarity reverse (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed
______ ______
Note: The transfer clock output from multiple pins and the separate CTS/RTS pins functions cannot be
selected simultaneously.
127
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
UARTi transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
SLEP
0 (Must always be "0" in clock synchronous serial I/O mode)
Note: Set the corresponding port direction register to "0".
UART2 transmit/receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
01F816
When reset
0016
0
0 0 1
Bit symbol
Bit name
Function
R W
b2 b1 b0
SMD0
SMD1
SMD2
CKDIR
Serial I/O mode select bit
0 0 1 : Clock synchronous serial
I/O mode
Internal/external clock
select bit
0 : Internal clock
1 : External clock (Note 2)
STPS
PRY
Invalid in clock synchronous serial I/O mode
PRYE
IOPOL
TxD, RxD I/O polarity
reverse bit (Note 1)
0 : No reverse
1 : Reverse
Note 1: Usually set to "0".
Note 2: Set the corresponding port direction register to "0".
Figure 1.16.9. UARTi transmit/receive mode register in clock synchronous serial I/O mode
128
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
Table 1.16.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This
______
table shows the pin functions when the transfer clock output from multiple pins and the separate CTS/
______
RTS pins functions are not selected. Note that for a period from when the UARTi operation mode is
selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel open-drain is selected, this
pin is in floating state.)
Table 1.16.4. Input/output pin functions in clock synchronous serial I/O mode
_______ _______
(when transfer clock output from multiple pins and separate CTS/RTS pins functions are not selected)
Pin name
TxDi
(P6 , P6
RxDi
(P6 , P6
Function
Method of selection
Serial data output
(Outputs dummy data when performing reception only)
3
7, P70)
Serial data input
Port P62, P66 and P71 direction register (bits 2 and 6 at address 03EE16,
2
6, P7
1
)
)
bit 1 at address 03EF16)= "0"
(Can be used as an input port when performing transmission only)
CLKi
(P6 , P6
Transfer clock output
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = "0"
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = "1"
1
5, P7
2
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = "0"
CTSi/RTSi
(P6 , P6 , P73)
CTS input
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = "0"
0
4
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = "0"
Port P6 , P6 and P7 direction register (bits 0 and 4 at address 03EE16
0
4
3
,
bit 3 at address 03EF16) = "0"
RTS output
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = "0"
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = "1"
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = "1"
129
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1"
Transmit enable
"0"
"1"
"0"
"H"
Data is set in UARTi transmit buffer register
bit (TE)
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
CTSi
CLKi
T
CLK
"L"
Stopped pulsing because CTS = "H"
Stopped pulsing because transfer enable bit = "0"
TxDi
D
0
D
1
D2
D3
D4
D5
D6
D
7
D0
D
1
D2
D3
D
4
D5
D6
D7
D
0
D1
D2
D
3
D
4
D
5
D6
D7
Transmit
register empty
flag (TXEPT)
"1"
"0"
"1"
"0"
Transmit interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
Tc = TCLK = 2(n + 1) / fjSIO2
fjSIO2: frequency of BRGi count source (j = 2, 8, 32)
n: value set to BRGi
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0".
• Example of receive timing (when external clock is selected)
"1"
Receive enable
bit (RE)
"0"
"1"
Transmit enable
bit (TE)
"0"
"1"
"0"
"H"
Dummy data is set in UARTi transmit buffer register
Transmit buffer
empty flag (Tl)
Transferred from UARTi transmit buffer register to UARTi transmit register
RTSi
CLKi
RxDi
"L"
1 / fEXT
Receive data is taken in
D
0
D1
D
2
D3
D
4
D5
D
6
D0
D
1
D
2
D4
D5
D
7
D3
Transferred from UARTi receive register
to UARTi receive buffer register
Read out from UARTi receive buffer register
"1"
"0"
Receive complete
flag (Rl)
"1"
"0"
Receive interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Meet the following conditions are met when the CLK
input before data reception = "H"
• Transmit enable bit "1"
• Receive enable bit "1"
• Dummy data write to UARTi transmit buffer register
The above timing applies to the following settings:
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = "0".
f
EXT: frequency of external clock
Figure 1.16.10. Typical transmit/receive timings in clock synchronous serial I/O mode
130
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
(a) Polarity select function
As shown in Figure 1.16.11, the CLK polarity select bit (bit 6 at addresses 03A416, 03AC16, 01FC16)
allows selection of the polarity of the transfer clock.
• When CLK polarity select bit = "0"
CLK
i
Note 1: The CLKi pin level when not
transferring data is "H".
D0
D
1
D
2
D
3
3
D
4
D
5
5
D
6
6
D
7
7
TXDi
D0
D
1
D
2
D
D4
D
D
D
RXDi
• When CLK polarity select bit = "1"
CLK
i
Note 2: The CLKi pin level when not
transferring data is "L".
D
0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
D
0
D
1
D
2
D
3
D
D
5
D
6
D7
RXDi
Figure 1.16.11. Polarity of transfer clock
(b) LSB first/MSB first select function
As shown in Figure 1.16.12, when the transfer format select bit (bit 7 at addresses 03A416, 03AC16,
01FC16) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".
• When transfer format select bit = "0"
CLK
i
D0
D
1
D
2
D
3
D
4
4
D
5
D
6
D7
TXDi
LSB first
D
1
D
2
D
3
D
D
5
D
6
D7
D0
RXDi
• When transfer format select bit = "1"
CLK
i
D
7
7
D
6
D
5
D
4
D
3
3
D
2
D
1
D0
TXDi
MSB first
D
6
D
5
D
4
D
D
2
D
1
D0
D
RXDi
Note: This applies when the CLK polarity select bit = "0".
Figure 1.16.12. Transfer format
131
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Synchronous Serial I/O Mode
(c) Transfer clock output from multiple pins function (UART1)
This function allows the setting two transfer clock output pins and choosing one of the two to output a
clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.16.13.)
The multiple pins function is valid only when the internal clock is selected for UART1. Note that when
______ ______
this function is selected, UART1 CTS/RTS function cannot be used.
Microcomputer
T
X
D1
(P67)
CLKS
1
1
(P6
4
)
)
CLK
(P65
IN
IN
CLK
CLK
Note: This applies when the internal clock is selected and transmission
is performed only in clock synchronous serial I/O mode.
Figure 1.16.13. The transfer clock output from the multiple pins function usage
(d) Continuous receive mode
If the continuous receive mode enable bit (bits 2 and 3 at address 03B016, bit 5 at address 01FD16)
is set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer
register is read out, the unit simultaneously goes to a receive enable state without having to set
dummy data to the transmit buffer register back again.
_______ _______
(e) Separate CTS/RTS pins function (UART0)
This function works the same way as in the clock asynchronous serial I/O (UART) mode. The
method of setting and the input/output pin functions are both the same, so refer to select function in
the next section, "(2) Clock asynchronous serial I/O (UART) mode". Note that this function is invalid
if the transfer clock output from the multiple pins function is selected.
(f) Serial data logic switch function (UART2)
When the data logic select bit (bit6 at address 01FD16) = "1", and writing to transmit buffer register or
reading from receive buffer register, data is reversed. Figure 1.16.14 shows the example of serial
data logic switch timing.
• When LSB first
"H"
Transfer clock
"L"
"H"
2
TxD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
(no reverse)
"L"
"H"
"L"
TxD
2
(reverse)
Figure 1.16.14. Serial data logic switch timing
132
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
(2) Clock asynchronous serial I/O (UART) mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.16.5 and 1.16.6 list the specifications of the UART mode. Figure 1.16.15 shows
the UARTi transmit/receive mode register.
Table 1.16.5. Specifications of UART mode (1)
Item
Specification
Transfer data format
• Start bit: 1 bit
• Parity bit: Odd, even, or nothing as selected
• Stop bit: 1 bit or 2 bits as selected
• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected
Transfer clock
•
When internal clock is selected (bit 3 at addresses 03A016, 03A816, 01F816="0") :
fjSIO2/16(n+1) (Note 1) j = 2, 8, 32
•
When external clock is selected (bit 3 at addresses 03A016, 03A816, 01F816 ="1") :
f
EXT/16(n+1)(Note 1) (Note 2)
Transmission/reception
control
• CTS function/RTS function/CTS, RTS function chosen to be invalid
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at addresses 03A516, 03AD16, 01FD16) = "1"
Transmission start
condition
-
Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16, 01FD16) = "0"
- When CTS function selected, CTS input level = "L"
Reception start condition
• To start reception, the following requirements must be met:
- Receive enable bit (bit 2 at addresses 03A516, 03AD16, 01FD16) = "1"
- Start bit detection
• When transmitting
Interrupt request
generation timing
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 01FD16) = "0": Interrupts requested when data transfer from UARTi
transfer buffer register to UARTi transmit register is completed
- Transmit interrupt cause select bits (bits 0, 1 at address 03B016, bit4 at
address 01FD16) = "1": Interrupts requested when data transmission
fromUARTi transfer register is completed
• When receiving
- Interrupts requested when data transfer from UARTi receive register to
UARTi receive buffer register is completed
Error detection
• Overrun error (Note 3)
This error occurs when the next data is ready before contents of UARTi
receive buffer register are read out
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1’s in parity and
character bits does not match the number of 1’s set
• Error sum flag
This flag is set (= "1") when any of the overrun, framing, and parity errors is
encountered
Note 1: "n" denotes the value 0016 to FF16 that is set to the UARTi bit rate generator.
Note 2: fEXT is input from the CLKi pin.
Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that
the UARTi receive interrupt request bit is not set to "1".
133
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
Table 1.16.6. Specifications of UART mode (2)
Item
Specification
Select function
• Separate CTS/RTS pins (UART0)
UART0 CTS and RTS pins each can be assigned to separate pins
• Sleep mode selection (UART0, UART1)
This mode is used to transfer data to and from one of multiple slave micro-
computers
• Serial data logic switch (UART2)
This function is reversing logic value of transferring data. Start bit, parity bit
and stop bit are not reversed.
• TxD, RxD I/O polarity switch (UART2)
This function is reversing TxD port output and RxD port input. All I/O data
level is reversed.
134
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
UARTi transmit / receive mode registers
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UiMR(i=0,1)
Address
03A016, 03A816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
0 : Internal clock
1 : External clock (Note)
CKDIR
STPS
PRY
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity
PRYE
SLEP
Parity enable bit
Sleep select bit
0 : Parity disabled
1 : Parity enabled
0 : Sleep mode deselected
1 : Sleep mode selected
Note: Set the corresponding port direction register to "0".
UART2 transmit / receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2MR
Address
01F816
When reset
0016
R W
Bit symbol
Bit name
Function
b2 b1 b0
SMD0
SMD1
SMD2
Serial I/O mode select bit
1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
Internal / external clock
select bit
Must always be fixed to "0"
CKDIR
STPS
PRY
Stop bit length select bit
0 : One stop bit
1 : Two stop bits
Odd / even parity
select bit
Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity
PRYE
Parity enable bit
0 : Parity disabled
1 : Parity enabled
IOPOL
TxD, RxD I/O polarity
reverse bit (Note)
0 : No reverse
1 : Reverse
Note: Usually set to "0".
Figure 1.16.15. UARTi transmit/receive mode register in UART mode
135
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
Table 1.16.7 lists the functions of the input/output pins during UART mode. This table shows the pin
______ ______
functions when the separate CTS/RTS pins function is not selected. Note that for a period from when the
UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a "H". (If the N-channel
open-drain is selected, this pin is in floating state.)
Table 1.16.7. Input/output pin functions in UART mode
_______ _______
(when separate CTS/RTS pins function is not selected)
Pin name
TxDi
(P6 , P67, P70)
Function
Method of selection
Serial data output
3
RxDi
(P6 , P6
Serial data input
Port P6
bit 1 at address 03EF16)= "0"
(Can be used as an input port when performing transmission only)
2
, P6
6
and P7
1
direction register (bits 2 and 6 at address 03EE16,
2
6
, P7
1
)
)
CLKi
(P6 , P6
Programmable I/O port
Transfer clock input
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = "0"
Internal/external clock select bit (bit 3 at address 03A016, 03A816, 01F816) = "1"
1
5
, P7
2
Port P61, P65 and P72 direction register (bits 1 and 5 at address 03EE16,
bit 2 at address 03EF16) = "0"
CTSi/RTSi
(P6 , P6 , P73)
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = "0"
CTS input
0
4
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = "0"
Port P6 , P6 and P7 direction register (bits 0 and 4 at address 03EE16
0
4
3
,
bit 3 at address 03EF16) = "0"
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = "0"
RTS output
CTS/RTS function select bit (bit 2 at address 03A416, 03AC16, 01FC16) = "1"
Programmable I/O port
CTS/RTS disable bit (bit 4 at address 03A416, 03AC16, 01FC16) = "1"
136
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTS is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to "L".
Tc
Transfer clock
"1"
Transmit enable
bit(TE)
"0"
"1"
"0"
Data is set in UARTi transmit buffer register.
Transmit buffer
empty flag(TI)
Transferred from UARTi transmit buffer register to UARTi transmit register
"H"
"L"
CTSi
Stopped pulsing because transmit enable bit = "0"
Start
bit
Parity Stop
bit bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
D6
D6
SP
"1"
"0"
Transmit register
empty flag (TXEPT)
"1"
"0"
Transmit interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fjSIO2 or 16 (n + 1) / fEXT
The above timing applies to the following settings :
• Parity is enabled.
fjSIO2 : frequency of BRGi count source (j = 2, 8, 32)
f
EXT : frequency of BRGi count source (external clock)
• One stop bit.
n : value set to BRGi
• CTS function is selected.
• Transmit interrupt cause select bit = "1".
• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)
Tc
Transfer clock
"1"
Transmit enable
Data is set in UARTi transmit buffer register
bit(TE)
"0"
"1"
Transmit buffer
empty flag(TI)
"0"
Transferred from UARTi transmit buffer register to UARTi transmit register
Stop Stop
Start
bit
bit
bit
TxDi
ST
D0
D1
ST
D0
D1
D2
D3
D4
D5
D7
D8
ST
D0
D1
D2
D3
D4
D5
D7
D8
SPSP
D6
SP SP
D6
"1"
"0"
Transmit register
empty flag (TXEPT)
"1"
"0"
Transmit interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is disabled.
• Two stop bits.
Tc = 16 (n + 1) / fjSIO2 or 16 (n + 1) / fEXT
fjSIO2 : frequency of BRGi count source (j = 2, 8, 32)
EXT : frequency of BRGi count source (external clock)
n : value set to BRGi
f
• CTS function is disabled.
• Transmit interrupt cause select bit = "0".
Figure 1.16.16. Typical transmit timings in UART mode (UART0, UART1)
137
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)
Tc
Transfer clock
"1"
Transmit enable
bit (TE)
Data is set in UART2 transmit buffer register
"0"
"1"
Note
Transmit buffer
empty flag (TI)
"0"
Transferred from UART2 transmit buffer register to UARTi transmit register
Parity
bit
Stop
bit
Start
bit
TxD2
ST
D
0
D1
D2
D3
D4
D5
D7
P
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D6
D6
"1"
"0"
Transmit register
empty flag (TXEPT)
"1"
"0"
Transmit interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
Tc = 16 (n + 1) / fjSIO2
fjSIO2 : frequency of BRG2 count source (j = 2, 8, 32)
n : value set to BRG2
• Transmit interrupt cause select bit = "1".
Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Figure 1.16.17. Typical transmit timings in UART mode (UART2)
138
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
BRGi count
source
"1"
Receive enable bit
"0"
Stop bit
Start bit
D1
D7
RxDi
D0
Sampled "L"
Receive data taken in
Transfer clock
Transferred from UARTi receive register to
UARTi receive buffer register
Reception triggered when transfer clock
is generated by falling edge of start bit
"1"
Receive
"0"
"H"
"L"
complete flag
RTSi
Receive interrupt
request bit
"1"
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
The above timing applies to the following settings :
• Parity is disabled.
• One stop bit.
• RTS function is selected.
Figure 1.16.18. Typical receive timing in UART mode
______ ______
(a) Separate CTS/RTS pins function (UART0)
______ ______
______
With the separate CTS/RTS bit (bit 6 at address 03B016) is set to "1", the unit outputs/inputs the CTS
______
and RTS signals on different pins. (See Figure 1.16.19.) This function is valid only for UART0. Note
______ ______
that if this function is selected, the CTS/RTS function for UART1 cannot be used, but set to "0", both
_______ _______
_______ _______
the CTS/RTS function select bit (bit 2 at address 03AC16) and the CTS/RTS disable bit (bit 4 at
address 03AC16).
Microcomputer
IC
T
X
D0
(P63)
IN
RX
D0
(P62)
OUT
RTS0 (P6
0
)
CTS
RTS
CTS0 (P6
4
)
Note: CTS/RTS cannot be used simultaneously.
_______ _______
Figure 1.16.19. The separate CTS/RTS pins function usage
(b) Sleep mode (UART0, UART1)
This mode is used to transfer data between specific microcomputers among multiple microcomputers
connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses
03A016 and 03A816) is set to "1" during reception. In this mode, the unit performs receive operation
when the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".
139
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
(c) Function for switching serial data logic (UART2)
When the data logic select bit (bit 6 at address 01FD16) is assigned 1, data is inverted in writing to the
transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the ex-
ample of timing for switching serial data logic.
• When LSB first, parity enabled, one stop bit
"H"
Transfer clock
"L"
"H"
TxD2
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse)
"L"
"H"
"L"
TxD2
(reverse)
ST : Start bit
P : Even parity
SP : Stop bit
Figure 1.16.20. Timing for switching serial data logic
(d) TxD, RxD I/O polarity reverse function (UART2)
This function is to reverse TxD pin output and RxD pin input. The level of any data to be input or output
(including the start bit, stop bit (s), and parity bit) is reversed. Set this function to "0" (not to reverse) for
usual use.
(e) Bus collision detection function (UART2)
This function is to sample the output level of the TxD pin and the input level of the RxD pin at the rising
edge of the transfer clock; if their values are different, then an interrupt request occurs. Figure 1.16.21
shows the example of detection timing of a buss collision (in UART mode).
"H"
Transfer clock
"L"
"H"
TxD
2
2
ST
ST
SP
SP
"L"
"H"
"L"
RxD
Bus collision detection
interrupt request signal
"1"
"0"
Bus collision detection
interrupt request bit
"1"
"0"
ST : Start bit
SP : Stop bit
Figure 1.16.21. Detection timing of a bus collision (in UART mode)
140
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
(3) Clock-asynchronous serial I/O mode (compliant with the SIM interface)
The SIM interface is used for connecting the microcomputer with a memory card I/C or the like; adding
some extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function.
Table 1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).
Table 1.16.8. Specifications of clock-asynchronous serial I/O mode (compliant with the SIM interface)
Item
Specification
Transfer data format
• Transfer data 8-bit UART mode (bit 2 through bit 0 at address 01F816 = "101
• One stop bit (bit 4 at address 01F816 = "0")
2")
• With the direct format chosen
Set parity to "even" (bit 5 and bit 6 at address 01F816 = "1" and "1" respectively)
Set data logic to "direct" (bit 6 at address 01FD16 = "0").
Set transfer format to LSB (bit 7 at address 01FC16 = "0").
• With the inverse format chosen
Set parity to "odd" (bit 5 and bit 6 at address 01F816 = "0" and "1" respectively)
Set data logic to "inverse" (bit 6 at address 01FD16 = "1")
Set transfer format to MSB (bit 7 at address 01FC16 = "1")
Transfer clock
•
With the internal clock chosen (bit 3 at address 01F816 = "0") : fjSIO2 / 16 (n + 1) (Note 1) : j=2, 8, 32
(Do not set external clock)
Transmission / reception
control
• Disable the CTS and RTS function (bit 4 at address 01FC16 = "1")
Other settings
• The sleep mode select function is not available for UART2
Set transmission interrupt factor to "transmission completed" (bit 4 at address
01FD16 = "1")
•
Transmission start
condition
• To start transmission, the following requirements must be met:
- Transmit enable bit (bit 0 at address 01FD16 = "1")
- Transmit buffer empty flag (bit 1 at address 01FD16 = "1")
Reception start condition
• To start reception, the following requirements must be met:
- Reception enable bit (bit 2 at address 01FD16 = "1")
- Detection of a start bit
Interrupt request
generation timing
• When transmitting
When data transmission from the UART2 transfer register is completed
(bit 4 at address 01FD16 = "1")
• When receiving
When data transfer from the UART2 receive register to the UART2 receive
buffer register is completed
Error detection
• Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)
• Framing error (see the specifications of clock-asynchronous serial I/O)
• Parity error (see the specifications of clock-asynchronous serial I/O)
-
On the reception side, an "L" level is output from the TxD
2 pin by use of the parity error
signal output function (bit 7 at address 01FD16 = "1") when a parity error is detected
- On the transmission side, a parity error is detected by the level of input to
the RxD pin when a transmission interrupt occurs
• The error sum flag (see the specifications of clock-asynchronous serial I/O)
2
Note 1: "n" denotes the value 0016 to FF16 that is set to the UART2 bit rate generator.
Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also that
the UART2 receive interrupt request bit is not set to "1".
141
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
Tc
Transfer clock
"1"
Transmit enable
bit(TE)
"0"
"1"
Note 1
Data is set in UART2 transmit buffer register
Transmit buffer
empty flag(TI)
"0"
Transferred from UART2 transmit buffer register to UART2 transmit register
Start
bit
Parity
bit
Stop
bit
TxD
2
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P
P
SP
SP
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
P
SP
RxD
2
An "L" level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 2)
ST
D
0
D1
D
2
D
3
D
4
D5
D
7
P
SP
The level is
D
6
ST
D0
D1
D2
D3
D4
D5
D
6
D7
detected by the
interrupt routine.
The level is detected by the
interrupt routine.
"1"
Transmit register
empty flag (TXEPT)
"0"
"1"
"0"
Transmit interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
Tc = 16 (n + 1) / fjSIO2
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
fjSIO2 : frequency of BRG2 count source (j = 2, 8, 32)
n : value set to BRG2
• Transmit interrupt cause select bit = "1".
Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.
Tc
Transfer clock
"1"
Receive enable
bit (RE)
"0"
Parity
bit
Stop
bit
Start
bit
SP
RxD
2
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
SP
ST
ST
D
0
D
1
D
2
D
3
D
4
D
5
D
7
P
P
D
6
D6
TxD2
An "L" level returns from TxD
the occurrence of a parity error.
2 due to
Signal conductor level
(Note 2)
SP
ST
D0
D1
D2
D3
D4
D5
D7
P
SP
D
0
D
1
D
2
D
3
D
4
D
5
D7
D6
D6
"1"
Receive complete
flag (RI)
"0"
Read to receive buffer
Read to receive buffer
"1"
"0"
Receive interrupt
request bit (IR)
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings :
• Parity is enabled.
• One stop bit.
Tc = 16 (n + 1) / fjSIO2
fjSIO2 : frequency of BRG2 count source (j = 2, 8, 32)
n : value set to BRG2
• Transmit interrupt cause select bit = "0".
Note 2: Equal in waveform because TxD2 and RxD2 are connected.
Figure 1.16.22. Typical transmit/receive timing in UART mode (compliant with the SIM interface)
142
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
(a) Function for outputting a parity error signal
During reception, with the error signal output enable bit (bit 7 at address 01FD16) assigned "1", you
can output an "L" level from the TxD2 pin when a parity error is detected. And during transmission,
comparing with the case in which the error signal output enable bit (bit 7 at address 01FD16) is as-
signed "0", the transmission completion interrupt occurs in the half cycle later of the transfer clock.
Therefore parity error signals can be detected by a transmission completion interrupt program. Figure
1.16.23 shows the output timing of the parity error signal.
• LSB first
"H"
Transfer
"L"
clock
"H"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RxD
2
"L"
"H"
"L"
Hi-Z
TxD
2
"1"
"0"
Receive
complete flag
ST : Start bit
P : Even Parity
SP : Stop bit
Figure 1.16.23. Output timing of the parity error signal
(b) Direct format/inverse format
Connecting the SIM card allows you to switch between direct format and inverse format. If you choose
the direct format, D0 data is output from TxD2. If you choose the inverse format, D7 data is inverted
and output from TxD2.
Figure 1.16.24 shows the SIM interface format.
Transfer
clcck
TxD
(direct)
2
D0
D7
D1
D6
D2
D5
D3
D4
D4
D3
D5
D2
D6
D1
D7
D0
P
P
TxD
2
(inverse)
P : Even parity
Figure 1.16.24. SIM interface format
143
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Clock Asynchronous Serial I/O (UART) Mode
Figure 1.16.25 shows the example of connecting the SIM interface. When setting the data output select
bit (bit 5 at address 01FC16) to "1", connect TxD2 and RxD2 and apply pull-up.
Microcomputer
SIM card
TxD
2
2
RxD
Figure 1.16.25. Connecting the SIM interface (When setting NCH bit to "1")
144
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
UART2 Special Mode Register
The UART2 special mode register (address 01F716) is used to control UART2 in various ways.
Figure 1.16.26 shows the special UART2 mode register.
2
2
In the first place, the control bits related to the I C bus(simplified I C bus) interface are explained.
2
Bit 0 of the UART2 special mode register (address 01F716) is used as the I C mode selection bit.
2
2
Setting "1" in the I C mode selection bit (bit 0 at address 01F716) goes the circuit to achieve the I C bus
2
(simplified I C bus) interface effective.
Since this function uses clock-synchronous serial I/O mode, be sure to set this bit to "0" in UART mode.
2
Table 1.16.9 shows the relation between the I C mode selection bit and respective control workings.
In order to configure P70 as N-channel set the data output select bit (bit 5 at address 01FC16) to "1".
UART2 special mode register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR
Address
01F716
When reset
0016
0
Function
(During clock synchronous
serial I/O mode)
Bit
symbol
Function
(During UART mode)
Bit name
R W
2
I C mode selection bit
0 : Normal mode
1 : I C mode
IICM
Must always be "0"
Must always be "0"
Must always be "0"
Must always be "0"
2
ABC
BBS
Arbitration loss detecting 0 : Update per bit
flag control bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected
Bus busy flag
(Note)
LSYN
SCLL sync output
enable bit
0 : Disabled
1 : Enabled
Bus collision detect
sampling clock select bit
Must always be "0"
0 : Rising edge of transfer
clock
ABSCS
1 : Underflow signal of timer A0
0 : No auto clear function
1 : Auto clear at occurrence of
bus collision
ACSE
SSS
Auto clear function
select bit of transmit
enable bit
Must always be "0"
0 : Ordinary
Transmit start condition
select bit
Must always be "0"
Must always be "0"
1 : Falling edge of RxD
2
Reserved bit
Note: Nothing but "0" may be written.
Figure 1.16.26. UART2 special mode register
145
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
Table 1.16.9. Features in I2C mode
2
Function
Normal mode
I C mode (Note 1)
Start condition detection or stop
condition detection
Bus collision detection
1
Factor of interrupt number 10 (Note 2)
2
3
4
5
6
7
Factor of interrupt number 15 (Note 2)
Factor of interrupt number 16 (Note 2)
UART2 transmission output delay
UART2 transmission
UART2 reception
Not delayed
No acknowledgment detection (NACK)
Acknowledgment detection (ACK)
Delayed
P7
0
1
at the time when UART2 is in use
at the time when UART2 is in use
at the time when UART2 is in use
TxD
RxD
CLK2
2
(output)
(input)
SDA (input/output) (Note 3)
SCL (input/output)
P7
2
P72
P72
DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request cause select bits
8
9
UART2 reception
Acknowledgment detection (ACK)
Noise filter width
15ns
50ns
Reading the terminal when 0 is
assigned to the direction register
Reading the terminal regardless of the
value of the direction register
10 Reading P7
1
H level (when "0" is assigned to
the CLK polarity select bit)
The value set in latch P7
selected
0 when the port is
11 Initial value of UART2 output
2
Note 1: Make the settings given below when I C mode is in use.
Set "0 1 0" in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the CTS/RTS function. Select TXD2 as Nch. Choose the MSB First function.
Note 2: Follow the steps given below to switch from a factor to another.
1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.
Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.
2
P70
through P7
2
conforming to the simplified I C bus
Nch open drain/cmos port select signal
P70/TxD2/SDA
To DMA0, DMA1
To DMA0
Timer
I/O
UART2 transmission/
NACK interrupt
request
Selector
IICM="1"
delay
IICM="0"
IICM="0"
IICM="1"
Transmission
register
UART2
UART2
D
Q
Arbitration
T
UART2 reception/ACK
interrupt request
DMA1 request
Noize
Filter
IICM="1"
Timer
IICM="0"
IICM="1"
Reception register
UART2
IICM="0"
Start condition detection
S
Q
R
Bus busy
Stop condition detection
L-synchronous
NACK
D
Q
Falling edge
detection
T
output enabling bit
D
Q
P71/RxD2/SCL
I/O
R
Q
ACK
T
Data bus
9th pulse
Bus collision/start, stop
condition detection
interrupt request
(Port P7
1
output data latch)
Internal clock
Selector
IICM="1"
IICM="0"
UART2
IICM="1"
Bus collision
detection
CLK
IICM="1"
Noize
Filter
External clock
Noize
Filter
UART2
IICM="0"
IICM="0"
Port reading
With IICM set to "1", the port terminal is to be readable
UART2
P72/CLK2
even if "1" is assigned to P71 of the direction register.
Selector
I/O
Timer
2
Figure 1.16.27. Functional block diagram for I C mode
146
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
2
2
Figure 1.16.27 shows the functional block diagram for I C mode. Setting "1" in the I C mode selection bit
(IICM) causes ports P70, P71, and P72 to work as data transmission-reception terminal SDA, clock
input-output terminal SCL, and port P72 respectively. A delay circuit is added to the SDA transmission
output, so the SDA output changes after SCL fully goes to "L". An attempt to read Port P71 (SCL) results
in getting the terminal's level regardless of the content of the port direction register. The initial value of
SDA transmission output in this mode goes to the value set in port P70. The interrupt factors of the bus
collision detection interrupt, UART2 transmission interrupt, and of UART2 reception interrupt turn to the
start/stop condition detection interrupt, acknowledgment non-detection interrupt, and acknowledgment
detection interrupt respectively.
The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA
terminal (P70) is detected with the SCL terminal (P71) staying "H". The stop condition detection interrupt
refers to the interrupt that occurs when the rising edge of the SDA terminal (P70) is detected with the
SCL terminal (P71) staying "H". The bus busy flag (bit 2 of the special UART2 mode register) is set to "1"
by the start condition detection, and set to "0" by the stop condition detection. The acknowledgment non-
detection interrupt refers to the interrupt that occurs when the SDA terminal level is detected still staying
"H" at the rising edge of the 9th transmission clock. The acknowledgment detection interrupt refers to
the interrupt that occurs when SDA terminal's level is detected already went to "L" at the 9th transmis-
sion clock. Also, assigning "1 1 0 1" (UART2 reception) to the DMA1 request cause select bits provides
the means to start up the DMA transfer by the effect of acknowledgment detection.
Bit 1 of the special UART2 mode register (address 01F716) is used as the arbitration lost detecting flag
control bit. Arbitration means the act of detecting the nonconformity between transmission data and
SDA terminal data at the timing of the SCL rising edge. This detecting flag is located at bit 3 of the
UART2 reception buffer register (address 01FF16), and "1" is set in this flag when nonconformity is
detected. Use the arbitration lost detecting flag control bit to choose which way to use to update the flag,
bit by bit or byte by byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity
is detected, the arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock.
If updated the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after com-
pleting the first byte acknowledge detect and before starting the next one byte transmission.
Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enabling bit.
Setting this bit to "1" resets the P71 data register to "0" in synchronization with the SCL terminal level
going to "L".
147
Mitsubishi microcomputers
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register
Some other functions added are explained here. Figure 1.16.28 shows their workings.
Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit.
The bus collision detect interrupt occurs when the RxD2 level and TxD2 level do not match, but the
nonconformity is detected in synchronization with the rising edge of the transfer clock signal if the bit is
set to "0". If this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0
rather than at the rising edge of the transfer clock.
Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable
bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus
collision detect interrupt request bit (nonconformity).
Bit 6 of the UART2 special mode register is used as the transmission start condition select bit. Setting
this bit to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal.
1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)
0: Rising edges of the transfer clock
CLK
TxD/RxD
1: Timer A0 overflow
Timer A0
2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)
CLK
TxD/RxD
Bus collision
detect interrupt
request bit
Transmit
enable bit
3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)
0: In normal state
CLK
TxD
Enabling transmission
With "1: falling edge of RxD2" selected
CLK
TxD
RxD
Figure 1.16.28. Some other functions added
148
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
UART2 Special Mode Register 2
2
The UART2 special mode register 2 (address 01F616) is used to further control UART2 in I C mode.
Figure 1.16.29 shows the UART2 special mode register 2.
UART2 special mode register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2SMR2
Address
01F616
When reset
0016
Bit
symbol
Bit name
R W
Function
2
I C mode selection bit 2 Refer to Table 1.16.10.
IICM2
CSC
Clock-synchronous bit
SCL wait output bit
0 : Disabled
1 : Enabled
SWC
0 : Disabled
1 : Enabled
(Note)
ASL
SDA output stop bit
0 : Disabled
1 : Enabled
UART2 initialization bit
0 : Disabled
1 : Enabled
STAC
SWC2
SCL wait output bit 2
SDA output disable bit
0: UART2 clock
1: 0 output
0: Enabled
1: Disabled (high impedance)
SDHI
SHTC
Start/stop condition
control bit
Set this bit to "1" in I2C mode
(refer to Table 1.16.11)
Figure 1.16.29. UART2 special mode register 2
149
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
2
Bit 0 of the UART2 special mode register 2 (address 01F616) is used as the I C mode selection bit 2.
2
2
Table 1.16.10 shows the types of control to be changed by I C mode selection bit 2 when the I C mode
selection bit is set to "1". Table 1.16.11 shows the timing characteristics of detecting the start condition
and the stop condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to
2
"1" in I C mode.
2
Table 1.16.10. Functions changed by I C mode selection bit 2
IICM2 = 1
Function
IICM2 = 0
1
2
3
UART2 transmission (the rising edge
of the final bit of the clock)
Factor of interrupt number 15
No acknowledgment detection (NACK)
Factor of interrupt number 16
Acknowledgment detection (ACK)
UART2 reception (the falling edge
of the final bit of the clock)
DMA1 factor at the time when "1 1 0 1" Acknowledgment detection (ACK)
is assigned to the DMA request
cause select bits
UART2 reception (the falling edge of
the final bit of the clock)
The rising edge of the final bit of the
Timing for transferring data from the
UART2 reception shift register to the
reception buffer.
4
5
The falling edge of the final bit of the
reception clock
reception clock
Timing for generating a UART2
reception/ACK interrupt request
The rising edge of the final bit of the
reception clock
The falling edge of the final bit of the
reception clock
Table 1.16.11. Timing characteristics of detecting the start condition and the stop condition (Note 1)
3 to 6 cycles < duration for setting-up (Note 2)
3 to 6 cycles < duration for holding (Note 2)
Note 1: When the start/stop condition count bit is "1".
Note 2: "cycles" is in terms of the input oscillation frequency f(XIN) of the main clock.
Duration for
setting up
Duration for
holding
SCL
SDA
(Start condition)
SDA
(Stop condition)
150
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
2
P70 through P72 conforming to the simplified I C bus
Nch open drain/cmos port select signal
P70/TxD2/SDA
Timer
To DMA0, DMA1
Selector
IICM="0"
or IICM2="1"
I/O
UART2 transmission/
NACK interrupt
request
UART2
IICM="1"
Transmission register
UART2
delay
IICM="1"
IICM="0"
SDHI
and IICM2="0"
ALS
To DMA0
D
Arbitration
IICM="1"
Q
T
Noize
Filter
IICM="0"
or IICM2="1"
UART2 reception/ACK interrupt request
DMA1 request
Reception register
UART2
IICM="0"
IICM="1"
and IICM2="0"
Start condition detection
S
R
Bus
busy
Q
Stop condition detection
L-synchronous
NACK
D
D
Q
Q
Falling edge
detection
T
T
output enabling bit
P71/RXD2/SCL
I/O
R
ACK
Data register
9th pulse
Selector
Bus collision/start, stop condition detection
interrupt request
IICM="1"
Internal clock
UART2
IICM="1"
Bus collision
detection
UART2
SWC2
CLK
control
IICM="0"
IICM="1"
Noize
Filter
External clock
Noize
Filter
Falling of 9th pulse
SWC
IICM="0"
R
S
Port reading
With IICM set to "1", the port terminal is to be readable
even if "1" is assigned to P71 of the direction register.
UART2
IICM="0"
P72/CLK2
Selector
I/O
Timer
2
Figure 1.16.30. Functional block diagram for I C mode
2
Functions available in I C mode are shown in Figure 1.16.30 — a functional block diagram.
Bit 3 of the UART2 special mode register 2 (address 01F616) is used as the SDA output stop bit. Setting
this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state the
instant when the arbitration lost detecting flag is set to "1".
Bit 1 of the UART2 special mode register 2 (address 01F616) is used as the clock synchronization bit.
With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the
falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting
within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops
counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this
function, the UART2 transmission-reception clock becomes the logical product of the signal flowing
through the internal SCL and that flowing through the SCL pin. This function operates over the period
from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the
ninth bit. To use this function, choose the internal clock for the transfer clock.
Bit 2 of the UART2 special mode register 2 (address 01F616) is used as the SCL wait output bit. Setting
this bit to "1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting
this bit to "0" frees the output fixed to "L".
151
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
UART2 Special Mode Register 2
Bit 4 of the UART2 special mode register 2 (address 01F616) is used as the UART2 initialization bit.
Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows:
(1) The transmission shift register is initialized, and the content of the transmission register is transferred
to the transmission shift register. This starts transmission by dealing with the clock entered next as
the first bit. The UART2 output value, however, does not change until the first bit data is output after
the entrance of the clock, and remains unchanged from the value at the moment when the microcom-
puter detected the start condition.
(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the
clock entered next as the first bit.
(3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of
the clock.
Starting to transmit/receive signals to/from UART2 using this function does not change the value of the
transmission buffer empty flag. To use this function, choose the external clock for the tansfer clock.
Bit 5 of the UART2 special mode register 2 (address 01F616) is used as the SCL pin wait output bit 2.
Setting this bit to "1" with the serial I/O specified allows the user to forcibly output an "L" from the SCL pin
even if UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2
clock is input/output.
Bit 6 of the UART special mode register 2 (address 01F616) is used as the SDA output enable bit.
Setting this bit to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the
value of this bit at the rising edge of the UART2 transfer clock. There can be instances in which arbitra-
tion lost detecting flag is turned on.
152
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
S I/O3
S I/O3 is exclusive clock-synchronous serial I/O.
Figure 1.16.31 shows the S I/O3 block diagram, and Figure 1.16.32 shows the S I/O3 control register.
Table 1.16.12 shows the specifications of S I/O3.
Data bus
f
2
SIO
2
2
SM31
SM30
f
8
SIO
f
32SIO
2
Synchronous
circuit
1/2
1/(n+1)
SM33
SM36
Transfer rate register (8)
S I/O3 counter (3)
SM36
S I/O3
interrupt request
P90/CLK3
SM32
SM33
SM35 LSB
MSB
P92/SOUT3
P91/SIN3
S I/O3 transmission/reception register (8)
8
n: A value set in the S I/O3 transfer rate register (01E316
)
Figure 1.16.31. S I/O3 block diagram
153
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
S I/O3 control register (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3C
Address
01E216
When reset
4016
Bit
symbol
Description
Bit name
R W
b1 b0
SM30
SM31
Internal synchronous
clock select bit
0 0 : Selecting f2SIO2
0 1 : Selecting f8SIO2
1 0 : Selecting f32SIO2
1 1 : Not to be used
SOUT3 output disable bit
0 : SOUT3 output
1 : SOUT3 output disable (high impedance
SM32
SM33
)
S I/O3 port select bit
(Note 2)
0 : Input-output port
1 : SOUT3 output, CLK function
Nothing is assigned.
This bit can neither be set nor read.
When read, the value of this bit is "0".
SM35
0 : LSB first
1 : MSB first
Transfer direction
select bit
SM36
SM37
Synchronous clock
select bit (Note 2)
0 : External clock
1 : Internal clock
SOUT3initial value
set bit
Effective when SM33 = 0
0 : L output
1 : H output
Note 1: Set "1" in bit 2 of the protection register (000A16) in advance to write to the
S I/O3 control register.
Note 2: When set "0" to SM33 bit and select input - output port, set "1" to SM36 bit
and select internal clock.
Figure 1.16.32. S I/O3 control register
S I/O3 bit rate generator (Note 1, 2)
Symbol
S3BRG
Address
01E316
When reset
Indeterminate
b7
b0
Indeterminate
Values that can be set
0016 to FF16
R
W
Assuming that set value = n, BRG3 divides the count
source by n + 1
Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.
S I/O3 transmit/receive register (Note)
b7
b0
Symbol
S3TRR
Address
01E016
When reset
Indeterminate
R W
Indeterminate
Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.
Note: Write a value to this register while transmit/receive halts.
Figure 1.16.33. S I/O3 related register
154
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
Table 1.16.12. Specifications of S I/O3
Item
Specifications
Transfer data format • Transfer data length: 8 bits
• With the internal clock selected (bit 6 at address 01E216 = "1"): fjSIO2/2(n+1)
(j = 2, 8, 32) (Note 1)
Transfer clock
•
With the external clock selected (bit 6 at address 01E216 = "0"): Input from the CLK3
terminal (Note 2)
Conditions for
transmission/
reception start
• To start transmit/reception, the following requirements must be met:
- Select the synchronous clock (use bit 6 at address 01E216).
Select a frequency dividing ratio if the internal clock has been selected (use bits
0 and 1 at address 01E216).
- SOUT3 initial value set bit (use bit 7 at address 01E216) = "1".
- S I/O3 port select bit (bit 3 at address 01E216) = "1".
- Select the transfer direction (use bit 5 at address 01E216
)
- Write transfer data to the S I/O3 transmit/receive register (address 01E016
• To use S I/O3 interrupts, the following requirements must be met:
)
- Clear the S I/O3 interrupt request bit (bit 3 at address 004916) before writing
transfer data to the S I/O3 transmit/receive register.
Interrupt request • Rising edge of the last transfer clock. (Note 3)
generation timing
Select function
• LSB first or MSB first selection
Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be
selected.
Precaution
• Unlike UART0 to 2, S I/O3 is not divided for transfer register and buffer.
Therefore, do not write the next transfer data to the S I/O3 transmit/receive
register (address 01E016) during a transfer.
• When the internal clock is selected for the transfer clock, SOUT3 holds the last
data for a 1/2 transfer clock period after it finished transferring and then goes to a
high-impedance state. However, if the transfer data is written to the S I/O3
transmit/receive register (address 01E016) during this time, SOUT3 is placed in the
high-impedance state immediately upon writing and the data hold time is thereby
reduced.
Note 1: "n" is a value from 0016 to FF16 set in the S I/O3 transfer rate generator.
Note 2: With the external clock selected:
• Before data can be written to the S I/O3 transmit/receive register (address 01E016), the CLK3 pin input
must be in the high state. Also, before rewriting bit 7 of the S I/O3 control register (address 01E216), make
sure the CLK3 pin input is held high.
• The S I/O3 circuit keeps on with the shift operation as long as the synchronous clock is entered in it,
so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,
automatically stops.
Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the "H" state.
155
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
S I/O3
Functions for setting an SOUT3 initial value
When using an external clock for the transfer clock, the SOUT3 pin output level during a non-transfer
time can be set to high or low state. Figure 1.16.34 shows the timing chart for setting an SOUT3 initial
value and how to set it.
(Example) With "H" selected for SOUT3
S I/O3 port select bit SM33 = "0"
Signal written to the S I/O3
transmission/reception
register
S
OUT3 initial value select bit
SM37 = "1"
S
OUT3’s initial value
setting bit (SM37)
(SOUT3: Internal -> "H" level)
S I/O3 port select bit
SM33 = 0 -> 1
(Port select: Normal port -> SOUT3)
S I/O3 port select bit
(SM33)
D0
D0
S
OUT3 terminal = "H" output
S
OUT3 (internal)
Signal written to the S I/O3 register
= "L" -> "H" -> "L"
Port output
S
OUT3 terminal output
(Falling edge)
Initial value = "H" (Note)
Setting the SOUT3
initial value to "H"
Port selection
(normal port -> SOUT3
S
OUT3 terminal = Outputting
stored data in the S I/O3
)
transmission/reception register
Note: The set value is output only when the external clock has been selected. When initializing
OUT3, make sure the CLK3 pin input is held "H" level.
S
If the internal clock has been selected or if SOUT3 output disable has been set, this
output goes to the high-impedance state.
Figure 1.16.34. Timing chart for setting SOUT3's initial value and how to set it
S I/O3 operation timing
Figure 1.16.35 shows the S I/O3 operation timing
1.5 cycle (max)
"H"
S I/O3 internal clock
"L"
"H"
"L"
Transfer clock
(Note 1)
"H"
"L"
Signal written to the S I/O3
transmit/receive register
(Note 2)
Hiz
Hiz
"H"
"L"
S I/O3 output
SOUT3
D0
D1
D2
D3
D4
D5
D6
D7
"H"
"L"
S I/O3 input
S
IN3
"1"
"0"
S I/O3 interrupt request bit
Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/O3 control
register. (No frequency division, 8-division frequency, 32-division frequency.)
Note 2: With the internal clock selected for the transfer clock, the SOUT3 pin becomes to the high-impedance state after the transfer finishes.
Note 3: Shown above is the case where the SOUT3 port select bit ="1".
Figure 1.16.35. S I/O3 operation timing chart
156
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D Converter
The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive
coupling amplifier. Pins P00 to P07, P20 to P27, P100 to P107, P95, and P96 function as the analog signal
input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The VREF
connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from
the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current
flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D con-
verter, start A-D conversion only after setting the VREF connect bit (bit 5 at address 03D716) to connect
VREF.
The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision,
the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit
precision, the low 8 bits are stored in the even addresses.
Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the A-
D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers.
Table 1.17.1. Performance of A-D converter
Item
Method of A-D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to AVCC (VCC
Performance
)
Operating condition øAD
VCC = 5V, f2AD divided by 1, 2, or 4. f2AD=f(XIN)/2 (PCLK0 ="0")
(Note 2)
f2AD=f(XIN) (PCLK0 ="1")
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5
• Without sample and hold function
3LSB
•
•
With sample and hold function (8-bit resolution)
2LSB
With sample and hold function (10-bit resolution)
AN0 to AN7, AN00 to AN07, and AN20 to AN27 input : 3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected) : 7LSB
Operating modes
Analog input pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and
repeat sweep mode 1
24pins(AN0 toAN7, AN00 toAN07 andAN20 toAN27) +2pins(ANEX0andANEX1)
A-D conversion start condition • Software trigger
A-D conversion starts when the A-D conversion start flag changes to "1"
• External trigger (can be retriggered)
A-D conversion starts when the A-D conversion start flag is "1" and the
ADTRG/P9
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 AD cycles
• With sample and hold function
8-bit resolution: 28 AD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Without sample and hold function, set the AD frequency to 250kHz min.
With the sample and hold function, set the AD frequency to 1MHz min.
In either case, the AD frequency may not exceed 10 MHz.
7 input changes from "H" to "L"
ø
,
10-bit resolution: 59
ø
AD cycles
AD cycles
ø
, 10-bit resolution: 33
ø
ø
ø
ø
157
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
PCLK0="1"
PCLK0="0"
f2AD
XIN
1/2
A-Dconversion rate selection
CKS1="1"
CKS1="0"
ø
AD
CKS0="1"
f2AD
1/2
1/2
CKS0="0"
VREF
Resister ladder
VCUT="0"
VCUT="1"
AVSS
Successive conversion register
A-D control register 1
(Address 03D716
)
A-D control register 0
(Address 03D616
)
A-D register 0 (16)
(Address 03C116,03C016
(Address 03C316,03C216
(Address 03C516,03C416
(Address 03C716,03C616
(Address 03C916,03C816
)
)
)
)
)
A-D register 1 (16)
A-D register 2 (16)
A-D register 3 (16)
Decoder for
register
A-D register 4 (16)
A-D register 5 (16)
A-D register 6 (16)
(Address 03CB16,03CA16
(Address 03CD16,03CC16
(Address 03CF16,03CE16
)
)
A-D register 7 (16)
)
Data bus high-order
A-D control register 2
Data bus low-order
(Address 03D416)
PM00
PM01
V
REF
Decoder for selectiong
channel
Comparator
V
IN
CH2,CH1,CH0
=000
Port P10 group
ADGSEL1,ADGSEL0=00
OPA1,OPA0=00
P10
0
/AN
0
1
=001
=010
=011
=100
=101
=110
=111
P101/AN
P10
2
/AN
2
3
PM01,PM00,CH2,CH1,CH0
=00000
Port P0 group
P103/AN
P0
0
/AN00
/AN01
P10
4
/AN
4
5
=00001
=00010
=00011
=00100
=00101
=00110
=00111
PM01,PM00=00
ADGSEL1,ADGSEL0=10
OPA1,OPA0=00
P01
P105/AN
P0
2
/AN02
P10
6
/AN
6
7
P03/AN03
P107/AN
P0
4
/AN04
/AN05
P05
P0
6
/AN06
PM01,PM00=00
ADGSEL1,ADGSEL0=11
OPA1,OPA0=00
P07/AN07
PM01,PM00,CH2,CH1,CH0
=00000
Port P2 group
P20/AN20
=00001
=00010
=00011
=00100
=00101
=00110
=00111
P2
1
/AN21
ADGSEL1,ADGSEL0=00
OPA1,OPA0=11
P22/AN22
P2
3
/AN23
/AN24
P24
PM01,PM00=00
ADGSEL1,ADGSEL0=10
OPA1,OPA0=11
P2
5
/AN25
P26/AN26
P27/AN27
PM01,PM00=00
ADGSEL1,ADGSEL0=11
OPA1,OPA0=11
OPA1,OPA0
=01
OPA0=1
OPA1=1
ANEX
0
1
OPA1=1
ANEX
Figure 1.17.1. Block diagram of A-D converter
158
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
R W
Bit symbol
Bit name
Function
0 is selected
b2 b1 b0
CH0
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
b4 b3
Analog input pin select bit
(Note 2, 3)
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
CH1
CH2
MD0
MD1
A-D operation mode
select bit 0
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0
Repeat sweep mode 1
Trigger select bit
0 : Software trigger
1 : ADTRG trigger
TRG
ADST
CKS0
A-D conversion start flag
Frequency select bit 0
0 : A-D conversion disabled
1 : A-D conversion started
0 : f2AD/4 is selected
1 : f2AD/2 is selected
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN
0 to AN7.
Note 3: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
Bit symbol
Bit name
Function
R W
When single sweep and repeat sweep
A-D sweep pin select bit
(Note 2)
mode 0 are selected
b1 b0
SCAN0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
(6 pins)
(8 pins)
When repeat sweep mode 1 is selected
b1 b0
SCAN1
MD2
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN
1
(2 pins)
to AN
2
3
(3 pins)
(4 pins)
to AN
A-D operation mode
select bit 1
0 : Any mode other than repeat sweep
mode 1
1 : Repeat sweep mode 1
8/10-bit mode select bit
0 : 8-bit mode
1 : 10-bit mode
BITS
Frequency select bit 1
(Note 3)
0 : f2AD/2 or f2AD/4 is selected
1 : f2AD is selected
CKS1
V
REF connect bit
0 : VREF not connected
1 : VREF connected
VCUT
OPA0
OPA1
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is
indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7.
Note 3: Divide the frequency if f(XIN) exceeds 10MHz, and make øAD frequency equal to or
less than 10MHz.
Figure 1.17.2. A-D converter-related registers (1)
159
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
A-D control register 2 (Note)
Symbol
ADCON2
Address
03D416
When reset
b7 b6 b5 b4 b3 b2 b1 b0
XXXX0000
2
0
0 0 0 0
Bit symbol
SMP
Bit name
Function
R W
0 : Without sample and hold
1 : With sample and hold
A-D conversion method
select bit
b2 b1
A-D group select bit
ADGSEL0
ADGSEL1
0 0 : Port P10 group select
0 1 : inhibited
1 0 : Port P0 group select
1 1 : Port P2 group select
Always set to "0"
Reserved bits
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Symbol
ADi (i=0 to 7)
Address
When reset
A-D register i
(b15)
b7
03C016 to 03CF16 Indeterminate
(b8)
b0 b7
b0
Function
R W
Eight low-order bits of A-D conversion result
• During 10-bit mode
Two high-order bits of A-D conversion result
• During 8-bit mode
When read, the content is indeterminate
Nothing is assigned.
These bits can neither be set nor reset. When read, their
content is "0".
Figure 1.17.3. A-D converter-related registers (2)
160
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(1) One-shot mode
In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-
sion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control regis-
ter in one-shot mode.
Table 1.17.2. One-shot mode specifications
Item
Specification
Function
The pin selected by the analog input pin select bit is used for one A-D conversion
Writing "1" to A-D conversion start flag
Start condition
Stop condition
•
•
End of A-D conversion (A-D conversion start flag changes to "0", except
when external trigger is selected)
Writing "0" to A-D conversion start flag
Interrupt request
generation timing
End of A-D conversion
Input pin
One of AN0 to AN7, as selected
Reading of result of
A-D converter
Read A-D register corresponding to selected pin
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
When reset
00000XXX2
b7 b6 b5 b4 b3 b2 b1 b0
0
0
Bit symbol
CH0
Bit name
Function
R W
b2 b1 b0
Analog input pin select
bit (Note 2, 3)
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0 (Note 3)
0 0 : One-shot mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0 : f2AD/4 is selected
1 : f2AD/2 is selected
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN
0 to AN7.
Note 3: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in one-shot mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Set to "0" when this mode is selected
MD2
BITS
CKS1
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
Frequency select bit1
(Note 2)
0 : f2AD/2 or f2AD/4 is selected
1 : f2AD is selected
V
REF connect bit
1 : VREF connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make øAD frequency
equal to or less than 10MHz.
Figure 1.17.4. A-D conversion register in one-shot mode
161
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(2) Repeat mode
I
n repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.
Table 1.17.3 shows the specifications of repeat mode. Figure 1.17.5 shows the A-D control register in
repeat mode.
Table 1.17.3. Repeat mode specifications
Item
Specification
Function
Start condition
Stop condition
The pin selected by the analog input pin select bit is used for repeated A-D conversion.
Writing "1" to A-D conversion start flag
Writing "0" to A-D conversion start flag
Interrupt request
generation timing
None generated
Input pin
One of AN
0 to AN7, as selected
Reading of result of A-D
converter
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note 1)
Symbol
ADCON0
Address
03D616
When reset
b7 b6 b5 b4 b3 b2 b1 b0
00000XXX
2
0
1
Bit symbol
Bit name
Analog input pin select
Function
R W
b2 b1 b0
CH0
CH1
CH2
0 0 0 : AN
0 0 1 : AN
0 1 0 : AN
0 1 1 : AN
1 0 0 : AN
1 0 1 : AN
1 1 0 : AN
1 1 1 : AN
0
1
2
3
4
5
6
7
is selected
is selected
is selected
is selected
is selected
is selected
is selected
is selected
bit (Note 2, 3)
b4 b3
MD0
MD1
A-D operation mode
select bit 0 (Note 3)
0 1 : Repeat mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0 : f2AD/4 is selected
1 : f2AD/2 is selected
Frequency select bit 0
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN
0 to AN7.
Note 3: When changing A-D operation mode, set analog input pin again.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
Invalid in repeat mode
SCAN0
SCAN1
select bit
A-D operation mode
select bit 1
0 : Set to "0" when this mode is selected
MD2
BITS
CKS1
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
Frequency select bit1
(Note 2)
0 : f2AD/2 or f2AD/4 is selected
1 : f2AD is selected
V
REF connect bit
1 : VREF connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: Divide the frequency if f(XIN) exceeds 10MHz, and make øAD frequency
equal to or less than 10MHz.
Figure 1.17.5. A-D conversion register in repeat mode
162
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(3) Single sweep mode
I
n single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D
conversion. Table 1.17.4 shows the specifications of single sweep mode. Figure 1.17.6 shows the A-D
control register in single sweep mode.
Table 1.17.4. Single sweep mode specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion.
Start condition
Stop condition
Writing "1" to A-D converter start flag
• End of A-D conversion (A-D conversion start flag changes to "0", except when external
trigger is selected)
• Writing "0" to A-D conversion start flag
Interrupt request
generation timing
End of A-D conversion
Input pin
AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)
Reading of result of A-D
converter
Read A-D register corresponding to selected pin
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
00000XXX
b7 b6 b5 b4 b3 b2 b1 b0
2
1
0
Bit symbol
Bit name
Function
R W
Analog input pin select
bit
Invalid in single sweep mode
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 0 : Single sweep mode
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0 : f2AD/4 is selected
1 : f2AD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
When single sweep and repeat sweep mode
select bit (Note 2)
0 are selected:
SCAN0
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
SCAN1
MD2
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Set to "0" when this mode is selected
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Frequency select bit1
(Note 3)
0 : fAD2/2 or fAD2/4 is selected
1 : fAD2 is selected
CKS1
V
REF connect bit
1 : VREF connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
(Note 4)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7.
Note 3: Divide the frequency if f(XIN) exceeds 10MHz, and make øAD frequency
equal to or less than 10MHz.
Note 4: Neither "01" nor "10" can be selected with the external op-amp connection
mode bit.
Figure 1.17.6. A-D conversion register in single sweep mode
163
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(4) Repeat sweep mode 0
In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep
A-D conversion. Table 1.17.5 shows the specifications of repeat sweep mode 0. Figure 1.17.7 shows the
A-D control register in repeat sweep mode 0.
Table 1.17.5. Repeat sweep mode 0 specifications
Item
Specification
Function
The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion.
Writing "1" to A-D conversion start flag
Start condition
Stop condition
Writing "0" to A-D conversion start flag
Interrupt request
generation timing
None generated
Input pin
AN0
and AN
1
(2 pins), AN
0
to AN
3
(4 pins), AN
0
to AN
5
(6 pins), or AN
0
to AN7 (8 pins)
Reading of result of A-D
converter
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
00000XXX
b7 b6 b5 b4 b3 b2 b1 b0
2
1
1
Bit symbol
Bit name
Function
R W
Analog input pin select
bit
Invalid in repeat sweep mode 0
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 0
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0 : f2AD/4 is selected
1 : f2AD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
0
Bit symbol
Bit name
A-D sweep pin
Function
R W
When single sweep and repeat sweep mode
select bit (Note 2)
0 are selected:
SCAN0
b1 b0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
, AN1 (2 pins)
to AN
to AN
to AN
3
5
7
(4 pins)
SCAN1
MD2
(6 pins)
(8 pins)
A-D operation mode
select bit 1
0 : Set to "0" when this mode is selected
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Frequency select bit1
(Note 3)
0 : f2AD/2 or f2AD/4 is selected
1 : f2AD is selected
CKS1
V
REF connect bit
1 : VREF connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bit
(Note 4)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7.
Note 3: Divide the frequency if f(XIN) exceeds 10MHz, and make øAD frequency
equal to or less than 10MHz.
Note 4: Neither "01" nor "10" can be selected with the external op-amp connection
mode bit.
Figure 1.17.7. A-D conversion register in repeat sweep mode 0
164
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(5) Repeat sweep mode 1
In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected
using the A-D sweep pin select bit. Table 1.17.6 shows the specifications of repeat sweep mode 1. Figure
1.17.8 shows the A-D control register in repeat sweep mode 1.
Table 1.17.6. Repeat sweep mode 1 specifications
Item
Specification
Function
All pins perform repeat sweep A-D conversion, with emphasis on the pin or pins selected
by the A-D sweep pin select bit
Example; AN
0
selected AN
0
AN
1
AN
0
AN2
AN
0
AN3, etc
Start condition
Stop condition
Writing "1" to A-D conversion start flag
Writing "0" to A-D conversion start flag
Interrupt request
generation timing
None generated
Input pin
With emphasis on these pins; AN
0
(1 pin), AN
0
and AN
1
(2 pins), AN
0
to AN
2
(3 pins), AN0 to AN3 (4 pins)
Reading of result of A-D
converter
Read A-D register corresponding to selected pin (at any time)
A-D control register 0 (Note)
Symbol
ADCON0
Address
03D616
When reset
00000XXX
b7 b6 b5 b4 b3 b2 b1 b0
2
1
1
Bit symbol
Bit name
Function
R W
Analog input pin select
bits
Invalid in repeat sweep mode 1
CH0
CH1
CH2
b4 b3
MD0
MD1
A-D operation mode
select bit 0
1 1 : Repeat sweep mode 1
0 : Software trigger
1 : ADTRG trigger
Trigger select bit
TRG
ADST
CKS0
A-D conversion start flag 0 : A-D conversion disabled
1 : A-D conversion started
0 : f2AD/4 is selected
1 : f2AD/2 is selected
Frequency select bit 0
Note: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
A-D control register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D716
When reset
0016
1
1
Bit symbol
Bit name
A-D sweep pin
Function
R W
When repeat sweep mode 1 is selected:
select bits (Note 2)
b1 b0
SCAN0
0 0 : AN
0 1 : AN
1 0 : AN
1 1 : AN
0
0
0
0
(1 pin)
, AN (2 pins)
1
to AN
to AN
2
3
(3 pins)
(4 pins)
SCAN1
MD2
A-D operation mode
select bit 1
1 : Set to "1" when this mode is selected
8/10-bit mode select bit 0 : 8-bit mode
1 : 10-bit mode
BITS
Frequency select bit1
(Note 3)
0 : f2AD/2 or f2AD/4 is selected
1 : f2AD is selected
CKS1
V
REF connect bit
1 : VREF connected
VCUT
OPA0
b7 b6
External op-amp
connection mode bits
(Note 4)
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode
OPA1
Note 1: If the A-D control register is rewritten during A-D conversion, the conversion
result is indeterminate.
Note 2: AN00 to AN07 and AN20 to AN27 can be used in the same way as AN0 to AN7.
Note 3: Divide the frequency if f(XIN) exceeds 10MHz, and make øAD frequency
equal to or less than 10MHz.
Note 4: Neither "01" nor "10" can be selected with the external op-amp connection
mode bit.
Figure 1.17.8. A-D conversion register in repeat sweep mode 1
165
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
A-D Converter
(a) Sample and hold
Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to "1". When
sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 øAD cycle is
achieved with 8-bit resolution and 33 øAD with 10-bit resolution. Sample and hold can be selected in all
modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and
hold is to be used.
(b) Extended analog input pins
In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can
also be converted from analog to digital.
When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "0", input via ANEX0 is
converted from analog to digital. The result of conversion is stored in A-D register 0.
When bit 6 of the A-D control register 1 (address 03D716) is "0" and bit 7 is "1", input via ANEX1 is
converted from analog to digital. The result of conversion is stored in A-D register 1.
(c) External operation amp connection mode
In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can
be amplified together by just one operation amp and used as the input for A-D conversion.
When bit 6 of the A-D control register 1 (address 03D716) is "1" and bit 7 is "1", input via AN0 to AN7 is
output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the
corresponding A-D register. The speed of A-D conversion depends on the response of the external op-
eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.17.9 is an example of how to
connect the pins in external operation amp mode.
ADGSEL1, ADGSEL0
="0,0"
AN0
Resistor ladder
AN
1
2
AN
Port P10 group
analog input
AN
3
4
AN
Successive conversion register
AN
5
6
AN
AN7
ADGSEL1, ADGSEL0
="1,0"
AN00
AN01
AN02
Port P0 group
analog input
AN03
AN04
AN05
AN06
AN07
ADGSEL1, ADGSEL0
="1,1"
AN20
AN21
AN22
Port P2 group
analog input
AN23
AN24
AN25
AN26
AN27
ANEX
0
1
ANEX
Comparator
External op-amp
Figure 1.17.9. Example of external op-amp connection mode
166
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A Converter
This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of
this type.
D-A conversion is performed when a value is written to the corresponding D-A register. The D-A output
enable bits (bits 0 and 1 at address 03DC16) decide if the result of conversion is to be output. Do not set the
target port to output mode if D-A conversion is to be performed.
Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.
V = VREF X n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 1.18.1 lists the performance of the D-A converter. Figure 1.18.1 shows the block diagram of the D-A
converter. Figure 1.18.2 shows the D-A control register.
Table 1.18.1. Performance of D-A converter
Item
Conversion method
Resolution
Performance
R-2R method
8 bits
Analog output pin
2 channels
Data bus low-order bits
D-A register0 (8)
(Address 03D816
)
D-A0 output enable bit
P9 /DA
3
0
R-2R resistor ladder
D-A register1 (8)
(Address 03DA16
D-A1 output enable bit
P9 /DA
)
4
1
R-2R resistor ladder
Figure 1.18.1. Block diagram of D-A converter
167
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D-A Converter
D-A control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DC16
When reset
0016
Bit symbol
DA0E
Bit name
Function
0 : Output disabled
R W
D-A0 output enable bit
D-A1 output enable bit
1 : Output enabled
0 : Output disabled
1 : Output enabled
DA1E
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".
D-A register
b7
Symbol
DAi (i = 0,1)
Address
03D816 03DA16
When reset
Indeterminate
b0
,
Function
R W
Output value of D-A conversion
Figure 1.18.2. D-A control register
D-A0 output enable bit
"0"
R
R
R
R
R
R
R
3R
DA0
"1"
2R
MSB
2R
2R
2R
2R
2R
2R
2R
LSB
D-A0 register0
AVSS
REF
V
Note 1: The above diagram shows an instance in which the D-A register is assigned 2A16
.
Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to "0" and set the D-A register to
"0016" so that no current flows in the resistors Rs and 2Rs.
Figure 1.18.3. D-A converter equivalent circuit
168
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
CRC Calculation Circuit
The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcomputer
uses a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC
code is set in a CRC data register each time one byte of data is transferred to a CRC input register after
writing an initial value into the CRC data register. Generation of CRC code for one byte of data is completed
in two machine cycles.
Figure 1.19.1 shows the block diagram of the CRC circuit. Figure 1.19.2 shows the CRC-related registers.
Figure 1.19.3 shows the calculation example using the CRC calculation circuit.
Data bus high-order bits
Data bus low-order bits
Eight low-order bits
Eight high-order bits
CRC data register (16)
(Addresses 03BD16, 03BC16
)
CRC code generating circuit
16
12
5
x
+ x + x + 1
CRC input register (8) (Address 03BE16
)
Figure 1.19.1. Block diagram of CRC circuit
CRC data register
(b15)
b7
(b8)
b0 b7
Symbol
CRCD
Address
03BD16, 03BC16
When reset
Indeterminate
b0
Values that
can be set
Function
R W
CRC calculation result output register
000016 to FFFF16
CRC input register
b7
b0
Symbol
CRCIN
Address
03BE16
When reset
Indeterminate
Values that
can be set
Function
R W
Data input register
0016 to FF16
Figure 1.19.2. CRC-related registers
169
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CRC
b15
b0
b0
CRC data register CRCD
[Addresses 03BD16, 03BC16
(1) Setting "000016
"
]
b7
CRC input register
2 cycles
CRCIN
[Address 03BE16
(2) Setting "0116
"
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[Addresses 03BD16, 03BC16
118916
]
The code resulting from sending "0116" in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,
16
12
5
16
(X + X + X + 1), becomes the remainder resulting from dividing (1000 0000) X by (1 0001 0000 0010 0001) in
conformity with the modulo-2 operation.
LSB
MSB
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
1 0001 0000 0010 0001
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
LSB
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
MSB
9
8
1
1
Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to "118916" in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation
circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.
b7
b0
CRC input register
CRCIN
[Address 03BE16
(3) Setting "2316
"
]
After CRC calculation is complete
b15
b0
CRC data register
Stores CRC code
CRCD
[Addresses 03BD16, 03BC16
0A4116
]
Figure 1.19.3. Calculation example using the CRC calculation circuit
170
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Module
The CAN (Controller Area Network) module for the M16C/6N group of microcomputers is a communication
controller implementing the CAN 2.0B protocol as defined in the BOSCH specification. The M16C/6N0
group contains two Full CAN modules and the M16C/6N1 group contains one Full CAN module which can
transmit and receive messages in both standard (11 bit) ID and extended (29 bit) ID formats.
Figure 1.20.1 shows a block diagram of the CAN module.
External CAN bus driver and receiver are required.
Data Bus
CANi Configuration
Register
CANi Control
Register
CANi Global Mask
Register
CANi Extended ID
Register
CANi Local Mask A
Register
CANi Message
Control
CANi Local Mask B
Register
Register 0 to 15
CTX
Message Box
slots 0 to 15
Protocol
Controller
Acceptance Filter
slots 0 to 15
Message ID
DLC
16 Bit Timer
Message Data
Time Stamp
CAN Time Stamp
Register
CR
X
Wake Up
Function
Interrupt
Generation
Function
CANiReceiveError
CountRegister
CANi RecSuc Int
CANi Status
Register
CANi Slot Status
CANi Interrupt
Control Register
CANiTransmitError
CountRegister
Register
CANi TrmSuc Int
CANi Error Int
CANi Wake Up Int
Data Bus
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1group.
Figure 1.20.1. Block diagram of the CAN module
CTx/CRx:
CAN I/O pins.
Protocol controller:
This controller handles the bus arbitration and the CAN protocol services, i.e. bit
timing, stuffing, error status etc.
Message box:
This memory block consists of 16 slots that can be configured either as transmitter
or receiver. Each slot contains an individual ID, data length code, a data field (8
bytes) and a time stamp.
Acceptance filter:
This block performs filtering operation for received messages. For the filtering
operation, the CANi global mask register, the CANi local mask A register, or the
CANi local mask B register is used.
16 bit timer:
Used for the time stamp function. When the received message is stored in the
message memory, the timer value is stored as a time stamp.
CANi wake up interrupt is generated by a message from the CAN bus.
Wake up function:
Interrupt generation function: The interrupt events are provided by the CAN module. CANi successful reception
interrupt, CANi successful transmission interrupt, CAN0/1 error interrupt, and
CAN0/1 wake up interrupt.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
171
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Registers Related to the CAN Modules
The CANi modules have the following registers, respectively.
(1) CAN message box
A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN.
• Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and
reception.
• A program can define whether a slot is defined as transmitter or receiver.
(2) Acceptance mask registers
A CAN module is equipped with 3 masks for the acceptance filter.
• CANi global mask register (6 bytes)
Configuration of the masking condition for acceptance filtering processing to slots 0 to 13
• CANi local mask A register (6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 14
• CANi local mask B register (6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 15
(3) CAN SFR Registers
• CANi message control register (8 bits X 16)
Control of transmission and reception of a corresponding slot
• CANi control register (16 bits)
Control of the CAN protocol
• CANi status register (16 bits)
Indication of the protocol status
• CANi slot status register (16 bits)
Indication of the status of contents of each slot
• CANi interrupt control register (16 bits)
Selection of "interrupt enabled or disabled" for each slot
• CANi extended ID register (16 bits)
Selection of ID format (standard or extended) for each slot
• CANi configuration register (16 bits)
Configuration of the bus timing
• CANi receive error count register (8 bits)
Indication of the error status of the CAN module in reception: the counter value is incremented or
decremented according to the error occurence.
• CANi transmit error count register (8 bits)
Indication of the error status of the CAN module in transmission: the counter value is incremented or
decremented according to the error occurence.
• CANi time stamp register (16 bits)
Indication of the value of the time stamp counter
• CANi acceptance filter support register
Decoding the received ID for use by the acceptance filter support unit
Explanation of each register is given below.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
172
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Message Box
Table 1.20.1 shows the memory mapping of the CANi message box.
It is possible to access to the message box in byte or word.
Mapping of the message contents differs from byte access to word access. Byte access or word access can
be selected by the MsgOrder bit of the CANi control register.
Table 1.20.1. Memory mapping of the CANi message box (n = 0 to 15: the number of the slot)
Address
Message content (Memory mapping)
Byte access (8 bits) Word access (16 bits)
SID10 to SID SID to SID
SID to SID
EID17 to EID14
EID13 to EID
EID to EID
CAN0
CAN1
006016 + n
•
16 + 0
026016 + n
026016 + n
026016 + n
026016 + n
026016 + n
026016 + n
026016 + n
026016 + n
•
16 + 0
16 + 1
16 + 2
16 + 3
16 + 4
16 + 5
16 + 6
16 + 7
6
5
0
006016 + n
006016 + n
006016 + n
006016 + n
006016 + n
006016 + n
006016 + n
•
16 + 1
16 + 2
16 + 3
16 + 4
16 + 5
16 + 6
16 + 7
•
5
0
SID10 to SID
EID13 to EID
6
6
•
•
•
•
•
•
6
EID17 to EID14
5
0
Data Length Code (DLC)
•
•
•
•
•
•
Data Length Code (DLC)
Data byte 0
EID5 to EID0
Data byte 1
Data byte 0
Data byte 1
006016 + n
006016 + n
•
•
16 + 13
16 + 14
026016 + n
026016 + n
•
•
16 + 13
16 + 14
Data byte 7
Data byte 6
Time stamp high order byte
Time stamp low order byte
Time stamp high order byte
006016 + n
•
16 + 15
026016 + n
•
16 + 15
Time stamp low order byte
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
173
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Figures 1.20.2 and 1.20.3 show the bit mapping in each slot in byte access and word access. The content
of each slot remains unchanged unless transmission or reception of a new message is performed.
Bit 7
Bit 0
SID6
SID10
SID4
SID9
SID3
EID17
SID8
SID2
SID7
SID1
SID5
SID0
EID16
EID15
EID14
EID11
EID5
EID9
EID3
DLC3
EID8
EID2
DLC2
EID7
EID1
DLC1
EID6
EID0
DLC0
EID13
EID12
EID10
EID4
Data Byte 0
Data Byte 1
Data Byte 7
Time Stamp high order byte
Time Stamp low order byte
CAN Data Frame:
Data Byte1
Data Byte7
SID10 to 6
SID5 to 0
EID17 to 14
EID13 to 6
EID5 to 0
DLC3 to 0
Data Byte0
is read, the value is the one written upon the transmission slot configuration.
Note: When
The value is "0" when read on the reception slot configuration.
Figure 1.20.2. Bit mapping in byte access
Bit 15
Bit 8 Bit 7
SID
Bit 0
SID10 SID
9
SID
8
SID
7
6
SID5
SID
4
SID
3
SID
2
8
SID
1
SID0
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID
EID EID EID EID DLC
Data Byte 1
9
EID
EID
7
1
EID6
EID5
EID4
3
2
1
0
3
DLC
2
DLC
DLC
0
Data Byte 0
Data Byte 2
Data Byte 4
Data Byte 6
Data Byte 3
Data Byte 5
Data Byte 7
Time Stamp high order byte
Time Stamp low order byte
CAN Data Frame:
Data Byte1
Data Byte7
SID10 to 6
SID5 to 0
EID17 to 14
EID13 to 6
EID5 to 0
DLC3 to 0
Data Byte0
is read, the value is the one written upon the transmission slot configuration.
Note: When
The value is "0" when read on the reception slot configuration.
Figure 1.20.3. Bit mapping in word access
174
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Acceptance Mask Registers
Figures 1.20.4 and 1.20.5 show the CANi global mask register, the CANi local mask A register, and the
CANi local mask B register, in which bit mapping in byte access and word access are shown.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Addresses
CAN0 CAN1 (Note)
Bit 7
Bit 0
016016
016116
016216
016316
016416
036016
036116
036216
036316
036416
SID10
SID
SID
9
3
SID
8
2
SID
7
1
SID
6
SID
5
4
SID
SID
SID
SID0
CANi global
mask register
EID17
EID16
EID15
EID14
EID13
EID12
EID12
EID12
EID11
EID10
EID
SID10
SID
EID
9
3
EID
8
2
EID
7
1
EID
6
0
EID5
4
EID
EID
EID
EID
016616
016716
016816
016916
036616
036716
036816
036916
SID
9
3
SID
8
2
SID
7
1
SID
6
0
SID5
4
SID
SID
SID
SID
CANi local
mask A register
EID17
EID16
EID15
EID14
EID13
EID11
EID10
EID
EID
9
3
EID
8
2
EID
7
1
EID
6
0
016A16 036A16
EID5
4
EID
EID
EID
EID
016C16 036C16
016D16 036D16
016E16 036E16
SID10
SID
SID
9
3
SID
8
2
SID
7
1
SID
6
0
SID5
4
SID
SID
SID
SID
CANi local
mask B register
EID17
EID16
EID15
EID14
016F16
017016
036F16
037016
EID13
EID11
EID
EID10
EID
EID
9
3
EID
8
2
EID
7
1
EID
6
0
5
4
EID
EID
EID
EID
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.4. Bit mapping of the mask registers in byte access
Addresses
Bit 15
Bit 8 Bit 7
SID
Bit 0 CAN0 / CAN1 (Note)
016016/036016
016216/036216
016416/036416
016616/036616
016816/036816
016A16/036A16
016C16/036C16
016E16/036E16
017016/037016
SID10 SID
9
SID
8
SID
7
6
SID
5
SID
4
SID
3
SID
EID
2
8
SID
1
7
SID
0
CANi global
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID
9
EID
EID
6
mask register
EID
EID
EID
5
5
5
EID
4
EID3
EID
SID
2
8
EID
1
7
EID
SID
0
6
SID10 SID
9
SID
SID5
SID
4
SID3
SID
EID
2
8
SID
1
7
SID
EID
0
6
CANi local
mask A register
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID
9
EID
EID
4
EID3
EID
SID
2
8
EID
1
7
EID
SID
0
6
SID10 SID
9
SID
SID5
SID
4
SID3
SID
EID
2
8
SID
1
7
SID
EID
0
6
CANi local
mask B register
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID
EID EID EID EID
9
EID
EID
4
3
2
1
0
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.5. Bit mapping of the mask registers in word access
175
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN SFR Registers
CANi Message Control Register j (j = 0 to 15)
Figure 1.20.6 shows the CANi message control register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi message control register j (i = 0, 1, j = 0 to 15)
b7
b6
b5
b4
b3
b2
b1
b0
Address
When reset
Symbol
C0MCTLj (j = 0 to 15)
C1MCTLj (j = 0 to 15) (Note 1)
020016 to 020F16
022016 to 022F16
0016
0016
Bit symbol
NewData
Bit name
Successful
Function
R
W
When set to reception slot
0: The content of the slot is read or
still under processing by the CPU.
1: The CAN module has stored new data in the
slot.
reception flag
SentData
InvalData
Successful
transmission flag
When set to transmission slot
0: Transmission is not started or completed yet.
1: Transmission is successfully completed.
"Under reception"
flag
When set to reception slot
0: The message is valid.
1: The message is invalid.
(The message is being updated.).
When set to transmission slot
TrmActive
MsgLost
"Under
transmission" flag
0: Waiting for bus idle or completion of
arbitration.
1: Transmitting
Overwrite flag
When set to reception slot
0: No message has been overwritten in this slot.
1: This slot already contained a message,
but it has been overwritten by a new one.
RemActive
RspLock
0: Data frame transmission/reception status
1: Remote frame automatic transfer status
Remote frame
transmission/
reception status
flag (Note 3)
Transmission/
reception auto
response lock
mode select bit
When set to reception remote frame slot
0: After a remote frame is received, it will be
answered automatically.
1: After a remote frame is received, no transmis-
sion will be started as long as this bit is set to "1".
(Not responding)
Remote
Remote frame
corresponding
slot select bit
0: Slot not corresponding to remote frame
1: Slot corresponding to remote frame
RecReq
(Note 4)
Reception slot
request bit
0: Not reception slot
1: Reception slot
TrmReq
(Note 4)
Transmission
slot
request bit
0: Not transmission slot
1: Transmission slot
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: As for write, only writing "0" is possible. The value of each bit is written when the
CAN module enters the respective state.
Note 3: In Basic CAN mode, they serve as data format identification flag.
Refer to the section of Basic CAN mode for more details.
Note 4: One slot cannot be defined as reception slot and transmission slot at the same
time.
Figure 1.20.6. CANi message control register j
176
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Control Register
Figure 1.20.7 shows the CANi control register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi control register (i = 0, 1)
Symbol
Address
021016
When reset
b7
b6
b5
b4
b3
b2
b1
b0
C0CTLR
X0000001
X0000001
2
C1CTLR (Note 1)
2
023016
Bit symbol
Bit name
Function
R
W
Reset
Full CAN module
reset bit
0: Operation mode
1: Reset/initialization mode
LoopBack
MsgOrder
Loop back mode
select bit
0: Normal operation mode
1: Loop back mode
Message order
select bit
0: Word access
1: Byte access
BasicCAN
BusErrEn
Sleep
Basic CAN mode
select bit
0: Normal operation mode
1: Basic CAN mode
Bus error interrupt
enable bit
0: Bus error interrupt disabled
1: Bus error interrupt enabled
Sleep mode
select bit
0: Sleep mode disabled
1: Sleep mode enabled; clock supply stopped
0: I/O port function
PortEn
CAN port enable bit
1: CTx/CRx function (Note 2)
Nothing is assigned. Write "0" in case of write. The value is indeterminate when read.
Note 1: The C1CTLR register (addresses 023116, 023016) has to be set to "002016" for
M16C/6N1 group.
Note 2: CTx/CRx function regardless of configuration of PD7 and PD9 registers.
(b15)
b7
(b8)
b0
b6
b5
b4
b3
b2
b1
Symbol
Address
021116
When reset
XX0X0000
XX0X0000
2
C0CTLR
2
C1CTLR (Note 1) 023116
Bit symbol
Bit name
Function
R
W
b1 b0
TSPreScale
Bit1, Bit0
Time stamp
prescaler
0 0: Period of 1 bit time
0 1: Period of 1/2 bit time
1 0: Period of 1/4 bit time
1 1: Period of 1/8 bit time
TSReset
0: Normal operation mode
Time stamp counter
(Note 2)
1: Compulsory reset of the time stamp counter
reset bit
RetBusOff
Return from bus off
command bit
(Note 3)
0: Normal operation mode
1: Compulsory return from bus off
Nothing is assigned. Write "0" in case of write. The value is indeterminate when read.
RXOnly
0: Normal operation mode
1: Listen-only mode
Listen-only mode
select bit
Nothing is assigned. Write "0" in case of write. The value is indeterminate when read.
Note 1: The C1CTLR register (addresses 023116, 023016) has to be set to "002016" for M16C/6N1
group.
Note 2: When the TSReset bit is set to "1", the CiTSR register gets cleared to "000016".
After this, the bit is automatically cleared to "0".
Note 3: When the RetBusOff bit is set to "1", the CiRECR register and the CiTECR register gets
cleared to "0016". After this, the bit is automatically cleared to "0".
Figure 1.20.7. CANi control register
177
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Status Register
Figure 1.20.8 shows the CANi status register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi status register (i =0, 1)
Symbol
Address
021216
023216
When reset
b7
b6
b5
b4
b3
b2
b1
b0
C0STR
0016
0016
C1STR (Note)
Bit symbol
MBox
Bit name
Function
R
W
Active slot bits
b3 b2 b1 b0
0 0 0 0 : Slot 0
0 0 0 1 : Slot 1
0 0 1 0 : Slot 2
...
1 1 1 0 : Slot 14
1 1 1 1 : Slot 15
TrmSucc
RecSucc
Successful
transmission flag
No [successful] transmission
0:
1:
The CAN module has transmitted a message
successfully.
0: No [successful] reception
1: CAN module received a message
successfully.
Successful
reception flag
TrmState
RecState
Transmission flag
(Transmitter)
0: CAN module is idle or receiver.
1: CAN module is transmitter.
0: CAN module is idle or transmitter.
1: CAN module is receiver.
Reception flag
(Receiver)
Note: Channel CAN1 is not available for M16C/6N1 group.
(b15)
b7
(b8)
b0
Symbol
Address
021316
023316
When reset
b6
b5
b4
b3
b2
b1
C0STR
X0000001
X0000001
2
2
C1STR (Note)
Bit symbol
Bit name
Function
R
W
0: Operation mode
1: Reset mode
State_Reset Reset state flag
State_
LoopBack
Loop back state flag 0: Normal operation mode
1: Loop back mode
State_
MsgOrder
Message order
state flag
0: Word access
1: Byte access
0:
1: BasicCAN mode
No error has occurred.
0:
Normal operation mode
State_
BasicCAN
Basic CAN mode
state flag
State_
BusError
Bus error
state flag
1: A CAN bus error has occurred.
0: The CAN module is not in error passive state.
1: The CAN module is in error passive state.
State_
ErrPass
Error passive
state flag
0:
1:
The CAN module is not in error bus off state.
The CAN module is in error bus off state.
State_
BusOff
Error bus off
state flag
Nothing is assigned.
Write "0" in case of write. The value is indeterminate when read.
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.8. CANi status register
178
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Slot Status Register
Figure 1.20.9 shows the CANi slot status register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi slot status register (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
When reset
C0SSTR
C1SSTR
021516, 021416
023516, 023416
000016
000016
(Note)
Values
R
W
Function
Slot status bits
0: Reception slot
The message has been read.
Each bit corresponds to the slot with the
same number.
Transmission slot
Transmission is not completed.
1: Reception slot
The message has not been read.
Transmission slot
Transmission is completed.
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.9. CANi slot status register
179
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Interrupt Control Register
Figure 1.20.10 shows the CANi interrupt control register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi interrupt control register (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0ICR
Address
When reset
021716, 021616
000016
000016
C1ICR (Note 1) 023716, 023616
Function
Values (Note 2)
0: Interrupt disabled
1: Interrupt enabled
R
W
Interrupt enable bits:
Each bit corresponds with a slot with the same
number.
Enabled/disabled of successful transmission inter-
rupt or successful reception interrupt can be selected.
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: These bits can not be set in CAN reset/initialization and CAN sleep modes of the CAN module.
Figure 1.20.10. CANi interrupt control register
CANi Extended ID Register
Figure 1.20.11 shows the CANi extended ID register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi extended ID register (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0IDR
Address
When reset
000016
021916, 021816
C1IDR (Note 1) 023916, 023816
000016
Function
Values (Note 2)
R
W
0: Standard ID
1: Extended ID
Extended ID bits:
Each bit corresponds with a slot with the same
number.
Selection of the ID format that each slot handles.
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: These bits can not be set in CAN reset/initialization and CAN sleep modes of the CAN module.
Figure 1.20.11. CANi extended ID register
180
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Configuration Register
Figure 1.20.12 shows the CANi configuration register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi configuration register (i = 0, 1)
Symbol
Address
021A16
When reset
b7
b6
b5
b4
b3
b2
b1
b0
C0CONR
Indeterminate
Indeterminate
C1CONR (Note 1) 023A16
Bit symbol
BRP
Bit name
Function
(Note 2)
R
W
b3 b2 b1 b0
Prescaler division
ratio select bits
0 0 0 0 : fCAN/1
0 0 0 1 : fCAN/2
0 0 1 0 : fCAN/3
1 1 1 0 : fCAN/15
1 1 1 1 : fCAN/16
SAM
PTS
Sampling control
bit
0 : One time sampling
1 : Three times sampling
b7 b6 b5
Propagation time
segment control bits
0 0 0 : 1Tq
0 0 1 : 2Tq
0 1 0 : 2Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits
(i = 0, 1, 2, 3, 4, 5, 6).
(b15)
b7
(b8)
b0
b6
b5
b4
b3
b2
b1
Symbol
Address
021B16
023B16
When reset
C0CONR
Indeterminate
Indeterminate
C1CONR (Note)
Bit symbol
PBS1
Bit name
Function
R
W
b2 b1b0
Phase buffer
segment 1
control bits
0 0 0 : Inhibited
0 0 1 : 2Tq
0 1 0 : 3Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
b5 b4 b3
PBS2
SJW
Phase buffer
segment 2
control bits
0 0 0 : Inhibited
0 0 1 : 2Tq
0 1 0 : 3Tq
1 1 0 : 7Tq
1 1 1 : 8Tq
b7 b6
Resynchronization
jump width
control bits
0 0 : 1Tq
0 1 : 2Tq
1 0 : 3Tq
1 1 : 4Tq
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.12. CANi configuration register
181
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Receive Error Count Register
Figure 1.20.13 shows the CANi receive error count register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi receive error count register (i = 0, 1)
b7
b0
Symbol
Address
021C16
When reset
C0RECR
0016
0016
C1RECR (Note 1) 023C16
Range of the value
Function
R
W
Reception error counting function
0016 to FF16 (Note 2)
The value is incremented or decremented
according to the CAN module’s error status.
Note 1: Channel CAN1 is not available for M16C/6N1 group.
Note 2: The value is indeterminate in bus off state.
Figure 1.20.13. CANi receive error count register
CANi Transmit Error Count Register
Figure 1.20.14 shows the CANi transmit error count register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi transmit error count register (i = 0, 1)
b7
b0
Symbol
Address
021D16
023D16
When reset
0016
0016
C0TECR
C1TECR (Note)
R
W
Function
Range of the value
0016 to FF16
Transmission error counting function
The value is incremented or decremented
according to the CAN module’s error status.
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.14. CANi transmit error count register
182
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CANi Time Stamp Register
Figure 1.20.15 shows the CANi time stamp register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi time stamp register (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
When reset
C0TSR
021F16, 021E16
023F16, 023E16
000016
000016
C1TSR (Note)
Function
Range of the value
000016 to FFFF16
R
W
Time stamp function
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.15. CANi time stamp register
CANi Acceptance Filter Support Register
Figure 1.20.16 shows the CANi acceptance filter support register.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
CANi acceptance filter support register (i = 0, 1)
(b15)
b7
(b8)
b0
b0
b7
Symbol
Address
When reset
Indeterminate
Indeterminate
024316
024516
C0AFS
, 024216
, 024416
C1AFS (Note)
Values
R
W
Function
Write the content equivalent to the standard frame
ID of the received message.
Standard frame ID
The value is "converted standard ID" when read.
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.16. CANi acceptance filter support register
183
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Operational Modes
The CAN module has the following three operational modes.
• CAN Reset/Initialization Mode
• CAN Sleep Mode
• CAN Operation Mode
Figure 1.20.17 shows transition between operational modes.
MCU Reset
Reset = "0"
Reset/initialization
mode
(State-Reset = "1")
Operation mode
(State-Reset = "0")
Reset = "1"
Bus off state
(Bus off = "1")
Reset = "1"
Sleep mode
Figure 1.20.17. Transition between operational modes
CAN Reset/Initialization Mode
The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit of the CANi
control register. It can be observed by reading the State-Reset bit of the CANi status register. Entering the
CAN reset/initialization mode initiates the following functions by the module:
• Suspend all communication functions. When the CAN reset/initialization mode is activated during an
ongoing transmission in operation mode, the module suspends the mode transition until completion
of the transmission (successful, arbitration loss, or error detection) and then sets the State-Reset bit.
• Initialization of CANi extended ID, CANi message control, CANi interrupt control, CANi status, CANi
time stamp, CANi receive error count and CANi transmit error count registers to their reset values. All
these registers are locked to prevent CPU modification.
• The CANi configuration and CANi control registers and the message box retain their contents and
are available for CPU access.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
184
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Operation Mode
The CAN operation mode is activated by clearing the Reset bit of the CANi control register. Entering the
operation mode initiates the following functions by the module:
• The module's communication functions are released and it becomes an active node on the network
and may transmit and receive CAN messages.
• Release the internal fault confinement logic including receive and transmit error counters. The mod-
ule may leave the CAN operation mode depending on the error counts.
Within the CAN operation mode the module may be in three different sub modes, depending on which
type of communication functions are performed:
• Module idle: The modules receive and transmit sections are inactive.
• Module receives: The module receives a CAN message sent by another node.
• Module transmits: The module transmits a CAN message. The module may receive its own message
simultaneously when the loopback function is enabled.
Figure 1.20.18 shows sub modes of the CAN operation mode.
Module idle
TrmState = "0"
RecState = "0"
Start
transmission
Detect
an SOF
Finish
transmission
Finish
reception
Module transmits
Module receives
TrmState = "1"
RecState = "0"
TrmState = "0"
RecState = "1"
Lost in arbitration
Figure 1.20.18. Sub modes of the CAN operation mode
CAN Sleep Mode
The CAN sleep mode is activated by setting the Sleep bit of the CANi control register. It should never be
activated from the CAN operation mode but only via the CAN reset/initialization mode. Entering the CAN
sleep mode instantly stops the modules clock supply and thereby reduces power dissipation.
Bus off State
The bus off state is entered according to the fault confinement rules of the CAN specification. It can be
quit instantly to error active state by setting the RetBusOff bit of the CANi control register. This does not
alter any CAN registers, except CANi receive error count and CANi transmit error count registers.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
185
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Configuration of the CAN Module System Clock
The M16C/6N group has a CAN module system clock select circuit dedicated to each channel.
Configuration of the CAN module system clock can be done through manipulating the CAN0/1 clock select register
(address 025F16) and the BRP bits of the CANi configuration registers (addresses 021A16 and 023A16).
For the CAN0/1 clock select register, refer to the section of the clock generating circuit.
Figure 1.20.19 shows a block diagram of the clock generating circuit of the CAN module system.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
f
P:
CAN
:
CAN module system clock
The value written in the BRP bit of the CANi configuration register
f
CANCLK
:
CAN communication clock
f
CANCLK = fCAN/2(P + 1)
XIN/1
XIN/2
XIN/4
XIN/8
XIN/16
Prescaler
XIN
Divider
Value: 1, 2, 4, 8, 16
f
CAN
Prescaler
for baud rate
f
CANCLK = fCAN/2(P + 1)
1/2
Division by (P + 1)
(P = 0 to 15)
CAN 0/1 clock select register
(Address 025F16
)
CAN module
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.19. Block diagram of the CAN module system clock generating circuit
CAN Bus Timing Control
Bit Timing Configuration
The bit time consists of the following four segments:
• Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum of
delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than expected,
the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the bit
falls earlier than expected, the segment can become shorter by the maximum of the value defined in
SJW.
Figure 1.20.20 shows the bit timing.
Bit time
SS
PTS
PBS1
PBS2
SJW
Sampling point
SJW
The range of each segment: Bit time = 8 to 25Tq
SS = 1Tq
Configuration of PBS1 and PBS2: PBS1 ≥ PBS2
PBS1 ≥ SJW
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4
SJW = 1Tq to 4Tq
Figure 1.20.20. Bit timing
186
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Baud Rate
Baud rate depends on XIN, the division value of the CAN module system clock, the division value of the
prescaler for baud rate, and the number of Tq of one bit.
Table 1.20.2 shows the examples of baud rate.
Table 1.20.2. Examples of baud rate
Baud rate
1Mbps
16MHz
8Tq (1)
10MHz
8MHz
500kbps
8Tq (2)
16Tq (1)
10Tq (1)
8Tq (1)
125kbps
83.3kbps
33.3kbps
8Tq (8)
16Tq (4)
10Tq (4)
20Tq (2)
8Tq (4)
16Tq (2)
8Tq (12)
18Tq (6)
8Tq (30)
10Tq (6)
20Tq (3)
10Tq (15)
8Tq (6)
16Tq (3)
8Tq (15)
16Tq (15)
Note: The number in ( ) indicates a value of "fCAN division value" multiplied by "division value of the
prescaler for baud rate".
Calculation of baud rate
XIN
2 X "fCAN division value (Note 1)" X "division value of prescaler for baud rate (Note 2)" X "number of Tq of one bit"
Note 1: fCAN division value = 1, 2, 4, 8, 16
fCAN division value: a value selected in the CAN0/1 clock select register
Note 2: Division value of prescaler for baud rate = P + 1 (P: 0 to 15)
P: a value selected in the BRP bit of the CANi configuration register
187
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Acceptance Filtering Function and Masking Function
These functions serve the users to select and receive a facultative message. The CANi global mask regis-
ter, the CANi local mask A register, and the CANi local mask B register can perform masking to the stan-
dard ID and the extended ID of 29 bits. The CANi global mask register corresponds to slots 0 to 13, the
CANi local mask A register corresponds to slot 14, and the CANi local mask B register corresponds to slot
15. The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in the
corresponding slot of the extended ID register upon acceptance filtering operation. When the masking
function is employed, it is possible to receive a certain range of IDs.
Figure 1.20.21 shows correspondence of the mask registers and slots, Figure 1.20.22 shows the accep-
tance function.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Slot #0
Slot #1
Slot #2
Slot #3
Slot #4
Slot #5
Slot #6
CANi global mask register
Slot #7
Slot #8
Slot #9
Slot #10
Slot #11
Slot #12
Slot #13
Slot #14
Slot #15
CANi local mask A register
CANi local mask B register
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.21. Correspondence of the mask registers to slots
Mask Bit Values
ID stored in
the slot
The value of the
mask register
ID of the
received message
0: ID (to which the received message
corresponds) match is handled as
"Don’t care".
1: ID (to which the received message
corresponds) match is checked.
Acceptance
Signal
Acceptance judge signal
0: The CAN module ignores the
current incoming message.
(Not stored in any slot)
1: The CAN module stores the
current incoming message in
a slot of which ID matches.
Figure 1.20.22. Acceptance function
When using the acceptance function, note the following points.
(1) When one ID is defined in two slots, the one with a smaller number alone is valid.
(2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15
receive all IDs which are not stored into slots 0 to 13.
188
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Acceptance Filter Support Unit (ASU)
The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search.
The IDs to receive are registered in the data table; a received ID is stored in the CANi acceptance filter
support register, and table search is performed with a decoded received ID. The acceptance filter support
unit can be used for the IDs of the standard frame only.
The acceptance filter support unit is valid in the following cases.
• When the ID to receive cannot be masked by the acceptance filter.
(Example) IDs to receive: 07816, 08716, 11116
• When there are too many IDs to receive; it would take too much time to filter them by software.
Figure 1.20.23 shows the write and read of CANi acceptance filter support register in word access.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
Addresses
CAN0/CAN1
Bit 15
Bit 8 Bit 7
SID
Bit 0
SID
(Note)
When write
SID10 SID
9
SID
8
SID7
6
SID5
SID
4
SID3
SID
2
SID1
0
24216/24416
3/8 Decoder
Bit 15
Bit 8 Bit 7
SID10 SID
Bit 0
SID
When read
9
SID8
SID
7
SID6
SID
5
SID4
3
24216/24416
Note: Channel CAN1 is not available for M16C/6N1 group.
Figure 1.20.23. Write/read of acceptance filter support register in word access
189
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Basic CAN Mode
When the BasicCAN bit of the CANi control register is set to "1", slots 14 and 15 correspond to Basic CAN
mode. When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are
stored in slots 14 and 15 alternately.
Figure 1.20.24 shows the operation of slots 14 and 15 in Basic CAN mode.
Empty
Msg n
(Msg n lost)
Msg n+2
Slot 14
Slot 15
(Msg n)
Locked
Locked (empty)
Locked (empty)
Locked (Msg n+1)
Msg n + 1
Msg n
Msg n+1
Msg n+2
Figure 1.20.24. Operation of slots 14 and 15 in Basic CAN mode
When configuring Basic CAN mode, note the following points.
(1) Selection of Basic CAN mode has to be done in reset/initialization mode.
(2) Select the same ID for slots 14 and 15. Also, configuration of the CANi local mask A register and that
of the local mask B register has to be the same.
(3) Define slots 14 and 15 as reception slot only.
(4) There is no protection available against message overwrite. A message can be overwritten by a new
message.
(5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode.
Concerning the CANi message control registers and communication environment configuration, Basic CAN
mode is different from normal CAN operation mode in the following points:
(1) In normal CAN operation mode each slot can handle either data frame or remote frame, while in Basic
CAN mode each slot can handle both frames. Namely, in Basic CAN mode slots 14 and 15 can
receive both data frame and remote frame.
(2) For the above (1), the data format of a received message should be identified. In Basic CAN mode, the
data is judged by the RemActive bit of the CANi message control register. The bit is cleared to "0"
when the corresponding slot has received a data frame; set to "1" when the slot has received a remote
frame.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
190
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Return from Bus off Function
When the protocol controller enters bus off state, it is possible to make it compulsorily return from bus off
state by the return from bus off function of the CANi control register. At this time, the error state changes
from bus off state to error active state. Implementation of this function initializes the protocol controller.
However, registers of the CAN module such as CANi configuration register and the content of each slot are
not initialized.
Time Stamp Counter and Time Stamp Function
When the time stamp register is read, the value of the time stamp counter at the moment is read. The period
of the time stamp counter reference clock is the same as that of 1 bit time that is configured by the CANi
configuration register. The time stamp counter functions as a free run counter.
1/1, 1/2, 1/4, and 1/8 can be selected for the time stamp counter reference clock by configuration of the
TSPreScale bits 1 and 0 of the CANi control register.
The time stamp counter is equipped with a register that captures the counter value when the protocol
controller regards it as a successful reception. The captured value is stored when a time stamp value is
stored in a reception slot.
Listen-Only Mode
When the RXOnly bit of the CANi control register is set to "1", the module enters listen-only mode.
In listen-only mode, no transmission -- data frames, error frames, and ACK response -- is performed to bus.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
191
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Reception and Transmission
Configuration of CAN Reception and Transmission Mode
Table 1.20.3 shows configuration of CAN reception and transmission mode.
Table 1.20.3. Configuration of CAN reception and transmission mode
RecReq
0
TrmReq
0
Remote RspLock
Communication mode of the slot
Communication environment configuration mode: configure the commu-
nication mode of the slot.
0
1
1
0
0
1
0
0
Configured as a reception slot for a data frame.
Configured as a transmission slot for a remote frame. (At this time the
RemActive bit is "1".)
After completion of transmission, this functions as a reception slot for a
data frame. (At this time the RemActive bit is "0".)
However, when an ID that matches on the CAN bus is detected before
remote frame transmission, this immediately functions as a reception
slot for a data frame.
1
0
0
1
0
1
0
Configured as a transmission slot for a data frame.
1/0
Configured as a reception slot for a remote frame. (At this time the
RemActive bit is "1".)
After completion of reception, this functions as a transmission slot for a
data frame. (At this time the RemActive bit is "0".)
However, transmission does not start as long as RspLock bit remains "1";
thus no automatic remote frame response.
Response (transmission) starts when RspLock bit is cleared to "0".
When configuring a slot as a reception slot, note the following points.
(1) Before configuring a slot as a reception slot, be sure to clear the CANi message control register.
(2) A received message is stored in a slot that matches the condition first according to the result of
reception mode configuration and acceptance filtering operation. Upon deciding in which slot to
store, the smaller the number of the slot is, the higher priority it has.
(3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches, the
CAN module never receives the transmitted data. In loop back mode, however, the CAN module
receives back the transmitted data. In this case, the module does not return ACK.
When configuring a slot as a transmission slot, note the following points.
(1) Before configuring a slot as a transmission slot, be sure to clear the CANi message control register.
(2) Clear the TrmReq bit without fail before rewriting a transmission slot.
(3) A transmission slot cannot be rewritten when the TrmActive bit is "1".
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
192
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Reception
Figure 1.20.25 shows the behavior of the module when receiving two consecutive CAN messages, that fit
into the slot of the shown CANi message a control register and leads to losing/overwriting of the first
message.
SOF
SOF
ACK
EOF
IF
ACK
EOF
IF
CANbus
RecReq
1)
2)
InvalData
NewData
MsgLost
Succ.Rec Int.
RecState
RecSucc
Mbox
4)
5)
3)
Receive slot No.
Figure 1.20.25. Timing of receive data frame sequence
1) On monitoring a SOF on the CAN bus the RecState bit becomes active immediately, given the module
has no transmission pending (see section "Transmission" below).
2) After successful reception of the message the NewData bit of the receiving slot becomes active. The
InvalData bit becomes active at the same time and becomes inactive again after the complete mes-
sage was transferred to the slot.
3) When the bit in the CANi interrupt control register of the receiving slot is active the receive successful
interrupt is requested and the CANi status register changes. It shows the slot number where the
message was stored and the RecSucc bit is active.
4) After reading out the message out of the slot the CPU should clear the NewData bit to signal this to the
module.
5) If the NewData bit is not cleared by the CPU and the Receive request for the slot is not disabled
before the next successful reception of a CAN message that is fitting in this slot the MsgLost bit
becomes acitive. The new received message is transferred to the slot. The interrupt request and
change of the status register is same as in 3).
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
193
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
Transmission
SOF
SOF
ACK
EOF
IF
CTx
TrmReq
TrmActive
SentData
Succ. Xmit Int.
TrmState
TrmSucc
Mbox
B
A
Transmission slot No.
Figure 1.20.26. Timing of transmit sequence
1) If one or more of the slots of a module has a request for transmission, the module attempts to start the
transmission at the next possible time (depending on the bus condition).
2) The TrmActive bit of the lowest slot with transmit request is set. Also the TrmState bit is set. If the
arbitration is lost against another CAN node both bits are cleared again (A).
3a) When the arbitration was won, but the transmission was not successful, the module will attempt to re-
transmit.
3b) When the arbitration was won and the transmission has been successful the SentData bit is set
together with TrmSucc bit and the transmit successfull interrupt is activated, if the according bit in the
CANi interrupt control register is active. The number of the slot that was transmitted can be found in
Mbox bit.
4) After a successful transmission the module will not attempt to send the slot again until it is reactivated.
To reactivate a slot for transmission, first the TrmReq bit has to be cleared. Then the SentData bit can
be cleared and the TrmReq bit set again (B). Note that the SentData bit is locked and cannot be
cleared as long as TrmReq bit is active.
Note: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
194
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN Module
CAN Interrupts
The CAN module provides the following CAN interrupts. (Note 1)
• CAN0 Successful Reception Interrupt
• CAN0 Successful Transmission Interrupt
• CAN1 Successful Reception Interrupt
• CAN1 Successful Transmission Interrupt
• CAN0/1 Error Interrupt
Error Passive State
Error BusOff State
Bus Error (this feature can be disabled separately)
• CAN0/1 Wake Up Interrupt
When the CPU detects a successful reception/transmission interrupt, the CANi status register must
be read to determine which slot has issued the interrupt. (Note 2)
Note 1: M16C/6N1 group provides 4 interrupts. Interrupts relating to channel CAN1 are invalid for
M16C/6N1 group.
Note 2: i = 0, 1. Channel CAN1 is not available for M16C/6N1 group.
195
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Programmable I/O Port
There are 87 programmable I/O ports: P0 to P10 (excluding P85). Each port can be set independently for
input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P71 and
P91 are Nch open drain ports and have no built-in pull-up resistance. P85 is an input-only port and has no
built-in pull-up resistance.
Figures 1.21.1 to 1.21.4 show the programmable I/O ports. Figure 1.21.5 shows the input pins.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input
mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-
verter), they function as outputs regardless of the contents of the direction registers. When the pins are to
be used as the outputs for the D-A converter, do not set the direction registers to output mode. See the
descriptions of the respective functions for how to set up the built-in peripheral devices.
(1) Direction registers
Figure 1.21.6 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-
ters corresponds one for one to each I/O pin. (Note)
In memory expansion and microprocessor mode, the contents of corresponding direction register of pins
_______
_______ _____ ________ ______ ________ _______
________ __________ __________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
Note: There is no direction register bit for P85.
(2) Port registers
Figure 1.21.7 shows the port registers.
These registers are used to write and read data for input and output to and from an external device. A
port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit
in port registers corresponds one for one to each I/O pin.
In memory expansion and microprocessor mode, the contents of corresponding direction register of pins
_______
_______ _____ ________ ______ ________ _______
________ __________ __________
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.
(3) Pull-up control registers
Figure 1.21.8 shows the pull-up control registers.
The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports
are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is
set for input.
However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3,
P40 to P43, and P5 is invalid.
The contents of register can be changed, but the pull-up resistance is not connected.
196
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
(4) Port control register
Figure 1.21.9 shows the port control register.
The bit 0 of port control register is used to read port P1 as follows:
0 : When port P1 is input port, port input level is read.
When port P1 is output port , the contents of port P1 register is read.
1 : The contents of port P1 register is read though port P1 is input/output port.
This register is valid in the following:
• External bus width is 8 bits in microprocessor mode or memory expansion mode.
• Port P1 can be used as a port in multiplexed bus for the entire space.
197
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P00
to P0
7
, P2
0
to P27,
Data bus
Port latch
(Note)
Analog input
Pull-up selection
Direction register
P3
P5
0
0
to P3
7
, P4
0
6
to P47,
to P54, P5
Data bus
Port latch
(Note)
Pull-up selection
Direction register
P10 to P14
Port P1 control register
Port latch
Data bus
(Note)
Pull-up selection
Direction register
P15 to P17
Port P1 control register
Port latch
Data bus
(Note)
Input to respective peripheral functions
Pull-up selection
Direction register
P57
P72
P90
, P6
to P7
, P9
0
, P6
1
, P6
4, P65,
"1"
6
, P8
0
, P81,
2
Output
Data bus
Port latch
(Note)
Input to respective peripheral functions
Note: Symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 1.21.1. Programmable I/O ports (1)
198
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P82 to P84
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P5
5, P62, P66, P77,
P9
7
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P63, P67
"1"
Output
Nch
Data bus
Port latch
(Note 1)
Note 1: P63 and P67 can be N-channel open drain only when used as
T
X
D0/T
X
D1 pin.
Pull-up selection
Direction register
P70
"1"
Output
Nch
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Note 2: P70 can be N-channel open drain only when used as T
X
D2 pin. If used as
input port it is only usable as CMOS port.
P85
Data bus
NMI interrupt input
(Note 1)
Direction register
"1"
P71, P91
Output
Port latch
(Note 2)
Input to respective peripheral functions
Note 1:
Symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2:
Symbolizes a parasitic diode.
Figure 1.21.2. Programmable I/O ports (2)
199
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P100 to P103
(inside dotted-line not included)
P104 to P107
(inside dotted-line included)
Data bus
Port latch
(Note 1)
Analog input
Input to respective peripheral functions
Pull-up selection
D-A output enabled
Direction register
P93, P94
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Analog output
D-A output enabled
Pull-up selection
Direction register
"1"
P96
Output
Port latch
Data bus
(Note 1)
Analog input
Pull-up selection
Direction register
"1"
P95
Output
Data bus
Port latch
(Note 1)
Input to respective peripheral functions
Analog input
(Note 2)
Note 1:
Symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Note 2: When selecting external op-amp connection mode, P9
functions as analog-output pin.
5/ANXE0 pin
Figure 1.21.3. Programmable I/O ports (3)
200
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up selection
Direction register
P87
Data bus
Port latch
(Note)
fc
Rf
Pull-up selection
Direction register
Rd
P8
6
"1"
Output
Data bus
Port latch
(Note)
Note:
Symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 1.21.4. Programmable I/O ports (4)
BYTE
BYTE signal input
(Note)
CNVSS
CNVSS signal input
(Note)
RESET
RESET signal input
(Note)
Note:
Symbolizes a parasitic diode.
Do not apply a voltage higher than Vcc to each port.
Figure 1.21.5. Input pins
201
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi direction register (Note1, 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
When reset
PDi (i = 0 to 10,
03E216, 03E316, 03E616, 03E716, 03EA16
03EB16, 03EE16, 03EF16, 03F316, 03F616
0016
except 8)
Bit symbol
Bit name
Function
R W
PDi_0
Port Pi
0
direction register
0 : Input mode
(Functions as an input port)
1 : Output mode
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
Port Pi
1
2
direction register
direction register
direction register
direction register
direction register
direction register
Port Pi
(Functions as an output port)
Port Pi
Port Pi
3
(i = 0 to 10 except 8)
4
Port Pi
Port Pi
Port Pi
5
6
7
PDi_7
direction register
Note 1: Set bit 2 of protect register (address 000A16) to "1" before rewriting
to the port P7 and P9 direction register.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi register of pins A0 to A19, D0 to D15, CS0 to
CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and
BCLK cannot be modified.
Port P8 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F216
When reset
00X00000
2
Bit symbol
PD8_0
Bit name
Function
0 : Input mode
(Functions as an input port)
1 : Output mode
R W
Port P8
Port P8
Port P8
0
direction register
direction register
direction register
direction register
direction register
PD8_1
PD8_2
PD8_3
PD8_4
1
2
(Functions as an output port)
Port P8
3
4
Port P8
Nothing is assigned.
This bit can either be set nor reset. When read, its content is indeterminate.
0 : Input mode
(Functions as an input port)
1 : Output mode
PD8_6
PD8_7
Port P8
6
7
direction register
direction register
Port P8
(Functions as an output port)
Figure 1.21.6. Direction register
202
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port Pi register (Note1, 2)
Symbol
Pi (i = 0 to 10,
Address
When reset
Indeterminate
Indeterminate
b7 b6 b5 b4 b3 b2 b1 b0
03E016, 03E116, 03E416, 03E516, 03E816
03E916, 03EC16, 03ED16, 03F116, 03F416
except 8)
Bit symbol
Bit name
register
register
register
register
register
Function
R W
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Port Pi
0
1
2
3
4
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : "L" level data
Port Pi
Port Pi
Port Pi
Port Pi
1 : "H" level data
(i = 0 to 10 except 8)
Pi_5
Pi_6
Pi_7
Port Pi
Port Pi
Port Pi
5
6
7
register
register
register
Note 1: Since P7
impedance.
Note 2: In memory expansion and microprocessor mode, the contents of
corresponding port Pi register of pins A to A19, D to D15, CS0 to CS3,
0
and P9
1
are N-channel open drain ports, the data is high-
0
0
RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA, and BCLK cannot
be modified.
Port P8 register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F016
When reset
Indeterminate
Bit symbol
P8_0
Bit name
Function
R W
Port P8
0
register
register
register
register
register
register
register
register
Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P85)
0 : "L" level data
1 : "H" level data
P8_1
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
Port P8
1
2
3
4
5
6
7
P8_2
P8_3
P8_4
P8_5
P8_6
P8_7
Figure 1.21.7. Port register
203
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Pull-up control register 0 (Note)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FC16
When reset
0016
Bit symbol
PU00
Bit name
Function
R W
P0
P0
P1
P1
P2
P2
P3
P3
0
to P0
3
pull-up select bit
The corresponding port is
pulled high with a pull-up resistor
0 : Not pulled high
7 pull-up select bit
3 pull-up select bit
PU01
PU02
PU03
PU04
PU05
PU06
PU07
4
0
4
0
4
0
4
to P0
to P1
to P1
to P2
to P2
to P3
to P3
1 : Pulled high
7
pull-up select bit
3 pull-up select bit
7 pull-up select bit
3
pull-up select bit
7 pull-up select bit
Note: In memory expansion and microprocessor mode, the content of this register can
be changed, but the pull-up resistance is not connected.
Pull-up control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FD16
When reset
0016 (Note 2)
R W
Bit symbol
PU10
Bit name
Function
P4
(Note 3)
P4 to P4
0
to P4
3
pull-up select bit
The corresponding port is
pulled high with a pull-up resistor
0 : Not pulled high
PU11
PU12
4
7
pull-up select bit
pull-up select bit
1 : Pulled high
P5 to P5
0
3
(Note 3)
PU13
PU14
PU15
P5
P6
P6
4
0
4
to P5
to P6
to P6
7
3
7
pull-up select bit
pull-up select bit
pull-up select bit
PU16
P7
0
to P7
3
pull-up select bit
(Note 1)
PU17
to P77
P74
pull-up select bit
Note 1: Since P71 is an N-channel open drain port, pull-up control is not available for it.
Note 2: When the VCC level is being impressed to the CNVSS terminal, this register
becomes to 0216 when reset (PU11 becomes to "1").
Note 3: In memory expansion and microprocessor mode, the content of this register
can be changed, but the pull-up resistance is not connected.
Pull-up control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FE16
When reset
0016
Bit symbol
PU20
Bit name
Function
R W
P8
0
4
to P8
3
pull-up select bit
The corresponding port is
pulled high with a pull-up resistor
0 : Not pulled high
PU21
P8
to P8
7
pull-up select bit
5)
(Except P8
P9 , P9 , P9
bit (Note)
P9 to P9
P100 to P10
P10 to P10
1 : Pulled high
PU22
0
2
3
pull-up select
PU23
PU24
PU25
4
7
pull-up select bit
3
pull-up select bit
4
7 pull-up select bit
Nothing is assigned.
These bits can neither be set nor reset. When read, their contents are "0".
Note: Since P9 is an N-channel open drain port, pull-up control is not available for it.
1
Figure 1.21.8. Pull-up control register
204
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Port control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCR
Address
03FF16
When reset
0016
R W
Bit symbol
PCR0
Bit name
Function
Port P1 control register
0 : When input port, read port
input level. When output port,
read the contents of port P1
register.
1 : Read the contents of port P1
register though input/output
port.
Nothing is assigned.
Theses bits can neither be set nor reset. When read, their contents are "0".
Figure 1.21.9. Port control register
205
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Programmable I/O Port
Table 1.21.1. Example connection of unused pins in single-chip mode
Pin name
Connection
Ports P0 to P10
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
(excluding P85)
XOUT (Note)
Open
Connect via a resistor to VCC (pull-up)
Connect to VCC
NMI
AVCC
AVSS, VREF, BYTE
Connect to VSS
Note: With external clock input to XIN pin.
Table 1.21.2. Example connection of unused pins in memory expansion mode and microprocessor mode
Pin name
Connection
Ports P6 to P10
After setting for input mode, connect every pin to VSS via a resistor
(pull-down); or after setting for output mode, leave these pins open.
(excluding P8
5
)
P4 /CS1 to P4
5
7/CS3
Sets ports to input mode, set output enable bits of CS1 through CS3 to
"0", and connect to VCC via resistors (pull-up).
Open
BHE, ALE, HLDA,
OUT(Note 1), BCLK(Note 2)
X
Connect via a resistor to VCC (pull-up)
Connect to VCC
HOLD, RDY, NMI
AVCC
AVSS, VREF
Connect to VSS
Note 1: With external clock input to XIN pin.
Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to "1", connect to VCC via a resis-
tor (pull-up).
Microcomputer
Microcomputer
Port P6 to P10 (except for P85)
Port P0 to P10 (except for P85)
(Input mode)
(Input mode)
(Input mode)
(Input mode)
(Output mode)
(Output mode)
Open
Open
Open
NMI
Port P45/CS1
to P47/CS3
(Note 1) NMI
BHE
HLDA
ALE
XOUT
VCC
Open
VCC
XOUT
(Note 2) BCLK
AVCC
HOLD
BYTE
AVSS
RDY
AVCC
VREF
AVSS
V
SS
V
REF
VSS
In single-chip mode
In memory expansion mode or
in microprocessor mode
Note 1: When the wiring between NMI pin and VCC is long, connect to VCC via a resistor (pull-up).
Note 2: When the BCLK output disable bit (bit 7 at address 000416) is set to "1", connect to VCC via a re-
sistor (pull-up).
Figure 1.21.10. Example connection of unused pins
206
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.22.1. Absolute maximum ratings
Symbol
Vcc
Unit
V
Condition
Rated value
-0.3 to 6.5
Parameter
Supply voltage
VCC=AVCC
VCC=AVCC
Analog supply voltage
AVcc
-0.3 to 6.5
V
CNVSS , BYTE,
Input
voltage
to P0
to P3
to P6
7
7
7
, P1
, P4
, P7
0
0
0
7
to P1
7
, P2
0
0
7
to P2
7
,
,
to P4
7
, P5
to P5
7
-0.3 to Vcc+0.3
V
, P7
2
to P7
, P8
0
to P8
7,
V
I
to P9
, P10
0
to P10
7,
P7
1
, P9
1
-0.3 to 6.5
V
V
Output
voltage
P00
P30
P60
P86
to P0
to P3
to P6
7
7
7
, P1
, P4
, P7
0
0
0
to P1
7
, P2
0
0
7
to P2
7
,
,
to P4
7
, P5
to P5
7
-0.3 to Vcc+0.3
VO
, P7
2
to P7
, P8
0
to P8
4
,
,
, P8
7
, P9
0, P9
2
to P9
7, P10
0
to P10
7
X
P7
OUT
1
, P9
1,
-0.3 to 6.5
700
V
Power dissipation
Topr=25 ˚C
P
d
mW
C
T
opr
-40 to 125 (Note)
-65 to 150
Operating ambient temperature
Storage temperature
T
stg
C
Note: In case of 85 ˚C guaranted version, -40 to 85 ˚C.
In case of 125 ˚C guaranted version, -40 to 125 ˚C.
207
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.22.2. Recommended operating conditions (referenced to Vcc = 4.2 V to 5.5 V at
Topr = –40 to 125 ˚C unless otherwise specified)
Standard
Symbol
Parameter
Unit
V
V
Typ
.
Max.
5.5
Min
4.2
Vcc
Supply voltage
5.0
Vcc
AVcc
Analog supply voltage
Supply voltage
Analog supply voltage
Vss
0
0
V
V
AVss
P3
P7
IN, RESET, CNVSS, BYTE
P7 , P9
P0 to P0
P0 to P0
(data input function during memory expansion and microprocessor modes)
P3 to P3 , P4 to P4 , P5 to P57, P6 to P6
P7 to P7 , P8 to P8 , P9 to P9 , P10 to P10
IN, RESET, CNVSS, BYTE
P0 to P0 , P1 to P1 , P2
P0 to P0 , P1 to P1 , P2
(data input function during memory expansion and microprocessor modes)
1
to P3
7
, P4
0
to P4
7
, P5
0
to P57, P6
0
to P6
7
, P70,
to P10
2
to P7
7
, P8
0
to P8
7
, P9
0
, P9 to P9
2
7
, P10
0
7,
0.8Vcc
Vcc
V
X
HIGH input
voltage
V
IH
0.8Vcc
0.8Vcc
1
1
6.5
V
V
0
7
, P1
0
to P1
7
, P2
0
to P27, P3
0 (during single-chip mode)
Vcc
0
7
, P1
0
to P1
7
, P2
0
to P27, P3
0
0.5Vcc
Vcc
V
1
7
0
7
0
0
7,
0
7
0
7
0
7
0
7
,
0
0.2Vcc
V
X
LOW input
voltage
V
IL
0
7
0
7
0
to P2
7
, P3
0 (during single-chip mode)
0
0
0.2Vcc
V
V
0
7
0
7
0
to P27, P3
0
0.16Vcc
P0
P4
P8
0
to P0
to P4
to P84,P86,P87,P90 ,P9
7
, P1
, P5
0
to P1
to P5
7
, P2
, P6
0
to P2
to P6
to P97,P10
7
,P3
,P7
0
to P3
,P7 to P7
to P10
7,
HIGH peak output
current
IOH (peak)
0
7
0
7
0
7
0
2
7,
-10.0
mA
0
2
0
7
P0
P4
P8
0
to P0
to P4
to P8
7
, P1
, P5
, P8
0
to P1
7
, P2
0
to P2
7
, P3
0
to P3
2
7,
HIGH average output
current
IOH (avg)
IOL (peak)
IOL (avg)
-5.0
mA
mA
mA
0
0
7
4
0
0
to P5
7
, P6
0
to P6
7
, P7
0
, P to P
7,
, P8
7, P9
0, P9
2
to P3
7, P10
0 to P107
P0
P4
P8
0
to P0
to P4
to P84,P86,P87,P9
7
, P1
, P5
0
to P1
to P5
7
, P2
, P6
0
to P2
to P6
7
,P3
,P7
0
to P37,
LOW peak output
current
0
7
0
7
0
7
0 to P77,
10.0
0
0
to P97,P10 to P10
0
7
P0
P4
P8
0
to P0 , P1 to P1
to P4 , P5 to P5
to P84,P86,P87,P9
7
0
7
, P2 to P2 ,P3
, P6 to P6 ,P7
0
7
0
to P37,
LOW average
output current
5.0
16
0
7
0
7
0
7
0 to P77,
0
0
to P97,P10 to P107
0
No wait
0
0
MHz
MHz
kHz
(XIN
)
Main clock input oscillation frequency
Subclock oscillation frequency
f
With wait
16
50
f (XcIN
)
32.768
Note 1: The mean output current is the mean value within 100ms.
Note 2: The total IOL (peak) for ports P0, P1, P2, P8 , P8 , P9, and P10 must be 80mA max. The total IOH (peak) for ports P0, P1,
4 must be
6
7
P2, P8 , P8 , P9, and P10 must be 80mA max. The total IOL (peak) for ports P3, P4, P5, P6, P7, and P8 to P8
6
7
0
80mA max. The total IOH (peak) for ports P3, P4, P5, P6, P7 , P7 to P7 , and P8 to P8 must be 80mA max.
0
2
7
0
4
Note 3: Relationship between main clock oscillation frequency and supply voltage.
Main clock input oscillation frequency
(Mask ROM, No wait)
Main clock input oscillation frequency
(Mask ROM, With wait)
16.0
16.0
0.0
0.0
4.2
Supply voltage[V]
(BCLK: no division)
5.5
4.2
Supply voltage[V]
(BCLK: no division)
5.5
Note 4: Execute case without wait, program/erase of flash memory by Vcc = 4.2V to 5.5V and f(BCLK)
≤ 6.25 MHz. Execute case
with wait, program/erase of flash memory by Vcc = 4.2V to 5.5V and f(BCLK) ≤ 12.5 MHz.
208
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.22.3. Electrical characteristics (referenced to Vcc = 5V, Vss = AVss = 0 V at Topr = –40 to
125 ˚C, f(XIN) = 16MHz unless otherwise specified)
Standard
Parameter
Unit
Symbol
Measuring condition
Min
Typ. Max.
P0
P3
0
0
to P0
to P3
7
, P1
0
0
7
, P2
, P5
0
0
7
7
,
,
7
, P4
HIGH output
voltage
VOH
P6
0
0
2
to P6
7
4
7
, P7
0
, P7
, P8
, P10 to P10
IOH=-5mA
0.6Vcc
V
,
P8
to P8
P8
6
P9 to P9
7
P0
P3
0
0
to P0
7
, P1
0
to P1
to P4
, P7
, P8
, P10 to P10
7
, P2
0
0
7
7
,
,
to P3
7, P4
0
0
7
, P5
HIGH output
voltage
VOH
P6
0
0
2
to P6
7
4
7
, P7
2
to P7
0.9Vcc
IOH=-200µA
V
,
P8
to P8
P8
6
, P9 ,
7 0
P9 to P9
0
7
HIGHPOWER
LOWPOWER
I
OH=-1mA
3.0
3.0
HIGH output
voltage
X
OUT
V
V
IOH=-0.5mA
VOH
HIGH output
voltage
3.0
1.6
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
X
COUT
LOW output
voltage
P0
P3
P6
0
to P0
to P3
to P6
7
, P1
, P4
, P7
0
to P1
to P4
to P7
7
, P2
, P5
, P8
0
to P2
to P5
to P8
7
,
0
7
0
7
0
7,
I
OL=5mA
V
V
OL
OL
0.4Vcc
0.1Vcc
V
V
0
7
0
7
0
4,
P86
, P8
7, P9
0
to P9
7, P10
0
to P10
7
P00
to P0
7
, P1
0
to P1
7
, P2
0
to P2
7
,
LOW output
voltage
P3
P6
0
0
to P3
7
, P4
, P7
0
0
to P4
7
, P5
, P8
0
0
to P5
7
,
,
I
OL=200µA
to P6
7
to P7
7
to P8
4
P86
, P8
7
, P9
0
to P97, P10
0
to P107
I
OL=1mA
2.0
HIGHPOWER
LOWPOWER
LOW output
voltage
X
OUT
VOL
V
V
IOL=0.5mA
2.0
0
0
With no load applied
With no load applied
HIGHPOWER
LOWPOWER
LOW output
voltage
X
COUT
HOLD, RDY, TA0IN to TA4IN, TB0IN
Hysteresis
to TB5IN, INT
CTS , CTS , CLK
TA2OUT to TA4OUT, NMI, KI
RXD to RXD , SIN
0
to INT
5
, ADTRG
,
V
V
T+
T+
-
-
V
V
T-
T-
0
1
0
to CLK3,
0.2
0.2
0.8
V
0
to KI3,
0
2
3
Hysteresis
RESET, CNVSS, BYTE
1.8
5.0
V
P00
P30
P60
P90
to P0
to P3
to P6
to P9
7
7
7
7
, P1
, P4
, P7
0
0
0
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7,
HIGH input
current
7
,
,
µA
I
IH
7
V
I
I
=5V
=0V
, P100 to P107,
X
IN, RESET, CNVss, BYTE
P00
P30
P60
P90
to P0
to P3
to P6
to P9
7
7
7
7
, P1
, P4
, P7
0
0
0
to P1
to P4
to P7
7
7
7
, P2
, P5
, P8
0
0
0
to P2
to P5
to P8
7
,
,
,
LOW input
current
7
7
µA
IIL
V
-5.0
, P100 to P107,
X
IN, RESET, CNVss, BYTE
P0
P3
P6
P8
P9
0
0
0
0
0
to P0
to P3
to P6
to P8
7
7
7
4
, P1
, P4
, P7
, P8
0
0
0
6
to P1
to P4
7
7
, P2
, P5
0
0
7
to P2
7
,
RPULLUP
Pull-up
resistance
to P5
7
,
, P7
2
to P7
,
kΩ
V
I
=0V
30.0
2.0
50.0 167.0
, P8
7
,
P92 to P97, P100 to P107
,
Ω
RfXIN
Feedback resistance
Feedback resistance
X
X
IN
1.0
6.0
M
MΩ
RfCXIN
CIN
RAM retention voltage
V
V
When clock is stopped
RAM
209
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Table 1.22.4. Electrical characteristics (referenced to Vcc = AVcc = VREF = 5V, Vss = AVss = 0 V
at Topr = –40 to 125 ˚C, f(XIN) = 16MHz unless otherwise specified)
Standard
Parameter
Measuring condition
Unit
Symbol
Min. Typ. Max.
6NBMC
50
55
60
65
70
75
mA
mA
mA
f(XIN)=16MHz
Square wave,
no division
In single-chip
mode, the output
pins are open
and other pins
are Vss.
6NBFC
6NAMG
6NAMC
6NAFG
60
65
75
80
mA
mA
Icc
Power supply current
f(XCIN)=32kHz,square wave
(Note)
200
4.0
µA
f(XCIN)=32kHz, square wave,
wait. Timer A operates with fc32
µA
µA
.
Topr=25°C
Clock is stopped.
1.0
Topr=85°C
Clock is stopped.
µA
µA
20.0
50.0
Topr=125°C
Clock is stopped.
Note: For devices with flash memory the program resides in the internal RAM and FMR13 is set to "1".
210
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Table 1.22.5. A-D conversion characteristics (referenced to Vcc = AVcc = VREF = 5V,
Vss = AVss = 0 V at Topr = –40 to 125 ˚C, f(XIN) = 16MHz unless otherwise specified)
Standard
Symbol
Parameter
Measuring condition (Note1, 2, 3)
Unit
Min. Typ. Max.
10 Bits
V
V
V
V
REF
REF
REF
=
=
=
VCC = 5V
Resolution
Absolute accuracy (8bit)
AVCC
AVCC
=
=
V
CC
=
=
5V, øAD ≤ 10MHz
5V, øAD ≤ 10MHz
2
3
LSB
LSB
Sample & hold function disabled
V
CC
Absolute
accuracy
(10bit)
AN0 to AN7 input,
AN00 to AN07 input,
AN20 to AN27 input,
REF = AVCC
= VCC
3
LSB
LSB
Sample & hold function enabled
= 5V,
ANEX0, ANEX1 input
ø
AD ≤ 10MHz
External op-amp connection mode
7
R
LADDER
V
REF
=
=
=
=
=
V
CC
=
5V
10
4.125
3.3
40
kΩ
Ladder resistance
Conversion time (10bit)
f(XIN
f(XIN
f(XIN
f(XIN
f(XIN
f(XIN
)
)
)
)
)
)
16MHz, øAD = f2AD/2 = 8MHz (Note 4)
10MHz, øAD = f2AD = 10MHz (Note 4)
16MHz, øAD = f2AD/2 = 8MHz (Note 4)
10MHz, øAD = f2AD = 10MHz (Note 4)
16MHz, øAD = f2AD/2 = 8MHz (Note 4)
10MHz, øAD = f2AD = 10MHz (Note 4)
t
CONV
µ
s
µs
µ
s
t
CONV
Conversion time (8bit)
Sampling time
3.5
2.8
t
SAMP
=
=
0.375
0.3
V
REF
IA
2
0
V
CC
REF
Reference voltage
V
V
V
Analog input voltage
V
Note 1: Do f(XIN) in range of main clock input oscillation frequency prescribed with recommended operating
conditions of table 1.22.2. Divide the f2AD if f(XIN) exceeds 10MHz, and make AD operation clock
frequency (øAD) equal to or lower than 10MHz.
Note 2: A case without sample & hold function turn AD operation clock frequency (øAD) into 250kMHz or
more in addition to a limit of Note 2.
A case with sample & hold function turn AD operation clock frequency (øAD) into 1MHz or more in
addition to a limit of Note 2.
Note 3: Connect AVCC pin to VCC pin and apply the same potential.
Note 4: This applies when f2AD is selected no division mode and PCLK0 is "1".
Table 1.22.6. D-A conversion characteristics (referenced to Vcc = 5 V, VREF = 5V,
Vss = AVss = 0 V at Topr = –40 to 125 ˚C, f(XIN) = 16MHz unless otherwise specified)
Standard
Min. Typ. Max.
Symbol
Parameter
Measuring condition
Unit
Resolution
Absolute accuracy
Setup time
Bits
%
8
1.0
3
tsu
µs
R
O
Output resistance
4
10
20
kΩ
IVREF
Reference power supply input current
1.5
mA
(Note)
Note: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
"0016". The A-D converter's ladder resistance is not included. Also, when the VREF is unconnected
at the A-D control register, IVREF is passed.
Table 1.22.7. Flash memory version electrical characteristics (referenced to Vcc = 4.2 to 5.5V,
Vss = AVss = 0 V at Topr = 0 to 60 ˚C, f(XIN) = 16MHz unless otherwise specified)
Standard
Parameter
Unit
Min.
Typ.
6
Max.
120
600
ms
ms
ms
ms
Page program time
Block erase time
Erase all unlocked blocks time
Lock bit program time
50
50 X n (Note)
6
600 X n (Note)
120
Note: "n" denotes the number of block erase.
211
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Timing requirements (Vcc = 5 V, Vss = 0 V at Topr = –40 to 125 ˚C unless otherwise specified)
Table 1.22.8. External clock input
Standard
Symbol
Parameter
Unit
Min.
62.5
25
Max.
t
c
ns
ns
ns
ns
ns
External clock input cycle time
t
w(H
)
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
t
w(L)
25
t
r
15
15
t
f
External clock fall time
Table 1.22.9. Memory expansion- and microprocessor modes
Standard
Symbol
Parameter
Unit
Min.
Max.
t
ac1(RD-DB)
Data input access time (no wait)
ns
ns
ns
(Note)
t
ac2(RD-DB)
ac3(RD-DB)
(Note)
(Note)
Data input access time (with wait)
Data input access time (when accessing multiplex bus area)
Data input setup time
t
t
t
su(DB-RD)
40
30
40
0
ns
ns
ns
ns
ns
ns
ns
su(RDY-BCLK )
RDY input setup time
HOLD input setup time
Data input hold time
t
su(HOLD-BCLK )
h(RD-DB)
h(BCLK -RDY)
t
t
0
RDY input hold time
t
h(BCLK-HOLD )
d(BCLK-HLDA )
0
HOLD input hold time
HLDA output delay time
t
40
Note: Calculated according to the BCLK frequency as follows:
109
tac1(RD – DB) =
tac2(RD – DB) =
t
ac3(RD – DB) =
– 45
– 45
– 45
f(BCLK) X 2
[ns]
3 X 109
f(BCLK) X 2
[ns]
[ns]
3 X 109
f(BCLK) X 2
212
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Timing requirements (referenced to Vcc = 5 V, Vss = 0 V at Topr = –40 to 125 ˚C unless otherwise
specified)
Table 1.22.10. Timer A input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
40
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
40
Table 1.22.11. Timer A input (gating input in timer mode)
Standard
Symbol
Parameter
Unit
Min.
400
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
200
200
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.22.12. Timer A input (external trigger input in one-shot timer mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
ns
ns
ns
t
c(TA)
TAiIN input cycle time
t
w(TAH)
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.22.13. Timer A input (external trigger input in pulse width modulation mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
t
w(TAH)
ns
ns
TAiIN input HIGH pulse width
TAiIN input LOW pulse width
t
w(TAL)
Table 1.22.14. Timer A input (up/down input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
Max.
t
c(UP)
ns
ns
ns
2000
1000
1000
TAiOUT input cycle time
t
w(UPH)
w(UPL)
TAiOUT input HIGH pulse width
t
TAiOUT input LOW pulse width
TAiOUT input setup time
TAiOUT input hold time
t
su(UP-TIN)
ns
ns
400
400
t
h(TIN-UP)
213
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Timing requirements (referenced to Vcc = 5 V, Vss = 0 V at Topr = –40 to 125 ˚C unless otherwise
specified)
Table 1.22.15. Timer B input (counter input in event counter mode)
Standard
Symbol
Parameter
Unit
Min.
100
Max.
t
c(TB)
ns
ns
ns
ns
ns
ns
TBiIN input cycle time (counted on one edge)
t
w(TBH)
w(TBL)
c(TB)
TBiIN input HIGH pulse width (counted on one edge)
TBiIN input LOW pulse width (counted on one edge)
TBiIN input cycle time (counted on both edges)
TBiIN input HIGH pulse width (counted on both edges)
TBiIN input LOW pulse width (counted on both edges)
40
40
t
t
200
80
t
w(TBH)
t
w(TBL)
80
Table 1.22.16. Timer B input (pulse period measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
TBiIN input cycle time
ns
ns
ns
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.22.17. Timer B input (pulse width measurement mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
t
c(TB)
ns
ns
ns
TBiIN input cycle time
t
w(TBH)
TBiIN input HIGH pulse width
TBiIN input LOW pulse width
t
w(TBL)
Table 1.22.18. A-D trigger input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
t
c(AD)
ns
ns
ADTRG input cycle time (trigger able minimum)
ADTRG input LOW pulse width
t
w(ADL)
Table 1.22.19. Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
t
c(CK)
w(CKH)
w(CKL)
ns
ns
ns
ns
ns
ns
ns
CLKi input cycle time
CLKi input HIGH pulse width
CLKi input LOW pulse width
TxDi output delay time
TxDi hold time
t
t
t
t
d(C-Q)
h(C-Q)
80
0
30
90
t
su(D-C)
RxDi input setup time
RxDi input hold time
t
h(C-D)
________
Table 1.22.20. External interrupt INTi inputs
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
t
w(INH)
w(INL)
ns
ns
INTi input HIGH pulse width
INTi input LOW pulse width
t
214
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Topr = –40 to 125 ˚C, CM15 ="1"
unless otherwise specified)
Table 1.22.21. Memory expansion mode and microprocessor mode (no wait)
Standard
Measuring condition
Symbol
Parameter
Unit
ns
Min.
Max.
25
t
t
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
0
0
ns
ns
h(RD-AD)
t
t
h(WR-AD)
Address output hold time (WR standard)
Chip select output delay time
ns
ns
d(BCLK-CS)
25
25
25
25
40
t
t
h(BCLK-CS)
d(BCLK-ALE)
Chip select output hold time (BCLK standard)
ALE signal output delay time
4
– 4
0
ns
ns
Figure 1.22.1
t
h(BCLK-ALE)
ALE signal output hold time
RD signal output delay time
RD signal output hold time
ns
ns
ns
t
t
d(BCLK-RD)
h(BCLK-RD)
t
t
d(BCLK-WR)
h(BCLK-WR)
WR signal output delay time
WR signal output hold time
ns
ns
0
t
t
d(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
ns
ns
h(BCLK-DB)
4
(Note1)
t
d(DB-WR)
h(WR-DB)
Data output delay time (WR standard)
ns
ns
Data output hold time (WR standard)(Note2)
0
t
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB – WR) =
– 40
[ns]
f(BCLK) X 2
Note 2: This is standard value shows the timing when the output is off,
and doesn’t show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t =
–CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output "L" level is
t =
– 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
215
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Topr = –40 to 125 ˚C, CM15 ="1"
unless otherwise specified)
Table 1.22.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
25
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
ns
ns
ns
ns
ns
ns
t
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
4
0
th(RD-AD)
h(WR-AD)
t
0
d(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
ALE signal output delay time
25
25
25
25
t
t
h(BCLK-CS)
4
td(BCLK-ALE)
th(BCLK-ALE)
ns
ns
ALE signal output hold time
– 4
Figure 1.22.1
d(BCLK-RD)
RD signal output delay time
ns
ns
ns
ns
t
h(BCLK-RD)
RD signal output hold time
WR signal output delay time
WR signal output hold time
0
0
t
t
d(BCLK-WR)
th(BCLK-WR)
d(BCLK-DB)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
t
t
t
t
ns
ns
ns
40
4
h(BCLK-DB)
(Note1)
d(DB-WR)
h(WR-DB)
Data output hold time (WR standard)(Note2)
0
ns
Note 1: Calculated according to the BCLK frequency as follows:
10 9
td(DB
– WR) =
–
40
[ns]
f(BCLK)
Note 2: This is standard value shows the timing when the output is off,
and doesn’t show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
R
C
DBi
t =
–CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output "L" level is
t =
– 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
216
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
Vcc = 5 V
Switching characteristics (referenced to Vcc = 5 V, Vss = 0 V at Topr = –40 to 125 ˚C, CM15 ="1"
unless otherwise specified)
Table 1.22.23. Memory expansion mode and microprocessor mode (with wait, accessing external
memory, multiplex bus area selected)
Standard
Measuring condition
Symbol
Parameter
Unit
Min.
Max.
t
d(BCLK-AD)
h(BCLK-AD)
Address output delay time
25
ns
ns
ns
t
Address output hold time (BCLK standard)
Address output hold time (RD standard)
4
(Note)
th(RD-AD)
(Note)
th(WR-AD)
Address output hold time (WR standard)
ns
t
d(BCLK-CS)
h(BCLK-CS)
Chip select output delay time
25
25
ns
ns
ns
ns
ns
ns
t
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
RD signal output delay time
4
(Note)
th(RD-CS)
(Note)
t
h(WR-CS)
t
d(BCLK-RD)
h(BCLK-RD)
t
RD signal output hold time
0
0
t
t
t
d(BCLK-WR)
WR signal output delay time
25
40
ns
ns
ns
h(BCLK-WR)
d(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
Figure 1.22.1
t
h(BCLK-DB)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
4
ns
ns
(Note)
t
d(DB-WR)
h(WR-DB)
(Note)
t
Data output hold time (WR standard)
ns
ns
ns
t
d(BCLK-ALE)
h(BCLK-ALE)
ALE signal output delay time (BCLK standard)
25
– 4
(Note)
t
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
ALE signal output hold time (Adderss standard)
t
d(AD-ALE)
h(ALE-AD)
ns
ns
30
0
t
td(AD-RD)
Post-address RD signal output delay time
ns
t
d(AD-WR)
Post-address WR signal output delay time
Address output floating start time
0
ns
ns
t
dZ(RD-AD)
8
Note: Calculated according to the BCLK frequency as follows:
109
9 X 3
10
td(DB – WR) =
th(RD – AD) =
– 40
[ns]
[ns]
f(BCLK) X 2
f(BCLK) X 2
109
109
th(WR – DB) =
td(AD – ALE) =
th(WR – AD) =
th(RD – CS) =
[ns]
[ns]
[ns]
[ns]
f(BCLK) X 2
f(BCLK) X 2
109
109
– 25
f(BCLK) X 2
f(BCLK) X 2
109
th(WR – CS) =
[ns]
f(BCLK) X 2
217
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Electrical Characteristics
P0
P1
P2
P3
30pF
P4
P5
P6
P7
P8
P9
P10
Figure 1.22.1. Port P0 to P10 measurement circuit
218
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
VCC = 5V
t
c(TA)
t
w(TAH)
TAiIN input
tw(TAL)
tc(UP)
tw(UPH)
TAiOUT input
t
w(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling
edge is selected)
t
h(TIN UP)
tsu(UP–TIN)
TAiIN input
(When count on rising
edge is selected)
t
c(TB)
t
w(TBH)
TBiIN input
tw(TBL)
t
t
c(AD)
t
w(ADL)
ADTRG input
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
th(C–Q)
TxDi
RxDi
t
su(D–C)
t
d(C–Q)
t
h(C–D)
tw(INL)
INTi input
t
w(INH)
Figure 1.22.2. Vcc = 5V timing diagram (1)
219
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
VCC = 5V
Memory expansion mode and microprocessor mode
(valid only with wait)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
tsu(RDY–BCLK)
th(BCLK–RDY)
(Valid with or without wait)
BCLK
tsu(HOLD–BCLK)
th(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
td(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Note: The above pins are set to high-impedance regardless of the input level of the
BYTE pin and bit (PM06) of processor mode register 0 selects the function of
ports P40 to P43.
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=1.0V, VIH=4.0V
• Output timing voltage : Determined with VOL=2.5V, VOH=2.5V
Figure 1.22.3. Vcc = 5V timing diagram (2)
220
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
VCC = 5V
Memory expansion mode and microprocessor mode
(with no wait)
Read timing
BCLK
td(BCLK–CS)
t
h(BCLK–CS)
4ns.min
25ns.max
CSi
t
h(RD–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
25ns.max
4ns.min
ADi
BHE
t
d(BCLK–ALE)
t
h(BCLK–ALE)
t
h(RD–AD)
0ns.min
–4ns.min
25ns.max
ALE
RD
DB
t
h(BCLK–RD)
0ns.min
t
d(BCLK–RD)
25ns.max
t
ac1(RD–DB)
Hi–Z
t
SU(DB–RD)
40ns.min
t
h(RD–DB)
0ns.min
Write timing
BCLK
t
h(BCLK–CS)
4ns.min
t
d(BCLK–CS)
25ns.max
CSi
t
h(WR–CS)
0ns.min
tcyc
t
d(BCLK–AD)
t
h(BCLK–AD)
4ns.min
25ns.max
ADi
BHE
0ns.min
th(WR–AD)
t
h(BCLK–ALE)
–4ns.min
t
d(BCLK–ALE)
25ns.max
ALE
t
h(BCLK–WR)
0ns.min
t
d(BCLK–WR)
25ns.max
WR, WRL,
WRH
t
d(BCLK–DB)
40ns.max
t
h(BCLK–DB)
4ns.min
Hi–Z
DB
t
h(WR–DB)
0ns.min
t
d(DB–WR)
(tcyc/2–40)ns.min
Figure 1.22.4. Vcc = 5V timing diagram (3)
221
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
VCC = 5V
Memory expansion mode and microprocessor mode
(when accessing external memory area with wait)
Read timing
BCLK
t
h(BCLK
–CS)
t
d(BCLK–CS)
25ns.max
4ns.min
CSi
t
h(RD
0ns.min
–CS)
tcyc
t
d(BCLK
–AD)
t
h(BCLK
–
AD)
25ns.max
4ns.min
ADi
BHE
25ns.max
t
d(BCLK
–
ALE)
t
h(BCLK
–ALE)
t
h(RD
0ns.min
–AD)
–
4ns.min
ALE
RD
DB
t
h(BCLK
0ns.min
–
RD)
t
d(BCLK
25ns.max
–RD)
t
ac2(RD
–DB)
Hi–
Z
t
h(RD
0ns.min
–
DB)
t
SU(DB
40ns.min
–RD)
Write timing
BCLK
t
d(BCLK–CS)
25ns.max
t
h(BCLK
–CS)
4ns.min
CSi
t
h(WR
0ns.min
–CS)
tcyc
t
d(BCLK
25ns.max
–AD)
t
h(BCLK
4ns.min
–AD)
ADi
BHE
t
d(BCLK
25ns.max
–ALE)
t
h(WR
0ns.min
–AD)
t
h(BCLK
–ALE)
–
4ns.min
ALE
t
h(BCLK
0ns.min
–
WR)
t
d(BCLK
25ns.max
–
WR)
WR, WRL,
WRH
t
d(BCLK
40ns.max
–DB)
t
h(BCLK
4ns.min
–
DB)
DBi
t
h(WR
0ns.min
–DB)
t
d(DB
–WR)
(tcyc 40)ns.min
–
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with: VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with: VOL=0.8V, VOH=2.0V
Figure 1.22.5. Vcc = 5V timing diagram (4)
222
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing
V
CC = 5V
Memory expansion mode and microprocessor mode
(when accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
tcyc
t
h(BCLK
4ns.min
–CS)
t
d(BCLK
25ns.max
–CS)
t
h(RD–CS)
(tcyc/2)ns.min
CSi
t
d(AD
–
ALE)
t
h(ALE
50ns.min
–
AD)
(tcyc/2
–25)ns.min
ADi
Address
Data input
Address
t
h(RD
0ns.min
–RD)
–DB)
/DBi
t
dz(RD
8ns.max
–AD)
tac3(RD–DB)
t
SU(DB
40ns.min
t
d(AD–RD)
0ns.min
t
d(BCLK
25ns.max
–
AD)
th(BCLK
–AD)
4ns.min
ADi
BHE
t
d(BCLK
–ALE)
t
h(BCLK
–
ALE)
t
h(RD
(tcyc/2)ns.min
–
AD)
–
4ns.min
25ns.max
ALE
RD
t
h(BCLK
–RD)
t
d(BCLK
–RD)
25ns.max
0ns.min
Write timing
BCLK
t
h(BCLK
–
CS)
tcyc
t
d(BCLK
–CS)
4ns.min
t
h(WR
–CS)
25ns.max
(tcyc/2)ns.min
CSi
t
h(BCLK
4ns.min
–DB)
t
d(BCLK
–DB)
40ns.max
Data output
ADi
/DBi
Address
Address
–ALE)
t
d(DB
–
WR)
t
h(WR
(tcyc/2)ns.min
h(BCLK
4ns.min
–DB)
t
d(AD
(tcyc*3/2
–
40)ns.min
(tcyc/2–25)ns.min
t
d(BCLK
–AD)
t
–AD)
25ns.max
ADi
BHE
t
h(BCLK
–
ALE)
t
d(AD
0ns.min
–WR)
t
d(BCLK
–
ALE)
t
h(WR
(tcyc/2)ns.min
–AD)
–
4ns.min
25ns.max
ALE
t
h(BCLK
0ns.min
–WR)
t
d(BCLK
–WR)
25ns.max
WR, WRL,
WRH
Measuring conditions :
• VCC=5V
• Input timing voltage : Determined with VIL=0.8V, VIH=2.5V
• Output timing voltage : Determined with VOL=0.8V, VOH=2.0V
Figure 1.22.6. Vcc = 5V timing diagram (5)
223
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
Outline Performance
Table 1.23.1 shows the outline performance of the M16C/6N group (flash memory version).
Table 1.23.1. Outline performance of the M16C/6N group (flash memory version)
Item
Performance
Flash memory operation mode
Four modes (parallel I/O, standard serial I/O, CPU rewrite and CAN I/O)
Erase block
division
See Figure 1.23.1
User ROM area
Boot ROM area
One division (8 Kbytes) (Note)
In units of pages (in units of 256 bytes)
Collective erase/block erase
Program/erase control by software command
Protected for each block by lock bit
8 commands
Program method
Erase method
Program/erase control method
Protect method
Number of commands
Program/erase count
100 times
Data retention
10 years
Parallel I/O, standard serial I/O and CAN I/O modes are supported.
ROM code protect
Note: The boot ROM area contains a standard serial I/O and CAN I/O modes control program which is stored
in it when shipped from the factory. This area can be erased and programmed in only parallel I/O mode.
224
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description (Flash Memory Version)
Flash Memory
The M16C/6N group (flash memory version) contains the flash memory that can be rewritten with a single
voltage. For this flash memory, four flash memory modes are available in which to read, program, and
erase: parallel I/O, standard serial I/O and CAN I/O modes in which the flash memory can be manipulated
using a programmer and a CPU rewrite mode in which the flash memory can be manipulated by the Central
Processing Unit (CPU). Each mode is detailed in the pages to follow.
The flash memory is divided into several blocks as shown in Figure 1.23.1, so that memory can be erased
one block at a time. Each block has a lock bit to enable or disable execution of an erase or program
operation, allowing for data in each block to be protected.
In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash
memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite, standard
serial I/O and CAN I/O modes. This boot ROM area has had a standard serial I/O and CAN I/O modes
control program stored in it when shipped from the factory. However, the user can write a rewrite control
program in this area that suits the user’s application system. This boot ROM area can be rewritten in only
parallel I/O mode.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
Note 1: The boot ROM area can be rewritten in
only parallel input/output mode. (Access
to any other areas is inhibited.)
Note 2: To specify a block, use the maximum
address in the block that is an even
address.
0F000016
Block 3 : 32K byte
Flash memory
size
Flash memory
start address
0F800016
0FA00016
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
256Kbytes
0C000016
128Kbytes
0E000016
0FC00016
0FFFFF16
0FE00016
8K byte
0FFFFF16
Boot ROM area
User ROM area
Figure 1.23.1. Block diagram of flash memory version
225
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control
of the central processing unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 1.23.1 can be rewritten, the boot ROM area
cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM
area and each block area.
The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU
rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must
be transferred to any area other than the internal flash memory before it can be executed.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in
parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard
serial I/O and CAN I/O modes become unusable.)
See Figure 1.23.1 for details about the boot ROM area.
Normal microcomputer mode is entered when the microcomputer is reset with pulling CNVSS pin low. In
this case, the CPU starts operating using the control program in the user ROM area.
When the microcomputer is reset by pulling the P55 pin low, the CNVSS pin high, and the P50 pin high, the
CPU starts operating using the control program in the boot ROM area. This mode is called the "boot"
mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.
Block Address
Block addresses refer to the maximum even address of each block. These addresses are used in the
block erase command, lock bit program command, and read lock status command.
226
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by
software commands. Operations must be executed from a memory other than the internal flash memory,
such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 03B716) is set to "1", transition to CPU rewrite mode
occurs and software commands can be accepted.
In the CPU rewrite mode, write to and read from software commands and data into even numbered address
("0" for byte address A0) in 16 bit units. Always write 8 bit software commands into even numbered address.
Commands are ignored with odd numbered addresses.
Use software commands to control program and erase operations. Whether a program or erase operation
has terminated normally or in error can be verified by reading the status register.
Figure 1.24.1 shows the flash memory control register 0 and the flash memory control register 1.
_____
Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1".
Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is
entered by setting this bit to "1", so that software commands become acceptable. In CPU rewrite mode, the
CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other
_______
than the internal flash memory. Also only when NMI pin is "H" level. To set this bit to "1", it is necessary to
write "0" and then write "1" in succession. The bit can be set to "0" by only writing a "0".
Bit 2 of the flash memory control register 0 is a lock bit disable select bit. By setting this bit to "1", it is
possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable
select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase
operation is performed when this bit is "1", the lock bit data that is "0" (locked) is set to "1" (unlocked) after
erasure. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. This bit can be
manipulated only when the CPU rewrite mode select bit is "1".
Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access
has failed. When the CPU rewrite mode select bit is "1", writing "1" for this bit resets the control circuit. To
release the reset, it is necessary to set this bit to "0".
Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot
mode. If this bit is set to "1" in boot mode, the area to be accessed is switched from the boot ROM area to
the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to "1". Note
that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be
accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of
whether the CPU rewrite mode is on or off. Write to this bit only when executing out of an area other than
the internal flash memory.
Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When
this bit is set to "1", power is not supplied to the internal flash memory, thus power dissipation can be
reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to "1", it is
necessary to write "0" and then write "1" in succession. Use this bit mainly in the low speed mode (when
XCIN is the count source of BCLK).
When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut
off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces-
sary to set flash memory control register 1.
227
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Figure 1.24.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.24.3 shows a flow-
chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
03B716
When reset
XX000001
2
0
R W
Bit name
Function
Bit symbol
FMR00
0: Busy (being written or erased)
1: Ready
RY/BY status flag
CPU rewrite mode
select bit (Note 1)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
FMR01
(Software commands acceptable)
Lock bit disable
select bit (Note 2)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
FMR02
FMR03
Flash memory reset bit 0: Normal operation
(Note 3)
1: Reset
Reserved bit
User ROM area select bit
Must always be set to "0"
0: Boot ROM area is accessed
1: User ROM area is accessed
FMR05
(Note 4) (Effective in only
boot mode)
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in
succession. When it is not this procedure, it is not enacted in "1". This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Write to
this bit only when executing out of an area other than the internal flash memory. Also
only when NMI pin is "H" level. Clear this bit to "0" after read array command.
Note 2: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession
when the CPU rewrite mode select bit = "1". When it is not this procedure, it is not
enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = "1". Set this bit to "0" subsequently
after setting it to "1" (reset).
Note 4: Write to this bit only when executing out of an area other than the internal flash memory.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
03B616
When reset
XXXX0XXX
0
0
0
0
0 0 0
2
R W
Bit name
Function
Bit symbol
Reserved bit
Must always be set to "0"
0: Flash memory power supply is
connected
1: Flash memory power supply off
FMR13
Flash memory power
supply off bit (Note)
Reserved bits
Must always be set to "0"
Note : For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in
succession. When it is not this procedure, it is not enacted in "1". This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. During
parallel I/O mode, programming, erase or read of flash memory is not controlled by this
bit,only by external pins. Write to this bit only when executing out of an area other than
the internal flash memory.
Figure 1.24.1. Flash memory control registers
228
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Program in ROM
Start
Program in RAM
*1
Single chip mode, memory expansion
mode, or boot mode
(Boot mode only)
Set user ROM area select bit to "1"
Set CPU rewrite mode select bit to "1" (by
writing "0" and then "1" in succession)(Note 2)
Set processor mode register (Note 1)
Transfer CPU rewrite mode control
program to internal RAM
Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing "1" and then "0" in succession) (Note 3)
*1
Write "0" to CPU rewrite mode select bit
(Boot mode only)
Write "0" to user ROM area select bit (Note 4)
End
Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bits (bit 6
at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state)
12.5 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state)
Note 2: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in
succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of
an area other than the internal flash memory. Also only when NMI pin is "H" level.
Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to
execute a read array command or reset the flash memory.
Note 4: "1" can be set. However, when this bit is "1", user ROM area is accessed.
Figure 1.24.2. CPU rewrite mode set/reset flowchart
Program in ROM
Program in RAM
*1
Start
Transfer the program to be executed in the
low speed mode, to the internal RAM.
Set flash memory power supply off bit to "1"
(by writing "0" and then "1" in succession)(Note 1)
Jump to transferred control program in RAM
(Subsequent operations are executed by control
program in this RAM)
Switch the count source of BCLK.
XIN stop. (Note 2)
Process of low speed mode
*1
X
IN oscillating
Wait until the XIN has stabilized
Switch the count source of BCLK (Note 2)
Set flash memory power supply-OFF bit to "0"
Wait time until the internal circuit stabilizes
(Set NOP instruction about twice)
End
Note 1: For flash memory power supply off bit to be set to "1", the user needs to write a "0" and then a "1" to it in
succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.
Note 2: Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which
the count source is going to be switched must be oscillating stably.
Figure 1.24.3. Shifting to the low speed mode flowchart
229
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite
mode.
(1) Operation speed
During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit
(bit 6 at address 000616 and bits 6 and 7 at address 000716):
6.25 MHz or less when wait bit (bit 7 at address 000516) = "0" (without internal access wait state)
12.5 MHz or less when wait bit (bit 7 at address 000516) = "1" (with internal access wait state)
(2) Instructions inhibited against use
The instructions listed below cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory:
UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
(3) Interrupts inhibited against use
The address match interrupt cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be
_______
used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be
used because the flash memory conterol register 0 and 1 is forcibly initialized and return to normal
mode when each interrupt occurs. But it is needed that the jump addresses for each interrupt are set
in the fixed vector table and there is an interrupt program. Since the rewrite operation is halted when
_______
the NMI and watchdog timer interrupts occur, it is needed that CPU rewriting mode select bit is set to
"1" and the erase/program operation is performed over again.
(4) Internal reserved area expansion bit (bit 3 at address 000516)
The reserved area of the internal memory can be changed by using the internal reserved area expan-
sion bit (bit 3 at address 000516). However, if the CPU rewrite mode select bit (bit 1 at address 03B716)
is set to "1", the internal reserved area expansion bit (bit 3 at address 000516) also is set to "1"
automatically. Similarly, if the CPU rewrite mode select bit (bit 1 at address 03B716) is set to "0", the
internal reserved area expansion bit (bit 3 at address 000516) also is set to "0" automatically.
The precautions above apply to the products which flash memory size is over 192 Kbytes.
(5) Reset
Reset input is always accepted. After a reset, the addresses 0C000016 through 0CFFFF16 are made
a reserved area and cannot be accessed. Therefore, if your product has this area in the user ROM
area, do not write any address of this area to the reset vector. This area is made accessible by
changing the internal reserved area expansion bit (bit 3 at address 000516) in a program.
(6) Access disable
Write CPU rewrite mode select bit, flash memory power supply off bit and user ROM area select bit
only when executing out of an area other than the internal flash memory.
(7) How to access
For CPU rewrite mode select bit, lock bit disable select bit, and flash memory power supply off bit to be
set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this procedure,
it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be executed
during the interval.
Write CPU rewrite mode select bit only when executing out of an area other than the internal flash
_______
memory. Also only when NMI pin is "H" level.
230
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
(8) Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode,
those blocks may not be correctly rewritten and it is possible that the flash memory can no longer be
rewritten after that. Therefore, it is recommended to use the standard serial I/O mode, CAN I/O mode
or parallel I/O mode to rewrite these blocks.
(9) Using the lock bit
To use the CPU rewrite mode, use a boot program that can set and cancel the lock command.
231
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Software Commands
Table 1.24.1 lists the software commands available with the M16C/6N group (flash memory version).
After setting the CPU rewrite mode select bit to "1", write a software command to specify an erase or
program operation. Note that when entering a software command, the upper byte (D8 to D15) is ignored.
The content of each software command is explained below.
Table 1.24.1. List of software commands (CPU rewrite mode)
1st bus cycle
2nd bus cycle
3rd bus cycle
Command
Data
(D to D
Data
to D
Data
to D7)
Mode Address
Mode Address
Mode
Address
0
7)
(D
0
7)
(D
0
(Note 6)
Read array
Write
Write
Write
Write
Write
Write
Write
Write
X
FF16
7016
5016
4116
2016
A716
7716
7116
(Note 2)
Read status register
Clear status register
X
X
X
X
X
X
X
Read
X
SRD
(Note 3)
(Note 3)
WA0(Note 3)
BA (Note 4)
X
Page program
WD0
D016
D016
D016
Write
WA1
WD1
Write
Write
Write
Write
Read
Block erase
Erase all unlocked blocks
Lock bit program
Read lock bit status
BA (Note 4)
BA (Note 4)
(Note 5)
6
D
Note 1: When a software command is input, the high order byte of data (D
Note 2: SRD = Status Register Data
8 to D15) is ignored.
Note 3: WA = Write Address, WD = Write Data
WA and WD must be set sequentially from 0016 to FE16 (byte address; however, an even address). The page size is
256 bytes.
Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D6 corresponds to the block lock status. Block not locked when D6 = "1", block locked when D6 = "0".
Note 6: X denotes a given address in the user ROM area (that is an even address).
Read Array Command (FF16)
The read array mode is entered by writing the command code "FF16" in the 1st bus cycle. When an
even address to be read is input in one of the bus cycles that follow, the content of the specified
address is read out at the data bus (D0 to D15), 16 bits at a time.
The read array mode is retained intact until another command is written.
Read Status Register Command (7016)
When the command code "7016" is written in the 1st bus cycle, the content of the status register is read
out at the data bus (D0 to D7) by a read in the 2nd bus cycle.
The status register is explained in the next section.
Clear Status Register Command (5016)
This command is used to clear the bits SR3 to 5 of the status register after they have been set. These
bits indicate that operation has ended in an error. To use this command, write the command code
"5016" in the 1st bus cycle.
232
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Page Program Command (4116)
Page program allows for high speed programming in units of 256 bytes. Page program operation
starts when the command code "4116" is written in the 1st bus cycle. In the 2nd bus cycle through the
129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses A0
to A7 need to be incremented by 2 from "0016" to "FE16." When the system finishes loading the data,
it starts an auto write operation (data program and verify operation).
Whether the auto write operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto write operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to "0" at the same time the auto write operation starts and is returned
to "1" upon completion of the auto write operation. In this case, the read status register mode remains
active until the Read Array command (FF16) or Read Lock Bit Status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is "0" during auto write operation and "1"
when the auto write operation is completed as is the status register bit 7.
After the auto write operation is completed, the status register can be read out to know the result of the
auto write operation. For details, refer to the section where the status register is detailed.
Figure 1.24.4 shows an example of a page program flowchart.
Each block of the flash memory can be write protected by using a lock bit. For details, refer to the
section where the data protect function is detailed.
Additional writes to the already programmed pages are prohibited.
Start
Write 4116
n = 0
Write address n and
n = n + 2
data n
NO
n = FE16
YES
NO
RY/BY status flag
= 1?
YES
Check full status
Page program
completed
Figure 1.24.4. Page program flowchart
233
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Block Erase Command (2016/D016)
By writing the command code "2016" in the 1st bus cycle and the confirmation command code "D016"
in the 2nd bus cycle that follows to the block address of a flash memory block, the system initiates an
auto erase (erase and erase verify) operation.
Whether the auto erase operation is completed can be confirmed by reading the status register or the
flash memory control register 0. At the same time the auto erase operation starts, the read status
register mode is automatically entered, so the content of the status register can be read out. The
status register bit 7 (SR7) is set to "0" at the same time the auto erase operation starts and is returned
to "1" upon completion of the auto erase operation. In this case, the read status register mode remains
active until the read array command (FF16) or the read lock bit status command (7116) is written or the
flash memory is reset using its reset bit.
____
The RY/BY status flag of the flash memory control register 0 is "0" during auto erase operation and "1"
when the auto erase operation is completed as is the status register bit 7.
After the auto erase operation is completed, the status register can be read out to know the result of
the auto erase operation. For details, refer to the section where the status register is detailed.
Figure 1.24.5 shows an example of a block erase flowchart.
Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer
to the section where the data protect function is detailed.
Start
Write 2016
Write D016
Block address
NO
RY/BY status flag
= 1?
YES
Check full status
check(Note)
Error
Erase error
Block erase
completed
Note: Refer to Figure 1.24.8.
Figure 1.24.5. Block erase flowchart
234
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Erase All Unlocked Blocks Command (A716/D016)
By writing the command code "A716" in the 1st bus cycle and the confirmation command code "D016"
in the 2nd bus cycle that follows, the system starts erasing blocks successively.
Whether the erase all unlock blocks command is terminated can be confirmed by reading the status
register or the flash memory control register 0, in the same way as for block erase. Also, the status
register can be read out to know the result of the auto erase operation.
When the lock bit disable select bit of the flash memory control register 0 is "1", all blocks are erased
no matter how the lock bit is set. On the other hand, when the lock bit disable select bit is "0", the
function of the lock bit is effective and only nonlocked blocks (where lock bit data is "1") are erased.
Lock Bit Program Command (7716/D016)
By writing the command code "7716" in the 1st bus cycle and the confirmation command code "D016"
in the 2nd bus cycle that follows to the block address of a flash memory block, the system sets the lock
bit for the specified block to "0" (locked).
Figure 1.24.6 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit
data) can be read out by a read lock bit status command.
Whether the lock bit program command is terminated can be confirmed by reading the status register
or the flash memory control register 0, in the same way as for page program.
For details about the function of the lock bit and how to reset the lock bit, refer to the section where the
data protect function is detailed.
Start
Write 7716
Write D016
block address
NO
RY/BY status flag
= 1?
YES
NO
Lock bit program in
error
SR4 = 0?
YES
Lock bit program
completed
Figure 1.24.6. Lock bit program flowchart
235
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Read Lock Bit Status Command (7116)
By writing the command code "7116" in the 1st bus cycle and then reading the block address of a flash
memory block in the 2nd bus cycle that follows, the system reads out the status of the lock bit of the
specified block on to the data bus (D6).
Figure 1.24.7 shows an example of a read lock bit program flowchart.
Start
Write 7116
Enter block address
(Note)
NO
D
6
= 0?
YES
Blocks locked
Blocks not locked
Note: Data bus bit 6.
Figure 1.24.7. Read lock bit status flowchart
236
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Data Protect Function (Block Lock)
Each block in Figure 1.23.1 has a nonvolatile lock bit to specify that the block be protected (locked)
against erase/write. The lock bit program command is used to set the lock bit to "0" (locked). The lock bit
of each block can be read out using the read lock bit status command.
Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash
memory control register 0's lock bit disable select bit is set.
(1) When the lock bit disable select bit is "0", a specified block can be locked or unlocked by the lock bit
status (lock bit data). Blocks whose lock bit data is "0" are locked, so they are disabled against
erase/write. On the other hand, the blocks whose lock bit data is "1" are not locked, so they are
enabled for erase/write.
(2) When the lock bit disable select bit is "1", all blocks are nonlocked regardless of the lock bit data, so
they are enabled for erase/write. In this case, the lock bit data that is "0" (locked) is set to "1"
(nonlocked) after erasure, so that the lock bit actuated lock is removed.
Status Register
The status register indicates the operating status of the flash memory and whether an erase or program
operation has terminated normally or in an error. The content of this register can be read out by only
writing the read status register command (7016). Table 1.24.2 details the status register.
The status register is cleared by writing the clear status register command (5016).
After a reset, the status register is set to "8016."
Each bit in this register is explained below.
Write State Machine (WSM) Status (SR7)
After power on, the write state machine (WSM) status is set to "1".
The write state machine (WSM) status indicates the operating status of the device, as for output on the
____
RY/BY pin. This status bit is set to "0" during auto write or auto erase operation and is set to "1" upon
completion of these operations.
Erase Status (SR5)
The erase status informs the operating status of auto erase operation to the CPU. When an erase
error occurs, it is set to "1".
The erase status is reset to "0" when cleared.
237
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Program Status (SR4)
The program status informs the operating status of auto write operation to the CPU. When a write
error occurs, it is set to "1".
The program status is reset to "0" when cleared.
When an erase command is in error (which occurs if the command entered after the block erase
command (2016) is not the confirmation command (D016), both the program status and erase status
(SR5) are set to "1".
When the program status or erase status is "1", only the following flash commands will be accepted:
Read Array, Read Status Register, and Clear Status Register.
Also, in one of the following cases, both SR4 and SR5 are set to "1" (command sequence error):
(1) When the valid command is not entered correctly
(2) When the data entered in the 2nd bus cycle of lock bit program (7716/D016), block erase (2016/
D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is entered,
read array is assumed and the command that has been set up in the 1st bus cycle is canceled.
Block Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), "1" is set for the program status after program at the end of the page
write operation. In other words, when writing ends successfully, "8016" is output; when writing fails,
"9016" is output; and when excessive data is written, "8816" is output.
Table 1.24.2. Definition of each bit in status register
Definition
Each bit of
SRD
Status name
"1"
Ready
-
"0"
Busy
-
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Write state machine (WSM) status
Reserved
Erase status
Terminated normally
Terminated in error
Program status
Block status after program
Reserved
Terminated normally
Terminated in error
Terminated normally
Terminated in error
-
-
-
-
-
-
Reserved
Reserved
238
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU Rewrite Mode (Flash Memory Version)
Full Status Check
By performing full status check, it is possible to know the execution results of erase and program opera-
tions. Figure 1.24.8 shows a full status check flowchart and the action to be taken when each error
occurs.
Read status register
YES
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
SR4=1 and SR5
=1 ?
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Block erase error
Program error (page
or lock bit)
Execute the read lock bit status command (7116
)
SR4=0?
YES
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
Program error
(block)
NO
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to "1", none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 1.24.8. Full status check flowchart and remedial procedure for errors
239
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function to Inhibit Rewriting Flash Memory Version (Flash Memory Version)
Functions to Inhibit Rewriting Flash Memory Version
To prevent the contents of the flash memory version from being read out or rewritten easily, the device
incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
ROM Code Protect Function
The ROM code protect function is used to prohibit reading out or modifying the contents of the flash
memory during parallel I/O mode and is set by using the ROM code protect control address register
(0FFFFF16). Figure 1.25.1 shows the ROM code protect control address (0FFFFF16). (This address ex-
ists in the user ROM area.)
If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents
of the flash memory version are protected against readout and modification. ROM code protect is imple-
mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is
selected by default.
If both of the two ROM code protect reset bits are set to "00", ROM code protect is turned off, so that the
contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,
the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/
O or some other mode to rewrite the contents of the ROM code protect reset bits.
ROM code protect control address
Symbol
ROMCP
Address
0FFFFF16
When reset
FF16
b7 b6 b5 b4 b3 b2 b1 b0
1
1
Bit symbol
Bit name
Function
Always set this bit to "1".
Reserved bits
b3 b2
ROM code protect level
2 set bit (Note 1, 2)
ROMCP2
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
b5 b4
ROM code protect reset
bit (Note 3)
ROMCR
00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective
b7 b6
ROM code protect level
1 set bit (Note 1)
ROMCP1
00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled
Note 1: When ROM code protect is turned on, the internal memory is protected against readout
or modification in parallel input/output mode.
Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and
ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.
Figure 1.25.1. ROM code protect control address
240
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function to Inhibit Rewriting Flash Memory Version (Flash Memory Version)
ID Code Check Function
Use this function in standard serial I/O and CAN I/O modes. When the contents of the flash memory are
not blank, the ID code sent from the peripheral unit is compared with the ID code written in the flash
memory to see if they match. If the ID codes do not match, the commands sent from the peripheral unit
are not accepted. The ID code consists of 8 bit data, the areas of which, beginning with the 1st byte, are
0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. Write a program
which has had the ID code preset at these addresses to the flash memory.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Oscilation stop detection/Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
4 bytes
Figure 1.25.2. ID code store addresses
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Parallel I/O Mode (Flash Memory Version)
Parallel I/O Mode
The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate
(read, program, erase, etc.) the internal flash memory. This I/O is parallel.
Use an exclusive programmer supporting M16C/6N group (flash memory version).
Refer to the instruction manual of each programer maker for the datails of use.
User ROM and Boot Rom Areas
In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.23.1 can be rewritten. Both
areas of flash memory can be operated on in the same way.
Program and block erase operations can be performed in the user ROM area. The user ROM area and its
blocks are shown in Figure 1.23.1.
The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FE00016 through
0FFFFF16. Make sure program and block erase operations are always performed within this address
range. (Access to any location outside this address range is prohibited.)
In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area
has had a standard serial I/O and CAN I/O modes. control program stored in it when shipped from the
Mitsubishi factory. Therefore, using the device in standard serial input/output and CAN I/O modes, you do
not need to write to the boot ROM area.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
Pin Functions (Flash memory standard serial I/O mode)
Name
Description
Pin
I/O
Apply program/erase protection voltage to VCC pin and 0 V to VSS pin.
Power input
VCC,VSS
Connect to VCC pin.
CNVSS
CNVSS
RESET
I
I
Reset input
Reset input pin. While reset is "L" level, more than 20cycles of clock
must be input to XIN pin.
XIN
Connect a ceramic resonator or a quartz crystal oscillator between XIN
and XOUT pins. To input an externally generated clock, input it to XIN pin
and open XOUT pin.
Clock input
I
O
I
XOUT
Clock output
BYTE
Connect to VSS or VCC.
BYTE
AVCC, AVSS
VREF
Analog power supply input
Reference voltage input
Input port P0
Connect AVSS to VSS and AVCC to VCC, respectively.
Reference voltage input pin for AD converter.
Input "H" or "L" level or open.
I
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
I
I
I
I
I
I
Input "H" or "L" level or open.
Input "H" or "L" level or open.
Input "H" or "L" level or open.
Input "H" or "L" level or open.
Input "H" or "L" level or open.
Input port P1
Input port P2
Input port P3
Input port P4
P51 to P54,
P56, P57
Input port P5
Input "H" level.
Input "L" level.
P50
P55
CE input
I
EPM input
Input port P6
BUSY output
I
I
P60 to P63
P64
Input "H" or "L" level or open.
Standard serial I/O mode 1: BUSY signal output pin.
Standard serial I/O mode 2: Monitors the boot program operation.
check signal output pin.
O
Standard serial I/O mode 1: Serial clock input pin.
Standard serial I/O mode 2: Input "L" level.
P65
P66
SCLK input
I
RxD input
Serial data input pin.
I
P67
TxD output
Input port P7
O
Serial data output pin.
Input "H" or "L" level or open.
P70 to P77
I
I
I
I
P80 to P84, P86,
P87
Input "H" or "L" level or open.
Input port P8
NMI input
P85
Connect to VCC.
Input "H" or "L" level or open.
P90 to P94, P97
P95
Input port P9
CAN input
Connect to a CAN transceiver or input "H" or "L" level.
Connect to a CAN transceiver, connect to VCC via a resister or open.
Input "H" or "L" level or open.
I
P96
CAN output
Input port P10
O
P100 to P107
I
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
Mode setup method
Signal
Value
CNVss
EPM
Vcc
Vss
RESET
CE
Vss to Vcc
Vcc
P9
6
/ANEX1/CTX
0
0
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
0
/D
8
9
P9
5
/ANEX0/CRX
1/D
P9
P9
P9
P9
P9
4
/DA
/DA
1
/TB4IN
/TB3IN
2
3
4
/D10
/D11
/D12
/D13/INT3
/D14/INT4
/D15/INT5
/A
/A
/A
/A
/A
/A
/A
/A
3
0
2/TB2IN/SOUT
3
3
1/TB1IN/SIN
5
0
/TB0IN/CLK3
BYTE
6
7
CNVss
CNVss
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
(/D
(/D
(/D
(/D
(/D
(/D
(/D
(/D
0
1
2
3
4
5
6
7
/-)
/D
/D
/D
/D
/D
/D
/D
P8
P8 /XCOUT
RESET
7/XCIN
0
1
2
3
4
5
6
)
)
)
)
)
)
)
6
RESET
X
OUT
V
SS
X
IN
M306NAFGTFP
(100P6S)
V
CC
P8
P8
P8
P8
5
/NMI
/INT
/INT
/INT
Vss
P3
Vcc
P3
4
2
0
/A
8
(/-/D
7)
3
1
0
2
1/A
9
P8
P8 /TA4OUT/U
P7 /TA3IN/CRX
P7 /TA3OUT/CTX
P7
P7 /TA2OUT/W
/RTS /TA1IN/V
/CLK /TA1OUT/V
/SCL/TA0IN/TB5IN
/T /SDA/TA0OUT
1/TA4IN/U
P3
2/A10
3/A11
4/A12
5/A13
6/A14
7/A15
0/A16
1/A17
2/A18
3/A19
0
P3
P3
P3
P3
P3
P4
P4
P4
P4
7
1
1
6
5
/TA2IN/W
4
P7
3
/CTS
P7
/RxD
P7
2
2
2
2
P7
1
2
0
XD2
Figure 1.27.1. Pin connections for serial I/O mode
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode (Flash Memory Version)
Standard Serial I/O Mode
The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to
operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two
standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both
modes require a purpose specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory
rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-
_____
________
leased, which is done when the P50 (CE) pin is "H" level, the P55 (EPM) pin "L" level and the CNVss pin "H"
level. (In the ordinary command mode, set CNVss pin to "L" level.)
This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-
ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is
rewritten in the parallel I/O mode. Figure 1.27.1 shows the pin connections for the standard serial I/O mode.
Serial data I/O uses UART1 and transfers the data serially in 8 bit units. Standard serial I/O switches
between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of CLK1 pin
when the reset is released.
To use standard serial I/O mode 1 (clock synchronized), set the CLK1 pin to "H" level and release the reset.
The operation uses the four UART1 pins CLK1, RxD1, TxD1 and RTS1 (BUSY). The CLK1 pin is the transfer
clock input pin through which an external transfer clock is input. The TxD1 pin is for CMOS output. The
RTS1 (BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.
To use standard serial I/O mode 2 (clock asynchronized), set the CLK1 pin to "L" level and release the
reset. The operation uses the two UART1 pins RxD1 and TxD1.
In the standard serial I/O mode, only the user ROM area indicated in Figure 1.28.17 can be rewritten. The
boot ROM cannot.
In the standard serial I/O mode, a 7 byte ID code is used. When there is data in the flash memory, com-
mands sent from the peripheral unit are not accepted unless the ID code matches.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Overview of Standard Serial I/O Mode 1 (Clock Synchronized)
In standard serial I/O mode 1, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 4 wire clock synchronized serial I/O (UART1).
Standard serial I/O mode 1 is engaged by releasing the reset with the P65 (CLK1) pin "H" level.
In reception, software commands, addresses and program data are synchronized with the rise of the
transfer clock that is input to the CLK1 pin, and are then input to the MCU via the RxD1 pin. In transmis-
sion, the read data and status are synchronized with the fall of the transfer clock, and output from the
TxD1 pin.
The TxD1 pin is for CMOS output. Transfer is in 8 bit units with LSB first.
When busy, such as during transmission, reception, erasing or program execution, the RTS1 (BUSY) pin
is "H" level. Accordingly, always start the next transfer after the RTS1 (BUSY) pin is "L" level.
Also, data and status registers in memory can be read after inputting software commands. Status, such
as the operating state of the flash memory or whether a program or erase operation ended successfully or
not, can be checked by reading the status register. Here following are explained software commands,
status registers, etc.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Software Commands
Table 1.28.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Software commands are
explained here below.
Table 1.28.1. Software commands (Standard serial I/O mode 1)
When ID is
not verified
1st byte
transfer
Control command
Page read
2nd byte 3ne byte 4th byte 5th byte 6th byte
Data
output to
259th byte
Data
input to
259th byte
Address Address
(middle) (high)
Data
output
Data
output
Data
output
Not
acceptable
1
2
FF16
Address Address
(middle) (high)
Data
input
Data
input
Data
input
Not
acceptable
Page program
4116
Address Address
Not
acceptable
Not
3
4
5
6
Block erase
2016
A716
7016
5016
D016
(middle)
(high)
Erase all unlocked blocks
Read status register
Clear status register
D016
acceptable
SRD
output
SRD1
output
Acceptable
Not
acceptable
Lock bit
data
output
Address Address
(middle) (high)
Not
acceptable
7
Read lock bit status
7116
Address Address
(middle) (high)
Not
acceptable
Not
acceptable
Not
8
9
Lock bit program
Lock bit enable
7716
7A16
7516
F516
D016
10 Lock bit disable
11 ID check function
acceptable
Address Address Address
ID size
ID 1
To ID 7
Acceptable
(low)
(middle)
(high)
To
Not
acceptable
Size
(low)
Size
(high)
Check-
sum
Data
input
required
number
of times
12 Download function
FA16
FB16
Version
data
output to
9th byte
Data
output to
259th byte
Version
data
output
Version Version
Version
data
output
Version
data
output
Version information output
13
data
output
data
output
Acceptable
function
Boot ROM area output
function
Address Address
(middle)
Data
output
Data
output
Data
output
Not
acceptable
14
FC16
FD16
(high)
Check
data
(low)
Check
data
(high)
Not
acceptable
15 Read check data
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register 1 data.
Note 3:All commands can be accepted when the flash memory is totally blank.
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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the "FF16" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8
to A23 will be output sequentially from the smallest address first in sync with the fall of the clock.
CLK
1
1
A
8
to
A
16 to
RxD
FF16
A
15
A23
(M16C reception data)
TxD
1
data0
data255
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.1. Timing for page read
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the "4116" command code with the 1st byte.
(2) Transfer addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
0
to D ) for the page (256 bytes) specified with addresses
7
A8
When reception setup for the next 256 bytes ends, the RTS1 (BUSY) signal changes from the "H" to
the "L" level. The result of the page program can be known by reading the status register. For more
information, see the section on the status register.
Each block can be write-protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
CLK
1
1
RxD
A
8
to
A
16 to
4116
data0
data255
(M16C reception data)
A
15
A23
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.2. Timing for the page program
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Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the "2016" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A8 to A23.
When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. After block
erase ends, the result of the block erase operation can be known by reading the status register. For
more information, see the section on the status register.
Each block can be erase protected with the lock bit. For more information, see the section on the data
protection function.
CLK
1
1
RxD
A
8
to
A
16 to
2016
D016
A
15
A23
(M16C reception data)
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.3. Timing for block erasing
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the "A716" command code with the 1st byte.
(2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
When block erasing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. The result of the
erase operation can be known by reading the status register. Each block can be erase protected with the
lock bit. For more information, see the section on the data protection function.
CLK
1
1
RxD
A716
D016
(M16C reception data)
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.4. Timing for erasing all unlocked blocks
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Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Read Status Register Command
This command reads status information. When the "7016" command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
CLK
1
1
RxD
7016
(M16C reception data)
SRD
output
SRD1
output
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.5. Timing for reading the status register
Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when the status register operation ends in
error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared.
When the clear status register operation ends, the RTS1 (BUSY) signal changes from the "H" to the
"L" level.
CLK
1
1
RxD
5016
(M16C reception data)
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.6. Timing for clearing the status register
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Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the "7116" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th
bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to
A23.
CLK
1
1
A
8
to
A
16 to
RxD
7116
A
15
A23
(M16C reception data)
TxD
1
D6
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.7. Timing for reading lock bit status
Lock Bit Program Command
This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the "7716" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
When writing ends, the RTS1 (BUSY) signal changes from the "H" to the "L" level. Lock bit status can
be read with the read lock bit status command. For information on the lock bit function, reset proce-
dure and so on, see the section on the data protection function.
CLK
1
RxD
1
A
8
to
A
16 to
7716
D016
A
15
A23
(M16C reception data)
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.8. Timing for the lock bit program
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Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code "7A16" is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.
CLK
1
1
RxD
7A16
(M16C reception data)
TxD
1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.9. Timing for enabling the lock bit
Lock Bit Disable Command
This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, "0" (locked)
lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
CLK1
RxD1
7516
(M16C reception data)
TxD1
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.10. Timing for disabling the lock bit
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Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
ID Check Function Command
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the "F516" command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
CLK
1
1
RxD
ID size
ID1
ID7
F516
DF16
FF16
0F16
(M16C reception
data)
TxD
(M16C transmission
data)
1
RTS1 (BUSY)
Figure 1.28.11. Timing for the ID check
Download Function Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the "FA16" command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
CLK
1
1
RxD
Program Program
data
data
Check
sum
FA16
Data size (low)
(M16C reception data)
TxD
1
Data size (high)
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.12. Timing for download
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Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Version Information Output Function Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the "FB16" command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
CLK
1
1
RxD
FB16
(M16C reception data)
TxD
1
’V’
’E’
’R’
’X’
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.13. Timing for version information output
Boot ROM Area Output Function Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the "FC16" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8
to A23 will be output sequentially from the smallest address first, in sync with the fall of the clock.
CLK1
RxD1
A8 to
A15
A16 to
A23
FC16
(M16C reception data)
TxD1
data0
data255
(M16C transmission data)
RTS1 (BUSY)
Figure 1.28.14. Timing for boot ROM area output
254
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Read Check Data Command
This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.
To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write data.
CLK
1
1
RxD
FD16
(M16C reception data)
TxD
1
(M16C transmission data)
Check data (high)
Check data (low)
RTS1 (BUSY)
Figure 1.28.15. Timing for the read check data
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write
a program into the flash memory, which already has the ID code set for these addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Oscilation stop detection/Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
4 bytes
Figure 1.28.16. ID code storage addresses
255
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Data Protection Function (Block Lock)
Each of the blocks in Figure 1.28.17 have a nonvolatile lock bit that specifies protection (block lock)
against erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command.
Also, the lock bit of any block can be read with the read lock bit status command.
Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock
bit disable and lock enable bit commands.
(1) After the reset has been cancelled and the lock bit enable command executed, the specified block
can be locked/unlocked using the lock bit (lock bit data). Blocks with a "0" lock bit data are locked
and cannot be erased or written in. On the other hand, blocks with a "1" lock bit data are unlocked
and can be erased or written in.
(2) After the lock bit disable command has been executed, all blocks are unlocked regardless of lock bit
data status and can be erased or written in. In this case, lock bit data that was "0" (locked) before the
block was erased is set to "1" (unlocked) after erasing, therefore the block is actually unlocked with
the lock bit.
0C000016
Block 6 : 64K byte
0D000016
Block 5 : 64K byte
0E000016
Block 4 : 64K byte
0F000016
Block 3 : 32K byte
Flash memory
size
Flash memory
start address
0F800016
0FA00016
Block 2 : 8K byte
Block 1 : 8K byte
Block 0 : 16K byte
256Kbytes
0C000016
128Kbytes
0E000016
0FC00016
0FFFFF16
User ROM area
Figure 1.28.17. Blocks in the user area
256
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase
operation or a program ended successfully or in error. It can be read by writing the read status register
command (7016). Also, the status register is cleared by writing the clear status register command (5016).
Table 1.28.2 gives the definition of each status register bit. After clearing the reset, the status register
outputs "8016".
Table 1.28.2. Status register (SRD)
Definition
SRD bits
Status name
"1"
"0"
Write state machine (WSM) status
Reserved
Ready
Busy
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
-
-
Erase status
Terminated in error
Terminated normally
Program status
Block status after program
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
Reserved
Reserved
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When
power is turned on, "1" (ready) is set for it. The bit is set to "0" (busy) during an auto write or auto erase
operation, but it is set back to "1" when the operation ends.
Erase Status (SR5)
The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is
set to "1". When the erase status is cleared, it is set to "0".
Program Status (SR4)
The program status reports the operating status of the auto write operation. If a write error occurs, it is
set to "1". When the program status is cleared, it is set to "0".
Block Status After Program (SR3)
If excessive data is written (phenomenon whereby the memory cell becomes depressed which results
in data not being read correctly), "1" is set for the block status after program at the end of the page
write operation. In other words, when writing ends successfully, "8016" is output; when writing fails,
"9016" is output; and when excessive data is written, "8816" is output.
If "1" is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked
blocks and lock bit program commands are not accepted. Before executing these commands, execute
the clear status register command (5016) and clear the status register.
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M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communications, results from ID checks and results from
check sum comparisons. It can be read after the SRD by writing the read status register command (7016).
Also, status register 1 is cleared by writing the clear status register command (5016).
Table 1.28.3 gives the definition of each status register 1 bit. "0016" is output when power is turned ON
and the flag status is maintained even after the reset.
Table 1.28.3. Status register 1 (SRD1)
Definition
SRD1 bits
Status name
"1"
"0"
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
SR11 (bit3)
SR10 (bit2)
Boot update completed bit
Reserved
Not update
Update completed
-
-
-
Reserved
-
Check sum match bit
ID check completed bits
Mismatch
Match
00
01
10
11
Not verified
Verification mismatch
Reserved
Verified
SR9 (bit1)
SR8 (bit0)
Data receive time out
Reserved
Normal operation
-
Time out
-
Boot Update Completed Bit (SR15)
This flag indicates whether the control program was downloaded to the RAM or not, using the down-
load function.
Check Sum Match Bit (SR12)
This flag indicates whether the check sum matches or not when a program, is downloaded for execu-
tion using the download function.
ID Check Completed Bits (SR11 and SR10)
These flags indicate the result of ID checks. Some commands cannot be accepted without an ID
check.
Data Receive Time Out (SR9)
This flag indicates when a time out error is generated during data reception. If this flag is attached
during data reception, the received data is discarded and the microcomputer returns to the command
wait state.
258
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Full Status Check
Results from executed erase and program operations can be known by running a full status check. Figure
1.28.18 shows a flowchart of the full status check and explains how to remedy errors which occur.
Read status register
YES
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
SR4=1 and SR5
=1 ?
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Block erase error
Program error (page
or lock bit)
Execute the read lock bit status command (7116
)
SR4=0?
YES
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
Program error
(block)
NO
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to "1", none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 1.28.18. Full status check flowchart and remedial procedure for errors
259
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 1 (Flash Memory Version)
Example Circuit Application for the Standard Serial I/O Mode 1
The below figure shows a circuit application for the standard serial I/O mode 1. Control pins will vary
according to programmer, therefore see the peripheral unit manual for more information.
Clock input
BUSY output
Data input
CLK1
RTS1(BUSY)
RXD1
TXD1
Data output
CNVss
M16C/6N Group
(Flash memory version)
P85(NMI)
RESET
CAN transceiver
CAN H
P95(CRX)
CAN H
CAN L
CAN L
P96(CTX)
P50(CE)
P55(EPM)
(1) Control pins and external circuitry will vary according to peripheral unit.
For more information, see the peripheral unit manual.
(2) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.
Figure 1.28.19. Example circuit application for the standard serial I/O mode 1
260
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Overview of Standard Serial I/O Mode 2 (Clock Asynchronized)
In standard serial I/O mode 2, software commands, addresses and data are input and output between the
MCU and peripheral units (serial programer, etc.) using 2 wire clock asynchronized serial I/O (UART1).
Standard serial I/O mode 2 is engaged by releasing the reset with the P65 (CLK1) pin "L" level.
The TxD1 pin is for CMOS output. Data transfer is in 8 bit units with LSB first, 1 stop bit and parity off.
After the reset is released, connections can be established at 9,600 bps when initial communications are
made with a peripheral unit. However, this requires a main clock with 10 MHz or 16 MHz input oscillation
frequency. Baud rate can also be changed from 9,600 bps, 19,200 bps or 38,400 bps by executing
software commands. However, communication errors may occur because of the oscillation frequency of
the main clock. If errors occur, change the main clock's oscillation frequency and the baud rate.
After executing commands from a peripheral unit that requires time to erase and write data, as with erase
and program commands, allow a sufficient time interval or execute the read status command and check
how processing ended, before executing the next command.
Data and status registers in memory can be read after transmitting software commands. Status, such as
the operating state of the flash memory or whether a program or erase operation ended successfully or
not, can be checked by reading the status register. Here following are explained the operation frequency
and the baud rate, how frequency is identified and software commands.
261
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M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Table 1.29.1. Operation frequency and the baud rate
Operation frequency
(MH
Baud rate
9,600bps
Baud rate
19,200bps
Baud rate
38,400bps
Z)
16MH
Z
Z
√
√
√
√
√
—
10MH
√ : Communications possible
— : Communications not possible
262
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Software Commands
Table 1.29.2 lists software commands. In the standard serial I/O mode 2, erase operations, programs and
reading are controlled by transferring software commands via the RxD1 pin. Standard serial I/O mode 2
adds three transmission speed commands 9,600, 19,200 and 38,400 bps to the software commands of
standard serial I/O mode 1. Software commands are explained here below.
Table 1.29.2. Software commands (Standard serial I/O mode 2)
When ID is
not verified
1st byte
transfer
Control command
Page read
2nd byte 3ne byte 4th byte 5th byte 6th byte
Data
output to
259th byte
Data
input to
259th byte
Address Address
(middle) (high)
Data
output
Data
output
Data
output
Not
acceptable
1
2
FF16
Address Address
(middle) (high)
Data
input
Data
input
Data
input
Not
acceptable
Page program
4116
Address Address
Not
acceptable
Not
3
4
5
6
Block erase
2016
A716
7016
5016
D016
(middle)
(high)
Erase all unlocked blocks
Read status register
Clear status register
D016
acceptable
SRD
output
SRD1
output
Acceptable
Not
acceptable
Lock bit
data
output
Address Address
(middle) (high)
Not
acceptable
7
Read lock bit status
7116
Address Address
(middle) (high)
Not
acceptable
Not
acceptable
Not
8
9
Lock bit program
Lock bit enable
7716
7A16
7516
F516
D016
10 Lock bit disable
11 ID check function
acceptable
Address Address Address
ID size
ID 1
To ID 7
Acceptable
(low)
(middle)
(high)
To
Not
acceptable
Size
(low)
Size
(high)
Check-
sum
Data
input
required
number
of times
12 Download function
FA16
FB16
Version
data
output to
9th byte
Data
output to
259th byte
Version
data
output
Version Version
Version
data
output
Version
data
output
Version information output
13
data
output
data
output
Acceptable
function
Boot ROM area output
function
Address Address
(middle)
Data
output
Data
output
Data
output
Not
acceptable
14
FC16
FD16
(high)
Check
data
(low)
B016
B116
B216
Check
data
(high)
Not
acceptable
15 Read check data
16 Baud rate 9600
17 Baud rate 19200
18 Baud rate 38400
B016
B116
B216
Acceptable
Acceptable
Acceptable
Note 1:Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-
ferred from the peripheral unit to the flash memory microcomputer.
Note 2:SRD refers to status register data. SRD1 refers to status register 1 data.
Note 3:All commands can be accepted when the flash memory is totally blank.
263
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M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Page Read Command
This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page read command as explained here following.
(1) Transfer the "FF16" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8
to A23 will be output sequentially from the smallest address first.
A8 to
A15
A16 to
A23
RxD1
FF16
(M16C reception data)
TxD1
data0
data255
(M16C transmission data)
Figure 1.29.1. Timing for page read
Page Program Command
This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a
time. Execute the page program command as explained here following.
(1) Transfer the "4116" command code with the 1st byte.
(2) Transfer addresses A
(3) From the 4th byte onward, as write data (D
to A23 is input sequentially from the smallest address first, that page is automatically written.
8
to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
0
to D ) for the page (256 bytes) specified with addresses
7
A
8
The result of the page program can be known by reading the status register. For more information, see
the section on the status register.
Each block can be write protected with the lock bit. For more information, see the section on the data
protection function. Additional writing is not allowed with already programmed pages.
RxD1
A8 to A16 to
A15 A23
4116
data0
data255
(M16C reception data)
TxD1
(M16C transmission data)
Figure 1.29.2. Timing for the page program
264
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Block Erase Command
This command erases the data in the specified block. Execute the block erase command as explained
here following.
(1) Transfer the "2016" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, the
erase operation will start for the specified block in the flash memory. Write the highest address of
the specified block for addresses A8 to A23.
After block erase ends, the result of the block erase operation can be known by reading the status
register. For more information, see the section on the status register.
Each block can be erase protected with the lock bit. For more information, see the section on the data
protection function.
RxD1
A8 to
A15
A16 to
A23
2016
D016
(M16C reception data)
TxD1
(M16C transmission data)
Figure 1.29.3. Timing for block erasing
Erase All Unlocked Blocks Command
This command erases the content of all blocks. Execute the erase all unlocked blocks command as
explained here following.
(1) Transfer the "A716" command code with the 1st byte.
(2) Transfer the verify command code "D016" with the 2nd byte. With the verify command code, the
erase operation will start and continue for all blocks in the flash memory.
The result of the erase operation can be known by reading the status register. Each block can be erase-
protected with the lock bit. For more information, see the section on the data protection function.
RxD
1
A716
D016
(M16C reception data)
TxD
1
(M16C transmission data)
Figure 1.29.4. Timing for erasing all unlocked blocks
265
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Read Status Register Command
This command reads status information. When the "7016" command code is sent with the 1st byte, the
contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1
(SRD1) specified with the 3rd byte are read.
RxD
1
7016
(M16C reception data)
SRD
output
SRD1
output
TxD
1
(M16C transmission data)
Figure 1.29.5. Timing for reading the status register
Clear Status Register Command
This command clears the bits (SR3 to SR5) which are set when the status register operation ends in
error. When the "5016" command code is sent with the 1st byte, the aforementioned bits are cleared.
RxD
1
5016
(M16C reception data)
TxD
1
(M16C transmission data)
Figure 1.29.6. Timing for clearing the status register
266
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Read Lock Bit Status Command
This command reads the lock bit status of the specified block. Execute the read lock bit status com-
mand as explained here following.
(1) Transfer the "7116" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th
bit(D6) of the output data. Write the highest address of the specified block for addresses A8 to
A23.
A
8
to
A16 to
A23
RxD
1
7116
A
15
(M16C reception data)
TxD
1
D6
(M16C transmission data)
Figure 1.29.7. Timing for reading lock bit status
Lock Bit Program Command
This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program
command as explained here following.
(1) Transfer the "7716" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) Transfer the verify command code "D016" with the 4th byte. With the verify command code, "0" is
written for the lock bit of the specified block. Write the highest address of the specified block for
addresses A8 to A23.
Lock bit status can be read with the read lock bit status command. For information on the lock bit
function, reset procedure and so on, see the section on the data protection function.
RxD
1
A
8
to
A16 to
A23
7716
D016
A
15
(M16C reception data)
TxD
1
(M16C transmission data)
Figure 1.29.8. Timing for the lock bit program
267
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Lock Bit Enable Command
This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-
mand. The command code "7A16" is sent with the 1st byte of the serial transmission. This command
only enables the lock bit function; it does not set the lock bit itself.
RxD
1
7A16
(M16C reception data)
TxD
1
(M16C transmission data)
Figure 1.29.9. Timing for enabling the lock bit
Lock Bit Disable Command
This command disables the lock bit. The command code "7516" is sent with the 1st byte of the serial
transmission. This command only disables the lock bit function; it does not set the lock bit itself.
However, if an erase command is executed after executing the lock bit disable command, "0" (locked)
lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is
cancelled, the lock bit is enabled.
RxD
1
7516
(M16C reception data)
TxD
1
(M16C transmission data)
Figure 1.29.10. Timing for disabling the lock bit
268
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
ID Check Function Command
This command checks the ID code. Execute the boot ID check command as explained here following.
(1) Transfer the "F516" command code with the 1st byte.
(2) Transfer addresses A0 to A7, A8 to A15 and A16 to A23 of the 1st byte of the ID code with the 2nd,
3rd and 4th bytes respectively.
(3) Transfer the number of data sets of the ID code with the 5th byte.
(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.
RxD
(M16C reception
data)
1
ID size
ID1
ID7
F516
DF16
FF16
0F16
TxD
(M16C transmission
data)
1
Figure 1.29.11. Timing for the ID check
Download Function Command
This command downloads a program to the RAM for execution. Execute the download command as
explained here following.
(1) Transfer the "FA16" command code with the 1st byte.
(2) Transfer the program size with the 2nd and 3rd bytes.
(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th
byte onward.
(4) The program to execute is sent with the 5th byte onward.
When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.
RxD1
Program Program
data
data
Check
sum
FA16
Data size (low)
(M16C reception data)
TxD1
Data size (high)
(M16C transmission data)
Figure 1.29.12. Timing for download
269
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Version Information Output Function Command
This command outputs the version information of the control program stored in the boot area. Execute
the version information output command as explained here following.
(1) Transfer the "FB16" command code with the 1st byte.
(2) The version information will be output from the 2nd byte onward. This data is composed of 8
ASCII code characters.
RxD1
FB16
(M16C reception data)
TxD1
’V’
’E’
’R’
’X’
(M16C transmission data)
Figure 1.29.13. Timing for version information output
Boot ROM Area Output Function Command
This command outputs the control program stored in the boot ROM area in one page blocks (256
bytes). Execute the boot ROM area output command as explained here following.
(1) Transfer the "FC16" command code with the 1st byte.
(2) Transfer addresses A8 to A15 and A16 to A23 with the 2nd and 3rd bytes respectively.
(3) From the 4th byte onward, data (D0 to D7) for the page (256 bytes) specified with addresses A8
to A23 will be output sequentially from the smallest address first.
RxD
1
A
8
to
A16 to
A23
FC16
A
15
(M16C reception data)
TxD
1
data0
data255
(M16C transmission data)
Figure 1.29.14. Timing for boot ROM area output
270
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Read Check Data Command
This command reads the check data that confirms that the write data, which was sent with the page
program command, was successfully received.
(1) Transfer the "FD16" command code with the 1st byte.
(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.
To use this read check data command, first execute the command and then initialize the check data.
Next, execute the page program command the required number of times. After that, when the read
check command is executed again, the check data for all of the read data that was sent with the page
program command during this time is read. The check data is the result of CRC operation of write
data.
RxD1
FD16
(M16C reception data)
TxD1
(M16C transmission data)
Check data (high)
Check data (low)
Figure 1.29.15. Timing for the read check data
Baud Rate 9600 Command
This command changes baud rate to 9,600 bps. Execute it as follows.
(1) Transfer the "B016" command code with the 1st byte.
(2) After the "B016" check code is output with the 2nd byte, change the baud rate to 9,600 bps.
RxD1
B016
(M16C reception data)
TxD1
B016
(M16C transmission data)
Figure 1.29.16. Timing of baud rate 9600
271
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Baud Rate 19200 Command
This command changes baud rate to 19,200 bps. Execute it as follows.
(1) Transfer the "B116" command code with the 1st byte.
(2) After the "B116" check code is output with the 2nd byte, change the baud rate to 19,200 bps.
RxD
1
B116
(M16C reception data)
TxD
1
B116
(M16C transmission data)
Figure 1.29.17. Timing of baud rate 19200
Baud Rate 38400 Command
This command changes baud rate to 38,400 bps. Execute it as follows.
(1) Transfer the "B216" command code with the 1st byte.
(2) After the "B216" check code is output with the 2nd byte, change the baud rate to 38,400 bps.
RxD1
B216
(M16C reception data)
TxD1
B216
(M16C transmission data)
Figure 1.29.18. Timing of baud rate 38400
272
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
ID Code
When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written
in the flash memory are compared to see if they match. If the codes do not match, the command sent
from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,
addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716 and 0FFFFB16. Write
a program into the flash memory, which already has the ID code set for these addresses.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
0FFFE816 to 0FFFEB16
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
BRK instruction vector
ID3 Address match vector
ID4 Single step vector
ID5 Oscilation stop detection/Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
4 bytes
Figure 1.29.19. ID code storage addresses
273
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix Standard Serial I/O Mode 2 (Flash Memory Version)
Example Circuit Application for the Standard Serial I/O Mode 2
The below figure shows a circuit application for the standard serial I/O mode 2.
CLK
1
BUSY
Monitor output
Data input
RXD1
TXD1
Data output
CNVss
M16C/6N Group
(Flash memory version)
P85(NMI)
RESET
CAN transceiver
CAN H
P9
5
(CR
X
)
)
CAN H
CAN L
CAN L
P9
6
(CT
X
P5
0(CE)
P5
5(EPM)
(1) In this example, the microprocessor mode and standard serial I/O mode are switched via a switch.
Figure 1.29.20. Example circuit application for the standard serial I/O mode 2
274
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
CAN I/O Mode
In CAN I/O mode, output and input of the software command, address, and data required for the opera-
tions (read, program, erase, etc.) are performed to the internal flash memory. An exclusive program-
mer is used for this purpose.
CAN I/O mode, unlike parallel I/O mode, the CPU controls operations such as rewrite (in CPU rewrite
mode) in the flash memory and CAN input for rewrite data. CAN I/O mode is started when the CNVss pin
_____
________
and the P50 (CE) pin are pulled up to "H" level, the P55 (EPM) pin is pulled down to "L" level, and reset is
released. (In normal microprocessor mode, pull the CNVss pin down to "L" level.)
The control program is written in the boot ROM area when the device is shipped from Mitsubishi. Note, if the
boot ROM area is rewritten in the parallel I/O mode, the CAN I/O mode cannot be used.
Figure 1.30.1 shows the pin connections for CAN I/O mode.
Two CAN pins are used for input and output of the CAN data: P96 (CTx) pin and P95 (CRx) pin. The P96
(CTx) pin and the P95 (CRx) pin have to be connected to the CAN transceiver IC.
In CAN I/O mode, only the user ROM area shown in Figure 1.28.17 can be rewritten; the boot ROM area
cannot.
CAN I/O mode has a 7 byte ID code. When the flash memory is not blank and the ID code does not match,
the command sent from the external equipment (programmer) cannot be accepted.
275
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Pin Functions
Pin
Name
Power input
Description
I/O
Apply program/erase guaranteed voltage to Vcc pin and 0 V to Vss pin.
V
CC,VSS
I
I
CNVSS
Connect this pin to Vcc pin.
CNVSS
RESET
Reset input pin: While reset is at "L" level, 20 cycles or more clock
must be input to XIN pin.
Reset input
Connect a ceramic resonator or a quartz crystal oscillator between XIN
and XOUT pins. To input an externally generated clock, input it to XIN
pin and leave XOUT pin open.
X
IN
Clock input
I
X
OUT
Clock output
O
Connect to Vcc or Vss.
BYTE
BYTE
I
I
Connect AVss to Vss and AVcc to Vcc, respectively
Reference voltage input pin for AD converter.
AVCC, AVSS
Analog power supply input
Reference voltage input
Input port P0
I
V
REF
P0
P1
P2
P3
P4
0
0
0
0
0
to P0
to P1
to P2
to P3
to P4
7
7
7
7
7
I
I
I
I
I
Input "H" or "L" level or open.
Input "H" or "L" level or open.
Input "H" or "L" llevel or open.
Input "H" or "L" level or open.
Input port P1
Input port P2
Input port P3
Input port P4
Input "H" or "L" level or open.
Input "H" level.
I
I
CE input
P50
Input port P5
Input "H" or "L" level or open.
P51
to P54,
P56, P5
P5
P6
7
Input "L" level.
EPM input
5
I
Input port P6
SCLK input
0
to P6
4
Input "H" or "L" level or open.
Connect to Vss.
, P6
6
I
I
P6
5
7
P6
TxD output
O
I
Connect to Vcc or open.
Input "H" or "L" level or open.
Input "H" or "L" level or open.
Input port P7
Input port P8
P70
to P7
7
4
P8
P8
0
to P8
I
6
5
0
5
6
, P8
7
I
P8
P9
P9
P9
NMI input
Connect to Vcc.
to P9
4, P9
7
Input port P9
CRx input
Input "H" or "L" level or open.
Connect to a CAN transceiver.
Connect to a CAN transceiver.
Input "H" or "L" level or open.
I
I
CTx Output
Input port P10
O
I
P10
0
to P107
276
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Mode setup method
Signal
Value
RESET
CNVss
CE
Vss to Vcc
Vcc
Vcc
EPM
Vss
CTX0
CRX0
P9
6
/ANEX1/CTX
0
0
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
0
/D
8
9
P9
5
/ANEX0/CRX
1/D
P9
P9
P9
P9
P9
4
/DA
/DA
1
/TB4IN
/TB3IN
2
3
4
/D10
/D11
/D12
/D13/INT3
/D14/INT4
/D15/INT5
/A
/A
/A
/A
/A
/A
/A
/A
3
0
2/TB2IN/SOUT
3
3
1/TB1IN/SIN
5
0
/TB0IN/CLK3
BYTE
6
7
CNVss
RESET
CNVss
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
(/D
(/D
(/D
(/D
(/D
(/D
(/D
(/D
0
1
2
3
4
5
6
7
/-)
/D
/D
/D
/D
/D
/D
/D
P8
P8 /XCOUT
RESET
7/XCIN
0
1
2
3
4
5
6
)
)
)
)
)
)
)
6
X
OUT
V
SS
X
IN
M306NAFGTFP
(100P6S)
V
CC
P8
P8
5
/NMI
/INT
/INT
/INT
Vss
P3
Vcc
P3
4
2
0
/A
8
(/-/D
7)
P8
P8
3
1
0
2
1/A
9
P8
P8 /TA4OUT/U
P7 /TA3IN/CRX
P7 /TA3OUT/CTX
P7
P7 /TA2OUT/W
/RTS /TA1IN/V
/CLK /TA1OUT/V
/SCL/TA0IN/TB5IN
/T /SDA/TA0OUT
1/TA4IN/U
P3
2/A10
3/A11
4/A12
5/A13
6/A14
7/A15
0/A16
1/A17
2/A18
3/A19
0
P3
P3
P3
P3
P3
P4
P4
P4
P4
7
1
1
6
5
/TA2IN/W
4
P7
3
/CTS
P7
/RxD
P7
2
2
2
2
P7
1
2
0
XD2
Figure 1.30.1. Pin connections for CAN I/O mode
277
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Upon entering CAN I/O mode, the microcomputer with the internal flash memory selects automatically the
CAN baud rate. Table 1.30.1 lists baud rate that can be automatically selected.
Table 1.30.1. List of selectable CAN baudrate
Clock frequency of M16C/6N group microcomputer with the internal flash memory
Baud rate
16MHz
10MHz
—
√
√
√
√
√
—
√
√
8MHz
—
√
√
√
√
√
√
√
5MHz
—
—
√
√
√
4MHz
2.5MHz
—
—
—
√
—
√
—
—
—
√
2MHz
—
—
—
√
√
√
—
√
√
—
—
√
√
√
√
√
√
√
1000kbps
500kbps
250kbps
125kbps
100kbps
83.3kbps
80kbps
√
√
√
√
√
√
√
√
√
√
√
—
—
√
40kbps
20kbps
10kbps
√
√
√
√
√
√
√ : Selectable
When a configuration remote frame (see Table 1.30.2) transmitted from an external equipment (program-
mer) is received and CAN baud rate configuration is completed, the M16C/6N group microcomputer with
the internal flash memory transmits a configuration data frame.
Table 1.30.2. List of CAN frame at the time of baudrate selection
Frame
Configuration remote frame Remote Standard 7F016
Configuration data frame Data Standard 7F016
Type
Format
ID
DLC (Note 1)
Data contents
0
0
Transmit at the time of baud rate selection
Transmit when M16C/6N group
completes automatic baud rate selection
Note 1: DLC indicates the number of the transfer data byte.
Note 2: The shadowed part is a transfer frame from the microcomputer with the internal flash memory to an external equipment.
Otherwise a transfer frame from the external equipment to the microcomputer with the internal flash memory.
Table 1.30.3 lists IDs for the CAN data transfer that the external equipment uses. Here, all are standard
data frames.
Table 1.30.3. ID for CAN data transfer that the external equipment uses
Frame
Command
Write data
Busy
ID
DLC (Note 1)
Data contents
7FE16
7FF16
7F116
7F216
7F316
1 to 5
0 to 8
0
Command that an external equipment issues
Data that an external equipment transmits
To transmit when M16C/6N group accepts a command
To transmit when M16C/6N group is waiting for a command
Data that M16C/6N group transmits
0
Ready
Read data
0 to 8
Note 1: DLC indicates the number of the transfer data byte.
Note 2: The shadowed part is a transfer frame from the microcomputer with the internal flash memory to an external equipment.
Otherwise a transfer frame from the external equipment to the microcomputer with the internal flash memory.
In CAN I/O mode, input and output of software commands, address, and data are performed between the
microcomputer and the external equipment using a CAN interface.
Moreover, the data in a memory, status register, etc. can be read by read operation after a software com-
mand input. Status, such as operating status of the flash memory and whether program operation or erase
operation is completed successfully or ended up in error, can be checked by reading the status register. An
explanation of the software commands, status register, etc. are given below.
278
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Software Command
Table 1.30.4 lists software commands and I/O CAN frames. In CAN I/O mode, erase operation, program,
and reading are controlled by transferring software commands through the CAN bus. Software commands
are explained here below.
Table 1.30.4. List of software commands and I/O frames
The last
frame
When ID is
not verified
Frame 1
(Note 1)
Control command
Page read
Frame 2
Frame 3 ~
Command
Command
Command
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Busy
Write data 32 times
Ready Not accepted
Ready Not accepted
Ready Not accepted
Ready Not accepted
1
2
Page program
Block erase
Write data 33 times
—
—
3
Erase all unlocked blocks Command
4
Read status register
Clear status register
Read lock bit status
Lock bit program
Lock bit enable
Command
Command
Command
Command
Command
Command
Command
Command
Read data (SRD, SRD1)(Note 2) Ready Accepted
5
Ready Not accepted
Ready Not accepted
Ready Not accepted
Ready Not accepted
Ready Not accepted
Ready Accepted
6
—
Read data
7
8
—
—
—
9
Lock bit disable
10
11
12
13
14
ID check function
Download function
Write data
Write data n times
Read data
Ready Not accepted
Ready Accepted
Version information output function Command
Boot ROM area output function Command
Read data 32 times
Ready Not accepted
Note 1: See Table 1.30.5.
Note 2: SRD signifies Status Register Data, SRD1 signifies Status Register Data 1.
Note 3: The shadowed part is transfer frame from the microcomputer with the internal flash memory to the external
equipment. Otherwise transfer frame from the external equipment to the microcomputer with the internal
flash memory
Note 4: All the commands can be accepted on the blank devices.
Table 1.30.5. Contents of software command frame
Contents of command frame
Software command
1st byte
FF16
4116
2016
A716
7016
5016
7116
7716
7A16
7516
F516
FA16
FB16
FC16
2nd byte
3rd byte
4th byte
5th byte
—
—
—
Page read
Address (middle) Address (high)
Address (middle) Address (high)
Address (middle) Address (high)
1
2
—
Page program
—
Block erase
3
D016
Erase all unlocked blocks
Read status register
Clear status register
Read lock bit status
Lock bit program
D016
4
—
—
—
—
—
—
5
—
—
—
—
—
6
—
Address (middle) Address (high)
Address (middle) Address (high)
7
—
8
D016
—
Lock bit enable
—
—
—
—
—
—
—
9
—
Lock bit disable
10
11
12
13
14
ID check function
Address (low)
Size (low)
—
Address (middle) Address (high) ID size
Download function
Version information output function
Boot ROM area output function
Size (high)
Check sum
—
—
—
—
—
Address (middle) Address (high)
—
279
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Page Read Command
A specified page (256 bytes) of the flash memory is read in unit of 8 byte by turns. Execute the command in
the following procedure:
(1) Receive data of 3 bytes in the 1st frame: "FF16", address A8 to A15, and A16 to A23.
(2) Transmit a busy frame on the 2nd frame.
(3) Read sequentially from address 0XXX0016 on the 3rd to 34th frame, and transmit data at every 8 bytes.
(4) Transmit a ready frame on the 35th frame.
CRx
Command
(M16C reception data)
CTx
Busy
Read data
Read data
Ready
(M16C transmission data)
Figure 1.30.2. Timing of page read command
Page Program Command
This command serves for writing data in unit of 256 bytes, to the page (256 bytes) specified in the flash
memory. The command should be executed in the following procedure:
(1) Receive data of 3 bytes in the 1st frame: "4116", address A8 to A15, and A16 to A23.
(2) Transmit a busy frame on the 2nd frame.
(3) Receive the write data sequentially from address 0XXX0016 on the 3rd to 34th frame.
(4) Receive DLC= "0" on the 35th frame.
(5) Transmit a ready frame on the 36th frame after completion of flash write operation.
The result of the page program can be known by reading the status register. Refer to the section of the
status register for details.
In addition, write protect on each block can be realized by the lock bit. For further details, refer to the section
of the data protection function. Program cannot be done again to the page which is already programmed.
DLC = "0"
CRx
Write data
Write data
Command
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.3. Timing of page program command
280
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Block Erase Command
This command serves for erasing the data in the specified block. Execute the command in the following
procedure:
(1) Receive data of 4 bytes in the 1st frame: "2016", address A8 to A15, A16 to A23, and "D016".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit a ready frame on the 3rd frame after completion of flash erase operation.
The result of block erase can be known by reading the status register after completion of block erase. Refer
to the section of the status register for details. In addition, erase protect on each block can be realized by
the lock bit. For details, refer to the section of data protection function.
CRx
Command
(M16C reception data)
Busy
Ready
CTx
(M16C transmission data)
Figure 1.30.4. Timing of block erase command
Erase All Unlocked Blocks Command
This command serves for erasing the contents of all blocks. Execute the command in the following
procedures.
(1) Receive data of 2 bytes in the 1st frame: "A716" and "D016".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit a ready frame on the 3rd frame after completion of erase all unlocked blocks operation.
The result of erase all unlocked blocks can be known by reading the status register after completion of
erase all unlocked blocks. Refer to the section of the status register for details.
In addition, erase protect on each block can be realized by the lock bit. For details, refer to the section of
data protection function.
CRx
Command
(M16C reception data)
Busy
Ready
CTx
(M16C transmission data)
Figure 1.30.5. Timing of erase all unlocked blocks command
281
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Read Status Register Command
This command serves for confirmation of the operating status of the flash memory. Execute the command
in the following procedure:
(1) Receive data of 1 byte in the 1st frame: "7016".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit 2 bytes on the 3rd frame: SRD and SRD1.
(4) Transmit a ready frame on the fourth frame.
CRx
Command
(M16C reception data)
CTx
Busy
Read data
Ready
(M16C transmission data)
Figure 1.30.6. Timing of read status register command
Clear Status Register Command
This command serves for clearing the bits (SR4, SR5), that show the status register has been ended in
error. Execute the command in the following procedure:
(1) Receive 1 byte of "5016" in the 1st frame.
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit a ready frame on the 3rd frame after completion of status register reset operation.
CRx
Command
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.7. Timing of clear status register command
282
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Read Lock Bit Status Command
This command serves for reading the state of the lock bit of a specified block. Execute the command in the
following procedure:
(1) Receive 3 bytes in the 1st frame: "7116", address A8 to A15, and A16 to A23.
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit 1 byte of lock bit data on the 3rd frame. A state is displayed at the 6th bit of the data. "1" means
that the block is not locked, "0" means that the block is locked.
(4) Transmit a ready frame on the 4th frame.
CRx
Command
(M16C reception data)
CTx
Busy
Read data
Ready
(M16C transmission data)
Figure 1.30.8. Timing of read lock bit status command
Lock Bit Program Command
This program serves for writing "0" (locked state) to the lock bit of a specified block. Execute the program in
the following procedure:
(1) Receive 4 bytes in the 1st frame: "7716", address A8 to A15, A16 to A23, and "D016".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit a ready frame on the 3rd frame after completion of lock operation (clearing the lock bit to "0")
to the specified block.
The state of a lock bit can be read by the read lock bit status command.
Refer to the section of data protection function about the function of a lock bit, reset method and others.
CRx
Command
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.9. Timing of lock bit program command
283
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Lock Bit Enable Command
This command enables again the lock bit in blocks whose bit has been disabled by the lock bit disable com-
mand. Execute the command in the following procedure:
(1) Receive 1 byte in the 1st frame: "7A16".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit a ready frame on the 3rd frame after setting to enable the lock bit.
This command only enables the lock bit function, however, it does not either set or clear the lock bit itself.
CRx
Command
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.10. Timing of lock bit enable command
Lock Bit Disable Command
This command disables the block lock. Execute the command in the following procedure:
(1) Receive 1 byte in the 1st frame: "7516".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit a ready frame on the 3rd frame after completion of lock bit disable selection.
This command only disables the lock bit function, however, it does not either set or clear the lock bit itself.
The lock bit data which has been "0" (locked state) is set to "1" (unlocked sate) after completion of erase
operation, when erase is performed after lock bit disable command execution. The lock bit enables after
reset release.
CRx
Command
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.11. Timing of lock bit disable command
284
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
ID Check Function Command
This command serves for judging the ID code. Execute the command in the following procedure:
(1) Receive 5 bytes in the 1st frame: "F516", address A0 to A7, A8 to A15, A16 to A23, and the number of ID
data.
(2) Transmit a busy frame on the 2nd frame.
(3) Receive the ID data in the 3rd frame and on.
(4) Receive, by DLC = "0" after completion of ID data transmission.
(5) Transmit a ready frame on the last frame after completion of ID check.
It takes up to a maximum of 1 sec., from the transmission of the ID data on the 3rd frame to the reception of
the next ready frame.
DLC = "0"
CRx
Command
Write data
Write data
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.12. Timing of ID check function command
Download Function Command
This command serves for download of an execution program to RAM. Execute the command in the follow-
ing procedure:
(1) Transmit 4 bytes in the 1st frame: "FA16", program size (low), program size (high), and check sum.
(2) Transmit a busy frame on the 2nd frame.
(3) Receive an execution program as a write data on the 3rd frame and after.
(4) Transmit a ready frame on the last frame after completion of check sum comparison.
A transfer program will be executed after completion of ready frame transmission, if a check sum matches.
The size of the transmission program varies according to the internal RAM.
CRx
Command
Write data
Write data
(M16C reception data)
CTx
Busy
Ready
(M16C transmission data)
Figure 1.30.13. Timing of download function command
285
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Version Information Output Function Command
The version information on the control program stored in the boot ROM area is output. Please perform it in
the following procedures.
(1) Receive 1 byte in the 1st frame: "FB16".
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit 8 bytes of version information on the 3rd frame.
(4) Transmit a ready frame on the 4th frame.
CRx
Command
(M16C reception data)
CTx
Busy
Read data
Ready
(M16C transmission data)
Figure 1.30.14. Timing of version information output function command
Boot ROM Area Output Function Command
This function serves for reading the control program stored in the boot ROM area in unit of page (256
bytes). Please perform it in the following procedure:
(1) Receive 3 bytes in the 1st frame: "FC16", address A8 to A15 and A16 to A23.
(2) Transmit a busy frame on the 2nd frame.
(3) Transmit the read data sequentially, starting from address 0XXX0016 from the 3rd frame to the 34th
frame.
(4) Receive a ready frame at the 35th frame.
CRx
Command
(M16C reception data)
CTx
Busy
Read data
Read data
Ready
(M16C transmission data)
Figure 1.30.15. Timing of boot ROM area output function command
286
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
ID Code
If the contents of a flash memory are not blank, the microcomputer judges whether the ID code currently
written in the flash memory matches the one that is sent from the external equipment. If they do not match,
the command sent from the external equipment cannot be accepted. Each of the ID codes consists of 8
bit data, and the area spans, from the first byte and on, address 0FFFDF16, 0FFFE316, 0FFFEB16,
0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16 respectively. Write in the flash memory a program in
which the ID codes are defined beforehand.
Address
ID1 Undefined instruction vector
ID2 Overflow vector
0FFFDC16 to 0FFFDF16
0FFFE016 to 0FFFE316
0FFFE416 to 0FFFE716
BRK instruction vector
0FFFE816 to 0FFFEB16 ID3 Address match vector
0FFFEC16 to 0FFFEF16
0FFFF016 to 0FFFF316
0FFFF416 to 0FFFF716
0FFFF816 to 0FFFFB16
0FFFFC16 to 0FFFFF16
ID4 Single step vector
Oscillation stop detection/
ID5
Watchdog timer vector
ID6 DBC vector
ID7 NMI vector
Reset vector
4 bytes
Figure 1.30.16. Storing address of ID code
287
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Data Protection Function (block lock)
Each block shown in Figure 1.28.17 has a nonvolatile lock bit that selects the protection (block lock) against
erase/write. Writing "0" (locked state) into a lock bit is done by lock bit program command. The lock bit of
each block can be read by the read lock bit status command.
Disable or enable block lock is defined by the state of the lock bit and execution status of the lock bit disable
command and the lock bit enable command.
(1) After reset release and after execution of the lock bit enable command, lock or unlock to the specified
block can be selected, according to the lock bit state (lock bit data). A block of a lock bit data "0" is in
locked state, and erase/write is disabled. On the other hand, a block of a lock bit data "1" is in unlocked
state, and erase/write is enabled.
(2) After lock bit disable command execution, all the blocks are in unlocked state regardless of the lock bit
data, and erase/write is enabled. At this time, the lock bit data which has been "0" (locked state) is set to
"1" (unlocked state) after completion of erase, and the lock by the lock bit is released.
288
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Status Register (SRD)
The status register indicates operating status of the flash memory and status such as whether an erase or
a program operation has been ended successfully or in error. It can be read by writing the read status
register command (7016). Also, the status register is cleared by writing the clear status register command
(5016). The status register outputs "8016" after reset release.
Table 1.30.6 shows the definition of each status register bit, definition of each bit is given below.
Table 1.30.6. Status register (SRD)
Definition
SRD bits
Status name
"1"
"0"
Write state machine (WSM) status
Reserved
Ready
Busy
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
-
-
Erase status
Terminated in error
Terminated normally
Program status
Block status after program
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
Reserved
Reserved
Write State Machine (WSM) Status (SR7)
The write state machine (WSM) status indicates the operating status of the flash memory. When power is
turned on, "1" (ready) is set for it. The bit is set to "0" (busy) during an auto write or auto erase operation, but
it is set back to "1" when the operation ends.
Erase Status (SR5)
The erase status indicates the operating status of an auto erase operation. It is set to "1" when an erase
error occurs. When the erase status is cleared, the value becomes "0".
Program Status (SR4)
The program status indicates the operating status of an auto write operation. It is set to "1" when an
program error occurs. When the program status is cleared, the value becomes "0".
Block Status After Program (SR3)
This is set to "1" if excessive write (phenomenon whereby the memory cell enters depletion state which
results in data not being read correctly) occurs at completion of page write. Namely, when write is com-
pleted successfully, the status register is at "8016"; the status register is at "9016" when write fails; it is at
"8816" when excessive write occurs.
If any of SR5, SR4 and SR3 is set to "1", the page program, block erase, erase all unlocked blocks and lock
bit program commands are not accepted. Before executing these commands, execute clear status register
command (5016) to clear the status.
289
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Status Register 1 (SRD1)
Status register 1 indicates the status of serial communication, results of ID checks, and result of checksum
comparisons. It can be read after the SRD by writing the read status register command (7016). Also, status
register 1 is cleared by writing the clear status register command (5016).
The value of the register is "0016" when power is turned on and the flag status is maintained even after the
reset.
Table 1.30.7 shows the status register 1, definition of each bit is given below.
Table 1.30.7. Status register 1 (SRD1)
Definition
SRD1 bits
Status name
"1"
"0"
Boot updating completed bit
Reserved
SR15 (bit7)
SR14 (bit6)
SR13 (bit5)
SR12 (bit4)
Updated
Not updated
Reserved
Checksum match bit
ID check completed bits
Matched
b3 b2
Not matched
SR11 (bit3)
SR10 (bit2)
0 0: Not verified
0 1: Verified as mismatched
1 0: Reserved
1 1: Verified
Data reception time out
Reserved
Time out
Successful operation
SR9 (bit1)
SR8 (bit0)
Boot Update Completed Bit (SR15)
This bit indicates whether the control program has been downloaded to the RAM by the download function
or not.
Checksum Match Bit (SR12)
This bit indicates whether the checksum matches or not when an execution program is downloaded by the
download function.
ID Check Completed Bits (SR11, SR10)
These bits indicate the result of ID checks. Some commands cannot be accepted without an ID check.
Data Reception Time Out (SR9)
This bit indicates a time out error during data reception. If this flag is set during data reception, the received
data is discarded and the microcomputer returns to the command wait state.
290
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Full Status Check
Execution results of erase and program operations can be known by full status check. Figure 1.30.17
shows a flowchart of the full status check and explains how to handle errors when they occur.
Read status register
YES
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
)
SR4=1 and SR5
=1 ?
NO
NO
NO
Should a block erase error occur, the block in error
cannot be used.
SR5=0?
YES
Block erase error
Program error (page
or lock bit)
Execute the read lock bit status command (7116
)
SR4=0?
YES
to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.
Program error
(block)
NO
After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.
SR3=0?
YES
End (block erase, program)
Note: When one of SR5 to SR3 is set to "1", none of the page program, block erase,
erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (5016) before executing these commands.
Figure 1.30.17. Full status check flowchart and remedial procedure for errors
291
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Appendix CAN I/O Mode (Flash Memory Version)
Example Circuit Application for the CAN I/O Mode
The figure blow shows a circuit application for the CAN I/O mode. Control pins may vary according to
programmer, therefore see the programmer manual for more information.
CAN transceiver
CAN H
CAN H
CAN L
P9
5
6
(CRx)
(CTx)
CAN L
P9
CNVss
M16C/6N Group
(Flash memory version)
P85(NMI)
RESET
P5
0
5
(CE)
P5
(EPM)
Note 1: Control pins and external circuitry may vary according to the external equipment (writer).
Refer to the using manual of the exclusive programmer for more details.
Note 2: In this example, switching between microprocessor mode and CAN I/O mode is done by
a switch.
Figure 1.30.18. Example circuit application for the CAN I/O mode
292
Mitsubishi microcomputers
M16C / 6N0 / 6N1 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Package Outline
MMP
100P6S-A
Plastic 100pin 14✕20mm body QFP
EIAJ Package Code
QFP100-P-1420-0.65
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
HD
D
100
81
1
80
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.25
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.4
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.13
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.3
0.15
14.0
20.0
0.65
16.8
22.8
0.6
1.4
–
b
c
D
E
e
30
51
31
50
HD
A
L1
HE
L
L1
x
y
–
–
F
b2
0.35
–
14.6
20.6
e
b
L
x
M
I
2
–
–
–
Detail F
y
M
M
D
E
–
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
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These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2002 MITSUBISHI ELECTRIC CORP.
New publication, effective Nov. 2002.
Specifications subject to change without notice.
REVISON HISTORY
M16C/6N0/6N1 GROUP DATA SHEET
Description
Summary
REV.
1.0
Date
11/15/02
Page
Full-fledged revision
( 1 / 1 )
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