M3455AGCFP [RENESAS]
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER; 单片4位微机的CMOS
| 型号： | M3455AGCFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| 文件： | 总148页 (文件大小：3576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
455A Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0224-0101
Rev.1.01
Feb 15, 2008
DESCRIPTION
• Interrupt..................................................................... 4 sources
• Key-on wakeup function pins ..............................................24
• I/O ports ...............................................................................24
• Output ports ........................................................................... 1
• LCD control circuit
Segment output .....................................................................32
Common output ...................................................................... 4
• Voltage drop detection circuit
Reset occurrence..................................Typ. 1.7 V (Ta = 25 °C)
Reset release ........................................Typ. 1.8 V (Ta = 25 °C)
Skip occurrence ...................................Typ. 2.0 V (Ta = 25 °C)
• Power-on reset circuit
• Watchdog timer
• Clock generating circuit
Built-in clock (high-speed/low-speed on-chip oscillator)
Main clock (ceramic resonator)
Sub-clock (quartz-crystal oscillation)
The 455A Group is a 4-bit single-chip microcomputer designed
with CMOS technology. Its CPU is that of the 4500 Series using
a simple, high-speed instruction set. The computer is equipped
with two 8-bit timers (each timer has one or two reload registers),
a 16-bit timer for clock count, interrupts, and oscillation circuit
switch function.
The various microcomputers in the 455A Group include
variations of type as shown in the table below.
FEATURES
• Minimum instruction execution time..............................0.5µs
(at 6 MHz oscillation frequency, in high-speed through-mode)
• Supply voltage .......................................................1.8 to 5.5 V
(It depends on operation source clock, oscillation frequency
and operation mode)
• Timers
• LED drive directly enabled (port D)
Timer 1..............................................................8-bit timer with
a reload register and carrier wave output auto-control function
Timer 2.............................8-bit timer with two reload registers
and carrier wave generation circuit
APPLICATION
Remote control transmitter
Timer 3........................ 16-bit timer (fixed dividing frequency)
Table 1 Support Product
Part number
M3455AG8FP (Note 1)
M3455AG8-XXXFP
ROM size (× 10 bits)
RAM size (× 4 bits)
Package
ROM type
QzROM
8192 words
512 words
PLQP0052JA-A
M3455AGCFP (Note 1)
M3455AGC-XXXFP
Note1.Shipped in blank
12288 words
Rev.1.01 Feb 15, 2008 Page 1 of 146
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PIN CONFIGURATION
Pin configuration (top view)
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
P11/SEG21
P12/SEG22
P13/SEG23
P20/SEG24
P21/SEG25
P22/SEG26
P23/SEG27
P30/SEG28
P31/SEG29
P32/SEG30
P33/SEG31
D0
SEG7
SEG6
SEG5
SEG4
M3455AG8FP
SEG3
SEG2/VLC1
SEG1/VLC2
SEG0/VLC3
COM3
M3455AG8-XXXFP
M3455AGCFP
M3455AGC-XXXFP
COM2
COM1
COM0
D1
VDCE
OUTLINE PLQP0052JA-A (52P6A-A)
Fig 1. Pin configuration (PLQP0052JA-A type)
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455A Group
FUNCTIONAL BLOCK DIAGRAM
Fig 2. Functional block diagram
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455A Group
PERFORMANCE OVERVIEW
Table 2 Performance overview
Parameter
Number of basic instructions
Minimum instruction execution time
Function
138
0.5 µs (Oscillation frequency 6 MHz: high-speed through mode)
8192 words × 10 bits
Memory sizes
ROM
M3455AG8
M3455AGC
12288 words × 10 bits
RAM
512 words × 4 bits (including LCD display RAM 32 words × 4 bits)
I/O port
D0−D5
I/O
(Input is
Six independent I/O ports. A pull-up function, a key-on wakeup function and output
structure can be switched by software.
examined by
skip decision.)
Port D5 is also used as INT pin.
D6, D7
I/O
(Input is
Two independent I/O ports; each pin is equipped with a pull-up function and a key-on
wakeup function. Both functions can be switched by software.
examined by
skip decision.)
Ports D6 and D7 are also used as XCIN and XCOUT, respectively.
P00−P03 I/O
P10−P13 I/O
P20−P23 I/O
P30−P33 I/O
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P00−P03 are also used as SEG16−SEG19, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P10−P13 are also used as SEG20−SEG23, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P20−P23 are also used as SEG24−SEG27, respectively.
4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can
be switched by software.
Ports P30−P33 are also used as SEG28−SEG31, respectively.
C
Output
1-bit output; Port C is also used as CNTR pin.
Timer
Timer 1
8-bit timer with a reload register and carrier wave output auto-control function, and
has an event counter.
Timer 2
Timer 3
Timer LC
8-bit timer with two reload registers and carrier wave generation function.
16-bit timer, fixed dividing frequency (timer for clock count)
4-bit programmable timer with a reload register (for LCD clock generating)
Watchdog timer
16-bit timer, fixed dividing frequency (timer for monitor)
Selective bias value
Selective duty value
Common output
1/2, 1/3 bias
LCD control circuit
2, 3, 4 duty
4
Segment output
32
Internal resistor for power 2r × 3, 2r × 2, r × 3, r × 2 (r = 100 kΩ, (Ta = 25 °C, Typical value))
supply
Voltage drop
detection circuit
Reset occurrence
Reset release
Typ. 1.7 V (Ta=25 °C)
Typ. 1.8 V (Ta=25 °C)
Skip occurrence
Typ. 2.0 V (Ta=25 °C)
Power-on reset circuit
Built-in
Interrupt
Source
Nesting
4 sources (one for external, three for timers)
1 level
Subroutine nesting
Device structure
Package
8 levels
CMOS silicon gate
52-pin plastic molded LQFP (PLQP0052JA-A)
-20 to 85 °C
Operating temperature range
Power source voltage
1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and
operation mode)
Power
At active mode
0.3 mA (Ta = 25 °C, VDD = 3.0 V, f(XIN) = 4 MHz, f(XCIN) = stop, f(HSOCO) = stop,
dissipation
(Typ. value)
f(LSOCO)=stop, f(STCK) = f(XIN/8)
At clock operating mode
At RAM back-up
5 µA (Ta = 25 °C, VDD = 3.0 V, f(XCIN) = 32 kHz)
0.1 µA (Ta = 25 °C, output transistor is cut-off state)
Rev.1.01 Feb 15, 2008 Page 4 of 146
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PIN DESCRIPTION
Table 3 Pin description
Pin
Name
Power source
Input/Output
Function
VDD
−
−
Connected to a plus power supply.
Connected to a 0 V power supply.
VSS
Power source
CNVSS
CNVSS
VDCE
−
Connect this pin to VSS and always apply “L”(0 V) to it.
Voltage drop detection
circuit enable
Input
This pin is used to operate/stop the voltage drop detection circuit.
When “H“ level is input to this pin, the circuit starts operating.
When “L“ level is input to this pin, the circuit stops operating.
XIN
Main clock input
Main clock output
Sub clock input
Sub clock output
Input
Output
Input
I/O pins of the main clock generating circuit. When using a ceramic resonator,
connect it between pins XIN and XOUT. A feedback resistor is built-in between them.
XOUT
XCIN
XCOUT
I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal
oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between
them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively.
Output
RESET Reset I/O
I/O
I/O
An N-channel open-drain I/O pin for a system reset. When the SRST instruction,
watchdog timer, the built-in power-on reset or the voltage drop detection circuit
causes the system to be reset, the RESET pin outputs “L” level.
D0−D5
D6, D7
I/O port D
(Input is examined by
skip decision.)
Each pin of port D has an independent 1-bit wide I/O function. The output structure
can be switched to N-channel open-drain or CMOS by software. For input use, set
the latch of the specified bit to “1” and select the N-channel open-drain. Port D0 to
D5 has a key-on wakeup function and a pull-up function. Both functions can be
switched by software.
Port D5 is also used as INT pin.
I/O port D
I/O
I/O
Each pin of port D has an independent 1-bit wide I/O function. The output structure
is N-channel open-drain. Port D6, D7 has a key-on wakeup function and a pull-up
function. Both functions can be switched by software.
(Input is examined by
skip decision.)
Ports D6 and D7 are also used as XCIN pin and XCOUT pin, respectively.
P00−P03 I/O port P0
P10−P13 I/O port P1
P20−P23 I/O port P2
P30−P33 I/O port P3
Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-
channel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P0 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P00-P03 are also used as SEG16-SEG19, respectively.
I/O
I/O
I/O
Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-
channel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P1 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P10-P13 are also used as SEG20-SEG23, respectively.
Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-
channel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P2 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P20–P23 are also used as SEG24–SEG27, respectively.
Port P3 serves as a 4-bit I/O port. The output structure can be switched to N-
channel open-drain or CMOS by software. For input use, set the latch of the
specified bit to “1” and select the N-channel open-drain. Port P3 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P30–P33 are also used as SEG28–SEG31, respectively.
C
Output port C
Output
Output
1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin.
COM0− Common output
COM3
LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0–
COM2 are used at 1/3 duty and pins COM0–COM3 are used at 1/4 duty.
SEG0−
SEG31
Segment output
Output
LCD segment output pins. SEG0–SEG2 pins are used as VLC3–VLC1 pins,
respectively. SEG16-SEG31 pins are used as Ports P00-P03, Ports P10-P13, Ports
P20-P23, and Ports P30-P33, respectively.
CNTR
INT
Timer I/O
I/O
Input
−
CNTR pin has the function to input the clock for the timer 1 event counter and to
output the PWM signal generated by timer 2. CNTR pin is also used as Port C.
Interrupt input
LCD power source
INT pin accepts external interrupts. They have the key-on wakeup function which
can be switched by software. INT pin is also used as Port D5.
VLC3−
VLC1
These are the LCD power supply pins. If an internal resistor is used, connect the
VLC3 pin to the VDD pin. (If brightness adjustment is required, connect via a resistor.)
When using an external power supply, apply voltage such that VSS ≤ VLC1 ≤ VLC2 ≤
VLC3 ≤ VDD. Pins VLC3 to VLC1 also function as pins SEG0 to SEG2.
Rev.1.01 Feb 15, 2008 Page 5 of 146
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Table 4 Pin description
Pin
Multifunction
Pin
SEG16
Multifunction
P00
Pin
Multifunction
Pin
SEG28
SEG29
SEG30
SEG31
INT
Multifunction
P30
P31
P32
P33
D5
D6
D7
C
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
P30
P31
P32
P33
D5
D6
D7
C
SEG28
SEG29
SEG30
SEG31
INT
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
XCIN
XCIN
XCOUT
CNTR
VLC3
VLC2
VLC1
XCOUT
CNTR
VLC3
VLC2
VLC1
SEG0
SEG1
SEG2
SEG0
SEG1
SEG2
Note 1. Pins except above have just single function.
Note 2. The input/output of D5 can be used even when INT is selected.
Be careful when using inputs of both INT and D5 since the input threshold value of INT pin is different from that of port D5.
Note 3. “H“ output function of port C can be used even when the CNTR (output) is used.
PORT FUNCTION
Table 5 Port function
Port
Pin
Input
Output
Output
structure
I/O unit
1 bit
Control
instructions
Control
registers
Remark
Port D
D0−D4,
D5/INT
I/O
(6)
N-channel
open-drain/
CMOS
SD, RD
SZD, CLD
FR1, FR2,
I1, K3, PU3
Programmable pull-up, key-
on wakeup and output
structure selection function
D6/XCIN,
D7/XCOUT
I/O
(2)
N-channel
open-drain
RG, K3, PU3
Programmable pull-up and
key-on wakeup function
Port P0
Port P1
Port P2
Port P3
Port C
P00/SEG16,
P01/SEG17,
P02/SEG18,
P03/SEG19
I/O
(4)
N-channel
open-drain/
CMOS
4 bits
4 bits
4 bits
4 bits
1 bit
OP0A
IAP0
PU0, K0,
FR0, C1
Programmable pull-up, key-
on wakeup and output
structure selection function
P10/SEG20,
P11/SEG21,
P12/SEG22,
P13/SEG23
I/O
(4)
N-channel
open-drain/
CMOS
OP1A
IAP1
PU0, K0,
FR0, C2
Programmable pull-up, key-
on wakeup and output
structure selection function
P20/SEG24,
P21/SEG25,
P22/SEG26,
P23/SEG27,
I/O
(4)
N-channel
open-drain/
CMOS
OP2A
IAP2
PU1, K1,
FR3, L3
Programmable pull-up, key-
on wakeup and output
structure selection function
P30/SEG28,
P31/SEG29,
P32/SEG30,
P33/SEG31
I/O
(4)
N-channel
open-drain/
CMOS
OP3A
IAP3
PU2, K2, K3,
FR2, C3
Programmable pull-up, key-
on wakeup and output
structure selection function
C/CNTR
Output CMOS
(1)
RCP
SCP
W1, W2, W4
−
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455A Group
CONNECTIONS OF UNUSED PINS
Table 6 Port function
Pin
Connection
Connect to VSS.
Usage condition
XIN
−
XOUT
Open.
−
XCIN/D6
Connect to VSS.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
The key-on wakeup function is invalid.
The key-on wakeup function is invalid.
XCOUT/D7
Open.
D0−D4
Open.
Connect to VSS.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
D5/INT
Open.
INT pin input is disabled.
The key-on wakeup function is invalid.
Connect to VSS.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
C/CNTR
Open.
CNTR input is not selected for timer 1 count source.
The key-on wakeup function is invalid.
P00/SEG16−
P03/SEG19
Open.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
P10/SEG20−
P13/SEG23
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
P20/SEG24−
P23/SEG27
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
P30/SEG28−
P33/SEG31
Open.
The key-on wakeup function is invalid.
Connect to VSS.
Segment output is not selected.
N-channel open-drain is selected for the output structure.
Pull-up transistor is OFF.
The key-on wakeup function is invalid.
COM0–COM3 Open.
−
SEG0/VLC3
SEG1/VLC2
SEG2/VLC1
Open.
Open.
Open.
SEG0 pin is selected.
SEG1 pin is selected.
SEG2 pin is selected.
−
SEG3–SEG15 Open.
(Note when connecting to VSS or VDD)
Connect the unused pins to VSS using the thickest wire at the shortest distance against noise.
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DEFINITION OF CLOCK AND CYCLE
• System clock (STCK)
The system clock is the basic clock for controlling this product.
The system clock is selected by the clock control register MR
shown as the table below.
• Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.
• Clock (f(XIN)) by the external ceramic resonator
• Clock (f(XIN)) by the external input
• Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.
• Clock (f(HSOCO)) of the high-speed on-chip oscillator which is
the internal oscillator
• Clock (f(XCIN)) by the external quartz-crystal oscillation
• Clock (f(LSOCO)) by the low-speed on-chip oscillator
• Instruction clock (INSTCK)
The instruction clock is the basic clock for controlling CPU. The
instruction clock (INSTCK) is a signal derived by dividing the
system clock (STCK) by 3. The one instruction clock cycle
generates the one machine cycle.
Table 7 Table Selection of system clock
Register MR
System clock
Operation mode
MR3
1
MR2
1
MR1
0
MR0
0
f(STCK) = f(HSOCO)/8
f(STCK) = f(HSOCO)/4
f(STCK) = f(HSOCO)/2
f(STCK) = f(HSOCO)
f(STCK) = f(XIN)/8
Internal frequency divided by 8 mode
Internal frequency divided by 4 mode
Internal frequency divided by 2 mode
Internal frequency through mode
1
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
High-speed frequency divided by 8 mode
High-speed frequency divided by 4 mode
High-speed frequency divided by 2 mode
High-speed through mode
1
0
0
1
f(STCK) = f(XIN)/4
0
1
0
1
f(STCK) = f(XIN)/2
0
0
0
1
f(STCK) = f(XIN)
1
1
1
0
f(STCK) = f(XCIN)/8
f(STCK) = f(XCIN)/4
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
Low-speed frequency divided by 8 mode
Low-speed frequency divided by 4 mode
Low-speed frequency divided by 2 mode
Low-speed through mode
1
0
1
0
0
1
1
0
0
0
1
0
1
1
1
1
f(STCK) = f(LSOCO)/8
f(STCK) = f(LSOCO)/4
f(STCK) = f(LSOCO)/2
f(STCK) = f(LSOCO)
Internal Low-speed frequency divided by 8 mode
Internal Low-speed frequency divided by 4 mode
Internal Low-speed frequency divided by 2 mode
Internal Low-speed through mode
1
0
1
1
0
1
1
1
0
0
1
1
Note 1. The f(HSOCO)/8 is selected after system is released from reset
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PORT BLOCK DIAGRAM
Skip decision
SZD instruction
（Note3）
Register Y
Decoder
FR1i
CLD
instruction
（Note1）
D0～D3（Note2）
S
SD instruction
RD instruction
（Note1）
R
Q
（Note4）
（Note4）
PU3j
K3j
Pull-up
transistor
Key-on wakeup
input
Edge detection
circuit
Skip decision
Register Y
Decoder
SZD instruction
FR20
CLD
（Note1）
instruction
S
D4（Note2)
SD instruction
RD instruction
（Note1）
R
Q
K32
PU32
Key-on wakeup
Edge detection
circuit
Pull-up
transistor
input
K32
PU32
Key-on wakeup
input
Edge detection
circuit
Pull-up
transistor
Skip decision
Register Y
Decoder
SZD instruction
FR21
CLD
（Note1）
instruction
D5/INT（Note2）
（Note1）
S
SD instruction
RD instruction
R
Q
External 0 interrupt circuit
External 0 interrupt
（Note5）
Key-on wakeup input
Timer 1 count start
synchronous circuit input
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. i represents bits 0 to 3.
4. j represents bits 0 to 1.
5. As for details, refer to the external interrupt structure.
Fig 3. Port block diagram (1)
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455A Group
K33
Key-on wakeup
input
Edge detection
circuit
PU33
Skip decision
Pull-up
transistor
Register Y
Decoder
SZD instruction
CLD
instruction
(Note 1)
XCIN/D6 (Note 2)
(Note 1)
S
R
SD instruction
RD instruction
RG2
1
Q
0
Quartz-crystal
oscillation circuit
Sub-clock input
Decoder
Pull-up
transistor
PU33
RG2
Skip decision
SZD instruction
Register Y
CLD
instruction
(Note 1)
XCOUT/D7 (Note 2)
(Note 1)
S
R
SD instruction
RD instruction
RG2
1
Q
0
K33
Key-on wakeup
input
Edge detection
circuit
Clock input for timer 1 event count
Timer 1 underflow signal
W41
D
T
Q
R
(Note 1)
C/CNTR (Note 2)
(Note 1)
W12
PWMOD
SCP instruction
RCP instruction
S
R
Q
W10
W11
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
Fig 4. Port block diagram (2)
Rev.1.01 Feb 15, 2008 Page 10 of 146
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455A Group
LCD power supply
LCD control signal
C1j
(Note 3)
0
1
(Note 1)
P00/SEG16,
P01/SEG17
(Note 2)
(Note 3)
C1j
(Note 1)
LCD power
supply
K00
Edge detection
circuit
Key-on wakeup
input
IAP0
instruction
(Note 3)
Register A
Aj
Pull-up
transistor
PU00
FR00
Aj
D
OP0A
instruction
T
Q
LCD power supply
C1k (Note 4)
0
1
LCD control signal
（Note1）
P02/SEG18,
P03/SEG19
（Note1）
(Note 4)
C1k
（Note2）
LCD power
supply
K01
Edge detection
circuit
Key-on wakeup
input
IAP0
instruction
(Note 4)
Register A
Ak
Pull-up
transistor
PU01
FR01
Ak
D
OP0A
instruction
T
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 5. Port block diagram (3)
Rev.1.01 Feb 15, 2008 Page 11 of 146
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455A Group
LCD power supply
LCD control signal
C2j
(Note 3)
0
1
(Note 1)
P10/SEG20,
P11/SEG21
(Note 2)
(Note 3)
C2j
(Note 1)
LCD power
supply
K02
Edge detection
circuit
Key-on wakeup
input
IAP1
instruction
（注3）
Register A
Aj
Pull-up
transistor
PU02
FR02
Aj
D
OP1A
T
Q
instruction
LCD power supply
C2k （Note 4）
0
1
LCD control signal
（Note 1）
P12/SEG22,
P13/SEG23
（Note 4）
（Note 2）
（Note 1）
C2k
LCD power
supply
K03
Edge detection
circuit
Key-on wakeup
input
IAP1
instruction
（Note4）
Register A
Ak
Pull-up
transistor
PU03
FR03
Ak
D
T
OP1A
instruction
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 6. Port block diagram (4)
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455A Group
LCD power supply
LCD control signal
(Note 3)
L3j
(Note 1)
0
1
P20/SEG24,
P21/SEG25
(Note 2)
(Note 3)
L3j
(Note 1)
(Note 3)
K1j
LCD power
supply
Edge detection
circuit
Key-on wakeup
input
IAP2
instruction
(Note 3)
Register A
Aj
Pull-up
transistor
(Note 3)
FR3j
PU1j
(Note 3)
Aj
D
OP2A
instruction
T
Q
LCD power supply
(Note 4)
L3k
0
1
LCD control signal
(Note 1)
(Note 1)
P22/SEG26,
P23/SEG27
(Note 2)
(Note 4)
L3k
(Note 4)
LCD power
supply
K1k
Edge detection
circuit
Key-on wakeup
input
IAP2
instruction
(Note 4)
Register A
Ak
Pull-up
transistor
(Note 4)
FR3k
PU1k
(Note 4)
Ak
D
OP2A
instruction
T
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 7. Port block diagram (5)
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455A Group
LCD power supply
LCD control signal
C3j
（Note3）
0
1
（Note1）
P30/SEG28,
P31/SEG29
（Note3）
（Note2）
（Note1）
C3j
LCD power
supply
K22
Edge detection
circuit
Key-on wakeup
input
IAP3
instruction
（Note3）
Register A
Aj
（Note3）
PU2j
FR22
Pull-up transistor
Aj
D
OP3A
T
Q
instruction
LCD power supply
C3k （Note4）
0
1
LCD control signal
（Note1）
P32/SEG30,
P33/SEG31
（Note1）
（Note4）
（Note2）
C3k
LCD power
supply
K23
Edge detection
circuit
Key-on wakeup
input
IAP3
instruction
（Note4）
Register A
Ak
（Note4）
PU2k
FR23
Pull-up transistor
Ak
D
OP3A
instruction
T
Q
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
3. j represents bits 0, 1.
4. k represents bits 2, 3.
Fig 8. Port block diagram (6)
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455A Group
LCD power supply
LCD control signal
(Note 1)
SEG SEG
(Note 2)
3 -
15
(Note 1)
LCD control signal
LCD power supply
LCD power supply
LCD control signal
(Note 1)
COM
0 -
COM3
(Note 2)
(Note 1)
LCD control signal
LCD power supply
LCD power supply
LCD control signal
LCD control signal
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
Fig 9. Port block diagram (7)
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455A Group
LCD power supply
LCD control signal
0
0
0
1 L23
(Note 1)
SEG0/VLC3
(Note 2)
(Note 1)
L23
LCD power
supply
L23
0
LCD power supply
(VLC3)
1
LCD power supply
L13
L22
1
1
LCD control
signal
0
(Note 1)
SEG1/VLC2
(Note 2)
(Note 1)
L22
LCD power
supply
L22
L20
1
0
0
LCD power supply
(VLC2)
1
LCD power supply
LCD control
L13
L21
1
1
0
signal
(Note 1)
SEG2/VLC1
L11
1
0
(Note 2)
(Note 1)
L21
LCD power
supply
L21
L20
1
0
0
LCD power supply
(VLC1)
1
L13
1
0
L20
Reset signal
L12
EPOF instruction
+
POF2 instruction
Notes 1.
This symbol represents a parasitic diode on the port.
2. Applied potential to these ports must be VDD or less.
注
Fig 10. Port block diagram (8)
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455A Group
Timer 1 count start
synchronization
circuit input
I12
Falling
(Note 1)
D9 /INT
One-sided edge
detection circuit
I11
0
External 0
0
EXF0
1
Both edges
detection circuit
interrupt
1
(Note 1)
Rising
or
I13
SNZI0 instruction
Skip decision
(Note 2)
K21
0
Level detection circuit
Edge detection circuit
K20
Key-on wakeup input
1
(Note 3)
Notes 1:
This symbol represents a parasitic diode on the port.
2: When I12 is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
Fig 11. External interrupt circuit structure
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455A Group
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(1) Arithmetic logic unit (ALU)
(CY)
The arithmetic logic unit ALU performs 4-bit arithmetic such as
4-bit data addition, comparison, AND operation, OR operation,
and bit manipulation.
(M(DP))
Addition
ALU
(2) Register A and carry flag
(A)
<Result>
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 12).
Fig 12. AMC instruction execution example
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 13).
<Set>
<Clear>
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
SC instruction
RC instruction
(3) Registers B and E
CY
A0
A3 A2 A1 A0
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and register
A as the low-order 4 bits (Figure 14).
Register E is undefined after system is released from reset and
returned from the power down mode. Accordingly, set the initial
value.
<Rotation>
RAR instruction
CY A3 A2 A1
Fig 13. RAR instruction execution example
(4) Register D
Register D is a 3-bit register.
Register B
Register A
TAB instruction
It is used to store a 7-bit ROM address together with register A
and is used as a pointer within the specified page when the TABP
p, BLA p, or BMLA p instruction is executed (Figure 15).
Also, when the TABP p instruction is executed at UPTF flag =
“1”, the high-order 2 bits of ROM reference data is stored to the
low-order 2 bits of register D, the high-order 1 bit of register D is
“0”.
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction
E7 E6 E5 E4 E3 E2 E1 E0
Register E
When the TABP p instruction is executed at UPTF flag = “0”, the
contents of register D remains unchanged. The UPTF flag is set
to “1” with the SUPT instruction and cleared to “0” with the
RUPT instruction.
TABE instruction
B3 B2 B1 B0
A3 A2 A1 A0
The initial value of UPTF flag is “0”.
Register B
Register A
TBA instruction
Register D is undefined after system is released from reset and
returned from the power down mode. Accordingly, set the initial
value.
Fig 14. Registers A, B and register E
ROM
TABP p
instruction
8
4
0
Specifying address
Low-order 2 bits
PCH
PCL
Register A (4)
Register B (4)
Register D (3)
p6 p5 p4 p3 p2 p1 p0
DR2 DR1 DR0 A3 A2 A1 A0
Middle-order 2 bits
High-order 2 bits
The contents
of register A
Field value p
The contents
of register D
Flag UPTF = 1;
High-order 2 bits of reference data is transferred to the low-order 2
bits of register D.
“0” is stored to the high-order 1 bit of register D.
Flag UPTF = 0;
Data is not transferred to register D.
Fig 15. TABP p instruction execution example
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455A Group
(5) Stack registers (SKs) and stack pointer (SP)
Stack registers are 14-bit registers.
Program counter (PC)
Executing BM instruction Executing RT instruction
Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;
• branching to an interrupt service routine (referred to as an
interrupt service routine),
• performing a subroutine call, or
SK0
SK1
SK2
SK3
SK4
SK5
SK6
SK7
(SP) = 0
(SP) = 1
(SP) = 2
(SP) = 3
(SP) = 4
(SP) = 5
(SP) = 6
(SP) = 7
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction.
Accordingly, be careful not to over the stack when performing
these operations together. The contents of registers SKs are
destroyed when 8 levels are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 16 shows the stack registers (SKs) structure.
Figure 17 shows the example of operation at subroutine call.
Stack pointer (SP) points “7” at reset or
returning from power down mode.
It points “0” by executing the first BM
instruction, and the contents of program
counter is stored in SK0.
When the BM instruction is executed after
eight stack registers are used ((SP) = 7), (SP)
= 0 and the contents of SK0 is destroyed.
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an
interrupt occurs, this register (SDP) is used to temporarily store
the contents of data pointer, carry flag, skip flag, register A, and
register B just before an interrupt until returning to the original
routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table
reference instruction.
Fig 16. Stack registers (SKs) structure
(SP) ← 0
(SK0) ← 000116
(PC) ← SUB1
Main program
Address
Subroutine
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions. When an
interrupt occurs, the contents of skip flag is stored automatically
in the interrupt stack register (SDP) and the skip condition is
retained.
SUB1:
NOP
000016 NOP
000116 BM SUB1
000216 NOP
RT
(PC) ← (SK0)
(SP) ← 7
Note :Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.
Fig 17. Example of operation at subroutine call
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455A Group
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments the
number of instruction bytes each time an instruction is executed.
However, the value changes to a specified address when branch
instructions, subroutine call instructions, return instructions, or
the table reference instruction (TABP p) is executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the next
page (Figure 18).
Program counter (PC)
p6 p5 p4 p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
PCL
Specifying page
Specifying address
Fig 18. Program counter (PC) structure
Make sure that the PCH does not specify after the last page of the
built-in ROM.
Data pointer (DP)
(9) Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group,
register X specifies a file, and register Y specifies a RAM digit
(Figure 19).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure
20).
Register Y (4)
Specifying RAM digit
Specifying RAM file
Register X (4)
• Note
Register Z (2)
Specifying RAM file group
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the power down
mode. After system is returned from the power down mode, set
these registers.
Fig 19. Data pointer (DP) structure
Specifying bit position
Set
D3 D2 D1 D0
1
0
0
0
1
Register Y (4)
Port D output latch
Fig 20. SD instruction execution example
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455A Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is
composed of 10 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127). Table 8 shows the ROM size
and pages. Figure 21 shows the ROM map of M3455AGD.
A part of page 1 (addresses 008016 to 00FF16) is reserved for
interrupt addresses (Figure 22). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
9 8
7
6
5
4
3
2
1
0
000016
007F16
008016
00FF16
010016
017F16
018016
Page 0
Page 1
Page 2
Page 3
Interrupt address page
Subroutine special page
Page 2 (addresses 010016 to 017F16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with the
BM instruction when it starts on page 2.
ROM pattern (bits 9 to 0) of all addresses can be used as data
areas with the TABP p instruction.
2FFF16
Page 95
Fig 21. ROM map of M3455AGC
Table 8 ROM size and pages
Part number
ROM (PROM) size
Pages
(× 10 bits)
M3455AG8
8192 words
64 (0 to 63)
96 (0 to 95)
9
8
7
6
5
4
3
2
1
0
M3455AGC (Note 1) 12288 words
External 0 interrupt address
008016
008216
008416
Note1.In the initial state, data in pages 0 to 63 can be
refered with the TABP instruction. Data in pages
64 to 95 can be refferd with the TABP p instruction
after the SBK instruction is executed.Data in
pages 0 to 63 can be referred with the TABP p
instruction after the RBK instruction is executed.
Timer 1 interrupt address
ROM Code Protect Address
Timer 2 interrupt address
Timer 3 interrupt address
008616
008816
When selecting the protect bit write by using a serial
programmer or selecting protect enabled for writing shipment by
Renesas Technology corp., reading or writing from/to QzROM is
disabled by a serial programmer.
As for the QzROM product in blank, the ROM code is protected
by selecting the protect bit write at ROM writing with a serial
programmer.
As for the QzROM product shipped after writing, whether the
ROM code protect is used or not can be selected as ROM option
setup (“MASK option” written in the mask file converter) when
ordering.
008A16
008C16
008E16
00FF16
Fig 22. Page 1 (addresses 008016 to 00FF16) structure
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455A Group
DATA MEMORY (RAM)
• Note
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers Z, X, and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM (also, set a value after system returns from power
down mode).
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in power down mode.
After system is returned from the power down mode, set these
registers.
RAM includes the area for LCD.
When writing “1” to a bit corresponding to displayed segment,
Table 9 RAM size and pages
the segment is turned on.
Table 9 shows the RAM size. Figure 23 shows the RAM map.
Part number
M3455AG8
M3455AGC
RAM size
512 words × 4 bits (2048 bits)
RAM 512 words×4 bits (2048 bits)
1
Register Z
0
Register X 0
1
2
3
… 12
13 14 15
0
1
2
3
… 12 13 14 15
0
1
2
3
4
5
6
7
0
8
8
9
16 24
17 25
1
2
3
4
5
6
7
9
10
11
12
13
14
15
10 18 26
11 19 27
12 20 28
13 21 29
14 22 30
15 23 31
Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig 23. RAM map
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455A Group
INTERRUPT FUNCTION
Table 10 Interrupt sources
The interrupt type is a vectored interrupt branching to an
individual address (interrupt address) according to each interrupt
source. An interrupt occurs when the following 3 conditions are
satisfied.
Interrupt source
Priority
level
Interrupt
address
Activated
condition
Interrupt name
• An interrupt activated condition is satisfied (request flag =
“1”)
1
2
3
4
External 0
interrupt
Level change of Address 0
• Interrupt enable bit is enabled (“1”)
INT0 pin
in page 1
• Interrupt enable flag is enabled (INTE = “1”)
Table 10 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
Timer 1 interrupt Timer 1
underflow
Address 4
in page 1
Timer 2 interrupt Timer 2
underflow
Address 6
in page 1
(1) Interrupt enable flag (INTE)
Timer 3 interrupt Timer 3
underflow
Address 8
in page 1
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE flag
is set to “1” with the EI instruction and disabled when INTE flag
is cleared to “0” with the DI instruction. When any interrupt
occurs, the INTE flag is automatically cleared to “0,” so that
other interrupts are disabled until the EI instruction is executed.
Table 11 Interrupt request flag, interrupt enable bit
and skip instruction
Interrupt
request
flag
Skip
Interrupt
Interrupt name
instruction enable bit
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and
V2 to select the corresponding interrupt or skip instruction.
Table 11 shows the interrupt request flag, interrupt enable bit and
skip instruction.
External 0 interrupt EXF0
SNZ0
V10
V12
V13
V20
Timer 1 interrupt
Timer 2 interrupt
Timer 3 interrupt
T1F
T2F
T3F
SNZT1
SNZT2
SNZT3
Table 12 shows the interrupt enable bit function.
(3) Interrupt request flag
Table 12 Interrupt enable bit function
When the activated condition for each interrupt is satisfied, the
corresponding interrupt request flag is set to “1.” Each interrupt
request flag except the voltage drop detection circuit interrupt
request flag is cleared to “0” when either;
• an interrupt occurs, or
• a skip instruction is executed.
Interrupt enable
bit
Occurrence of
interrupt
Skip instruction
1
0
Enabled
Disabled
Invalid
Valid
The voltage drop detection circuit interrupt request flag cannot
be cleared to “0” at the state that the activated condition is
satisfied.
Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its
interrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state
is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 10.
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(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as
follows (Figure 25).
• Program counter (PC)
An interrupt address is set in program counter. The address to
be executed when returning to the main routine is
automatically stored in the stack register (SK).
• Interrupt enable flag (INTE)
• Program counter (PC)
• Stack register (SK)
Each interrupt address
The address of main routine to be
executed when returning
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is cleared
to “0”.
0 (Interrupt disabled)
• Interrupt request flag (only the flag for the current interrupt
source)
0
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
• Data pointer, carry flag, registers A and B, skip flag
Stored in the interrupt stack register (SDP)
automatically
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is
executed after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an
interrupt address. Use the RTI instruction to return from an
interrupt service routine.
Fig 25. Internal state when interrupt occurs
Activated
condition
Request flag
(state retained)
Enable bit
Enable flag
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed just
before the RTI instruction, interrupts are enabled after returning
the main routine. (Refer to Figure 24)
Address 0
in page 1
INT pin interrupt
waveform input
EXF0
T1F
V10
V12
V13
V20
Timer 1
underflow
Address 4
in page 1
Main
routine
Timer 2
underflow
Address 6
in page 1
T2F
Interrupt
service routine
Timer 3
underflow
Address 8
in page 1
T3F
INTE
Interrupt
occurs
Fig 26. Interrupt system diagram
EI
RTI
Interrupt is
enabled
: Interrupt enabled state
: Interrupt disabled state
Fig 24. Program example of interrupt processing
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455A Group
(6) Interrupt control registers
• Interrupt control register V2
The timer 3 interrupt enable bit are assigned to register V2. Set
the contents of this register through register A with the TV2A
instruction. The TAV2 instruction can be used to transfer the
contents of register V2 to register A.
• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can
be used to transfer the contents of register V1 to register A.
Table 13 Interrupt control registers
R/W
at power down : 00002
Interrupt control register V1
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 Not used
at reset : 00002
TAV1/TV1A
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
V10 External 0 interrupt enable bit
R/W
TAV2/TV2A
Interrupt control register V2
V23 Not used
at reset : 00002
at power down : 00002
0
1
0
1
0
1
0
1
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
V22 Not used
V21 Not used
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V20 Timer 3 interrupt enable bit
Note 1.“R” represents read enabled, and “W” represents write enabled.
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10, V12, V13, V30), and interrupt request flag are
set to “1.” The interrupt occurs two or three cycles after the cycle
where all the above three conditions are satisfied.
The interrupt occurs after three machine cycles if instructions
other than one-cycle instruction are executed when the
conditions are satisfied (Refer to Figure 27).
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455A Group
Fig 27. Interrupt sequence
Rev.1.01 Feb 15, 2008 Page 26 of 146
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455A Group
EXTERNAL INTERRUPTS
The 455A Group has the external 0 interrupt. An external
interrupt request occurs when a valid waveform is input to an
interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.
Table 14 External interrupt activated conditions
Input pin
Activated condition
Valid waveform
selection bit
Name
External 0 interrupt
D5/INT
When the next waveform is input to D5/INT pin
I11
I12
• Falling waveform (“H” → “L”)
• Rising waveform (“L” → “H”)
• Both rising and falling waveforms
I12
Falling
One-sided edge
detection circuit
I11
0
(Note 1)
D5/INT
0
External 0
interrupt
EXF0
or
1
1
(Note 1)
Both edges
Rising
detection circuit
Timer 1 count start
synchronization
circuit input
SNZI0 instruction
Skip
I13
(Note 2)
K21
Level detection circuit
Edge detection circuit
(Note 3)
0
Key-on wakeup input
K20
1
Note 1:
This symbol represents a parasitic diode on the port.
2: When I12= 0(X=0 or 1) is 0, “L” level is detected.
When I12 is 1, “H” level is detected.
3: When I12 is 0, falling edge is detected.
When I12 is 1, rising edge is detected.
Fig 28. External interrupt circuit structure
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455A Group
(1) External 0 interrupt request flag (EXF0)
(2) External interrupt control registers
External 0 interrupt request flag (EXF0) is set to “1” when a
valid waveform is input to D5/INT pin.
The valid waveforms causing the interrupt must be retained at
their level for 4 clock cycles or more of the system clock (Refer
to Figure 27).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the
interrupt or the skip instruction. The EXF0 flag is cleared to “0”
when an interrupt occurs or when the next instruction is skipped
with the skip instruction.
(1) Interrupt control register I1
Register I1 controls the valid waveform for the external 0
interrupt. Set the contents of this register through register A
with the TI1A instruction. The TAI1 instruction can be used
to transfer the contents of register I1 to register A.
• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a
valid waveform is input to D5/INT pin.
The valid waveform can be selected from rising waveform,
falling waveform or both rising and falling waveforms. An
example of how to use the external 0 interrupt is as follows.
(1) Set the bit 3 of register I1 to “1” for the INT pin to be in the
input enabled state.
(2) Select the valid waveform with the bits 1 and 2 of register
I1.
(3) Clear the EXF0 flag to “0” with the SNZ0 instruction.
(4) Set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction.
(5) Set both the external 0 interrupt enable bit (V10) and the
INTE flag to “1.”
The external 0 interrupt is now enabled. Now when a valid
waveform is input to the D5/INT pin, the EXF0 flag is set to “1”
and the external 0 interrupt occurs.
Table 15 External interrupt control register
R/W
at power down : state retained
TAI1/TI1A
Interrupt control register I1
at reset : 00002
INT pin input disabled
0
1
I13 INT pin input control bit (Note 2)
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
0
1
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
0
1
0
1
One-sided edge detected
Both edges detected
I11 INT pin edge detection circuit control bit
INT pin timer 1 count start synchronous cir-
I10
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
cuit selection bit
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
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455A Group
(3) Notes on interrupts
(3) Bit 2 of register I1
When the interrupt valid waveform of the INT pin is
changed with the bit 2 of register I1 in software, be careful
about the following notes.
(1) Bit 3 of register I1
When the input of the INT pin is controlled with the bit 3 of
register I1 in software, be careful about the following notes.
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 31.) and then, change the bit 2 of register I1 is
changed.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 31.).
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 29.) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 29.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
29.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
31.).
•
•
•
•
•
•
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
; (×××02)
; The SNZ0 instruction is valid ...... (1)
; (1×××2)
; Control of INT pin input is changed
...................................................... (2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
LA 4
; (×××02)
TV1A
LA 12
TI1A
NOP
SNZ0
; The SNZ0 instruction is valid ......(1)
; (×1××2)
; Interrupt valid waveform is changed
.......................................................(2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
...................................................... (3)
•
•
•
NOP
.......................................................(3)
•
•
•
×: these bits are not used here.
×: these bits are not used here.
Fig 29. External 0 interrupt program example-1
Fig 31. External 0 interrupt program example-3
(2) Bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the power
down mode is selected and the input of INT pin is disabled,
be careful about the following notes.
• When the INT pin input is disabled (register I13 = “0”), set the
key-on wakeup of INT pin to be invalid (register K20 = “0”)
before system enters to power down mode. (refer to (1) in
Figure 30.).
•
•
•
LA 0
TK2A
DI
; (×××02)
; INT0 key-on wakeup disabled .....(1)
EPOF
POF2
; RAM back-up
•
•
•
×: these bits are not used here.
Fig 30. External 0 interrupt program example-2
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455A Group
TIMERS
• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency
dividing ratio (n). An interrupt request flag is set to “1” after
every n count of a count pulse.
The 455A Group has the following timers.
• Programmable timer
The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer
interrupt request flag is set to “1,” new data is loaded from the
reload register, and count continues (auto-reload function).
FF16
n : Counter initial value
Count starts
Reload
Reload
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
“1”
“0”
Timer interrupt
request flag
An interrupt occurs or
a skip instruction is executed.
Fig 32. Auto-reload function
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455A Group
The 455A Group timer consists of the following circuits.
• Prescaler : 8-bit programmable timer
• Timer 1 : 8-bit programmable timer
• Timer 2 : 8-bit programmable timer
• Timer 3 : 16-bit fixed frequency timer
Prescaler, timer 1, timer 2, timer 3 and timer LC can be
controlled with the timer control registers PA and W1 to W5. The
watchdog timer is a free counter which is not controlled with the
control register.
Each function is described below.
• Timer LC : 4-bit programmable timer
• Watchdog timer: 16-bit fixed frequency timer
(Timers 1, 2 and 3 have the interrupt function, respectively)
Table 16 Function related timers
Frequency
dividing ratio
Control
register
Circuit
Structure
Count source
Use of output signal
Prescaler 8-bit programmable
binary down counter
• Instruction clock (INSTCK)
1 to 256
• Timer 1 count source
• Timer 2 count source
• Timer 3 count source
PA
Timer 1
8-bit programmable
binary down counter
(link to INT input)
(carrier wave output auto-
control function)
• PWM signal (PWMOUT)
• Prescaler output (ORCLK)
• Timer 3 underflow (T3UDF)
• CNTR input
1 to 256
• CNTR output control
• Timer 1 interrupt
W1
W4
Timer 2
Timer 3
8-bit programmable
binary down counter
(with carrier wave
generation function)
• XIN input
• Prescaler output divided by 2
(ORCLK/2)
1 to 256
• Timer 1 count source
• CNTR output
• Timer 2 interrupt
W2
W4
16-bit fixed dividing
frequency
• XCIN input
512
1024
2048
4096
8192
16384
32768
65536
• Timer 1 count source
• Timer LC count source
• Timer 3 interrupt
W3
W5
• Prescaler output (ORCLK)
• High-speed on-chip oscillator
(f(HSOCO))
• Low-speed on-chip oscillator
(f(LSOCO))
Timer LC 4-bit programmable binary • Bit 4 of timer 3 (T34)
1 to 16
• LCD clock
W4
-
down counter
• System clock (STCK)
Watchdog 16-bit fixed dividing
• Instruction clock (INSTCK)
65536
• System reset (counting twice)
• Decision of flag WDF1
timer
frequency
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455A Group
MR3, MR2
11
Division circuit
Divided by 8
Divided by 4
Divided by 2
System clock (STCK)
MR1, MR0
00
10
High-speed on-chip oscillator
Internal clock
generating circuit
(divided by 3)
Instruction clock
(INSTCK)
01
00
01
10
XIN
Ceramic resonance
Quartz-crystal
oscillation
XＣＩN
11
Low-speed on-chip oscillator
Prescaler (8)
ORCLK
PA0
Reload register RPS (8)
(TPSAB)
(TPSAB)
(TPSAB)
(TABPS)
(TABPS)
Register B Register A
I12
0
I11
0
One-sided edge
detection circuit
I10
D5/INT
I13
S
R
Q
1
Both edges
detection circuit
1
1
0
I10
W13
T1UDF
Timer 1
interrupt
Timer 1 (8)
T1F
W11, W10
00
Timer 1 underflow signal
(T1UDF)
PWMOUT
ORCLK
T3UDF
Reload register R1 (8)
01
(T1AB)
(T1AB)
(TR1AB)
(T1AB)
10
11
(TAB1)
(TAB1)
Register B Register A
W40
0
C/CNTR
W12
1
PWMOUT
Port C output
T1UDF
W41
D
T
W11 W10
Q
R
W12
Register B Register A
Q
T
PWMOD
(T2HAB)
Reload register R2H (8)
R
W20
0
Reload control circuit
W22
1
W23
T2F
XIN
“H” interval
expansion
Timer 2 (8)
Timer 2
interrupt
1
ORCLK
1/2
0
(T2R2L)
Reload register R2L (8)
W21
(T2AB)
(T2AB)
(T2AB)
(TAB2)
(TAB2)
Register B Register A
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Fig 33. Timers structure (1)
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455A Group
W51, W50
00
XCIN
01
ORCLK
Timer3 (16)
1 - - 4 - - - - - 9 10 11 12 13 14 15 16
10
11
Low-speed OCO
W32、W31、W30
High-speed OCO
111
W33
110
101
100
Timer 3
interrupt
T3F
011
Timer 3 underflow signal
(T3UDF)
010
001
000
W42
0
Timer LC (4)
1/2
LCD clock
1
STCK
W43
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Watchdog timer (16)
1 - - - - - - - - - - - - - 16
INSTCK
(Note 1)
S
Q
WDF1
R
WRST
instruction
Reset signal
(Note 3)
S
Q
WEF
Watchdog reset
signal
D
T
Q
R
DWDT instruction
+
WRST instruction
R
(Note 2)
reset signal
Data is set automatically from each reload register
when timer underflows (auto-reload function).
Note 1: Flag WDF1 is cleared to “0” and the next instruction is skipped when the WRST instruction is executed
while flag WDF1 = “1”.
The WRST instruction is equivalent to the NOP instruction while flag WDF1 = “0”.
2: Flag WEF is cleared to “0” and watchdog timer reset does not occur when the DWDT instruction and
WRST instruction are executed continuously.
3: The WEF flag is set to “1” at system reset or RAM back-up mode.
Fig 34. Timers structure (2)
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455A Group
Table 17 Timer control registers
W
TPAA
Timer control register PA
at reset : 02
at power down : 02
0
1
Stop (state retained)
Operating
PA0 Prescaler control bit
Timer control register W1
R/W
TAW1/TW1A
at reset : 00002
at power down : state retained
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Timer 1 count auto-stop circuit selection bit
(Note 2)
W13
W12 Timer 1 control bit
Operating
W11
W10
Count source
W11
0
0
1
1
0
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 1 count source selection bits (Note 3)
1
0
Timer 3 underflow signal (T3UDF)
CNTR input
W10
1
R/W
TAW2/TW2A
Timer control register W2
at reset : 00002
at power down : 00002
0
1
0
1
0
1
0
1
CNTR pin output invalid
CNTR pin output valid
W23 CNTR pin function control bit
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
PWM signal
“H” interval expansion function control bit
W22
W21 Timer 2 control bit
Operating
XIN input
W20 Timer 2 count source selection bit
Prescaler output (ORCLK)/2
R/W
TAW3/TW3A
Timer control register W3
W33 Timer 3 control bit
at reset : 00002
at power down : state retained
0
Stop (initial state)
Operating
1
W32 W31 W30
Count value
W32
000
001
010
011
100
101
110
111
Underflow every 512 count
Underflow every 1024 count
Underflow every 2048 count
Underflow every 4096 count
Underflow every 8192 count
Underflow every 16384 count
Underflow every 32768 count
Underflow every 65536 count
W31 Timer 3 count value selection bits
W30
R/W
TAW4/TW4A
Timer control register W4
W43 Timer LC control bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Stop (state retained)
Operating
Bit 4 (T34) of timer 3
System clock (STCK)
W42 Timer LC count source selection bit
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
CNTR pin output auto-control circuit
selection bit
W41
W40 CNTR pin input count edge selection bit
Rising edge
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. This function is valid only when the timer 1 control start synchronous circuit is selected (I10 =“1”).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
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455A Group
R/W
TAW5/TW5A
Timer control register W5
at reset : 00002
at power down : state retained
0
1
0
1
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
W53 Not used
W52 Not used
W51
W51W52 Count source
00
01
10
11
XCIN input
Timer 3 count source selection bits
ORCLK input
W50
Low-speed on-chip oscillator
High-speed on-chip oscillator
(1) Timer control registers
(2) Prescaler
• Timer control register PA
Prescaler is an 8-bit binary down counter with the prescaler
reload register PRS. Data can be set simultaneously in prescaler
and the reload register RPS with the TPSAB instruction. Data
can be read from reload register RPS with the TABPS
instruction.
Stop counting and then execute the TPSAB or TABPS
instruction to read or set prescaler data.
Prescaler starts counting after the following process;
(1) set data in prescaler, and
Register PA controls the count operation of prescaler. Set the
contents of this register through register A with the TPAA
instruction.
• Timer control register W1
Register W1 controls the count operation and count source of
timer 1, and timer 1 count auto-stop circuit. Set the contents of
this register through register A with the TW1A instruction.
The TAW1 instruction can be used to transfer the contents of
register W1 to register A.
(2) set the bit 0 of register PA to “1.”
When a value set in reload register RPS is n, prescaler divides the
count source signal by n + 1 (n = 0 to 255).
• Timer control register W2
Register W2 controls the count operation and count source of
timer 2, CNTR pin output, and extension function of PWM
signal “H” interval. Set the contents of this register through
register A with the TW2A instruction. The TAW2 instruction
can be used to transfer the contents of register W2 to register
A.
Count source for prescaler can be selected the instruction clock
(INSTCK).
Once count is started, when prescaler underflows (the next count
pulse is input after the contents of prescaler becomes “0”), new
data is loaded from reload register RPS, and count continues
(auto-reload function).
The output signal (ORCLK) of prescaler can be used for timer 1,
2 and 3 count sources.
• Timer control register W3
Register W3 controls the count operation and count value of
timer 3. Set the contents of this register through register A with
the TW3A instruction. The TAW3 instruction can be used to
transfer the contents of register W3 to register A.
• Timer control register W4
Register W4 controls the input count edge of CNTR pin,
CNTR1 pin output auto-control circuit. Set the contents of this
register through register A with the TW4A instruction. The
TAW4 instruction can be used to transfer the contents of
register W4 to register A.
• Timer control register W5
Register W5 controls the count source of timer 3. Set the
contents of this register through register A with the TW5A
instruction. The TAW5A instruction can be used to transfer the
contents of register W5 to register A.
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455A Group
(3) Timer 1 (interrupt function)
(4) Timer 2 (interrupt function)
Timer 1 is an 8-bit binary down counter with a timer 1 reload
register (R1). Data can be set simultaneously in timer 1 and the
reload register R1 with the T1AB instruction. Data can be read
from timer 1 with the TAB1 instruction.
Stop counting and then execute the T1AB or TAB1 instruction to
read or set timer 1 data.
When executing the TR1AB instruction to set data to reload
register R1 while timer 1 is operating, avoid a timing when timer
1 underflows.
Timer 2 is an 8-bit binary down counter with two timer 2 reload
register (R2L, R2H). Data can be set simultaneously in timer 2
and the reload register R2L with the T2AB instruction. Data can
be set in the reload register R2H with the T2HAB instruction.
The contents of reload register R2L set with the T2AB
instruction can be set to timer 2 again with the T2R2L
instruction. Data can be read from timer 2 with the TAB2
instruction.
Stop counting and then execute the T2AB or TAB2 instruction to
Timer 1 starts counting after the following process;
(1) set data in timer 1
(2) set count source by bit 0 and 1 of register W1, and
(3) set the bit 2 of register W1 to “1.”
read or set timer 2 data.
When executing the T2HAB instruction to set data to reload
register R2H while timer 2 is operating, avoid a timing when
timer 2 underflows.
Timer 2 starts counting after the following process;
(1) set data in timer 2
(2) set count source by bit 0 of register W2, and
(3) set the bit 1 of register W2 to “1.”
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 interrupt request flag (T1F) is set to “1,” new data is
loaded from reload register R1, and count continues (auto-reload
function).
When a value set in reload register R2L is n and R2H is m, timer
2 divides the count source signal by n + 1 or m + 1 (n = 0 to 255,
m = 0 to 255).
The INT pin input can be used as the start trigger for timer 1
count operation by setting “1” in bit 0 of interrupt control register
l1.
Also, in this time, the auto-stop function by timer 1 underflow
can be performed by setting the bit 3 of register W1 to “1.”
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the
timer 2 interrupt request flag (T2F) is set to “1,” new data is
loaded from reload register R2L, and count continues (auto-
reload function).
When bit 3 of register W2 is set to “1”, timer 2 reloads data from
reload register R2L and R2H alternately each underflow.
Timer 2 generates the PWM signal (PWMOUT) of the “L”
interval set as reload register R2L, and the “H” interval set as
reload registerR2H. The PWM signal (PWMOUT) is output
from CNTR pin. When bit 2 of register W2 is set to “1” at this
time, the interval (PWM signal “H” interval) set to reload
register R2H for the counter of timer 2 is extended for a half
period of count source.
In this case, when a value set in reload register R2H is m, timer 2
divides the count source signal by n + 1.5 (m = 1 to 255).
When this function is used, set “1” or more to reload register
R2H.
When bit 1 of register W4 is set to “1”, the PWM signal output to
CNTR pin is switched to valid/invalid each timer 1 underflow.
However, when timer 1 is stopped (bit 2 of register W1 is cleared
to “0”), this function is canceled.
Even when bit 1 of a register W2 is cleared to “0” in the “H”
interval of PWM signal, timer 2 does not stop until it next timer 2
underflow.
When clearing bit 1 of register W2 to “0” to stop timer 2, avoid a
timing when timer 2 underflows.
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455A Group
(5) Timer 3 (interrupt function)
(8) Timer interrupt request flags (T1F, T2F, T3F)
Timer 3 is a 16-bit binary down counter.
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the
skip instructions (SNZT1, SNZT2, SNZT3).
Use the interrupt control register V1, V2 to select an interrupt or
a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
Timer 3 starts counting after the following process;
(1) set count value by bits 0, 1 and 2 of register W3,
(2) set count source by bit 0 and 1 of register W5, and
(3) set the bit 3 of register W3 to “1.”
Once count is started, when timer 3 underflows (the set count
value is counted), the timer 3 interrupt request flag (T3F) is set to
“1,” and count continues.
Bit 4 of timer 3 can be used as the timer LC count source for the
LCD clock generating.
When bit 3 of register W3 is cleared to “0”, timer 3 is initialized
(9) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which
synchronizes the input of INT pin, and can start the timer count
operation.
Timer 1 count start synchronous circuit function is selected by
setting the bit 0 of register I1 to “1” and the control by INT pin
input can be performed.
When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to timer
by inputting valid waveform to INT pin.
The valid waveform of INT pin to set the count start synchronous
circuit is the same as the external interrupt activated condition.
Once set, the count start synchronous circuit is cleared by
clearing the bit I10 to “0” or system reset.
to “FFFF16” and count is stopped.
Timer 3 can be used as the counter for clock because it can be
operated at clock operating mode (POF instruction execution).
When timer 3 underflow occurs at clock operating mode, system
returns from the power down state.
When operating timer 3 during clock operating mode, set 1 cycle
or more of count source to the following period; from setting bit
3 of register W3 to “1” till executing the POF instruction.
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC
reload register (RLC). Data can be set simultaneously in timer
LC and the reload register (RLC) with the TLCA instruction.
Data cannot be read from timer LC. Stop counting and then
execute the TLCA instruction to set timer LC data.
Timer LC starts counting after the following process;
(1) set data in timer LC,
However, when the count auto-stop circuit is selected, the count
start synchronous circuit is cleared (auto-stop) at the timer 1
underflow.
(10)Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop
timer 1 automatically by the timer 1 underflow when the count
start synchronous circuit is used.
(2) select the count source with the bit 2 of register W4, and
(3) set the bit 3 of register W4 to “1.”
The count auto-stop circuit is valid by setting the bit 3 of register
W1 to “1”. It is cleared by the timer 1 underflow and the count
source to timer 1 is stopped.
This function is valid only when the timer 1 count start
synchronous circuit is selected.
When a value set in reload register RLC is n, timer LC divides
the count source signal by n + 1 (n = 0 to 15).
Once count is started, when timer LC underflows (the next count
pulse is input after the contents of timer LC becomes “0”), new
data is loaded from reload register RLC, and count continues
(auto-reload function).
Timer LC underflow signal divided by 2 can be used for the LCD
clock.
(7) Timer input/output pin (C/CNTR pin)
CNTR pin is used to input the timer 1 count source and output
the PWM signal generated by timer 2. The selection of CNTR
output signal can be controlled by bit 3 of register W2.
When the PWM signal is output from C/CNTR pin, set “0” to the
output latch of port C.
When the CNTR input is selected for timer 1 count source, timer
1 counts the waveform of CNTR input selected by bit 0 of
register W4. Also, when the CNTR input is selected, the output
of port C is invalid (high-impedance state).
Rev.1.01 Feb 15, 2008 Page 37 of 146
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455A Group
(11) Precautions
• Prescaler and timer 1 count start timing and count time when
operation starts
Count starts from the first rising edge of the count source (2) in
Figure 35 after prescaler and timer operations start (1) in
Figure 35.
• Prescaler
Stop prescaler counting and then execute the TABPS
instruction to read its data.
Time to first underflow (3) in Figure 35 is shorter (for up to 1
period of the count source) than time among next underflow
(4) in Figure 35 by the timing to start the timer and count
source operations after count starts.
When selecting CNTR input as the count source of timer 1,
timer 1 operates synchronizing with the falling edge of CNTR
input.
Stop prescaler counting and then execute the TPSAB
instruction to write data to prescaler.
• Timer count source
Stop timer 1, 2, 3 or LC counting to change its count source.
• Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or
TAB2 instruction to read its data.
• Writing to the timer
(2)
Stop timer 1, 2 or LC counting and then execute the T1AB,
T2AB, T2R2L or TLCA instruction to write data to timer.
• Writing to reload register
In order to write a data to the reload register R1 while the timer
1 is operating, execute the TR1AB instruction except a timing
of the timer 1 underflow.
Count source
Count source
(When falling edge of
CNTR input is selected)
3
2
1
0
3
2
1
0
3
2
Timer 1 value
Timer 1 underflow signal
In order to write a data to the reload register R2H while the
timer 2 is operating, execute the T2HAB instruction except a
timing of the timer 3 underflow.
(3)
(4)
• PWM signal
(1) Timer start
If the timer 2 count stop timing and the timer 2 underflow
timing overlap during output of the PWM signal, a hazard may
occur in the PWM output waveform.
Fig 35. Timer count start timing and count time when
operation starts
When “H” interval expansion function of the PWM signal is
used, set “1” or more to reload register R2H.
Set the port C output latch to “0” to output the PWM signal
from C/CNTR pin.
• Timer 2 and Timer LC count start timing and count time when
operation starts
Count starts from the rising edge (2) after the first falling edge
of the count source, after Timer 2 and Timer LC operations
start (1).
Time to first underflow (3) is different from time among next
underflow (4) by the timing to start the timer and count source
operations after count starts.
• Timer 3
Stop timer 3 counting to change its count source.
When operating timer 3 during clock operating mode, set 1
cycle or more of count source to the following period; from
setting bit 3 of register W3 to “1” till executing the POF
instruction.
(2)
Count source
3
2
1
0
3
2
1
0
3
Timer value
Timer underflow signal
(3)
(4)
(1) Timer start
Fig 36. Timer count start timing and count time when
operation starts (Timer 2 and Timer LC)
Rev.1.01 Feb 15, 2008 Page 38 of 146
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455A Group
- CNTR pin output invalid (W23=0)
Timer 2 count source
Timer 2 count value
(Reload register)
0316
0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
(R2L)
(R2L)
(R2L)
(R2L)
(R2L)
Timer 2 underflow signal
PWM signal
PWM1 signal “L” fixed
Timer 2 start
- CNTR pin output valid (W23=1), PWM signal “H” interval expansion function invalid (W22=0)
Timer 2 count source
Timer 2 count value
(Reload register)
0316
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
(R2L)
(R2H)
(R2L)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
PWM signal
4 clock
Timer 2 start
3 clock
4 clock
3 clock
4 clock
PWM period 7 clock
PWM period 7 clock
- CNTR pin output valid (W23=1), PWM signal “H” interval expansion function valid (W22=1) (Note)
Timer 2 count source
Timer 2 count value
(Reload register)
0316
0216 0116 0016
0216
0116 0016 0316 0216 0116 0016
(R2L)
0216
0116 0016 0316 0216 0116 0016 0216
(R2L)
(R2H)
(R2H)
(R2L)
(R2H)
Timer 2 underflow signal
PWM signal
4 clock
Timer 2 start
3.5 clock
4 clock
3.5 clock
4 clock
PWM period 7.5 clock
PWM period 7.5 clock
* : “0316” is set to reload register R3L and “0216” is set to reload register R3H.
Note: When the PWM signal “H” interval expansion function is valid,
set “1” or more to reload register R2H.
Fig 37. Timer 2 operation example
Rev.1.01 Feb 15, 2008 Page 39 of 146
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455A Group
• CNTR output auto-control circuit operation example 1 (W23 = “1”, W41 = “1”)
PWM signal
Timer 1 underflow signal
Timer 1 start
CNTR output
CNTR output start
* When the CNTR1 output auto-control circuit is selected, valid/invalid of CNTR output is repeated every timer 1 underflows.
• CNTR output auto-control circuit operation example 2 (W23 = “1”, W41 = “1”)
PWM signal
Timer 1 underflow signal
Timer 1 stop
(3)
(1)
(2)
Timer 1 start
Register W41
CNTR output
CNTR output start
CNTR output stop
(1) When the CNTR output auto-control function is not selected while the CNTR output is invalid,
CNTR output invalid state is retained.
(2) When the CNTR output auto-control function is not selected while the CNTR output is valid,
CNTR output valid state is retained.
(3) When the timer 1 is stopped, the CNTR output auto-control function becomes invalid.
Fig 38. CNTR output auto-control function by timer 1
Rev.1.01 Feb 15, 2008 Page 40 of 146
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455A Group
Timer 2 count start timing (R2L = “0216”, R2H = “0216”, W23 = “1”)
Mi
Mi + 1
Mi + 2
Mi + 3
Machine cycle
TW2A instruction execution (W21←1)
Timer 2 count source
(XIN input)
Register W21
Timer 2 count value
(reload register)
0216
(R2L)
0116
0016
0216
(R2H)
0116
0016
0216
(R2L)
Timer 2 underflow signal
PWM signal
Timer 2 count start timing
Timer 2 count stop timing (R2L = “0216”, R2H = “0216”, W23 = “1”)
Machine cycle
Mi
Mi + 1
Mi + 2
TW2A instruction execution (W21←0)
Mi + 3
Timer 2 count source
(XIN input)
Register W21
Timer 2 count value
(reload register)
0216
(R2H)
0116
0016
0216
(R2L)
0116
0016
0216
(R2H)
Timer 2 underflow signal
PWM signal
(Note 1)
Timer 2 count stop timing
Notes 1: If the timer count stop timing and the timer underflow timing overlap while the CNTR pin output
is valid (W23=“1”), a hazard may occur in the PWM signal waveform.
2: When timer count is stopped during “H” interval of the PWM signal, timer is stopped after
the end of the “H” output interval.
Fig 39. Timer count start/stop timing
Rev.1.01 Feb 15, 2008 Page 41 of 146
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455A Group
WATCHDOG TIMER
When the WEF flag is set to “1” after system is released from
reset, the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are
executed continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
Watchdog timer provides a method to reset the system when a
program run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks (INSTCK) as
the count source from “FFFF16” after system is released from
reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “000016,” the next
count pulse is input), the WDF1 flag is set to “1.” If the WRST
instruction is never executed until the timer WDT underflow
occurs (until timer WDT counts 65534), WDF2 flag is set to “1,”
and the RESET pin outputs “L” level to reset the microcomputer.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.
The WEF flag is set to “1” at system reset or RAM back-up
mode.
The WRST instruction has the skip function. When the WRST
instruction is executed while the WDF1 flag is “1”, the WDF1
flag is cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is
“0”, the next instruction is not skipped.
The skip function of the WRST instruction can be used even
when the watchdog timer function is invalid.
FFFF16
Value of 16-bit timer (WDT)
000016
(2)
(2)
WDF1 flag
65534 count
(Note)
(4)
WDF2 flag
RESET pin output
(1) Reset released
(3) WRST instruction
executed (skip occurrence)
(5) System reset
(1) After system is released from reset (= after program is started), timer WDT starts count down.
(2) When timer WDT underflow occurs, WDF1 flag is set to “1.”
(3) When the WRST instruction is executed while the WDF1 flag is “1”, WDF1 flag is cleared to “0,” the next
instruction is skipped.
(4) When timer WDT underflow occurs while WDF1 flag is “1,” WDF2 flag is set to “1” and the watchdog reset
signal is output.
(5) The output transistor of RESET pin is turned “ON” by the watchdog reset signal and system reset is
executed.
Note: The number of count is equal to the number of machine cycle because the count source of watchdog timer
is the instruction clock.
Fig 40. Watchdog timer function
Rev.1.01 Feb 15, 2008 Page 42 of 146
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455A Group
When the watchdog timer is used, clear the WDF1 flag at the
period of 65534 machine cycles or less with the WRST
instruction.
When the watchdog timer is not used, execute the DWDT
instruction and the WRST instruction continuously (refer to
Figure 41).
•
•
•
WRST
; WDF1 flag cleared
•
•
•
The watchdog timer is not stopped with only the DWDT
instruction.
DI
The contents of WDF1 flag and timer WDT are initialized at the
power down mode.
When using the watchdog timer and the power down mode,
initialize the WDF1 flag with the WRST instruction just before
the microcomputer enters the power down mode. Also, set the
NOP instruction after the WRST instruction, for the case when a
skip is performed with the WRST instruction (refer to Figure 42).
DWDT
WRST
; Watchdog timer function enabled/disabled
; WEF and WDF1 flags cleared
•
•
•
Fig 41. Program example to start/stop watchdog timer
•
•
•
WRST
NOP
DI
; WDF1 flag cleared
; Interrupt disabled
EPOF
POF2
↓
; POF instruction enabled
; RAM back-up mode
Oscillation stop
•
•
•
Fig 42. Program example when using the watchdog
timer
Rev.1.01 Feb 15, 2008 Page 43 of 146
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455A Group
LCD FUNCTION
(1) Duty and bias
The 455A Group has an LCD (Liquid Crystal Display)
controller/ driver. When data are set in LCD RAM and timer LC,
LCD control registers (L1, L2, L3, C1, C2, C3), and timer
control registers (W3, W4), the LCD controller/driver
automatically reads the display data and controls the LCD
display by setting duty and bias.
4 common signal output pins and 32 segment signal output pins
can be used to drive the LCD. By using these pins, up to 128
pixels (when internal power, 1/4 duty and 1/3 bias are selected)
can be controlled to display. When using the external input, set
necessary pins with the LCD control register 2 and apply the
proper voltage to the pins .
There are 3 combinations of duty and bias for displaying data on
the LCD. Use bits 0 and 1 of LCD control register (L1) to select
the proper display method for the LCD panel being used.
• 1/2 duty, 1/2 bias
• 1/3 duty, 1/3 bias
• 1/4 duty, 1/3 bias
Table 18 Duty and maximum number of displayed
pixels
Maximum number of displayed
Duty
Used COM pins
The LCD power input pins (VLC3–VLC1) are also used as pins
SEG0–SEG2. When SEG0 is selected, the internal power (VDD)
is used for the LCD power.
pixels
1/2
1/3
1/4
64 pixels
96 pixels
128 pixels
COM0, COM1 (Note)
COM0–COM2 (Note)
COM0–COM3
Note. Leave unused COM pins open.
to
to
to
to
to
VDD
L23
L13
L23
L22
L21
....
....
....
....
....
....
....
....
....
L13
L13
L20
Common
driver
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Segment
driver
Bias control
L12
LCD ON/OFF
control
....
....
....
....
....
Selector
Selector
Selector
Selector
Selector
Selector
Decoder
LCD RAM
1/2, 1/3, 1/4
counter
L11
L10
Register A
LCD clock
(from timer LC)
Fig 43. LCD controller/driver
Rev.1.01 Feb 15, 2008 Page 44 of 146
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455A Group
(2) LCD clock control
The LCD clock is determined by the timer LC setting value and
timer LC count source.
• When using the bit 4 of timer 3 as timer LC count source
(W42=“0”)
After setting data to timer LC, timer LC starts counting by setting
count source with bit 2 of register W4 and setting bit 3 of register
W4 to “1.”
1
1
2
F = T34 ×
×
LC + 1
Accordingly, the frequency (F) of the LCD clock is obtained by
the following formula. Numbers ((1) to (3)) shown below the
formula correspond to numbers in Figure 44, respectively.
(1)
(2)
(3)
[LC: 0 to 15]
• When using the system clock (STCK) as timer LC count
source (W42=“1”)
The frame frequency and frame period for each display method
can be obtained by the following formula:
1
1
2
F = STCK ×
×
LC + 1
F
Frame frequency =
(Hz)
n
(1)
(2)
(3)
[LC: 0 to 15]
n
Frame frequency =
(Hz)
F
F: LCD clock frequency
1/n: Duty
(1)
W42
0
(2)
Timer LC (4)
T34
(3)
1/2
LCD clock
1
STCK
W43
Reload register RLC (4)
(TLCA)
(TLCA)
Register A
Fig 44. LCD clock control circuit structure
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display.
When “1” is written to this LCD RAM, the display pixel
corresponding to the bit is automatically displayed.
Z
1
12
13
14
15
X
bit
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0
Y
SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG16 SEG16 SEG16 SEG16 SEG24 SEG24 SEG24 SEG24
SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25
8
9
10
11
12
13
14
15
COM
SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26
SEG3 SEG3 SEG3 SEG3 SEG11 SEG11 SEG11 SEG11 SEG19 SEG19 SEG19 SEG19 SEG27 SEG27 SEG27 SEG27
SEG4 SEG4 SEG4 SEG4 SEG12 SEG12 SEG12 SEG12 SEG20 SEG20 SEG20 SEG20 SEG28 SEG28 SEG28 SEG28
SEG5 SEG5 SEG5 SEG5 SEG13 SEG13 SEG13 SEG13 SEG21 SEG21 SEG21 SEG21 SEG29 SEG29 SEG29 SEG29
SEG6 SEG6 SEG6 SEG6 SEG14 SEG14 SEG14 SEG14 SEG22 SEG22 SEG22 SEG22 SEG30 SEG30 SEG30 SEG30
SEG7 SEG7 SEG7 SEG7 SEG15 SEG15 SEG15 SEG15 SEG23 SEG23 SEG23 SEG23 SEG31 SEG31 SEG31 SEG31
COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Fig 45. LCD RAM map
Rev.1.01 Feb 15, 2008 Page 45 of 146
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455A Group
(4) LCD drive waveform
When “1” is written to a bit in the LCD RAM data, the voltage
difference between common pin and segment pin which
correspond to the bit automatically becomes lVLC3l and the
display pixel at the cross section turns on.
When returning from reset, and in the RAM back-up mode, a
display pixel turns off because every segment output pin and
common output pin becomes VLC3 level.
1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM.
1 flame
(2/F)
M (1, 14, 8)
1/F
Voltage level
COM0
(bit 0)
0
VLC3
VLC1=VLC2
VSS
COM1
COM1
1
COM0
SEG16
X
X
(bit 3)
VLC3
VLC1=VLC2
VSS
SEG16
COM1
SEG16
COM0
SEG16
ON
OFF
1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM.
1 flame (3/F)
M (1, 14, 8)
1/F
Voltage level
COM0
COM1
COM2
(bit 0)
1
0
1
X
VLC3
VLC2
VLC1
VSS
COM2
COM1
COM0
(bit 3)
SEG16
VLC3
VLC2
VLC1
VSS
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
ON
ON
OFF
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM.
1 flame
(4/F)
M (1, 14, 8)
1/F
Voltage level
COM0
COM1
COM2
COM3
(bit 0)
0
VLC3
VLC2
VLC1
VSS
COM3
COM2
COM1
COM0
SEG16
1
0
1
(bit 3)
SEG16
VLC3
VLC2
VLC1
VSS
F : LCD clock frequency
COM3
SEG16
COM2
SEG16
COM1
SEG16
COM0
SEG16
X: Set an arbitrary value.
(These bits are not related to
ON
OFF
ON
OFF
set the drive waveform at each duty.)
Fig 46. LCD controller/driver structure
Rev.1.01 Feb 15, 2008 Page 46 of 146
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455A Group
(5) LCD power supply circuit
• SEG0/VLC3 pin
The selection of SEG0/VLC3 pin function is controlled with the
bit 3 of register L2.
When the VLC3 pin function is selected, apply voltage of VLC3 <
VDD to the pin externally.
When the SEG0 pin function is selected, VLC3 is connected to
VDD internally.
Select the LCD power supply circuit suitable for the using LCD
panel.
The LCD power supply circuit is fixed by the followings;
• The internal dividing resistor is controlled by bit 0 of register
L2.
• The internal dividing resistor is selected by bit 3 of register L1.
• The bias condition is selected by bits 0 and 1 of register L1.
• SEG1/VLC2, SEG2/VLC1 pin
The selection of SEG1/VLC2 pin function is controlled with the
bit 2 of register L2.
The selection of SEG2/VLC1 pin function is controlled with the
bit 1 of register L2.
When the VLC2 pin and VLC1 pin functions are selected and the
internal dividing resistor is not used, apply voltage of 0 < VLC1 <
VLC2 < VLC3 to these pins. Short the VLC2 pin and VLC1 pin at
1/2 bias.
When the VLC2 pin and VLC1 pin functions are selected and the
internal dividing resistor is used, the dividing voltage value
generated internally is output from the VLC1 pin and VLC2 pin.
The VLC2 pin and VLC1 pin have the same electric potential at
1/2 bias.
• Internal dividing resistor
The 4553 Group has the internal dividing resistor for LCD power
supply.
When bit 0 of register L2 is set to ì0î, the internal dividing
resistor is valid. However, when the LCD is turned off by setting
bit 2 of register L1 to ì0î, the internal dividing resistor is turned
off.
The same six resistor (r) is prepared for the internal dividing
resistor.
According to the setting value of bit 3 of register L1 and using
bias condition, the resistor is prepared as follows;
• L13 = “0”, 1/3 bias used: 2r × 3 = 6r
• L13 = “0”, 1/2 bias used: 2r × 2 = 4r
• L13 = “1”, 1/3 bias used: r × 3 = 3r
• L13 = “1”, 1/2 bias used: r × 2 = 2r
When SEG1 and SEG2 pin functions are selected, use the
internal dividing resistor (L20 = ”0”). In this time, VLC2 and
VLC1 are connected to the generated dividing voltage.
External power supply
VLC3
SEG0
VLC3
VLC3
VLC2
VLC1
SEG1
SEG2
VLC2
VLC1
SEG1
SEG2
VSS
VSS
(a) Register L2 = (0000)2
(b) Register L2 = (1000)2
External power supply
External power supply
VLC3
VLC3
VLC3
VLC2
VLC1
VLC3
VLC2
VLC1
VLC2
VLC1
VLC2
VLC1
VSS
VSS
(c) Register L2 = (1110)2
(d) Register L2 = (1111)2
Fig 47. LCD power supply circuit example (1/3 bias condition selected)
Rev.1.01 Feb 15, 2008 Page 47 of 146
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455A Group
(6) LCD control register
• LCD control register C1
• LCD control register L1
Register C1 controls selection of pin functions; P00/SEG16 to
P03/SEG19. Set the contents of this register through register A
with the TC1A instruction.
Register L1 controls duty/bias selection, LCD operation, internal
dividing resistor selection. Set the contents of this register
through register A with the TL1A instruction. The TAL1
instruction can be used to transfer the contents of register L1.
• LCD control register C2
Register C2 controls selection of pin functions; P10/SEG20 to
P13/SEG23. Set the contents of this register through register A
with the TC2A instruction.
• LCD control register L2
Register L2 controls internal dividing resistor operation,
selection of pin functions; SEG0/VLC3, SEG1/VLC2, SEG2/VLC1.
Set the contents of this register through register A with the TL2A
instruction.
• LCD control register C3
Register C3 controls selection of pin functions; P30/SEG28 to
P33/SEG31. The contents of this register through register A with
the TC3A instruction.
• LCD control register L3
Register L3 controls selection of pin functions; P20/SEG24 to
P23/SEG27. Set the contents of this register through register A
with the TL3A instruction.
Table 19 LCD control registers (1)
R/W
at power down : state retained
TAL1/TL1A
LCD control register L1
at reset : 00002
2r × 3, 2r × 2
0
1
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L13
r × 3, r × 2
Stop (OFF)
Operating
L1
0
L12 LCD control bit
1
L11
Duty
Bias
L11
0
0
1
1
0
1
0
1
Not available
Not available
1/2
1/3
1/4
1/2
1/3
1/3
LCD duty and bias selection bits
L10
W
TL2A
LCD control register L2
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
SEG0
VLC3
L23 SEG0/VLC3 pin function switch bit (Note 3)
L22 SEG1/VLC2 pin function switch bit (Note 4)
L21 SEG2/VLC1 pin function switch bit (Note 4)
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
Internal dividing resistor for LCD power
L20
supply control bit
W
TL3A
LCD control register L3
L33 P23/SEG27 pin function switch bit
L32 P22/SEG26 pin function switch bit
L31 P21/SEG25 pin function switch bit
L30 P20/SEG24 pin function switch bit
at reset : 11112
at power down : state retained
0
1
0
1
0
1
0
1
SEG27
P23
SEG26
P22
SEG25
P21
SEG24
P20
Note 1.“R” represents read enabled, and “W” represents write enabled.
Note 2.“r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
Note 3.VLC3 is connected to VDD internally when SEG0 pin is selected.
Note 4.Use internal dividing resistor when SEG1 and SEG2 pins are selected.
Rev.1.01 Feb 15, 2008 Page 48 of 146
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455A Group
Table 20 LCD control registers (2)
W
TC1A
LCD control register C1
at reset : 11112
at power down : state retained
at power down : state retained
at power down : state retained
0
1
0
1
0
1
0
1
SEG19
P03
C13 P03/SEG19 pin function switch bit
C12 P02/SEG18 pin function switch bit
C11 P01/SEG17 pin function switch bit
C10 P00/SEG16 pin function switch bit
SEG18
P02
SEG17
P01
SEG16
P00
W
TC2A
LCD control register C2
C23 P13/SEG23 pin function switch bit
C22 P12/SEG22 pin function switch bit
C21 P11/SEG21 pin function switch bit
C20 P10/SEG20 pin function switch bit
at reset : 11112
0
1
0
1
0
1
0
1
SEG23
P13
SEG22
P12
SEG21
P11
SEG20
P00
W
TC3A
LCD control register C3
C33 P33/SEG31 pin function switch bit
C32 P32/SEG30 pin function switch bit
C31 P31/SEG29 pin function switch bit
C30 P30/SEG28 pin function switch bit
at reset : 11112
0
1
0
1
0
1
0
1
SEG31
P33
SEG30
P32
SEG29
P31
SEG28
P30
Note 1.“R” represents read enabled, and “W” represents write enabled.
Rev.1.01 Feb 15, 2008 Page 49 of 146
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455A Group
RESET FUNCTION
System reset is performed by the followings:
• “L” level is applied to the RESET pin externally,
• System reset instruction (SRST) is executed,
• Reset occurs by watchdog timer,
• Reset occurs by built-in power-on reset
• Reset occurs by voltage drop detection circuit
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
Pull-up transistor
(Note 1)
Voltage drop
detection circuit
Internal reset signal
RESET pin
(Note 2)
(Note 1)
Power-on reset circuit
SRST instruction
Watchdog reset signal
WEF
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 48. Structure of RESET pin and its peripherals
Table 21 Port state at reset
Name
Function
State
High-impedance (Notes 1, 2)
D0−D4
D0−D4
D5/INT
D5
High-impedance (Notes 1, 2)
Sub-clock input
XCIN/D6, XCOUT/D7
P00/SEG16−P03/SEG19
P10/SEG20−P13/SEG23
P20/SEG24−P23/SEG27
P30/SEG28−P33/SEG31
SEG0/VLC3−SEG2/VLC1
SEG3−SEG15
XCIN, XCOUT
P00−P03
P10−P13
P20−P23
P30−P33
SEG0−SEG2
SEG3−SEG15
COM0−COM3
C/CNTR
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
VLC3 (VDD) level
VLC3 (VDD) level
COM0−COM3
VLC3 (VDD) level
C/CNTR
“L” (VSS) level
Note 1. Output latch is set to “1.”
Note 2. The output structure is N-channel open-drain.
Note 3. Pull-up transistor is turned OFF.
Rev.1.01 Feb 15, 2008 Page 50 of 146
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(1) RESET pin input
System reset is performed certainly by applying “L” level to
RESET pin for 1 machine cycle or more when the following
condition is satisfied;
the value of supply voltage is the minimum value or more of the
recommended operating conditions.
Reset input
1 machine cycle or more
0.85VDD
Program starts
(address 0 in page 0)
RESET
0.3VDD
(Note 1)
f(HSOCO)
High-speed on-chip oscillator (internal oscillator) is
counted 1376 times (Note 2).
Notes 1: Keep the value of supply voltage to the minimum value or more of the
recommended operating conditions.
2: It depends on the internal state at reset.
Fig 49. RESET pin input waveform and reset release timing
(2) Power-on reset
Reset can be automatically performed at power on (power-on
reset) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, set the time for the supply voltage
to rise from 0 V to the minimum voltage of recommended
operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between
the RESET pin and Vss at the shortest distance, and input “L”
level to RESET pin until the value of supply voltage reaches the
minimum operating voltage.
100µs or less
VDD (Note)
Power-on reset
circuit output
(3) System reset instruction (SRST)
By executing the SRST instruction, “L” level is output to RESET
pin and system reset is performed.
Internal reset signal
Reset Reset
state released
Power-on
Note: Keep the value of supply voltage to
the minimum value or more of the
recommended operating conditions.
Fig 50. Power-on reset operation
Rev.1.01 Feb 15, 2008 Page 51 of 146
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(4) Internal state at reset
Figure 51 and 52 shows internal state at reset (they are the same
after system is released from reset). The contents of timers,
registers, flags and RAM except shown in Figure 51 and 52 are
undefined, so set the initial value to them.
• Program counter (PC)
Address 0 in page 0 is set to program counter.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• Interrupt enable flag (INTE)
• Power down flag (P)
(Interrupt disabled)
0
0
0
0
0
0
0
0
• External 0 interrupt request flag (EXF0)
• Interrupt control register V1
• Interrupt control register V2
• Interrupt control register I1
• Timer 1 interrupt request flag (T1F)
• Timer 2 interrupt request flag (T2F)
• Timer 3 interrupt request flag (T3F)
• Watchdog timer flags (WDF1, WDF2)
• Watchdog timer enable flag (WEF)
• Timer control register PA
(Interrupt disabled)
(Interrupt disabled)
0
0
0
0
0
0
0
0
0
0
0
1
0
(Prescaler stopped)
(Timer 1 stopped)
(Timer 2 stopped)
(Timer 3 stopped)
(Timer LC stopped)
• Timer control register W1
0
0
0
0
0
0
0
0
0
0
0
0
• Timer control register W2
•Timer control register W3
• Timer control register W4
0
0
0
0
0
0
0
0
• Timer control register W5
1
1
0
0
• Clock control register MR
• Clock control register RG
• LCD control register L1
• LCD control register L2
• LCD control register L3
• LCD control register C1
• LCD control register C2
• LCD control register C3
1
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
Fig 51. Internal state at reset (1)
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455A Group
• Key-on wakeup control register K0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• Key-on wakeup control register K1
• Key-on wakeup control register K2
• Key-on wakeup control register K3
• Pull-up control register PU0
• Pull-up control register PU1
• Pull-up control register PU2
• Pull-up control register PU3
• Port output structure control register FR0
• Port output structure control register FR1
• Port output structure control register FR2
• Port output structure control register FR3
• High-order bit reference enable flag (UPTF)
• Carry flag (CY)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• Register A
0
0
0
0
×
×
0
0
0
0
×
×
0
0
×
1
• Register B
0
×
×
0
0
×
1
• Register D
• Register E
×
×
×
×
×
0
0
• Register X
• Register Y
• Register Z
• Stack pointer (SP)
1
• Operation source clock
• Ceramic resonator circuit
• Low-speed on-chip oscillator
• Quartz-crystal oscillator
High-speed on-chip oscillator (operating)
Operating
Stop
Operating
“X” represents undefined.
Fig 52. Internal state at reset (2)
Rev.1.01 Feb 15, 2008 Page 53 of 146
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455A Group
VOLTAGE DROP DETECTION CIRCUIT (WITH SKIP
JUDGMENT)
The built-in voltage drop detection circuit is used to set the
voltage drop detection circuit flag (VDF) or to perform system
reset.
EPOF instruction + POF instruction
EPOF instruction + POF2 instruction
S
R
Q
Q
Oscillation stop signal
Internal reset signal
T3UDF
Key-on wakeup signal
VDD
S
R
Q
SVDE instruction
－
＋
Voltage drop detection
circuit reset signal
−
+
VRST /VRST
Internal reset signal
Reset occurrence
(Note 1)
(Note 1)
Voltage drop detection
VDD
VDCE
(Note 2)
circuit flag
VDF
－
Skip judgement
VSKIP
＋
Flag occurrence
Voltage drop
detection circuit
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
Fig 53. Voltage drop detection reset circuit
(1) Operating state of voltage drop detection circuit
The voltage drop detection circuit becomes valid by inputting
“H” to the VDCE pin and it becomes invalid by inputting “L.”
When not executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit become invalid in
power down state (RAM back-up, clock operating mode). As for
this, the voltage drop detection circuit becomes valid at returning
from power down, again.
When executing the SVDE instruction under “H” level of the
VDCE pin, the voltage drop detection circuit becomes valid in
power down state (RAM back-up, clock operating mode).
The state of executing SVDE instruction can be cleared by
system reset.
Table 22 Operating state of voltage drop detection circuit
VDCE pin
SVDE instruction
No execute
Execute
at CPU operating
at power down
×
×
×
×
“L”
No execute
Execute
O
O
×
“H”
O
Note. “O” indicates valid, “×” indicates invalid.
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455A Group
(2) Voltage drop detection circuit flag (VDF)
(3) Voltage drop detection circuit reset
Voltage drop detection circuit flag (VDF) is set to “1” when the
supply voltage goes the skip occurrence voltage (VSKIP) or less.
Moreover, voltage drop detection circuit flag (VDF) is cleared to
“0” when the supply voltage goes the skip occurrence voltage
(VSKIP) or more. The state of the voltage drop detection circuit
flag (VDF) can be examined with the skip instruction (SNZVD).
Even when the skip instruction is executed, the voltage drop
detection circuit flag is not cleared to “0”.
System reset is performed when the supply voltage goes the reset
-
occurrence voltage (VRST ) or less.
When the supply voltage goes reset release voltage (VRST ) or
+
more, the oscillation circuit goes to be in the operating enabled
state and system reset is released .
Refer to the electrical characteristics for reset occurrence value
and reset release voltage value.
Refer to the electrical characteristics for skip occurrence voltage
value.
VDD
VSKIP (skip occurrence voltage)
+
VRST (reset release voltage)
VRST-(reset occurrence voltage)
Voltage drop detection circuit
flag (VDF)
Voltage drop
detection circuit
reset signal
(Note 1)
Note 1: Microcomputer starts operation after high-speed on-chip oscillator clock is counted 1376 times.
Fig 54. Voltage drop detection circuit operation waveform
(4) Note on voltage drop detection circuit
VDD
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
Recommended operating condition
min.value
+
VRST
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and
regoes up, depending on the capacity value of the bypass
capacitor added to the power supply pin, the following case may
cause program failure (Figure 55);
VRST-
No reset
Program failure may occur.
-
Normal operation
supply voltage does not fall below to VRST , and its voltage re-
goes up with no reset.
VDD
In such a case, please design a system which supply voltage is
once reduced below to VRST and re-goes up after that.
Recommended operating condition
min.value
-
+
VRST
VRST-
Reset
-
Fig 55. VDD and VRST
Rev.1.01 Feb 15, 2008 Page 55 of 146
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455A Group
POWER DOWN FUNCTION
Table 23 Functions and states retained at power down
mode
The 455A Group has 2-type power down functions.
System enters into each power down state by executing the
following instructions.
Power down mode
Function
Clock
operating back-up
RAM
• Clock operating mode ................. EPOF and POF instructions
• RAM back-up mode ................... EPOF and POF2 instructions
Program counter (PC), registers A, B,
carry flag (CY), stack pointer (SP) (Note
2)
×
×
When the EPOF instruction is not executed before the POF or
POF2 instruction is executed, these instructions are equivalent to
the NOP instruction.
Contents of RAM
O
×
O
×
Interrupt control registers V1, V2
Interrupt control registers I1, V2
Selected oscillation circuit
Clock control register MR, RG
Timer 1, Timer 2 functions
Timer 3 function
O
O
O
O
O
O
(1) Clock operating mode
The following functions and states are retained.
• RAM
• Reset circuit
• XCIN–XCOUT oscillation
• LCD display
• Timer 3
(Note 3) (Note 3)
O
O
O
Timer LC function
(Note 3)
Watchdog timer function
× (Note
4)
× (Note
4)
• Low-speed on-chip oscillator
Timer control registers PA, W2
Timer control registers W1, W3, W4, W5
LCD display function
×
×
O
(2) RAM back-up mode
O
O
O
The following functions and states are retained.
• RAM
• Reset circuit
(Note 5)
O
LCD control registers L1 to L3, C1 to C3
Voltage drop detection circuit
Port level
(Note 6) (Note 6)
(Note 7) (Note 7)
(3) Warm start condition
Key-on wakeup control registers K0 to K3
Pull-up control registers PU0 to PU3
O
O
O
O
The system returns from the power down state when;
• External wakeup signal is input
• Timer 3 underflow occurs
in the power down mode.
In either case, the CPU starts executing the software from
address 0 in page 0. In this case, the P flag is “1.”
Port output structure control registers
FR0 to FR3
O
O
External interrupt request flags (EXF0)
Timer interrupt request flags (T1F, T2F)
Timer interrupt request flag (T3F)
Interrupt enable flag (INTE)
×
×
(Note 3) (Note 3)
O
×
O
×
(4) Cold start condition
Voltage drop detection circuit flag (VDF)
Watchdog timer flags (WDF1, WDF2)
×
×
The CPU starts executing the software from address 0 in page 0
when;
• external “L” level is input to RESET pin,
• execute system reset instruction (SRST instruction)
• reset by watchdog timer is performed
• reset by internal power-on reset, or
× (Note
4)
× (Note
4)
Watchdog timer enable flag (WEF)
× (Note
4)
× (Note
4)
Note 1. “O” represents that the function can be retained, and “×”
represents that the function is initialized.
Registers and flags other than the above are undefined at
power down mode, and set an initial value after returning.
Note 2. The stack pointer (SP) points the level of the stack
register and is initialized to “7” at power down mode.
Note 3. The state of the timer is undefined.
• reset by the voltage drop detection circuit is performed.
In this case, the P flag is “0.”
(5) Identification of the start condition
Note 4. Initialize the WDF1 flag with the WRST instruction, and
Warm start or cold start can be identified by examining the state
of the power down flag (P) with the SNZP instruction.
then go into the power down state.
Note 5. LCD is turned off.
Note 6. When the SVDE instruction is executed, this function is
valid at power down.
(6) Identification of the return condition using the timer
3 interrupt request flag
Note 7. In the power down mode, C/CNTR pin outputs “L” level.
However, when the CNTR input is selected (W11,
W10=“11”), C/CNTR pin is in an input enabled state
(output = high-impedance).
When the system returns from the power down mode, the
following conditions can be identified by examining the state of
the timer 3 interrupt request flag (T3F):
Other ports retain their respective output levels.
• When T3F = “1”, return by timer 3 underflow (time elapse)
• When T3F = “0”, return by key-on wakeup (key input)
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455A Group
(7) Return signal
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P0 and P1 pull-
up transistor. Set the contents of this register through register
A with the TPU0A instruction. In addition, the TAPU0
instruction can be used to transfer the contents of register PU0
to register A.
An external wakeup signal or timer 3 interrupt request flag (T3F)
is used to return from the clock operating mode.
An external wakeup signal is used to return from the RAM back-
up mode because the oscillation is stopped.
Table 24 shows the return condition for each return source.
• Pull-up control register PU1
(8) Control registers
Register PU1 controls the ON/OFF of the port P2 pull-up
transistor. Set the contents of this register through register A
with the TPU1A instruction. In addition, the TAPU1
instruction can be used to transfer the contents of register PU1
to register A.
• Key-on wakeup control register K0
Register K0 controls the ports P0 and P1 key-on wakeup
function. Set the contents of this register through register A
with the TK0A instruction. In addition, the TAK0 instruction
can be used to transfer the contents of register K0 to register A.
• Key-on wakeup control register K1
Register K1 controls the port P2 key-on wakeup function. Set
the contents of this register through register A with the TK1A
instruction. In addition,the TAK1 instruction can be used to
transfer the contents of register K1 to register A.
• Pull-up control register PU2
Register PU2 controls the ON/OFF of the ports P3 pull-up
transistor. Set the contents of this register through register A
with the TPU2A instruction. In addition, the TAPU2
instruction can be used to transfer the contents of register PU2
to register A.
• Pull-up control register PU3
• Key-on wakeup control register K2
Register PU3 controls the ON/OFF of the ports D0 to D7 pull-
up transistor. Set the contents of this register through register
A with the TPU3A instruction. In addition, the TAPU3
instruction can be used to transfer the contents of register PU3
to register A.
Register K2 controls the port P3 and INT pin key-on wakeup
function and the selection of return condition of INT pin. Set
the contents of this register through register A with the TK2A
instruction. In addition, the TAK2 instruction can be used to
transfer the contents of register K2 to register A.
• External interrupt control register I1
• Key-on wakeup control register K3
Register I1 controls the input control and the selection of valid
waveform/level of INT pin. Set the contents of this register
through register A with the TI1A instruction. In addition, the
TAI1 instruction can be used to transfer the contents of register
I1 to register A.
Register K3 controls the port D0 to D7 pin key-on wakeup
function. Set the contents of this register through register A
with the TK3A instruction. In addition, the TAK3 instruction
can be used to transfer the contents of register K3 to register A.
Table 24 Return source and return condition
Return source
Return condition
Remarks
Ports P00−P03
Ports P10−P13
Ports P20−P23
Ports P30−P33
Ports D0−D7
Return by an external falling edge (“H” → “L”). For ports P0, P1, P3 and D0 to D7 the key-on
wakeup function can be selected by two port unit,
for port P2, it can be selected by a unit.
INT pin
Return by an external “H” level or “L” level
Select the return level (“L” level or “H” level) with
input, or rising edge (“L” → “H”) or falling edge register I1 and return condition (return by level or
(“H” → “L”).
When the return level is input, the interrupt
request flag (EXF0) is not set.
edge) with register K2 according to the external
state before going into the power down state.
Timer 3 interrupt request flag
(T3F)
Return by timer 3 underflow or by setting T3F
to “1”.
It can be used in the clock operating mode.
Clear T3F with the SNZT3 instruction before
system enters into the power down state.
When system enters into the power down state
while T3F is “1”, system returns from the state
immediately because it is recognized as return
condition.
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455A Group
High-speed mode
EPOF + POF2 instruction
execution
EPOF + POF instruction
execution
E
F
B
Clock operating mode
RAM back-up mode
Operation state
Key-on wakeup
Key-on wakeup
Operation source clock: f(XIN)
Ceramic resonator
(Stabilizing time [c] )
Timer 3 underflow
(Stabilizing time [c] )
MR1, MR0 ← 00
MR1, MR0 ← 01
EPOF + POF instruction
execution
Internal mode
EPOF + POF2 instruction
execution
A
(Stabilizing time [a] )
Operation state
Key-on wakeup
Operation source clock:
f(HSOCO)
(Stabilizing time [b] )
High-speed on-chip oscillator
Key-on wakeup
Timer 3 underflow
(Stabilizing time [b] )
MR1, MR0 ← 00
MR1, MR0 ← 10
Low-speed mode
EPOF + POF2 instruction
execution
EPOF + POF instruction
execution
C
Operation state
Operation source clock: f(XCIN)
Quartz-crystal oscillation
Key-on wakeup
Key-on wakeup
Timer 3 underflow
(Stabilizing time [d] )
(Stabilizing time [d] )
MR1, MR0 ← 11
MR1, MR0 ← 10
f(HSOCO): stop
f(XIN): stop
f(XCIN),
f(LSOCO)：
by RG register
f(HSOCO): stop
f(XIN): stop
f(XCIN): stop
EPOF + POF2
instruction execution
EPOF + POF instruction
execution
Internal low-speed mode
D
f(LSOCO): stop
Key-on wakeup
Operation state
Key-on wakeup
Operation source clock: f(LSOCO)
Low-spped on-chip oscillator
(Stabilizing time [e] )
Timer 3 underflow
(Stabilizing time [e] )
Stabilizing time [a] : Microcomputer starts its operation after counting the f(HSOCO) to 1376 times.
Stabilizing time [b] : Microcomputer starts its operation after counting the f(HSOCO) to (system clock division ratio X 15) times.
Stabilizing time [c] : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio X 171) times.
Stabilizing time [d] : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio X 171) times.
Stabilizing time [e] : Microcomputer starts its operation after counting the f(LSOCO) to (system clock division ratio X 15) times.
Notes
1. The system clock selected by the clock control registers MR and RG is retained at power down.
The oscillation stability time at return can be adjusted by setting the clock control registers MR and RG before transiting to
the power down state.
2. To transmit to the clock operating mode, the EPOF and POF instructions must be executed continuously.
3. To transmit to the RAM back-up mode, the EPOF and POF2 instructions must be executed continuously.
4. After reset release, the main clock (f(XIN)), the sub-clock, and the internal clock (f(HSOCO)) are enabled.
5. To select a stopped clock as the system clock, first start the clock selected by the clock control register RG and generate
the oscillation stability time by software. Then switch the system clock.
Fig 56. State transition
Power down flag P
P
Program start
POF or
POF2
EPOF instruction +
S
Q
Warm start
Yes
instruction
SNZP
instruction
“1”
No
P =
?
R
Reset input
SNZT3
instruction
“1”
T3F =
?
Cold start
Yes
POF or
POF2
No
• • • • • • •
Set source
EPOF instruction +
instruction
Return from
external wakeup signal
Return from
timer 3 underflow
Clear source• • • • • • System reset
Fig 57. Set source and clear source of the P flag
Fig 58. Start condition identified example using the
SNZP instruction
Rev.1.01 Feb 15, 2008 Page 58 of 146
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455A Group
Table 25 Key-on wakeup control register
R/W
TAK0/TK0A
Key-on wakeup control register K0
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Ports P12 and P13 key-on wakeup
control bit
K03
Ports P10 and P11 key-on wakeup
control bit
K02
Ports P02 and P03 key-on wakeup
control bit
K01
Ports P00 and P01 key-on wakeup
control bit
K00
R/W
TAK1/TK1A
Key-on wakeup control register K1
K13 Port P23 key-on wakeup control bit
K12 Port P22 key-on wakeup control bit
K11 Port P21 key-on wakeup control bit
K10 Port P20 key-on wakeup control bit
at reset : 00002
at power down : state retained
at power down : state retained
at power down : state retained
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
R/W
TAK2/TK2A
Key-on wakeup control register K2
at reset : 00002
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Return by level
Ports P32 and P33 key-on wakeup
control bit
K23
Ports P30 and P31 key-on wakeup
control bit
K22
K21 INT pin return condition selection bit
K20 INT pin key-on wakeup control bit
Return by edge
Key-on wakeup invalid
Key-on wakeup valid
R/W
TAK3/TK3A
Key-on wakeup control register K3
at reset : 00002
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K33 Ports D6 and D7 key-on wakeup control bit
K32 Ports D4 and D5 key-on wakeup control bit
K31 Ports D2 and D3 key-on wakeup control bit
K30 Ports D0 and D1 key-on wakeup control bit
Note 1. “R” represents read enabled, and “W” represents write enabled.
Rev.1.01 Feb 15, 2008 Page 59 of 146
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455A Group
Table 26 Pull-up control register
R/W
TAPU0/TPU0A
Pull-up control register PU0
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P12 and P13 pull-up transistor control
PU03
bit
Port P10 and P11 pull-up transistor control
PU02
bit
Port P02 and P03 pull-up transistor control
PU01
bit
Port P00 and P01 pull-up transistor control
PU00
bit
R/W
TAPU1/TPU1A
Pull-up control register PU1
PU13 Port P23 pull-up transistor control bit
PU12 Port P22 pull-up transistor control bit
PU11 Port P21 pull-up transistor control bit
PU10 Port P20 pull-up transistor control bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
R/W
TAPU2/TPU2A
Pull-up control register PU2
PU23 Port P33 pull-up transistor control bit
PU22 Port P32 pull-up transistor control bit
PU21 Port P31 pull-up transistor control bit
PU20 Port P30 pull-up transistor control bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
R/W
TAPU3/TPU3A
Pull-up control register PU3
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU33 Port D6 and D7 pull-up transistor control bit
PU32 Port D4 and D5 pull-up transistor control bit
PU31 Port D2 and D3 pull-up transistor control bit
PU30 Port D0 and D1 pull-up transistor control bit
Note 1.“R” represents read enabled, and “W” represents write enabled.
Rev.1.01 Feb 15, 2008 Page 60 of 146
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455A Group
Table 27 Interrupt control register
R/W
TAI1/TI1A
Interrupt control register I1
at reset : 00002
at power down : state retained
0
1
INT pin input disabled
INT pin input enabled
I13 INT pin input control bit (Note 2)
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
0
1
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
0
1
0
1
One-sided edge detected
I11 INT pin edge detection circuit control bit
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
INT pin timer 1 count start synchronous
I10
circuit selection bit
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag EXF0 may be set.
Rev.1.01 Feb 15, 2008 Page 61 of 146
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455A Group
CLOCK CONTROL
The system clock and the instruction clock are generated as the
source clock for operation by these circuits.
Figure 59 shows the structure of the clock control circuit.
The 455A Group operates by the high-speed on-chip oscillator
clock (f(HSOCO)) which is the internal oscillator after system is
released from reset.
The clock control circuit consists of the following circuits.
• High-speed on-chip oscillator
• Ceramic resonator
• Low-speed on-chip oscillator
• Quartz-crystal oscillation circuit
• Frequency divider
The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
• Internal clock generating circuit
MR3, MR2
11
Division circuit
Divided by 8
Divided by 4
Divided by 2
System clock (STCK)
Instruction clock
MR1, MR0
00
10
High-speed on-chip oscillator
(internal oscillator)
Internal clock
01
00
generating circuit
(divided by 3)
01
10
11
(INSTCK)
RG0
RG1
XIN
Ceramic
resonance
XOUT
Internal reset signal
T3F signal
Q S
R
Key-on wakeup signal
EPOF instruction + POF instruction
XCIN
Quartz-crystal
oscillation
Q S
R
XCOUT
EPOF instruction + POF2 instruction
RG2
Low-speed on-chip oscillator
(Low-speed internal oscillator)
RG3
Fig 59. Clock control circuit structure
Rev.1.01 Feb 15, 2008 Page 62 of 146
REJ03B0224-0101
455A Group
(1) High-speed on-chip oscillator operation
After system is released from reset, the MCU starts operation by
the clock output from the high-speed on-chip oscillator which is
the internal oscillator.
455A
The clock frequency of the high-speed on-chip oscillator depends
on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
XIN
XOUT
(2) Main clock generating circuit (f(XIN))
After reset release, the ceramic oscillation is valid for the main
clock. Connect the ceramic oscillator and the external circuit to
pins XIN and XOUT at the shortest distance (Figure 61). A
feedback resistor is built in between pins XIN and XOUT.
If the main clock is not used, connect the XIN pin to VSS and
leave the XOUT pin open.
Fig 60. Handling of XIN and XOUT when operating on-
chip oscillator
455A
(3) Low-speed on-chip oscillator operation
After system is released from reset, the low-speed on-chip
oscillator turns invalid which is the internal oscillator.
Oscillator operation/stopping and the control of system clock
selection are operated by the register RG and MR.
The clock frequency of the low-speed on-chip oscillator depends
on the supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
XIN
XOUT
Rd
CIN
COUT
Note: Externally connect a damping resistor Rd
depending on the oscillation frequency.
(A feedback resistor is built-in.)
Use the resonator manufacturer’s recommended
value because constants such as capacitance
depend on the resonator.
Fig 61. Ceramic resonator external circuit
Rev.1.01 Feb 15, 2008 Page 63 of 146
REJ03B0224-0101
455A Group
(4) External clock
When the external clock signal is used as the main clock
(f(XIN)), connect the XIN pin to the clock source and leave XOUT
pin open (Figure 62).
455A
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating
condition). Also, note that the power down mode (POF and
POF2 instructions) cannot be used when using the external clock.
VDD
VSS
XIN
XOUT
External oscillation circuit
(5) Sub-clock generating circuit f(XCIN)
Sub-clock signal f(XCIN) is obtained by externally connecting a
quartz-crystal oscillator. Connect this external circuit and a
quartz-crystal oscillator to pins XCIN and XCOUT at the shortest
distance. A feedback resistor is built in between pins XCIN and
XCOUT (Figure 63). XCIN pin and XCOUT pin are also used as
ports D6 and D7, respectively. The sub-clock oscillation circuit is
invalid and the function of ports D6 and D7 are valid by setting
bit 2 of register RG to “1”.
Fig 62. External clock input circuit
455A
XCIN
XCOUT
When sub-clock, ports D6 and D7 are not used, connect XCIN/D6
to VSS and leave XCOUT/D7 open.
Rd
CIN
COUT
Note: Externally connect a damping resistor Rd
depending on the oscillation frequency.
(A feedback resistor is built-in.)
Use the quartz-crystal manufacturer’s
recommended value because constants such as
capacitance depend on the resonator.
Fig 63. External quarts-crystal circuit
Rev.1.01 Feb 15, 2008 Page 64 of 146
REJ03B0224-0101
455A Group
(6) Clock control register MR
(7) Clock control register RG
Register MR controls system clock and operation mode
(frequency division of system clock). Set the contents of this
register through register A with the TMRA instruction. In
addition, the TAMR instruction can be used to transfer the
contents of register MR to register A.
Register RG controls the start/stop of each oscillation circuit. Set
the contents of this register through register A with the TRGA
instruction.
Table 28 Clock control registers
R/W
at power down : state retained
TAMR/TMRA
Clock control register MR
at reset : 11002
MR3 MR2
Operation mode
MR3
MR2
MR1
MR0
0
0
1
1
0
1
0
1
Through mode
Operation mode selection bits
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
MR1 MR0
System clock
0
0
1
1
0
1
0
1
f(HSOCO)
f(XIN)
System clock selection bits (Note 2)
f(XCIN)
f(LSOCO)
W
TRGA
Clock control register RG
at reset : 10002
at power down : state retained
0
1
0
1
0
1
0
1
Low-speed on-chip oscillator (f(LSOCO)) oscillation available
Low-speed on-chip oscillator (f(LSOCO)) oscillation stop
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
Main clock (f(XIN)) oscillation available
Low-speed on-chip oscillator (f(LSOCO))
control bit (Note 3)
RG3
RG2 Sub-clock (f(XCIN)) control bit (Note 3)
RG1 Main-clock (f(XIN)) control bit (Note 3)
Main clock (f(XIN)) oscillation stop
High-speed on-chip oscillator (f(HSOCO)) oscillation available
High-speed on-chip oscillator (f(HSOCO)) oscillation stop
High-speed on-chip oscillator (f(HSOCO))
control bit (Note 3)
RG0
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. The oscillation circuit selected for system clock cannot be stopped.
Rev.1.01 Feb 15, 2008 Page 65 of 146
REJ03B0224-0101
455A Group
QzROM Writing Mode
In the QzROM writing mode, the user ROM area can be
rewritten while the microcomputer is mounted on-board by using
a serial pro-grammer which is applicable for this microcomputer.
Table 29 lists the pin description (QzROM writing mode) and
Figure 64 shows the pin connections.
Refer to Figure 65 for examples of a connection with a serial pro-
grammer.
Contact the manufacturer of your serial programmer for serial
pro-grammer. Refer to the user’s manual of your serial
programmer for details on how to use it.
Table 29 Pin description (QzROM writing mode)
Pin
Name
I/O
Function
VDD, VSS
RESET
Power source, GND
Apply 2.7 to 4.7V to VCC, and 0V to VSS.
Reset input pin for active “L”. Reset occurs when RESET pin is hold
at an “L” level for 16 cycles or more of XIN.
Reset input
input
XIN, XCIN
XOUT, XCOUT
D0 − D5
Clock input
input
Either connect an oscillator circuit or connect XIN and XCIN to VSS
and leave XOUT and XCOUT open.
Clock output
output
P00/SEG16 − P03/SEG19
P10/SEG20 − P13/SEG23
P20/SEG24 (Note 1) − P23/SEG27
P30/SEG28 − P33/SEG31
I/O port
I/O
Input “H” or “L” level signal or leave the pin open.
CNVSS
D4
VPP input
input
I/O
QzROM programmable power source pin.
Serial data I/O pin.
SDA input/output
SCLK input
D3
input
Serial clock input pin.
D2
input
Read/program pulse input pin.
PGM input
Voltage drop
detection circuit
enable
VDCE
input
Input “H” or “L” level signal
SEG0/VLC3 − SEG2/VLC1
SEG3 − SEG15
COM0 − COM3
Segment output/
LCD power source/ output Either connect to an LCD panel or leave open.
Common output
Output port C/
C/CNTR
output C/CNTR pin outputs “L” level.
Timer I/O
Note 1. Note that the P20/SEG24 pin is pulled down internally by the MCU during the transition period (the period when VPP is
approximately 0.5 VDD to 1.3 VDD) when the programming power supply (VPP) is applied to the CNVSS pin. In addition, the
P20/SEG24 pin is high inpedance when VPP is approximately 1.3 VDD or grater.
Rev.1.01 Feb 15, 2008 Page 66 of 146
REJ03B0224-0101
455A Group
Pin configuration (top view)
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
P11/SEG21
P12/SEG22
P13/SEG23
SEG7
SEG6
SEG5
(Note) P20/SEG24
P21/SEG25
P22/SEG26
P23/SEG27
P30/SEG28
P31/SEG29
P32/SEG30
P33/SEG31
D0
SEG4
M3455AG8FP
SEG3
SEG2/VLC1
SEG1/VLC2
SEG0/VLC3
COM3
M3455AG8-XXXFP
M3455AGCFP
M3455AGC-XXXFP
COM2
COM1
COM0
D1
VDCE
VSS
PGM
SCLK
SDA
＊
＊
1KΩ
VDD
*: Connect an oscillation circuit
: QzROM pin
VPP
OUTLINE PLQP0052JA-A (52P6A-A)
Note: Note that the P20/SEG24 pin is pulled down internally by the MCU during the transition
period (that period when VPP is approximately 0.5 VDD to 1.3 VDD) when the programming
power supply (VPP) is applied to the CNVSS pin. In addition, the P20/SEG24 pin is high
impedance when VPP is approximately 1.3 VDD or greater.
Fig 64. Pin connection diagram
Rev.1.01 Feb 15, 2008 Page 67 of 146
REJ03B0224-0101
455A Group
455A Group
T_VDD
T_VPP
Vcc
CNVSS
4.7 kΩ
1 kΩ
T_TXD
T_RXD
D4 (SDA)
D3 (SCLK)
T_SCLK
T_BUSY
N.C.
D2 (PGM)
T_PGM/OE /MD
RESET circuit
RESET
T_RESET
GND
Vss
XIN
XOUT
Set the same termination
as the single-chip mode.
Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF.
Fig 65. When using programmer of Suisei Electronics System Co., LTD, connection example
Rev.1.01 Feb 15, 2008 Page 68 of 146
REJ03B0224-0101
455A Group
LIST OF PRECAUTIONS
(8) Power-on reset
When the built-in power-on reset circuit is used, set the time for
the supply voltage to rise from 0 V to the minimum voltage of
recommended operating conditions to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between
the RESET pin and Vss at the shortest distance, and input “L”
level to RESET pin until the value of supply voltage reaches the
minimum operating voltage.
(1) Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a bypass capacitor (approx. 0.1 µF) between pins VDD
and VSS at the shortest distance,
• equalize its wiring in width and length, and
• use relatively thick wire.
CNVSS is also used as VPP pin. Accordingly, when using this pin,
connect this pin to VSS through a resistor about 5kΩ (connect
this resistor to CNVSS/VPP pin as close as possible).
(9) POF, POF2 instruction
When the POF or POF2 instruction is executed continuously
after the EPOF instruction, system enters the RAM back-up
state.
(2) Note on Power Source Voltage
Note that system cannot enter the RAM back-up state when
executing only the POF or POF2 instruction.
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and
may perform unstable operation.
Be sure to disable interrupts by executing the DI instruction
before executing the EPOF instruction and the POF/POF2
instruction continuously.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the supply voltage is less than the
recommended operating conditions and design a system not to
cause errors to the system by this unstable operation.
(3) Register initial values 1
The initial value of the following registers are undefined after
system is released from reset. After system is released from reset,
set initial values.
• Register Z (2 bits)
• Register D (3 bits)
• Register E (8 bits)
(4) Register initial values 2
The initial value of the following registers are undefined at RAM
back-up. After system is returned from RAM back-up, set initial
values.
• Register Z (2 bits)
• Register X (4 bits)
• Register Y (4 bits)
• Register D (3 bits)
• Register E (8 bits)
(5) Program counter
Make sure that the PCH does not specify after the last page of the
built-in ROM.
(6) Stack registers (SKS)
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of stack
registers is used respectively when using an interrupt service
routine and when executing a table reference instruction.
Accordingly, be careful not to over the stack when performing
these operations together.
(7) Multifunction
• The input/output of D5 can be used even when INT is used. Be
careful when using inputs of both INT and D5 since the input
threshold value of INT pin is different from that of port D5.
• “H“ output function of port C can be used even when the
CNTR (output) is used.
Rev.1.01 Feb 15, 2008 Page 69 of 146
REJ03B0224-0101
455A Group
(10)D5/INT pin
(3) Bit 2 of register I1
When the interrupt valid waveform of the D5/INT pin is
changed with the bit 2 of register I1 in software, be careful
about the following notes.
(1) Bit 3 of register I1
When the input of the D5/INT pin is controlled with the bit 3
of register I1 in software, be careful about the following
notes.
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 68.) and then, change the bit 2 of register I1 is
changed.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 68.).
• Depending on the input state of the D5/INT pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of
register I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to “0” (refer
to (1) in Figure 66.) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0
flag to “0” after executing at least one instruction (refer to (2)
in Figure 66.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
68.).
Also, set the NOP instruction for the case when a skip is
performed with the SNZ0 instruction (refer to (3) in Figure
66.).
•
•
•
•
•
•
LA 4
; (×××02)
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
; (×××02)
TV1A
LA 12
TI1A
NOP
SNZ0
; The SNZ0 instruction is valid ......(1)
; (×1××2)
; Interrupt valid waveform is changed
.......................................................(2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
; The SNZ0 instruction is valid ...... (1)
; (1×××2)
; Control of INT pin input is changed
...................................................... (2)
; The SNZ0 instruction is executed
(EXF0 flag cleared)
NOP
.......................................................(3)
NOP
...................................................... (3)
•
•
•
•
•
•
×: these bits are not used here.
×: these bits are not used here.
Fig 66. External 0 interrupt program example-1
Fig 68. External 0 interrupt program example-3
(2) Bit 3 of register I1
When the bit 3 of register I1 is cleared to “0”, the power
down mode is selected and the input of INT pin is disabled,
be careful about the following notes.
• When the INT pin input is disabled (register I13 = “0”), set the
key-on wakeup of INT pin to be invalid (register K20 = “0”)
before system enters to the power down mode. (refer to (1) in
Figure 67.).
•
•
•
LA 0
TK2A
DI
; (×××02)
; INT0 key-on wakeup disabled .....(1)
EPOF
POF2
; RAM back-up
•
•
•
×: these bits are not used here.
Fig 67. External 0 interrupt program example-2
Rev.1.01 Feb 15, 2008 Page 70 of 146
REJ03B0224-0101
455A Group
(11)Prescaler
(18)Prescaler, timer 1 count start timing and count time
when operation starts
Stop prescaler counting and then execute the TABPS instruction
to read its data.
Stop prescaler counting and then execute the TPSAB instruction
to write data to prescaler.
Count starts from the first rising edge of the count source (2) in
Figure 69 after prescaler and timer operations start (1) in Figure
69.
Time to first underflow (3) in Figure 69 is shorter (for up to 1
period of the count source) than time among next underflow (4)
in Figure 69 by the timing to start the timer and count source
operations after count starts.
(12)Timer count source
Stop timer 1, 2 or LC counting to change its count source.
When selecting CNTR input as the count source of timer 1, timer
1 operates synchronizing with the count edge (falling edge or
rising edge) of CNTR input selected by software.
(13)Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.
(2)
(14)Writing to the timer
Count source
Stop timer 1, 2 or LC counting and then execute the T1AB,
T2AB, T2R2L or TLCA instruction to write data to timer.
Count source
(When falling edge of
CNTR input is selected)
3
2
1
0
3
2
1
0
3
2
Timer 1 value
(15)Writing to reload register
In order to write a data to the reload register R1 while the timer 1
is operating, execute the TR1AB instruction except a timing of
the timer 1 underflow.
In order to write a data to the reload register R2H while the timer
2 is operating, execute the T3HAB instruction except a timing of
the timer 2 underflow.
Timer 1 underflow signal
(3)
(1) Timer start
(4)
Fig 69. Timer count start timing and count time when
operation starts (1)
(16)PWM signal
If the timer 2 count stop timing and the timer 2 underflow timing
overlap during output of the PWM signal, a hazard may occur in
the PWM output waveform.
(19)Timer 2, LC count start timing and count time when
operation starts
When “H” interval expansion function of the PWM signal is
used, set “1” or more to reload register R2H.
Set the port C output latch to “0” to output the PWM signal from
C/CNTR pin.
Count starts from the first edge of the count source (2) in Figure
70 after timer 2 and LC operation start (1) in Figure 70.
Time to first underflow (3) in Figure 70 is different (for up to 1
period of the count source) from time among next underflow (4)
in Figure 70 by the timing to start the timer and count source
operations after count starts.
(17)Timer 3
Stop timer 3 counting to change its count source.
When operating timer 3 during clock operating mode, set 1 cycle
or more of count source to the following period; from setting bit
3 of register W3 to “1” till executing the POF instruction.
(2)
Count source
3
2
1
0
3
2
1
0
3
2
Timer value
Timer underflow signal
(3)
(4)
(1) Timer start
Fig 70. Timer count start timing and count time when
operation starts (2)
Rev.1.01 Feb 15, 2008 Page 71 of 146
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455A Group
(20)Watchdog timer
(23)External clock
• The watchdog timer function is valid after system is released
from reset. When not using the watchdog timer function,
execute the DWDT instruction and the WRST instruction
continuously, and clear the WEF flag to “0” to stop the
watchdog timer function.
• The contents of WDF1 flag and timer WDT are initialized at
the power down.
• When using the watchdog timer and the power down, initialize
the WDF1 flag with the WRST instruction just before the
microcomputer enters the power down mode.
Be careful that the maximum value of the oscillation frequency
when using the external clock differs from the value when using
the ceramic resonator (refer to the recommended operating
condition).
Also, note that the power-down mode (POF or POF2 instruction)
cannot be used when using the external clock.
(24)QzROM
(1) Be careful not to apply overvoltage to MCU. The contents
of QzROM may be overwritten because of overvoltage.
Take care especially at turning on the power.
Also, set the NOP instruction after the WRST instruction, for
the case when a skip is performed with the WRST instruction.
(2) As for the product shipped in blank, Renesas does not
perform the writing test to user ROM area after the
assembly process though the QzROM writing test is
performed enough before the assembly process. Therefore, a
writing error of approx. 0.1 % may occur. Moreover, please
note the contact of cables and foreign bodies on a socket,
etc. because a writing environment may cause some writing
errors.
(21)Voltage drop detection circuit
The voltage drop detection circuit detection voltage of this
product is set up lower than the minimum value of the supply
voltage of the recommended operating conditions.
When the supply voltage of a microcomputer falls below to the
minimum value of recommended operating conditions and
regoes up (ex. battery exchange of an application product),
depending on the capacity value of the bypass capacitor added to
the power supply pin, the following case may cause program
failure (Figure 71);
(25)Notes On ROM Code Protect (QzROM product
shipped after writing)
As for the QzROM product shipped after writing, the ROM code
protect is specified according to the ROM option setup data in
the mask file which is submitted at ordering.
The ROM option setup data in the mask file is “0016” for protect
enabled or “FF16” for protect disabled.
-
supply voltage does not fall below to VRST , and its voltage re-
goes up with no reset.
In such a case, please design a system which supply voltage is
-
once reduced below to VRST and re-goes up after that.
Note that the mask file which has nothing at the ROM option
data or has the data other than “0016” and “FF16” can not be
accepted.
VDD
Recommended operating
condition min. value
(26)Data Required for QzROM Writing Orders
+
VRST
The following are necessary when ordering a QzROM product
shipped after writing:
1. QzROM Writing Confirmation Form*
VRST-
No reset
Program failure may occur.
2. Mark Specification Form*
3. ROM data...........Mask file
* For the QzROM writing confirmation form and the mark
specification form, refer to the “Renesas Technology Corp.”
Homepage (http://www.renesas.com/homepage.jsp).
Note that we cannot deal with special font marking (customer’s
trademark etc.) in QzROM microcomputer.
Normal operation
VDD
Recommended operating
condition min. value
+
VRST
VRST-
Reset
-
Fig 71. VDD and VRST
(22)On-chip oscillator
The clock frequency of the on-chip oscillator depends on the
supply voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
Also, the oscillation stabilize wait time after system is released
from reset is generated by the on-chip oscillator clock. When
considering the oscillation stabilize wait time after system is
released from reset, be careful that the variable frequency of the
on-chip oscillator clock.
Rev.1.01 Feb 15, 2008 Page 72 of 146
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455A Group
NOTES ON NOISE
Countermeasures against noise are described below.
The following countermeasures are effective against noise in
theory, however, it is necessary not only to take measures as
follows but to evaluate before actual use.
Noise
(1) Shortest wiring length
The wiring on a printed circuit board can function as an antenna
which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the
XIN
XOUT
VSS
XIN
XOUT
VSS
possibility of noise insertion into a microcomputer.
(1) Wiring for RESET input pin
Make the length of wiring which is connected to the RESET
input pin as short as possible.
Especially, connect a capacitor across the RESET input pin
and the VSS pin with the shortest possible wiring.
N.G.
O.K.
Fig 73. Wiring for clock I/O pins
• Reason
In order to reset a microcomputer correctly, 1 machine cycle or
more of the width of a pulse input into the RESET pin is
required.
If noise having a shorter pulse width than this is input to the
RESET input pin, the reset is released before the internal state
of the microcomputer is completely initialized.
This may cause a program runaway.
• Reason
If noise enters clock I/O pins, clock waveforms may be
deformed. This may cause a program failure or program
runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an
oscillator, the correct clock will not be input in the
microcomputer.
Noise
(3) Wiring to CNVSS pin
Connect an approximately 5 kΩ resistor to the VPP pin and
also to the GND pattern supplied to the VSS pin with
shortest possible wiring.
Reset
RESET
circuit
• Reason
VSS
VSS
The CNVSS pin is the power source input pin for the built-in
QzROM. When programming in the built-in QzROM, the
impedance of the CNVSS pin is low to allow the electric
current for writing flow into the QzROM. Because of this,
noise can enter easily. If noise enters the CNVSS pin, abnormal
instruction codes or data are read from the built-in QzROM,
which may cause a program runaway.
N.G.
Reset
circuit
RESET
VSS
VSS
(Note)
The shortest
CNVss
O.K.
Fig 72. Wiring for the RESET input pin
about 5kΩ
(2) Wiring for clock input/output pins
VSS
• Make the length of wiring which is connected to clock I/O
pins as short as possible.
The shortest
(Note)
• Make the length of wiring across the grounding lead of a
capacitor which is connected to an oscillator and the VSS
pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other
VSS patterns.
Note: This indicates pin.
Fig 74. Wiring for CNVSS pin
Rev.1.01 Feb 15, 2008 Page 73 of 146
REJ03B0224-0101
455A Group
(2) Connection of bypass capacitor across VSS line
and VDD line
(3) Oscillator concerns
Take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
Connect an approximately 0.1 µF bypass capacitor across the
VSS line and the VDD line as follows:
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far
as possible from signal lines where a current larger than the
tolerance of current value flows.
• Connect a bypass capacitor across the VSS pin and the VDD pin
at equal length.
• Connect a bypass capacitor across the VSS pin and the VDD pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS
line and VDD line.
• Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When
a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VDD pin.
VDD
VDD
Microcomputer
Mutual inductance
M
XIN
XOUT
Large
current
VSS
VSS
VSS
GND
N.G.
O.K.
Fig 76. Wiring for a large current signal line
Fig 75. Bypass capacitor across the VSS line and the
VDD line
(2) Installing oscillator away from signal lines where potential
levels change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change
frequently. Also, do not cross such signal lines over the
clock lines or the signal lines which are sensitive to noise.
• Reason
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal
rising edge or falling edge. If such lines cross over a clock line,
clock waveforms may be deformed, which causes a
microcomputer failure or a program runaway.
Do not cross
CNTR
XIN
XOUT
VSS
N.G.
Fig 77. Wiring to a signal line where potential levels
change frequently
Rev.1.01 Feb 15, 2008 Page 74 of 146
REJ03B0224-0101
455A Group
(3) Oscillator protection using VSS pattern
• Watches the operation of the interrupt processing routine by
comparing the SWDT contents with counts of interrupt
processing after the initial value N has been set.
• Detects that the interrupt processing routine has failed and
determines to branch to the program initialization routine for
recovery processing in the following case:
As for a two-sided printed circuit board, print a VSS pattern
on the underside (soldering side) of the position (on the
component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with
the shortest possible wiring.
Besides, separate this VSS pattern from other VSS patterns.
If the SWDT contents do not change after interrupt processing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at each interrupt
An example of VSS patterns on the
underside of a printed circuit board
processing.
• Determines that the main routine operates normally when the
SWDT contents are reset to the initial value N at almost fixed
cycles (at the fixed interrupt processing count).
• Detects that the main routine has failed and determines to
branch to the program initialization routine for recovery
processing in the following case:
Oscillator wiring
pattern example
XIN
XOUT
VSS
If the SWDT contents are not initialized to the initial value N
but continued to decrement and if they reach 0 or less.
Separate the VSS line for oscillation from other VSS lines
Main routine
Interrupt processing routine
(SWDT) ← (SWDT)−1
Interrupt processing
Fig 78. VSS pattern on the underside of an oscillator
(SWDT) ← N
(4) Setup for I/O ports
Setup I/O ports using hardware and software as follows:
EI
<Hardware>
Main processing
• Connect a resistor of 100 Ω or more to an I/O port in series.
<Software>
> 0
(SWDT)
≤ 0?
• As for an input port, read data several times by a program for
checking whether input levels are equal or not.
• As for an output port or an I/O port, since the output data may
reverse because of noise, rewrite data to its output latch at
fixed periods.
≠ N
RTI
≤ 0
(SWDT)
= N?
Return
N
Main routine
errors
• Rewrite data to pull-up control registers at fixed periods.
Interrupt processing
routine errors
(5) Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it
can be detected by a software watchdog timer and the
microcomputer can be reset to normal operation. This is
equal to or more effective than program runaway detection
by a hardware watchdog timer. The following shows an
example of a watchdog timer provided by software.
Fig 79. Watchdog timer by software
In the following example, to reset a microcomputer to
normal operation, the main routine detects errors of the
interrupt processing routine and the interrupt processing
routine detects errors of the main routine.
This example assumes that interrupt processing is repeated
multiple times in a single main routine processing.
<The main routine>
• Assigns a single word of RAM to a software watchdog timer
(SWDT) and writes the initial value N in the SWDT once at
each execution of the main routine. The initial value N should
satisfy the following condition:
N + 1 ≥
As the main routine execution cycle may change because of
an interrupt processing or others, the initial value N should
have a margin.
Rev.1.01 Feb 15, 2008 Page 75 of 146
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455A Group
CONTROL REGISTERS
R/W (Note 1)
TAV1/TV1A
Interrupt control register V1
at reset : 00002
at power down : 00002
0
1
0
1
0
1
0
1
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
V13 Timer 2 interrupt enable bit
V12 Timer 1 interrupt enable bit
V11 Not used
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
V10 External 0 interrupt enable bit
R/W
TAV2/TV2A
Interrupt control register V2
V23 Not used
at reset : 00002
at power down : 00002
0
1
0
1
0
1
0
1
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
V22 Not used
V21 Not used
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
V20 Timer 3 interrupt enable bit
R/W
TAI1/TI1A
Interrupt control register I1
at reset : 00002
at power down : state retained
0
1
INT pin input disabled
INT pin input enabled
I13 INT pin input control bit (Note 2)
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
0
1
Interrupt valid waveform for INT pin/
I12
return level selection bit (Note 2)
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
0
1
0
1
One-sided edge detected
I11 INT pin edge detection circuit control bit
Both edges detected
Timer 1 count start synchronous circuit not selected
Timer 1 count start synchronous circuit selected
INT pin timer 1 count start synchronous
I10
circuit selection bit
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
Rev.1.01 Feb 15, 2008 Page 76 of 146
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455A Group
R/W
TAMR/TMRA
Clock control register MR
at reset : 11002
MR3 MR2
at power down : state retained
Operation mode
MR3
0
0
1
1
0
1
0
1
Through mode
Operation mode selection bits
Frequency divided by 2 mode
Frequency divided by 4 mode
Frequency divided by 8 mode
MR2
MR1
MR0
MR1 MR0
System clock
0
0
1
1
0
1
0
1
f(HSOCO)
f(XIN)
System clock selection bits (Note 2)
Clock control register RG
f(XCIN)
f(LSOCO)
W
TRGA
at reset : 10002
at power down : state retained
0
1
0
1
0
1
0
1
Low-speed on-chip oscillator (f(LSOCO)) oscillation available
Low-speed on-chip oscillator (f(LSOCO)) oscillation stop
Low-speed on-chip oscillator (f(LSOCO))
control bit (Note 3)
RG3
Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected
Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected
Main clock (f(XIN)) oscillation available
RG2 Sub-clock (f(XCIN)) control bit (Note 3)
RG1 Main-clock (f(XIN)) control bit (Note 3)
Main clock (f(XIN)) oscillation stop
High-speed on-chip oscillator (f(HSOCO)) oscillation available
High-speed on-chip oscillator (f(HSOCO)) oscillation stop
High-speed on-chip oscillator (f(HSOCO))
control bit (Note 3)
RG0
Note 1. R” represents read enabled, and “W” represents write enabled.
Note 2. The stopped clock cannot be selected for system clock.
Note 3. The oscillation circuit selected for system clock cannot be stopped.
Rev.1.01 Feb 15, 2008 Page 77 of 146
REJ03B0224-0101
455A Group
W
TAPP
Timer control register PA
PA0 Prescaler control bit
at reset : 02
at power down : 02
0
1
Stop (state retained)
Operating
R/W (Note 1)
TAW1/TW1A
Timer control register W1
at reset : 00002
at power down : state retained
0
1
0
1
Timer 1 count auto-stop circuit not selected
Timer 1 count auto-stop circuit selected
Stop (state retained)
Timer 1 count auto-stop circuit selection bit
(Note 2)
W13
W12 Timer 1 control bit
Operating
W11
W10
Count source
W11
0
0
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 1 count source selection bits (Note 3)
0
1
1
0
Timer 3 underflow signal (T3UDF)
CNTR input
W10
1
1
R/W
TAW2/TW2A
Timer control register W2
at reset : 00002
at power down : 00002
0
1
0
1
0
1
0
1
CNTR pin output invalid
CNTR pin output valid
W23 CNTR pin function control bit
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
PWM signal
“H” interval expansion function control bit
W22
W21 Timer 2 control bit
Operating
XIN input
W20 Timer 2 count source selection bit
Prescaler output (ORCLK)/2
R/W
TAW3/TW3A
Timer control register W3
W33 Timer 3 control bit
at reset : 00002
at power down : state retained
0
1
Stop (initial state)
Operating
W32 W31 W30
Count value
W32
000
001
010
011
100
101
110
111
Underflow every 512 count
Underflow every 1024 count
Underflow every 2048 count
Underflow every 4096 count
Underflow every 8192 count
Underflow every 16384 count
Underflow every 32768 count
W31
Timer 3 count value selection bits
W30
Underflow every 65536 count
R/W
TAW4/TW4A
Timer control register W4
W43 Timer LC control bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Stop (state retained)
Operating
Bit 4 (T34) of timer 3
System clock (STCK)
W42 Timer LC count source selection bit
CNTR output auto-control circuit not selected
CNTR output auto-control circuit selected
Falling edge
CNTR pin output auto-control circuit
selection bit
W41
W40 CNTR pin input count edge selection bit
Rising edge
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. This function is valid only when the timer 1 count start synchronous circuit is selected (I10 =“1”).
Note 3. Port C output is invalid when CNTR input is selected for the timer 1 count source.
Rev.1.01 Feb 15, 2008 Page 78 of 146
REJ03B0224-0101
455A Group
R/W
TAW5/TW5A
Timer control register W5
at reset : 00002
at power down : state retained
0
1
0
1
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
W53 Not used
W52 Not used
W51 W52
Count source
W51
00
01
10
11
XCIN input
Timer 3 count source selection bits
ORCLK input
W50
Low-speed on-chip oscillator
High-speed on-chip oscillator
R/W
TAL1/TL1A
LCD control register L1
at reset : 00002
at power down : state retained
0
1
0
1
2r × 3, 2r × 2
r × 3, r × 2
Stop (OFF)
Operating
Internal dividing resistor for LCD power
supply selection bit (Note 2)
L13
L12 LCD control bit
L11 L1
Duty
Bias
L11
0
0
1
1
0
1
0
1
Not available
Not available
1/2
1/3
1/4
1/2
1/3
1/3
LCD duty and bias selection bits
L10
W
TL2A
LCD control register L2
at reset : 00002
at power down : state retained
0
SEG0
VLC3
L23 SEG0/VLC3 pin function switch bit (Note 3)
L22 SEG1/VLC2 pin function switch bit (Note 4)
L21 SEG2/VLC1 pin function switch bit (Note 4)
1
0
1
0
1
0
1
SEG1
VLC2
SEG2
VLC1
Internal dividing resistor valid
Internal dividing resistor invalid
Internal dividing resistor for LCD power
L20
supply control bit
W
TL3A
LCD control register L3
L33 P23/SEG27 pin function switch bit
L32 P22/SEG26 pin function switch bit
L31 P21/SEG25 pin function switch bit
L30 P20/SEG24 pin function switch bit
at reset : 11112
at power down : state retained
0
1
0
1
0
1
0
1
SEG27
P23
SEG26
P22
SEG25
P21
SEG24
P20
Note 1. ”R” represents read enabled, and “W” represents write enabled.
Note 2. “r (resistor) multiplied by 3” is used at 1/3 bias, and “r multiplied by 2” is used at 1/2 bias.
Note 3. VLC3 is connected to VDD internally when SEG0 pin is selected.
Note 4. Use internal dividing resistor when SEG1 and SEG2 pins are selected.
Rev.1.01 Feb 15, 2008 Page 79 of 146
REJ03B0224-0101
455A Group
W
TC1A
LCD control register C1
at reset : 11112
at power down : state retained
at power down : state retained
at power down : state retained
0
1
0
1
0
1
0
1
SEG19
P03
C13 P03/SEG19 pin function switch bit
C12 P02/SEG18 pin function switch bit
C11 P01/SEG17 pin function switch bit
C10 P00/SEG16 pin function switch bit
SEG18
P02
SEG17
P01
SEG16
P00
W
TC2A
LCD control register C2
C23 P13/SEG23 pin function switch bit
C22 P12/SEG22 pin function switch bit
C21 P11/SEG21 pin function switch bit
C20 P10/SEG20 pin function switch bit
at reset : 11112
0
1
0
1
0
1
0
1
SEG23
P13
SEG22
P12
SEG21
P11
SEG20
P10
W
TC3A
LCD control register C3
C33 P33/SEG31 pin function switch bit
C32 P32/SEG30 pin function switch bit
C31 P31/SEG29 pin function switch bit
C30 P30/SEG28 pin function switch bit
at reset : 11112
0
1
0
1
0
1
0
1
SEG31
P33
SEG30
P32
SEG29
P31
SEG28
P30
Note 1.“R” represents read enabled, and “W” represents write enabled. .
Rev.1.01 Feb 15, 2008 Page 80 of 146
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455A Group
R/W
TAK0/TK0A
Key-on wakeup control register K0
at reset : 00002
at power down : state retained
at power down : state retained
at power down : state retained
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Ports P12 and P13 key-on wakeup
control bit
K03
K02
K01
K00
Ports P10 and P11 key-on wakeup
control bit
Ports P02 and P03 key-on wakeup
control bit
Ports P00 and P01 key-on wakeup
control bit
R/W
TAK1/TK1A
Key-on wakeup control register K1
at reset : 00002
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K13 Port P23 key-on wakeup control bit
K12 Port P22 key-on wakeup control bit
K11 Port P21 key-on wakeup control bit
K10 Port P20 key-on wakeup control bit
R/W
TAK2/TK2A
Key-on wakeup control register K2
at reset : 00002
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Return by level
Ports P32 and P33 key-on wakeup
control bit (Note 3)
K23
Ports P30 and P31 key-on wakeup
control bit (Note 2)
K22
K21 INT pin return condition selection bit
K20 INT pin key-on wakeup control bit
Return by edge
Key-on wakeup invalid
Key-on wakeup valid
R/W
TAK3/TK3A
Key-on wakeup control register K3
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
K33 Ports D6 and D7 key-on wakeup control bit
K32 Ports D4 and D5 key-on wakeup control bit
K31 Ports D2 and D3 key-on wakeup control bit
K30 Ports D0 and D1 key-on wakeup control bit
Note 1. “R” represents read enabled, and “W” represents write enabled.
Note 2. To be invalid (K22 = “0”) key-on wakeup of ports P30 and P31, set the registers K30 and K31 to “0.”
Note 3. To be invalid (K23 = “0”) key-on wakeup of ports P32 and P33, set the registers K32 and K33 to “0.”
Rev.1.01 Feb 15, 2008 Page 81 of 146
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455A Group
R/W
TAPU0/TPU0A
Pull-up control register PU0
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Port P12 and P13 pull-up transistor control
bit
PU0
PU0
PU0
PU0
3
2
1
0
Port P10 and P11 pull-up transistor control
bit
Port P02 and P03 pull-up transistor control
bit
Port P00 and P01 pull-up transistor control
bit
R/W
TAPU1/TPU1A
Pull-up control register PU1
Port P23 pull-up transistor control bit
Port P22 pull-up transistor control bit
Port P21 pull-up transistor control bit
Port P20 pull-up transistor control bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU1
3
2
PU1
PU1
1
PU1
0
R/W
TAPU2/TPU2A
Pull-up control register PU2
Port P33 pull-up transistor control bit
Port P32 pull-up transistor control bit
Port P31 pull-up transistor control bit
Port P30 pull-up transistor control bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU2
PU2
PU2
PU2
3
2
1
0
R/W
TAPU3/TPU3A
Pull-up control register PU3
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
Pull-up transistor OFF
Pull-up transistor ON
PU3
PU3
PU3
PU3
3
2
1
0
Port D6 and D7 pull-up transistor control bit
Port D4 and D5 pull-up transistor control bit
Port D2 and D3 pull-up transistor control bit
Port D0 and D1 pull-up transistor control bit
Note 1. “R” represents read enabled, and “W” represents write enabled.
Rev.1.01 Feb 15, 2008 Page 82 of 146
REJ03B0224-0101
455A Group
W
TFR0A
Port output structure control register FR0
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
N-channel open-drain output
CMOS output
Ports P12 and P13 output structure selection
bit
FR0
FR0
FR0
FR0
3
2
1
0
N-channel open-drain output
CMOS output
Ports P10 and P11 output structure selection
bit
N-channel open-drain output
CMOS output
Ports P02 and P03 output structure selection
bit
N-channel open-drain output
CMOS output
Ports P00 and P01 output structure selection
bit
W (Note 1)
TFR1A
Port output structure control register FR1
Ports D3 output structure selection bit
Ports D2 output structure selection bit
Ports D1 output structure selection bit
Ports D0 output structure selection bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
N-channel open-drain output
CMOS output
FR1
3
2
N-channel open-drain output
CMOS output
FR1
N-channel open-drain output
CMOS output
FR1
1
N-channel open-drain output
CMOS output
FR1
0
W
TFR2A
Port output structure control register FR2
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
N-channel open-drain output
CMOS output
Ports P32 and P33 output structure selection
bit
FR2
FR2
FR2
FR2
3
2
1
0
N-channel open-drain output
CMOS output
Ports P30 and P31 output structure selection
bit
N-channel open-drain output
CMOS output
Ports D5 output structure selection bit
Ports D4 output structure selection bit
N-channel open-drain output
CMOS output
W
TFR3A
Port output structure control register FR3
Ports P23 output structure selection bit
Ports P22 output structure selection bit
Ports P21 output structure selection bit
Ports P20 output structure selection bit
at reset : 00002
at power down : state retained
0
1
0
1
0
1
0
1
N-channel open-drain output
CMOS output
FR3
FR3
FR3
FR3
3
2
1
0
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
N-channel open-drain output
CMOS output
Note 1. “W” represents write enabled.
Rev.1.01 Feb 15, 2008 Page 83 of 146
REJ03B0224-0101
455A Group
INSTRUCTIONS
The symbols shown below are used in the following list of
instruction function and the machine instructions.
Each instruction is described as follows;
1. Index list of instruction function
2. Machine instructions (index by alphabet)
3. Machine instructions (index by function)
4. Instruction code table
SYMBOL
Symbol
Contents
Symbol
R2H
Contents
Timer 2 reload register (8 bits)
Timer LC reload register (4 bits)
Prescaler
A
B
Register A (4 bits)
Register B (4 bits)
Register DR (3 bits)
Register E (8 bits)
RLC
PS
DR
E
T1
Timer 1
V1
Interrupt control register V1 (4 bits)
Interrupt control register V2 (4 bits)
Interrupt control register I1 (4 bits)
Timer control register PA (1 bit)
T2
Timer 2
V2
TLC
T1F
T2F
T3F
WDF1
WEF
INTE
EXF0
VDF
P
Timer LC
I1
Timer 1 interrupt request flag
Timer 2 interrupt request flag
Timer 3 interrupt request flag
Watchdog timer flag
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
Voltage drop detection circuit flag
Power down flag
PA
W1
W2
W3
W4
W5
MR
RG
L1
Timer control register W1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer control register W4 (4 bits)
Timer control register W5 (5 bits)
Clock control register MR (4 bits)
Clock control register RG (3 bits)
LCD control register L1 (4 bits)
D
Port D (8 bits)
L2
LCD control register L2 (4 bits)
P0
Port P0 (4 bits)
L3
LCD control register L3 (4 bits)
P1
Port P1 (4 bits)
C1
C2
C3
K0
LCD control register C1 (4 bits)
P2
Port P2 (4 bits)
LCD control register C2 (4 bits)
P3
Port P3 (4 bits)
LCD control register C3 (4 bits)
C
Port C (1 bit)
Key-on wakeup control register K0 (4 bits)
Key-on wakeup control register K1 (4 bits)
Key-on wakeup control register K2 (4 bits)
Key-on wakeup control register K3 (4 bits)
Pull-up control register PU0 (4 bits)
Pull-up control register PU1 (4 bits)
Pull-up control register PU2 (4 bits)
Pull-up control register PU3 (4 bits)
Port output structure control register FR0 (4 bits)
Port output structure control register FR1 (4 bits)
Port output structure control register FR2 (4 bits)
Port output structure control register FR3 (4 bits)
Register X (4 bits)
INT
INT pin (1 bit)
K1
K2
x
y
z
p
n
i
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal constant
Hexadecimal constant
Hexadecimal constant
K3
PU0
PU1
PU2
PU3
FR0
FR1
FR2
FR3
X
j
A3 A2 A1 A0 Binary notation of hexadecimal variable A
(same for others)
←
(
Direction of data movement
)
Contents of registers and memories
Y
Register Y (4 bits)
−
Negate, Flag unchanged after executing instruction
RAM address pointed by the data pointer
Label indicating address a6 a5 a4 a3 a2 a1 a0
Z
Register Z (2 bits)
M (DP)
a
DP
Data pointer (10 bits)
(It consists of registers X, Y, and Z)
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0 in page
p6 p5 p4 p3 p2 p1 p0
PC
Program counter (14 bits)
PCH
PCL
SK
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits × 8)
Stack pointer (3 bits)
C+x
?
Hex. C + Hex. number x (also same for others)
Decision of state shown before “?”
SP
← →
Data exchange between a register and memory
CY
Carry flag
UPTF
RPS
R1
High-order bit reference enable flag
Prescaler reload register (8 bits)
Timer 1 reload register (8 bits)
Timer 2 reload register (8 bits)
R2L
Note 1. The 455A Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased
by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if
the TABP p, RT, or RTS instruction is skipped.
Rev.1.01 Feb 15, 2008 Page 84 of 146
REJ03B0224-0101
455A Group
INDEX LIST OF INSTRUCTION FUNCTION
Group-
Group-
ing
Mnemonic
Function
Page
Mnemonic
LA n
Function
Page
ing
TAB
TBA
TAY
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
103 122
110 122
110 122
119 122
112 122
(A) ← n
92 124
n = 0 to 15
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
(UPTF) = 1,
104 124
TYA
TEAB
(DR2) ← 0
(DR1, DR0) ← (ROM(PC))9, 8
(E7−E4) ← (B)
(E3−E0) ← (A)
(B) ← (ROM(PC))7−4
(A) ← (ROM(PC))3−0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
TABE
(B) ← (E7−E4)
(A) ← (E3−E0)
104 122
TDA
TAD
(DR2−DR0) ← (A2−A0)
111 122
105 122
AM
(A) ← (A) + (M(DP))
87 124
87 124
(A2−A0) ← (DR2−DR0)
(A3) ← 0
AMC
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
TAZ
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
110 122
A n
(A) ← (A) + n
87 124
n = 0 to 15
TAX
(A) ← (X)
110 122
108 122
AND
OR
(A) ← (A)AND(M(DP))
(A) ← (A)OR(M(DP))
(CY) ← 1
87 124
94 124
98 124
96 124
102 124
89 124
95 124
TASP
(A2−A0) ← (SP2−SP0)
(A3) ← 0
LXY x, y
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
93 122
SC
RC
(CY) ← 0
LZ z
INY
(Z) ← z, z = 0 to 3
(Y) ← (Y) + 1
93 122
92 122
90 122
106 122
SZC
CMA
RAR
(CY) = 0 ?
(A) ← (A)
DEY
TAM j
(Y) ← (Y) − 1
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
CY
A3A2A1A0
SB j
(Mj(DP)) ← 1
j = 0 to 3
97 124
95 124
101 124
XAM j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
120 122
120 122
RB j
SZB j
(Mj(DP)) ← 0
j = 0 to 3
XAMD j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Mj(DP)) = 0 ?
j = 0 to 3
(Y) ← (Y) − 1
SEAM
SEA n
(A) = (M(DP)) ?
99 126
98 126
XAMI j
TMA j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
120 122
115 122
(A) = n ?
n = 0 to 15
(Y) ← (Y) + 1
B a
(PCL) ← a6−a0
88 126
88 126
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
BL p, a
(PCH) ← p
(PCL) ← a6−a0
Note 1. M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95.
BLA p
(PCH) ← p
88 126
(PCL) ← (DR2−DR0, A3−A0)
Rev.1.01 Feb 15, 2008 Page 85 of 146
REJ03B0224-0101
455A Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
Group-
ing
Mnemonic
Function
Page
Mnemonic
Function
(PA) ← (A)
Page
ing
BM a
(SP) ← (SP) + 1
88 126
TPAA
TAW1
TW1A
TAW2
TW2A
TAW3
TW3A
TAW4
TW4A
TAW5
TW5A
TABPS
116 128
109 128
118 128
109 128
118 128
109 128
119 128
109 128
119 128
119 128
119 128
104 130
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6−a0
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W3)
(W3) ← (A)
(A) ← (W4)
(W4) ← (A)
(A) ← (W5)
(W5) ← (A)
BML p, a
BMLA p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
89 126
89 126
(PCL) ← a6−a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2−DR0, A3−A0)
RTI
RT
(PC) ← (SK(SP))
(SP) ← (SP) − 1
97 126
96 126
97 126
(PC) ← (SK(SP))
(SP) ← (SP) − 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) − 1
(B) ← (TPS7−TPS4)
(A) ← (TPS3−TPS0)
DI
(INTE) ← 0
(INTE) ← 1
90 128
91 128
99 128
EI
TPSAB
(RPS7−RPS4) ← (B)
(TPS7−TPS4) ← (B)
(RPS3−RPS0) ← (A)
(TPS3−TPS0) ← (A)
116 130
SNZ0
V10 = 0 : (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1 : SNZ0 = NOP
TAB1
T1AB
(B) ← (T17−T14)
(A) ← (T13−T10)
103 130
102 130
SNZI0
I12 = 0 : (INT) = “L” ?
I12 = 1 : (INT) = “H” ?
99 128
(R17−R14) ← (B)
(T17−T14) ← (B)
(R13−R10) ← (A)
(T13−T10) ← (A)
TAV1
TV1A
TAV2
TV2A
TAI1
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
(I1) ← (A)
108 128
118 128
108 128
118 128
105 128
113 128
TR1AB
TAB2
(R17−R14) ← (B)
(R13−R10) ← (A)
117 130
104 130
102 130
(B) ← (T27−T24)
(A) ← (T23−T20)
T2AB
(R2L7−R2L4) ← (B)
(T27−T24) ← (B)
(R2L3−R2L0) ← (A)
(T23−T20) ← (A)
TI1A
T2R2L
T2HAB
(T27−T20) ← (R2L7−R2L0)
103 130
103 130
(R2H7−R2H4) ← (B)
(R2H3−R2H0) ← (A)
Note 1. M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95.
Rev.1.01 Feb 15, 2008 Page 86 of 146
REJ03B0224-0101
455A Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Group-
Group-
ing
Mnemonic
Function
Page
Mnemonic
Function
(PU3) ← (A)
Page
ing
TPU3A
TAK0
TK0A
TAK1
TK1A
TAK2
TK2A
TAK3
TK3A
TAL1
117 132
105 134
113 134
105 134
113 134
106 134
114 134
106 134
114 134
106 134
114 134
114 134
115 134
111 134
111 134
111 134
107 134
115 134
117 134
TLCA
(RLC) ← (A)
115 130
(TLC) ← (A)
(A) ← (K0)
(K0) ← (A)
(A) ← (K1)
(K1) ← (A)
(A) ← (K2)
(K2) ← (A)
(A) ← (K3)
(K3) ← (A)
(A) ← (L1)
(L1) ← (A)
(L2) ← (A)
(L3) ← (A)
(C1) ← (A)
(C2) ← (A)
(C3) ← (A)
(A) ← (MR)
(MR) ← (A)
(RG2−RG0) ← (A2−A0
SNZT1
SNZT2
SNZT3
V12 = 0 : (T1F) = 1 ?
(T1F) ← 0
V12 = 1 : SNZT1=NOP
100 130
100 130
100 130
V13 = 0 : (T2F) = 1 ?
(T2F) ← 0
V13 = 1 : SNZT2=NOP
V20 = 0 : (T3F) = 1 ?
(T3F) ← 0
V20 = 1 : SNZT3=NOP
IAP0
(A) ← (P0)
91 132
93 132
91 132
94 132
92 132
94 132
92 132
94 132
89 132
96 132
98 132
102 132
96 132
98 132
112 132
112 132
112 132
113 132
107 132
116 132
107 132
116 132
107 132
117 132
108 132
OP0A
IAP1
(P0) ← (A)
TL1A
TL2A
TL3A
TC1A
TC2A
TC3A
TAMR
TMRA
TRGA
(A) ←(P1)
OP1A
IAP2
(P1) ← (A)
(A) ← (P2)
OP2A
IAP3
(P2) ← (A)
(A) ← (P3)
OP3A
CLD
(P3) ← (A)
(D) ← 1
RD
(D(Y)) ← 0, (Y) = 0 to 4
(D(Y)) ← 1, (Y) = 0 to 4
(D(Y)) = 0 ?, (Y) = 0 to 4
(C) ← 0
NOP
(PC) ← (PC)+1
93 136
95 136
95 136
91 136
99 136
100 136
119 136
SD
POF
Transition to clock operating
Transition to RAM back-up
POF instruction valid
(P) = 1 ?
SZD
POF2
EPOF
SNZP
SNZVD
WRST
RCP
SCP
(C) ← 1
TFR0A
TFR1A
TFR2A
TFR3A
TAPU0
TPU0A
TAPU1
TPU1A
TAPU2
TPU2A
TAPU3
(FR0) ← (A)
(FR1) ← (A)
(FR2) ← (A)
(FR3) ← (A)
(A) ← (PU0)
(PU0) ← (A)
(A) ← (PU1)
(PU1) ← (A)
(A) ← (PU2)
(PU2) ← (A)
(A) ← (PU3)
(VDF) = 1?
(WDF1) = 1 ?
(WDF1) ← 0
DWDT
Stop of watchdog timer func-
tion enabled
90 136
SRST
RUPT
SUPT
SVDE
System reset
(UPTF) ←0
(UPTF) ←1
101 136
97 136
101 136
101 136
At power down mode, volt-
age drop detection circuit
valid
RBK
(Note 1)
When TABPp instruction is
81 117
84 117
executed,
When TABPp instruction is
executed,
p6←0
SBK
(Note 1)
p6←1
Note 1. (SBK, RBK) cannot be used in the M3455AG8.
Rev.1.01 Feb 15, 2008 Page 87 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
Overflow = 0
D9
D0
0
0
0
1
1
0
n
n
n
n
0
6
0
0
n
A
B
2
16
16
16
1
1
Opera- (A) ← (A) + n
tion: n = 0 to 15
Grouping: Arithmetic operation
Description: Adds the value n in the immediate field to register A, and
stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the
result of operation.
Executes the next instruction when there is overflow as the
result of operation.
AM (Add accumulator and Memory)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
0
1
0
1
0
0
2
1
1
Opera- (A) ← (A)Å{(M(DP))
tion:
Grouping: Arithmetic operation
Description: Adds the contents of M(DP) to register A.
Stores the result in register A. The contents of carry flag
CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruc-
Number of
words
Number of
cycles
Flag CY
0/1
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
0
1
0
1
1
0
2
1
1
Opera- (A) ← (A) + (M(DP)) + (CY)
tion: (CY) ← Carry
Grouping: Arithmetic operation
Description: Adds the contents of M(DP) and carry flag CY to register
A. Stores the result in register A and carry flag CY.
AND (logical AND between accumulator and memory)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
1
1
0
0
0
0
1
8
16
2
1
1
Opera- (A) ← (A) AND (M(DP))
tion:
Grouping: Arithmetic operation
Description: Takes the AND operation between the contents of register
A and the contents of M(DP), and stores the result in regis-
ter A.
Rev.1.01 Feb 15, 2008 Page 88 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
B a (Branch to address a)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
8
+a
0
1
1
a6 a5 a4 a3 a2 a1 a0
1
a
2
16
1
1
Opera- (PCL) ← a6 to a0
tion:
Grouping: Branch operation
Description: Branch within a page : Branches to address a in the identi-
cal page.
Note:
Specify the branch address within the page including this
instruction.
BL p,a (Branch Long to address a in page p)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
E
0
0
1
1
1
p4 p3 p2 p1 p0
0
2
p
a
2
2
16
16
2
2
+p
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
a
Grouping: Branch operation
Description: Branch out of a page : Branches to address a in page p.
Note:
Opera- (PCH) ← p
tion: (PCL) ← a6 to a0
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
BLA p (Branch Long to address (D)+(A) in page p)
Instruc-
tion
code
Number of
words
Number of
Flag CY
cycles
Skip condition
-
D9
D0
0
0
0
0
0
0
1
0
0
0
0
0
0
2
1
p
0
p
2
2
16
16
2
2
-
1
p6 p5 p4
p3 p2 p1 p0
Grouping: Branch operation
Description: Branch out of a page : Branches to address (DR2 DR1 DR0
A3 A2 A1 A0)2 specified by registers D and A in page p.
Opera- (PCH) ← p
tion: (PCL) ← (DR2−R0, A3−A0)
Note:
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
BM a (Branch and Mark to address a in page 2)
Instruc-
tion
code
Number of
words
Number of
Flag CY
cycles
Skip condition
-
D9
D0
0
1
0
a6 a5 a4 a3 a2 a1 a0
1
a
a
2
16
1
1
-
Opera- (SP) ← (SP) + 1
Grouping: Subroutine call operation
tion:
(SK(SP)) ← (PC)
(PCH) ← 2
Description: Call the subroutine in page 2 : Calls the subroutine at
address a in page 2.
(PCL) ← a6−a0
Note:
Subroutine extending from page 2 to another page can
also be called with the BM instruction when it starts on
page 2.
Be careful not to over the stack because the maximum
level of subroutine nesting is 8.
Rev.1.01 Feb 15, 2008 Page 89 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BML p,a (Branch and Mark Long to address a in page p)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
c
0
0
1
1
0
p4 p3 p2 p1 p0
0
2
p
a
2
2
16
16
2
2
+p
1
p6 p5 a6 a5 a4 a3 a2 a1 a0
a
Grouping: Subroutine call operation
Description: Call the subroutine : Calls the subroutine at address a in
page p.
Opera- (SP) ← (SP) + 1
tion:
(SK(SP)) ← (PC)
(PCH) ← p
Note:
M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95
Be careful not to over the stack because the maximum
level of subroutine nesting is 8.
(PCL) ← a6−a0
BMLA p (Branch and Mark Long to address (D)+(A) in page p)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
1
0
1
0
0
0
0
0
0
2
3
p
0
p
2
2
16
16
2
2
1
p6 p5 p4
p3 p2 p1 p0
Grouping: Subroutine call operation
Description: Call the subroutine : Calls the subroutine at address (DR2
DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
Opera- (SP) ← (SP) + 1
tion:
(SK(SP)) ← (PC)
(PCH) ← p
Note:
M3455AG8: p=0 to 63 p6=0
(PCL) ← (DR2−DR0, A3−A0)
M3455AGC: p=0 to 95
Be careful not to over the stack because the maximum
level of subroutine nesting is 8.
CLD (CLear port D)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
1
0
0
0
1
0
1
1
2
16
1
1
Opera- (D) ← 1
tion:
Grouping: Input/Output operation
Description: Sets (1) to port D.
CMA (CoMplement of Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
1
1
1
0
0
0
1
C
2
16
1
1
Grouping: Arithmetic operation
Opera- (A) ←(A)
tion:
Description: Stores the one’s complement for register A’s contents in
register A.
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
DEY (DEcrement register Y)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(Y) = 15
D9
D0
0
0
0
0
0
1
0
1
1
1
0
0
2
1
0
9
7
2
2
2
16
16
16
1
1
Opera- (Y) ← (Y) −1
tion:
Grouping: RAM addresses
Description: Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped. When the contents of
register Y is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
0
0
1
0
0
4
1
1
Opera- (INTE) ← 0
tion:
Grouping: Interrupt control operation
Description: Clears (0) to interrupt enable flag INTE, and disables the
interrupt.
Note:
Interrupt is disabled by executing the DI instruction after
executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruc-
Number of
Number of
Flag CY
-
Skip condition
-
tion
words
cycles
D9
D0
code
1
0
1
0
0
1
1
1
0
0
C
1
1
Opera- Stop of watchdog timer function enabled
tion:
Grouping: Other operation
Description: Stops the watchdog timer function by the WRST instruction
after executing the DWDT instruction.
Rev.1.01 Feb 15, 2008 Page 91 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
EI (Enable Interrupt)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
0
0
1
0
1
0
0
5
6
6
5
B
0
1
2
16
16
16
16
1
1
Opera- (INTE) ← 1
tion:
Grouping: Interrupt control operation
Description: Sets (1) to interrupt enable flag INTE, and enables the
interrupt.
Note:
Interrupt is enabled by executing the EI instruction after
executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
1
0
1
1
0
1
1
0
2
1
1
Opera- POF instruction or POF2 instruction valid
tion:
Grouping: Other operation
Description: Makes the immediate after POF instruction or POF2
instruction valid by executing the EPOF instruction.
IAP0 (Input Accumulator from port P0)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
0
1
1
0
0
0
0
0
2
2
1
1
Opera- (A) ← (P0)
tion:
Grouping: Input/Output operation
Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
0
1
1
0
0
0
0
1
2
2
1
1
Opera- (A) ← (P1)
tion:
Grouping: Input/Output operation
Description: Transfers the input of port P1 to register A.
Rev.1.01 Feb 15, 2008 Page 92 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP2 (Input Accumulator from port P2)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
1
0
0
0
1
0
2
2
0
0
6
6
1
7
2
3
3
n
2
2
2
2
16
16
16
16
1
1
Opera- (A) ← (P2)
tion:
Grouping: Input/Output operation
Description: Transfers the input of port P2 to the register A.
IAP3 (Input Accumulator from port P3)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
0
1
1
0
0
0
0
n
1
1
n
1
1
1
Opera- (A) ← (P3)
tion:
Grouping: Input/Output operation
Description: Transfers the input of port P3 to the register A.
INY (INcrement register Y)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(Y) = 0
tion
D9
D0
code
0
0
0
0
0
1
0
1
1
1
Opera- (Y) ← (Y) + 1
tion:
Grouping: RAM addresses
Description: Adds 1 to the contents of register Y. As a result of addition,
when the contents of register Y is 0, the next instruction is
skipped. When the contents of register Y is not 0, the next
instruction is executed.
LA n (Load n in Accumulator)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
tion
D9
D0
code
Continuous
description
0
0
0
1
1
1
n
n
1
1
Opera- (A) ← n
tion: n = 0 to 15
Grouping: Arithmetic operation
Description: Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and exe-
cuted, only the first LA instruction is executed and other LA
instructions coded continuously are skipped.
Rev.1.01 Feb 15, 2008 Page 93 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LXY x,y (Load register X and Y with x and y)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
Continuous
description
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
2
16
1
1
Opera- (X) ← x x = 0 to 15
tion: (Y) ← y y = 0 to 15
Grouping: RAM addresses
Description: Loads the value x in the immediate field to register X, and
the value y in the immediate field to register Y. When the
LXY instructions are continuously coded and executed,
only the first LXY instruction is executed and other LXY
instructions coded continuously are skipped.
LZ z (Load register Z with z)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
8
+z
0
0
0
1
0
0
1
0
Z1 Z0
0
4
2
16
16
16
1
1
Opera- (Z) ← z z = 0 to 3
tion:
Grouping: RAM addresses
Description: Loads the value z in the immediate field to register Z.
NOP (No OPeration)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
1
Opera- (PC) ← (PC) + 1
tion:
Grouping: Other operation
Description: No operation; Adds 1 to program counter value, and others
remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
0
0
1
0
0
0
0
0
2
2
0
2
1
1
Opera- (P0) ← (A)
tion:
Grouping: Input/Output operation
Description: Outputs the contents of register A to port P0.
Rev.1.01 Feb 15, 2008 Page 94 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP1A (Output port P1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
0
0
0
1
2
2
2
2
2
2
1
2
3
2
16
16
16
16
1
1
Opera- (P1) ← (A)
tion:
Grouping: Input/Output operation
Description: Outputs the contents of register A to port P1.
OP2A (Output port P2 from Accumulator)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
0
0
1
0
0
0
1
0
2
1
1
Opera- (P2) ← (A)
tion:
Grouping: Input/Output operation
Description: Outputs the contents of the register A to port P2.
OP3A (Output port P3 from Accumulator)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
0
0
1
0
0
0
1
1
2
1
1
Opera- (P3) ← (A)
tion:
Grouping: Input/Output operation
Description: Outputs the contents of the register A to port P3.
OR (logical OR between accumulator and memory)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
1
1
0
0
1
0
1
9
2
1
1
Opera- (A) ← (A) OR (M(DP))
tion:
Grouping: Arithmetic operation
Description: Takes the OR operation between the contents of register A
and the contents of M(DP), and stores the result in register
A.
Rev.1.01 Feb 15, 2008 Page 95 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
POF (Power OFf)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
2
2
2
2
16
16
16
1
1
Opera- Transition to clock operating mode
tion:
Grouping: Other operation
Description: Puts the system in clock operating mode by executing the
POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed just before this
instruction, this instruction is equivalent to the NOP instruc-
tion.
POF2 (Power OFf2)
Instruc-
Number of
Number of
Flag CY
-
Skip condition
-
tion
words
cycles
D9
D0
code
0
0
0
0
0
0
1
0
0
0
8
1
1
Opera- Transition to RAM back-up mode
tion:
Grouping: Other operation
Description: Puts the system in RAM back-up state by executing the
POF2 instruction after executing the EPOF instruction.
Note:
If the EPOF instruction is not executed before executing
this instruction, this instruction is equivalent to the NOP
instruction.
RAR (Rotate Accumulator Right)
Instruc-
Number of
Number of
Flag CY
0/1
Skip condition
-
tion
words
cycles
D9
D0
code
0
0
0
0
0
1
1
1
0
1
D
1
1
Opera-
tion:
Grouping: Arithmetic operation
CY
A3A2A1A0
Description: Rotates 1 bit of the contents of register A including the con-
tents of carry flag CY to the right.
RB j (Reset Bit)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
C
+j
0
0
0
1
0
0
1
1
j
j
0
4
2
16
1
1
Opera- (Mj(DP)) ← 0
tion: j = 0 to 3
Grouping: Bit operation
Description: Clears (0) the contents of bit j (bit specified by the value j in
the immediate field) of M(DP).
Rev.1.01 Feb 15, 2008 Page 96 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RBK (Reset Bank flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
0
0
0
0
0
4
0
0
2
16
16
16
16
1
1
Opera-
tion:
When TABPp instruction is executed, p6←0
Grouping: Other operation
Description: Sets referring data area to pages 0 to 63 when the TABPp
instruction is executed. This instruction is valid only for the
TABPp instruction.
Note:
This instruction cannot be used in M3455AG8.
RC (Reset Carry flag)
Instruc-
tion
code
Number of
Number of
Flag CY
0
Skip condition
words
cycles
D9
D0
0
0
0
0
0
0
0
1
1
0
0
2
0
0
8
1
6
2
1
1
-
Opera- (CY) ← 0
tion:
Grouping: Arithmetic operation
Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
0
0
1
1
0
0
C
2
1
1
Opera- (C) ← 0
tion:
Grouping: Input/Output operation
Description: Clears (0) to port C.
RD (Reset port D specified by register Y)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
1
0
1
0
0
4
2
1
1
Opera- (D(Y)) ← 0
tion: (Y) = 0 to 7
Grouping: Input/Output operation
Description: Clears (0) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 7.
Do not execute this instruction if values except above are
set to register Y.
Rev.1.01 Feb 15, 2008 Page 97 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
RT (ReTurn from subroutine)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
4
4
4
5
4
6
5
8
2
2
2
2
16
16
16
16
1
2
Opera- (PC) ← (SK(SP))
tion: (SP) ← (SP) −1
Grouping: Return operation
Description: Returns from subroutine to the routine called the subrou-
tine.
RTI (ReTurn from Interrupt)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
1
0
0
0
1
1
0
1
1
Opera- (PC) ← (SK(SP))
tion: (SP) ← (SP) − 1
Grouping: Return operation
Description: Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip
status, NOP mode status by the continuous description of
the LA/LXY instruction, register A and register B to the
states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
tion
D9
D0
code
0
0
0
1
0
0
0
1
0
1
1
2
Skip at uncondition
Operation:
(PC) ← (SK(SP))
(SP) ← (SP) − 1
Grouping: Return operation
Description: Returns from subroutine to the routine called the subrou-
tine, and skips the next instruction at uncondition.
RUPT (Reset UPT flag)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
1
0
1
1
0
0
0
1
1
Opera- (UPTF) ←0
tion:
Grouping: Other operation
Description: Clears (0) to the high-order bit reference enable flag
UPTF.
Note:
Even when the table reference instruction (TABP p) is exe-
cuted, the high-order 2 bits of ROM reference data is not
transferred to register D.
SB j (Set Bit)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
C
+j
0
0
0
1
0
1
1
1
j
j
0
5
2
16
1
1
Opera- (Mj(DP)) ← 1
tion: j = 0 to 3
Grouping: Bit operation
Description: Sets (1) the contents of bit j (bit specified by the value j in
the immediate field) of M(DP).
Rev.1.01 Feb 15, 2008 Page 98 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SBK (Set BanK flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
0
0
0
0
1
0
4
1
16
2
1
1
Opera-
tion:
When TABPp instruction is executed, p6←1
Grouping: Arithmetic operation
Description: Sets referring data area to pages 64 to 127 when the
TABPp instruction is executed. This instruction is valid only
for the TABPp instruction.
Note:
This instruction cannot be used in M3455AG8.
SC (Set Carry flag)
Instruc-
tion
code
Number of Number of
Flag CY
1
Skip condition
words
1
cycles
1
D9
D0
0
0
0
0
0
0
0
1
1
1
0
0
7
16
2
-
Opera- (CY) ← 1
tion:
Grouping: Arithmetic operation
Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
0
0
1
1
0
1
2
8 D
16
2
1
1
Opera- (C) ← 1
tion:
Grouping: Input/Output operation
Description: Sets (1) to port C.
SD (Set port D specified by register Y)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
1
0
1
0
1
0
1
5
16
2
1
1
Opera- (D(Y)) ← 1
tion: (Y) = 0 to 7
Grouping: Input/Output operation
Description: Sets (1) to a bit of port D specified by register Y.
Note:
(Y) = 0 to 7.
Do not execute this instruction if values except above are
set to register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
(A) = n
n = 0 to 15
0
0
0
0
0
0
1
1
1
0
1
0
n
1
n
0
n
1
0
0
2
7
5
n
2
2
16
16
2
2
0
n
Grouping: Comparison operation
Description: Skips the next instruction when the contents of register A is
equal to the value n in the immediate field.
Opera- (A) = n ?
tion: n = 0 to 15
Executes the next instruction when the contents of register
A is not equal to the value n in the immediate field.
Rev.1.01 Feb 15, 2008 Page 99 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SEAM (Skip Equal, Accumulator with Memory)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(A) = (M(DP))
D9
D0
0
0
0
0
1
0
0
1
1
0
0
2
6
16
2
1
1
Opera- (A) = (M(DP)) ?
tion:
Grouping: Comparison operation
Description: Skips the next instruction when the contents of register A is
equal to the contents of M(DP).
Executes the next instruction when the contents of register
A is not equal to the contents of M(DP).
SNZ0 (Skip if Non Zero condition of external interrupt 0 request flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
0
0
0
0
1
1
1
0
0
0
0
3
8
16
2
1
1
V10 = 0 : (EXF0) = 1
Opera- V10 = 0 : (EXF0) = 1 ?
Grouping: Interrupt operation
tion:
(EXF0) ← 0
Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the
next instruction when external 0 interrupt request flag
EXF0 is “1”. When the EXF0 flag is “0”, executes the next
instruction.
V10 = 1 : SNZ0 = NOP
(V10 : bit 0 of the interrupt control register V1)
When V10 = 1 : This instruction is equivalent to the NOP
instruction.
SNZI0 (Skip if Non Zero condition of external Interrupt 0 input pin)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
I12 = 0 : (INT0) = “L”
I12 = 1 : (INT0) = “H”
0
0
0
0
1
1
1
0
1
0
0
3 A
16
2
1
1
Opera- I12 = 0 : (INT) = “L” ?
tion: I12 = 1 : (INT) = “H” ?
(I12 : bit 2 of the interrupt control register I1)
Grouping: Interrupt operation
Description: When I12 = 0 : Skips the next instruction when the level of
INT pin is “L”. Executes the next instruction when the level
of INT pin is “H”.
When I12 = 1 : Skips the next instruction when the level of
INT pin is “H.” Executes the next instruction when the level
of INT pin is “L”.
SNZP (Skip if Non Zero condition of Power down flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(P) = 1
D9
D0
0
0
0
0
0
0
0
0
1
1
0
0
3
16
2
1
1
Opera- (P) = 1 ?
tion:
Grouping: Other operation
Description: Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0”.
Rev.1.01 Feb 15, 2008 Page 100 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
1
0
1
0
0
0
0
0
0
0
2
8
0
16
2
1
1
V12 = 0 : (T1F) = 1
Opera- V12 = 0 : (T1F) = 1 ?
tion: (T1F) ← 0
V12 = 1 : SNZT1 = NOP
(V12 = bit 2 of interrupt control register V1)
Grouping: Timer operation
Description: When V12 = 0 : Clears (0) to the T1F flag and skips the
next instruction when timer 1 interrupt request flag T1F is
“1”. When the T1F flag is “0,” executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP
instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
1
0
1
0
0
0
0
0
0
1
2
8
1
16
2
1
1
V13 = 0 : (T2F) = 1
Opera- V13 = 0 : (T2F) = 1 ?
tion: (T2F) ← 0
V13 = 1 : SNZT2 = NOP
(V13 = bit 3 of interrupt control register V1)
Grouping: Timer operation
Description: When V13 = 0 : Clears (0) to the T2F flag and skips the
next instruction when timer 2 interrupt request flag T2F is
“1”. When the T2F flag is “0”, executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP
instruction.
SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
1
0
1
0
0
0
0
0
1
0
2
8
2
16
2
1
1
V20 = 0 : (T3F) = 1
Opera- V20 = 0 : (T3F) = 1 ?
tion: (T3F) ← 0
V20 = 1 : SNZT3 = NOP
Grouping: Timer operation
Description: When V20 = 0 : Clears (0) to the T3F flag and skips the
next instruction when timer 3 interrupt request flag T3F is
“1”. When the T3F flag is “0”, executes the next instruction.
When V20 = 1 : This instruction is equivalent to the NOP
instruction.
SNZVD (Skip if Non Zero condition of Voltage Detector flag)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
D9
D0
1
0
1
0
0
0
1
0
1
0
2
8 A
16
2
1
1
V23 = 0 : (VDF) = 1
Opera- (VDF) = 1?
tion:
Grouping: Other operation
Description: Skips the next instruction when voltage drop detection cir-
cuit flag VDF is “1”. Execute instruction when VDF is “0”.
After skipping, the contents of VDF remains unchanged.
Rev.1.01 Feb 15, 2008 Page 101 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SRST (System ReSet)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
0
0
0
0
1
0
0
2
0
5
9
1
9
3
2
16
16
16
16
1
1
Opera- System reset
tion:
Grouping: Other operation
Description: System reset occurs.
SUPT (Set UPT flag)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
1
0
1
1
0
0
1
2
1
1
Opera- (UPTF) ←1
tion:
Grouping: Other operation
Description: Sets (1) to the high-order bit reference enable flag UPTF.
When the table reference instruction (TABP p) is executed,
the high-order 2 bits of ROM reference data is transferred
to the low-order 2 bits of register D.
SVDE (Set Voltage Detector Enable flag)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
1
0
0
1
0
0
1
1
2
1
1
Opera- Voltage drop detection circuit valid at powerdown
tion: mode.
Grouping: Other operation
Description: Voltage drop detection circuit is valid at powerdown mode
(clock operating mode, RAM back-up mode)
Note:
This instruction can be used only for H version.
SZB j (Skip if Zero, Bit)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
tion
D9
D0
code
(Mj(DP)) = 0
j = 0 to 3
0
0
0
0
1
0
0
0
j
j
0
2
j
2
1
1
Opera- (Mj(DP)) = 0 ?
tion: j = 0 to 3
Grouping: Bit operation
Description: Skips the next instruction when the contents of bit j (bit
specified by the value j in the immediate field) of M(DP) is
“0”.
Executes the next instruction when the contents of bit j of
M(DP) is “1”.
Rev.1.01 Feb 15, 2008 Page 102 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZC (Skip if Zero, Carry flag )
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(CY) = 0
D9
D0
0
0
0
0
1
0
1
1
1
1
0
2
F
2
16
1
1
Opera- (CY) = 0 ?
tion:
Grouping: Arithmetic operation
Description: Skips the next instruction when the contents of carry flag
CY is “0”.
After skipping, the CY flag remains unchanged.
Executes the next instruction when the contents of the CY
flag is “1”.
SZD (Skip if Zero, port D specified by register Y)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(D(Y)) = 0
D9
D0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
2
2
4
2
2
16
16
2
2
0
1
B
Grouping: Input/Output operation
Description: Skips the next instruction when a bit of port D specified by
register Y is “0”. Executes the next instruction when the bit
is “1”.
Opera- (D(Y)) = 0 ?
tion: (Y) = 0 to 5
Note:
(Y) = 0 to 5.
Do not execute this instruction if values except above are
set to register Y.
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
1
0
0
0
0
2
3
0
16
2
1
1
Opera- (T17−T14) ← (B)
Grouping: Timer operation
tion:
(R17−R14) ← (B)
(T13−T10) ← (A)
(R13−R10) ← (A)
Description: Transfers the contents of register B to the high-order 4 bits
of timer 1 and timer 1 reload register R1. Transfers the
contents of register A to the low-order 4 bits of timer 1 and
timer 1 reload register R1.
T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
1
0
0
0
1
2
3
1
16
2
1
1
Opera- (T27−T24) ← (B)
tion: (R2L7−R2L4) ← (B)
Grouping: Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
(T27−T24) of timer 2 and the high-order 4 bits (R2L7−R2L4)
of timer 2 reload register R2L. Transfers the contents of
register A to the low-order 4 bits (T23−T20) of timer 2 and
the low-order 4 bits (R2L3−R2L0) of timer 2 reload register
R2.
(T23−T20) ← (A)
(R2L3−R2L0) ← (A)
Rev.1.01 Feb 15, 2008 Page 103 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
T2HAB (Transfer data to register R2H from Accumulator and register B)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
0
1
0
1
0
0
2
9
4
2
16
16
16
1
1
Opera- (R2H7−R2H4) ← (B)
tion: (R2H3−R2H0) ← (A)
Grouping: Timer operation
Description: Transfers the contents of register B to the high-order 4 bits
of timer 2 and timer 2 reload register R2H. Transfers the
contents of register A to the low-order 4 bits of timer 2 and
timer 2 reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
1
0
1
0
0
1
0
1
0
1
2
9
5
2
1
1
Opera- (T27−T20) ← (R2L7−R2L0)
tion:
Grouping: Timer operation
Description: Transfers the contents of reload register R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
1
1
1
1
0
0
1 E
2
1
1
Opera- (A) ← (B)
tion:
Grouping: Register to register transfer
Description: Transfers the contents of register B to register A.
TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
1
1
0
0
0
0
2
7
0
16
2
1
1
Opera- (B) ← (T17−T14)
tion: (A) ← (T13−T10)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T17−T14) of timer 1 to reg-
ister B.
Transfers the low-order 4 bits (T13−T10) of timer 1 to regis-
ter A.
Rev.1.01 Feb 15, 2008 Page 104 of 146
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455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
1
1
0
0
0
1
2
7
1
16
2
1
1
Opera- (B) ← (T27−T24)
tion: (A) ← (T23−T20)
Grouping: Timer operation
Description: Transfers the high-order 4 bits (T27−T24) of timer 2 to reg-
ister B.
Transfers the low-order 4 bits (T23−T20) of timer 2 to regis-
ter A.
TABE (Transfer data to Accumulator and register B from register E)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
1
0
1
0
1
0
0
2 A
16
2
1
1
Opera- (B) ← (E7−E4)
tion: (A) ← (E3−E0)
Grouping: Register to register transfer
Description: Transfers the high-order 4 bits (E7−E4) of register E to reg-
ister B, and low-order 4 bits of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
Skip condition
-
D9
D0
8
+p
0
0
1
0
p5 p4 p3 p2 p1 p0
0
p
2
16
1
3
-
Opera- (SP) ← (SP) + 1
Grouping: Arithmetic operation
tion:
(SK(SP)) ← (PC)
(PCH) ← p
Description: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to
0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by
registers A and D in page p. When UPTF is 1, Transfers bits 9, 8 to the low-
order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant
bit (DR2) of register D.
(PCL) ← (DR2−DR0, A3−A0)
(B) ← (ROM(PC))7−4
(A) ← (ROM(PC))3−0
(UPTF) ← 1
When this instruction is executed, 1 stage of stack register (SK) is used.
Note:
p is 0 to 63 for M3455AG8, and p is 0 to 95 for M3455AGC.
When this instruction is executed, be careful not to over the stack because 1
stage of stack register is used.
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
TABPS (Transfer data to Accumulator and register B from Pre-Scaler)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
1
1
0
1
0
1
2
7
5
16
2
1
1
Opera- (B) ← (TPS7−TPS4)
tion: (A) ← (TPS3−TPS0)
Grouping: Timer operation
Description: Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
Rev.1.01 Feb 15, 2008 Page 105 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAD (Transfer data to Accumulator from register D)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
1
0
0
0
1
0
5
1
16
2
1
1
Opera- (A2−A0) ← (DR2−DR0)
tion: (A3) ← 0
Grouping: Register to register transfer
Description: Transfers the contents of register D to the low-order 3 bits
(A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
TAI1 (Transfer data to Accumulator from register I1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
0
0
1
1
2
5
3
16
2
1
1
Opera- (A) ← (I1)
tion:
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control register I1 to reg-
ister A.
TAK0 (Transfer data to Accumulator from register K0)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
0
1
1
0
2
5
6
16
2
1
1
Opera- (A) ← (K0)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K0 to register A.
TAK1 (Transfer data to Accumulator from register K1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
1
0
0
1
2
5
9
16
2
1
1
Opera- (A) ← (K1)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K1 to register A.
Rev.1.01 Feb 15, 2008 Page 106 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAK2 (Transfer data to Accumulator from register K2)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
1
0
1
0
2
5 A
16
2
1
1
Opera- (A) ← (K2)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K2 to register A.
TAK3 (Transfer data to Accumulator from register K3)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
1
0
1
1
2
5 B
16
2
1
1
Opera- (A) ← (K3)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of key-on wakeup control register
K3 to register A.
TAL1 (Transfer data to Accumulator from register L1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
0
1
0
1
0
2
4 A
16
2
1
1
Opera- (A) ← (L1)
tion:
Grouping: LCD operation
Description: Transfers the contents of LCD control register L1 to regis-
ter A.
TAM j (Transfer data to Accumulator from Memory)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
1
0
0
j
j
j
j
2
C
j
16
2
1
1
Opera- (A) ← (M(DP))
Grouping: RAM to register transfer
tion:
(X) ← (X)EXOR(j)
Description: After transferring the contents of M(DP) to register A, an
exclusive OR operation is performed between register X
and the value j in the immediate field, and stores the result
in register X.
j = 0 to 15
Rev.1.01 Feb 15, 2008 Page 107 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAMR (Transfer data to Accumulator from register MR)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
0
0
1
0
2
5
2
16
2
1
1
Opera- (A) ← (MR)
tion:
Grouping: Clock operation
Description: Transfers the contents of clock control register MR to reg-
ister A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
0
1
1
1
2
5
7
16
2
1
1
Opera- (A) ← (PU0)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of pull-up control register PU0 to
register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
1
1
1
0
2
5 E
16
2
1
1
Opera- (A) ← (PU1)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of pull-up control register PU1 to
register A.
TAPU2 (Transfer data to Accumulator from register PU2)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
1
1
1
1
2
5
F
16
2
1
1
Opera- (A) ← (PU2)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of pull-up control register PU2 to
register A.
Rev.1.01 Feb 15, 2008 Page 108 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAPU3 (Transfer data to Accumulator from register PU3)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
1
1
1
0
1
2
5 D
16
2
1
1
Opera- (A) ← (PU3)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of pull-up control register PU3 to
register A.
TASP (Transfer data to Accumulator from Stack Pointer)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
1
0
0
0
0
0
5
0
16
2
1
1
Opera- (A2−A0) ← (SP2−SP0)
tion: (A3) ← 0
Grouping: Register to register transfer
Description: Transfers the contents of stack pointer (SP) to the low-
order 3 bits (A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
TAV1 (Transfer data to Accumulator from register V1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
1
0
1
0
0
0
5
4
16
2
1
1
Opera- (A) ← (V1)
tion:
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control register V1 to
register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
1
0
1
0
1
0
5
5
16
2
1
1
Opera- (A) ← (V2)
tion:
Grouping: Interrupt operation
Description: Transfers the contents of interrupt control register V2 to
register A.
Rev.1.01 Feb 15, 2008 Page 109 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW1 (Transfer data to Accumulator from register W1)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
0
1
0
1
1
2
4 B
16
2
1
1
Opera- (A) ← (W1)
tion:
Grouping: Timer operation
Description: Transfers the contents of timer control register W1 to regis-
ter A.
TAW2 (Transfer data to Accumulator from register W2)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
0
1
1
0
0
2
4 C
16
2
1
1
Opera- (A) ← (W2)
tion:
Grouping: Timer operation
Description: Transfers the contents of timer control register W2 to regis-
ter A.
TAW3 (Transfer data to Accumulator from register W3)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
0
1
1
0
1
2
4 D
16
2
1
1
Opera- (A) ← (W3)
tion:
Grouping: Timer operation
Description: Transfers the contents of timer control register W3 to regis-
ter A.
TAW4 (Transfer data to Accumulator from register W4)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
0
1
1
1
0
2
4 E
16
2
1
1
Opera- (A) ← (W4)
tion:
Grouping: Timer operation
Description: Transfers the contents of timer control register W4 to regis-
ter A.
TAW5 (Transfer data to Accumulator from register W5)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
1
0
0
1
1
1
1
2
4
F
16
2
1
1
Opera- (A) ← (W5)
tion:
Grouping: Timer operation
Description: Transfers the contents of timer control register W5 to regis-
ter A.
Rev.1.01 Feb 15, 2008 Page 110 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAX (Transfer data to Accumulator from register X)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
1
0
1
0
0
1
0
0
5
2
2
16
16
16
16
1
1
Opera- (A) ← (X)
tion:
Grouping: Register to register transfer
Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
1
1
1
1
1
0
1
F
2
1
1
Opera- (A) ← (Y)
tion:
Grouping: Register to register transfer
Description: Transfers the contents of register Y to register A.
TAZ (Transfer data to Accumulator from register Z)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
1
0
1
0
0
1
1
0
5
3
2
1
1
Opera- (A1, A0) ← (Z1, Z0)
tion: (A3, A2) ← 0
Grouping: Register to register transfer
Description: Transfers the contents of register Z to the low-order 2 bits
(A1, A0) of register A. “0” is stored to the high-order 2 bits
(A3, A2) of register A.
TBA (Transfer data to register B from Accumulator)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
0
1
1
1
0
0
0 E
2
1
1
Opera- (B) ← (A)
tion:
Grouping: Register to register transfer
Description: Transfers the contents of register A to register B.
Rev.1.01 Feb 15, 2008 Page 111 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TC1A (Transfer data to register C1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
1
0
1
0
0
0
2 A 8
2 16
1
1
Opera- (C1) ← (A)
tion:
Grouping: LCD control operation
Description: Transfers the contents of register A to the LCD control reg-
ister C1.
TC2A (Transfer data to register C2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
1
0
1
0
0
1
2 A 9
2 16
1
1
Opera- (C2) ← (A)
tion:
Grouping: LCD control operation
Description: Transfers the contents of register A to the LCD control reg-
ister C2.
TC3A (Transfer data to register C3 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
0
1
1
0
2
2
6
16
2
1
1
Opera- (C3) ← (A)
tion:
Grouping: LCD control operation
Description: Transfers the contents of register A to the LCD control reg-
ister C3.
TDA (Transfer data to register D from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
1
0
1
0
0
1
0
2
9
16
2
1
1
Opera- (DR2−DR0) ← (A2−A0)
tion:
Grouping: Register to register transfer
Description: Transfers the contents of the low-order 3 bits (A2−A0) of
register A to register D.
Rev.1.01 Feb 15, 2008 Page 112 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TEAB (Transfer data to register E from Accumulator and register B)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
0
1
1
0
1
0
0
1 A
16
2
1
1
Opera- (E7−E4) ← (B)
tion: (E3−E0) ← (A)
Grouping: Register to register transfer
Description: Transfers the contents of register B to the high-order 4 bits
(E3−E0) of register E, and the contents of register A to the
low-order 4 bits (E3−E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
0
0
0
2
2
8
16
2
1
1
Opera- (FR0) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
0
0
1
2
2
9
16
2
1
1
Opera- (FR1) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR1.
TFR2A (Transfer data to register FR2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
0
1
0
2
2 A
16
2
1
1
Opera- (FR2) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR2.
Rev.1.01 Feb 15, 2008 Page 113 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR3A (Transfer data to register FR3 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
0
1
1
2
2 B
16
2
1
1
Opera- (FR3) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to port output structure
control register FR3.
TI1A (Transfer data to register I1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
1
1
1
2
1
7
16
2
1
1
Opera- (I1) ← (A)
tion:
Grouping: Interrupt operation
Description: Transfers the contents of register A to interrupt control reg-
ister I1.
TK0A (Transfer data to register K0 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
1
0
1
1
2
1 B
16
2
1
1
Opera- (K0) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-on wakeup con-
trol register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
1
0
0
2
1
4
16
2
1
1
Opera- (K1) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-on wakeup con-
trol register K1.
Rev.1.01 Feb 15, 2008 Page 114 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
1
0
1
2
1
5
16
2
1
1
Opera- (K2) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-on wakeup con-
trol register K2.
TK3A (Transfer data to register K3 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
1
0
0
2
2 C
16
2
1
1
Opera- (K3) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to key-on wakeup con-
trol register K3.
TL1A (Transfer data to register L1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
0
1
0
2
0 A
16
2
1
1
Opera- (L1) ← (A)
tion:
Grouping: LCD control operation
Description: Transfers the contents of register A to the LCD control reg-
ister L1.
TL2A (Transfer data to register L2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
0
1
1
2
0 B
16
2
1
1
Opera- (L2) ← (A)
tion:
Grouping: LCD control operation
Description: Transfers the contents of register A to the LCD control reg-
ister L2.
Rev.1.01 Feb 15, 2008 Page 115 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TL3A (Transfer data to register L3 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
1
0
0
2
0 C
16
2
1
1
Opera- (L3) ← (A)
tion:
Grouping: LCD control operation
Description: Transfers the contents of register A to the LCD control reg-
ister L3.
TLCA (Transfer data to timer LC and register RLC from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
1
0
1
2
0 D
16
2
1
1
Opera- (LC) ← (A)
tion: (RLC) ← (A)
Grouping: Timer control operation
Description: Transfers the contents of register A to timer LC and reload
register RLC.
TMA j (Transfer data to Memory from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
1
1
j
j
j
j
2
B
j
16
2
1
1
Opera- (M(DP)) ← (A)
Grouping: RAM to register transfer
tion:
(X) ← (X)EXOR(j)
Description: After transferring the contents of register A to M(DP), an
exclusive OR operation is performed between register X
and the value j in the immediate field, and stores the result
in register X.
j = 0 to 15
TMRA (Transfer data to register MR from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
1
1
0
2
1
6
16
2
1
1
Opera- (MR) ← (A)
tion:
Grouping: Clock operation
Description: Transfers the contents of register A to clock control register
MR.
Rev.1.01 Feb 15, 2008 Page 116 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPAA (Transfer data to register PA from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
0
1
0
1
0
1
0
2 A A
2 16
1
1
Opera- (PA0) ← (A0)
tion:
Grouping: Timer operation
Description: Transfers the least significant bit of register A (A0) to timer
control register PA.
TPSAB (Transfer data to Pre-Scaler and register RPS from Accumulator and register B)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
1
0
1
0
1
2
3
5
16
2
1
1
Opera- (RPS7−RPS4) ← (B)
Grouping: Timer operation
tion:
(TPS7−TPS4) ← (B)
(RPS3−RPS0) ← (A)
(TPS3−TPS0) ← (A)
Description: Transfers the contents of register B to the high-order 4 bits
of prescaler and prescaler reload register RPS. Transfers
the contents of register A to the low-order 4 bits of
prescaler and prescaler reload register RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
1
0
1
2
2 D
16
2
1
1
Opera- (PU0) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to pull-up control regis-
ter PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
1
1
0
2
2 E
16
2
1
1
Opera- (PU1) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to pull-up control regis-
ter PU1.
Rev.1.01 Feb 15, 2008 Page 117 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPU2A (Transfer data to register PU2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
0
1
1
1
1
2
2
F
16
2
1
1
Opera- (PU2) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to pull-up control regis-
ter PU2.
TPU3A (Transfer data to register PU3 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
0
0
0
2
0
8
16
2
1
1
Opera- (PU3) ← (A)
tion:
Grouping: Input/Output operation
Description: Transfers the contents of register A to pull-up control regis-
ter PU3.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
1
1
1
1
1
1
2
3
F
16
2
1
1
Opera- (R17−R14) ← (B)
tion: (R13−R10) ← (A)
Grouping: Timer control operation
Description: Transfers the contents of register B to the high-order 4 bits
(R17−R14) of timer 1 reload register R1, and the contents
of register A to the low-order 4 bits (R13−R10) of timer 1
reload register R1.
TRGA (Transfer data to register RG from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
0
0
1
2
0
9
16
2
1
1
Opera- (RG2−RG0) ← (A2−A0)
tion:
Grouping: Clock control operation
Description: Transfers the contents of register A to register RG.
Rev.1.01 Feb 15, 2008 Page 118 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TV1A (Transfer data to register V1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
1
1
1
1
1
1
0
3
F
16
2
1
1
Opera- (V1) ← (A)
tion:
Grouping: Interrupt operation
Description: Transfers the contents of register A to interrupt control reg-
ister V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
0
0
0
0
1
1
1
1
1
0
0
3 E
16
2
1
1
Opera- (V2) ← (A)
tion:
Grouping: Interrupt operation
Description: Transfers the contents of register A to interrupt control reg-
ister V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
1
1
0
2
0 E
16
2
1
1
Opera- (W1) ← (A)
tion:
Grouping: Timer operation
Description: Transfers the contents of register A to timer control register
W1.
TW2A (Transfer data to register W2 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
0
1
1
1
1
2
0
F
16
2
1
1
Opera- (W2) ← (A)
tion:
Grouping: Timer operation
Description: Transfers the contents of register A to timer control register
W2.
Rev.1.01 Feb 15, 2008 Page 119 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW3A (Transfer data to register W3 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
0
0
0
2
1
0
16
2
1
1
Opera- (W3) ← (A)
tion:
Grouping: Timer operation
Description: Transfers the contents of register A to timer control register
W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
0
0
1
2
1
1
16
2
1
1
Opera- (W4) ← (A)
tion:
Grouping: Timer operation
Description: Transfers the contents of register A to timer control register
W4.
TW5A (Transfer data to register W5 from Accumulator)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
0
0
0
1
0
0
1
0
2
1
2
2
16
16
16
1
1
Opera- (W5) ← (A)
tion:
Grouping: Timer operation
Description: Transfers the contents of register A to timer control register
W5.
TYA (Transfer data to register Y from Accumulator)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
tion
D9
D0
code
0
0
0
0
0
0
1
1
0
0
0
0
C
2
1
1
Opera- (Y) ← (A)
tion:
Grouping: Register to register transfer
Description: Transfers the contents of register A to register Y.
WRST (Watchdog timer ReSeT)
Instruc-
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(WDF1) = 1
tion
D9
D0
code
1
0
1
0
1
0
0
0
0
0
2
A
0
2
1
1
Opera- (WDF1) = 1 ?
tion: (WDF1) ← 0
Grouping: Other operation
Description: Clears (0) to the WDF1 flag and skips the next instruction
when watchdog timer flag WDF1 is “1”. When the WDF1
flag is “0”, executes the next instruction. Also, stops the
watchdog timer function when executing the WRST
instruction immediately after the DWDT instruction.
Rev.1.01 Feb 15, 2008 Page 120 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
XAM j (eXchange Accumulator and Memory data)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
-
D9
D0
1
0
1
1
0
1
j
j
j
j
2
D
j
16
2
1
1
Opera- (A) ← → (M(DP))
Grouping: RAM to register transfer
tion:
(X) ← (X)EXOR(j)
Description: After exchanging the contents of M(DP) with the contents
of register A, an exclusive OR operation is performed
between register X and the value j in the immediate field,
and stores the result in register X.
j = 0 to 15
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(Y) = 15
D9
D0
1
0
1
1
1
1
j
j
j
j
2
F
j
16
2
1
1
Opera- (A) ← → (M(DP))
Grouping: RAM to register transfer
tion:
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After exchanging the contents of M(DP) with the contents
of register A, an exclusive OR operation is performed
between register X and the value j in the immediate field,
and stores the result in register X.
(Y) ← (Y) −1
Subtracts 1 from the contents of register Y.
As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped. When the contents of
register Y is not 15, the next instruction is executed.
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruc-
tion
code
Number of
words
Number of
cycles
Flag CY
-
Skip condition
(Y) = 0
D9
D0
1
0
1
1
1
0
j
j
j
j
2
E
j
16
2
1
1
Opera- (A) ← → (M(DP))
Grouping: RAM to register transfer
tion:
(X) ← (X)EXOR(j)
j = 0 to 15
Description: After exchanging the contents of M(DP) with the contents
of register A, an exclusive OR operation is performed
between register X and the value j in the immediate field,
and stores the result in register X.
(Y) ← (Y) + 1
Adds 1 to the contents of register Y. As a result of addition,
when the contents of register Y is 0, the next instruction is
skipped. When the contents of register Y is not 0, the next
instruction is executed.
Rev.1.01 Feb 15, 2008 Page 121 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES)
Instruction code
Para
meter
Mnemonic
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TAB
TBA
TAY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1
E
E
F
C
A
1
1
1
1
1
1
1
1
1
1
(A) ← (B)
(B) ← (A)
(A) ← (Y)
(Y) ← (A)
TYA
TEAB
(E7−E4) ← (B)
(E3−E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7−E4)
(A) ← (E3−E0)
TDA
TAD
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
2
5
9
1
1
1
1
1
(DR2−DR0) ← (A2−A0)
(A2−A0) ← (DR2−DR0)
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
5
5
2
0
1
1
1
1
(A) ← (X)
TASP
(A2−A0) ← (SP2−SP0)
(A3) ← 0
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
(X) ← x x = 0 to 15
(Y) ← y y = 0 to 15
LZ z
INY
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
1
0
1
0
0
j
0
0
1
j
z1 z0
0
0
0
2
4
1
8
+z
1
1
1
1
1
1
1
1
(Z) ← z z = 0 to 3
(Y) ← (Y) + 1
1
1
j
1
1
j
3
7
j
DEY
TAM j
1
(Y) ← (Y) − 1
C
(A) ← (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAM j
1
1
0
0
1
1
1
1
0
1
1
1
j
j
j
j
j
j
j
j
2
2
D
F
j
j
1
1
1
1
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
XAMD j
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) − 1
XAMI j
TMA j
1
1
0
0
1
1
1
0
1
1
0
1
j
j
j
j
j
j
j
j
2
2
E
B
j
j
1
1
1
1
(A) ←→ (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
j = 0 to 15
Rev.1.01 Feb 15, 2008 Page 122 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
−
−
−
−
−
−
−
−
−
−
Transfers the contents of register B to register A.
Transfers the contents of register A to register B.
Transfers the contents of register Y to register A.
Transfers the contents of register A to register Y.
Transfers the contents of register B to the high-order 4 bits (E3−E0) of register E, and the contents of register
A to the low-order 4 bits (E3−E0) of register E.
−
−
Transfers the high-order 4 bits (E7−E4) of register E to register B, and low-order 4 bits of register E to register
A.
−
−
−
−
Transfers the contents of the low-order 3 bits (A2−A0) of register A to register D.
Transfers the contents of register D to the low-order 3 bits (A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
−
−
Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A.
“0” is stored to the high-order 2 bits (A3, A2) of register A.
−
−
−
−
Transfers the contents of register X to register A.
Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2−A0) of register A.
“0” is stored to the bit 3 (A3) of register A.
Continuous
description
−
Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
and other LXY instructions coded continuously are skipped.
−
−
−
−
−
Loads the value z in the immediate field to register Z.
(Y) = 0
(Y) = 15
−
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next
instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
−
−
−
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
(Y) = 15
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15,
the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
(Y) = 0
−
−
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
performed between register X and the value j in the immediate field, and stores the result in register X.
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next
instruction is skipped. when the contents of register Y is not 0, the next instruction is executed.
−
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
Rev.1.01 Feb 15, 2008 Page 123 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
LA n
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
1
1
0
1
1
n
n
n
n
0
7
n
1
1
1
3
(A) ← n
n = 0 to 15
TABP p
p5 p4 p3 p2 p1 p0
0
8
p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note 1)
+p
(PCL) ← (DR2−DR0, A3−A0)
(B) ← (ROM(PC))7-4
(A) ← (ROM(PC))3-0
(UPTF) = 1
(DR1, DR0) ← (ROM(PC))9, 8
(DR2) ← 0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
AM
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
n
0
0
n
1
1
n
0
1
n
0
0
0
0
0
6
A
B
n
1
1
1
1
1
1
(A) ← (A) + (M(DP))
AMC
A n
(A) ← (A) + (M(DP)) + (CY)
(CY) ← Carry
(A) ← (A) + n
n = 0 to 15
AND
OR
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
0
0
1
1
8
9
1
1
1
1
(A) ← (A) AND (M(DP))
(A) ← (A) OR (M(DP))
SC
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
2
7
6
F
1
1
1
1
1
1
(CY) ← 1
(CY) ← 0
(CY) = 0 ?
RC
SZC
CMA
RAR
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
0
0
1
1
C
D
1
1
1
1
(A) ← (A)
CY
A3A2A1A0
SB j
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
1
0
1
1
0
j
j
j
j
j
j
0
0
0
5
4
2
C
+j
1
1
1
1
1
1
(Mj(DP)) ← 1
j = 0 to 3
RB j
SZB j
C
+j
(Mj(DP)) ← 0
j = 0 to 3
j
(Mj(DP)) = 0 ?
j = 0 to 3
Note 1. M3455AG8: p=0 to 63 and M3455AGC: p=0 to 95.
Rev.1.01 Feb 15, 2008 Page 124 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
Continuous
description
−
−
Loads the value n in the immediate field to register A.
When the LA instructions are continuously coded and executed, only the first LA instruction is executed and
other LA instructions coded continuously are skipped.
−
Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in
address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When UPTF is 1, Transfers
bits 9, 8 to the low-order 2 bits (DR1, DR0) of register D, and “0” is stored to the least significant bit (DR2) of
register D.
When this instruction is executed, 1 stage of stack register (SK) is used.
−
−
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
−
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
Overflow = 0
−
Adds the value n in the immediate field to register A, and stores a result in register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
Executes the next instruction when there is overflow as the result of operation.
−
−
−
−
Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result
in register A.
−
−
1
0
−
Sets (1) to carry flag CY.
Clears (0) to carry flag CY.
(CY) = 0
Skips the next instruction when the contents of carry flag CY is “0”. Executes the next instruction when the
contents of carry flag CY is “1”.
The contents of carry flag CY remains unchanged.
−
−
−
Stores the one’s complement for register A’s contents in register A.
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
−
−
−
−
−
Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
(Mj(DP)) = 0
j = 0 to 3
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of
M(DP) is “0”.
Executes the next instruction when the contents of bit j of M(DP) is “1”.
Rev.1.01 Feb 15, 2008 Page 125 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SEAM
SEA n
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
2
2
6
5
1
2
1
2
(A) = (M(DP)) ?
(A) = n ?
n = 0 to 15
0
0
0
1
0
1
1
1
1
n
n
n
n
0
1
7
n
a
B a
a6 a5 a4 a3 a2 a1 a0
8
+a
1
2
1
2
(PCL) ← a6−a0
BL p, a
0
0
1
1
1
p4 p3 p2 p1 p0
0
E
+p
p
(PCH) ←p (Note 1)
(PCL) ← a6−a0
1
0
p6 p5 a6 a5 a4 a3 a2 a1 a0
2
0
a
1
a
0
BLA p
BM a
0
0
0
0
0
1
0
0
0
0
0
2
1
2
1
(PCH) ← p (Note 1)
(PCL) ← (DR2−DR0, A3−A0)
1
0
p6 p5 p4
p3 p2 p1 p0
2
1
p
a
p
a
1
0
0
1
a6 a5 a4 a3 a2 a1 a0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← 2
(PCL) ← a6−a0
BML p, a
BMLA p
RTI
0
1
0
p4 p3 p2 p1 p0
0
C
+p
p
2
2
1
2
2
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note 1)
(PCL) ← a6−a0
1
0
p6 p5 a6 a5 a4 a3 a2 a1 a0
2
0
a
3
a
0
0
0
0
1
0
0
1
0
0
0
0
0
0
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p (Note 1)
(PCL) ← (DR2−DR0, A3−A0)
1
0
p6 p5 p4
p3 p2 p1 p0
2
0
p
4
p
6
0
0
1
0
1
1
0
(PC) ← (SK(SP))
(SP) ← (SP) − 1
RT
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
4
4
4
5
1
1
2
2
(PC) ← (SK(SP))
(SP) ← (SP) − 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) − 1
Note 1. M3455AG8: p=0 to 63 and p6=0, and M3455AGC: p=0 to 95.
Rev.1.01 Feb 15, 2008 Page 126 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
(A) = (M(DP))
−
−
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
(A) = n
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
n = 0 to 15
Executes the next instruction when the contents of register A is not equal to the value n in the immediate
field.
−
−
−
−
Branch within a page : Branches to address a in the identical page.
Branch out of a page : Branches to address a in page p.
−
−
−
−
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in
page p.
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
Call the subroutine : Calls the subroutine at address a in page p.
−
−
−
−
−
−
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D
and A in page p.
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous
description of the LA/LXY instruction, register A and register B to the states just before interrupt.
−
−
−
Returns from subroutine to the routine called the subroutine.
Skip at uncondition
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.1.01 Feb 15, 2008 Page 127 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
0
0
0
0
1
0
0
0
0
0
0
3
4
5
8
1
1
1
1
1
1
(INTE) ← 0
(INTE) ← 1
EI
SNZ0
V10 = 0 : (EXF0) = 1 ?
(EXF0) ← 0
V10 = 1 : SNZ0 = NOP
SNZI0
0
0
0
0
1
1
1
0
1
0
0
3
A
1
1
I12 = 0 : (INT) = “L”?
I12 = 1 : (INT) = “H”?
TAV1
TV1A
TAV2
TV2A
TAI1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
1
1
0
1
0
1
0
0
1
0
1
1
1
1
1
1
0
1
0
0
1
0
1
1
0
1
1
0
1
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
2
2
2
2
2
2
2
2
2
2
2
2
2
5
3
5
3
5
1
A
4
0
4
0
4
1
4
1
4
1
4
F
5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (V1)
(V1) ← (A)
(A) ← (V2)
(V2) ← (A)
(A) ← (I1)
E
3
TI1A
7
(I1) ← (A)
TPAA
TAW1
TW1A
TAW2
TW2A
TAW3
TW3A
TAW4
TW4A
TAW5
TW5A
A
B
E
C
F
D
0
(PA) ← (A)
(A) ← (W1)
(W1) ← (A)
(A) ← (W2)
(W2) ← (A)
(A) ← (W3)
(W3) ← (A)
(A) ← (W4)
(W4) ← (A)
(A) ← (W5)
(W5) ← (A)
E
1
F
2
Rev.1.01 Feb 15, 2008 Page 128 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
−
−
−
−
Clears (0) to interrupt enable flag INTE, and disables the interrupt.
Sets (1) to interrupt enable flag INTE, and enables the interrupt.
−
V10
= 0 : (EXF0) = 1
When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request
flag EXF0 is “1”. When the EXF0 flag is “0”, executes the next instruction.
When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register
V1)
(INT) =
However, I1
“
L
2
”
= 0
−
When I12 = 0 : Skips the next instruction when the level of INT pin is “L”. Executes the next instruction when
the level of INT0 pin is “H”.
(INT) =
However, I12 = 1
“
H
”
When I12 = 1 : Skips the next instruction when the level of INT pin is “H”. Executes the next instruction when
the level of INT0 pin is “L”. (I12: bit 2 of interrupt control register I1)
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Transfers the contents of interrupt control register V1 to register A.
Transfers the contents of register A to interrupt control register V1.
Transfers the contents of interrupt control register V2 to register A.
Transfers the contents of register A to interrupt control register V2.
Transfers the contents of interrupt control register I1 to register A.
Transfers the contents of register A to interrupt control register I1.
Transfers the contents of register A (A0) to timer control register PA.
Transfers the contents of timer control register W1 to register A.
Transfers the contents of register A to timer control register W1.
Transfers the contents of timer control register W2 to register A.
Transfers the contents of register A to timer control register W2.
Transfers the contents of timer control register W3 to register A.
Transfers the contents of register A to timer control register W3.
Transfers the contents of timer control register W4 to register A.
Transfers the contents of register A to timer control register W4.
Transfers the contents of timer control register W5 to register A.
Transfers the contents of register A to timer control register W5.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Rev.1.01 Feb 15, 2008 Page 129 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
TABPS
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
2
2
7
3
5
5
1
1
1
1
(B) ← (TPS7−TPS4)
(A) ← (TPS3−TPS0)
TPSAB
(RPS7−RPS4) ← (B)
(TPS7−TPS4) ← (B)
(RPS3−RPS0) ← (A)
(TPS3−TPS0) ← (A)
TAB1
T1AB
1
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
2
2
7
3
0
0
1
1
1
1
(B) ← (T17−T14)
(A) ← (T13−T10)
(R17−R14) ← (B)
(T17−T14) ← (B)
(R13−R10) ← (A)
(T13−T10) ← (A)
TR1AB
TAB2
1
1
1
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
0
0
1
0
0
1
0
0
1
1
1
2
2
2
3
7
3
F
1
1
1
1
1
1
1
1
(R17−R14) ← (B)
(R13−R10) ← (A)
(B) ← (T27−T24)
(A) ← (T23−T20)
T2AB
(R2L7−R2L4) ← (B)
(T27−T24) ← (B)
(R2L3−R2L0) ← (A)
(T23−T20) ← (A)
T2HAB
1
0
1
0
0
1
0
1
0
0
2
9
4
1
1
(R2H7−R2H4) ← (B)
(R2H3−R2H0) ← (A)
T2R2L
TLCA
1
1
0
0
1
0
0
0
0
0
1
0
0
1
1
1
0
0
1
1
2
2
9
0
5
1
1
1
1
(T27) ← (R2L)
D
(RLC) ← (A)
(TLC) ← (A)
SNZT1
SNZT2
SNZT3
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
2
2
2
8
8
8
0
1
2
1
1
1
1
1
1
V12 = 0 : (T1F) = 1 ?
After skipping, (T1F) ← 0
V12 = 1 : SNZT1=NOP
V13 = 0 : (T2F) = 1 ?
After skipping, (T2F) ← 0
V13 = 1 : SNZT2=NOP
V20 = 0 : (T3F) = 1 ?
After skipping, (T3F) ← 0
V20 = 1 : SNZT3=NOP
Rev.1.01 Feb 15, 2008 Page 130 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
−
−
−
−
Transfers the high-order 4 bits of prescaler to register B.
Transfers the low-order 4 bits of prescaler to register A.
Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS.
Transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
−
−
−
−
Transfers the high-order 4 bits (T17−T14) of timer 1 to register B.
Transfers the low-order 4 bits (T13−T10) of timer 1 to register A.
Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1L.
Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1L.
−
−
−
−
−
−
Transfers the contents of register B to the high-order 4 bits (R17−R14) of reload register R1, and the contents
of register A to the low-order 4 bits (R13−R10) of reload register R1.
Transfers the high-order 4 bits (T27−T24) of timer 2 to register B.
Transfers the low-order 4 bits (T23−T20) of timer 2 to register A.
Transfers the contents of register B to the high-order 4 bits (R2L7−R2L4) of timer 2 and timer 2 reload register
R2L. Transfers the contents of register A to the low-order 4 bits (R2L3−R2L0) of timer 2 and timer 2 reload
register R2L.
−
−
Transfers the contents of register B to the high-order 4 bits (R2H7−R2H4) of timer 2 and timer 2 reload
register R2H. Transfers the contents of register A to the low-order 4 bits (R2H3−R2H0) of timer 2 and timer 2
reload register R2H.
−
−
−
−
Transfers the contents of timer 2 reload register R2L to timer 2.
Transfers the contents of register A to timer LC and reload register RLC.
V12 = 0 : (T1F) = 1
V13 = 0 : (T2F) = 1
V20 = 0 : (T3F) = 1
−
−
−
When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag
T1F is “1”. When the T1F flag is “0”, executes the next instruction.
When V12 = 1 : This instruction is equivalent to the NOP instruction.
(V12: bit 2 of interrupt control register V1)
When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag
T2F is “1”. When the T2F flag is “0”, executes the next instruction.
When V13 = 1 : This instruction is equivalent to the NOP instruction.
(V13: bit 3 of interrupt control register V1)
When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag
T3F is “1”. When the T3F flag is “0”, executes the next instruction.
When V20 = 1 : This instruction is equivalent to the NOP instruction.
(V20: bit 0 of interrupt control register V2)
Rev.1.01 Feb 15, 2008 Page 131 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
IAP0
OP0A
IAP1
OP1A
IAP2
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
2
2
2
2
2
6
2
6
2
6
0
0
1
1
2
1
1
1
1
1
1
1
1
1
1
(A) ← (P0)
(P0) ← (A)
(A) ← (P1)
(P1) ← (A)
(A) ← (P2)
OP2A
IAP3
OP3A
CLD
RD
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
2
2
2
0
0
2
6
2
1
1
2
3
3
1
4
1
1
1
1
1
1
1
1
1
1
(P2) ← (A)
(A) ← (P3)
(P3) ← (A)
(D) ← 1
(D(Y)) ← 0
(Y) = 0 to 7
SD
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
1
2
5
4
1
2
1
2
(D(Y)) ← 1
(Y) = 0 to 7
SZD
(D(Y)) = 0 ?
(Y) = 0 to 5
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
1
0
1
0
0
2
2
8
B
C
RCP
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(C) ← 0
SCP
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
0
1
0
1
1
1
0
0
1
1
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
8
2
2
2
2
5
2
5
2
5
2
5
0
D
8
(C) ← 1
TFR0A
TFR1A
TFR2A
TFR3A
TAPU0
TPU0A
TAPU1
TPU1A
TAPU2
TPU2A
TAPU3
TPU3A
(FR0) ← (A)
(FR1) ← (A)
(FR2) ← (A)
(FR3) ← (A)
(A) ← (PU0)
(PU0) ← (A)
(A) ← (PU1)
(PU1) ← (A)
(A) ← (PU2)
(PU2) ← (A)
(A) ← (PU3)
(PU3) ← (A)
9
A
B
7
D
E
E
F
F
D
8
Rev.1.01 Feb 15, 2008 Page 132 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
−
−
−
−
−
−
−
−
−
−
Transfers the input of port P0 to register A.
Outputs the contents of register A to port P0.
Transfers the input of port P1 to register A.
Outputs the contents of register A to port P1.
Transfers the input of port P2 to the register A.
−
−
−
−
−
−
−
−
−
−
Outputs the contents of the register A to port P2.
Transfers the input of port P3 to the register A.
Outputs the contents of the register A to port P3.
Sets (1) to port D.
Clears (0) to a bit of port D specified by register Y.
−
−
−
Sets (1) to a bit of port D specified by register Y.
(D(Y)) = 0
Y = 0 to 4
Skips the next instruction when a bit of port D specified by register Y is “0”. Executes the next instruction
when a bit of port D specified by register Y is “1”.
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Clears (0) to port C.
Sets (1) to port C.
Transfers the contents of register A to port output structure control register FR0.
Transfers the contents of register A to port output structure control register FR1.
Transfers the contents of register A to port output structure control register FR2.
Transfers the contents of register A to port output structure control register FR3.
Transfers the contents of pull-up control register PU0 to register A.
Transfers the contents of register A to pull-up control register PU0.
Transfers the contents of pull-up control register PU1 to register A.
Transfers the contents of register A to pull-up control register PU1.
Transfers the contents of pull-up control register PU2 to register A.
Transfers the contents of register A to pull-up control register PU2.
Transfers the contents of pull-up control register PU3 to register A.
Transfers the contents of register A to pull-up control register PU3.
Rev.1.01 Feb 15, 2008 Page 133 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TAK0
TK0A
TAK1
TK1A
TAK2
TK2A
TAK3
TK3A
TAL1
TL1A
TL2A
TL3A
TC1A
TC2A
TC3A
TAMR
TMRA
TRGA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
1
1
0
0
1
0
1
0
1
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
0
1
0
0
0
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
5
1
5
1
5
1
5
2
4
0
0
0
A
A
2
5
1
0
6
B
9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(A) ← (K0)
(K0) ← (A)
(A) ← (K1)
(K1) ← (A)
(A) ← (K2)
(K2) ← (A)
(A) ← (K3)
(K3) ← (A)
(A) ← (L1)
(L1) ← (A)
(L2) ← (A)
(L3) ← (A)
(C1) ← (A)
(C2) ← (A)
(C3) ← (A)
(A) ← (MR)
(MR) ← (A)
4
A
5
B
C
A
A
B
C
8
9
6
2
6
9
(RG2−RG0) ← (A2−A0)
Rev.1.01 Feb 15, 2008 Page 134 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Transfers the contents of key-on wakeup control register K0 to register A.
Transfers the contents of register A to key-on wakeup control register K0.
Transfers the contents of key-on wakeup control register K1 to register A.
Transfers the contents of register A to key-on wakeup control register K1.
Transfers the contents of key-on wakeup control register K2 to register A.
Transfers the contents of register A to key-on wakeup control register K2.
Transfers the contents of key-on wakeup control register K3 to register A.
Transfers the contents of register A to key-on wakeup control register K3.
Transfers the contents of the LCD control register L1 to register A.
Transfers the contents of register A to the LCD control register L1.
Transfers the contents of register A to the LCD control register L2.
Transfers the contents of register A to the LCD control register L3.
Transfers the contents of register A to the LCD control register C1.
Transfers the contents of register A to the LCD control register C2.
Transfers the contents of register A to the LCD control register C3.
Transfers the contents of clock control regiser MR to register A.
Transfers the contents of register A to clock control register MR.
Transfers the contents of register A to clock control register RG.
Rev.1.01 Feb 15, 2008 Page 135 of 146
REJ03B0224-0101
455A Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Instruction code
Para
meter
Mnemonic
Function
Hexadecim
al notation
Type of
instructi
ons
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOP
POF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
2
1
1
1
1
(PC) ← (PC) + 1
Transition to clock operating mode
Transition to RAM back-up mode
POF2
0
0
0
0
0
0
1
0
0
0
0
0
8
1
1
EPOF
SNZP
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
1
1
1
0
0
5
0
B
3
1
1
1
1
POF or POF2 instruction valid
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2
A
0
1
1
(WDF1) = 1 ?
(WDF1) ← 0
DWDT
SRST
RUPT
SUPT
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
1
0
1
2
0
0
0
9
0
5
5
C
1
8
9
1
1
1
1
1
1
1
1
Stop of watchdog timer function enabled
System reset
(UPTF) ← 0
(UPTF) ← 1
SVDE
1
0
1
0
0
1
0
0
1
1
2
9
3
1
1
At power down mode, voltage drop detection
circuit valid
SNZVD
1
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
2
0
8
4
A
0
1
1
1
1
(VDF) = 1?
RBK
(Note 1)
When TABPp instruction is executed, p6←0
When TABPp instruction is executed, p6←1
SBK
0
0
0
1
0
0
0
0
0
1
0
4
1
1
1
(Note 1)
Note 1. (SBK, RBK) cannot be used int the M3455AG8. The pages which can be referred by the TABP instruction after the SBK
instruction is executed are 64 to 95 in the M3455AGC.
Rev.1.01 Feb 15, 2008 Page 136 of 146
REJ03B0224-0101
455A Group
Skip condition
Detailed description
−
−
−
−
No operation; Adds 1 to program counter value, and others remain unchanged.
Puts the system in clock operating mode by executing the POF instruction after executing the EPOF
instruction.
−
−
Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF
instruction.
−
−
−
Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction.
(P) = 1
Skips the next instruction when the P flag is “1”.
After skipping, the P flag remains unchanged.
Executes the next instruction when the P flag is “0”.
(WDF1) = 1
Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is “1”. When the
WDF1 flag is “0”, executes the next instruction. Also, stops the watchdog timer function when executing the
WRST instruction immediately after the DWDT instruction.
−
−
−
−
−
−
−
−
Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
System reset occurs.
Clears (0) to the high-order bit reference enable flag UPTF.
Sets (1) to the high-order bit reference enable flag UPTF.
(VDF) = 1
−
Skips the next instruction when voltage drop detection circuit flag VDF is “1”. Execute instruction when VPF
is “0”.
After skipping, the contents of VDF remains unchanged.
−
−
Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode).
Sets referring data area to pages 0 to 63 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
－
－
－
－
Sets referring data area to pages 64 to 127 when the TABP p instruction is executed.
This instruction is valid only for the TABP p instruction.
Rev.1.01 Feb 15, 2008 Page 137 of 146
REJ03B0224-0101
455A Group
INSTRUCTION CODE TABLE
010000
to
010111
011000
to
011111
D9−
D4
000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111
D3−
D0
Hex,
notation
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F 10−17 18−F
SZB
0
A
0
LA TABP TABP TABP TABP
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP BLA
SRST CLD
BMLA RBK** TASP
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BML BML BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BL
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
BM
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
0
0
16
LA TABP TABP TABP TABP
17 33* 49*
LA TABP TABP TABP TABP
18 34* 50*
LA TABP TABP TABP TABP
19 35* 51*
LA TABP TABP TABP TABP
20 36* 52*
LA TABP TABP TABP TABP
21 37* 53*
LA TABP TABP TABP TABP
22 38* 54*
LA TABP TABP TABP TABP
23 39* 55*
LA TABP TABP TABP TABP
24 40* 56*
LA TABP TABP TABP TABP
25 41* 57*
LA TABP TABP TABP TABP
10 10 26 42* 58*
LA TABP TABP TABP TABP
11 11 27 43* 59*
LA TABP TABP TABP TABP
12 12 28 44* 60*
LA TABP TABP TABP TABP
13 13 29 45* 61*
LA TABP TABP TABP TABP
14 14 30 46* 62*
LA TABP TABP TABP TABP
15 15 31 47* 63*
32*
48*
SZB
1
A
1
−
SBK** TAD
1
1
SZB
2
A
2
POF
−
−
−
−
TAX
TAZ
2
2
SZB
3
A
3
SNZP INY
−
3
3
A
4
DI
EI
RD SZD
SD SEAn
−
RT TAV1
RTS TAV2
4
4
A
5
−
5
5
A
6
SEAM
RC
−
−
−
RTI
−
6
6
A
7
SC DEY
−
−
−
−
7
7
LZ
0
A
8
POF2 AND
SNZ0
−
RUPT
SUPT
−
8
8
LZ
1
A
9
−
OR TDA
9
9
SNZI LZ
A
10
AM TEAB TABE
0
2
LZ
3
A
11
AMC
TYA CMA
RAR
TBA TAB
−
−
−
−
−
−
EPOF
RB
0
SB
0
A
12
−
−
RB
1
SB
1
A
13
−
RB
2
SB
2
A
14
TV2A
RB
3
SB
3
A
15
−
TAY SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each
instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are
described below.
The second word
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
• **(SBK and RBK instructions) cannot be used in the M3455AG8.
• * cannot be used after the SBK instruction executed in the M3455AGC.
• A page referred by the TABP instruction can be switched by the SBK and RBK instructions in
the M3455AGC.
• The pages which can be referred by the TABP instruction after the SBK instruction is executed
are 64 to 95 in the M3455AGC.
BL
BML
BLA
BMLA
SEA
SZD
• The pages which can be referred by the TABP instruction after the RBK instruction is executed
are 0 to 63.
• When the SBK instruction is not used, the pages which can be referred by the TABP instruction
are 0 to 63.
Rev.1.01 Feb 15, 2008 Page 138 of 146
REJ03B0224-0101
455A Group
INSTRUCTION CODE TABLE
110000
to
111111
D9−
D4
100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111
D3− Hex,
20
21
22
23
24
−
−
−
−
−
−
−
−
−
−
25
−
26
27
28
29
2A
2B
2C
2D
2E
2F 30−3F
D0
notation
SNZT
1
TMA TAM XAM XAMI XAMD
0
0000
0
−
TW3A OP0A T1AB
TW4A OP1A T2AB
IAP0 TAB1
IAP1 TAB2
−
WRST
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
LXY
0
0
0
0
SNZT
2
TMA TAM XAM XAMI XAMD
1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
−
−
−
−
−
1
1
1
1
SNZT
3
TMA TAM XAM XAMI XAMD
2
−
TW5A OP2A
−
TAMR IAP2
TAI1 IAP3
−
−
2
2
2
2
TMA TAM XAM XAMI XAMD
3
−
−
OP3A
−
−
−
−
−
−
−
−
−
SVDE
−
3
3
3
3
T2HA
B
TMA TAM XAM XAMI XAMD
4
−
−
TK1A
TK2A
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
4
4
4
4
T2R2
L
TMA TAM XAM XAMI XAMD
5
TPSAB
TABPS
−
5
5
5
5
TMA TAM XAM XAMI XAMD
6
−
TMRA TC3A
−
−
−
−
−
−
−
−
−
TAK0
TAPU0
−
−
−
−
−
−
−
−
−
−
−
−
−
6
6
6
6
TMA TAM XAM XAMI XAMD
7
−
TI1A
−
−
−
7
7
7
7
TMA TAM XAM XAMI XAMD
8
TPU3A
TRGA
TL1A
TFR0A
TFR1A
TFR2A
TFR3A
TK3A
−
−
−
−
TC1A
8
8
8
8
TMA TAM XAM XAMI XAMD
9
TAK1
−
TC2A
9
9
9
9
SNZV
D
TMA TAM XAM XAMI XAMD
TAL1 TAK2
TAW1 TAK3
−
TPAA
10
TMA TAM XAM XAMI XAMD
11 11 11 11 11
TMA TAM XAM XAMI XAMD
12 12 12 12 12
TMA TAM XAM XAMI XAMD
13 13 13 13 13
TMA TAM XAM XAMI XAMD
14 14 14 14 14
TMA TAM XAM XAMI XAMD
15 15 15 15 15
10
10
10
10
TL2A TK0A
−
RCP
SCP
−
−
−
−
−
−
−
DWDT
TL3A
TLCA
TW1A
TW2A
−
−
−
−
TAW2
−
TPU0A
TPU1A
TAW3 TAPU3
−
−
−
TAPU1
TAPU2
TAW4
TAW5
TPU2A TR1AB
−
The above table shows the relationship between machine language codes and machine language instructions. D3–D0 show the low-order
4 bits of the machine language code, and D9–D4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each
instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are
described below.
The second word
BL
10 paaa aaaa
10 paaa aaaa
10 pp00 pppp
10 pp00 pppp
00 0111 nnnn
00 0010 1011
BML
BLA
BMLA
SEA
SZD
Rev.1.01 Feb 15, 2008 Page 139 of 146
REJ03B0224-0101
455A Group
Electrical characteristics
Absolute maximum ratings
Table 30 Absolute maximum ratings
Symbol
VDD
Parameter
Conditions
Ratings
−0.3 to 6.5
Unit
V
Supply voltage
-
-
VI
−0.3 to VDD+0.3
V
Input voltage P0, P1, P2, P3, D0-D7, RESET, XIN,
XCIN, INT, CNTR
VO
Output transistors in cut-off
state
−0.3 to VDD+0.3
V
Output voltage P0, P1, P2, P3, D0–D7, RESET
VO
VO
Pd
-
−0.3 to VDD+0.3
−0.3 to VDD+0.3
300
V
V
Output voltage C/CNTR, XOUT, XCOUT
-
Output voltage SEG0 to SEG31, COM0 to COM3
Power dissipation
Ta = 25 °C
mW
°C
°C
Topr
Tstg
Operating temperature range
Storage temperature range
-
-
−20 to 85
−40 to 125
Rev.1.01 Feb 15, 2008 Page 140 of 146
REJ03B0224-0101
455A Group
Recommended operating conditions
Table 31 Recommended operating conditions 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol
Parameter
Supply voltage
Conditions
Unit
V
Min.
4
Typ.
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VDD
f(STCK) ≤ 6MHz
f(STCK) ≤ 4.4MHz
f(STCK) ≤ 2.2MHz
f(STCK) ≤ 1.1MHz
f(STCK) ≤ 4.8MHz
f(STCK) ≤ 3.2MHz
f(STCK) ≤ 1.6MHz
f(STCK) ≤ 0.8MHz
f(STCK) ≤ 50 kHz
(with a ceramic resonator)
2.7
2
1.8
4
VDD
Supply voltage
(when an external clock is
used)
V
2.7
2
1.8
1.8
VDD
VDD
Supply voltage
(when quartz-crystal oscillation
is used)
V
V
Supply voltage
(Low-speed/High-speed on-
chip oscillator is used)
1.8
1.6
5.5
5.5
VRAM
VSS
RAM back-up voltage
Supply voltage
(at RAM back-up)
V
V
V
V
0
VLC3
VIH
LCD power supply (Note 1)
“H” level input voltage
1.8
VDD
VDD
VDD
VDD
P0, P1, P2, P3, D0–D7
0.8VDD
0.7VDD
0.85VDD
XIN, XCIN
RESET
0.85VDD
VDD
INT
CNTR
0.8VDD
VDD
VIL
“L” level input voltage
P0, P1, P2, P3, D0–D7
XIN, XCIN
0
0
0
0.2VDD
0.3VDD
0.3VDD
V
RESET
0
0
0.15VDD
INT
CNTR
0.15VDD
−20
−10
−30
−15
−10
−5
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
“H” level peak output current
P0, P1, P2, P3, D0–D5
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
mA
mA
mA
mA
C/CNTR
“H” level average output current P0, P1, P2, P3, D0–D5
(Note 2)
C/CNTR
−20
−10
24
“L” level peak output current
P0, P1, P2, P3, D0–D7, C/CNTR
RESET
12
10
4
“L” level average output current
(Note 2)
15
P0, P1, P2, P3, D0–D7, C/CNTR
RESET
7
5
2
ΣIOH(avg)
ΣIOL(avg)
“H” level total average current
“L” level total average current
P0, C/CNTR
−40
−40
40
mA
mA
P1, P2, P3, D0−D5
P0, C/CNTR
40
P1, P2, P3, D0−D7, RESET
Note 1. At 1/2 bias: VLC1 = VLC2 = (1/2)•VLC3
At 1/3 bias: VLC1 = (1/3)•VLC3, VLC2 = (2/3)•VLC3
Note 2. The average output current is the average value during 100ms.
Rev.1.01 Feb 15, 2008 Page 141 of 146
REJ03B0224-0101
455A Group
Table 32 Recommended operating conditions 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol
f(XIN)
Parameter
Conditions
Unit
Min.
Typ.
Max.
6
Oscillation frequency
f(STCK) = f(XIN)
VDD = 4.0 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 4 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2.7 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
VDD = 2 V to 5.5 V
VDD = 1.8 V to 5.5 V
MHz
(with a ceramic resonator)
4.4
2.2
1.1
6
f(STCK) = f(XIN)/2
4.4
2.2
6
f(STCK) = f(XIN)/4, f(XIN)/8
f(STCK) = f(XIN)
4.4
4.8
3.2
1.6
0.8
4.8
3.2
1.6
4.8
3.2
50
f(XIN)
Oscillation frequency
(with an external clock input)
MHz
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)/4, f(XIN)/8
Quartz-crystal oscillator
f(XCIN)
Oscillation frequency
kHz
(at quarts-crystal oscillation)
f(CNTR)
Timer external input frequency CNTR
f(STCK)/6 Hz
s
tw(CNTR) Timer external input period
(“H” and “L” pulse width)
CNTR
3/f(STCK)
TPON
Power-on reset circuit valid
supply voltage rising time
(Note 1)
VDD = 0 → 1.8V
100
µs
Note 1. If the rising time exceeds the maximum rating value, connect a capacitor between the RESET pin and Vss at the shortest
distance, and input “L” level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
with a ceramic resonator
f(STCK)
at external clock oscillation
f(STCK)
[MHz]
[MHz]
6
4.8
4.4
2.2
3.2
1.6
0.8
1.1
Recommended
operating conditions
Recommended
operating conditions
1.8 2
2.7
4
5.5
1.8 2
2.7
4
5.5
VDD
[V]
VDD
[V]
at quartz-crystal oscillation
f(STCK)
[kHz]
50
Recommended
operating conditions
1.8
5.5
VDD
[V]
Fig 80. System clock (STCK) operating condition map
Rev.1.01 Feb 15, 2008 Page 142 of 146
REJ03B0224-0101
455A Group
Electrical characteristics
Table 33 Electrical characteristics 1 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = −10mA
Unit
V
Min. Typ. Max.
VOH
“H” level output voltage P0, P1, P2, P3, D0–D5
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
3
IOH = −3mA
IOH = −5mA
IOH = −1mA
IOH = −20mA
IOH = −6mA
IOH =−10mA
IOH = −3mA
IOL = 15mA
IOL = 5mA
IOL = 9mA
IOL = 3mA
IOL = 5mA
IOL = 1mA
IOL = 2mA
4.1
2.1
2.4
3
VOH
VOL
VOL
“H” level output voltage C/CNTR
V
V
V
4.1
2.1
2.4
2
“L” level output voltage P0, P1, P2, P3, D0–D7
C/CNTR
0.9
1.4
0.9
2
“L” level output voltage
RESET
0.6
0.9
2
VDD = 3V
VI = VDD
IIH
IIL
“H” level input current
“L” level input current
Pull-up resistor value
P0, P1, P2, P3, D0–D7
RESET, XIN, XCIN, INT
CNTR
µA
µA
P0, P1, P2, P3, D0–D7
RESET, XIN, XCIN, INT
CNTR
VI = 0V
−2
P0, P1, P2, P3, D0 to D7
No pull-up
RPU
P0, P1, P2, P3, D0 to D7
RESET
VI = 0V
VDD = 5V
VDD = 3V
30
50
60
120
1
125
250
kΩ
V
VT+ −VT−
VT+ −VT−
VT+ −VT−
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
Hysteresis
Hysteresis
Hysteresis
RESET
INT
0.4
0.6
0.3
0.2
0.2
V
CNTR
V
f(HSOCO) High-speed on-chip oscillator clock frequency
f(LSOCO) Low-speed on-chip oscillator clock frequency
400 1000 1600 kHz
200
40
500
100
50
1.5
2
700
160 kHz
70
20
RCOM
RSEG
RVLC
COM output impedance
(Note 1)
7.5
10
kΩ
SEG output impedance
(Note 1)
1.5
2
7.5
10
kΩ
Internal resistor for LCD power supply
When dividing resistor 2r × 3 selected 300
When dividing resistor 2r × 2 selected 200
600 1200 kΩ
400
300
200
800
600
400
When dividing resistor r × 3 selected
When dividing resistor r × 2 selected
150
100
Note 1. The impedance state is the resistor value of the output voltage.
at VLC3 level output: VO = 0.8 VLC3
at VLC2 level output: VO = 0.8 VLC2
at VLC1 level output: VO = 0.2 VLC2 + VLC1
at VSS level output: VO = 0.2 VLC1
Rev.1.01 Feb 15, 2008 Page 143 of 146
REJ03B0224-0101
455A Group
Table 34 Electrical characteristics 2 (Ta = –20 °C to 85 °C, VDD = 1.8 to 5.5 V, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
f(STCK) = f(XIN)/8
Unit
mA
Min. Typ. Max.
IDD
Supply current
at active mode
(with a ceramic oscillator) f(XIN) = 6MHz
VDD = 5V
1.2
1.3
1.6
2.2
2.4
2.6
3.2
4.4
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
(1, 2)
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = stop
VDD = 5V
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
0.9
1
1.8
2
mA
mA
µA
µA
µA
µA
µA
µA
f(XIN) = 4MHz
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = stop
1.2
1.6
2.4
3.2
VDD = 3V
f(STCK) = f(XIN)/8
f(STCK) = f(XIN)/4
f(STCK) = f(XIN)/2
f(STCK) = f(XIN)
0.3
0.4
0.5
0.7
0.6
0.8
1
f(XIN) = 4MHz
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = stop
1.4
at active mode
(with a quartz-crystal
oscillator)(1, 2)
VDD = 5V
f(XIN) = stop
f(HSOCO) = stop
f(XCIN) = 32 kHz
f(LSOCO) = stop
f(STCK) = f(XCIN)/8
f(STCK) = f(XCIN)/4
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
7
8
14
16
20
28
10
14
VDD = 3V
f(XIN) = stop
f(HSOCO) = stop
f(XCIN) = 32 kHz
f(LSOCO) = stop
f(STCK) = f(XCIN)/8
f(STCK) = f(XCIN)/4
f(STCK) = f(XCIN)/2
f(STCK) = f(XCIN)
5
6
7
8
10
12
14
16
at active mode
VDD = 5V
f(XIN) = stop
f(HSOCO) = active
f(XCIN) = stop
f(LSOCO) = stop
f(STCK) = f(HSOCO)/8
f(STCK) = f(HSOCO)/4
f(STCK) = f(HSOCO)/2
f(STCK) = f(HSOCO)
50
70
100
140
220
380
(with a high-speed
on-chip oscillator
f(HSOCO))(1, 2)
110
190
VDD = 3V
f(XIN) = stop
f(HSOCO) = active
f(XCIN) = stop
f(LSOCO) = stop
f(STCK) = f(HSOCO)/8
f(STCK) = f(HSOCO)/4
f(STCK) = f(HSOCO)/2
f(STCK) = f(HSOCO)
12
18
30
54
24
36
60
108
at active mode
VDD = 5V
f(STCK) = f(LSOCO)/8
f(STCK) = f(LSOCO)/4
f(STCK) = f(LSOCO/2
f(STCK) = f(LSOCO)
10
12
16
24
20
24
32
48
(with a low-speed on-chip f(XIN) = stop
oscillator f(LSOCO))(1, 2)
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = active
VDD = 3V
f(XIN) = stop
f(HSOCO) = stop
f(XCIN) = stop
f(LSOCO) = active
f(STCK) = f(LSOCO)/8
f(STCK) = f(LSOCO)/4
f(STCK) = f(LSOCO)/2
f(STCK) = f(LSOCO)
3
4
5
7
6
8
10
14
at clock operation mode
(POF instruction
execution)
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
6
5
12
10
40
10
3
µA
µA
f(XCIN) = 32 kHz
20
5
(1, 2)
f(LSOCO) = active
at RAM back-up mode
(POF2 instruction
execution)(1)
Ta = 25°C
VDD = 5V
VDD = 3V
0.1
10
6
Note 1. The voltage drop detection circuit operation current (IRST) is added.
Note 2. When the internal dividing resistors for LCD power are used, the current values according to using resistor values are added.
Rev.1.01 Feb 15, 2008 Page 144 of 146
REJ03B0224-0101
455A Group
Voltage drop detection circuit characteristics
Table 35 Voltage drop detection circuit characteristics (Ta = –20 °C to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Detection voltage
Test conditions
Unit
V
Min.
Typ.
1.7
Max.
VRST-
Ta = 25°C
(reset occurs) (Note 1)
−20°C≤ Ta < 0°C
0°C≤ Ta < 50°C
50°C≤ Ta ≤ 85°C
Ta = 25°C
1.6
1.3
1.1
2.2
2.1
1.8
VRST+
Detection voltage
(reset release) (Note 2)
1.8
2
V
V
−20°C≤ Ta < 0°C
0°C≤ Ta < 50°C
50°C≤ Ta ≤ 85°C
Ta = 25°C
1.7
1.4
1.2
2.3
2.2
1.9
VSKIP
Detection voltage
(skip occurs) (Note 3)
−20°C≤ Ta < 0°C
0°C≤ Ta < 50°C
50°C≤ Ta ≤ 85°C
1.9
1.6
1.4
2.5
2.4
2.1
VRST+ −VRST-
Detection voltage hysteresis
Operation current (Note 4)
0.1
30
15
6
V
IRST
VDD = 5V
60
30
12
1.2
µA
VDD = 3V
VDD = 1.8V
TRST
Detection time (Note 5)
VDD → (VRST- −0.1V)
0.2
ms
Note 1. The detection voltage (VRST−) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
Note 2. The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset
occurs.
Note 3. When the supply voltage goes lower than the detection voltage (VSKIP), the voltage drop detection circuit interrupt request flag
(VDF) is set to “1“.
Note 4. Voltage drop detection circuit operation current (IRST) is added to IDD (power current) when voltage drop detection circuit is used.
Note 5. The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- −0.1V].
Basic timing diagram
Machine cycle
Mi
Mi + 1
Parameter
Pin name
STCK
System clock
Port output
D0 to D7
P00 to P03
P10 to P13
P20 to P23
P30 to P33, C
Port input
D0 to D7
P00 to P03
P10 to P13
P20 to P23
P30 to P33
Interrupt input
INT
Rev.1.01 Feb 15, 2008 Page 145 of 146
REJ03B0224-0101
455A Group
PACKAGE OUTLINE
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
MASS[Typ.]
0.3g
HD
D
*1
39
27
NOTE)
40
26
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
Dimension in Millimeters
Reference
Symbol
Min Nom Max
52
Terminal cross section
D
E
9.9 10.0 10.1
9.9 10.0 10.1
1.4
14
A2
HD
HE
A
1
ZD
13
11.8 12.0 12.2
11.8 12.0 12.2
1.7
Index mark
F
c
A1
bp
b1
c
0.05 0.1 0.15
0.27 0.32 0.37
0.30
0.145
0.125
0.09
0.20
L
c1
y
*3
e
bp
L1
0°
8°
x
e
x
0.65
Detail F
0.13
0.10
y
ZD
ZE
L
1.1
1.1
0.35 0.5 0.65
1.0
L1
Rev.1.01 Feb 15, 2008 Page 146 of 146
REJ03B0224-0101
REVISION HISTORY
RI
455A Group Datasheet
Rev.
Date
Description
Summary
Page
1.00
1.01
Oct 18, 2007
Feb 15, 2008
-
-
First edition issued
Delete the “PRELIMINARY” note
7
Table 6: "The key-on wakeup function is invalid." is added to “Usage Condition”
column of “XCOUT/D7”- “Open”, “D0-D4”-“Open”, and “D5/INT”-“Open”.
28
50
58
76
Table 15: Revised
Figure 48: Revised
Figure 56: Revised whole
Interrupt control register I1:
At the “INT pin timer 1 count start synchronous circuit selection bit” value is “0”
“Timer 1 disabled”
At the “INT pin timer 1 count start synchronous circuit selection bit” value is “1”
“Timer 1 enabled” “Timer 1 count start synchronous circuit selected”
→ “Timer 1 count start synchronous circuit not selected”
→
89
90
The second word “D8” value of “BL p, a” instruction: “0” “p6”
→
Note: “p=0 to 47” ”M3455AG8: p=0 to 63 p6=0
→
M3455AGC: p=0 to 95”
The second word “D8” value of “BLA p” instruction: “0”
→ “p6”
Note: “p=0 to 47”
→ ”M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95”
The second word “D8” value of “BML p, a” instruction: “0”
Note: “p=0 to 47” ”M3455AG8: p=0 to 63 p6=0
→ “p6”
→
M3455AGC: p=0 to 95”
The second word “D8” value of “BMLA p” instruction: “0”
→ “p6”
Note: “p=0 to 47”
→ ”M3455AG8: p=0 to 63 p6=0
M3455AGC: p=0 to 95”
98
The “RBK” instruction order is changed to next of the ”RBj” instruction
The second word “D8” value of “BL p, a” instruction: “0” “p6”
The second word “D8” value of “BLA p” instruction: “0” “p6”
The second word “D8” value of “BML p, a” instruction: “0” “p6”
“p6”
126
→
→
→
The second word “D8” value of “BMLA p” instruction: “0”
Note: ”M3455AG8: p6=0” is added
→
144
Table 34: All “f(STCK)=f(XIN)“ are changed to “f(STCK)=f(LSOCO)” at active mode
(with a low-speed on-chip oscillator f(LSOCO))“
(1/1)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
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http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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