M37513M5-XXXHP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M37513M5-XXXHP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总66页 (文件大小：1134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no ces whatsoever have been
made to the contents of the document, and these changes do not cony alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business opof high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀSerial I/O1 ....................8-bit ꢀ 1 (UART or Clock-synchronized)
ꢀSerial I/O2 ...................................8-bit ꢀ 1 (Clock-synchronized)
ꢀPWM output.................................................................... 8-bit ꢀ 1
ꢀA-D converter ............................................... 10-bit ꢀ 8 channels
ꢀD-A converter ................................................. 8-bit ꢀ 2 channels
ꢀLCD drive control circuit
DESCRIPTION
The 7513 group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7513 group has the LCD drive control circuit, the A-D/D-A
converter, the UART, and the PWM as additional functions.
The various microcomputers in the 7513 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Bias ................................................................................... 1/2, 1/3
Duty ...........................................................................1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 40
ꢀ2 Clock generating circuits
For details on availability of microcomputers in the 7513 group,
refer to the section on group expansion.
(connect to external ceramic resonator or quartz-crystal oscillator)
ꢀWatchdog timer ............................................................ 14-bit ꢀ 1
ꢀPower source voltage................................................ 2.2 to 5.5 V
ꢀPower dissipation
FEATURES
ꢀBasic machine-language instructions ...................................... 71
ꢀThe minimum instruction execution time ........................... 0.5 µs
(at 8MHz oscillation frequency)
In high-speed mode ..................................................40 mW
(at 8 MHz oscillaticy, at 5 V power source voltage)
In low-speed mod.......................................... 60 µW
(at 32 kHz oquency, at 3 V power source voltage)
ꢀOperating tange................................... – 20 to 85°C
ꢀMemory size
ROM ............................................................... 32 K to 60 K bytes
RAM ............................................................... 1024 to 2048 bytes
ꢀProgrammable input/output ports ............................................ 55
ꢀOutput port ................................................................................. 8
ꢀInput port .................................................................................... 1
ꢀInterrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
APPLS
Cams phone, etc.
ꢀTimers ........................................................... 8-bit ꢀ 3, 16-bit ꢀ 2
PIN CONFIGURATION (TOP VIEW)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
81
82
83
84
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
M37513EFFS
V
X
X
X
X
SS
V
CC
REF
AVSS
OUT
IN
V
COUT
CIN
COM
COM
COM
COM
3
2
1
0
RESET
P7
P7
P7
P7
0
1
2
3
/INT0
V
L3
V
L2
C2
Package type : 100D0 (Window type ceramic LCC)
Fig. 1 M37513EFFS pin configuration
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
76
50
SEG12
P1
P1
P1
P1
P2
P2
P2
P2
P2
2
4
5
6
7
0
1
2
3
4
5
/SEG38
/SEG39
SEG11
77
49
48
47
46
45
44
43
42
41
4
33
32
31
30
29
28
27
26
SEG10
SEG
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
9
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
8
7
6
5
4
3
2
1
0
M37513M8-XXXGP
M37513M8-XXXHP
X
X
X
V
CC
OUT
V
REF
IN
COUT
AVSS
CIN
COM
COM
COM
COM
3
2
1
0
RESET
P70
P71
P72
P73
P74
P75
P76
/INT0
V
V
L3
L2
C
C
2
1
V
L1
Package ty...... 100P6Q-A (100-pin plastic-molded LQFP)
Package P........ 100PFB-A (100-pin plastic-molded TQFP)
Fig. 2 M37513M8-XXXGP/M37HP pin configuration
2
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Key input/key-p interrupt
Real time
I N 1 T , I N T
INT
0
Fig. 3 Functional block diagram
3
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
VREF
Power source
•Apply voltage of 2.2 V to 5.5 V to VCC, and 0 V to VSS.
Analog refer-
ence voltage
•Reference voltage input pin for A-D converter and D-A converter.
AVSS
Analog power
source
•GND input pin for A-D converter and D-A converter.
•Connect to VSS.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the main clock generating circuit.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN in and leave the XOUT pin open.
LCD power
source
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
VL1–VL3
C1, C2
•Input 0 – VL3 voltage to LCD.
Charge-pump
capacitor pin
•External capacitor pins for a voltage multiplier (3 timontorl.
Common output
•LCD common output pins.
COM0–COM3
•COM2 and COM3 are not used at 1/2 dut
•COM3 is not used at 1/3 duty ratio.
•LCD segment output pins.
SEG0–SEG17 Segment output
P00/SEG26–
P07/SEG33
•LCD segment output pins
I/O port P0
•8-bit I/O port.
•CMOS compatible input lev
•CMOS 3-state output st
•Pull-up control is en
•I/O direction regeach 8-bit pin to be pro-
grammed as eoutput.
P10/SEG34– I/O port P1
P15/SEG39
•6-bit I/O pofunction as port P0.
•CMOS put level.
•CMOtput structure.
•Pl is enabled.
ion register allows each 6-bit pin to be pro-
d as either input or output.
P16, P17
t I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually programmed as either input or output.
•Pull-up control is enabled.
P20 – P27
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•Key input (key-on wake-up) interrupt
input pins
I/O port P2
•CMOS 3-state output structure.
•Pull-up control is enabled.
•LCD segment output pins
P3
P3
0
7
/SEG18
/SEG25
–
Output port P3
•8-bit output port with same function as port P0.
•CMOS 3-state output structure.
•Port output control is enabled.
4
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
•A-D trigger input pin
P40/ADT
I/O port P4
•1-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•Interrupt input pin
•N-channel open-drain output structure.
•7-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•Interrupt input pins
P41/INT1,
P42/INT2
•CMOS 3-state output structure.
P43/φ/TOUT
•φ clock output pin
•Pull-up control is enabled.
•Timer 2 output pin
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
•Serial I/O1 I/O pins
P50/PWM0,
P51/PWM1
I/O port P5
•8-bit I/O port with same function as P16 and P17.
•CMOS compatible input level.
•PWM function pins
•CMOS 3-state output structure.
•Pull-up control is enabled.
P52/RTP0,
P53/RTP1
e port function pins
imer X, Y function pins
•D-A conversion output pins
P54/CNTR0,
P55/CNTR1
P56/DA1,
P57/DA2
P6
P6
P6
P6
0
1
2
3
/AN
/AN
/AN
/AN
0
1
2
3
/SIN2,
I/O port P6
•8-bit I/O port with same function as .
•CMOS compatible input level.
•A-D conversion input pins
•Serial I/O2 I/O pins
/SOUT2,
/SCLK21,
/SCLK22
•CMOS 3-state output structu
•Pull-up control is enabled
P64/AN4–
P67/AN7
•A-D conversion input pins
•Interrupt input pin
Input port P7
I/O port P7
•1-bit I/O port.
P70/INT0
•CMOS comlevel.
•7-bit I/O me function as P16 and P17.
•CMOe input level.
P71–P77
•Nen-drain output structure.
XCOUT
XCIN
Sub-clock output generating circuit I/O pins.
ct a resonator. External clock cannot be used.)
Sub-clock input
5
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PART NUMBERING
Product
M37513
M
8
–
XXX HP
Package type
HP : 100PFB-A package
GP : 100P6Q-A package
FS : 100D0 package
ROM number
Omitted in One Time PROM version
shipped in blank and EPROM versi
ROM/PRO
: 409
: 8
s
ytes
0 bytes
576 bytes
28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
1
2
3
9
A
B
C
D
E
F
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
E
: Mask ROM version
: EPROM or One Time PROM version
RAM size
M37513M8-XXXGP/HP
M37513EFGP/HP/FS
: 1024 byte
: 2048 bytes
Fig. 4 Part numbering
6
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
Package
Mitsubishi plans to expand the 7513 group as follows:
100PFB-A ................................0.4 mm-pitch plastic molded TQFP
100P6Q-A ................................ 0.5 mm-pitch plastic molded LQFP
100D0 ..................... Window type ceramic LCC (EPROM version)
Memory Type
Support for Mask ROM, One Time PROM, and EPROM versions
Memory Size
ROM/PROM size ............................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2048 bytes
Memory Expansion Plan
ROM size (bytes)
Under development
M37513EF
60 K
56 K
52 K
48 K
44 K
40 K
36 K
Mass production
M37513M8
32 K
28 K
24 K
20 K
16 K
12 K
8 K
4 K
192 256
384
5
68
896
1024
1152
1280
1408
1536
1664
1792
1920
2048
RAM size (bytes)
Note: Pdevelopment or planning: the development schedule and specifications
ed without notice.
Fig. 5 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
As of Nov. 2000
(P) ROM size (bytes)
Product
RAM size (bytes)
1024
Package
Remarks
ROM size for User in (
)
M37513M8-XXXHP
M37513M8-XXXGP
M37513EFHP
100PFB-A
100P6Q-A
100PFB-A
100P6Q-A
100D0
Mask ROM version
Mask ROM version
32768
(32638)
One Time PROM version (blank)
One Time PROM version (blank)
EPROM version
61440
(61310)
2048
M37513EFGP
M37513EFFS
7
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
Central Processing Unit (CPU)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The 7513 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Series addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Series instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Count
The program counit counter consisting of two 8-bit
registers PCH aused to indicate the address of the
next instructicuted.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b7
Accumulator
b0
b
X
Index register X
b0
Y
Index register Y
b7
b0
S
Stack pointer
b15
b7
b7
b0
PCH
PCL
Program counter
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
8
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
M (S) (PCL)
(S) (S) – 1
Push return address
on stack
Push contents of processor
status register on stack
M (S) (PS)
(S) (S
In
See
I Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
RTI
S) (S) + 1
POP return
address from stack
POP contents of
processor status
register from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condieptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
9
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT uction is stored in the overflow flag.
•Bit 7: Negative flag (N
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is seof an arithmetic operation or data
transfer is nethe BIT instruction is executed, bit 7 of
the memoerated on by the BIT instruction is stored
in the
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 5 Set and clear instructions of each bit of procesegister
C flag
Z flag
D flag
B flag
T flag
V flag
_
N flag
_
_
_
_
_
Set instruction
SEC
CLC
I
CLI
SED
CLD
SET
CLT
Clear instruction
CLV
10
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1”
(Do not write “0” to
Sub-clock (XCINt
0 : Stoppe
1 : Oscil
Main cltop bit
0 :
sion ratio selection bit
igh-speed mode)
(middle-speed mode)
l system clock selection bit
XIN-XOUT selected (middle-/high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
Fig. 8 Structure of CPU mode register
11
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
RAM
Access to this area with only 2 bytes is possible in the special
RAM is used for data storage and for stack area of subroutine
page addressing mode.
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
00
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
6
192
256
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
LCD display RAM area
384
10016
XXXX16
084016
512
640
768
896
1024
1536
2048
Reserved area
Not used
ROM area
ROM size
(bytes)
Address
YYYY1
s
Z16
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
4096
8192
F0
E00
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 9 Memory map diagram
12
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
Timer X (low) (TXL)
Port P0 (P0)
Timer X (high) (TXH)
Timer Y (low) (TYL)
Timer Y (high) (TYH)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 output control register (P1D)
Port P2 (P2)
002416 Timer 1 (T1)
002516
002616
002716
002816
002916
002A16
Timer 2 (T2)
Port P2 direction register (P2D)
Port P3 (P3)
Timer 3 (T3)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
Port P3 output control register (P3C)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
T
OUT/φ output control register (CKOUT)
002B16 PWM control register (PWMCON)
Port P5 direction register (P5D)
Port P6 (P6)
002C16 PWM prescaler (PREPWM)
002D16 PWM register (PWM)
Port P6 direction register (P6D)
Port P7 (P7)
002E16
002F16
003016
Port P7 direction register (P7D)
A-D control regi
003116
003216
003316
003416
003516
A-D conversw-order) (ADL)
A-D con(high-order) (ADH)
D-A1 ister (DA1)
Dregister (DA2)
Key input control register (KIC)
PULL register A (PULLA)
00361egister (DACON)
timer control register (WDTCON)
ent output enable register (SEG)
D mode register (LM)
00
B16
03C16
003D16
003E16
003F16
PULL register B (PULLB)
Transmit/Receive buffer register(TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Serial I/O2 control register (SIO
Reserved area
Serial I/O2 register (SIO2
Fig. 10 Memory map of special funer (SFR)
13
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O PORTS
Direction Registers
b0
b7
PULL register A
(PULLA : address 001616)
The I/O ports have direction registers which determine the input/
output direction of each individual pin. (P00–P07 and P10–P15 use
bit 0 of port P0, P1 direction registers respectively.)
When “1” is written to that bit, that pin becomes an output pin.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin.
Not used
P10–P13 pull-up
P14, P15 pull-up
P16, P17 pull-up
P20–P23 pull-up
P24–P27 pull-up
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating and the value of that pin can be read. If a pin set to input
is written to, only the port output latch is written to and the pin re-
mains floating.
b7
b0
PULL register B
(PULLB : address 001716)
P41–P43 pull-up
P44–P47 pull-up
50–P53 pull-up
–P57 pull-up
63 pull-up
Port P3 Output Control Register
Bit 0 of the port P3 output control register (address 000716) en-
ables control of the output of ports P30 to P37.
–P67 pull-up
Not used (return “0” when read)
When the bit is set to “1”, the port output function is valid.
When resetting, bit 0 of the port P3 output control register is set to
“0” (the port output function is invalid) and ports P30 to P37 are
pulled up.
0 : No pull-up
1 : Pull-up
Nnts of PULL register A and PULL register B
affect ports programmed as the output port.
Pull-up Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports P1, P2, P4 to P6 can control
pull-up with a program.
ucture of PULL register A and PULL register B
However, the contents of PULL register A and PULL register B
not affect ports programmed as the output ports.
The PULL register A setting is invalid for pins set to seg
put on the segment output enable register.
14
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 List of I/O port function (1)
Name
Input/Output
Non-Port Function
Pin
I/O Format
Related SFRs
Diagram No.
(1)
P00/SEG26–
P07/SEG33
Port P0
Input/output,
byte unit
CMOS compatible
input level
LCD segment output
Segment output enable
register
(2)
CMOS 3-state output
P10/SEG34–
P15/SEG39
Port P1
Input/output,
6-bit unit
CMOS compatible
input level
LCD segment output
PULL register A
(3)
(4)
Segment output enable
register
CMOS 3-state output
Input/output,
individual bits
CMOS compatible
input level
PULL register A
P16 , P17
(6)
(6)
(5)
CMOS 3-state output
P20–P27
Port P2
Port P3
Input/output,
individual bits
CMOS compatible
input level
Key input (key-on
wake-up) interrupt
input
PULL register A
Interrupt control register2
Key input control register
CMOS 3-state output
egment output enable
ster
P30/SEG18–
P37/SEG25
Output
CMOS 3-state output
LCD segment output
output enable register
CMOS compatible
input level
A-D control register
(15)
P40/ADT
Port P4
Input/output,
individual bits
A-D trigge
Interrupt edge selection
register
Externput
N-channel open-drain
output
CMOS compatible
input level
interrupt input
(6)
PULL register B
P41/INT1,
P42/INT2
Interrupt edge selection
register
CMOS 3-state o
P43/φ/TOUT
Timer output
(14)
PULL register B
φ output
Timer 123 mode register
TOUT/φ output control
register
P44/RXD,
P45/TXD,
P46/SCLK1,
P47/SRDY1
Serial I/O1 function I/O
PULL register B
(7)
(8)
Serial I/O1 control register
Serial I/O1 status register
UART control register
(9)
(10)
(12)
P50/PWM0,
P51/PWM1
Port P5
Inpu
in
CMOS compatible
input level
PWM output
PULL register B
PWM control register
CMOS 3-state output
P52/RTP0,
P53/RTP1
Real time port
function output
(11)
(13)
(16)
(17)
PULL register B
Timer X mode register
P54/CNTR0
P55/CNTR1
P56/DA1
PULL register B
Timer X function I/O
TimerY function input
Timer X mode register
PULL register B
Timer Y mode register
PULL register B
DA1 output
A-D VREF input
D-A control register
A-D control register
PULL register B
P57/DA2
DA2 output
(17)
D-A control register
15
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 7 List of I/O port function (2)
Pin
Name
Input/Output
I/O Format
Non-Port Function
Related SFRS
Diagram No.
P60/SIN2/AN0
Port P6
Input/
A-D conversion input
Serial I/O2 function I/O
A-D control register
Serial I/O2 control
register
(19)
CMOS compatible input
level
CMOS 3-state output
output,
individual
bits
P61/SOUT2/
AN1
(20)
(21)
P62/SCLK21/
AN2
P63/SCLK22 /
AN3
(22)
(18)
A-D conversion input
External interrupt input
A-D control register
P64/AN4–
P67/AN7
P70/INT0
Port P7
Input
CMOS compatible input
level
Interrupt edge
selection register
(25)
(15)
P71–P77
Input/
CMOS compatible input
level
output,
individual
bits
N-channel open-drain
output
COM0–COM3
SEG0–SEG17
Common
Segment
Output
Output
LCD common output
LCD segment output
LCD mode register
(23)
(24)
Notes1: How to use double-function ports as function I/O ports, refer to the apns.
2: Make sure that the input level at each pin is either 0 V or VCC durinthe STP instruction. When an input level is at an intermediate po-
tential, a current will flow VCC to VSS through the input-stage gat
16
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P01–P07
VL2/VL3/VCC
LCD drive timing
Segment/Port
Segment
Segment data
Interface logic level
shift circuit
Data bus
Port latch
Port direction register
V
L1/VSS
Port/Segment
Port
Port direction register
(2) Port P0
0
VL2/VL3/VCC
LCD drive timing
Segment/
Direction register
Segment data
Port latch
Interface logic level
shift circuit
Se
Data bus
VSS
Port/Segment
t
Port directio
(3) Ports P11–P15
Pull-up
V
L2/VL3/VCC
LCD driv
Segment/Port
Segment data
c level
Segment
Data bus
Port latch
Port direction register
V
L1/VSS
ment
Port
Port direction register
(4) Port P1
0
Pull-up
V
L2/VL3/VCC
LCD drive timing
Segment/Port
irection register
Segment data
Port latch
Interface logic level
shift circuit
Segment
Data bus
VL1/VSS
Port/Segment
Port direction register
Port
(5) Port P3
V
L2/VL3/VCC
LCD drive timing
Segment/Port
Segment
Segment data
Interface logic level
shift circuit
Data bus
Port latch
V
L1/VSS
Port/Segment
Output control
Port
Fig. 12 Port block diagram (1)
17
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(6) Ports P16, P17, P2, P41, P42
(7) Port P4
4
Pull-up control
Pull-up control
Serial I/O1 enable bit
Reception enable bit
Direction register
Direction register
Data bus
Port latch
Port latch
Data bus
Key input interrupt input
INT , INT interrupt input
Serial I/O1 input
1
2
Except P1 , P17
6
(8) Port P4
5
(9) Port P4
6
Serial I/O1 clock
selection bit
Serial I/O1 enable bit
Pull-up control
Pull-up control
P45
/TxD P-channel output disable bit
Serial I/O1 enable bit
Transmission enable bit
Serial I/O1 mode
Serial
ster
Direction register
Port latch
Data bus
D
Port latch
Serial I/O1 output
Serial I/O1 clock outupt
Serial I/O1 clock input
(11) Ports P52, P53
(10) Port P4
7
Pull-up control
ull-up control
Serial I/O1 mode selection bit
Serial I/O1 enable b
S
RDY1 output enable bi
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
Real time control bit
Real time port data
Serial I/O1 ready output
Fig. 13 Port block diagram (2)
18
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Pull-up control
(13) Port P5
4
(12) Ports P50,P51
Pull-up control
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
Pulse output mode
Timer output
PWM function enable bit
PWM output
TR0 interrupt input
(15) Ports P40, P71–P7
(14) Port P4
3
Pull-up control
Direction register
Data
Port latch
Data bus
Port latch
TOUT/φ output control
A-D trigger input
Timer output
OUT/φ selection bit
Except P71 to P77
T
φ output
(17) Ports P56, P57
(16) Port P5
5
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
D-A conversion output
D-A , D-A output enable bit
REF input switch
REF input selection bit
CNTR1 interrupt input
1
2
V
Except P5
7
V
Fig. 14 Port block diagram (3)
19
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(19) Port P60
(18) Ports P64–P67
Pull-up control
Pull-up control
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 input
A-D conversion input
Analog input pin selection bit
A-D conversion input
Analog input pin selection bit
(20) Port P61
(21) Port P62
Pull-up control
Pull-up control
Synchronous clock selection
P61/SOUT2 P-channel output disable bit
Serial I/O2 transmit completion signal
Synchronous clock selection bit
Serial I/O2 port selectio
Synchronous clock ou
se
Serial I/O2 port selection bit
Direction register
Data bus
Port latch
Data b
latch
Serial I/O2 output
Serial I/O2 clock output
A-D conversion input
Serial I/O2 clock input
Analog input p
A-D conversion input
Analog input pin selection bit
(22) Port P63
control
(23) COM0–COM3
Synchronous clock selection bit
Serial I/O2 port selection bit
Synchronous clock output pin selection bit
VL3
Direction register
VL2
VL1
Data bus
Port
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
VSS
Serial I/O2 clock output
A-D conversion input
Analog input pin selection bit
(25) Port P70
(24) SEG0–SEG17
VL2/VL3
Data bus
The voltage applied to the sources of
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
INT0 input
VL1/VSS
Fig. 15 Port block diagram (4)
20
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupts occur by seventeen sources: seven external, nine inter-
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
nal, and one software.
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an in-
terrupt request bit and an interrupt enable bit, and is controlled by
the interrupt disable flag. An interrupt occurs if the corresponding
interrupt request and enable bits are “1” and the interrupt disable
flag is “0”. Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software. The BRK instruction interrupt and reset cannot be
disabled with any flag or bit. The I flag disables all interrupts ex-
cept the BRK instruction interrupt and reset. If several interrupts
requests occurs at the same time, the interrupt with highest prior-
ity is accepted first.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
■Notes
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer e register (address 2716)
Timegister (address 2816)
•When switching inces of an interrupt vector address
where two or msources are allocated
Related regntrol register (address 003116)
Table 8 Interrupt vector addresses and priority
quest
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Conditions
Reset (Note 2)
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
ion of either rising or
dge of INT0 input
External interrupt
(active edge selectable)
etection of either rising or
lling edge of INT1 input
INT1
FFF916
FFF716
FFF516
FFF8
6
External interrupt
(active edge selectable)
3
4
Serial I/O1
reception
At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Valid when serial I/O1 is selected
At completion of serial I/O1
transmit shift or when transmis-
sion buffer is empty
Serial I/O1
transmission
5
Timer X
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
FF
16
FEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
Timer Y
Timer 2
Timer 3
8
9
CNTR0
At detection of either rising or
falling edge of CNTR0 input
10
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
CNTR1
11
FFE916
FFE816
External interrupt
(active edge selectable)
FFE616
FFE416
At timer 1 underflow
Timer 1
INT2
12
13
FFE716
FFE516
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
Serial I/O2
At completion of serial I/O2 data
transmission or reception
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
Valid when serial I/O2 is selected
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode)
(valid at falling)
External interrupt (Valid when ADT
interrupt is selected
ADT
At either rising or falling edge of
ADT input
At completion of A-D conversion Valid when A-D interrupt is se-
lected
A-D conversion
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
21
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➀ Set the interrupt edge selection bit (active edge switch bit) or
the interrupt source selection bit to “1”.
➀ Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➀ Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
pt request
BRK instruction
Reset
Fig. 16 Interrupt control
b7
b0
b7
0
Key input control register
(KIC : address 001516
Interrupt edge selection register
(INTEDGE : address 003A16
)
)
P20
P21
P22
P23
P24
P25
P26
P27
trigger valid bit
INT
INT
INT
0
1
2
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
trigger valid bit
trigger valid bit
trigger valid bit
trigger valid bit
trigger valid bit
trigger valid bit
trigger valid bit
ADT interrupt edge selection bit
Not used (return “0” when read)
0 : Falling edge active
1 : Rising edge active
0 : Trigger invalid
1 : Trigger valid
b7
b0
b7
b0
Interrupt request register 2
Interrupt re
(IREQ1 6
(IREQ2 : address 003D16
)
)
equest bit
pt request bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Se1 receive interrupt request bit
SeriaI/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
INT interrupt request bit
Serial I/O2 interrupt request bit
Key input interrupt request bit
2
Timer Y interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
INT interrupt enable bit
2
Serial I/O2 interrupt enable bit
Key input interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
Timer 3 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 17 Structure of interrupt-related registers
22
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
“1” to “0”. An example of using a key input interrupt is shown in
Figure 18, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Key Input Interrupt (Key-on wake-up)
A Key-on wake up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is generated when AND of input level goes from
Port PXx
“L” level output
PULLA register
Bit 2 = “1”
Key input control register = “1”
Port P27
direction register = “1”
Key input interrupt request
➀
➀
➀
➀
➀➀
Port P27
latch
Port P27 output
Key input control register = “1”
Port P26
direction register = “1”
➀➀
Port P26
latch
Port P26 output
Key input control regis
Port P25
direction register = “1”
➀➀
Port P25
latch
Port P25 output
Kregister = “1”
Port P24
directi
➀➀
Port P24 output
Key input control register = “1”
P23
ection register = “0”
Port P2 input
reading circuit
➀
➀➀
Port P23
latch
Port P23
input
Key input control register = “1”
direction register = “0”
Port P22
➀➀
Port P22
latch
Port P22
input
Key input control register = “1”
Port P21
direction register = “0”
➀
➀
➀➀
Port P21
latch
Port P21
input
Key input control register = “1”
Port P20
direction register = “0”
➀➀
Port P20
latch
Port P20
input
➀➀ P-channel transistor for pull-up
➀➀ CMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P2 block diagram
23
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
responding to that timer is set to “1”.
TIMERS
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
The 7513 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
Real time port
control bit “1”
Q D
Data bus
P52
data for real time port
P52
Latch
“0”
P5 latch
P5
2
direction register
2
Real time port
control bit “1”
Q D
P53
data for real time port
P5
3
Real time port
control bit “0”
Latch
“0”
P53 direction register
Timer X mode registe
write signal
P53 latch
“1”
f(XIN)/16
(f(XCIN)/16 in low-speed mode*)
Timer X stop
control bit
r X write
ntrol bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge switch bit
Timer X (low) latch
igh) latch (8)
Timer X
interrupt
request
“0”
P54
/CNTR0
Timer X (lo
er X (high) (8)
“10”
“1”
Pulse width
CNTR
0
measurement
interrupt
request
mode
CNTR
0
active
edge switch bit
ode
“0”
“1”
S
Q
Timer Y operating mode bit
“00”,“01”,“10”
CNTR
1
P54 direction register
Pulse width HL continuously measurement mode
interrupt
request
P54 latch
“11”
Rising edge detection
Falling edge detection
Pulse output mo
Period
measurement mode
f(
w-speed mode*)
Timer Y stop
control bit
CNTR1 ac
edge sw
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
,“01”,“11”
Timer Y
interrupt
request
P55
/CNTR
1
Timer Y (low) (8)
“10”
Timer Y operating
mode bit
“1
f(XIN)/16
Timer 1
interrupt
request
(
f(XCIN)/16 in low-speed mode*)
Timer 1 count source
selection bit
“0”
Timer 2 write
control bit
Timer 2 count source
selection bit
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
“0”
Timer 2
interrupt
request
X
CIN
Timer 2 (8)
“1”
“1”
f(XIN)/16
(
f(XCIN)/16 in low-speed mode*)
T
OUT output
T
OUT output
control bit
active edge
switch bit
T
OUT output
control bit
“0”
S
Q
Q
P43
/φ/TOUT
T
“1”
P43
latch
P4
3
direction register
Timer 3 latch (8)
Timer 3 (8)
“0”
“1”
Timer 3
interrupt
request
f(XIN)/16(f(XCIN)/16 in low-speed mode*)
Timer 3 count
source selection bit
* φ = XCIN divided by 2 in low-speed mode
Fig. 19 Timer block diagram
24
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer X
●NotesonCNTR0interruptactiveedgeselection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
●Real time port control
(1) Timer Mode
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, if the real time port control bit is changed
from “0” to “1”, data are output without the timer X.) When the data
for the real time port is changed while the real time port function is
valid, the changed data are output at the next underflow of timer
X.
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the port shared with the CNTR0 pin to input.
Before using this function, set the corresponding port direction
registers to output mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the port
shared with the CNTR0 pin to input.
b7
X mode register
M : address 002716)
Timer X write control bit
(4) Pulse Width Measurement Mode
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P52 data for real time port
P53 data for real time port
Timer X operating mode bits
b5 b4
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the port shared with tha CNTR0 pin to input.
●Timer X write control
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
If the timer X write control bit is “0”, when the value is writ
address of timer X, the value is loaded in the timer X
at the same time.
CNTR0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
If the timer X write control bit is “1”, when the vain the
address of timer X, the value is loaded only The value
in the latch is loaded in timer X after timews.
If the value is written in latch only, unue may be set in
the high-order counter when the worder latch and the
underflow of timer X are perforame timing.
Rising edge active for CNTR0 interrupt
Timer X stop control bit
0 : Count start
1 : Count stop
Fig. 20 Structure of timer X mode register
25
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
b0
Timer Y mode register
(TYM : address 002816)
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
(2) Period Measurement Mode
0
0
1
1
0 : Timer mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
sure the rising edge period in period
ement mode
ge active for CNTR1 interrupt
op control bit
nt start
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the port
shared with the CNTR1 pin to input.
ount stop
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the port
shared with the CNTR1 pin to input.
Fig. 21 of timer Y mode register
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and
edges of CNTR1 pin input signal. Except for this, the op
pulse width HL continuously measurement mode is th
period measurement mode. When using a timer iset
the port shared with the CNTR1 pin to input.
ꢀNotes on CNTR1 interrupt actselection
CNTR1 interrupt active edge dependTR1 active edge
switch bit. However, in pulse width usly measurement
mode, CNTR1 interrupt requeted at both rising and
falling edges of CNTR1 pin input siegardless of the setting of
CNTR1 active edge switch bit.
26
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer. Therefore, rewrite the value
of timer whenever the count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
T
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at ”L” output
OUT/φ output control bit
0 : TOUT/φ output disabled
1 : TOUT/φ output enabled
ꢀTimer 2 write control
Timer 2 write control bit
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode*)
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
Timer 3 count source selection bit
0 : Timer 1 output
(XIN)/16
(XCIN)/16 in low-speed mode*)
ꢀTimer 2 output control
unt source selection bit
IN)/16
When the timer 2 (TOUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output.
or f(XCIN)/16 in low-speed mode*)
1 : f(XCIN
)
Not used (return “0” when read)
* IXCIN/2 in the low-speed mode.
ꢀNotes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer. If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a t
pulse is generated in timer 1 output.
cture of timer 123 mode register
Therefore, set the value of timer in the order of timer 1
and timer 3 after the count source selection of timer 1
27
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Clock Synchronous Serial I/O Mode
SERIAL I/O
Clock synchronous serial I/O1 can be selected by setting the
mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer registers.
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer register
Receive buffer full flag (RBF)
Receive shift register
Receive interrupt request (RI)
P44/RXD
Shift clock
Clock control circuit
P46/SCLK
Serial I/O1
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
1/4
uit
Falling-edge detector
P47/SRDY1
F/F
Transmit shift register shift completion flag (TSC)
Shift clo
Transmit shift r
Transmit
ransmit interrupt source selection bit
P45/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
001816
Fig. 23 Block diagram of clock synchronO1
Transfer shift clock
(1/2 to 1/2048 of the
clock, or an external clo
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Serial output TXD
Serial input RXD
Receive enable signal SRDY1
Write signal to receive/transmit
buffer register (address 001816)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1)
or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TXD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 24 Operation of clock synchronous serial I/O1 function
28
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O1 control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Serial I/O1 control register
Address 001A16
Receive buffer register
OE
Receive buffer full flag (RBF)
Receive interrupt request (RI)
1/16
Character length selection bit
P44/RXD
STdetector
7 bits
Receive shift register
8 bits
l register
SP detector
PE FE
dress 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
Transm
P45/TXD
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
gister
Address 001816
Address 001916
Serial I/O1 status register
Fig. 25 Block diagram of UART serial I/
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=1
TBE=0
TBE=1
TSC=1ꢀ
SP
Serial output TXD
ST
D
0
D
1
ST
D
0
D1
SP
ꢀGenerated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input RXD
D
0
D
1
ST
D
0
D1
Notes 1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O1 control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 26 Operation of UART serial I/O1 function
29
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
ꢀꢀNotes
When setting the transmit enable bit to “1”, the serial I/O1 transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
ꢀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
[Serial I/O1 Status Register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
ꢀ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O1 enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O1 status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift register shift comple-
tion flag (bit 2) and the transmit buffer empty flag (bit 0) become
“1”.
[Serial I/O1 Control Register (SIO1CON)] 00
The serial I/O1 control register contains eight control b
serial I/O1 function.
[UART Control Register (UARTCB16
This is a 5 bit register containing four contrare valid
when UART is selected and set the df an data re-
ceiver/transfer, and one control bit, ws valid and sets
the output structure of the P45/TX
[Baud Rate Generator(B] 001616
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
30
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b7
b0
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
(SIO1CON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin.
7
pin operates as SRDY1 output pin.
Transmit interrupsource selection bit (TIC)
0: Interrupt whnsmit buffer has emptied
1: Interrupt mit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
TransE)
0: Td
1led
Framing error flag (FE)
0: No error
1: Framing error
able bit (RE)
e disabled
eive enabled
Summing error flag (SE)
0: OE U PE U FE =0
1: OE U PE U FE =1
erial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O1 enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
4
7
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PAR
0: Even parity
1: Odd parity
Stop bit length TPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 27 Structure of serial I/O1 control registers
31
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
The serial I/O2 function can be used only for clock synchronous
b7
b0
serial I/O.
Serial I/O2 control register
(SIO2CON : address 001D16)
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
When an internal clock is selected as the synchronous clock of the
serial I/O2, either P62 or P63 can be selected as an output pin of
the synchronous clock. In this case, the pin that is not selected as
an output pin of the synchronous clock functions as a port.
Internal synchronous clock select bits
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 0 0:
Do not set
1 0 1:
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains 8 bits which control vari-
ous serial I/O2 functions.
1: SOUT2,SCLK21/SCLK22 signal output
P61/SOUT2 P-channel output disable bit
0: CMOS output (in output mode)
1: N-cel open-drain output
(iode)
tion selection bit
rst
chronous clock selection bit
: External clock
1: Internal clock
Synchronous clock output pin selection bit
0: SCLK21
1: SCLK22
28 Structure of serial I/O2 control register
Internal synchronous
clock select bits
1/8
1/16
Data bus
1/32
f(XIN
)
1/64
(f(XCIN) in low-speed mode)
1/128
1/256
atch
Synchronous clock
selection bit
te)
“1”
P6
3
/SCLK22
Synchronous circuit
“0”
External clock
P62 latch
“0”
P6
P6
2
1
/SCLK21
/SOUT2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
(Note)
“1”
P61
latch
“0”
“1”
Serial I/O2 port selection bit
Serial I/O shift register 2 (8)
P60/SIN2
Note: It is selected by the synchronous clock selection bit, the synchronous
clock output pin selection bit, and the serial I/O port selection bit.
Fig. 29 Block diagram of serial I/O2 function
32
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output
SOUT2
D2
D0
D1
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Seril I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be stting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes ance after transfer completion.
When the external clock is selected as the transfer clock, a content of the register is continued to shift
during inputting a transfer clock. The SOUT2 pin does not go to high imperansfer completion.
Fig. 30 Timing of serial I/O2 function
33
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PULSE WIDTH MODULATION (PWM)
The 7513 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input XIN or that clock input di-
vided by 2.
PWM Operation
When at least either bit 1 (PWM0 output enable bit) or bit 2 (PWM1
output enable bit) of the PWM control register is set to “1”, opera-
tion starts by initializing the PWM output circuit, and pulses are
output starting at an “H”. When one PWM output is enabled and
that the other PWM output is enabled, PWM output which is en-
abled to output later starts pulse output from halfway.
Data Setting
The PWM output pin also functions as ports P50 and P51. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an “H” by the PWM register.
If PWM count source is f(XIN) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
PWM period = 255 ꢀ (n+1)/f(XIN)
= 51 ꢀ (n+1) µs (when f(XIN) = 5 MHz)
51 ꢀ m ꢀ (n+1)
µs
Output pulse “H” period = PWM period ꢀ m/255
= 0.2 ꢀ (n+1) ꢀ m µs
255
(when f(XIN) = 5 MHz)
PWM output
T = [51 ꢀ (n+1)] µs
nts of PWM register
ntents of PWM prescaler
PWM cycle (when f(XIN) = 5 MHz)
Timing of PWM cycle
Data bus
PWM
register pre-latch
ph
PWM1 enable bit
Transfer control circuit
PWM
prescaler latch
PWM
register latch
Port P5
1
0
Count source
selection bit
“0”
PWM prescaler
PWM circuit
XIN
Port P5
“1”
1/2
PWM0 enable bit
Fig. 32 Block diagram of PWM function
34
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
b7
PWM control register
(PWMCON : address 002B16
)
Count source selection bit
0: f(XIN
)
1: f(XIN)/2
PWM
0: PWM
1: PWM
0
function enable bit
0
disabled
enabled
0
PWM1 function enable bit
0: PWM
1: PWM
1
disabled
enabled
1
Not used (return “0” when read)
Fig. 33 Structure of PWM control register
C
T2
B
T
=
C
A
B
PWM
(internal)
stop
Port
stop
T2
T
Port
PWM
PWM
0
1
output
output
Port
Port
PWM register
write signal
(Changes from “A” to “B” during “H” period)
PWM prescaler
write signal
(Changes from “T” to “T2” during PWM period)
PWM
0 function
enable bit
PWM
1 function
enable bit
When the contents of the PWM register or PWM prescaler have changed, the PWM
output will change from the next period after the change.
Fig. 34 PWM output timing when PWM register or PWM prescaler is changed
35
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
003216, 003316
The A-D conversion registers are read-only registers that contain
the result of an A-D conversion. During A-D conversion, do not
read these registers.
b7
b0
A-D control register
(ADCON : address 003116)
Analog input pin selection bits
0 0 0 : P60/SIN2/AN0
0 0 1 : P61/SOUT2/AN1
0 1 0 : P62/SCLK21/AN2
0 1 1 : P63/SCLK22/AN3
1 0 0 : P64/AN4
1 0 1 : P65/AN5
1 1 0 : P66/AN6
1 1 1 : P67/AN7
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
VREF input switch bit
0 : OFF
[A-D Control Register (ADCON)] 003116
The A-D control register controls the A-D conversion process. Bits
0 to 2 are analog input pin selection bits. Bit 3 is an A-D conver-
sion completion bit and “0” during A-D conversion, then changes
to “1” when the A-D conversion is completed. Writing “0” to this bit
starts the A-D conversion. Bit 4 controls the transistor which
breaks the through current of the resistor ladder. When bit 5,
which is the AD external trigger valid bit, is set to “1”, A-D conver-
sion is started even by a rising edge or falling edge of an ADT
input. Set ports which share with ADT pin to input when using an
A-D external trigger.
1 : ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
terrupt source selection bit
0 : Interrupt request at A-D
conversion completed
1 : Interrupt request at ADT
input rising or falling
Reference voltage input selection bit
0 : VREF
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
1 : P56/DA1
AVSS and VREF, and outputs the divided voltages.
-bit read (Read only address 003216.)
b0
b7
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
ersion register (low-order)
(ADL: Address 003216)
b9 b8 b7 b6 b5 b4 b3 b2
AN0, and inputs it to the comparator.
•10-bit read (Read address 003316 first.)
b0
b7
A-D conversion register (high-order)
(ADH: Address 003316)
[Comparator and Control Circuit]
b9 b8
The comparator and control circuit compares an analog i
age with the comparison voltage and stores the resu
conversion register. When an A-D conversion is the
control circuit sets the AD conversion complethe AD
interrupt request bit to “1”.
b0
b7
A-D conversion register (low-order)
(ADL: Address 003216)
b7 b6 b5 b4 b3 b2 b1 b0
Note: High-order 6 bits of address 003316 becomes “0” at reading.
Note that the comparator is constructed capacitor, so
set f(XIN) to at least 500 kHz during An.
Fig. 35 Structure of A-D control register
Use a clock divided the main clock nternal clock φ.
Data bus
b0
b7
A-D control register
P40/ADT
3
A-D control register
ADT/A-D interrupt request
P6
0
/SIN2/AN
0
1
2
3
4
5
6
7
P61/SOUT2/AN
(L)
(H)
P6
P6
2
/SCLK21/AN
Comparater
A-D conversion register A-D conversion register
3/SCLK22/AN
10
P6
P6
P6
P6
4
5
6
7
/AN
/AN
/AN
/AN
Resistor ladder
AVSS
V
REF
P56/DA1
Fig. 36 A-D converter block diagram
36
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER
The 7513 group has an on-chip D-A converter with 8-bit resolution
and 2 channels (DAi (i=1, 2)). The D-A converter is performed by
setting the value in the D-A conversion register. The result of D-A
converter is output from DAi pin. When using the D-A converter,
the corresponding port direction register bit (P56/DA1, P57/DA2)
should be set to “0” (input status).
b7
b0
D-A control register
(DACON : address 003616)
DA1 output enable bit/DA1 VREF
ON/OFF switch
DA2 output enable bit/DA2 VREF
ON/OFF switch
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
Not used (return “0” when read)
0 : Output disabled/OFF
1 : Output enabled/ON
V=VREF ꢀ n/256 (n=0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion registers are cleared to “0016”, the
DAi output enable bits are cleared to “0”, and DAi pin goes to
high impedance state. The DA output is not buffered, so connect
an external buffer when driving a low-impedance load.
Fig. 37 Structure of D-A rol register
Data bus
D-A1 conversion register
(DA1: address 003416
D-A2 conversion register
(DA2: address 003516
)
)
D-A i conversion register (8)
DA i output enable bit
R-2R resistor ladder
P5
6
/DA
/DA
1
2
P57
Fig. 38 Block diagram of D-A converter
Internal: D-A output
External: VREF
Reference voltaswitch
VREF
A-D conversion register
Resistor ladder
(10 bits)
VREF input
ON/OFF switch
D-A1 output enable switch
D-A1 VREF ON/OFF switch
D-A1 output
(P56)
D-A1 conversion register (8 bits)
R-2R resistor ladder
D-A2 output enable switch
D-A2 VREF ON/OFF switch
D-A2 output
R-2R resistor ladder
(P57)
D-A2 conversion register (8 bits)
Fig. 39 A-D converter, D-A converter block diagram
37
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Up to 160 pixels can be controlled for LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 7513 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
ꢀLCD display RAM
ꢀSegment output enable register
ꢀLCD mode register
ꢀVoltage multiplier
Table 9 Maximum number of display pixels at each duty ratio
ꢀSelector
Duty ratio
2
Maximum number of display pixel
80 dots
ꢀTiming controller
ꢀCommon driver
or 8 segment LCD 10 digits
120 dots
ꢀSegment driver
ꢀBias control circuit
3
4
or 8 segment LCD 15 digits
160 dots
A maximum of 40 segment output pins and 4 common output pins
can be used.
or 8 segment LCD 20 digits
b7
b0
Segment output enable register
(SEG : address 003816
)
Segment output enable bit
0 : Output ports P3 –
0
1 : Segment output
Segment output en
0 : Output por
1 : Segmen,SEG25
Segment o2
0 : I/O
1 : SEG26–SEG31
Segable bit 3
06,P07
t output SEG32,SEG33
utput enable bit 4
port P1
0
Segment output SEG34
gment output enable bit 5
0 : I/O ports P11–P15
1 : Segment output SEG35–SEG39
LCD output enable bit
0 : Disable
1 : Enable
Not used (return “0” when read)
(Do not write “1” to this bit)
b7
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 duty (use COM
1 0 : 3 duty (use COM
1 1 : 4 duty (use COM
Bias control bit
0 : 1/3 bias
0
0
0
, COM
–COM
–COM
1
2
3
)
)
)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Voltage multiplier control bit
0 : Voltage multiplier disabled
1 : Voltage multiplier enabled
LCD circuit divider division ratio selection bits
0 0 : 1 division of clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode)
Note : LCDCK is a clock for a LCD timing controller.
Fig. 40 Structure of LCD mode register
38
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 41 Block diagram of LCD controller/driver
39
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Voltage Multiplier (3 Times)
Bias Control and Applied Voltage to LCD
Power Input Pins
The voltage multiplier performs threefold boosting. This circuit in-
puts a reference voltage for boosting from LCD power input pin
VL1. (However, when using a 1/2 bias, connect VL1 and VL2 and
apply voltage by external resistor division.)
To the LCD power input pins (VL1–VL3), apply the voltage shown
in Table 10 according to the bias value.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Set each bit of the segment output enable register and the LCD
mode register in the following order for operating the voltage mul-
tiplier.
Table 10 Bias control and applied voltage to VL1–VL3
1. Set the segment output enable bits (bits 0 to 5) of the seg-
ment output enable register to “0” or “1.”
Bias value
Voltage value
VL3=VLCD
2. Set the duty ratio selection bits (bits 0 and 1), the bias con-
trol bit (bit 2), the LCD circuit divider division ratio selection
bits (bits 5 and 6), and the LCDCK count source selection
bit (bit 7) of the LCD mode register to “0” or “1.”
3. Set the LCD output enable bit (bit 6) of the segment output
enable register to “1.”
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
1/2 bias
VL2=VL1=1/2 VLCD
Note: VLCD is the maximum vf supplied voltage for the LCD panel.
4. Set the voltage multiplier control bit (bit 4) of the LCD mode
register to “1.”
When voltage is input to the VL1 pin during operating the voltage
multiplier, voltage that is twice as large as VL1 occurs at the VL2
pin, and voltage that is three times as large as VL1 occurs at the
VL3 pin.
When using the voltage multiplier, apply 1.3 V ≤ Voltage ≤ 2.3 V to
the VL1 pin.
When not using the voltage multiplier,apply proper voltage to the
LCD power input pins (VL1–VL3). Then set the LCD output enable
bit to “1.”
When the LCD output enable bit is set to “0,” the VCC volt
applied to the VL3 pin inside of this microcomputer.
The voltage multiplier control bit (bit 4 of the LCD m
controls the voltage multiplier.
Contrast control
Contrast control
VCC
VCC
V
L3
L2
V
L3
L2
V
L3
R1
R2
R4
V
V
V
L2
2
C
C
2
1
C
C
2
1
Open
Open
C
Open
Open
C
V
1
VL1
VL1
L1
R3
R5
PX
X
R1=R2=R3
R4=R5
1/3 bias
1/3 bias
when not using the voltage multiplier
1/2 bias
when using the voltage multiplier
Fig. 42 Example of circuit at each bias
40
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ment/output port pins are the high impedance condition. The seg-
ment/I/O port pins(SEG26–SEG33). are set to input ports, and the
high impedance condition.The segment/I/O port pins(SEG34–
SEG39). are set to input ports, and VCC (=VL3) is applied to them
by pull-up resistor.
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
When releasing from reset, the VCC (VL3) voltage is output from
the common pins.
LCD Display RAM
Address 004016 to 005316 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
Table 11 Duty ratio control and common pins used
Duty ratio selection bit
Duty
Common pins used
ratio
Bit 1
Bit 0
LCD Drive Timing
2
3
4
0
1
1
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
Notes1: COM2 and COM3 are open.
2: COM3 is open.
(frequeount source for LCDCK)
f(LCDCK) =
sion ratio for LCD)
LCDCK)
Segment Signal Output Pin
Frame fre
(duty ratio)
Segment signal output pins are classified into the segment-only
pins (SEG0–SEG17), the segment/output port pins (SEG18–
SEG25), and the segment/I/O port pins (SEG26–SEG39).
Segment signals are output according to the bit data of the LCD
RAM corresponding to the duty ratio. After reset release, a VCC
(=VL3) voltage is output to the segment-only pins and the seg-
Bit
7
4
3
2
1
0
address
004016
004116
00421
00
6
SEG
SEG
SEG
SEG
SEG
0
2
4
6
8
3
5
7
9
EG
SEG
SEG
SEG
SEG10
SEG11
SEG13
SEG15
SEG17
SEG19
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
005016
005116
005216
005316
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
SEG33
SEG35
SEG37
SEG39
SEG30
SEG32
SEG34
SEG36
SEG38
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM0
Fig. 43 LCD display RAM map
41
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
OFF
ON
COM
3
COM
COM
2
COM
1
COM
0
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
Fig. 44 LCD drive waveform (1/2 bias)
42
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Internal signal
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
VSL1S
COM
0
COM
COM
COM
1
2
3
VL3
SEG
0
VSS
OFF
ON
ON
COM
3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
VL3
SEG
0
VSS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 45 LCD drive waveform (1/3 bias)
43
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ꢀvalue of high-order 6-bit counter
WATCHDOG TIMER
ꢀvalue of STP instruction disable bit
ꢀvalue of count source selection bit.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runaway).
When bit 6 of the watchdog timer control register (address 003716)
is set to “0,” the STP instruction is valid. The STP instruction is
disabled by rewriting this bit to “1.” At this time, if the STP instruc-
tion is executed, it is processed as an undefined instruction, so
that a reset occurs inside.
The watchdog timer consists of an 8-bit watchdog timer L and a 6-
bit watchdog timer H. At reset or writing to the watchdog timer
control register (address 003716), the watchdog timer is set to
“3FFF16.” When any data is not written to the watchdog timer con-
trol register (address 003716) after reset, the watchdog timer is in
stop state. The watchdog timer starts to count down from “3FFF16”
by writing an optional value into the watchdog timer control regis-
ter (address 003716) and an internal reset occurs at an underflow.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register (address 003716) may be
started before an underflow. The watchdog timer does not function
when an optional value has not been written to the watchdog timer
control register (address 003716). When address 003716 is read,
the following values are read:
This bit cannot be rewritten to “0” by programming. This bit is “0”
immediately after reset.
The count source of the watchdog timer becomes the system
clock φ divided by 8. The detection time in this case is set to 8.19 s
at f(XCIN) = 32 kHz and 65.536 ms at f(XIN) = 4 MHz.
However, count source of high-order 6-bit timer can be connected
to a signal divided system k by 8 directly by writing the bit 7 of
the watchdog timer coer (address 003716) to “1.” The
detection time in thito 32 ms at f(XCIN) = 32 kHz and
256 µs at f(XIN) ere is no difference in the detection
time between peed mode and the high-speed mode.
“FF16” is set when
watchdog timer is
Data bus
X
CIN
Watchdo
source
“0”
written to.
Watchdog timer
L (8)
“1”
“0”
Internal
system clock
selection bit
Watchdog timer
1/16
H (6)
“3F16” is set when
watchdog timer is
written to.
X
IN
Undefined instructio
R
STP instruction disable bit
STP instruction
Internal reset
Reset circuit
RESETIN
Reset release time wait
Fig. 46 Block diagram of watchdog
b7
b0
Watchdog timer register (address 003716
)
WDTCON
Watchdog timer H (for read-out of high-order 6 bit)
“3FFF16” is set to the watchdog timer by writing values to this address.
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selecion bit
0 : Internal system clock/2048 (f(XIN)/4096)
1 : Internal system clock/8 (f(XIN)/16)
Fig. 47 Structure of watchdog timer control register
f(XIN
)
2
ms (f(XIN) = 4 MHZ)
Internal
reset signal
Watchdog timer detection
Fig. 48 Timing of reset output
44
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TOUT/φ CLOCK OUTPUT FUNCTION
The internal system clock φ or timer 2 divided by 2 (TOUT output)
can be output from port P43 by setting the TOUT/φ output control
bit (bit 1) of the timer 123 mode register and the TOUT/φ output
control register. Set bit 3 of the port P4 direction register to “1”
when outputting the clock.
b7
b0
TOUT/φ output control register
(CKOUT : address 002A16)
TOUT/φ output control bit
0 : φ clock output
1 : TOUT output
Not used (return “0” when read)
b7
b0
Timer 123 mode register
(T123M : address 002916
TOUT output activbit
0 : Start on
1 : Start
TOUT/φ o
0 : Tsable
1 enable
Tntrol bit
ta in latch and timer
data in latch only
count source selection bit
Timer 1 output
: f(XIN)/16
(or f(XCIN)/16 in low-speed mode✽)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✽)
Timer 1 count source selection bit
0 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode✽)
1 : f(XCIN)
Not used (return “0” when read)
ernal clock φ is f(XCIN)/2 in low-speed mode.
Fig. 49 Structure of TOUT/f output-related register
45
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
RESET CIRCUIT
Poweron
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the oscillation should be stable), reset is released. After
the reset is completed, the program starts from the address con-
tained in address FFFD16 (high-order byte) and address FFFC16
(low-order byte). Make sure that the reset input voltage is less
than 0.2 VCC for VCC of VCC (min.).
(Note)
Power source
voltage
RESET
VCC
0V
Reset input
voltage
0V
0.2VCC
Note : Reset release voltage ; VCC=VCC(min.)
RESET
VCC
Power source
voltage detection
circuit
Fig. ircuit Example
XIN
φ
RESET
Internal
reset
Reset address from
vector table
Address
Data
?
?
?
?
FFFC
FFFD
ADH, ADL
ADL
ADH
SYNC
XIN : about 8200 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that
depends on the previous state.
Fig. 51 Reset Sequence
46
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Address Register contents
Address Register contents
(1) Port P0 direction register
(2) Port P1 direction register
(3) Port P2 direction register
(4) Port P3 output control register
(5) Port P4 direction register
(6) Port P5 direction register
(7) Port P6 direction register
(8) Port P7 direction register
(9) Key input control register
(10) PULL register A
000116
000316
000516
000716
000916
000B16
000D16
000F16
001516
001616
001716
001916
001A16
001B16
001D16
002016
002116
002216
002316
002416
00
2816
002916
002A16
002B16
0016
003116
003216
003316
003416
003516
003616
003716
003816
003916
A16
003B16
003C16
003D16
003E16
003F16
(28) A-D control register
0816
0016
(29) A-D conversion register
(low-order)
(30) A-D conversion register
(high-order)
(31) D-A1 conversion register
(32) D-A2 conversion register
(33) D-A control register
XX16
0016
XX16
0016
0016
0016
0016
0016
0016
0 0 1 1 1 1 1 1
0016
(34) Watchdog timer control register
(35) Segment output enable register
(36) LCD mode register
0016
0016
0016
0016
3F16
(37) Interrupt edge selecti
(38) CPU mode regis
0016
0 1 0 0 1 0 0 0
(11) PULL register B
0016
1 0 0 0 0 0 0 0
(12) Serial I/O1 status register
(13) Serial I/O1 control register
(14) UART control register
(15) Serial I/O2 control register
(16) Timer X (low-order)
(17) Timer X (high-order)
(18) Timer Y (low-order)
(19) Timer Y (high-order)
(20) Timer 1
(39) Interrupt re1
(40) Interrister 2
(41) l register 1
ontrol register 2
essor status register
Program counter
0016
0016
0016
0016
0016
1 1 1 0 0 0 0 0
0016
FF16
FF16
FF1
6
FF16
0016
0016
0016
0016
0016
1
(PS) ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ
Contents of address FFFD16
(PCH)
Contents of address FFFC16
(PCL)
(45) Watchdog timer (high-order)
(46) Watchdog timer (low-order)
3F16
FF16
(21) Timer 2
(22) Timer 3
(23) Timer X mode register
(24) Timer Y mode register
(25) Timer 123 mode register
(26) TOUT/φ output control register
(27) PWM control register
Note: The contents of all other register and RAM are undefined after reset, so they must be initialized by software.
ꢀ : Undefined
Fig. 52 Initial status at reset
47
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Oscillation Control
The 7513 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer’s recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. The value set to the
timer latch 1 and the timer latch 2 is loaded automatically to the
timer 1 and the timer 2. Thus, a value generated time for stabiliz-
ing oscillation should be set to the timer 1 latch and the timer 2
latch (low-order 8 bits for the timer 1, high-order 8 bits for the timer
2) before executing the STP instruction.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins go to high impedance state.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0,” Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock φ is
not supplied to the CPU umer 2 underflows. This allows timer
for the clock circuit oscabilize.
Frequency Control
(1) Middle-speed Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) Wait Mo
If the WIT inxecuted, the internal clock φ stops at an
“H” level. XIN and XCIN are the same as the state be-
fore ththe WIT instruction. The internal clock restarts
at ran interrupt is received. Since the oscillator does
rmal operation can be started immediately after the
estarted.
(2) High-speed Mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed Mode
ꢀThe internal clock φ is half the frequency of XCIN.
ꢀA low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bi
of the CPU mode register to “1”.
When the main clock XIN is restarted, set enough time
lation to stabilize by programming.
Note: If you switch the mode between middle/high-ow-
speed, stabilize both XIN and XCIN s. The
sufficient time is required for the subbilize, es-
pecially immediately after powerturning from
stop mode. When switching the en middle/high-
speed and low-speed, set ty on condition that
f(XIN)>3f(XCIN).
X
CIN
X
COUT
X
IN
XOUT
Rf
Rd
C
OUT
CCOUT
CIN
C
CIN
Fig. 53 Ceramic resonator circuit
XCIN
XCOUT
XIN
XOUT
Rf
Open
Rd
External oscillation
circuit
CCOUT
CCIN
VCC
VSS
Fig. 54 External clock input circuit
48
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
XCIN
X
COUT
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
X
IN
Internal system clock selection bit
XOUT
(Note)
Low-speed mode
“1”
“0”
“0”
Timer 1
Timer 2
1/2
1/2
1/4
“1”
“0”
“1”
Middle-/High-speed mode
Main clock division rat
Middle-speed mod
“1”
Timing φ
(Internal clock)
“0”
High-speed mode
or Low-speed mode
Main clock stop bit
Q
S
R
R
S
R
Q
STP instruction
STP instruction
Reset
Interrupt disable flag
I
Interrupt request
Note: When selecting the X
C
oscillation, set the port XC switch bit to “1” .
Fig. 55 Clock generating circuit block diagram
49
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset
CM
6
Middle-speed mode (f(φ) =1 MHz)
High-speed mode (f(φ) =4 MHz)
CM
CM
CM
CM
7
6
5
4
=0(8MHz selected)
=1(Middle-speed)
=0(8MHz oscillating)
=0(32kHz stoped)
“1”
“0”
CM
CM
CM
CM
7
6
5
4
=0(8MHz selected)
=0(High-speed)
=0(8MHz oscillating)
=0(32kHz stoped)
C
M
“
4
”
0
0
”
C
“
M
M4
“
1
6
”
”
0
C
“
“
”
1
M6
1
”
“
C
“
0
”
”
1
“
CM
6
Middle-speed mode (f(φ) =1 MHz)
High-speed mode (f(φ) =4 MHz)
CM
CM
CM
CM
7
6
5
4
=0(8MHz selected)
=1(Middle-speed)
=0(8MHz oscillating)
=1(32kHz oscillating)
“1”
“0”
CM
CM
CM
CM
7
6
5
4
=0(8MHz selected)
=0(High-speed)
=0(8MHz oscillating)
=1(32kHz oscillating)
CM
6
Low-speed mode (f(φ) =16 kHz)
(f(φ) =16 kHz)
CM
CM
CM
CM
7
6
5
4
=1(32kHz selected)
=1(Middle-speed)
=0(8MHz oscillating)
=1(32kHz oscillating)
“1”
“0”
z selected)
h-speed)
8MHz oscillating)
1(32kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Sub-clock (XCIN–XCOUT) stop bit
0: Stopped
1: Oscillating
”
0
“
M5
“
1
C
”
”
5
: Main clock (XIN–XOUT) stop bit
M6
1
“
“
0
C
0: Oscillating
1: Stopped
”
”
1
“
6
: Main clock division ratio selection bit
Low-power dissipation
mode (f(φ) =16 kHz)
Low-power dissipation
mode (f(φ) =16 kHz)
CM
“1”
6
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
“0”
CM
CM
CM
CM
7
6
5
4
=1(32kHz selected)
CM
CM
CM
CM
7
6
5
4
=1(32kHz selected)
=0(High-speed)
=1(8MHz stopped)
=1(32kHz oscillating)
7
: Internal system clock selection bit
=1(Middle-speed)
=1(8MHz stopped)
0: XIN–XOUT selected
=1(32kHz oscillating)
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, wait time can be set by connecting timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 56 State transitions of system clock
50
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed.
In serial I/O2, the SOUT2 pin goes to high impedance state after
transmission is completed.
Interrupt
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz during an A-D conver-
Decimal Calculations
sion.
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
Do not execute the STP oinstruction during an A-D conver-
sion.
Instruction n Time
The instructitime is obtained by multiplying the fre-
quency of clock φ by the number of cycles needed to
executon.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
The ycles required to execute an instruction is shown
imachine instructions.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
ency of the internal clock φ is half of the XIN frequency.
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do
the MUL and DIV instruction.
The execution of these instructions does not channts
of the processor status register.
Ports
The contents of the port direction regibe read.
The following cannot be used:
• The data transfer instruction (
• The operation instruction when tex X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
51
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a
general-purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
(1) Mask ROM Order Confirmation Form
(2) Mark Specification Form
(3) Data to be written to ROM, in EPROM form (three identical
copies) or in one floppy disk
Table 12 Special programming adapter
Package
100PFB-A
100P6Q-A
100D0
Name of Programming Adapter
PCA4738H-100A
PCA4738G-100A
PCA4738L-100A
The PROM of the blank Ome PROM version is not tested or
screened in the assemand following processes. To en-
sure proper operatiramming, the procedure shown in
Figure 57 is recoverify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 57 Programming and testing of One Time PROM version
52
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Table 13 Absolute maximum ratings
Symbol
VCC
Parameter
Power source voltage
Conditions
Ratings
Unit
V
–0.3 to 7.0
VI
Input voltage P00–P07, P10–P17, P20–P27,
P41–P47, P50–P57, P60–P67
–0.3 to VCC +0.3
V
VI
VI
VI
VI
VI
VI
VI
VO
–0.3 to 7.0
–0.3 to VCC +0.3
–0.3 to VL2
V
V
V
V
V
V
V
V
V
V
Input voltage P40, P71–P77
Input voltage P70
All voltages are based on VSS.
Output transistors are cut off.
Input voltage VL1
VL1 to VL3
Input voltage VL2
VL2 to 7.0
Input voltage VL3
–0.3 to 7.0
Input voltage C1, C2
Input voltage RESET, XIN
Output voltage C1, C2
–0.3 to VCC +0.3
–0.3 to 7.0
–0.3 to VCC
–0.3 to VL3
At output port
VO
Output voltage P00–P07, P10–P15, P30–P37
At segment output
Output voltage P16, P17, P20–P27, P41–P47,
P50–P57, P60–P67
–0.3 to VCC +0.3
V
VO
VO
Output voltage P40, P71–P77
Output voltage VL3, SEG0–SEG17,COM0–COM3
Output voltage VL2
–0.3 to 7.0
–0.3 to 7.0
–0.3 to VL3
–0.3 to VCC +0.3
300
V
V
VO
VO
V
VO
Output voltage XOUT
V
Pd
Ta =
Power dissipation
Operating temperature
mW
°C
°C
–20 to 85
Topr
Tstg
–40 to 125
RECOMMENDED OPERATING CONDITI
Table 14 Recommended operating conditions (V.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
5.0
Symbol
eter
Unit
V
Min.
4.0
2.2
2.2
Max.
5.5
speed mode f(XIN) = 8 MHz
ddle-speed mode f(XIN) = 8 MHz
Low-speed mode
VCC
Power source voltage
Power source vo
5.0
5.5
5.0
5.5
VSS
0
V
V
V
V
VREF
AVSS
VIA
A-D, D-A conversience voltage
Analog power source oltage
2.7
VCC+0.3
0
Analog input voltage AN0–AN7
AVSS
VCC
VCC
“H” input voltage
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
VIH
VIH
0.7 VCC
V
V
“H” input voltage
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
0.8 VCC
VCC
VIH
VIH
“H” input voltage
“H” input voltage
“L” input voltage
RESET
XIN
0.8 VCC
0.8 VCC
VCC
VCC
V
V
P00–P07, P10–P17, P40, P43, P45, P47, P50–P53,
P56, P61, P64–P67, P71–P77
VIL
VIL
V
V
0
0
0.3 VCC
0.2 VCC
“L” input voltage
P20–P27, P41, P42, P44, P46, P54, P55, P57, P60,
P62, P63, P70
VIL
VIL
“L” input voltage
“L” input voltage
0
0
0.2 VCC
0.2 VCC
V
V
RESET
XIN
53
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 15 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–20
–20
20
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
20
80
–10
–10
10
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37 (Note 1)
P41–P47, P50–P57, P60–P67 (Note 1)
P40, P71–P77 (Note 1)
10
40
–1.0
P00–P07, P10–P15, P30–P37 (Note 2)
“H” peak output current
P16, P17, P20–P27, P41–P47, P50–P57, P60–P67
(Note 2)
IOH(peak)
IOL(peak)
IOL(peak)
–5.0
mA
mA
“L” peak output current
“L” peak output current
5.0
P00–P07, P10–P15, P30–P37 (Note 2)
P16, P17, P20–P27, P41–P47, P50–P57,
(Note 2)
10
mA
“L” peak output current
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
20
mA
mA
mA
mA
P40, P71–P77 (Note 2)
“H” average output current
“H” average output current
“L” average output current
–0.5
–2.5
2.5
P00–P07, P10–P15, P30–P37 (N
P16, P17, P20–P27, P41–P4P60–P67
P00–P07, P10–P15, P30–)
“L” average output current
P16, P17, P20–P27, P–P57, P60–P67
(Note 3)
IOL(avg)
IOL(avg)
5.0
10
mA
mA
“L” average output current
P40, P71–P77 (
Notes1: The total output current is the sum of all the currents flowing tapplicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of al
2: The peak output current is the peak current flowing in e
3: The average output current is an average value meams.
54
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 16 Recommended operating conditions (VCC = 2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
(4.0 V ≤ VCC ≤ 5.5 V)
Unit
MHz
MHz
Min.
Max.
4.0
f(CNTR0)
f(CNTR1)
Input frequency for timers X and Y
(duty cycle 50%)
(10✕VCC
–4)/9
(2.2 V ≤ VCC ≤ 4.0 V)
High-speed mode
(4.0 V ≤ VCC ≤ 5.5 V)
8.0
MHz
Main clock input oscillation frequency
(Note 1)
f(XIN)
High-speed mode
(2.2 V ≤ VCC ≤ 4.0 V)
(20✕VCC
–8)/9
MHz
Middle-speed mode
8.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency (Notes 1, 2)
32.768
Notes1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
55
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 17 Electrical characteristics (VCC =4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –1 mA
Unit
Max.
Min.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P15, P30–P37
VOH
IOH = –0.25 mA
VCC = 2.2 V
VCC–0.8
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67 (Note 1)
IOH = –1.5 mA
VOH
VOL
VOL
IOH = –1.25 mA
VCC = 2.2 V
VCC–0.8
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P15, P30–P37
IOL = 1.5 mA
IOL = 1.25 mA
VCC = 2.2 V
0.8
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 3.0 mA
“L” output voltage
P16, P17, P20–P27, P41–P47, P50–P57,
P60–P67
IOL = 2.5 mA
VCC = 2.2 V
V
0.8
0.5
0.3
IOL = 10 mA
V
V
“L” output voltage
P40, P71–P77
VOL
IOL = 5 mA
VCC = 2.2 V
Hysteresis
VT+ – VT–
0.5
V
INT0–INT2, ADT, CNTR0, CNTR1, P20–P27
Hysteresis
SCLK, RXD
RESET
0.5
0.5
VT+ – VT–
VT+ – VT–
V
V
Hysteresis
“H” input current
P00–P07, P10–P17, P20–P27, P40–P47,
P50–P57, P60–P67, P70–P77
IIH
5.0
5.0
µA
VI =
µA
µA
IIH
IIH
“H” input current RESET
“H” input current XIN
C
4.0
VSS
ll-ups “off”
–5.0
–240.0
–40.0
µA
µA
µA
“L” input current
VCC = 5 V, VI = VSS
Pull-ups “on”
P10–P17, P20–P27,P40–P47,
IIL
–60.0
–5.0
–120.0
–20.0
P50–P57, P60–P67, P70–P
VCC = 2.2 V, VI = VSS
Pull-ups “on”
µA
µA
µA
“L” input current P0
“L” input current
“L” input current
–5.0
–5.0
IIL
IIL
IIL
VI = VSS
VI = VSS
–4.0
VO = VCC
Output transistors “off”
µA
µA
5.0
Output load current
P30–P37
ILEAK
VO = VSS
Output transistors “off”
–5.0
56
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 18 Electrical characteristics (VCC =2.2 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
V
Min.
2.0
Max.
5.5
VRAM
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
6.4
1.6
13
mA
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
3.2
Output transistors “off”
A-D converter in operating
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
35
20
70
40
µA
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta = 25°
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT sta
Output transistors “off”
• Low-speed mode, VCC = C
f(XIN) = stopped
15.0
22.0
9.0
f(XCIN) = 32.768 k
Output transist
• Low-speed 3 V, Ta ≤ 25°C
f(XIN) =
4.5
0.1
µA
µA
f(XCIHz (in WIT state)
Otors “off”
n stopped
ate)
transistors “off”
Ta = 25 °C
Ta = 85 °C
1.0
10.0
Power source voltage
Power source cu
1.8
3.0
VL1
IL1
en using voltage multiplier
VL1 = 1.8 V
2.3
6.0
V
1.3
µA
(VL1)
10.0
VL1 < 1.3 V
50.0
Note: When the voltage multiplier controof the LCD mode register (bit 4 at address 003916) is “1”.
57
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 19 A-D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, 4 MHz ≤ f(XIN) ≤ 8 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
10
–
–
Resolution
Bits
LSB
LSB
Absolute accuracy
(excluding quantization error)
VCC = VREF = 4 V
±2.5
±4.0
VCC = VREF = 2.7 V (Note 2)
31
(Note 1)
tCONV
Conversion time
f(XIN) = 4 MHz
30.5
50
µs
RLADDER
IVREF
IIA
Ladder resistor
35
150
0.5
kΩ
µA
µA
200
5.0
Reference power source input current
Analog port input current
VREF = 5 V
Notes1: When an internal trigger is used in middle-speed mode, it is 34 ms.
2: 4 MHz ≤ f(XIN) ≤ 5.1 MHz in high-speed mode.
Table 20 D-A converter characteristics
(VCC = 2.7 to 5.5 V, VCC = VREF, VSS = AVSS = 0 V, Ta = –20 to 85°C, in middle/high-speed motherwise noted)
Limits
Symbol
Parameter
Test condition
Unit
Min.
Typ.
Max.
8
–
–
Bits
%
Resolution
1.0
2.0
VCC = VREF = 5
Absolute accuracy
VCC = VREF
%
Setting time
µs
tsu
3
Output resistor
1
4
kΩ
mA
RO
2.5
(N
IVREF
Reference power source input current
6.0
Note: Using one D-A converter, with the value in the D-A conversion regier D-A converter being “0016”, and excluding currents flowing through
the A-D resistance ladder.
58
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 21 Timing requirements 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
125
45
twH(XIN)
twL(XIN)
Main clock input “L” pulse width
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
CNTR0, CNTR1 input cycle time
250
105
105
80
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT2 input “H” pulse width
INT0 to INT2 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
80
tc(SCLK1)
twH(SCLK1)
twL(SCLK1)
800
370
370
20
100
1000
400
400
200
200
t
su(RXD–SCLK1)
th(SCLK1–RXD) Serial I/O1 input hold time
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
t
su(SIN2–SCLK2)
th(SCLK2–SIN2) Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
Table 22 Timing requirements 2 (VCC = 2.2 to 4.0 V, VSS = 0 to 85°C, unless otherwise noted)
Limits
Symbol
Para
Unit
Min.
Typ.
Max.
tw(RESET)
tc(XIN)
2
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
125
Main clock input cycle time (XIN in
Main clock input “H” pulse wid
Main clock input “L” pulse
twH(XIN)
twL(XIN)
45
40
900/(VCC–0.4)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK1)
CNTR0, CNTR1 input c
CNTR0, CNTR1 inpuidth
CNTR0, CNTR1 ie width
INT0 to INT2 input e width
INT0 to INT2 input “Lulse width
Serial I/O1 clock input cycle time (Note)
230
2000
twH(SCLK1)
twL(SCLK1)
950
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
ns
ns
950
t
su(R
X
D–SCLK1
)
Serial I/O1 input set up time
400
ns
ns
ns
ns
ns
ns
ns
th(SCLK1–RXD) Serial I/O1 input hold time
200
tc(SCLK2)
Serial I/O2 clock input cycle time (Note)
2000
twH(SCLK2)
twL(SCLK2)
Serial I/O2 clock input “H” pulse width (Note)
Serial I/O2 clock input “L” pulse width (Note)
Serial I/O2 input set up time
950
950
t
su(SIN2–SCLK2
)
400
th(SCLK2–SIN2) Serial I/O2 input hold time
300
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A16 is “0”.
59
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 23 Switching characteristics 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
140
tC (SCLK1)/2–30
tC (SCLK1)/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
td(SCLK1–TXD) Serial I/O1 output delay time (Note 1)
tv(SCLK1–TXD) Serial I/O1 output valid time (Note 1)
–30
tr(SCLK1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
30
30
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
C
(SCLK2)/2–160
t
C (SCLK2)/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
40
30
30
10
10
Notes1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 00
2: XOUT and XCOUT pins are excluded.
Table 24 Switching characteristics 2 (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to s otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
350
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse wid
Serial I/O2 clock output “L” pulse
Serial I/O2 output delay time
tC (SCLK1)/2–50
tC (SCLK1)/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(SCLK1)
twL(SCLK1)
td(SCLK1–TXD)
tv(SCLK1–TXD)
tr(SCLK1)
–30
50
50
tf(SCLK1)
twH(SCLK2)
twL(SCLK2)
t
C
(SCLK2)/2–240
t
C (SCLK2)/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
0.2 ✕ t
C
(SCLK2
)
Serial I/O2 output valid time
)
0
Serial I/O2 clock output
CMOS output rising
CMOS output falle 2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
50
50
50
20
20
Notes1: When the P45/TXD P-channisable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT and XCOUT pins are exclu
60
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Measurement output pin
1 kΩ
100 pF
Measurement output pin
100 pF
CMOS output
N-channel open-drain output (Note)
Note : When bit 4 of the UART
control register (address 001B16) is “1”.
(N-channel open-drain output mode)
Fig. 58 Circuit for measuring output switching characteristics
61
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
tC (CNTR)
tWL (CNTR)
tWH (CNTR)
CNTR0, CNTR1
0.8VCC
0.2VCC
tWL (INT)
tWH (INT)
INT0–INT3
0.8VCC
0.2VCC
tW (RESET)
RESET
0.2VCC
tC (X
tWL (XIN)
tWH (XIN)
0.8VCC
X
IN
0.2VCC
tC
(SCLK
)
tr
tWL (SCLK
)
tWH (SCLK)
0.8VCC
S
CLK
VCC
tsu (R
X
D-SCLK
)
th (SCLK-RXD)
0.8VCC
0.2VCC
RXD
t
d
(SCLK-T
X
D)
tv (SCLK-TXD)
TXD
Fig. 59 Timing diagram
62
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
MMP
100P6Q-A
Plastic 100pin 14✕14mm body LQFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
0.63
Lead Material
Cu Alloy
M
D
LQFP100-P-1414-0.50
HD
D
100
76
l2
Recommended Mount Pad
1
75
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A
1
0
0.1
–
1.4
0.13
0.105
13.9
13.9
–
0.18
0.125
14.0
14.0
0.5
0.28
0.175
14.1
14.1
–
25
51
H
H
L
D
15.8
15.8
0.3
–
0.45
–
–
–
0°
–
16.0
16.0
0.5
1.0
0.6
0.25
–
–
16.2
16.2
0.7
–
0.75
–
0.08
0.1
10°
–
26
50
E
A
L
1
L1
F
e
Lp
A3
x
y
–
b
x
y
L
M
b2
0.225
–
14.4
14.4
I
2
0.9
–
–
–
–
–
Lp
F
M
M
D
E
MMP
100PFB-A
Plastic 100pin 12✕12mm body TQFP
EIAJ Package Code
JEDEC Code
Lead Material
Cu Alloy
M
D
–
TQFP100-P-1212-0.40
HD
D
100
I
2
1
75
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.2
0.15
–
A
A
1
0.05
–
0.1
1.0
2
b
0.13
0.105
11.9
11.9
–
0.18
0.125
12.0
12.0
0.4
0.23
0.175
12.1
12.1
–
c
D
E
e
25
51
H
H
L
D
13.8
13.8
0.4
–
14.0
14.0
0.5
14.2
14.2
0.6
–
26
50
E
A
L1
1.0
L1
Lp
A3
x
0.45
–
–
–
0°
–
1.0
–
0.6
0.25
–
–
–
0.225
–
12.4
12.4
0.75
–
0.07
0.08
10°
–
–
–
–
e
F
y
b2
L
b
I
2
y
x
M
Detail F
Lp
M
M
D
E
–
63
MITSUBISHI MICROCOMPUTERS
7513 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
100D0
Glass seal 100pin QFN
EIAJ Package Code
JEDEC Code
Weight(g)
–
–
5.0MAX
3.5TYP
18.85±0.15
0.65TYP
0.45TYP
21.0±0.13
51
50
80
81
31
100
1
5TYP
INDEX
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
•
•
•
•
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved
destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 2001 MITSUBISHI ELECTRIC CORP.
New publication, effective Feb. 2001.
Specifications subject to change without notice.
64
REVISION HISTORY
7513 GROUP USER’S MANUAL
Rev.
Date
Description
Summary
Page
1.0
1.1
02/02/01
02/06/01
First edition issued.
4
Table 1: Function explanation of I/O port P0 and I/O port P1 is revised.
(1/1)
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