M38044F3SP [RENESAS]
8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES; 8位CISC单片机740系列/ 38000系列
| 型号： | M38044F3SP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT CISC SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 38000 SERIES |
| 文件： | 总387页 (文件大小：2846K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REJ09B0212-0100Z
3804 Group (Spec. H)
User’s Manual
8
RENESAS 8-BIT CISC SINGLHIP MICROCOMPUTER
40 FAMILY / 38000 SERIES
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.00
Revision date: Jan 14, 2005
www.renesas.com
Keep safety first in your circuit designs!
1.
Renesas Technology Corp. puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with ap-
propriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.
These materials are intended as a reference to assist our customers in the selection of the
Renesas Technology Corp. product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Renesas Technology Corp. or a third party.
2.
3.
Renesas Technology Corp. assumes no responsibility for any damage, oement of
any third-party's rights, originating in the use of any product data, diacharts, pro-
grams, algorithms, or circuit application examples contained in thesals.
All information contained in these materials, including product daams, charts, pro-
grams and algorithms represents information on products at thpublication of these
materials, and are subject to change by Renesas Technolp. without notice due to
product improvements or other reasons. It is therefore rnded that customers con-
tact Renesas Technology Corp. or an authorized Reechnology Corp. product dis-
tributor for the latest product information before pg a product listed herein.
The information described here may contain tecaccuracies or typographical errors.
Renesas Technology Corp. assumes no relity for any damage, liability, or other
loss rising from these inaccuracies or err
Please also pay attention to informatihed by Renesas Technology Corp. by vari-
ous means, including the Renesas logy Corp. Semiconductor home page (http://
www.renesas.com).
4.
5.
When using any or all of the tion contained in these materials, including product
data, diagrams, charts, prand algorithms, please be sure to evaluate all informa-
tion as a total system bking a final decision on the applicability of the information
and products. Renesnology Corp. assumes no responsibility for any damage, liabil-
ity or other loss rerom the information contained herein.
Renesas Techorp. semiconductors are not designed or manufactured for use in a
device or sat is used under circumstances in which human life is potentially at
stake. Plntact Renesas Technology Corp. or an authorized Renesas Technology
Corp. distributor when considering the use of a product contained herein for any
specifirposes, such as apparatus or systems for transportation, vehicular, medical,
aerospace, nuclear, or undersea repeater use.
6.
7.
The prior written approval of Renesas Technology Corp. is necessary to reprint or repro-
duce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions,
they must be exported under a license from the Japanese government and cannot be im-
ported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/
or the country of destination is prohibited.
8.
Please contact Renesas Technology Corp. for further details on these materials or the
products contained therein.
3804 Group (Spec. H) User’s Manual
REVISION HISTORY
Rev.
Date
Description
Summary
Page
1.00 Jan 14, 2005
–
First edition issued
(1/1)
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development.
1. Organization
ꢀ CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
ꢀ CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of relevant registers.
ꢀ CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development umicrocomputer, such
as the electrical characteristics, the notes, and the list of registers
2. Structure of Register
The figure of each register structure describes its functions, conreset, and attributes as follows:
(Note 2)
Bits
Bit attributes
(Note 1)
Contents imy after reset release
b7 b6 b5 b4 b3 b2 b1 b0
0
CPU mode register (Cdress : 003B16
]
At reset
b
0
1
2
Functions
R
W
b1
b0
0 0 : Single-chip mode
0 1 :
Procesbits
0
0
0
Not available
1 0 :
1 1 :
0 : 0 page
1 : 1 page
age selection bit
5
0
0
0
ꢀ
ꢀ
hing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.
b7 b6
”
0 0 : φ = XIN/2 (High-speed mode)
0 1 : φ = XIN/8 (Middle-speed mode)
1 0 : φ = XIN/8 (Middle-speed mode)
1 1 : φ = XIN (Double-speed mode)
Main clock division ratio selection
1
0
6
7
bits
: Bit in which nothing is arranged
: Bit that is not used for control of the corresponding function
Notes 1: Contents immediately after reset release
0 •••••• “0” at reset release
1 •••••• “1” at reset release
Undefined •••••• Undefined or reset release
ꢀ ••••••Contents determined by option at reset release
2: Bit attributes••••••The attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
R••••••Read
W••••••Write
••••••Read enabled
ꢀ••••••Read disabled
••••••Write enabled
ꢀ ••••••Write disabled
3. Supplementary
For details of related development tools and documents, refer to web page “3804 Group” on our website
(http://www.renesas.com/eng/products/mpumcu/8bit/38000/index.html).
Table of contents
3804 Group (Spec.H)
Table of contents
CHAPTER 1 HARDWARE
DESCRIPTION ................................................................................................................................ 1-2
FEATURES...................................................................................................................................... 1-2
PIN CONFIGURATION .................................................................................................................. 1-3
FUNCTIONAL BLOCK .................................................................................................................. 1-4
PIN DESCRIPTION ........................................................................................................................ 1-5
PART NUMBERING ....................................................................................................................... 1-6
GROUP EXPANSION .................................................................................................................... 1-7
Memory Size ......................................................................................................................... 1-7
Packages ...................................................................................................................... 1-7
FUNCTIONAL DESCRIPTION ......................................................................................... 1-8
CENTRAL PROCESSING UNIT (CPU) ................................................................... 1-8
MEMORY .................................................................................................................... 1-13
I/O PORTS ................................................................................................................. 1-15
INTERRUPTS............................................................................................................. 1-23
TIMERS ..................................................................................................................... 1-27
SERIAL INTERFACE ................................................................................................ 1-40
PULSE WIDTH MODULATION (PWM)................................................................... 1-54
A/D CONVERTER .................................................................................................... 1-56
D/A CONVERTER .................................................................................................... 1-58
WATCHDOG TIMER ................................................................................................. 1-59
MULTI-MASTER I2C-BUS INTER............................................................................ 1-60
RESET CIRCUIT ...................................................................................................... 1-74
CLOCK GENERATING CIR...................................................................................... 1-76
FLASH MEMORY MODE ........................................................................................... 1-80
NOTES ON PROGRAMM............................................................................................... 1-99
NOTES ON USAGE ......................................................................................................1-100
FUNCTIONAL DESN SUPPLEMENT .......................................................................1-101
Interrupt ...................................................................................................................1-101
Timing Afteupt...........................................................................................................1-102
A/D Con.....................................................................................................................1-103
CHAPTAPPLICATION
2.1 I/O port ..................................................................................................................................... 2-2
2.1.1 Memory map ................................................................................................................... 2-2
2.1.2 Relevant registers .......................................................................................................... 2-3
2.1.3 Port Pi pull-up control register ..................................................................................... 2-5
2.1.4 Terminate unused pins .................................................................................................. 2-5
2.1.5 Notes on I/O port ........................................................................................................... 2-6
2.1.6 Termination of unused pins .......................................................................................... 2-7
2.2 Interrupt ................................................................................................................................... 2-8
2.2.1 Memory map ................................................................................................................... 2-8
2.2.2 Relevant registers .......................................................................................................... 2-8
2.2.3 Interrupt source ............................................................................................................ 2-12
2.2.4 Interrupt operation........................................................................................................ 2-13
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
i
Table of contents
3804 Group (Spec.H)
2.2.5 Interrupt control ............................................................................................................ 2-16
2.2.6 INT interrupt.................................................................................................................. 2-19
2.2.7 Notes on interrupts ...................................................................................................... 2-20
2.3 Timer.......................................................................................................................................2-22
2.3.1 Memory map ................................................................................................................. 2-22
2.3.2 Relevant registers ........................................................................................................2-23
2.3.3 Timer application examples ........................................................................................ 2-32
2.3.4 Notes on timer ..............................................................................................................2-45
2.4 Serial interface .....................................................................................................................2-47
2.4.1 Memory map ................................................................................................................. 2-47
2.4.2 Relevant registers ........................................................................................................2-48
2.4.3 Serial I/O connection examples ................................................................................. 2-56
2.4.4 Setting of serial I/O transfer data format ................................................................. 2-58
2.4.5 Serial I/O1, serial I/O3 operation: stop and initialize..................................... 2-59
2.4.6 Serial I/O pin function and selection method............................................. 2-60
2.4.7 Serial I/O application examples .................................................................... 2-61
2.4.8 Notes on serial interface................................................................................ 2-81
2.5 Multi-master I2C-BUS interface ........................................................................... 2-84
2.5.1 Memory map ................................................................................................... 2-84
2.5.2 Relevant registers ...........................................................................................2-85
2.5.3 I2C-BUS overview ............................................................................................2-94
2.5.4 Communication format ................................................................................... 2-95
2.5.5 Synchronization and arbitration lost ............................................................. 2-96
2.5.6 SMBUS communication usage ex................................................................. 2-98
2.5.7 Notes on multi-master I2C-BUS ce ...............................................................2-114
2.5.8 Notes on programming for Sinterface.........................................................2-117
2.6 PWM .........................................................................................................................2-118
2.6.1 Memory map .................................................................................................2-118
2.6.2 Relevant registers ........................................................................................2-118
2.6.3 PWM output circucation example.................................................................2-120
2.6.4 Notes on PWM ................................................................................................2-122
2.7 A/D converter .......................................................................................................2-123
2.7.1 Memory .........................................................................................................2-123
2.7.2 Relevaters ......................................................................................................2-123
2.7.3 A/D er application examples ........................................................................2-127
2.7.4 NA/D converter ............................................................................................2-131
2.8 D/A rter .....................................................................................................................2-132
2mory map ...............................................................................................................2-132
2.Relevant registers ......................................................................................................2-133
2.8.3 D/A converter application example ..........................................................................2-135
2.8.4 Notes on D/A converter ............................................................................................2-138
2.9 Watchdog timer ..................................................................................................................2-139
2.9.1 Memory map ...............................................................................................................2-139
2.9.2 Relevant registers ......................................................................................................2-139
2.9.3 Watchdog timer application examples.....................................................................2-141
2.9.4 Notes on watchdog timer ..........................................................................................2-142
2.10 Reset ..................................................................................................................................2-143
2.10.1 Connection example of reset IC ............................................................................2-143
____________
2.10.2 Notes on RESET pin ...............................................................................................2-144
2.11 Clock generating circuit ................................................................................................2-145
2.11.1 Relevant registers ....................................................................................................2-145
2.11.2 Clock generating circuit application example .......................................................2-146
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
ii
Table of contents
3804 Group (Spec.H)
2.12 Standby function .............................................................................................................2-149
2.12.1 Stop mode.................................................................................................................2-149
2.12.2 Wait mode .................................................................................................................2-153
2.13 Flash memory mode .......................................................................................................2-156
2.13.1 Overview....................................................................................................................2-156
2.13.2 Memory map .............................................................................................................2-156
2.13.3 Relevant registers ....................................................................................................2-157
2.13.4 Parallel I/O mode .....................................................................................................2-159
2.13.5 Standard serial I/O mode........................................................................................2-159
2.13.6 CPU rewrite mode ...................................................................................................2-160
2.13.7 Flash memory mode application examples ..........................................................2-162
2.13.8 Notes on CPU rewrite mode ..................................................................................2-166
CHAPTER 3 APPENDIX
3.1 ELECTRICAL CHARACTERISTICS........................................................................ 3-2
3.1.1 Absolute maximum ratings ............................................................................... 3-2
3.1.2 Recommended operating conditions............................................................... 3-3
3.1.3 Electrical characteristics .................................................................................. 3-6
3.1.4 A/D converter characteristics........................................................................... 3-8
3.1.5 D/A converter characteristics........................................................................... 3-8
3.1.6 Power source circuit timing character............................................................ 3-8
3.1.7 Timing requirements and switching teristics ................................................... 3-9
3.1.8 Multi-master I2C-BUS bus line cristics.......................................................... 3-14
3.2 Standard characteristics ....................................................................................... 3-15
3.2.1 Power source current stanaracteristics ........................................................ 3-15
3.2.2 Port standard character.................................................................................. 3-19
3.2.3 A/D conversion standracteristics ................................................................... 3-22
3.2.4 D/A conversion stcharacteristics ................................................................... 3-26
3.3 Notes on use .......................................................................................................... 3-27
3.3.1 Notes on inpoutput ports ................................................................................ 3-27
3.3.2 Terminatioused pins ........................................................................................ 3-28
3.3.3 Notes oupts ...................................................................................................... 3-29
3.3.4 Notebit timer (timer 1, 2, X, Y) ..................................................................... 3-30
3.3.5 N16-bit timer (timer Z) .................................................................................. 3-30
3.3.6 on serial interface............................................................................................. 3-32
3.s on multi-master I2C-BUS interface ................................................................. 3-34
3otes on programming for SMBUS interface........................................................... 3-36
3.3.Notes on PWM ............................................................................................................. 3-37
3.3.10 Notes on A/D converter ............................................................................................ 3-37
3.3.11 Notes on D/A converter ............................................................................................ 3-38
3.3.12 Notes on watchdog timer .......................................................................................... 3-38
____________
3.3.13 Notes on RESET pin ................................................................................................. 3-38
3.3.14 Notes on low-speed operation mode ...................................................................... 3-38
3.3.15 Quartz-crystal oscillator ............................................................................................. 3-39
3.3.16 Notes on restarting oscillation.................................................................................. 3-39
3.3.17 Notes on using stop mode ....................................................................................... 3-39
3.3.18 Notes on wait mode .................................................................................................. 3-40
3.3.19 Notes on CPU rewrite mode .................................................................................... 3-40
3.3.20 Notes on programming .............................................................................................. 3-40
3.3.21 Notes on flash memory version ............................................................................... 3-42
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
iii
Table of contents
3804 Group (Spec.H)
3.3.22 Notes on electric characteristic differences between mask ROM and flash nemory
version MCUs ............................................................................................................. 3-42
3.3.23 Notes on handling of power source pins ............................................................... 3-42
3.3.24 Power Source Voltage............................................................................................... 3-42
3.4 Countermeasures against noise ...................................................................................... 3-43
3.4.1 Shortest wiring length ..................................................................................................3-43
3.4.2 Connection of bypass capacitor across VSS line and VCC line............................... 3-45
3.4.3 Wiring to analog input pins ........................................................................................ 3-46
3.4.4 Oscillator concerns....................................................................................................... 3-47
3.4.5 Setup for I/O ports....................................................................................................... 3-48
3.4.6 Providing of watchdog timer function by software .................................................. 3-49
3.5 Control registers.................................................................................................................. 3-50
3.6 Package outline .................................................................................................................. 3-80
3.7 Machine instructions ................................................................................................ 3-82
3.8 List of instruction code ........................................................................................ 3-93
3.9 SFR memory map ...................................................................................................3-94
3.10 Pin configurations ................................................................................................ 3-95
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
iv
List of figures
3804 Group (Spec.H)
List of figures
CHAPTER 1 HARDWARE
Fig. 1 3804 group (Spec. H) pin configuration ........................................................................ 1-3
Fig. 2 3804 group (Spec. H) pin configuration ........................................................................ 1-3
Fig. 3 Functional block diagram ................................................................................................. 1-4
Fig. 4 Part numbering .................................................................................................................. 1-6
Fig. 5 Memory expansion plan ................................................................................................... 1-7
Fig. 6 740 Family CPU register structure ................................................................................. 1-8
Fig. 7 Register push and pop at interrupt generation and subroutine call .......................... 1-9
Fig. 8 Structure of CPU mode register ............................................................................ 1-11
Fig. 9 Structure of MISRG .......................................................................................... 1-12
Fig. 10 Memory map diagram...................................................................................... 1-13
Fig. 11 Memory map of special function register (SFR) ......................................... 1-14
Fig. 12 Port block diagram (1) ................................................................................... 1-16
Fig. 13 Port block diagram (2) ................................................................................... 1-17
Fig. 14 Port block diagram (3) .................................................................................... 1-18
Fig. 15 Structure of port pull-up control register (1.................................................. 1-19
Fig. 16 Structure of port pull-up control register ...................................................... 1-20
Fig. 17 Structure of port pull-up control regis........................................................... 1-21
Fig. 18 Structure of port pull-up control re) ............................................................. 1-22
Fig. 19 Interrupt control ............................................................................................... 1-25
Fig. 20 Structure of interrupt-related s ....................................................................... 1-26
Fig. 21 Block diagram of timer X, , timer 1, and timer 2........................................ 1-29
Fig. 22 Structure of timer XY mister .......................................................................... 1-30
Fig. 23 Structure of timer 12timer Y, Z count source selection registers ........... 1-31
Fig. 24 Block diagram of t............................................................................................ 1-35
Fig. 25 Structure of timde register............................................................................. 1-36
Fig. 26 Timing chart /event counter mode ................................................................ 1-37
Fig. 27 Timing chlse output mode ............................................................................ 1-37
Fig. 28 Timing clse period measurement mode (Measuring term between two rising edges) .. 1-38
Fig. 29 Timinof pulse width measurement mode (Measuring “L” term)................ 1-38
Fig. 30 Tiart of programmable waveform generating mode ................................... 1-39
Fig. 31 chart of programmable one-shot generating mode (“H” one-shot pulse generating) ... 1-39
Fig. 3k diagram of clock synchronous serial I/O1 ...................................................... 1-40
Fig. peration of clock synchronous serial I/O1 .............................................................. 1-40
Fig. 34 Block diagram of UART serial I/O1............................................................................ 1-41
Fig. 35 Operation of UART serial I/O1 ................................................................................... 1-41
Fig. 36 Structure of serial I/O1 control registers ................................................................... 1-43
Fig. 37 Structure of serial I/O2 control register ..................................................................... 1-46
Fig. 38 Block diagram of serial I/O2 ....................................................................................... 1-46
Fig. 39 Timing of serial I/O2..................................................................................................... 1-47
Fig. 40 Block diagram of clock synchronous serial I/O3 ...................................................... 1-48
Fig. 41 Operation of clock synchronous serial I/O3 .............................................................. 1-48
Fig. 42 Block diagram of UART serial I/O3............................................................................ 1-49
Fig. 43 Operation of UART serial I/O3 ................................................................................... 1-49
Fig. 44 Structure of serial I/O3 control registers ................................................................... 1-51
Fig. 45 Timing of PWM period ................................................................................................. 1-54
Fig. 46 Block diagram of PWM function ................................................................................. 1-54
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
v
List of figures
3804 Group (Spec.H)
Fig. 47 Structure of PWM control register .............................................................................. 1-55
Fig. 48 PWM output timing when PWM register or PWM prescaler is changed .............. 1-55
Fig. 49 Structure of AD/DA control register ........................................................................... 1-56
Fig. 50 Structure of 10-bit A/D mode reading........................................................................ 1-56
Fig. 51 Block diagram of A/D converter.................................................................................. 1-57
Fig. 52 Block diagram of D/A converter.................................................................................. 1-58
Fig. 53 Equivalent connection circuit of D/A converter (DA1) ............................................. 1-58
Fig. 54 Block diagram of Watchdog timer .............................................................................. 1-59
Fig. 55 Structure of Watchdog timer control register ............................................................ 1-59
Fig. 56 Block diagram of multi-master I2C-BUS interface .................................................... 1-60
Fig. 57 Structure of I2C slave address registers 0 to 2 ....................................................... 1-61
Fig. 58 Structure of I2C clock control register........................................................................ 1-62
Fig. 59 Structure of I2C control register ................................................................................. 1-63
Fig. 60 Structure of I2C status register ......................................................................... 1-65
Fig. 61 Interrupt request signal generating timing ................................................... 1-65
Fig. 62 START condition generating timing diagram ............................................... 1-66
Fig. 63 STOP condition generating timing diagram.................................................. 1-66
Fig. 64 START/STOP condition detecting timing diagram...................................... 1-67
Fig. 65 STOP condition detecting timing diagram .................................................... 1-67
Fig. 66 Structure of I2C START/STOP condition conster ........................................ 1-68
Fig. 67 Structure of I2C special mode status regis................................................... 1-69
Fig. 68 Structure of I2C special mode control r........................................................ 1-70
Fig. 69 Address data communication format ............................................................. 1-71
Fig. 70 Reset circuit example ...................................................................................... 1-74
Fig. 71 Reset sequence .............................................................................................. 1-74
Fig. 72 Internal status at reset .................................................................................... 1-75
Fig. 73 Ceramic resonator circuit ................................................................................ 1-77
Fig. 74 External clock input cir.................................................................................... 1-77
Fig. 75 System clock genercuit block diagram ........................................................ 1-78
Fig. 76 State transitions m clock................................................................................ 1-79
Fig. 77 Block diagram -in flash memory ..................................................................... 1-81
Fig. 78 Structure of emory control register 0 ............................................................ 1-82
Fig. 79 Structure memory control register 1 ............................................................ 1-82
Fig. 80 Structuash memory control register 2 ............................................................ 1-83
Fig. 81 CPe mode set/release flowchart ................................................................... 1-83
Fig. 82 Pflowchart ......................................................................................................... 1-85
Fig. 83 flowchart.............................................................................................................. 1-86
Fig. l status check flowchart and remedial procedure for errors ............................. 1-88
Fig. 8Structure of ROM code protect control address ...................................................... 1-89
Fig. 86 ID code store addresses.............................................................................................. 1-90
Fig. 87 Connection for standard serial I/O mode 1 (M38049FFHFP/HP/KP) .................... 1-94
Fig. 88 Connection for standard serial I/O mode 2 (M38049FFHFP/HP/KP) .................... 1-95
Fig. 89 Connection for standard serial I/O mode 1 (M38049FFHSP) ................................ 1-96
Fig. 90 Connection for standard serial I/O mode 2 (M38049FFHSP) ................................ 1-97
Fig. 91 Operating waveform for standard serial I/O mode 1 ............................................... 1-98
Fig. 92 Operating waveform for standard serial I/O mode 2 ............................................... 1-98
Fig. 93 Timing chart after an interrupt occurs .....................................................................1-102
Fig. 94 Time up to execution of the interrupt processing routine.....................................1-102
Fig. 95 A/D conversion equivalent circuit .............................................................................1-104
Fig. 96 A/D conversion timing chart ......................................................................................1-105
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
vi
List of figures
3804 Group (Spec.H)
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6)................................................................................. 2-3
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6) .................................................. 2-3
Fig. 2.1.4 Structure of Port Pi pull-up control register (i = 0, 1, 2, 4, 5, 6)......................... 2-4
Fig. 2.1.5 Structure of Port P3 pull-up control register ............................................................ 2-4
Fig. 2.2.1 Memory map of registers relevant to interrupt ........................................................ 2-8
Fig. 2.2.2 Structure of Interrupt source selection register ....................................................... 2-8
Fig. 2.2.3 Structure of Interrupt edge selection register .......................................................... 2-9
Fig. 2.2.4 Structure of Interrupt request register 1 ................................................................... 2-9
Fig. 2.2.5 Structure of Interrupt request register 2 ................................................................. 2-10
Fig. 2.2.6 Structure of Interrupt control register 1 .................................................................. 2-10
Fig. 2.2.7 Structure of Interrupt control register 2 ......................................................... 2-11
Fig. 2.2.8 Interrupt operation diagram.......................................................................... 2-13
Fig. 2.2.9 Changes of stack pointer and program counter upon acceptaterrupt request .... 2-14
Fig. 2.2.10 Time up to execution of interrupt processing routi................................ 2-15
Fig. 2.2.11 Timing chart after acceptance of interrupt requ.................................... 2-15
Fig. 2.2.12 Interrupt control diagram ........................................................................... 2-16
Fig. 2.2.13 Example of multiple interrupts................................................................... 2-18
Fig. 2.2.14 Sequence of changing relevant register ................................................... 2-20
Fig. 2.2.15 Sequence of check of interrupt requ....................................................... 2-21
Fig. 2.3.1 Memory map of registers relevant s .......................................................... 2-22
Fig. 2.3.2 Structure of Prescaler 12, PrescPrescaler Y ............................................ 2-23
Fig. 2.3.3 Structure of Timer 1 ..................................................................................... 2-23
Fig. 2.3.4 Structure of Timer 2, Timeer Y ................................................................. 2-24
Fig. 2.3.5 Structure of Timer Z (lohigh-order) .......................................................... 2-24
Fig. 2.3.6 Structure of Timer XY register ...................................................................... 2-25
Fig. 2.3.7 Structure of Timer register......................................................................... 2-26
Fig. 2.3.8 Structure of Timcount source selection register .................................... 2-28
Fig. 2.3.9 Structure of TZ count source selection register ...................................... 2-28
Fig. 2.3.10 Structure rupt source selection register ................................................... 2-29
Fig. 2.3.11 Structuterrupt request register 1 ............................................................... 2-30
Fig. 2.3.12 StruInterrupt request register 2 ............................................................... 2-30
Fig. 2.3.13 Sof Interrupt control register 1 ................................................................ 2-31
Fig. 2.3.14 ure of Interrupt control register 2 ................................................................ 2-31
Fig. 2.3ers connection and setting of division ratios ................................................. 2-33
Fig. elevant registers setting ....................................................................................... 2-33
Fig. 27 Control procedure..................................................................................................... 2-34
Fig. 2.3.18 Peripheral circuit example....................................................................................... 2-35
Fig. 2.3.19 Timers connection and setting of division ratios ................................................. 2-35
Fig. 2.3.20 Relevant registers setting ....................................................................................... 2-36
Fig. 2.3.21 Control procedure..................................................................................................... 2-37
Fig. 2.3.22 Judgment method of valid/invalid of input pulses ............................................... 2-38
Fig. 2.3.23 Relevant registers setting ....................................................................................... 2-39
Fig. 2.3.24 Control procedure..................................................................................................... 2-40
Fig. 2.3.25 Timers connection and setting of division ratios ................................................. 2-41
Fig. 2.3.26 Relevant registers setting ....................................................................................... 2-42
Fig. 2.3.27 Control procedure (1) .............................................................................................. 2-43
Fig. 2.3.28 Control procedure (2) .............................................................................................. 2-44
Fig. 2.4.1 Memory map of registers relevant to Serial I/O .................................................... 2-47
Fig. 2.4.2 Structure of Transmit/Receive buffer register 1 and Transmit/Receive buffer register 3 .. 2-48
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
vii
List of figures
3804 Group (Spec.H)
Fig. 2.4.3 Structure of Serial I/O1 status register and Serial I/O3 status register............. 2-48
Fig. 2.4.4 Structure of Serial I/O1 control register.................................................................. 2-49
Fig. 2.4.5 Structure of Serial I/O3 control register.................................................................. 2-50
Fig. 2.4.6 Structure of UART1 control register ........................................................................ 2-51
Fig. 2.4.7 Structure of UART3 control register ........................................................................ 2-51
Fig. 2.4.8 Structure of Baud rate generator 1 and Baud rate generator 3 ......................... 2-52
Fig. 2.4.9 Structure of Serial I/O2 control register.................................................................. 2-52
Fig. 2.4.10 Structure of Serial I/O2 register............................................................................. 2-53
Fig. 2.4.11 Structure of Interrupt source selection register ................................................... 2-53
Fig. 2.4.12 Structure of Interrupt request register 1 ............................................................... 2-54
Fig. 2.4.13 Structure of Interrupt request register 2 ............................................................... 2-54
Fig. 2.4.14 Structure of Interrupt control register 1 ................................................................ 2-55
Fig. 2.4.15 Structure of Interrupt control register 2 ............................................................... 2-55
Fig. 2.4.16 Serial I/O connection examples (1) ............................................................. 2-56
Fig. 2.4.17 Serial I/O connection examples (2) ......................................................... 2-57
Fig. 2.4.18 Serial I/O transfer data format .................................................................. 2-58
Fig. 2.4.19 Connection diagram .................................................................................... 2-61
Fig. 2.4.20 Timing chart (using clock synchronous serial I/..................................... 2-61
Fig. 2.4.21 Registers setting relevant to transmitting sid.......................................... 2-62
Fig. 2.4.22 Registers setting relevant to receiving sid............................................... 2-63
Fig. 2.4.23 Control procedure of transmitting side.................................................... 2-64
Fig. 2.4.24 Control procedure of receiving side ........................................................ 2-65
Fig. 2.4.25 Connection diagrams .................................................................................. 2-66
Fig. 2.4.26 Timing chart (serial I/O1) ........................................................................... 2-66
Fig. 2.4.27 Registers setting relevant to /O1 ............................................................... 2-67
Fig. 2.4.28 Setting of serial I/O1 trann data ............................................................... 2-67
Fig. 2.4.29 Control procedure of s1 ............................................................................ 2-68
Fig. 2.4.30 Registers setting relo serial I/O2 ............................................................... 2-69
Fig. 2.4.31 Setting of serial Insmission data ............................................................... 2-69
Fig. 2.4.32 Control procederial I/O2 ............................................................................ 2-70
Fig. 2.4.33 Connection ................................................................................................. 2-71
Fig. 2.4.34 Timing c....................................................................................................... 2-72
Fig. 2.4.35 Relevaters setting ....................................................................................... 2-72
Fig. 2.4.36 Concedure of master unit ........................................................................... 2-73
Fig. 2.4.37 Cprocedure of slave unit ............................................................................. 2-74
Fig. 2.4.3ction diagram (Communication using UART) ............................................ 2-75
Fig. 2.4ing chart (using UART) ..................................................................................... 2-75
Fig. Registers setting relevant to transmitting side..................................................... 2-77
Fig. 21 Registers setting relevant to receiving side ......................................................... 2-78
Fig. 2.4.42 Control procedure of transmitting side.................................................................. 2-79
Fig. 2.4.43 Control procedure of receiving side ...................................................................... 2-80
Fig. 2.4.44 Sequence of setting serial I/Oi (i = 1, 3) control register again....................... 2-82
Fig. 2.5.1 Memory map of registers relevant to I2C-BUS interface ...................................... 2-84
Fig. 2.5.2 Structure of MISRG ................................................................................................... 2-85
Fig. 2.5.3 Structure of I2C data shift register........................................................................... 2-85
Fig. 2.5.4 Structure of I2C special mode status register ........................................................ 2-86
Fig. 2.5.5 Structure of I2C status register................................................................................. 2-87
Fig. 2.5.6 Structure of I2C control register ............................................................................... 2-88
Fig. 2.5.7 Structure of I2C clock control register ..................................................................... 2-89
Fig. 2.5.8 Structure of I2C START/STOP condition control register ..................................... 2-90
Fig. 2.5.9 Structure of I2C special mode control register....................................................... 2-90
Fig. 2.5.10 Structure of I2C slave address register i (i = 0 to 2) ......................................... 2-91
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
viii
List of figures
3804 Group (Spec.H)
Fig. 2.5.11 Structure of Interrupt source selection register ................................................... 2-91
Fig. 2.5.12 Structure of Interrupt request register 1 ............................................................... 2-92
Fig. 2.5.13 Structure of Interrupt request register 2 ............................................................... 2-92
Fig. 2.5.14 Structure of Interrupt control register 1 ................................................................ 2-93
Fig. 2.5.15 Structure of Interrupt control register 2 ................................................................ 2-93
Fig. 2.5.16 I2C-BUS connection structure ................................................................................. 2-94
Fig. 2.5.17 I2C-BUS communication format example .............................................................. 2-95
Fig. 2.5.18 RESTART condition of master reception .............................................................. 2-96
Fig. 2.5.19 SCL waveforms when synchronizing clocks......................................................... 2-97
Fig. 2.5.20 Initial setting example for SMBUS communication.............................................. 2-99
Fig. 2.5.21 Read Word protocol communication as SMBUS master device .....................2-100
Fig. 2.5.22 Generating of START condition and transmission process of slave address + write bit ...2-101
Fig. 2.5.23 Transmission process of command ....................................................................2-102
Fig. 2.5.24 Transmission process of RESTART condition and slave ad+ read bit... 2-103
Fig. 2.5.25 Reception process of lower data ...........................................................2-104
Fig. 2.5.26 Reception process of upper data ...........................................................2-105
Fig. 2.5.27 Generating of STOP condition ................................................................2-106
Fig. 2.5.28 Communication example as SMBUS slave devi...................................2-107
Fig. 2.5.29 Reception process of START condition and ddress ............................2-108
Fig. 2.5.30 Reception process of command..............................................................2-109
Fig. 2.5.31 Reception process of RESTART conditslave address .......................2-110
Fig. 2.5.32 Transmission process of lower data......................................................2-111
Fig. 2.5.33 Transmission process of upper d...........................................................2-112
Fig. 2.5.34 Reception of STOP condition ..................................................................2-113
Fig. 2.6.1 Memory map of registers relePWM .........................................................2-118
Fig. 2.6.2 Structure of PWM control .........................................................................2-118
Fig. 2.6.3 Structure of PWM presc..............................................................................2-119
Fig. 2.6.4 Structure of PWM re..................................................................................2-119
Fig. 2.6.5 Connection diagra.......................................................................................2-120
Fig. 2.6.6 PWM output tim............................................................................................2-120
Fig. 2.6.7 Setting of relgisters ...................................................................................2-121
Fig. 2.6.8 PWM outp.....................................................................................................2-121
Fig. 2.6.9 Control ure.....................................................................................................2-122
Fig. 2.7.1 Memof registers relevant to A/D converter...........................................2-123
Fig. 2.7.2 Stof AD/DA control register .......................................................................2-123
Fig. 2.7.3 re of AD conversion register 1 ..................................................................2-124
Fig. 2.7cture of AD conversion register 2 ..................................................................2-124
Fig. tructure of Interrupt source selection register ...................................................2-125
Fig. 2Structure of Interrupt request register 2 ...............................................................2-126
Fig. 2.7.7 Structure of Interrupt control register 2 ................................................................2-126
Fig. 2.7.8 Connection diagram .................................................................................................2-127
Fig. 2.7.9 Relevant registers setting .......................................................................................2-127
Fig. 2.7.10 Control procedure (10-bit A/D mode) ..................................................................2-128
Fig. 2.7.11 Connection diagram ...............................................................................................2-129
Fig. 2.7.12 Relevant registers setting .....................................................................................2-129
Fig. 2.7.13 Control procedure (8-bit A/D mode) ....................................................................2-130
Fig. 2.8.1 Memory map of registers relevant to D/A converter...........................................2-132
Fig. 2.8.2 Structure of Port P5 direction register ..................................................................2-133
Fig. 2.8.3 Structure of AD/DA control register .......................................................................2-133
Fig. 2.8.4 Structure of DAi converter register........................................................................2-134
Fig. 2.8.5 Peripheral circuit example.......................................................................................2-135
Fig. 2.8.6 Speaker output example .........................................................................................2-135
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
ix
List of figures
3804 Group (Spec.H)
Fig. 2.8.7 Relevant registers setting .......................................................................................2-136
Fig. 2.8.8 Control procedure.....................................................................................................2-137
Fig. 2.9.1 Memory map of registers relevant to watchdog timer ........................................2-139
Fig. 2.9.2 Structure of Watchdog timer control register .......................................................2-139
Fig. 2.9.3 Structure of CPU mode register ............................................................................2-140
Fig. 2.9.4 Watchdog timer connection and division ratio setting ........................................2-141
Fig. 2.9.5 Relevant registers setting .......................................................................................2-142
Fig. 2.9.6 Control procedure.....................................................................................................2-142
Fig. 2.10.1 Example of poweron reset circuit ........................................................................2-143
Fig. 2.10.2 RAM backup system ..............................................................................................2-143
Fig. 2.11.1 Structure of CPU mode register ..........................................................................2-145
Fig. 2.11.2 Connection diagram ...............................................................................................2-146
Fig. 2.11.3 Status transition diagram during power failure .................................................2-146
Fig. 2.11.4 Setting of relevant registers .......................................................................2-147
Fig. 2.11.5 Control procedure......................................................................................2-148
Fig. 2.12.1 Oscillation stabilizing time at restoration by reset inp..........................2-150
Fig. 2.12.2 Execution sequence example at restoration by occurreninterrupt request... 2-152
0
Fig. 2.12.3 Reset input time .......................................................................................2-154
Fig. 2.13.1 Memory map of M38049FFHSP/FP/HP/KP ...........................................2-156
Fig. 2.13.2 Memory map of registers relevant to flash ry .........................................2-157
Fig. 2.13.3 Structure of Flash memory control regi.................................................2-157
Fig. 2.13.4 Structure of Flash memory control r1 ....................................................2-158
Fig. 2.13.5 Structure of Flash memory controer 2 ....................................................2-158
Fig. 2.13.6 Rewrite example of built-in flasory in standard serial I/O mode.........2-162
Fig. 2.13.7 Connection example in stanrial I/O mode (1).......................................2-163
Fig. 2.13.8 Connection example in stserial I/O mode (2).......................................2-163
Fig. 2.13.9 Connection example in rd serial I/O mode (3).......................................2-164
Fig. 2.13.10 Example of rewrite for built-in flash memory in CPU rewrite mode (single-
chip mode) ..............................................................................................2-165
CHAPTER 3 APPEND
Fig. 3.1.1 Circuit suring output switching characteristics (1) ................................... 3-12
Fig. 3.1.2 Circeasuring output switching characteristics (2) ................................... 3-12
Fig. 3.1.3 Tiagram (in single-chip mode) ..................................................................... 3-13
Fig. 3.1.diagram of multi-master I2C-BUS ................................................................ 3-14
Fig. 3wer source current standard characteristics (in high-speed mode) ............... 3-15
Fig. Power source current standard characteristics (in middle-speed mode) ........... 3-15
Fig. 3.3 Power source current standard characteristics (in low-speed mode) ................. 3-16
Fig. 3.2.4 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8
MHz, WAIT state) ....................................................................................................... 3-16
Fig. 3.2.5 Power source current standard characteristics (in middle-speed mode, f(XIN) = 16.8
MHz, WAIT state) ....................................................................................................... 3-17
Fig. 3.2.6 Power source current standard characteristics (in low-speed mode, WAIT state)...... 3-17
Fig. 3.2.7 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8
MHz, A/D converter operating) ................................................................................. 3-18
Fig. 3.2.8 Power source current standard characteristics (at oscillation stopping) ............ 3-18
Fig. 3.2.9 CMOS output port P-channel side characteristics (Ta = 25 °C)......................... 3-19
Fig. 3.2.10 CMOS output port N-channel side characteristics (Ta = 25 °C) ...................... 3-19
Fig. 3.2.11 N-channel open-drain output port N-channel side characteristics (Ta = 25 °C) .... 3-20
Fig. 3.2.12 CMOS large current output port N-channel side characteristics (Ta = 25 °C) .... 3-20
Fig. 3.2.13 CMOS input port at pull-up characteristics (Ta = 25 °C) .................................. 3-21
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
x
List of figures
3804 Group (Spec.H)
Fig. 3.2.14 A/D conversion standard characteristics (f(XIN) = 8 MHz) ................................. 3-23
Fig. 3.2.15 A/D conversion standard characteristics (f(XIN) = 12 MHz) ............................... 3-24
Fig. 3.2.16 A/D conversion standard characteristics (f(XIN) = 16 MHz) ............................... 3-25
Fig. 3.2.17 D/A conversion standard characteristics............................................................... 3-26
Fig. 3.3.1 Sequence of changing relevant register ................................................................. 3-29
Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-30
Fig. 3.3.3 Sequence of setting serial I/Oi (i = 1, 3) control register again......................... 3-33
Fig. 3.3.4 Ceramic resonator circuit .......................................................................................... 3-38
Fig. 3.3.5 Initialization of processor status register ................................................................ 3-40
Fig. 3.3.6 Sequence of PLP instruction execution .................................................................. 3-41
Fig. 3.3.7 Stack memory contents after PHP instruction execution ..................................... 3-41
Fig. 3.3.8 Status flag at decimal calculations .......................................................................... 3-41
_____________
Fig. 3.4.1 Wiring for the RESET pin ........................................................................................ 3-43
Fig. 3.4.2 Wiring for clock I/O pins ................................................................................. 3-44
Fig. 3.4.3 Wiring for CNVSS pin.................................................................................... 3-44
Fig. 3.4.4 Bypass capacitor across the VSS line and the VCC line ............................ 3-45
Fig. 3.4.5 Analog signal line and a resistor and a capacitor ................................... 3-46
Fig. 3.4.6 Wiring for a large current signal line ........................................................ 3-47
Fig. 3.4.7 Wiring of signal lines where potential levels crequently ......................... 3-47
Fig. 3.4.8 VSS pattern on the underside of an oscillat............................................... 3-48
Fig. 3.4.9 Setup for I/O ports ....................................................................................... 3-48
Fig. 3.4.10 Watchdog timer by software ..................................................................... 3-49
Fig. 3.5.1 Structure of Port Pi....................................................................................... 3-50
Fig. 3.5.2 Structure of Port Pi direction re.................................................................. 3-50
Fig. 3.5.3 Structure of Timer 12, X coue selection register .................................... 3-51
Fig. 3.5.4 Structure of Timer Y, Z corce selection register ...................................... 3-52
Fig. 3.5.5 Structure of MISRG ...................................................................................... 3-53
Fig. 3.5.6 Structure of I2C data gister........................................................................... 3-53
Fig. 3.5.7 Structure of I2C spode status register ........................................................ 3-54
Fig. 3.5.8 Structure of I2C register................................................................................. 3-55
Fig. 3.5.9 Structure of Irol register ............................................................................... 3-56
Fig. 3.5.10 Structure clock control register ................................................................... 3-57
Fig. 3.5.11 StructC START/STOP condition control register ................................... 3-58
Fig. 3.5.12 Struf I2C special mode control register..................................................... 3-58
Fig. 3.5.13 Sof Transmit/Receive buffer register 1, Transmit/Receive buffer register 3 .... 3-59
Fig. 3.5.1ure of Serial I/O1 status register, Serial I/O3 status register ................. 3-59
Fig. 3.5ucture of Serial I/O1 control register................................................................ 3-60
Fig. Structure of UART1 control register ...................................................................... 3-61
Fig. 37 Structure of Baud rate generator i ........................................................................ 3-61
Fig. 3.5.18 Structure of Serial I/O2 control register................................................................ 3-62
Fig. 3.5.19 Structure of Watchdog timer control register ....................................................... 3-62
Fig. 3.5.20 Structure of Serial I/O2 register............................................................................. 3-63
Fig. 3.5.21 Structure of Prescaler 12, Prescaler X, Prescaler Y .......................................... 3-63
Fig. 3.5.22 Structure of Timer 1 ................................................................................................ 3-64
Fig. 3.5.23 Structure of Timer 2, Timer X, Timer Y ............................................................... 3-64
Fig. 3.5.24 Structure of Timer XY mode register .................................................................... 3-65
Fig. 3.5.25 Structure of Timer Z low-order, Timer Z high-order ........................................... 3-66
Fig. 3.5.26 Structure of Timer Z mode register....................................................................... 3-66
Fig. 3.5.27 Structure of PWM control register ......................................................................... 3-68
Fig. 3.5.28 Structure of PWM prescaler ................................................................................... 3-68
Fig. 3.5.29 Structure of PWM register ...................................................................................... 3-68
Fig. 3.5.30 Structure of Serial I/O3 control register................................................................ 3-69
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
xi
List of figures
3804 Group (Spec.H)
Fig. 3.5.31 Structure of UART3 control register ...................................................................... 3-70
Fig. 3.5.32 Structure of AD/DA control register....................................................................... 3-70
Fig. 3.5.33 Structure of AD conversion register 1 .................................................................. 3-71
Fig. 3.5.34 Structure of DAi conversion register (i = 1, 2) .................................................... 3-71
Fig. 3.5.35 Structure of AD conversion register 2 .................................................................. 3-71
Fig. 3.5.36 Structure of Interrupt source selection register ................................................... 3-72
Fig. 3.5.37 Structure of Interrupt edge selection register ...................................................... 3-73
Fig. 3.5.38 Structure of CPU mode register ............................................................................ 3-73
Fig. 3.5.39 Structure of Interrupt request register 1 ............................................................... 3-74
Fig. 3.5.40 Structure of Interrupt request register 2 ............................................................... 3-74
Fig. 3.5.41 Structure of Interrupt control register 1 ................................................................ 3-75
Fig. 3.5.42 Structure of Interrupt control register 2 ................................................................ 3-75
Fig. 3.5.43 Structure of Flash memory control register 0 ..................................................... 3-76
Fig. 3.5.44 Structure of Flash memory control register 1 ............................................ 3-77
Fig. 3.5.45 Structure of Flash memory control register 2 ......................................... 3-77
Fig. 3.5.46 Structure of Port Pi pull-up control register (i = 0 to 6)....................... 3-78
Fig. 3.5.47 Structure of Port P3 pull-up control register ........................................... 3-78
Fig. 3.5.48 Structure of I2C slave address register i (i = 0 ..................................... 3-79
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
xii
List of tables
3804 Group (Spec.H)
List of tables
CHAPTER 1 HARDWARE
Table 1 Support products ............................................................................................................ 1-2
Table 2 Pin description................................................................................................................ 1-5
Table 3 Push and pop instructions of accumulator or processor status register ............... 1-9
Table 4 Set and clear instructions of each bit of processor status register ..................... 1-10
Table 5 I/O port function ........................................................................................................... 1-15
Table 6 Interrupt vector addresses and priority ..................................................................... 1-24
Table 7 Multi-master I2C-BUS interface functions.................................................................. 1-60
Table 8 Set values of I2C clock control register and SCL frequency ............................. 1-62
Table 9 START condition generating timing table .................................................... 1-66
Table 10 STOP condition generating timing table .................................................... 1-66
Table 11 START condition/STOP condition detecting condition............................. 1-67
Table 12 Recommended set value to START/STOP conditios (SSC4–SSC0) for each
oscillation frequency ..................................................................................... 1-68
Table 13 Summary of 3804 group (spec. H) ........................................................... 1-80
Table 14 State of E/W inhibition function .................................................................. 1-83
Table 15 List of software commands (CPU rewri) .................................................. 1-85
Table 16 Definition of each bit in status regist......................................................... 1-87
Table 17 Description of pin function (Flash y Serial I/O Mode 1) .......................... 1-93
Table 18 Description of pin function (Flaory Serial I/O Mode 2) .......................... 1-93
Table 19 Interrupt sources, vector addand priority.................................................1-101
Table 20 Relative formula for a refeoltage VREF of A/D converter and Vref (at 10-bit A/
D mode) .......................................................................................................1-103
Table 21 Relative formula for ence voltage VREF of A/D converter and Vref (at 8-bit A/
D mode) ......................................................................................................1-103
Table 22 Change of AD on register during A/D conversion (at 10-bit A/D mode) . 1-103
Table 23 Change of Arsion register during A/D conversion (at 8-bit A/D mode) ... 1-104
CHAPTER 2 APTION
Table 2.1.nation of unused pins (in single-chip mode) ............................................... 2-5
Table 2errupt sources, vector addresses and priority .............................................. 2-12
Table List of interrupt bits according to interrupt source ............................................. 2-17
Table 1 CNTR
Table 2.3.2 CNTR
0
/CNTR
1
active edge switch bit function.................................................... 2-25
2
active edge switch bit function ................................................................ 2-27
Table 2.4.1 Pin function in clock synchronous serial I/O mode............................................ 2-60
Table 2.4.2 Pin function in UART mode................................................................................... 2-60
Table 2.4.3 Pin function in clock synchronous serial I/O mode............................................ 2-60
Table 2.4.4 Setting examples of Baud rate generator (BRG) values and transfer bit rate values ... 2-76
Table 2.12.1 State in stop mode .............................................................................................2-149
Table 2.12.2 State in wait mode..............................................................................................2-153
Table 2.13.1 Parallel unit when parallel programming (when using EFP-I provided by Suisei
Electronics System Co., Ltd.)............................................................................2-159
Table 2.13.2 Connection example to programmer when serial programming (4 wires) ..2-159
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
xiii
List of tables
3804 Group (Spec.H)
CHAPTER 3 APPENDIX
Table 3.1.1 Absolute maximum ratings ....................................................................................... 3-2
Table 3.1.2 Recommended operating conditions (1) ................................................................ 3-3
Table 3.1.3 Recommended operating conditions (2) ................................................................ 3-4
Table 3.1.4 Recommended operating conditions (3) ................................................................3-5
Table 3.1.5 Electrical characteristics (1)..................................................................................... 3-6
Table 3.1.6 Electrical characteristics (2)..................................................................................... 3-7
Table 3.1.7 A/D converter recommended operating conditions............................................... 3-8
Table 3.1.8 A/D converter characteristics................................................................................... 3-8
Table 3.1.9 D/A converter characteristics................................................................................... 3-8
Table 3.1.10 Power source circuit timing characteristics ......................................................... 3-8
Table 3.1.11 Timing requirements (1) ......................................................................................... 3-9
Table 3.1.12 Timing requirements (2) .............................................................................. 3-10
Table 3.1.13 Switching characteristics ........................................................................ 3-11
Table 3.1.14 Multi-master I2C-BUS bus line characteristics .................................... 3-14
Table 3.5.1 CNTR
Table 3.5.2 CNTR
0
/CNTR active edge switch bit function....................................... 3-65
active edge switch bit function .................................................. 3-67
1
2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
xiv
HAPTER 1
HARDWARE
DESCRIPTION
FEATURES
PIN CONFIGURATION
FUNCTIONAL BLOCK
PIN DESCRIPTION
PART NUMBERING
GROUP EXPANSION
FUNCTIONAL DESCRIPTION
NOTES ON PROGRAMMING
NOTES ON USAGE
DATA REQUIRED FOR MASK ORDERS
FUNCTIONAL DESCRIPTION SUPPLEMENT
HARDWARE
3804 Group (Spec.H)
DESCRIPTION/FEATURES
DESCRIPTION
The 3804 group (Spec. H) is the 8-bit microcomputer based on the
ꢀPower source voltage
In high-speed mode
740 family core technology.
At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V
At 12.5 MHz oscillation frequency ............................ 4.0 to 5.5 V
At 8.4 MHz oscillation frequency) ............................. 2.7 to 5.5 V
In middle-speed mode
The 3804 group (Spec. H) is designed for household products, of-
fice automation equipment, and controlling systems that require
analog signal processing, including the A/D converter and D/A
converters.
At 16.8 MHz oscillation frequency ............................ 4.5 to 5.5 V
At 12.5 MHz oscillation frequency ............................ 2.7 to 5.5 V
In low-speed mode
FEATURES
ꢀBasic machine-language instructions ...................................... 71
ꢀMinimum instruction execution time ................................ 0.24 µs
(at 16.8 MHz oscillation frequency)
At 32 kHz oscillation frequency................................. 2.7 to 5.5 V
ꢀPower dissipation
In high-speed mode ....................................... 27.5 mW (typ.)
(at 16.8 MHz oscillation frequencower source voltage)
In low-speed mode .............................. 1200 µW (typ.)
(at 32 kHz oscillation frequV power source voltage)
ꢀOperating temperature ............................–20 to 85°C
ꢀPackages
ꢀMemory size
Flash memory.............................................................. 60 K bytes
RAM ............................................................................ 2048 bytes
ꢀProgrammable input/output ports ............................................ 56
ꢀSoftware pull-up resistors ................................................. Built-in
ꢀInterrupts
SP ................................. 64P4B (64-pin 750 mil SDIP)
FP ...................... 64P6N-A (64-pin 14 ꢀ 14 mm QFP)
HP ................... 64P6Q-A (64-pin 10 ꢀ 10 mm LQFP)
KP .................... 64P6U-A (64-pin 14 ꢀ 14 mm LQFP)
21 sources, 16 vectors .................................................................
(external 8, internal 12, software 1)
ꢀTimers ........................................................................... 16-bit ꢀ 1
8-bit ꢀ 4
(with 8-bit prescaler)
<Flry mode>
ꢀWatchdog timer ............................................................ 16-bit ꢀ 1
ꢀSerial interface
ource voltage...................................... Vcc = 2.7 to 5.5 V
am/Erase voltage.................................... Vcc = 2.7 to 5.5 V
ogramming method ...................... Programming in unit of byte
ꢀErasing method ...................................................... Block erasing
ꢀProgram/Erase control by software command
Serial I/O1, 3 ............... 8-bit ꢀ 2 (UART or Clock-synchronized)
Serial I/O2 ...................................8-bit ꢀ 1 (Clock-synchroniz
ꢀPWM ............................................8-bit ꢀ 1 (with 8-bit pres
2
ꢀMulti-master I C-BUS interface ...................................
ꢀNumber of times for programming/erasing ............................ 100
ꢀA/D converter ............................................. 10-bit ꢀ ls
(8-bit rbled)
ꢀNotes
ꢀD/A converter.................................................. hannels
ꢀLED direct drive port ................................................ 8
ꢀClock generating circuit........................uilt-in 2 circuits
(connect to external ceramic resonato-crystal oscillator)
Cannot be used for application embedded in the MCU card.
Currently support products arlow.
Table 1 Support pro
sh memory size
Product name
RAM size (bytes)
2048
Package
Remarks
(bytes)
M38049FFHSP
M38049FFHFP
M38049FFHHP
M38049FFHKP
64P4B
64P6N-A
64P6Q-A
64P6U-A
61440
Vcc = 2.7 to 5.5 V
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-2
HARDWARE
3804 Group (Spec.H)
PIN CONFIGURATION
PIN CONFIGURATION (TOP VIEW)
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
1
P20(LED0)
P3
7
/SRDY3
/SCLK3
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P3
6
P21(LED1)
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED6)
P3
5
/T
X
D
3
3
P3
P3
P3
P3
4
/R
X
D
3/SCL
2/SDA
1/DA
2
P3
0/DA
1
P27(LED7)
M38049FFHFP/HP/KP
VCC
V
SS
V
REF
X
OUT
AVSS
/AN
XIN
P6
7
7
P4
0
P6
P6
P6
6/AN
5/AN
4
/AN
6
5
4
P63/AN3
/INT1
Package type : 644P6Q-A/64P6U-A
Fig. 1 3804 group (Spec. H) pin configuration
PIN CONFIGURATION (TOP VIEW
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
N
P3
P3
0
1
/DA
/DA
1
2
P3
2
/SDA
/SCL
/R
/T
/
/
5
P3
3
P34
XD
3
P35
X
D
3
/AN4
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
SCLK3
63
P62
P61
P60
/AN
/AN
/AN
/AN
7/INT
/PWM
3
2
1
0
3
S
RDY3
9
/AN
/AN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
/AN10
/AN11
/AN12
/AN13
/AN14
/AN15
/INT41
/INT01
P5
P56
P5
P5
5
/CNTR
/CNTR
1
4
0
P5
P5
P5
P5
CNTR
P4
P4
3
/SRDY2
/SCLK2
/SOUT2
/SIN2
2
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
1
0
P4
7
/SRDY1
/
2
6
/SCLK1
5
/T
/R
X
D
1
1
2
P4
P4
4
XD
3
/INT
/INT
CNVSS
RESET
P42
1
0
(LED
(LED
(LED
(LED
(LED
(LED
(LED
(LED
0
)
)
)
)
)
)
)
)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
P4
1
/INT00/XCIN
/INT40/XCOUT
P4
0
X
IN
OUT
SS
X
V
Package type : 64P4B
Fig. 2 3804 group (Spec. H) pin configuration
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-3
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL BLOCK
FUNCTIONAL BLOCK
Fig. 3 Functional block diagram
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-4
HARDWARE
3804 Group (Spec.H)
PIN DESCRIPTION
PIN DESCRIPTION
Table 2 Pin description
Functions
Pin
Name
Function except a port function
VCC, VSS
CNVSS
•Apply voltage of 2.7 V–5.5 V to Vcc, and 0 V to Vss.
•This pin controls the operation mode of the chip.
•Normally connected to VSS.
Power source
CNVSS input
VREF
AVSS
•Reference voltage input pin for A/D and D/A converters.
•Analog power source input pin for A/D and D/A converters.
•Connect to VSS.
Reference voltage
Analog power source
•Reset input pin for active “L”.
RESET
XIN
Reset input
Clock input
•Input and output pins for the clock generating circuit.
•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
•8-bit CMOS I/O port.
•A/D cput pin
•put pin
P00/AN8–
P07/AN15
I/O port P0
I/O port P1
•I/O direction register allows each pin to be individually
programmed as either input or output.
P10/INT41
P11/INT01
•CMOS compatible input level.
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
P12–P17
P20–P27
I/O port P2
I/O port P3
•P20–P27 are enabled to output large current ive.
P3
P3
0
1
/DA
/DA
1
2
•8-bit CMOS I/O port.
•D/A converter input pin
•I/O direction register allows each pin idually
programmed as either input or outp
2
P32/SDA
P33/SCL
•I C-BUS interface function pins
•CMOS compatible input level.
P34/RxD3
P35/TxD3
P36/SCLK3
P37/SRDY3
•P32 to P33 can be switched CMOS compat-
ible input level or SMBUel in the I C-BUS
interface function.
•Serial I/O3 function pin
2
•P30, P31, P34–P37 a3-state output structure.
•P32, P33 are N-cn-drain output structure.
•Pull-up contro31, P34–P37 is enabled in a bit
unit.
•8-bit CMrt.
•Interrupt input pin
P40/INT40/
XCOUT
P41/INT00/
XCIN
I/O port P4
•I/O gister allows each pin to be individually
pras either input or output.
•Sub-clock generating I/O pin
(resonator connected)
•Interrupt input pin
mpatible input level.
P42/INT1
P43/INT2
S 3-state output structure.
ll-up control is enabled in a bit unit.
P44/RxD1
P45/TxD1
P46/SCLK1
•Serial I/O1 function pin
P47/SRDY1
/CNTR2
•Serial I/O1, timer Z function pin
•Serial I/O2 function pin
P50/SIN2
I/O por
•8-bit CMOS I/O port.
P51/SOUT2
P52/SCLK2
P53/SRDY2
•I/O direction register allows each pin to be individually
programmed as either input or output.
•CMOS compatible input level.
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
•Timer X function pin
•Timer Y function pin
•PWM output pin
•CMOS 3-state output structure.
•Pull-up control is enabled in a bit unit.
•Interrupt input pin
I/O port P6
•A/D converter input pin
P60/AN0–
P67/AN7
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-5
HARDWARE
3804 Group (Spec.H)
PART NUMBERING
PART NUMBERING
Product name
M3804 9
F
F
H
SP
Package type
SP : 64P4B
FP : 64P6N-A
HP : 64P6Q-A
KP : 64P6U-A
: standard
H : Minner spec. change product
ROM/PROM size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 b
: 3276
9: 36864 byt
A: 40960
B: 45
C: es
bytes
44 bytes
61440 bytes
1
2
3
4
5
6
7
8
pe
sh memory version
RAM size
0: 192 bytes
1: 256 bytes
2: 384 bytes
3: 512 bytes
4: 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
8 : 1536 bytes
9 : 2048 bytes
Fig. 4 Part numbering
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-6
HARDWARE
3804 Group (Spec.H)
GROUP EXPANSION
GROUP EXPANSION
Packages
64P4B ......................................... 64-pin shrink plastic-molded DIP
64P6N-A .................................... 0.8 mm-pitch plastic molded QFP
64P6Q-A .................................. 0.5 mm-pitch plastic molded LQFP
64P6U-A .................................. 0.8 mm-pitch plastic molded LQFP
Renesas plans to expand the 3804 group (Spec. H) as follows.
Memory Size
Flash memory size ......................................................... 60 K bytes
RAM size ....................................................................... 2048 bytes
Memory Expansion Plan
As of Dec. 2004
ROM size (bytes)
:
Under development
: Mass production
FH
049FF
60K
48K
32K
28K
24K
20K
16K
12K
8K
384
5
768
896
1024
1152
1280
1408
1536
2048
3072
4032
RAM size (bytes)
Fig. 5 Memory expanplan
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-7
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3804 group (Spec. H) uses the standard 740 Family instruc-
tion set. Refer to the table of 740 Family addressing modes and
machine instructions or the 740 Family Software Manual for de-
tails on the instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
transfer, etc. are executed mainly through the accumulator.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls (see Table 3).
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit onsisting of two 8-bit
registers PCH and PCL. It is icate the address of the
next instruction to be exec
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
cumulator
b0
b0
b0
b0
b7
Index register X
Index register Y
b7
Y
S
Stack pointer
b15
b7
b7
H
PC
L
Program counter
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-8
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
Push return address
on stack
Push contents of processor
status register on stack
Interrupt
Service Routin
Flag is set from “0” to “1”
Execute RTS
(S) (S) + 1
Fetch the jump vector
Execute
(1
POP return
address from stack
POP contents of
processor status
register from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for accf an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop pt generation and subroutine call
Table 3 Push and pop ins of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-9
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The N flag is set if the result of etic operation or data
transfer is negative. When thction is executed, bit 7 of
the memory location operthe BIT instruction is stored
in the negative flag.
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can execute decimal arithmetic.
Table 4 Set and clear instructions of each bit of processor status reg
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
ED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLV
Clear instruction
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-10
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, etc.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
1
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 : Not available
1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
Port XC switch bit
0 : I/O port function (stg)
1 : XCIN–XCOUT osciion
Main clock (XIN–Xbit
0 : Oscillatin
1 : Stoppe
Main clratio selection bits
b7
f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-speed mode)
: φ = f(XCIN)/2 (low-speed mode)
1 : Not available
Fig. 8 Structure of CPU mode register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-11
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
MISRG
●Middle-speed mode automatic switch by SCL/SDA Interrupt
The SCL/SDA interrupt source enables an automatic switch when
the middle-speed mode automatic switch set bit (bit 1) of MISRG
(address 001016) is set to “1”. The conditions for an automatic
(1) Bit 0 of address 001016: Oscillation stabilizing time set af-
ter STP instruction released bit
When the MCU stops the clock oscillation by the STP instruction
and the STP instruction has been released by an external interrupt
source, usually, the fixed values of Timer 1 and Prescaler 12
(Timer 1 = 0116, Prescaler 12 = FF16) are automatically reloaded
in order for the oscillation to stabilize. The user can inhibit the au-
tomatic setting by setting “1” to bit 0 of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just be-
fore the STP instruction was executed, will remain in Timer 1 and
Prescaler 12. Therefore, you will need to set an appropriate value
to each register, in accordance with the oscillation stabilizing time,
before executing the STP instruction.
2
switch execution depend on the settings of bits 5 and 6 of the I C
START/STOP condition control register (address 001616). Bit 5 is
the SCL/SDA interrupt pin polarity selection bit and bit 6 is the
SCL/SDA interrupt pin selection bit. The main clock oscillation sta-
bilizing time can also be selected by middle-speed mode
automatic switch wait time set bit (bit 2) of the MISRG.
●Middle-speed mode automatic switch by program
The middle-speed mode can also be automatically switched by
program while operating in low-speed mode. By setting the
middle-speed automatic switch start bit (bit 3) of MISRG (address
001016) to “1” in the condition that the middle-speed mode auto-
matic switch set bit is “1” while operlow-speed mode, the
MCU will automatically switch to ed mode. In this case,
the oscillation stabilizing time oclock can be selected by
the middle-speed automawait time set bit (bit 2) of
MISRG (address 00101
Figure 9 shows the structure of MISRG.
(2) Bits 1, 2, 3 of address 001016: Middle-speed Mode Auto-
matic Switch Function
In order to switch the clock mode of an MCU which has a sub-
clock, the following procedure is necessary:
set CPU mode register (003B16) --> start main clock oscillation -->
wait for oscillation stabilization --> switch to middle-speed mode
(or high-speed mode).
However, the 3804 group (Spec. H) has the built-in function which
automatically switches from low to middle-speed mode either by
the SCL/SDA interrupt or by program.
b7
b0
MISRG
(MISRG : ad1016
)
Oscillailizing time set after STP instruction
rele
atically set “0116” to Timer 1, “FF16” to
scaler 12
utomatically set disabled
Middle-speed mode automatic switch set bit
0: Not set automatically
1: Automatic switching enabled (Note1, 2)
Middle-speed mode automatic switch wait time set bit
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
Middle-speed mode automatic switch start bit
(Depending on program)
0: Invalid
1: Automatic switch start (Note1)
Not used (return “0” when read)
(Do not write “1” to this bit)
Note 1: During operation in low-speed mode, it is possible automatically to
switch to middle-speed mode owing to SCL/SDA interrupt.
2: When automatic switch to middle-speed mode from low-speed
mode occurs, the values of CPU mode register (003B16) change.
Fig. 9 Structure of MISRG
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-12
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
MEMORY
Interrupt Vector Area
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
RAM
addressing mode.
The RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
Access to this area with only 2 bytes is possible in the special
ROM
page addressing mode.
The ROM area can program/erase.
RAM area
RAM size
(bytes)
Address
XXXX16
000016
SFR area
192
256
384
512
640
768
896
1024
1536
2048
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
063F16
083F16
Zero page
004016
010016
RAM
XXXX16
Not used
SFR area
6
Not used
YYYY16
ROM area
ROM size
(bytes)
Address
YYYY16
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
90001
800
16
0016
300016
200016
100016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ROM
FF0016
FFDC16
Special page
Interrupt vector area
FFFE16
FFFF16
Fig. 10 Memory map diagram
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-13
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Port P0 (P0)
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
Port P0 direction register (P0D)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
002316 Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
002416
002516
002616
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Port P3 direction register (P3D)
Port P4 (P4)
002716 Timer Y (TY)
Timer Z low-order (TZL)
Timer Z high-order (TZH)
002816
002916
Port P4 direction register (P4D)
Port P5 (P5)
002A16 Timer Z mode register (TZM)
Port P5 direction register (P5D)
Port P6 (P6)
002B16
002C16
PWM control register (PWMCON)
PWM prescaler (PREPWM)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
002D16 PWM register (PWM)
002E16
002F16
003016
003116
003216
Baud rate generator 3 (BR
Transmit/Receive buffeTB3/RB3)
001016 MISRG
2
001116
I C data shift register (S0)
2
Serial I/O3 status rSTS)
Serial I/O3 conSIO3CON)
001216 I C special mode status register (S3)
2
001316
001416
001516
001616
001716
003316 UART3 co(UART3CON)
I C status register (S1)
2
AD/DA ter (ADCON)
AD register 1 (AD1)
003416
003516
I C control register (S1D)
2
I C clock control register (S2)
2
003616 sion register (DA1)
I C START/STOP condition control register (S2D)
2
nversion register (DA2)
conversion register 2 (AD2)
0037
0
I C special mode control register (S3D)
001816 Transmit/Receive buffer register 1 (TB1/RB1)
001916 Serial I/O1 status register (SIO1STS)
Interrupt source selection register (INTSEL)
16 Interrupt edge selection register (INTEDGE)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
001A16
001B16
CPU mode register (CPUM)
03B16
003C16
003D16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
001C16 Baud rate generator 1 (BRG1)
001D16 Serial I/O2 control register (SIO2CON)
001E16 Watchdog timer control register (WDTCON
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001F16
Serial I/O2 register (SIO2)
Flash memory control regis0)
Flash memory control rCR1)
Flash memory cont(FMCR2)
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
0FE016
0FE116
0FE216
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
0FE316 Reserved ꢀ
0FE416
0FE516 Reserv
0FE616
Reserved
Reserve
2
0FE716 Reserved ꢀ
0FE816 Reserved ꢀ
0FE916 Reserved ꢀ
0FEA16 Reserved ꢀ
I C slave address register 0 (S0D0)
2
I C slave address register 1 (S0D1)
2
I C slave address register 2 (S0D2)
Reserved ꢀ
0FEC16 Reserved ꢀ
Reserved ꢀ
ꢀ Reserved area: Do not write any data to these addresses,
0FEB16
because these areas are reserved.
0FED16
0FEE16 Reserved ꢀ
0FEF16 Reserved ꢀ
Fig. 11 Memory map of special function register (SFR)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-14
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
I/O PORTS
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
When “0” is written to the bit corresponding to a pin, that pin be-
Table 5 I/O port function
Related SFRs
Ref.No.
(1)
Name
I/O Structure
CMOS compatible input level
CMOS 3-state output
Non-Port Function
A/D converter input
External interrupt input
Pin
P00/AN8–P07/AN15
P10/INT41
AD/DA control register
Port P0
Port P1
Interrupt edge selection
register
(2)
P11/INT01
P12–P17
(3)
Port P2
Port P3
P20/LED0–
P27/LED7
CMOS compatible input level
CMOS 3-state output
D/A converter output
AD/DA crol register
(4)
(5)
P30/DA1
P31/DA2
P32/SDA
P33/SCL
2
2
CMOS compatible input level
N-channel open-drain output
CMOS/SMBUS input level (when
I C-BUS interface func-
I gister
tion I/O
2
selecting I C-BUS interface function)
CMOS compatible input level
CMOS 3-state output
P34/RxD3
Serial I/O3 funct
Serial I/O3 control
register
(6)
(7)
P35/TxD3
UART3 control register
P36/SCLK3
(8)
P37/SRDY3
(9)
P40/INT40/XCIN
P41/INT00/XCOUT
Interrupt edge selection
register
(10)
(11)
CMOS compatible input level
CMOS 3-state output
Exrupt input
Port P4
generating
CPU mode register
P42/INT1
Interrupt edge selection
register
(2)
rnal interrupt input
P43/INT2
(6)
(7)
P44/RxD1
Serial I/O1 control
register
Serial I/O1 function I/O
P45/TxD1
UART1 control register
(8)
P46/SCLK1
P47/SRDY1/CNTR2
(12)
Serial I/O1 function I/O
Timer Z function I/O
Serial I/O1 control
register
Timer Z mode register
Serial I/O2 control
register
P50/SIN2
Port P5
Serial I/O2 function I/O
(13)
(14)
(15)
(16)
(17)
CMOS cinput level
CMOutput
P51/SOUT2
P52/SCLK2
P53/SRDY2
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
Timer X, Y function I/O
Timer XY mode register
PWM control register
PWM output
(18)
(2)
External interrupt input
Interrupt edge selection
register
P60/AN0–P67/AN7
Port P6
CMOS compatible input level
CMOS 3-state output
A/D converter input
AD/DA control register
(1)
Notes 1: Refer to the applicable sections how to use double-function ports as function I/O ports.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-15
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(1) Ports P0, P6
(2) Ports P10, P11, P42, P43, P57
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
A/D converter input
Analog input pin
selection bit
Interrupt input
(3) Ports P1
2
to P1
7
, P2
(4) Ports P30, P31
Pull-up control bit
Pull-up control bit
Direction
register
Direction
register
Data bus
Por
Data bus
Port latch
D/A converter output
DA
DA
1
2
output enable (P3
0
)
)
output enable (P3
1
(6) Port
(5) Ports P32, P33
Pull-up control bit
2
I C-BUS interface enable bit
Serial I/O enable bit
Receive enable bit
Direction
register
Direction
register
Data bus
Port latch
Data bus
Port latch
SDA output
SCL output
SD
Serial I/O input
(7) Ports P3
5
, P4
5
(8) Ports P36, P46
Pull-up control bit
Serial I/O synchronous clock
selection bit
p control bit
Serial I/O enable bit
P-channel output
disable bit
Serial I/O mode selection bit
Serial I/O enable bit
Serial I/O ena
Transmit en
Direction
register
Directi
register
Data bus
Port latch
Data bus
Port latch
Serial I/O clock output
Serial I/O output
Serial I/O external clock input
Fig. 12 Port block diagram (1)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-16
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(9) Port P3
7
(10) Port P40
Pull-up control bit
Pull-up control bit
Serial I/O3 mode
selection bit
Serial I/O3 enable bit
Port X
C
switch bit
S
RDY3 output enable bit
Direction
register
Direction
register
Data bus
Port latch
Port latch
Data bus
INT40 interrupt input
Oscillator
Serial I/O3 ready output
Port P4
1
switch bit
(11) Port P4
1
(12) Port P47
Timer Z operating
mode bits
Bit 2
up control bit
Pull-up control bit
Bit 1
Bit 0
Port X
C
switch bit
Serial I/O1 mode s
Serial I
Direction
register
S
RDYbit
Direction
register
Data bus
Port latch
bus
Port latch
INT00 interrupt input
Sub-clock generating circuit input
Timer output
Serial I/O1 ready output
CNTR2 interrupt input
(13) Port P5
0
(14) Port P51
Pull-up control bit
Pbit
Serial I/O2 transmit completion signal
Serial I/O2 port selection bit
P-channel output
disable bit
D
r
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 input
Serial I/O2 output
Fig. 13 Port block diagram (2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-17
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(15) Port P5
2
(16) Port P53
Pull-up control bit
Pull-up control bit
Serial I/O2 synchronous clock
selection bit
Serial I/O2 port selection bit
S
RDY2 enable bit
Direction
register
Direction
register
Port latch
Data bus
Data bus
Port latch
Serial I/O2 ready output
Serial I/O2 clock output
Serial I/O2 external clock input
(17) Ports P5
4
, P5
5
(18) Port P5
6
Pull-up control bit
Pull-up control bit
enable bit
Direction
register
Direction
register
us
Port latch
Data bus
Port latch
Pulse output mode
Timer output
PWM output
CNTR inter
Fig. 14 Port block diagram (3)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-18
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Port P0 pull-up control register
(PULL0: address 0FF016)
P00 pull-up control bit
0: No pull-up
1: Pull-up
P01 pull-up control bit
0: No pull-up
1: Pull-up
P02 pull-up control bit
0: No pull-up
1: Pull-up
P03 pull-up control bit
0: No pull-up
1: Pull-up
P04 pull-up control bit
0: No pull-up
1: Pull-up
P05 pull-up control bit
0: No pull-up
1: Pull-up
P06 pull-up control bit
0: No pull-up
1: Pull-up
P07 pull-up control bit
0: No pull-up
Note: Pull-up cod when the corresponding bit
of the pn register is “0” (input).
Whe“1” (output), pull-up cannot be set
to which pull-up is selected.
1: Pull-up
b7
b0
Port P1 pull-up control register
(PULL1: address 0FF116)
P10 pull-up control b
0: No pull-up
1: Pull-up
P11 pull-up
0: No p
1: P
P1trol bit
up
up
ull-up control bit
: No pull-up
1: Pull-up
P14 pull-up control bit
0: No pull-up
1: Pull-up
P15 pull-up control bit
0: No pull-up
1: Pull-up
P16 pull-up control bit
0: No pull-up
1: Pull-up
P17 pull-up control bit
0: No pull-up
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
1: Pull-up
Fig. 15 Structure of port pull-up control register (1)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-19
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Port P2 pull-up control register
(PULL2: address 0FF216
)
P20 pull-up control bit
0: No pull-up
1: Pull-up
P21 pull-up control bit
0: No pull-up
1: Pull-up
P22 pull-up control bit
0: No pull-up
1: Pull-up
P23 pull-up control bit
0: No pull-up
1: Pull-up
P24 pull-up control bit
0: No pull-up
1: Pull-up
P25 pull-up control bit
0: No pull-up
1: Pull-up
P26 pull-up control bit
0: No pull-up
1: Pull-up
P27 pull-up control bit
Note: Pull-up cid when the corresponding bit
of the n register is “0” (input).
Whe“1” (output), pull-up cannot be set
to which pull-up is selected.
0: No pull-up
1: Pull-up
b7
b0
Port P3 pull-up control registe
(PULL3: address 0FF316
)
P30 pull-up control b
0: No pull-up
1: Pull-up
P31 pull-up
0: No
1: P
N
” when read)
pull-up control bit
0: No pull-up
1: Pull-up
P35 pull-up control bit
0: No pull-up
1: Pull-up
P36 pull-up control bit
0: No pull-up
1: Pull-up
P37 pull-up control bit
0: No pull-up
1: Pull-up
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
Fig. 16 Structure of port pull-up control register (2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-20
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Port P4 pull-up control register
(PULL4: address 0FF416
)
P40 pull-up control bit
0: No pull-up
1: Pull-up
P41 pull-up control bit
0: No pull-up
1: Pull-up
P42 pull-up control bit
0: No pull-up
1: Pull-up
P43 pull-up control bit
0: No pull-up
1: Pull-up
P44 pull-up control bit
0: No pull-up
1: Pull-up
P45 pull-up control bit
0: No pull-up
1: Pull-up
P46 pull-up control bit
0: No pull-up
1: Pull-up
P47 pull-up control bit
Note: Pull-up conwhen the corresponding bit
of the poregister is “0” (input).
When 1” (output), pull-up cannot be set
to thich pull-up is selected.
0: No pull-up
1: Pull-up
b7
b0
Port P5 pull-up control register
(PULL5: address 0FF516
)
P50 pull-up control bit
0: No pull-up
1: Pull-up
P51 pull-up c
0: No pu
1: Pu
P5rol bit
p
p
ll-up control bit
No pull-up
1: Pull-up
P54 pull-up control bit
0: No pull-up
1: Pull-up
P55 pull-up control bit
0: No pull-up
1: Pull-up
P56 pull-up control bit
0: No pull-up
1: Pull-up
P57 pull-up control bit
Note: Pull-up control is valid when the corresponding bit
of the port direction register is “0” (input).
When that bit is “1” (output), pull-up cannot be set
to the port of which pull-up is selected.
0: No pull-up
1: Pull-up
Fig. 17 Structure of port pull-up control register (3)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-21
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Port P6 pull-up control register
(PULL6: address 0FF616
)
P60 pull-up control bit
0: No pull-up
1: Pull-up
P61 pull-up control bit
0: No pull-up
1: Pull-up
P62 pull-up control bit
0: No pull-up
1: Pull-up
P63 pull-up control bit
0: No pull-up
1: Pull-up
P64 pull-up control bit
0: No pull-up
1: Pull-up
P65 pull-up control bit
0: No pull-up
1: Pull-up
P66 pull-up control bit
0: No pull-up
1: Pull-up
P67 pull-up control bit
Note: Pull-up coid when the corresponding bit
of the pn register is “0” (input).
Whe“1” (output), pull-up cannot be set
to which pull-up is selected.
0: No pull-up
1: Pull-up
Fig. 18 Structure of port pull-up control register (4)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-22
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
INTERRUPTS
ꢀ Notes
The 3804 group (Spaec. H)’s interrupts are a type of vector and
occur by 16 sources among 23 sources: nine external, thirteen in-
ternal, and one software.
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 003A16)
Timer XY mode register (address 002316)
Timer Z mode register (address 002A16)
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
2
I C START/STOP condition control register
(address 001616)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt source selection register
(address 003916)
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
The reset and the BRK instruction cannot be disabled with any
flag or bit. The I (interrupt disable) flag disables all interrupts ex-
cept the reset and the BRK instruction interrupt.
When several interrupt requests occur at the same time, the inter-
rupts are received according to priority.
ꢀSet the corresponding interrupt enable bit to “0” (disabled).
ꢀSet the interrupt edge select bit or rrupt source select bit
to “1”.
ꢀSet the corresponding interrubit to “0” after 1 or more
instructions have been ex
Interrupt Operation
By acceptance of an interrupt, the following operations are auto-
ꢀSet the corresponding nable bit to “1” (enabled).
matically performed:
1. The contents of the program counter and the processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Which of each combination of the following interrupt sources
be selected by the interrupt source selection register (
003916).
1. INT0 or Timer Z
2. Serial I/O1 transmission or SCL, SDA
3. CNTR0 or SCL, SDA
4. CNTR1 or Serial I/O3 reception
5. Serial I/O2 or Timer Z
2
6. INT2 or I C
7. INT4 or CNTR2
8. A/D converter or serial I/O3 ion
External Interrupelection
The occurrence soure external interrupt INT0 and INT4
can be selected from eitinput from INT00 and INT40 pin, or in-
put from INT01 and INT41 pin by the INT0, INT4 interrupt switch bit
of interrupt edge selection register (bit 6 of address 003A16).
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-23
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Table 6 Interrupt vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Interrupt Source
Priority
High
Low
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Reset (Note 2)
INT0
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
Timer Z
INT1
At timer Z underflow
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
3
4
5
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
Serial I/O1
reception
Valid when serial I/O1 is selected
At completion of serial I/O1 data
reception
Serial I/O1
transmission
Valid when serial I/O1 is selected
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At detection of either rising or
falling edge of SCL or SDA
SCL, SDA
External interrupt
(active edge selectable)
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
8
Se timer underflow
9
At detection of either rising
falling edge of CNTR0 input
10
nal interrupt
tive edge selectable)
SCL, SDA
CNTR1
At detection of either r
falling edge of SCL or
External interrupt
(active edge selectable)
At detection of eior
falling edge of Ct
11
FFE816
External interrupt
(active edge selectable)
FFE916
Serial I/O3
reception
At completioI/O3 data
reception
Valid when serial I/O3 is selected
12
13
Serial I/O2
FFE716
FFE516
FFE616
FFE416
At comserial I/O2 data
tranr reception
Valid when serial I/O2 is selected
Timer Z
INT2
Anderflow
ction of either rising or External interrupt
edge of INT2 input
(active edge selectable)
2
completion of data transfer
I C
At detection of either rising or External interrupt
INT3
14
15
FFE316
FFE116
F
6
falling edge of INT3 input
(active edge selectable)
At detection of either rising or External interrupt
INT4
falling edge of INT4 input
(active edge selectable)
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR2 input
CNTR2
A/D converter
At completion of A/D conversion
16
1
F
FDD16
FFDE16
FFDC16
Valid when serial I/O3 is selected
Non-maskable software interrupt
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Serial I/O3
transmission
At BRK instruction execution
BRK instruction
Notes 1: Vector addresseerrupt jump destination addresses.
2: Reset function e way as an interrupt with the highest priority.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-24
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 19 Interrupt control
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-25
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16)
0 : Falling edge active
1 : Rising edge active
INT0 active edge selection bit
INT1 active edge selection bit
Not used (returns “0” when read)
INT2 active edge selection bit
INT3 active edge selection bit
INT4 active edge selection bit
INT0, INT4 interrupt switch bit
0 : INT00, INT40 interrupt
0 : Falling edge active
1 : Rising edge active
1 : INT01, INT41 interrupt
Not used (returns “0” when read)
b7
b0
b7
b0
Interrupt request register 1
(IREQ1 : address 003C16)
Interrupt request register 2
(IREQ2 : address 003D16)
INT0/Timer Z interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit/SCL, SDA interrupt
request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 2 interrupt request bit
CNTR0/SCL, SDA interrupt request bit
CNTR1/Serial I/O3 receive interrupt
request bit
Serial I/O2/Timeupt request bit
INT2/I2C intert bit
INT3 interrbit
INT4/CNt request bit
AD coal I/O3 transmit
intet bit
Nurns “0” when read)
0 : No inest issued
1 : Intest issued
b7
b0
b7
rupt control register 2
CON2 : address 003F16)
Interrupt control register 1
(ICON1 : address 003E16)
INT0/Timer Z interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit/SCL, SDA interrupt
enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
CNTR0/SCL, SDA interrupt enable bit
CNTR1/Serial I/O3 receive interrupt
enable bit
Serial I/O2/Timer Z interrupt enable bit
INT2/I2C interrupt enable bit
INT3 interrupt enable bit
INT4/CNTR2 interrupt enable bit
AD converter/Serial I/O3 transmit
interrupt enable bit
Not used (returns “0” when read)
0 : Interrupts disabled
1 : Interrupts enabled
b0
b7
Interrupt source sister
(INTSEL: addr
INT0/Tiupt source selection bit
0 : It
1 terrupt
(Do not write “1” to these bits simultaneously.)
(Do not write “1” to these bits simultaneously.)
imer Z interrupt source selection bit
l I/O2 interrupt
er Z interrupt
l I/O1 transmit/SCL, SDA interrupt source selection bit
: Serial I/O1 transmit interrupt
1 : SCL, SDA interrupt
CNTR0/SCL, SDA interrupt source selection bit
0 : CNTR0 interrupt
1 : SCL, SDA interrupt
INT4/CNTR2 interrupt source selection bit
0 : INT4 interrupt
1 : CNTR2 interrupt
INT2/I2C interrupt source selection bit
0 : INT2 interrupt
1 : I2C interrupt
CNTR1/Serial I/O3 receive interrupt source selection bit
0 : CNTR1 interrupt
1 : Serial I/O3 receive interrupt
AD converter/Serial I/O3 transmit interrupt source selection bit
0 : A/D converter interrupt
1 : Serial I/O3 transmit interrupt
Fig. 20 Structure of interrupt-related registers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-26
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
TIMERS
Timer X and Timer Y
ꢀ8-bit Timers
The timer X and timer Y can each select one of four operating
The 3804 group (Spec. H) has four 8-bit timers: timer 1, timer 2,
modes by setting the timer XY mode register (address 002316).
timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
(1) Timer mode
ꢀMode selection
This mode can be selected by setting “00” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt re-
quest bit corresponding to that timer is set to “1”.
ꢀExplanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 002316).
When the timer reaches “0016”, an underflow occurs at the next
count pulse and the contents of timer ltch are reloaded into the
timer and the count is continued.
ꢀTimer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B16). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), XIN is selected. When these bits are“10”
(low-speed mode), XCIN is selected.
(2) Pulse output mod
ꢀMode selection
This mode can be selecng “01” to the timer X operating
mode bits (bits 1 and e timer Y operating mode bits (bits
5 and 4) of the time register (address 002316).
ꢀExplanation on
ꢀPrescaler 12
The prescaler 12 counts the output of the timer divider. The count
source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512,
1/1024 of f(XIN) or f(XCIN).
The operasame as the timer mode’s. Moreover the
pulse werted each time the timer underflows is output
from NTR1 pin. Regardless of the timer counting or not
thCNTR0/CNTR1 pin is initialized to the level of speci-
heir active edge switch bits when writing to the timer.
the CNTR0 active edge switch bit (bit 2) and the CNTR1 ac-
e edge switch bit (bit 6) of the timer XY mode register (address
002316) is “0”, the output starts with “H” level. When it is “1”, the
output starts with “L” level.
Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and p
riodically set the interrupt request bit.
ꢀPrescaler X and prescaler Y
Switching the CNTR0 or CNTR1 active edge switch bit will reverse
the output level of the corresponding CNTR0 or CNTR1 pin.
ꢀPrecautions
The prescaler X and prescaler Y count the outpumer
divider or f(XCIN). The count source is selected r 12, X
count source selection register (address 000e timer Y,
Z count source selection register (addre) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN)
or f(XCIN); and f(XCIN).
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to output in this mode.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-27
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(3) Event counter mode
ꢀMode selection
This mode can be selected by setting “10” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
ꢀExplanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR0 or CNTR1 pin. The
valid edge for the count operation depends on the CNTR0 active
edge switch bit (bit 2) or the CNTR1 active edge switch bit (bit 6)
of the timer XY mode register (address 002316). When it is “0”, the
rising edge is valid. When it is “1”, the falling edge is valid.
ꢀPrecautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to input in this mode.
(4) Pulse width measurement mode
ꢀMode selection
This mode can be selected by setting “11” to the timer X operating
mode bits (bits 1 and 0) and the timer Y operating mode bits (bits
5 and 4) of the timer XY mode register (address 002316).
ꢀExplanation of operation
When the CNTR0 active edge switch bit (bit 2) or the CNTR1 ac-
tive edge switch bit (bit 6) of the timer XY mode register (address
002316) is “1”, the timer counts during the term of one falling edge
of CNTR0/CNTR1 pin input until the next rising edge of input (“L”
term). When it is “0”, the timer counts during the term of one rising
edge input until the next falling edge input (“H” term).
ꢀPrecautions
Set the double-function port of CNTR0/CNTR1 pin and port P54/
P55 to input in this mode.
The count operation can be stopped by setting “1” to the tim
count stop bit (bit 3) and the timer Y count stop bit (bit 7
timer XY mode register (address 002316). The interrupt
is set to “1” each time the timer underflows.
•Precautions when switching count source
When switching the count source by the timed Y count
source selection bits, the value of timer cred in incon-
siderable amount owing to generating es on the count
input signals.
Therefore, select the timer counefore setting the value
to the prescaler and the timer
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-28
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
X
IN
“00”
“01”
(1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, 1/1024)
Divider
Count source
selection bit
“10”
X
CIN
Data bus
Main clock
division ratio
selection bits
Prescaler X latch (8)
Timer X latch (8)
f(XCIN
)
Pulse width
Timer mode
Pulse output mode
measurement
mode
To timer X interrupt
request bit
Prescaler X (8)
Timer X (8)
CNTR
switch bit
0 active edge
Event
counter
mode
Timer X count stop bit
P5
4
/CNTR
0
“0”
“1”
To CNTR
0 interrupt
request bit
CNTR
edge switch bit
0
active
“1”
Q
Q
T
Toggle flip-flop
R
“0”
Port P5
latch
4
Timer X latc
Pulse ou
Port P5
4
direction register
Pulse output mode
Data bus
Count source selection bit
Clock for timer Y
f(XCIN
imer Y latch (8)
Timer Y (8)
Prescaler Y latch (8)
Pulse width
measurement
mode
)
Timer mode
Pulse output mode
To timer Y interrupt
request bit
Prescal
CNTR
switch bit
1
active edge
Event
counter
mode
Timer Y count stop
P55/CNTR1
“0”
“1”
To CNTR
1 interrupt
request bit
CNTR
edge switch
1
active
Q
T
Toggle flip-flop
R
Port P5
latch
5
Timer Y latch write pulse
Pulse output mode
Port P5
direction register
5
Pulse output mode
Data bus
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Prescaler 12 latch (8)
Prescaler 12 (8)
To timer 2 interrupt
request bit
Clo
To timer 1 interrupt
request bit
Fig. 21 Block diagram of timer X, timer Y, timer 1, and timer 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-29
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Timer XY mode register
(TM : address 002316
)
Timer X operating mode bits
b1 b0
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
CNTR
0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge in event counter mode
1 : Interrupt at rising edge
Count at falling edge in event counter mode
Timer X count stop bit
0 : Count start
1 : Count stop
Timer Y operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurem
CNTR
1 active edge switc
0 : Interrupt at falling e
Count at rising et counter mode
1 : Interrupt at risi
Count at fallevent counter mode
Timer Y co
0 : Coun
1 : Co
Fig. 22 Structure of timer XY mode register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-30
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Timer 12, X count source selection register
(T12XCSS : address 000E16
)
Timer 12 count source selection bits
b3b2b1b0
1010 :
1011 :
1100 :
1101 :
1110 :
1111 :
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIINN)/1024 or f(XCIN)/1024
Not used
Timer X count source selection bits
b7b6b5b4
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1011 :
1100 :
1101 : Not
1110 :
1111 :
1 0 1 0 : f(XCININ
)
b7
b0
Timer Y, Z count source selecer
(TYZCSS : address 000F16
Timer Y count source bits
b3b2b1b0
0 0 0 0 : f(X ))/2
0 0 0 1 : f(XINXIN)/4
0 0 1 0 : f(f(XCCIINN)/8
0 0 1 1 : or f(X )/16
0 1 0 2 or f(XCIN)/32
0 1 0 64 or f(XCCIINN)/64
0 1 )/128 or f(X )/128
0 XN)/256 or f(XCIN)/256
f(XIN)/512 or f(XCCIINN)/512
: f(XIN)/1024 or f(XCIN)/1024
1011 :
1100 :
1101 :
1110 :
1111 :
Not used
0 : f(XCININ
)
er Z count source selection bits
7b6b5b4
0 0 0 0 : f(X )/2 or f(X )/2
0 0 0 1 : f(XIN)/4 or f(XCIN)/4
0 0 1 0 : f(XIN)/8 or f(XCCIINN)/8
0 0 1 1 : f(XIN)/16 or f(X )/16
0 1 0 0 : f(XIN)/32 or f(XCIN)/32
0 1 0 1 : f(XIN)/64 or f(XCCIINN)/64
0 1 1 0 : f(XIN)/128 or f(X )/128
0 1 1 1 : f(XIN)/256 or f(XCIN)/256
1 0 0 0 : f(XIN)/512 or f(XCCIINN)/512
1 0 0 1 : f(XIN)/1024 or f(XCIN)/1024
1011 :
1100 :
1101 : Not used
1110 :
1111 :
1 0 1 0 : f(XCININ
)
Fig. 23 Structure of timer 12, X and timer Y, Z count source selection registers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-31
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
●16-bit Timer
(2) Event counter mode
The timer Z is a 16-bit timer. When the timer reaches “000016”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When the timer underflows, the interrupt request bit corresponding
to the timer Z is set to “1”.
●Mode selection
This mode can be selected by setting “000” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “1” to the timer/event
counter mode switch bit (bit 7) of the timer Z mode register (ad-
dress 002A16).
When reading/writing to the timer Z, perform reading/writing to
both the high-order byte and the low-order byte. When reading the
timer Z, read from the high-order byte first, followed by the low-or-
der byte. Do not perform the writing to the timer Z between read
operation of the high-order byte and read operation of the low-or-
der byte. When writing to the timer Z, write to the low-order byte
first, followed by the high-order byte. Do not perform the reading
to the timer Z between write operation of the low-order byte and
write operation of the high-order byte.
The valid edge for the count operation depends on the CNTR2 ac-
tive edge switch bit (bit 5) of the timer Z mode register (address
002A16). When it is “0”, the rising edge is valid. When it is “1”, the
falling edge is valid.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
The operation is the same as the timer mode’s.
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
The timer Z can select the count source by the timer Z count
source selection bits of timer Y, Z count source selection register
(bits 7 to 4 at address 000F16).
Figure 26 shows the timing chart of tr/event counter mode.
Timer Z can select one of seven operating modes by setting the
timer Z mode register (address 002A16).
(3) Pulse output mod
●Mode selection
This mode can be selecing “001” to the timer Z operat-
ing mode bits (bits d setting “0” to the timer/event
counter mode swiof the timer Z mode register (address
002A16).
(1) Timer mode
●Mode selection
This mode can be selected by setting “000” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count sotion
In high- speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 2 or 1/1024 of f(XIN); or f(XCIN) can be selected as
thurce.
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected as
the count source.
eed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
1/1024 of f(XCIN); or f(XCIN) can be selected as the count
urce.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/25
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as th
source.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
●Interrupt
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR2 pin. When the CNTR2 active edge switch bit (bit 5) of
the timer Z mode register (address 002A16) is “0”, the output starts
with “H” level. When it is “1”, the output starts with “L” level.
●Precautions
When an underflow occurs, the INT0/timer Z intest bit
(bit 0) of the interrupt request register 1 (addr6) is set to
“1”.
●Explanation of operation
During timer stop, usually write datand a timer at the
same time to set the timer value.
The double-function port of CNTR2 pin and port P47 is automati-
cally set to the timer pulse output port in this mode.
The output from CNTR2 pin is initialized to the level depending on
CNTR2 active edge switch bit by writing to the timer.
When the value of the CNTR2 active edge switch bit is changed,
the output level of CNTR2 pin is inverted.
The timer count operation is setting “0” to the timer Z
count stop bit (bit 6) of Z mode register (address
002A16).
When the timer reach16”, an underflow occurs at the next
count pulse and the conts of timer latch are reloaded into the
timer and the count is continued.
Figure 27 shows the timing chart of the pulse output mode.
When writing data to the timer during operation, the data is written
only into the latch. Then the new latch value is reloaded into the
timer at the next underflow.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-32
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(4) Pulse period measurement mode
ꢀMode selection
(5) Pulse width measurement mode
ꢀMode selection
This mode can be selected by setting “010” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
This mode can be selected by setting “011” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
ꢀCount source selection
ꢀCount source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
ꢀInterrupt
ꢀInterrupt
The interrupt at an underflow is the same as the timer mode’s.
When the pulse period measurement is completed, the INT4/
CNTR2 interrupt request bit (bit 5) of the interrupt request register
2 (address 003D16) is set to “1”.
The interrupt at an underflow is the same as the timer mode’s.
When the pulse widths measurement is completed, the INT4/
CNTR2 interrupt request bit (bit 5) of errupt request register
2 (address 003D16) is set to “1”.
ꢀExplanation of operation
ꢀExplanation of operation
The cycle of the pulse which is input from the CNTR2 pin is mea-
sured. When the CNTR2 active edge switch bit (bit 5) of the timer
Z mode register (address 002A16) is “0”, the timer counts during
the term from one falling edge of CNTR2 pin input to the next fall-
ing edge. When it is “1”, the timer counts during the term from one
rising edge input to the next rising edge input.
When the valid edge of measurement completion/start is detected,
the 1’s complement of the timer value is written to the timer latch
and “FFFF16” is set to the timer.
The pulse width which is inhe CNTR2 pin is measured.
When the CNTR2 active h bit (bit 5) of the timer Z mode
register (address 00, the timer counts during the term
from one rising edthe next falling edge input (“H” term).
When it is “1”, counts during the term from one falling
edge of CNut to the next rising edge of input (“L” term).
When thge of measurement completion is detected, the
1’s cof the timer value is written to the timer latch.
Wlid edge of measurement completion/start is detected,
is set to the timer.
Furthermore when the timer underflows, the timer Z interrupt re-
quest occurs and “FFFF16” is set to the timer. When reading the
timer Z, the value of the timer latch (measured value) is read. Th
measured value is retained until the next measurement com
tion.
the timer Z underflows, the timer Z interrupt occurs and
FF16” is set to the timer Z. When reading the timer Z, the value
of the timer latch (measured value) is read. The measured value is
retained until the next measurement completion.
ꢀPrecautions
ꢀPrecautions
Set the double-function port of CNTR2 pin and port t in
this mode.
Set the double-function port of CNTR2 pin and port P47 to input in
this mode.
A read-out of timer value is impossible in this timer can
be written to only during timer stop (no meof pulse pe-
riod).
A read-out of timer value is impossible in this mode. The timer can
be written to only during timer stop (no measurement of pulse
widths).
Since the timer latch in this mode is d for the read-out of
measured values, do not perform operation during mea-
surement.
Since the timer latch in this mode is specialized for the read-out of
measured values, do not perform any write operation during mea-
surement.
“FFFF16” is set to the timetimer underflows or when the
valid edge of measurecompletion is detected. Conse-
quently, the timer vart of pulse period measurement
depends on the timer vajust before measurement start.
Figure 28 shows the timing chart of the pulse period measurement
mode.
“FFFF16” is set to the timer when the timer underflows or when the
valid edge of measurement start/completion is detected. Conse-
quently, the timer value at start of pulse width measurement
depends on the timer value just before measurement start.
Figure 29 shows the timing chart of the pulse width measurement
mode.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-33
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(6) Programmable waveform generating mode
●Mode selection
•“L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “L” is output from the CNTR2 pin. When an underflow
occurs, “H” is output. The “L” one-shot pulse width is set by the
setting value to the timer Z low-order and high-order. When trigger
generating is detected during timer count stop, although “L” is out-
put from the CNTR2 pin, “L” output state continues because an
underflow does not occur.
This mode can be selected by setting “100” to the timer Z operat-
ing mode bits (bits 2 to 0) and setting “0” to the timer/event
counter mode switch bit (b7) of the timer Z mode register (address
002A16).
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be selected
as the count source.
●Precautions
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/
512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the count
source.
Set the double-function port of INT1 pin and port P42 to input in
this mode.
Set the double-function port of CNTR2 pin and port P22 is auto-
matically set to the programmable one-shot generating port in this
mode.
●Interrupt
The interrupt at an underflow is the same as the timer mode’s.
●Explanation of operation
This mode cannot be used in low-speed mode.
If the value of the CNTR2 active edge h bit is changed during
one-shot generating enabled or one-shot pulse, then
the output level from CNTR2 p.
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A16) from the CNTR2 pin each
time the timer underflows.
Figure 31 shows the timinhe programmable one-shot
generating mode.
Changing the value of the output level latch and the timer latch af-
ter an underflow makes it possible to output an optional waveform
from the CNTR2 pin.
●Notes regall modes
●Timer Z writ
●Precautions
The double-function port of CNTR2 pin and port P47 is automati-
cally set to the programmable waveform generating port in this
mode.
Which write n be selected by the timer Z write control bit
(bit 3) of Z mode register (address 002A16), writing data
to boh and the timer at the same time or writing data
ontch.
Figure 30 shows the timing chart of the programmable waveform
generating mode.
operation “writing data only to the latch” is selected, the
is set to the timer latch by writing data to the address of
er Z and the timer is updated at next underflow. After reset re-
lease, the operation “writing data to both the latch and the timer at
the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
(7) Programmable one-shot generating mode
●Mode selection
This mode can be selected by setting “101” to the timer Z
ing mode bits (bits 2 to 0) and setting “0” to the ti
counter mode switch bit (b7) of the timer Z mode regess
002A16).
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
●Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/32, 1/64, 1/
128, 1/256, 1/512 or 1/1024 of f(XIN); or n be selected as
the count source.
●Timer Z read control
A read-out of timer value is impossible in pulse period measure-
ment mode and pulse width measurement mode. In the other
modes, a read-out of timer value is possible regardless of count
operating or stopped.
●Interrupt
The interrupt at an underflow e as the timer mode’s.
The trigger to generate oulse can be selected by the
INT1 active edge select1) of the interrupt edge selection
register (address 003en it is “0”, the falling edge active is
selected; when it is “1”, trising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1 interrupt
request bit (bit 1) of the interrupt request register 1 (address
003C16) is set to “1”.
However, a read-out of timer latch value is impossible.
●Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2 ac-
tive edge switch bit and the INT1 active edge selection bit.
●Switch of count source
When switching the count source by the timer Z count source se-
lection bits, the value of timer count is altered in inconsiderable
amount owing to generating of thin pulses on the count input sig-
nals.
●Explanation of operation
•“H” one-shot pulse; Bit 5 of timer Z mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at mode se-
lection. When trigger generation (input signal to INT1 pin) is
detected, “H” is output from the CNTR2 pin. When an underflow
occurs, “L” is output. The “H” one-shot pulse width is set by the
setting value to the timer Z register low-order and high-order.
When trigger generating is detected during timer count stop, al-
though “H” is output from the CNTR2 pin, “H” output state
continues because an underflow does not occur.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
●Usage of CNTR2 pin as normal I/O port
To use the CNTR2 pin as normal I/O port P47, set timer Z operat-
ing mode bits (b2, b1, b0) of timer Z mode register (address
002A16) to “000”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-34
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
CNTR
switch bit
2
active edge
Programmable one-shot
generating mode
Data bus
“1”
“0”
P42/INT1
Programmable one-shot
generating circuit
Programmable one-shot
generating mode
To INT1 interrupt
request bit
Programmable waveform
generating mode
D
T
Output level latch
Q
Pulse output mode
CNTR
2
active edge switch bit
Pulse output mode
S
“0”
Q
Q
T
“1”
“001”
“100”
“101”
Timer Z operating
mode bits
Timer Z low-order latch Timer Z high-order latch
Timer Z low-order Timer Z high-order
Port P4
latch
7
To timer Z interrupt
request bit
Port P4
7
direction register
Pulse period measurement mode
Pulse width measurement mode
Edge detection circuit
To CNTR
request bit
2 interrupt
“1”
“0”
f(XCIN
)
P47/CNTR2
Timer Z count stop bit
CNTR
switch bit
2 active edge
Event
nter mode
switch bit
XIN
urce
ion bit
Divider
(1/2, 1/4, 11/64, 1/128, 1/256, 1/512, 1/1024)
XCIN
Fig. 24 Block diagram of timer Z
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-35
HARDWARE
3804 Group (Spec.H)
b7
FUNCTIONAL DESCRIPTION
b0
Timer Z mode register
(TZM : address 002A16
)
Timer Z operating mode bits
b2b1b0
0 0 0 : Timer/Event counter mode
0 0 1 : Pulse output mode
0 1 0 : Pulse period measurement mode
0 1 1 : Pulse width measurement mode
1 0 0 : Programmable waveform generating mode
1 0 1 : Programmable one-shot generating mode
1 1 0 : Not available
1 1 1 : Not available
Timer Z write control bit
0 : Writing data to both latch and timer simultansly
1 : Writing data only to latch
Output level latch
0 : “L” output
1 : “H” output
CNTR
active edge switch bit
2
0 : •Event counter mode: Cising edge
•Pulse output mode: putting “H”
•Pulse period measmode: Measurement
between two fales
•Pulse width mment mode: Measurement of
“H” term
•Programne-shot generating mode: After
start o“L”, “H” one-shot pulse generated
•Intealling edge
1 : •Enter mode: Count at falling edge
utput mode: Start outputting “L”
e period measurement mode: Measurement
tween two rising edges
Pulse width measurement mode: Measurement of
“L” term
•Programmable one-shot generating mode: After
start outputting “H”, “L” one-shot pulse generated
•Interrupt at rising edge
Timer Z count stop bit
0 : Count start
1 : Count stop
Timer/Event counter mode switch bit (Note)
0 : Timer mode
1 : Event counter mode
Note: When selecting the modes except the timer/event
counter mode, set “0” to this bit.
Fig. 25 Structure of timer Z mode register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-36
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
FFFF16
TL
000016
TR
TR
TR
TL : Value set to timer latch
TR : Timer interrupt request
Fig. 26 Timing chart of timer/event counter mode
FFFF16
TL
000016
TR
TR
TR
Waveform o
from CN
CNTR
2
CNTR
2
TL : Value set to timer latch
TR : Timer interrupt request
CNTR
2
: CNTR
2 interrupt request
(CNTR
2
active edge switch bit = “0”; Falling edge active)
Fig. 27 Timing chart of pulse output mode
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-37
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
000016
T3
T2
T1
FFFF16
TR
TR
T2
T3
FFFF16 + T1
FFFF16
Signal input from
CNTR pin
2
CNTR
2
CNTR
2
CNTR
2
TR2
CNTR
TR : Timer interrupt request
CNTR : CNTR interrupt request
2 of rising edge active
2
2
Fig. 28 Timing chart of pulse period measurement mode (Measuring term berising edges)
000016
T3
T2
T1
FFFF16
TR
T1
FFFF16 + T2
T3
Signal input fr
CNT
CNTR
2
CNTR
interrupt of rising edge active; Measurement of “L” width
TR : Timer interrupt request
CNTR : CNTR interrupt request
2
CNTR2
CNTR
2
2
2
Fig. 29 Timing chart of pulse width measurement mode (Measuring “L” term)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-38
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
FFFF16
T3
L
T2
T1
000016
Signal output
from CNTR2 pin
L
T3
T1
TR
CNTR2
L : Timer initial value
T2
TR
TR
TR
CNTR2
TR : Timer interrupt request
CNTR2 : CNTR2 interrupt request
(CNTR2 active edge switch bit = “0”; Fae active)
Fig. 30 Timing chart of programmable waveform generating mode
FFFF16
L
TR
TR
TR
Signal input from
INT
1
Sigt
fropin
L
L
L
2
CNTR
2
CNTR2
L : One-shot pulse width
TR : Timer interrupt request
CNTR : CNTR interrupt request
(CNTR active edge switch bit = “0”; Falling edge active)
2
2
2
Fig. 31 Timing chart of programmable one-shot generating mode (“H” one-shot pulse generating)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-39
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
SERIAL INTERFACE
(1) Clock Synchronous Serial I/O Mode
Serial I/O1
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6 of address 001A16) to “1”.
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O1. A dedicated timer is also provided for
baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Serial I/O1 control register
Receive buffer full flag (RBF)
Address 001A16
Address 001816
Receive buffer register 1
Receive shift register 1
Receive interrupt request (RI)
P44/RXD1
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
(f(XCIN) in low-speed mode)
f(XIN
)
Baud rate generator 1
Address 001C16
1/4
1/4
Clock c
Falling-edge detector
P47/SRDY1
F/F
Shift clock
Transmit shift completion flag (TSC)
mit interrupt source selection bit
P4
5/T
XD1
Transmit shift register 1
Transmit buffer reg
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
816
Data b
Fig. 32 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD1
Serial input
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Receive enabY1
Write pulse transmit
buffer register (ass 001816)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 33 Operation of clock synchronous serial I/O1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-40
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Address 001816
Address 001A16
Serial I/O1 control register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Receive buffer register 1
Character length selection bit
7 bits
P4
4/RX
D
1
ST detector
Receive shift register 1
1/16
8 bits
UART1 l register
PE FE
SP detector
ss 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
nsmit interrupt source selection bit
P45/TXD1
Transmit shift reg
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit b
ss 001816
Address 001916
Serial I/O1 status register
Dat
Fig. 34 Block diagram of UART serial I/O1
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TS
TBE=0
TSC=1ꢀ
TBE=1
Serial output TXD1
ST
SP
D0
D1
ST
D0
D1
SP
ꢀ Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input RXD1
D0
D1
ST
D0
D1
Notes
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig. 35 Operation of UART serial I/O1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-41
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
[Serial I/O1 Control Register (SIO1CON)]
001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART1 Control Register (UART1CON)]
001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer, and one bit (bit 4) which is al-
ways valid and sets the output structure of the P45/TXD1 pin.
[Serial I/O1 Status Register (SIO1STS)]
001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O1 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register 1/Receive B
Register 1 (TB1/RB1)] 001816
The transmit buffer register 1 and the receive buffer are
located at the same address. The transmit buffer ly and
the receive buffer is read-only. If a character b7 bits, the
MSB of data stored in the receive buffer is
[Baud Rate Generator 1 (001C16
The baud rate generator determiud rate for serial trans-
fer.
The baud rate generator direquency of the count source
by 1/(n + 1), where n is written to the baud rate genera-
tor.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-42
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
b0
b7
Serial I/O1 status register
(SIO1STS : address 001916
Serial I/O1 control register
(SIO1CON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as normal I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift eration is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable
0: Receive di
1: Receive
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial election bit (SIOM)
0: Cronous (UART) serial I/O
1hronous serial I/O
Not used (returns “1” when read)
O1 enable bit (SIOE)
rial I/O1 disabled
pins P4
1: Serial I/O1 enabled
(pins P4 to P4 operate as serial I/O pins)
4 to P47 operate as normal I/O pins)
4
7
b7
b0
UART1 control register
(UART1CON : address 001B16
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enable
Parity selection bit (
0: Even parity
1: Odd parity
Stop bit len bit (STPS)
0: 1 sto
1: 2
-channel output disable bit (POFF)
output (in output mode)
annel open drain output (in output mode)
ot used (return “1” when read)
Fig. 36 Structure of serial I/O1 control registers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-43
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀ Notes concerning serial I/O1
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
ꢀ Note
ꢀ Note
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O1 enable
bit to “0”.
Clear the serial I/O1 enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
ꢀ Reason
ꢀ Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internaly shifting is output to the
TxD1 pin and an operation failure oc
1.2 Stop of receive operation
2.2 Stop of receive operation
ꢀ Note
ꢀ Note
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O1 enable bit to “0” (serial I/O disabled).
Clear the receive enable receive disabled).
2.3 Stop of transe operation
1.3 Stop of transmit/receive operation
ꢀ Note
ꢀ Note 1 (onlsion operation is stopped)
Clear the trble bit to “0” (transmit disabled). The trans-
mission does not stop by clearing the serial I/O1 enable
bit to
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
n
transmission is not stopped and the transmission circuit is
initialized even if only the serial I/O1 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD1, RxD1, SCLK1, and SRDY1 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O1 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD1 pin and an operation failure occurs.
ꢀ Reason
In the clock synchronous serial I/O mode, the same clock
for transmission and reception. If any one of transmiss
ception is disabled, a bit error occurs because tranand
reception cannot be synchronized.
In this mode, the clock circuit of the transmissalso oper-
ates for data reception. Accordingly, the trn circuit does
not stop by clearing only the transmit to “0” (transmit
disabled). Also, the transmission cirinitialized by clear-
ing the serial I/O1 enable bit to I/O disabled) (refer to
1.1).
ꢀ Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-44
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
3. SRDY1 output of reception side
7. Transmit interrupt request when transmit enable bit is set
ꢀ Note
ꢀ Note
When signals are output from the SRDY1 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY1 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
When using the transmit interrupt, take the following sequence.
ꢀ Set the serial I/O1 transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O1 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
4. Setting serial I/O1 control register again
ꢀ Note
ꢀ Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
ꢀ Reason
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.”
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to “1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O control register
Can be set with the
↓
LDM instruction at the
same time
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
5. Data transmission control with referring to transmit shift
register completion flag
ꢀ Note
After the transmit data is written to the transmit buffer register, th
transmit shift register completion flag changes from “1” to “0”
a delay of 0.5 to 1.5 shift clocks. When data transmission
trolled with referring to the flag after writing the data to t
buffer register, note the delay.
6. Transmission control when external cloted
ꢀ Note
When an external clock is used as the us clock for data
transmission, set the transmit enablat “H” of the SCLK1
input level. Also, write data to thbuffer register at “H” of
the SCLK1 input level.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-45
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
Serial I/O2
b0
Serial I/O2 control register
(SIO2CON : address 001D16)
The serial I/O2 function can be used only for clock synchronous
serial I/O2.
Internal synchronous clock selection bits
b2 b1 b0
For clock synchronous serial I/O2, the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
1 1 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
[Serial I/O2 Control Register (SIO2CON)]
001D16
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
The serial I/O2 control register contains eight bits which control
various serial I/O2 functions.
SRDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronock selection bit
0: External clock
1: Internal cloc
P51/SOUT2 Pput disable bit
0: CMOoutput mode)
1: N-n drain output (in output mode)
Fig. 37 Structure O2 control register
Internal synchronous
clock selection bits
Data bus
f(XIN
)
/64
(f(XCIN) in low-speed mode)
1/128
1/256
P53 latch
Serial I/O2 s
clbit
“0”
“1”
P53/SRDY2
S
RDY2
“1”
SRDY2 output enable
“0”
External clock
P52 la
“0
P52/SCLK2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
Serial I/Otion bit
51 latch
“0”
P51/SOUT2
“1”
Serial I/O2 port selection bit
Serial I/O2 register (8)
P50/SIN2
Address 001F16
Fig. 38 Block diagram of serial I/O2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-46
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output
SOUT2
D2
D0
D1
D3
D4
D5
D6
D7
Serial I/O2 input SIN2
Receive enable signal SRDY2
Serial I/O2 interpt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio of f(XIN), or f(XCIN) ed mode, can be
selected by setting bits 0 to 2 of the serial I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high imper transfer completion.
Fig. 39 Timing of serial I/O2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-47
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Serial I/O3
(1) Clock Synchronous Serial I/O Mode
Serial I/O3 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O3. A dedicated timer is also provided for
baud rate generation.
Clock synchronous serial I/O3 mode can be selected by setting
the serial I/O3 mode selection bit of the serial I/O3 control register
(bit 6 of address 003216) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Serial I/O3 control register
Receive buffer full flag (RBF)
Address 003216
Address 003016
Receive buffer register 3
Receive shift register 3
Receive interrupt request (RI)
P34/RXD3
Shift clock
Clock control circuit
P36/SCLK3
Serial I/O3 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
(f(XCIN) in low-speed mode)
f(XIN
)
Baud rate generator 3
Address 002F16
1/4
1/4
Clock
Falling-edge detector
P37/SRDY3
F/F
Shift clock
Transmit shift completion flag (TSC)
smit interrupt source selection bit
P3
5/T
XD3
Transmit shift register 3
Transmit buffer re
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O3 status register
Address 003116
016
Data
Fig. 40 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input Rx
3
D
0
0
D
1
D
2
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
D
D1
D
D
D
D
D
D
Receive enable s
Write pulse to smit
buffer register (ad03016
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O3
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 41 Operation of clock synchronous serial I/O3
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-48
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O3 mode selection bit of the serial I/O3 control
register to “0”.
two buffers have the same address in a memory. Since the shift
register cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Data bus
Serial I/O3 control register Address 003216
Address 003016
Receive buffer register 3
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
Character length selection bit
P34/RXD3
ST detector
7 bits
8 bits
Receive shift register 3
1/16
UART3 cogister
PE FE SP detector
003316
Clock control circuit
Serial I/O3 synchronous clock selection bit
P36/SCLK3
f(XIN)
Frequency division ratio 1/(n+1)
BRG count source selection bit
Baud rate generator 3
Address 002F16
(f(XCIN) in low-speed mode)
1/4
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
mit interrupt source selection bit
Transmit shift regist
P35/TXD3
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buf
003016
Address 003116
Serial I/O3 status register
Data
Fig. 42 Block diagram of UART serial I/O3
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=
TBE=0
TSC=1ꢀ
SP
TBE=1
TB
Serial output TXD3
D0
D1
ST
D0
D1
SP
ꢀ Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input R
X
D3
D0
D1
ST
D0
D1
Notes
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O3 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle are necessary until changing to TSC=0.
Fig. 43 Operation of UART serial I/O3
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-49
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
[Serial I/O3 Control Register (SIO3CON)]
003216
The serial I/O3 control register consists of eight control bits for the
serial I/O3 function.
[UART3 Control Register (UART3CON)]
003316
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer, and one bit (bit 4) which is al-
ways valid and sets the output structure of the P35/TXD3 pin.
[Serial I/O3 Status Register (SIO3STS)] 003116
The read-only serial I/O3 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O3
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O3
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O3 enable bit SIOE
(bit 7 of the serial I/O3 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O3 status register are initialized to “0” at
reset, but if the transmit enable bit (bit 4) of the serial I/O3 control
register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register 3/Receive Buf
Register 3 (TB3/RB3)] 003016
The transmit buffer register 3 and the receive buffer re
located at the same address. The transmit buffer is and
the receive buffer is read-only. If a character bit leits, the
MSB of data stored in the receive buffer is “0”
[Baud Rate Generator 3 (BR02F16
The baud rate generator determines rate for serial trans-
fer.
The baud rate generator dividuency of the count source
by 1/(n + 1), where n is thtten to the baud rate genera-
tor.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-50
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
b0
b7
Serial I/O3 status register
(SIO3STS : address 003116
Serial I/O3 control register
(SIO3CON : address 003216
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O3 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P3
1: P3
RDY3 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as normal I/O pin
pin operates as SRDY3 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable b
0: Receive dis
1: Receive e
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial Ilection bit (SIOM)
0: Clonous (UART) serial I/O
1: ronous serial I/O
Not used (returns “1” when read)
3 enable bit (SIOE)
al I/O disabled
ns P3
Serial I/O enabled
(pins P3 to P3 operate as serial I/O pins)
4 to P37 operate as normal I/O pins)
4
7
b7
b0
UART3 control register
(UART3CON : address 003316
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (P
0: Even parity
1: Odd parity
Stop bit lenbit (STPS)
0: 1 stop
1: 2 st
Phannel output disable bit (POFF)
utput (in output mode)
nnel open drain output (in output mode)
t used (return “1” when read)
Fig. 44 Structure of serial I/O3 control registers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-51
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀ Notes concerning serial I/O3
1. Notes when selecting clock synchronous serial I/O
1.1 Stop of transmission operation
2. Notes when selecting clock asynchronous serial I/O
2.1 Stop of transmission operation
ꢀ Note
ꢀ Note
Clear the transmit enable bit to “0” (transmit disabled). The trans-
mission operation does not stop by clearing the serial I/O3 enable
bit to “0”.
Clear the serial I/O3 enable bit and the transmit enable bit to “0”
(serial I/O and transmit disabled).
ꢀ Reason
ꢀ Reason
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
Since transmission is not stopped and the transmission circuit is
not initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O3 enable bit is set to
“1” at this time, the data during internaly shifting is output to the
TxD3 pin and an operation failure occ
1.2 Stop of receive operation
2.2 Stop of receive operation
ꢀ Note
ꢀ Note
Clear the receive enable bit to “0” (receive disabled), or clear the
serial I/O3 enable bit to “0” (serial I/O disabled).
Clear the receive enable receive disabled).
2.3 Stop of transe operation
1.3 Stop of transmit/receive operation
ꢀ Note
ꢀ Note 1 (onlsion operation is stopped)
Clear the trble bit to “0” (transmit disabled). The trans-
mission does not stop by clearing the serial I/O3 enable
bit to
Clear both the transmit enable bit and receive enable bit to “0”
(transmit and receive disabled).
(when data is transmitted and received in the clock synchronous
serial I/O mode, any one of data transmission and reception can-
not be stopped.)
n
transmission is not stopped and the transmission circuit is
initialized even if only the serial I/O3 enable bit is cleared to “0”
(serial I/O disabled), the internal transmission is running (in this
case, since pins TxD3, RxD3, SCLK3, and SRDY3 function as I/O
ports, the transmission data is not output). When data is written to
the transmit buffer register in this state, data starts to be shifted to
the transmit shift register. When the serial I/O3 enable bit is set to
“1” at this time, the data during internally shifting is output to the
TxD3 pin and an operation failure occurs.
ꢀ Reason
In the clock synchronous serial I/O mode, the same clock
for transmission and reception. If any one of transmiss
ception is disabled, a bit error occurs because tranand
reception cannot be synchronized.
In this mode, the clock circuit of the transmissalso oper-
ates for data reception. Accordingly, the trn circuit does
not stop by clearing only the transmit to “0” (transmit
disabled). Also, the transmission cirinitialized by clear-
ing the serial I/O3 enable bit to I/O disabled) (refer to
1.1).
ꢀ Note 2 (only receive operation is stopped)
Clear the receive enable bit to “0” (receive disabled).
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-52
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
3. SRDY3 output of reception side
7. Transmit interrupt request when transmit enable bit is set
ꢀ Note
ꢀ Note
When signals are output from the SRDY3 pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDY3 output enable
bit, and the transmit enable bit to “1” (transmit enabled).
When using the transmit interrupt, take the following sequence.
ꢀ Set the serial I/O3 transmit interrupt enable bit to “0” (disabled).
ꢀ Set the transmit enable bit to “1”.
ꢀ Set the serial I/O3 transmit interrupt request bit to “0” after 1 or
more instruction has executed.
4. Setting serial I/O3 control register again
ꢀ Note
ꢀ Set the serial I/O3 transmit interrupt enable bit to “1” (enabled).
ꢀ Reason
Set the serial I/O3 control register again after the transmission and
the reception circuits are reset by clearing both the transmit en-
able bit and the receive enable bit to “0.”
When the transmit enable bit is set to “1”, the transmit buffer
empty flag and the transmit shift register shift completion flag are
also set to “1”. Therefore, regardless of selecting which timing for
the generating of transmit interrupts, the interrupt request is gener-
ated and the transmit interrupt request bit is set at this point.
Clear both the transmit enable bit
(TE) and the receive enable bit
(RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/O3 control register
Can be set with the
↓
LDM instruction at the
same time
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
5. Data transmission control with referring to transmit shift
register completion flag
ꢀ Note
After the transmit data is written to the transmit buffer register, th
transmit shift register completion flag changes from “1” to “0”
a delay of 0.5 to 1.5 shift clocks. When data transmission
trolled with referring to the flag after writing the data to t
buffer register, note the delay.
6. Transmission control when external cloted
ꢀ Note
When an external clock is used as the us clock for data
transmission, set the transmit enablat “H” of the SCLK3
input level. Also, write data to thbuffer register at “H” of
the SCLK input level.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-53
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
PULSE WIDTH MODULATION (PWM)
The 3804 group (Spec. H) has PWM functions with an 8-bit reso-
lution, based on a signal that is the clock input XIN or that clock
input divided by 2 or the clock input XCIN or that clock input di-
vided by 2 in low-speed mode.
PWM Operation
When bit 0 (PWM enable bit) of the PWM control register is set to
“1”, operation starts by initializing the PWM output circuit, and
pulses are output starting at an “H”.
If the PWM register or PWM prescaler is updated during PWM
output, the pulses will change in the cycle after the one in which
the change was made.
Data Setting
The PWM output pin also functions as port P56. Set the PWM pe-
riod by the PWM prescaler, and set the “H” term of output pulse by
the PWM register.
31.875 ꢀ m ꢀ(n+1)
µs
If the value in the PWM prescaler is n and the value in the PWM
register is m (where n = 0 to 255 and m = 0 to 255) :
PWM period = 255 ꢀ (n+1) / f(XIN)
255
PWM output
= 31.875 ꢀ (n+1) µs (when f(XIN) = 8 MHz)
Output pulse “H” term = PWM period ꢀ m / 255
= 0.125 ꢀ (n+1) ꢀ m µs
T = [31.875 ꢀ (n+1)] µs
(when f(XIN) = 8 MHz)
m: Contents of PWM
n : Contents of PWer
T : PWM period N) = 8 MHz
Fig. 45 Timing of Pd
Data bus
PWM
prescaler pre-latch
e-latch
Tranl circuit
latch
PWM
register latch
Count so
select
Port P5
6
“0”
X
IN
or
CIN
PWM register
PWM prescaler
X
1/2
Port P56 latch
PWM enable bit
Fig. 46 Block diagram of PWM function
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-54
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
PWM control register
(PWMCON : address 002B16
)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN
)
1: f(XIN)/2
Not used (return “0” when read)
Fig. 47 Structure of PWM control register
C
T2
A
B
C
PWM output
T
T2
T
PWM register
write signal
(Changes “H” term from ”.)
PWM prescaler
write signal
es PWM period from “T” to “T2”.)
When the contents of the PWM reWM prescaler have changed, the PWM
output will change from the next ter the change.
Fig. 48 PWM output timing when PWM regWM prescaler is changed
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-55
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
A/D CONVERTER
[AD Conversion Register 1, 2 (AD1, AD2)]
003516, 003816
Channel Selector
The channel selector selects one of ports P67/AN7 to P60/AN0 or
P07/AN15 to P00/AN8, and inputs the voltage to the comparator.
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 is the conversion mode se-
lection bit. When this bit is set to “0,” the A/D converter becomes
the 10-bit A/D mode. When this bit is set to “1,” that becomes the
8-bit A/D mode. The conversion result of the 8-bit A/D mode is
stored in the AD conversion register 1. As for 10-bit A/D mode, not
only 10-bit reading but also only high-order 8-bit reading of con-
version result can be performed by selecting the reading
procedure of the AD conversion registers 1, 2 after A/D conversion
is completed (in Figure 50).
Comparator and Control Circuit
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, and then stores the result in the
AD conversion registers 1, 2. When an A/D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD interrupt request bit to “1”.
Note that because the comparator consists of a capacitor cou-
pling, set f(XIN) to 500 kHz or more during an A/D conversion.
b7
b0
AD/DA control register
(ADCON dress 003416
As for 10-bit A/D mode, the 8-bit reading inclined to MSB is per-
formed when reading the AD converter register 1 after A/D
conversion is started; and when the AD converter register 1 is
read after reading the AD converter register 2, the 8-bit reading in-
clined to LSB is performed.
)
Anaselection bits 1
P6
1: P6
1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
1 1 1: P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
or P0
or P0
or P0
or P0
or P0
or P0
or P0
or P0
0
1
2
3
4
5
6
7
/AN
/AN
8
9
/AN10
/AN11
/AN12
/AN13
/AN14
/AN15
[AD/DA Control Register (ADCON)] 003416
The AD/DA control register controls the A/D conversion process.
Bits 0 to 2 and bit 4 select a specific analog input pin. Bit 3 signals
the completion of an A/D conversion. The value of this bit remains
at “0” during an A/D conversion, and changes to “1” when an A/D
conversion ends. Writing “0” to this bit starts the A/D conversion.
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Analog input pin selection bit 2
0: AN
1: AN
0
to AN
to AN15 side
7 side
8
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
VREF and AVSS into 1024, and that outputs the comparison voltag
in the 10-bit A/D mode (256 division in 8-bit A/D mode).
The A/D converter successively compares the comparison
Vref in each mode, dividing the VREF voltage (see belo
input voltage.
Not used (returns “0” when read)
DA
1
output enable bit
0: DA
1
output disabled
output enabled
1: DA
1
DA
2
output enable bit
0: DA
2
output disabled
output enabled
1: DA
2
• 10-bit A/D mode (10-bit reading)
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀn (n = 0–1023)
Fig. 49 Structure of AD/DA control register
1024
• 10-bit A/D mode (8-bit reading)
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀn (n = 0–255)
10-bit reading
256
(Read address 003816 before 003516
)
• 8-bit A/D mode
b0
b9 b8
b0
b7
VREF
Vref =ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ(n–0.5) (n =
AD conversion register 2
256
0
(AD2: address 003816
)
=0
(n
b7
AD conversion register 1
(AD1: address 003516
b7 b6 b5 b4 b3 b2 b1 b0
)
Note : Bits 2 to 6 of address 003816 become “0”
at reading.
8-bit reading
(Read only address 003516
AD conversion register 1
)
b7
b9 b8 b7 b6 b5 b4 b3 b2
b0
(AD1: address 003516
)
Fig. 50 Structure of 10-bit A/D mode reading
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-56
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Data bus
b7
4
b0
AD/DA control register
(Address 003416
)
AD converter interrupt request
A/D control circuit
P6
P6
0
/AN
0
1
/AN
1
P6
P6
2
3
/AN
/AN
2
3
(Address 003816
(Addss 003516
)
)
AD conversion register 2
AD conversion register 1
Comparator
P6
P6
P6
4
/AN
/AN
/AN
4
10
5
5
6
6
Resistor ladder
P6
P0
P0
7
0
1
/AN
/AN
/AN
7
8
9
P0
P0
P0
2
/AN10
/AN11
/AN12
3
V
REF AVSS
4
P0
P0
P0
5/AN13
6/AN14
7/AN15
Fig. 51 Block diagram of A/D converter
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-57
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
D/A CONVERTER
The 3804 group (Spec. H) has two internal D/A converters (DA1
and DA2) with 8-bit resolution.
The D/A conversion is performed by setting the value in each DA
conversion register. The result of D/A conversion is output from
the DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D/A converter, the corresponding port direction
register bit (P30/DA1 or P31/DA2) must be set to “0” (input status).
The output analog voltage V is determined by the value n (decimal
notation) in the DA conversion register as follows:
DA1 conversion register (8)
DA
1
output enable bit
P3 /DA
R-2R resistor ladder
0
1
V = VREF ꢀ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
DA2 conversion register (8)
At reset, the DA conversion registers are cleared to “0016”, and
the DA output enable bits are cleared to “0”, and the P30/DA1 and
P31/DA2 pins become high impedance.
D
output enable bit
P3 /DA
R-2R resistor ladder
1
2
The DA output does not have buffers. Accordingly, connect an ex-
ternal buffer when driving a low-impedance load.
Fig. 52 Block diagconverter
DA1
output enable bit
R
“0”
R
2R
R
R
R
R
P30/DA1
“1”
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
DA1 conversion register
“0”
“1”
AVSS
VREF
Fig. 53 Equivalent connection c/A converter (DA1)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-58
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
WATCHDOG TIMER
When bit 6 of the watchdog timer control register is kept at “0”, the
STP instruction is enabled. When that is executed, both the clock
and the watchdog timer stop. Count re-starts at the same time as
the release of stop mode (Note). The watchdog timer does not
stop while a WIT instruction is executed. In addition, the STP in-
struction is disabled by writing “1” to this bit again. When the STP
instruction is executed at this time, it is processed as an undefined
instruction, and an internal reset occurs. Once a “1” is written to
this bit, it cannot be programmed to “0” again.
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit watchdog timer L and an 8-bit watchdog timer H.
Watchdog Timer Initial Value
Watchdog timer L is set to “FF16” and watchdog timer H is set to
“FF16” by writing to the watchdog timer control register (address
001E16) or at a reset. Any write instruction that causes a write sig-
nal can be used, such as the STA, LDM, CLB, etc. Data can only
be written to bits 6 and 7 of the watchdog timer control register.
Regardless of the value written to bits 0 to 5, the above-mentioned
value will be set to each timer.
The following shows the period between the write execution to the
watchdog timer control register and the underflow of watchdog
timer H.
Bit 7 of the watchdog timer control register is “0”:
when XCIN = 32.768 kHz; 32 s
Watchdog Timer Operations
when XIN = 16 MHz; 65.536 ms
The watchdog timer stops at reset and a countdown is started by
the writing to the watchdog timer control register. An internal reset
occurs when watchdog timer H underflows. The reset is released
after its release time. After the release, the program is restarted
from the reset vector address. Usually, write to the watchdog timer
control register by software before an underflow of the watchdog
timer H. The watchdog timer does not function if the watchdog
timer control register is not written to at least once.
Bit 7 of the watchdog timer contro“1”:
when XCIN = 32.768 k
when XIN = 16 MHz
Note: The watchdog timto count even while waiting for a stop
release. Thereure that watchdog timer H does not un-
derflow durin.
“FF16” is set when
Data bus
watchdog timer
control register is
written to.
“FF16” is set when
watchdog timer
control register is
written to.
X
CIN
“10”
Watchdog timer L
Main clock division
ratio selection bits
(Note)
Watchdog timer H (8)
1/16
“00”
“01”
Watchdog timer H count
source selection bit
X
IN
STP instruction disable bit
STP instructio
Reset
circuit
Internal reset
RESET
Reset release time waiting
Note: Either high-speeed or low-speed mode is selected by bits 7 and 6 of the CPU mode register.
Fig. 54 Block diagram of timer
b0
b7
Watchdog timer control register
(WDTCON : address 001E16
)
Watchdog timer H (for read-out of high-order 6 bit)
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 55 Structure of Watchdog timer control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-59
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
2
MULTI-MASTER I C-BUS INTERFACE
Table 7 Multi-master I C-BUS interface functions
2
The 3804 group (Spec. H) has the multi-master I C-BUS interface.
Item
Function
2
The multi-master I C-BUS interface is a serial communications cir-
2
In conformity with Philips I C-BUS
standard:
2
cuit, conforming to the Philips I C-BUS data transfer format. This
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
interface, offering both arbitration lost detection and a synchro-
nous functions, is useful for the multi-master serial
communications.
Format
2
2
Figure 56 shows a block diagram of the multi-master I C-BUS in-
In conformity with Philips I C-BUS
standard:
2
terface and Table 7 lists the multi-master I C-BUS interface
Master transmission
Master reception
Slave transmission
Slave reception
functions.
Communication mode
SCL clock frequency
2
2
This multi-master I C-BUS interface consists of the I C slave ad-
2
2
dress registers 0 to 2, the I C data shift register, the I C clock
2
2
control register, the I C control register, the I C status register, the
16.1 kHz to 400 kHz (at φ= 4 MHz)
2
2
I C START/STOP condition control register, the I C special mode
System clock φ = f(XIN)/2 (high-speed mode)
φ = f(XIN)/8 (middle-smode)
2
control register, the I C special mode status register, and other
control circuits.
2
When using the multi-master I C-BUS interface, set 1 MHz or
more to the internal clock φ.
Interrupt
generating
circuit
Interrupt request signal
2
b7
b0
I C slave address registers 0 to 2
(SCL, SDA, IRQ)
Interrupt
generating
circuit
Interrupt request signal
(I2CIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RWB
S0D0–2
Address comparator
I2C data shift r
Noise
elimination
circuit
Data
control
circuit
Serial data
(SDA)
b7
b7
b0
S
0
AL AAS AD0 LRB
MST TRX BB PIN
S1
AL
circuit
SSC4 SSC3 SSC2 SSC1 SSC0
SIS SIP
I2C status register
2
I
C START/STOP condition control
S2D
register
Internal data bus
BB
ci
Noise
elimination
circuit
Serial
clock
(SCL)
b7
ACK
S2
b0
b7
b0
ACK
BIT
FAST
MODE
CCR4 CCR3 CCR2 CCR1 CCR0
SPCF
PIN2
AAS2 AAS1 AAS0
I2C clock control register
I2C special mode status register
S3
Clock division
System clock (φ)
b7
b0
b7
b0
PIN2 PIN2
ACKI
HSLAD
CON
SPCFL
HD
IN
10BIT
SAD
TISS TSEL
ALS
BC2 BC1
ES0 BC0
I2 C special mode control register
S3D
S1D I2C control register
Bit counter
2
Fig. 56 Block diagram of multi-master I C-BUS interface
ꢀꢀ: Purchase of MITSUBISHI ELECTRIC CORPORATIONS I2C components conveys a license under the Philips I2C Patent Rights to use these components
an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
Rev.1.00 Jan 14, 2005
1-60
REJ09B0212-0100Z
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
[I C Data Shift Register (S0)] 001116
b7
b0
2
I2C slave address register 0
The I C data shift register (S0: address 001116) is an 8-bit shift
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RWB
(S0D0: address 0FF716
I2C slave address register 1
(S0D1: address 0FF816
I2C slave address register 2
)
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL, and each
time one-bit data is output, the data of this register are shifted by
one bit to the left. When data is received, it is input to this register
from bit 0 in synchronization with the SCL, and each time one-bit
data is input, the data of this register are shifted by one bit to the
left. The minimum 2 cycles of the internal clock φ are required
from the rising of the SCL until input to this register.
)
(S0D2: address 0FF916
)
Read/write bit
Slave address
2
2
Fig. 57 Structure of I C slave address registers 0 to 2
The I C data shift register is in a write enable status only when the
2
2
I C-BUS interface enable bit (ES0 bit) of the I C control register
(S1D: address 001416) is “1”. The bit counter is reset by a write in-
2
struction to the I C data shift register. When both the ES0 bit and
2
the MST bit of the I C status register (S1: address 001316) are “1,”
2
the SCL is output by a write instruction to the I C data shift regis-
2
ter. Reading data from the I C data shift register is always enabled
regardless of the ES0 bit value.
2
[I CSlaveAddressRegisters0to2(S0D0toS0D2)]
0FF716 to 0FF916
2
The I C slave address registers 0 to 2 (S0D0 to S0D2: addresses
0FF716 to 0FF916) consists of a 7-bit slave address and a read/
write bit. In the addressing mode, the slave address written in this
register is compared with the address data to be received immedi-
ately after the START condition is detected.
•Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit ad
dressing mode, set RWB to “0” because the first address dat
be received is compared with the contents (SAD6 to S
2
RWB) of the I C slave address registers 0 to 2.
When 2-byte address data match slave address, a 7d-
dress which is received after restart condition hd and
R/W data can be matched by setting “1” to Rsoftware.
The RWB is cleared to “0” automatically whcondition is
detected.
•Bits 1 to 7: Slave address (SAD0–
These bits store slave addresses. s of the 7-bit address-
ing mode or the 10-bit addode, the address data
transmitted from the masteed with these bits’ contents.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-61
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
[I C Clock Control Register (S2)] 001516
b7
b0
2
The I C clock control register (S2: address 001516) is used to set
I2C clock control register
ACK FAST
BIT MODE
ACK
CCR4 CCR3 CCR2 CCR1 CCR0
(S2 : address 001516
)
ACK control, SCL mode and SCL frequency.
•Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 8.
•Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the
standard clock mode is selected. When the bit is set to “1,” the
high-speed clock mode is selected.
SCL frequency control bits
Refer to Table 8.
SCL mode specification bit
0 : Standard clock mode
1 : High-speed clock mode
ACK bit
2
When connecting the bus of the high-speed mode I C bus stan-
0 : ACK is returned.
1 : ACK is not returned.
dard (maximum 400 kbits/s), use 8 MHz or more oscillation
frequency f(XIN) in the high-speed mode (2 division clock).
•Bit 6: ACK bit (ACK BIT)
ACK clock bit
0 : No ACK clock
1 : ACK clock
ꢀ
This bit sets the SDA status when an ACK clock is generated.
When this bit is set to “0,” the ACK return mode is selected and
SDA goes to “L” at the occurrence of an ACK clock. When the bit
is set to “1,” the ACK non-return mode is selected. The SDA is
held in the “H” status at the occurrence of an ACK clock.
2
Fig. 58 Structure of I C clock cister
Table 8 Set values of control register and SCL
However, when the slave address agree with the address data in
the reception of address data at ACK BIT = “0,” the SDA is auto-
matically made “L” (ACK is returned). If there is a disagreement
between the slave address and the address data, the SDA is auto-
matically made “H” (ACK is not returned).
frequency
Setting value
SCL frequency
CCR4–CC
(at φ = 4 MHz, unit : kHz) (Note 1)
Standard clock
mode
High-speed clock
mode
CCR4 CCR3 CCR0
Setting disabled Setting disabled
Setting disabled Setting disabled
Setting disabled Setting disabled
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
ꢀACK clock: Clock for acknowledgment
•Bit 7: ACK clock bit (ACK)
This bit specifies the mode of acknowledgment which is an ac-
knowledgment response of data transfer. When this bit is set to
“0,” the no ACK clock mode is selected. In this case, no ACK cl
occurs after data transmission. When the bit is set to “1,” th
clock mode is selected and the master generates an A
each completion of each 1-byte data transfer. Thor
transmitting address data and control data releaDA at
the occurrence of an ACK clock (makes SDA “Hives the
ACK bit generated by the data receiving dev
– (Note 2)
– (Note 2)
100
333
250
400 (Note 3)
166
83.3
500/CCR value 1000/CCR value
(Note 3)
(Note 3)
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
34.5
17.2
33.3
16.6
32.3
16.1
Note: Do not write data into the I2C clock cer during transfer. If
data is written during transfer, thgenerator is reset, so
that data cannot be transferred
Notes 1: Duty of SCL output is 50 %. The duty becomes 35 to 45 % only
when the high-speed clock mode is selected and CCR value = 5
(400 kHz, at φ = 4 MHz). “H” duration of the clock fluctuates from
–4 to +2 machine cycles in the standard clock mode, and fluctu-
ates from –2 to +2 machine cycles in the high-speed clock mode.
In the case of negative fluctuation, the frequency does not in-
crease because “L” duration is extended instead of “H” duration
reduction.
These are values when SCL synchronization by the synchronous
function is not performed. CCR value is the decimal notation
value of the SCL frequency control bits CCR4 to CCR0.
2: Each value of SCL frequency exceeds the limit at φ = 4 MHz or
more. When using these setting value, use φ of 4 MHz or less.
3: The data formula of SCL frequency is described below:
φ/(8 ꢀ CCR value) Standard clock mode
φ/(4 ꢀ CCR value) High-speed clock mode (CCR value ≠ 5)
φ/(2 ꢀ CCR value) High-speed clock mode (CCR value = 5)
Do not set 0 to 2 as CCR value regardless of φ frequency.
Set 100 kHz (max.) in the standard clock mode and 400 kHz
(max.) in the high-speed clock mode to the SCL frequency by
setting the SCL frequency control bits CCR4 to CCR0.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-62
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
[I C Control Register (S1D)] 001416
b7
b0
2
I2C control register
The I C control register (S1D: address 001416) controls data com-
10 BIT
SAD
ALS ES0 BC2 BC1 BC0
TISS
(S1D : address 001416
)
munication format.
•Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
2
transmitted. The I C interrupt request signal occurs immediately
after the number of count specified with these bits (ACK clock is
added to the number of count when ACK clock is selected by ACK
clock bit (bit 7 of S2, address 001516) have been transferred, and
BC0 to BC2 are returned to “0002”.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 : 8
1 : 7
0 : 6
1 : 5
0 : 4
1 : 3
0 : 2
1 : 1
Also when a START condition is received, these bits become
“0002” and the address data is always transmitted and received in
8 bits.
I2C-BUS interface
eable bit
Disabled
nabled
2
•Bit 3: I C interface enable bit (ES0)
2
This bit enables to use the multi-master I C-BUS interface. When
this bit is set to “0,” the use disable status is provided, so that the
SDA and the SCL become high-impedance. When the bit is set to
“1,” use of the interface is enabled.
ta format selection bit
0 : Addressing format
1 : Free data format
When ES0 = “0,” the following is performed.
2
• PIN = “1,” BB = “0” and AL = “0” are set (which are bits of the I C
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
status register, S1, at address 001316 ).
2
• Writing data to the I C data shift register (S0: address 001116) is
disabled.
•Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses.
When this bit is set to “0,” the addressing format is selected, so
that address data is recognized. When a match is found between
a slave address and address data as a result of comparison or
Not used
(return “0” when read)
I2C-BUS interface pin input
level selection bit
2
when a general call (refer to “I C Status Register,” bit 1) is re
0 : SMBUS input
1 : CMOS input
ceived, transfer processing can be performed. When this bit is
to “1,” the free data format is selected, so that slave addres
not recognized.
2
Fig. 59 Structure of I C control register
•Bit 5: Addressing format selection bit (10BIT SA
This bit selects a slave address specification formhis bit
is set to “0,” the 7-bit addressing format is sehis case,
only the high-order 7 bits (slave address) oave address
registers 0 to 2 are compared with addWhen this bit is
set to “1,” the 10-bit addressing formed, and all the bits
2
of the I C slave address registerre compared with ad-
dress data.
2
•Bit 7: I C-BUS interface evel selection bit (TISS)
This bit selects the inpthe SCL and SDA pins of the
2
multi-master I C-BU
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-63
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
[I C Status Register (S1)] 001316
•Bit 4: SCL pin low hold bit (PIN)
2
2
The I C status register (S1: address 001316) controls the I C-BUS
interface status. The low-order 4 bits are read-only bits and the
high-order 4 bits can be read out and written to.
This bit generates an interrupt request signal. Each time 1-byte
data is transmitted, the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt
request signal occurs in synchronization with a falling of the PIN
bit. When the PIN bit is “0,” the SCL is kept in the “0” state and
clock generation is disabled. Figure 61 shows an interrupt request
signal generating timing chart.
Set “00002” to the low-order 4 bits, because these bits become the
reserved bits at writing.
•Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an
ACK clock occurs, the LRB bit is set to “0.” If ACK is not returned,
this bit is set to “1.” Except in the ACK mode, the last bit value of
received data is input. The state of this bit is changed from “1” to
The PIN bit is set to “1” in one of the following conditions:
2
• Executing a write instruction to the I C data shift register (S0:
2
“0” by executing a write instruction to the I C data shift register
address 001116). (This is the only condition which the prohibition
of the internal clock is released and data can be communicated
except for the start condition detecti
(S0: address 001116).
•Bit 1: General call detecting flag (AD0)
ꢀ
When the ALS bit is “0”, this bit is set to “1” when a general call
whose address data is all “0” is received in the slave mode. By a
general call of the master device, every slave device receives con-
trol data after the general call. The AD0 bit is set to “0” by
detecting the STOP condition or START condition, or reset.
• When the ES0 bit is “0”
• At reset
• When writing “1” to the PIN ware
The PIN bit is set to “0” in following conditions:
• Immediately after co1-byte data transmission (includ-
ing when arbitratietected)
ꢀGeneral call: The master transmits the general call address “0016” to all
• Immediately aetion of 1-byte data reception
• In the slavmode, with ALS = “0” and immediately af-
ter comf slave address agreement or general call
addrion
slaves.
•Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data when the
ALS bit is “0”.
• Ireception mode, with ALS = “1” and immediately af-
letion of address data reception
ꢀ In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions:
• The address data immediately after occurrence of a STA
condition agrees with the slave address stored in the hi
5: Bus busy flag (BB)
his bit indicates the status of use of the bus system. When this
bit is set to “0,” this bus system is not busy and a START condition
can be generated. The BB flag is set/reset by the SCL, SDA pins
input signal regardless of master/slave. This flag is set to “1” by
detecting the START condition, and is set to “0” by detecting the
STOP condition. The condition of these detecting is set by the
2
der 7 bits of the I C slave address register.
• A general call is received.
ꢀ In the slave receive mode, when the 10-bit addreat is
selected, this bit is set to “1” with the followin:
• When the address data is compared wslave ad-
2
START/STOP condition setting bits (SSC4–SSC0) of the I C
dress register (8 bits consisting of sess and RWB
bit), the first bytes agree.
START/STOP condition control register (S2D: address 001616).
2
When the ES0 bit of the I C control register (bit 3 of S1D, address
2
ꢀꢀThis bit is set to “0” by executing a uction to the I C data
001416) is “0” or reset, the BB flag is set to “0.”
shift register (S0: address 001S0 is set to “1” or reset.
For the writing function to the BB flag, refer to the sections
“START Condition Generating Method” and “STOP Condition Gen-
erating Method” described later.
ꢀ
•Bit 3: Arbitration lost flag (AL)
In the master transmie, when the SDA is made “L” by
any other device, arbis judged to have been lost, so that
this bit is set to “1.” At thsame time, the TRX bit is set to “0,” so
that immediately after transmission of the byte whose arbitration
was lost is completed, the MST bit is set to “0.” The arbitration lost
can be detected only in the master transmission mode. When ar-
bitration is lost during slave address transmission, the TRX bit is
set to “0” and the reception mode is set. Consequently, it becomes
possible to detect the agreement of its own slave address and ad-
dress data transmitted by another master device.
The AL bit is set to “0” in one of the following conditions:
2
•Executing a write instruction to the I C data shift register (S0: ad-
dress 001116)
•When the ES0 bit is “0”
•At reset
ꢀArbitration lost :The status in which communication as a master is dis-
abled.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-64
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
•Bit 6: Communication mode specification bit (transfer direc-
tion specification bit: TRX)
b7
b0
I2C status register
(S1 : address 001316
MST TRX BB PIN AL AAS AD0 LRB
This bit decides a direction of transfer for data communication.
When this bit is “0,” the reception mode is selected and the data of
a transmitting device is received. When the bit is “1,” the transmis-
sion mode is selected and address data and control data are
output onto the SDA in synchronization with the clock generated
on the SCL.
)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
This bit is set/reset by software and hardware. About set/reset by
hardware is described below. This bit is set to “1” by hardware
when all the following conditions are satisfied:
• When ALS is “0”
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Aess agreement
• In the slave reception mode or the slave transmission mode
• When the R/W bit reception is “1”
This bit is set to “0” in one of the following conditions:
• When arbitration lost is detected.
ost detecting flag
• When a STOP condition is detected.
ot detected
: Detected
• When writing “1” to this bit by software is invalid by the START
condition duplication preventing function (Note).
• With MST = “0” and when a START condition is detected.
• With MST = “0” and when ACK non-return is detected.
• At reset
SCL pin low hold bit
0 : SCL pin low hold
1 : SCL pin low release
•Bit 7: Communication mode specification bit (master/slave
specification bit: MST)
Bus busy flag
0 : Bus free
1 : Bus busy
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization
with the clock generated by the master. When this bit is “1,” the
master is specified and a START condition and a STOP condi
are generated. Additionally, the clocks required for data co
cation are generated on the SCL.
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
Note: These bits and flags can be read out, but cannot be written.
Write “0” to these bits at writing.
This bit is set to “0” in one of the following conditions
• Immediately after completion of the byte which rbitra-
tion when arbitration lost is detected
2
Fig. 60 Structure of I C status register
• When a STOP condition is detected.
• Writing “1” to this bit by software is inSTART condi-
tion duplication preventing function
• At reset
SCL
PIN
Note: START condition duplicang function
The MST, TRX, and Bto “1” at the same time after con-
firming that the BB the procedure of a START condition
occurrence. Howa START condition by another master
device occurs and tflag is set to “1” immediately after the con-
tents of the BB flag is confirmed, the START condition duplication
preventing function makes the writing to the MST and TRX bits in-
valid. The duplication preventing function becomes valid from the
rising of the BB flag to reception completion of slave address.
I2CIRQ
Fig. 61 Interrupt request signal generating timing
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-65
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
STOP Condition Generating Method
START Condition Generating Method
2
2
When the ES0 bit of the I C control register (S1D: address
When writing “1” to the MST, TRX, and BB bits of the I C status
001416) is “1,” write “1” to the MST and TRX bits, and write “0” to
register (S1: address 001316) at the same time after writing the
2
2
the BB bit of the I C status register (S1: address 001316) simulta-
slave address to the I C data shift register (S0: address 001116)
2
neously. Then a STOP condition occurs. The STOP condition
generating timing is different in the standard clock mode and the
high-speed clock mode. Refer to Figure 63, the STOP condition
generating timing diagram, and Table 10, the STOP condition gen-
erating timing table.
with the condition in which the ES0 bit of the I C control register
(S1D: address 001416) is “1” and the BB flag is “0”, a START con-
dition occurs. After that, the bit counter becomes “0002” and an
SCL for 1 byte is output. The START condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 62, the START condition generating timing
diagram, and Table 9, the START condition generating timing
table.
I2C status register
write signal
SCL
Setup
time
me
I2C status register
write signal
SDA
SCL
Setup
Hold time
time
Fig. 63 STOP condition g timing diagram
Table 10 STOP cenerating timing table
SDA
clock mode
s (20 cycles)
.5 µs (18 cycles)
High-speed clock mode
3.0 µs (12 cycles)
Item
Fig. 62 START condition generating timing diagram
Table 9 START condition generating timing table
Setup time
Hold ti
2.5 µs (10 cycles)
Note: me at φ = 4 MHz. The value in parentheses denotes the
of φ cycles.
Item
Standard clock mode High-speed clock mode
Setup time
Hold time
5.0 µs (20 cycles)
5.0 µs (20 cycles)
2.5 µs (10 cycles)
2.5 µs (10 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes th
number of φ cycles.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-66
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 64, 65, and Table 11. The START/STOP condition is set
by the START/STOP condition set bit.
SCL release time
SCL
SDA
Setup
time
Hold time
BB flag
set time
The START/STOP condition can be detected only when the input
signal of the SCL and SDA pins satisfy three conditions: SCL re-
lease time, setup time, and hold time (see Table 11).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
BB flag
Fig. 64 START/STOP condition detecting timing diagram
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 11, the BB flag set/
reset time.
SCL release time
SCL
Setup
Hold time
time
Note: When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I2CIRQ” occurs to the CPU.
SDA
BB flag
reset
time
BB flag
Table 11 START condition/STOP condition detecting conditions
Fig. 65 STOP condition detng diagram
Standard clock mode
High-speed clock mode
SCL release time
SSC value + 1 cycle (6.25 µs)
4 cycles (1.0 µs)
SSC value + 1
Setup time
cycle < 4.0 µs (3.125 µs)
2 cycles (0.5 µs)
2 cycles (0.5 µs)
2
SSC value + 1
Hold time
cycle < 4.0 µs (3.125 µs)
2
BB flag set/
reset time
SSC value –1
3.5 cycles (0.875 µs)
+ 2 cycles (3.375 µs)
2
Note: Unit : Cycle number of internal clock φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I2C START/
STOP condition control register is set to “1816” at φ = 4 MHz.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-67
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
[I C START/STOP Condition Control Register
•Bit 6: SCL/SDA interrupt pin selection bit (SIS)
(S2D)] 001616
The I C START/STOP condition control register (S2D: address
This bit selects the pin of which interrupt becomes valid between
2
the SCL pin and the SDA pin.
Note: When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and
enable the interrupt.
001616) controls START/STOP condition detection.
•Bits 0 to 4: START/STOP condition set bits (SSC4–SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(XIN) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 11.
Do not set “000002” or an odd number to the START/STOP condi-
tion set bits (SSC4 to SSC0).
Refer to Table 12, the recommended set value to START/STOP
condition set bits (SSC4–SSC0) for each oscillation frequency.
•Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or SDA
pin interrupt pin.
b7
b0
I2C START/STOP condition
control register
SSC4 SSC3 SSC2 SSC1 SSC0
SIS SIP
(S2D : address 001616)
START/STOP condition set bits
SCL/SDA interrupt pin polarity
selection bit
0 : Falling edge active
1 : Rising edge active
SCL/SDA interrupt pin bit
0 : SDA valid
1 : SCL valid
Not used
(Fix this
2
Fig. 66 Structure of I C START/STon control register
Table 12 Recommended set TART/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Oscillation
frequency
f(XIN) (MHz)
START/STOP
condition
control register
al
k φ
MHz)
Main clo
divide
SCL release time
Setup time
Hold time
(µs)
(µs)
(µs)
3.25 µs (13 cycles)
3.0 µs (12 cycles)
2.0 µs (2 cycles)
3.0 µs (6 cycles)
2.5 µs (5 cycles)
2.0 µs (2 cycles)
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
6.75 µs (27 cycles)
6.25 µs (25 cycles)
5.0 µs (5 cycles)
6.5 µs (13 cycles)
5.5 µs (11 cycles)
5.0 µs (5 cycles)
3.5 µs (14 cycles)
3.25 µs (13 cycles)
3.0 µs (3 cycles)
3.5 µs (7 cycles)
3.0 µs (6 cycles)
3.0 µs (3 cycles)
8
8
4
2
2
8
2
2
4
1
2
1
Note: Do not set an odd number to the START/STOP condition set bits (SSC4 to SSC0) and “000002”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-68
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
[I C Special Mode Status Register (S3)]
•Bit 5: SCL pin low hold 2 flag (PIN2)
001216
When the ACK interrupt control bit (ACKICON) and the ACK clock
bit (ACK) are “1”, this flag is set to “0” in synchronization with the
falling of the data’s last SCL clock, just before the ACK clock. The
2
The I C special mode status register (S3: address 001216) con-
2
2
sists of the flags indicating I C operating state in the I C special
2
2
mode, which is set by the I C special mode control register (S3D:
SCL pin is simultaneously held low, and the I C interrupt request
address 001716).
occurs.
The stop condition flag is valid in all operating modes.
•Bit 0: Slave address 0 comparison flag (AAS0)
Bit 1: Slave address 1 comparison flag (AAS1)
Bit 2: Slave address 2 comparison flag (AAS2)
These flags indicate a comparison result of address data. These
flags are valid only when the slave address control bit (MSLAD) is
“1”.
This flag is initialized to “1” at reset, when the ACK interrupt con-
trol bit (ACKICON) is “0”, or when writing “1” to the SCL pin low
hold 2 flag set bit (PIN2IN).
The SCL pin is held low when either the SCL pin low hold bit (PIN)
or the SCL pin low hold 2 flag (PIN2) becomes “0”. The low hold
state of the SCL pin is released when both the SCL pin low hold
bit (PIN) and the SCL pin low hold 2 flag (PIN2) are “1”.
•Bit 7: Stop condition flag (SPCF)
In the 7-bit addressing format of the slave reception mode, the re-
spective slave address i (i = 0, 1, 2) comparison flags
This flag is set to “1” when a STOP con occurs.
2
2
corresponding to the I C slave address registers 0 to 2 are set to
This flag is initialized to “0” at reshe I C-BUS interface
“1” when an address data immediately after an occurrence of a
enable bit (ES0) is “0”, or whe” to the STOP condition
START condition agrees with the high-order 7-bit slave address
flag clear bit (SPFCL).
2
stored in the I C slave address registers 0 to 2 (addresses 0FF716
to 0FF916).
In the 10-bit addressing format of the slave mode, the respective
slave address i (i = 0, 1, 2) comparison flags corresponding to the
2
I C slave address registers are set to “1” when an address data is
compared with the 8 bits consisting of the slave address stored in
2
the I C slave address registers 0 to 2 and the RWB bit, and the
first byte agrees.
These flags are initialized to “0” at reset, when the slave address
2
control bit (MSLAD) is “0”, or when writing data to the I C data
shift register (S0: address 001116).
b7
C special mode status register
(S3 : address 001216
SPCF
PIN2
)
Slave address 0 comparison flag
0 : Address disagreement
1 : Address agreement
Slave address 1 comparison flag
0 : Address disagreement
1 : Address agreement
Slave address 2 comparison flag
0 : Address disagreement
1 : Address agreement
Not used
(return “0” when read)
Not used
(return “0” when read)
SCL pin low hold 2 flag
0 : SCL pin low hold
1 : SCL pin low release (Note)
Not used
(return “0” when read)
STOP condition flag
0 : No detection
1 : Detection
Note: In order that the low hold state of the SCL pin may release, it is
necessary that the SCL pin low hold 2 flag and the SCL pin low
hold bit (PIN) are “1” simultaneously.
2
Fig. 67 Structure of I C special mode status register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-69
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
2
[I C Special Mode Control Register (S3D)]
•Bit 2: I C slave address control bit (MSLAD)
2
001716
This bit controls a slave address. When this bit is “0”, only the I C
slave address register 0 (address 0FF716) becomes valid as a
slave address and a read/write bit.
2
The I C special mode control register (S3D: address 001716) con-
trols special functions such as occurrence timing of reception
interrupt request and extending slave address comparison to 3
bytes.
2
When this bit is “1”, all of the I C slave address registers 0 to 2
(addresses 0FF716 to 0FF916) become valid as a slave address
and a read/write bit. In this case, when an address data agrees
•Bit 1: ACK interrupt control bit (ACKICON)
2
2
This bit controls the timing of I C interrupt request occurrence at
with any one of the I C slave address registers 0 to 2, the slave
2
completion of data receiving due to master reception or slave re-
ception.
address comparison flag (AAS) is set to “1” and the I C slave ad-
2
dress comparison flag corresponding to the agreed I C slave
When this bit is “0”, the SCL pin low hold bit (PIN) is set to “0” in
synchronization with the falling of the last SCL clock, including the
address registers 0 to 2 is also set to “1”.
•Bit 5: SCL pin low hold 2 flag set bit (PIN2IN)
Writing “1” to this bit initializes the SCL pin low hold 2 flag (PIN2)
to “1”.
2
ACK clock. The SCL pin is simultaneously held low, and the I C
interrupt request occurs.
When this bit is “1” and the ACK clock bit (ACK) is “1”, the SCL pin
low hold 2 flag (PIN2) is set to “0” in synchronization with the fall-
ing of the data’s last SCL clock, just before the ACK clock. The
When writing “0”, nothing is generated
•Bit 6: SCL pin low hold set bit (
When the SCL pin low hold bit mes “0”, the SCL pin is
held low. However, the SCL d bit (PIN) cannot be set to
“0” by software. The SCL ld set bit (PIN2HD) is used to ,
hold the SCL pin in thby software. When writing “1” to
this bit, the SCL p2 flag (PIN2) becomes “0”, and the
SCL pin is held writing “0”, nothing occurs.
•Bit 7: STOn flag clear bit (SPFCL)
Writing “t initializes the STOP condition flag (SPCF) to
“0”.
2
SCL pin is simultaneously held low, and the I C interrupt request
occurs again. The ACK bit can be changed after the contents of
data are confirmed by using this function.
Wh“0”, nothing is generated.
b7
b0
I2e control register
ACKI
CON
PIN2-
HD
SPFCL
MSLAD
PIN2IN
ss 001716
)
sed
x this bit to “0”.)
ACK interrupt control bit
0 : At communication completion
1 : At falling of ACK clock and communication
completion
Slave address control bit
0 : One-byte slave address compare mode
1 : Three-byte slave address compare mode
Not used
(return “0” when read)
Not used
(Fix this bit to “0”.)
SCL pin low hold 2 flag set bit (Notes 1, 2)
Writing “1” to this bit initializes the SCL pin low
hold 2 flag to “1”.
SCL pin low hold set bit (Notes 1, 2)
When writing “1” to this bit, the SCL pin low
hold 2 flag becomes “0” and the SCL pin is held
low.
STOP condition flag clear bit (Note 2)
Writing “1” to this bit initializes the STOP
condition flag to “0”.
Notes 1: Do not write “1” to these bits simultaneously.
2: return “0” when read
2
Fig. 68 Structure of I C special mode control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-70
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Address Data Communication
parison, an address comparison between the RWB bit of the
2
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective
address communication formats are described below.
ꢀ 7-bit addressing format
I C slave address register and the R/W bit which is the last bit
of the address data transmitted from the master is made. In the
10-bit addressing mode, the RWB bit which is the last bit of the
address data not only specifies the direction of communication
for control data, but also is processed as an address data bit.
When the first-byte address data agree with the slave address,
To adapt the 7-bit addressing format, set the 10BIT SAD bit of
2
the I C control register (S1D: address 001416) to “0”. The first 7-
2
bit address data transmitted from the master is compared with
the AAS bit of the I C status register (S1: address 001316) is
2
the high-order 7-bit slave address stored in the I C slave ad-
set to “1.” After the second-byte address data is stored into the
2
dress register. At the time of this comparison, address
I C data shift register (S0: address 001116), perform an ad-
2
comparison of the RWB bit of the I C slave address register is
dress comparison between the second-byte data and the slave
address by software. When the address data of the 2 bytes
not performed. For the data transmission format when the 7-bit
addressing format is selected, refer to Figure 69, (1) and (2).
ꢀ 10-bit addressing format
2
agree with the slave address, set the RWB bit of the I C slave
address register to “1” by software. This processing can make
the 7-bit slave address and R/W agree, which are re-
ceived after a RESTART conditited, with the value of
To adapt the 10-bit addressing format, set the 10BIT SAD bit of
2
the I C control register (S1D: address 001416) to “1.” An ad-
2
dress comparison is performed between the first-byte address
data transmitted from the master and the 8-bit slave address
the I C slave address regise data transmission for-
mat when the 10-bit adormat is selected, refer to
Figure 69, (3) and (4).
2
stored in the I C slave address register. At the time of this com-
(1) A master-transmitter transmits data to a slave-receiver
A
Data
A
Data
S
Slave address R/W
7 bits “0”
A/A
P
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
A
Data
A
Data
S
Slave address R/W
7 bits “1”
1 to 8 bits
1 to
(3) A master-transmitter transmits data to a slave-th a 10-bit address
Slave addr
2nd byte
Slave address
1st 7 bits
A/A
A
Data
Data
S
R/W
A
P
1 to 8 bits
1 to 8 bits
7 bits
“0”
(4) A master-receiver receives dalave-transmitter with a 10-bit address
e address
d bytes
Slave address
1st 7 bits
Slave address
1st 7 bits
Sr
A
A
Data
1 to 8 bits
Data
P
S
R/W
R/W
A
A
“1”
1 to 8 bits
7 bits
8 bits
7 bits
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
: Master to slave
: Slave to master
Fig. 69 Address data communication format
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-71
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is
shown below.
Example of Slave Reception
An example of slave reception in the high-speed clock mode, at
the SCL frequency of 400 kHz, in the ACK non-return mode and
using the addressing format is shown below.
2
2
ꢀ Set a slave address in the high-order 7 bits of the I C slave ad-
ꢀ Set a slave address in the high-order 7 bits of the I C slave ad-
dress register and “0” into the RWB bit.
dress register and “0” in the RWB bit.
ꢀ Set the ACK return mode and SCL = 100 kHz by setting “8516”
ꢀ Set the no ACK clock mode and SCL = 400 kHz by setting
2
2
in the I C clock control register (S2: address 001516).
“2516” in the I C clock control register (S2: address 001516).
2
2
ꢀ Set “0016” in the I C status register (S1: address 001316) so
ꢀ Set “0016” in the I C status register (S1: address 001316) so
that transmission/reception mode can become initializing condi-
that transmission/reception mode can become initializing condi-
tion.
tion.
2
2
ꢀ Set a communication enable status by setting “0816” in the I C
ꢀ Set a communication enable status by setting “0816” in the I C
control register (S1D: address 001416).
control register (S1D: address 001416).
ꢀ When a START condition is received, an address comparison is
performed.
2
ꢀ Confirm the bus free condition by the BB flag of the I C status
register (S1: address 001316).
ꢀ Set the address data of the destination of transmission in the
ꢀꢀ•When all transmitted addresses eneral call):
2
2
high-order 7 bits of the I C data shift register (S0: address
AD0 of the I C status registeess 001316) is set to “1”
001116) and set “0” in the least significant bit.
and an interrupt request rs.
2
ꢀ Set “F016” in the I C status register (S1: address 001316) to
• When the transmitted agree with the address set in
ꢀ:
generate a START condition. At this time, an SCL for 1 byte and
2
an ACK clock automatically occur.
AAS of the I C ster (S1: address 001316) is set to
2
ꢀ Set transmit data in the I C data shift register (S0: address
“1” and an inuest signal occurs.
2
001116). At this time, an SCL and an ACK clock automatically
• In the cahan the above AD0 and AAS of the I C sta-
occur.
tus readdress 001316) are set to “0” and no interrupt
ꢀ When transmitting control data of more than 1 byte, repeat step
ꢀ.
rel occurs.
2
ꢀ y data in the I C data shift register (S0: address
2
ꢀ Set “D016” in the I C status register (S1: address 001316) to
).
generate a STOP condition if ACK is not returned from slave re-
ception side or transmission ends.
n receiving control data of more than 1 byte, repeat step ꢀ.
hen a STOP condition is detected, the communication ends.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-72
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
2
ꢀPrecautions when using multi-master I C-
BUS interface
5. Disable interrupts during the following three process steps:
• BB flag confirming
• Writing of slave address value
(1) Read-modify-write instruction
The precautions when the read-modify-write instruction such as
SEB, CLB etc. is executed for each register of the multi-master
• Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
2
I C-BUS interface are described below.
2
• I C data shift register (S0: address 001116)
When executing the read-modify-write instruction for this regis-
ter during transfer, data may become a value not intended.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions of the generat-
ing procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is “0.”
2
• I C slave address registers 0 to 2 (S0D0 to S0D2: addresses
0FF716 to0FF916)
:
When the read-modify-write instruction is executed for this regis-
ter at detecting the STOP condition, data may become a value
not intended. It is because H/W changes the read/write bit
(RWB) at the above timing.
:
LDM #$00, S1
LDA —
(Select slave receive mode)
(Taking out of slave address value)
(Interrupt led)
SEI
2
• I C status register (S1: address 001316)
STAS0
(Writinddress value)
Do not execute the read-modify-write instruction for this register
because all bits of this register are changed by H/W.
LDM #$F0, S1
CLI
(
TrigART condition generating
)
(nabled)
2
:
:
• I C control register (S1D: address 001416)
When the read-modify-write instruction is executed for this regis-
ter at detecting the START condition or at completing the byte
transfer, data may become a value not intended. Because H/W
changes the bit counter (BC0-BC2) at the above timing.
2. Select the slave ree when the PIN bit is “0.” Do not
write “1” to the either “0” nor “1” is specified for the
writing to the
The TRX s “0” and the SDA pin is released.
3. The Seleased by writing the slave address value to
2
• I C clock control register (S2: address 001516)
The read-modify-write instruction can be executed for this regis-
ter.
the hift register.
4. errupts during the following two process steps:
of slave address value
2
• I C START/STOP condition control register (S2D: address
001616)
ger of RESTART condition generating
The read-modify-write instruction can be executed for this regis
ter.
2
4) Writing to I C status register
Do not execute an instruction to set the PIN bit to “1” from “0” and
an instruction to set the MST and TRX bits to “0” from “1” simulta-
neously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to “0” from “1” simultaneously when the PIN bit is “1.” It is because
it may become the same as above.
(2) START condition generating procedure using multi-m
1. Procedure example (The necessary conditions of at-
ing procedure are described as the following 2 t
:
:
LDA —
(Taking out of slavalue)
(Interrupt disa
SEI
BBS 5, S1, BUSBUSY (BB flag cnd branch process)
BUSFREE:
(5) Process of after STOP condition generating
2
2
STA S0
(Wre address value)
START condition generating)
t enabled)
Do not write data in the I C data shift register S0 and the I C sta-
tus register S1 until the bus busy flag BB becomes “0” after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers does not have the problem.
LDM #$F0, S1
CLI
:
:
BUSBUSY:
CLI
(Interrupt enabled)
:
:
2. Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag con-
firming and branch process.
3. Use “STA $12, STX $12” or “STY $12” of the zero page ad-
dressing instruction for writing the slave address value to the
2
I C data shift register.
4. Execute the branch instruction of above 2 and the store instruc-
tion of above 3 continuously shown the above procedure
example.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-73
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 16 cycles or more of XIN. Then the RESET pin is returned
to an “H” level (the power source voltage should be between 2.7 V
to 5.5 V, and the oscillation should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address
FFFC16 (low-order byte).
2.7 V
VCC
RESET
VCC
0V
RESET
0.2VCC or less
0V
td(P-R)+XIN 16 cycles or more
Input to the RESET pin in the following procedure.
ꢀWhen power source is stabilized
5V
2.7 V
VCC
(1) Input “L” level to RESET pin.
Power source
voltage detection
circuit
RESET
VCC
0V
5V
(2) Input “L” level for 16 cycles or more to XIN pin.
(3) Input “H” level to RESET pin.
RESET
0V
ꢀAt power-on
td(P-R)+XIN 16 cycles or more
(1) Input “L” level to RESET pin.
(2) Increase the power source voltage to 2.7 V.
(3) Wait for td(P-R) until internal power source has stabilized.
(4) Input “L” level for 16 cycles or more to XIN pin.
(5) Input “H” level to RESET pin.
Example at VCC = 5V
Fig. 70 Reset circuit
X
IN
φ
RESET
Internal
reset
Address
AD
H L
,
?
?
?
FFFC
FFFD
Reset address from the vector table.
Data
ADH
?
?
AD
L
?
SYNC
o 18.5 clock cycles
Notes
1: The frequency relation of f(XIN) and f(φ) is f(XIN)=8
• f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 71 Reset sequence
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-74
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Address
Register contents
Register contents
Address
(1)
0016
Port P0 (P0)
FF16
FF16
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
(41)Timer Z (low-order) (TZL)
002816
002916
002A16
002B16
002C16
002D16
002F16
003016
003116
003216
0
516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FE016
0FE116
0FE216
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
(PS)
(2)
0016
Port P0 direction register (P0D)
Port P1 (P1)
(42)Timer Z (high-order) (TZH)
(3)
0016
0016
(43)Timer Z mode register (TZM)
(44)PWM control register (PWMCON)
(45)PWM prescaler (PREPWM)
(4)
0016
Port P1 direction register (P1D)
Port P2 (P2)
0016
(5)
0016
X X X X X X X X
X X X X X X X X
X X X X X X X X
(6)
0016
Port P2 direction register (P2D)
Port P3 (P3)
(46)PWM register (PWM)
(7)
0016
(47)Baud rate generator 3 (BRG3)
(48)Transmit/Receive buffer register 3 (TB3/RB3)
(49)Serial I/O3 status register (SIO3STS)
(50)Serial I/O3 control register (SIO3CON)
(51)UART3 control register (UART3CON)
(52)AD/DA control register (ADCON)
(53)AD conversion register 1 (AD1)
(54)DA1 conversion register (D
(55)DA2 conversion regis
(56)AD conversion r2)
(57)Interrupt sourc(INTSEL)
(58)Interrupgister (INTEDGE)
(59)gister (CPUM)
(8)
0016
Port P3 direction register (P3D)
Port P4 (P4)
X X X X X X X X
1 0 0 0 0 0 0 0
0016
(9)
0016
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
0016
0016
Port P4 direction register (P4D)
Port P5 (P5)
1 1 1 0 0 0 0 0
0016
Port P5 direction register (P5D)
Port P6 (P6)
0 0 0 1 0 0 0
X X X X X X X X
0016
0016
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
MISRG
0016
0 0 1 1 0 0 1 1
0 0 1 1 0 0 1 1
0016
0016
0 0 0 0 0 0 X X
0016
I2C data shift register (S0)
I2C special mode status register (S3)
I2C status register (S1)
I2C control register (S1D)
X X X X X X X X
0 0 1 0 0 0 0 0
0016
0 1 0 0 1 0 0 0
0016
equest register 1 (IREQ1)
rrupt request register 2 (IREQ2)
2)Interrupt control register 1 (ICON1)
(63)Interrupt control register 2 (ICON2)
(64)Flash memory control register 0 (FMCR0)
(65)Flash memory control register 1 (FMCR1)
(66)Flash memory control register 2 (FMCR2)
(67)Port P0 pull-up control register (PULL0)
(68)Port P1 pull-up control register (PULL1)
(69)Port P2 pull-up control register (PULL2)
(70)Port P3 pull-up control register (PULL3)
(71)Port P4 pull-up control register (PULL4)
(72)Port P5 pull-up control register (PULL5)
(73)Port P6 pull-up control register (PULL6)
(74)I2C slave address register 0 (S0D0)
(75)I2C slave address register 1 (S0D1)
(76)I2C slave address register 2 (S0D3)
(77)Processor status register
0 0 0 1 0 0 0 X
0016
0016
I2C clock control register (S2)
2
0016
0016
0 0 0 1
I C START/STOP condition control register (S2D)
I2C special mode control register (S3D)
Transmit/Receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
0016
001616
001716
0018
1B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
0116
X X X X
0 0 0 0 0 0
4016
4516
0016
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1C
Baud rate generator 1 (BRG
Serial I/O2 control regisN)
Watchdog timer coWDTCON)
Serial I/O2 register
Prescaler 12 (PRE12)
0016
1 1 1 0 0 0 0 0
0016
X X X X X X X X
0016
0016
0016
0 0 1 1 1 1 1 1
0016
X X X X X X X X
0016
FF16
0116
FF16
0016
FF16
FF16
FF16
FF16
0016
Timer 1 (T1)
0016
Timer 2 (T2)
0016
Timer XY mode register (TM)
Prescaler X (PREX)
0016
X X X X X
1 X X
Timer X (TX)
(78)Program counter
(PCH)
FFFD16 contents
FFFC16 contents
Prescaler Y (PREY)
(PC
L)
Timer Y (TY)
Note : X : Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
Fig. 72 Internal status at reset
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-75
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
CLOCK GENERATING CIRCUIT
Oscillation Control
(1) Stop mode
The 3804 group (Spec. H) has two built-in oscillation circuits: main
clock XIN-XOUT oscillation circuit and sub clock XCIN-XCOUT oscil-
lation circuit. An oscillation circuit can be formed by connecting a
resonator between XIN and XOUT (XCIN and XCOUT). Use the cir-
cuit constants in accordance with the resonator manufacturer’s
recommended values. No external resistor is needed between XIN
and XOUT since a feed-back resistor exists on-chip.(An external
feed-back resistor may be needed depending on conditions.)
However, an external feed-back resistor is needed between XCIN
and XCOUT.
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. When the oscillation
stabilizing time set after STP instruction released bit is “0,” the
prescaler 12 is set to “FF16” and timer 1 is set to “0116.” When the
oscillation stabilizing time set after STP instruction released bit is
“1,” set the sufficient time for oscillation of used oscillator to stabi-
lize since nothing is set to the prescaler 12 and timer 1.
After STP instruction is released, the input of the prescaler 12 is
connected to count source which had set at executing the STP in-
struction, and the output of the prescaler 12 is connected to timer
1. Set the timer 1 interrupt enable bit to disabled (“0”) before ex-
ecuting the STP instruction. Oscillator restarts when an external
interrupt is received, but the internal clock φ is not supplied to the
CPU (remains at “H”) until timer 1 underlows. The internal clock φ
is supplied for the first time, when tiunderflows. Therefore
make sure not to set the timer 1 iquest bit to “1” before
the STP instruction stops the When the oscillator is re-
started by reset, apply “the RESET pin until the
oscillation is stable since will not be generated.
The internal power uit is changed to low power con-
sumption mode fption current reduction at the time of
STP instructio.
Immediately after power on, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal clock φ is the frequency of XIN divided by 8. After re-
set is released, this mode is selected.
(2) High-speed mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed mode
The internal clock φ is half the frequency of XCIN.
Although an ower supply circuit is usually changed to the
normal mode at the time of the return from an STP in-
struca certain time is required to start the power supply
to memory and operation of flash memory to be enabled,
ime 100 µs or more by the oscillation stabilization time
nction after release of the STP instruction which used the
er 1.
(4) Low power dissipation mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
bit 5 of the CPU mode register to “1.” When the main clock XIN is
restarted (by setting the main clock stop bit to “0”), set sufficient
time for oscillation to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock φ re-
starts when an interrupt is received. Since the oscillator does not
stop, normal operation can be started immediately after the clock
is restarted.
ꢀNote
•If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately
after power on and at returning from stop mode. When switching
the mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3f(XCIN).
•When using the quartz-crystal oscillator of high frequency, such
as 16 MHz etc., it may be necessary to select a specific oscillator
with the specification demanded.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-76
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
X
CIN
X
COUT
XIN
XOUT
Rd (Note)
Rf
Rd
C
COUT
C
IN
COUT
C
CIN
Notes : Insert a damping resistor if required.
The resistance will vary depending on the oscillator and
the oscillation drive capacity setting.
Use the value recommended by the maker of the
oscillator.
Also, if the oscillator manufacturer's data sheet
specifies that a feedback resistor be added external to
the chip though a feedback resistor exists on-chip,
insert a feedback resistor between XIN and XOUT
following the instruction.
Fig. 73 Ceramic resonator circuit
X
CIN
X
COUT
XIN
XOUT
Open
Open
External oscillation
circuit
External oscillation
circuit
V
CC
SS
V
CC
SS
V
V
Fig. 74 External clock input circuit
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-77
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
X
COUT
XCIN
“0”
“1”
Port X
C
switch bit
X
OUT
X
IN
Main clock division ratio
selection bits (Note 1)
Low-speed
(Note 4)
Divider
mode
Prescaler 12
(Note 3)
Timer 1
1/2
1/4
High-speed or
middle-speed
mode
Reset or
STP instruction
(Note 2)
Main clock division ratio
selection bits (Note 1)
Middle-speed mode
φ (internal clock)
High-speed or
low-speed mode
Main clock stop bit
Reset
Q
S
R
S Q
S
R
STP instruction
STP instruction
WIT instruction
Reset
Interrupt disable flag l
Interrupt request
Notes 1: Either high-speed, mior low-speed mode is selected by bits 7 and 6 of the CPU mode register.
When low-speed mected, set port Xc switch bit (b4) to “1”.
2: f(XIN)/16 is suppcount source to the prescaler 12 at reset. The count source before executing the STP
instruction is the count source at executing STP instruction.
3: When bit 0 is “0”, timer 1 is set “0116” and prescaler 12 is set “FF16” automatically. When bit 0 of MISRG is
“1”, set riate value to them in accordance with oscillation stablizing time required by the using oscillator
becais automatically set into timer 1 and prescaler 12.
4: Althoued-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions.
Fig. 75 System clock generating circuit block diagram
Rev.1.00 Jan 14, 2005
1-78
REJ09B0212-0100Z
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Reset
High-speed mode
Middle-speed mode
(f(φ)=4 MHz)
(f(φ)=1 MHz)
CM
6
“1”←→“0”
CM
CM
CM
CM
7
6
5
4
=0
=1
CM
CM
CM
CM
7
=0
6
5
4
=0
=0(8 MHz oscillating)
=0(32 kHz stopped)
=0(8 MHz oscillating)
=0(32 kHz stopped)
C
M
“
”
4
0
0
”
“
←
C
4
→
M
→
M
“
”
6
C
1
←
“
”
0
”
1
”
“
←
1
6
M
“
→
→
“
C
←
”
0
1
”
“
Middle-speed mode
(f(φ)=1 MHz)
High-speed mode
(f(φ)=4 MHz)
CM
6
“1”←→“0”
CM
CM
CM
CM
7
=0
CM
CM
CM
CM
7
=0
6=1
6
5
4
=0
5
=0(8 MHz oscillating)
=1(32 kHz oscillating)
=0(8 MHz oscillating)
=1(32 kHz oscillating)
4
C
M
“
7
0
”
←
C
M
→
“
6
1
“
1
”
←
”
→
“
0
”
Low-speed
(f(φ)=
CM
CM
CM
C
7
=1
6
=
b7
b4
lating)
scillating)
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
4
5
7
: Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
: Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
, CM
6: Main clock division ratio selection bit
Low-speed mode
(f(φ)=16 kHz)
b7 b6
0
0
1
1
0 : φ = f(XIN)/2 ( High-speed mode)
1 : φ = f(XIN)/8 (Middle-speed mode)
0 : φ = f(XCIN)/2 (Low-speed mode)
1 : Not available
CM
CM
CM
CM
7
=1
=0
6
5
4
=1(8 MHz stopped)
=1(32 kHz oscillating)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs by connecting prescaler 12 and Timer 1 in middle/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 76 State transitions of system clock
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-79
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
FLASH MEMORY MODE
The 3804 group (spec. H) has the flash memory that can be re-
written with a single power source.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated
using a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit
(CPU).
This flash memory has some blocks on it as shown in Figure 77
and each block can be erased.
In addition to the ordinary User ROM area to store the MCU op-
eration control program, the flash memory has a Boot ROM area
that is used to store a program to control rewriting in CPU rewrite
and standard serial I/O modes. This Boot ROM area has had a
standard serial I/O mode control program stored in it when
shipped from the factory. However, the user can write a rewrite
control program in this area that suits the user’s application sys-
tem. This Boot ROM area can be rewritten in only parallel I/O
mode.
ꢀ Summary
Table 13 lists the summary of the 3804 Group (spec. H).
Table 13 Summary of 3804 group (spec. H)
Item
Specifications
Power source voltage (Vcc)
Program/Erase VPP voltage (VPP)
Flash memory mode
VCC = 2.7 to 5
VCC = 2.7 t
3 modeI/O mode, Standard serial I/O mode, CPU rewrite mode
Erase block division
User ROM area/Data ROM area Refe7.
Boot ROM area (Note)
N(4K bytes)
Program method
Erase method
of bytes
k erase
Program/Erase control method
Number of commands
rogram/Erase control by software command
5 commands
Number of program/Erase times
ROM code protection
100
Available in parallel I/O mode and standard serial I/O mode
Note: The Boot ROM area has had a standO mode control program stored in it when shipped from the factory.
This Boot ROM area can be erasn in only parallel I/O mode.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-80
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀ Boot Mode
ꢀ CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated
on (read, program, or erase) under control of the Central Process-
ing Unit (CPU).
The control program for CPU rewrite mode must be written into
the User ROM or Boot ROM area in parallel I/O mode beforehand.
(If the control program is written into the Boot ROM area, the stan-
dard serial I/O mode becomes unusable.)
In CPU rewrite mode, only the User ROM area shown in Figure 77
can be rewritten; the Boot ROM area cannot be rewritten. Make
sure the program and block erase commands are issued for only
the User ROM area and each block area.
See Figure 77 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer
is reset with pulling CNVSS pin low. In this case, the CPU starts
operating using the control program in the User ROM area.
When the microcomputer is reset and the CNVSS pin high after
pulling the P45/TxD1 pin and CNVss pin high, the CPU starts op-
erating (start address of program is stored into addresses FFFC16
and FFFD16) using the control program in the Boot ROM area.
This mode is called the “Boot mode”. Also, User ROM area can be
rewritten using the control program in the Boot ROM area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite con-
trol program must be transferred to internal RAM area before it
can be executed.
ꢀ Block Address
Block addresses refer to the maximum address of each block.
These addresses are used in the block erase command.
000016
User ROM area
Data block B:
2K bytes
Data block A
2K byte
SFR area
100016
180016
200016
004016
083F16
Internal RAM area
(2K bytes)
RAM
Blocs
Notes 1: The boot ROM area can be rewritten in a paral-
lel I/O mode. (Access to except boot ROM
area is disablrd.)
0FE016
k 2: 16K bytes
Block 1: 8 K bytes
SFR area
0FFF16
100016
2: To specify a block, use the maximum address
in the block.
00016
FFFF16
Internal flash memory area
(60K bytes)
F00016
Boot ROM area
4K bytes
Block 0: 8 K bytes
FFFF16
FFFF16
Fig. 77 Block diagram n flash memory
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-81
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
ꢀOutline Performance
CPU rewrite mode is usable in the single-chip or Boot mode. The
Flash memory control register 0
(FMCR0: address : 0FE016: initial value: 0116
)
RY/BY status flag
0 : Busy (being written or erased)
1 : Ready
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to internal RAM area
before it can be executed.
CPU rewrite mode select bit (Note 1)
0 : CPU rewrite mode invalid
1 : CPU rewrite mode valid
8KB user block E/W enable bit (Notes 1, 2)
0 : E/W disabled
The MCU enters CPU rewrite mode by setting “1” to the CPU re-
write mode select bit (bit 1 of address 0FE016). Then, software
commands can be accepted.
1 : E/W enabled
Flash memory reset bit (Notes 3, 4)
0 : Normal operation
1 : reset
Not used (do not write “1” to this bit.)
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 78 shows the flash memory control register 0.
Bit 0 of the flash memory control register 0 is the RY/BY status
flag used exclusively to read the operating status of the flash
memory. During programming and erase operations, it is “0”
(busy). Otherwise, it is “1” (ready).
User ROM area select bit (Note 5)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Notes 1: For this bit to be set to “1”, to write a “0” and then a
“1” to it in succession. Fset to “0”, write “0” only to
this bit.
Bit 1 of the flash memory control register 0 is the CPU rewrite
mode select bit. When this bit is set to “1”, the MCU enters CPU
rewrite mode. And then, software commands can be accepted. In
CPU rewrite mode, the CPU becomes unable to access the inter-
nal flash memory directly. Therefore, use the control program in
the internal RAM for write to bit 1. To set this bit 1 to “1”, it is nec-
essary to write “0” and then write “1” in succession to bit 1. The bit
can be set to “0” by only writing “0”.
2: This bit can be wriCPU rewrite mode select bit is “1”.
3: Effective only wwrite mode select bit = “1”. Fix this
bit to “0” wheite mode select bit is “0”.
4: When sett” (when the control circuit of flash memory
is resetory cannot be accessed for 10 µs.
5: Write ogram on RAM
Fig. 78 Struash memory control register 0
b7
b0
Bit 2 of the flash memory control register 0 is the 8 KB user block
E/W enable bit. By setting combination of bit 4 of the flash memory
control register 2 and this bit as shown in Table 14, E/W is dis-
abled to user block in the CPU rewriting mode.
Flash memory control register 1
(FMCR1: address : 0FE116: initial value: 4016
)
Erase Suspend enble bit (Notes 1)
0 : Suspend invalid
1 : Suspend valid
Bit 3 of the flash memory control register 0 is the flash memory r
set bit used to reset the control circuit of internal flash mem
This bit is used when flash memory access has failed. W
CPU rewrite mode select bit is “1”, setting “1” for this bi
control circuit. To release the reset, it is necessary tit to
“0”.
Erase Suspend request bit (Notes 2)
0 : Erase restart
1 : Suspend request
Not used (do not write “1” to this bit.)
Erase Suspend flag
0 : Erase active
1 : Erase inactive (Erase Suspend mode)
Bit 5 of the flash memory control register 0 is ROM area
select bit and is valid only in the boot modthis bit to “1”
in the boot mode switches an accessibm the boot ROM
area to the user ROM area. To use ewrite mode in the
boot mode, set this bit to “1”. To it 5, execute the user-
original reprogramming contrtransferred to the internal
RAM in advance.
Not used (do not write “1” to this bit.)
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the suspend enable bit = “1”.
Fig. 79 Structure of flash memory control register 1
Bit 6 of the flash memoregister 0 is the program status
flag. This bit is set to n writing to flash memory is failed.
When program error occ, the block cannot be used.
Bit 7 of the flash memory control register 0 is the erase status flag.
This bit is set to “1” when erasing flash memory is failed. When
erase error occurs, the block cannot be used.
Figure 79 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporaly when block erase command
is executed can be used. In order to set this bit to “1”, writing “0”
and “1” in succession to bit 0. In order to set this bit to “0”, write “0”
only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-82
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
b7
b0
Flash memory control register 2
(FMCR2: address : 0FE216: initial value: 4516)
Not used
Not used (do not write “1” to this bit.)
Not used
All user block E/W enable bit (Notes 1, 2)
0 : E/W disabled
1 : E/W enabled
Not used
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the CPU rewrite mode select bit = “1”.
Fig. 80 Structure of flash memory control register 2
Table 14 State of E/W inhibition function
All user block E/W
8 KB user block E/W
8 KB ꢀꢀ2 block
Addresses C00016 to FFFF16
E/W disabled
16 KB + 24 KB block
Data block
enable bit
enable bit
Addresses 200016 to BFFFsses 100016 to 1FFF16
0
0
1
1
0
1
0
1
E/W disabled
E/W disable
E/W ena
E/W
E/W enabled
E/W enabled
E/W enabled
E/W enabled
E/W disabled
E/W disabled
E/W enabled
Figure 81 shows a flowchart for setting/releasing CPU rewrite
mode.
Start
Single-chip mode or Boot
Set CPU mod1)
Tranmode control program to
in
ontrol program transferred to internal
sequent operations are executed by control
rogram in this RAM)
Set CPU rewrite mode select bit to “1” (by
writing “0” and then “1” in succession)
Set all user block E/W enable bit to “1”
(by writing “0” and then “1” in succession)
Set 8 KB user block E/W enable bit
(At E/W disabled; writing “0”, at E/W enabled;
writing “0” and then “1” in succession)
Using software command executes erase,
program, or other operation
Execute read array command (Note 2)
Set all user block E/W enable bit to “0”
Set 8 KB user block E/W enable bit to “0”
Write “0” to CPU rewrite mode select bit
End
Notes 1: Set the main clock as follows depending on the clock division ratio selection bits of CPU
mode register (bits 6, 7 of address 003B16).
2: Before exiting the CPU rewrite mode after completing erase or program operation, always
be sure to execute the read array command.
Fig. 81 CPU rewrite mode set/release flowchart
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-83
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀ Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory
in CPU rewrite mode.
ꢀOperation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or
less using the clock division ratio selection bits (bits 6 and 7 of ad-
dress 003B16).
ꢀInstructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode.
ꢀInterrupts
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
ꢀWatchdog timer
If the watchdog timer has been already activated, internal reset
due to an underflow will not occur because the watchdog timer is
surely cleared during program or erase.
ꢀReset
Reset is always valid. The MCU is activated using the boot mode
at release of reset in the condition of CNVss = “H”, so that the pro-
gram will begin at the address which is stored in addresses
FFFC16 and FFFD16 of the boot ROM area.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-84
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀꢀSoftware Commands
The RY/BY status flag of the flash memory control register is “0”
during write operation and “1” when the write operation is com-
pleted as is the status register bit 7.
Table 15 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, execute a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
At program end, program results can be checked by reading the
status register.
• Read Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input
in one of the bus cycles that follow, the contents of the specified
address are read out at the data bus (D0 to D7).
Start
Write “4016
”
The read array mode is retained until another command is written.
• Read Status Register Command (7016)
Write address
Write data
Write
When the command code “7016” is written in the first bus cycle,
the contents of the status register are read out at the data bus (D0
to D7) by a read in the second bus cycle.
The status register is explained in the next section.
Read status register
• Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
SR7 = “
o
RY/
NO
NO
ES
R4 = “0”?
YES
• Program Command (4016)
Program
error
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed b
Program
_____
read status register or the RY/BY status flag. When the prog
starts, the read status register mode is entered automatic
the contents of the status register is read at the data
D7). The status register bit 7 (SR7) is set to “0” at tme
the write operation starts and is returned to “1” uption of
the write operation. In this case, the read statmode re-
mains active until the read array command written.
completed
Fig. 82 Program flowchart
Table 15 List of software commrewrite mode)
First bus cycle
Data
Second bus cycle
Command
Cycle number
Data
to D7)
Mode
Read
Address
Mode
Address
(D0 to D7)
(D0
(Note 4)
Read array
1
2
1
Write
Write
Write
X
FF16
7016
5016
(Note 1)
Read status register
Clear status register
X
X
X
SRD
(Note 2)
(Note 2)
Program
2
2
Write
Write
X
X
4016
2016
Write
Write
WA
WD
(Note 3)
Block erase
BA
D016
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-85
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
• Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the
second bus cycle that follows, the block erase (erase and erase
verify) operation starts for the block address of the flash memory
to be specified.
Start
Write “2016
”
Whether the block erase operation is completed can be confirmed
by read status register or the RY/BY status flag of flash memory
control register. At the same time the block erase operation starts,
the read status register mode is automatically entered, so that the
contents of the status register can be read out. The status register
bit 7 (SR7) is set to “0” at the same time the block erase operation
starts and is returned to “1” upon completion of the block erase
operation. In this case, the read status register mode remains ac-
tive until the read array command (FF16) is written.
“D016
Block address
”
Write
Read status register
SR7 = “1”?
or
RY/BY = “1”?
NO
The RY/BY status flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status reg-
ister bit 7.
YES
After the block erase ends, erase results can be checked by read-
ing the status register. For details, refer to the section where the
status register is detailed.
Erase error
SR5 = “0” ?
Eraed
(wrimmand
6”)
Erase flowchart
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-86
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀꢀStatus Register
•Erase status (SR5)
The status register shows the operating status of the flash
memory and whether erase operations and programs ended suc-
cessfully or in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
The erase status indicates the operating status of erase operation.
If an erase error occurs, it is set to “1”. When the erase status is
cleared, it is reset to “0”.
•Program status (SR4)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts
to when the read array command (FF16) is input.
The program status indicates the operating status of write opera-
tion. When a write error occurs, it is set to “1”.
The program status is reset to “0” when it is cleared.
Also, the status register can be cleared by writing the clear status
register command (5016).
If “1” is written for any of the SR5 and SR4 bits, the read array,
program, and block erase commands are not accepted. Before ex-
ecuting these commands, execute the clear status register
command (5016) and clear the status register.
After reset, the status register is set to “8016”.
Table 16 shows the status register. Each bit in this register is ex-
plained below.
Also, if any commands are not correct, both SR5 and SR4 are set
to “1”.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
Table 16 Definition of each bit in status register
Definition
Each bit of
SRD bits
Status name
“1”
“0”
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Ready
Busy
-
-
Erase status
Program status
Reserved
Terminated in error
Terminated normally
Terminated in error
Terminated normally
-
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-87
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀꢀFull Status Check
By performing full status check, it is possible to know the execu-
tion results of erase and program operations. Figure 84 shows a
full status check flowchart and the action to be taken when each
error occurs.
Read status register
YES
SR4 = “1” and
SR5 = “1” ?
Command
sequence error
Execute the clear status register command (5016
to clear the status register. Try performing the
)
operation one more time after confirming that the
command is entered correctly.
NO
NO
NO
Should an erase error occur, the rror
cannot be used.
Erase error
SR5 = “0” ?
YES
Should a program ethe block in error
cannot be used.
Program error
SR4 = “0” ?
YES
End (block erase, program)
Note: When one of SR5 and SR4 is set to “1f the read array, program,
and block erase commands is accepcute the clear status register
command (5016) before executing mmands.
Fig. 84 Full status check flowchart and remedial pfor errors
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-88
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀꢀ Functions To Inhibit Rewriting Flash
Memory Version
To prevent the contents of internal flash memory from being read
out or rewritten easily, this MCU incorporates a ROM code protect
function for use in parallel I/O mode and an ID code check func-
tion for use in standard serial I/O mode.
If one or both of the pair of ROM code protect bits is set to “0”, the
ROM code protect is turned on, so that the contents of internal
flash memory are protected against readout and modification. The
ROM code protect is implemented in two levels. If level 2 is se-
lected, the flash memory is protected even against readout by a
shipment inspection LSI tester, etc. When an attempt is made to
select both level 1 and level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal
flash memory can be readout or modified. Once the ROM code
protect is turned on, the contents of the ROM code protect reset
bits cannot be modified in parallel I/O mode. Use the serial I/O or
CPU rewrite mode to rewrite the contents of the ROM code protect
reset bits.
(1) ROM Code Protect Function
The ROM code protect function is the function to inhibit reading
out or modifying the contents of internal flash memory by using
the ROM code protect control address (address FFDB16) in paral-
lel I/O mode. Figure 85 shows the ROM code protect control
address (address FFDB16). (This address exists in the User ROM
area.)
Rewriting of only the ROM code protect control address (address
FFDB16) cannot be performed. When rewriting the ROM code pro-
tect reset bit, rewrite the whole ROM area (block 0)
containing the ROM code protect ress.
b7
b0
ROM code protect control address FFDB16
ROMCP (FF16 when ship
)
1 1
Reserved bits (“1” at r)
ROM code protect t bits (ROMCP2) (Notes 1, 2)
b3b2
0 0: Protect
0 1: Proted
1 0: Pabled
1 disabled
protect reset bits (ROMCR) (Note 3)
: Protect removed
0 1: Protect set bits effective
1 0: Protect set bits effective
1 1: Protect set bits effective
ROM code protect level 1 set bits (ROMCP1) (Note 1)
b7b6
0 0: Protect enabled
0 1: Protect enabled
1 0: Protect enabled
1 1: Protect disabled
Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect reset bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
Fig. 85 Structure of ROM code protect control address
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-89
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
(2) ID Code Check Function
Use this function in standard serial I/O mode. When the contents
of the flash memory are not blank, the ID code sent from the pro-
grammer is compared with the ID code written in the flash memory
to see if they match. If the ID codes do not match, the commands
sent from the programmer are not accepted. The ID code consists
of 8-bit data, and its areas are FFD416 to FFDA16. Write a pro-
gram which has had the ID code preset at these addresses to the
flash memory.
Address
FFD416
FFD516
FFD616
ID1
ID2
ID3
ID4
ID5
ID6
FFD716
FFD816
FFD916
ID7
FFDA16
FFDB16
ROM code protect control
Interrupt vector area
Fig. 86 ID code store addresses
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-90
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀꢀParallel I/O Mode
The parallel I/O mode is used to input/output software commands,
address and data in parallel for operation (read, program and
erase) to internal flash memory.
Use the external device (writer) only for 3804 Group (spec. H). For
details, refer to the user’s manual of each writer manufacturer.
• User ROM and Boot ROM Areas
In parallel I/O mode, the User ROM and Boot ROM areas shown
in Figure 77 can be rewritten. Both areas of flash memory can be
operated on in the same way.
The Boot ROM area is 4 Kbytes in size and located at addresses
F00016 through FFFF16. Make sure program and block erase op-
erations are always performed within this address range. (Access
to any location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial
I/O mode control program stored in it when shipped from the fac-tory.
Therefore, using the MCU in standard serial I/O mode, do not
rewrite to the Boot ROM area.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-91
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
ꢀꢀStandard serial I/O Mode
The standard serial I/O mode inputs and outputs the software
commands, addresses and data needed to operate (read, pro-
gram, erase, etc.) the internal flash memory. This I/O is clock
synchronized serial. This mode requires a purpose-specific pe-
ripheral unit.
The standard serial I/O mode is different from the parallel I/O
mode in that the CPU controls flash memory rewrite (uses the
CPU rewrite mode), rewrite data input and so forth. The standard
serial I/O mode is started by connecting “H” to the CNVss pin and
“H” to the P45 (BOOTENT) pin, and releasing the reset operation.
(In the ordinary microcomputer mode, set CNVss pin to “L” level.)
This control program is written in the Boot ROM area when the
product is shipped from Renesas. Accordingly, make note of the
fact that the standard serial I/O mode cannot be used if the Boot
ROM area is rewritten in parallel I/O mode. The standard serial I/
O mode has standard serial I/O mode 1 of the clock synchronous
serial and standard serial I/O mode 2 of the clock asynchronous
serial. Tables 17 and 18 show description of pin function (standard
serial I/O mode). Figures 87 to 90 show the pin connections for
the standard serial I/O mode.
In standard serial I/O mode, only the User ROM area shown in
Figure 77 can be rewritten. The Boot ROM area cannot be written.
In standard serial I/O mode, a 7-byte ID code is used. When there
is data in the flash memory, this function determines whether the
ID code sent from the peripheral unit (programmer) and those writ-
ten in the flash memory match. The commands sent from the
peripheral unit (programmer) are not accepted unless the ID code
matches.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-92
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
Table 17 Description of pin function (Flash Memory Serial I/O Mode 1)
Pin name
VCC,VSS
Signal name
Power supply
I/O
Function
I
I
I
Apply 2.7 to 5.5 V to the Vcc pin and 0 V to the Vss pin.
After input of port is set, input “H” level.
CNVSS
RESET
CNVSS
Reset input
Reset input pin. To reset the microcomputer, RESET pin should be held at an
“L” level for 16 cycles or more of XIN.
XIN
Clock input
I
Connect an oscillation circuit between the XIN and XOUT pins.
As for the connection method, refer to the “clock generating circuit”.
Connect AVss to Vss.
XOUT
AVSS
VREF
Clock output
O
Analog power supply input
Reference voltage input
I
Apply reference voltage of A/D to this pin.
P00–P07,P10–P17, I/O port
P20–P27,P30–P37,
P40–P43,P50–P57,
P60–P67
I/O
Input “L” or “H” level, or keep open.
P44
P45
P46
P47
RxD input
I
Serial data input pin.
Serial data output pin.
Serial clock input pin.
BUSY signal output pin.
TxD output
SCLK input
BUSY output
O
I
O
Table 18 Description of pin function (Flash Memory Serial I/O Mode 2)
Pin name
VCC,VSS
Signal name
Power supply
I/O
Apply 2.7 to 5.5 V to the Vcc pio the Vss pin.
After input of port is set, inel.
I
I
I
CNVSS
RESET
CNVSS
Reset input
Reset input pin. To resocomputer, RESET pin should be held at an
“L” level for 16 cyclof XIN.
XIN
Clock input
I
Connect an oscillt between the XIN and XOUT pins.
As for the coethod, refer to the “clock generating circuit”.
Connect As.
XOUT
AVss
VREF
Clock output
O
Analog power supply input
Reference voltage input
I
Apply voltage of A/D to this pin.
P00–P07,P10–P17, I/O port
P20–P27,P30–P37,
P40–P43,P50–P57,
P60–P67
I/O
Inp” level, or keep open.
P44
P45
P46
P47
RxD input
Serial data input pin.
Serial data output pin.
Input “L” level.
TxD output
SCLK input
BUSY output
I
O
BUSY signal output pin.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-93
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
P20(LED0)
P21(LED1)
PD2)
)
ED4)
5(LED5)
P26(LED6)
P27(LED7)
P37/SRDY3
31
30
29
28
27
23
22
21
20
19
18
17
P36/SCLK3
P35/TXD3
P34/RXD3
P33/SCL
P32/SDA
P31/DA2
P30/DA1
VCC
M38049FFHFP/HP/KP
VSS
VCC
VSS
XOUT
VREF
✽
XIN
AVSS
P40/INT40/XCOUT
P41/INT00/XCIN
RESET
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
RESET
CNVss
CNVSS
P42/INT1
✽ Connect oscillation circuit.
indicates flash memory pin.
RxD
TxD
SCLK
BUSY
Package type: 64P6N-A/64P6Q-A/64P6U-A
Fig. 87 Connection for standard serial I/O mode 1 (M38049FFHFP/HP/KP)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-94
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
49
50
51
32
31
P20(LED0)
P21(LED1)
P22(LED2)
P23(LED3)
PD4)
D6)
P37/SRDY3
P36/SCLK3
P35/TXD3
P34/RXD3
30
29
28
27
26
25
21
20
19
18
17
52
53
54
55
56
57
58
P33/SCL
P32/SDA
P31/DA2
P30/DA1
7(LED7)
M38049FFHFP/HP/KP
VCC
VCC
VSS
VSS
XOUT
VREF
AVSS
✽
59
60
XIN
P40/INT40/XCOUT
P41/INT00/XCIN
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
61
62
63
64
RESET
RESET
CNVSS
CNVss
P42/INT1
✽ Connect oscillation circuit.
RxD
indicates flash memory pin.
TxD
“L” input
BUSY
Package type: 64P6N-A/64P6Q-A/64P6U-A
Fig. 88 Connection for standard serial I/O mode 2 (M38049FFHFP/HP/KP)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-95
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
V
CC
V
V
AVSS
/AN
/AN
/AN
CC
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
5
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P3
P3
P3
P3
P3
P3
P3
P3
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/DA
/DA
/SDA
/SCL
1
2
REF
P6
P6
P6
7
6
5
7
6
5
/R
/T
X
D
3
X
D
3
P6
4
/AN
4
/
S
CLK3
P6
P6
P6
P6
3
2
1
0
/AN
/AN
/AN
/AN
/INT
/PWM
3
2
1
0
3
/
SRDY3
9
/AN
/AN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
30
31
32
/AN10
/AN11
/AN12
/AN13
/AN14
/AN15
/INT41
/INT01
P5
P5
7
6
P5
P5
5
/CNTR
/CNTR
1
4
0
P5
P5
P5
P5
CNTR
P4
P4
3
/SRDY2
/SCLK2
/SOUT2
/SIN2
2
1
0
P4
7
/SRDY1
/
2
BUSY
S
CLK
6
/SCLK1
5
/T
/R
X
D
D
1
1
2
1
TXD
P4
P4
P4
4
X
R
X
D
3
/INT
/INT
CNVSS
2
(LED
(LED
(LED
(LED
(LED
(LED
(LED
(LED
0
)
)
)
)
)
)
)
)
CNVSS
1
2
3
4
5
6
7
RESET
/INT00/XCIN
P4 /INT40/XCOUT
RESET
P4
1
0
X
I
✽
X
V
SS
✽ Connect oscillation cir
indicates flash pin.
Package type: 64P4B
Fig. 89 Connection for standarmode 1 (M38049FFHSP)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-96
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
V
V
AVSS
/AN
/AN
/AN
CC
1
2
3
4
5
6
7
8
V
CC
64
63
62
61
60
59
58
57
56
55
54
0
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P3
P3
P3
P3
P3
P3
P3
P3
P0
P0
P0
P0
P0
P0
P0
P0
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
/DA
/DA
/SDA
/SCL
1
2
REF
P6
P6
P6
7
6
5
7
6
5
/R
/T
X
D
3
X
D
3
P6
4
/AN
4
/
S
CLK3
P6
P6
P6
P6
3
2
1
0
/AN
/AN
/AN
/AN
/INT
/PWM
3
2
1
0
3
/
SRDY3
9
/AN
/AN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
8
29
30
31
32
/AN10
/AN11
/AN12
/AN13
/AN14
/AN15
/INT41
/INT01
P5
P5
7
6
P5
P5
5
/CNTR
/CNTR
1
4
0
P5
P5
P5
P5
CNTR
P4 /SCLK1
P4
3
/SRDY2
/SCLK2
/SOUT2
2
1
0
/SIN2
P4
7
/SRDY1
/
2
BUSY
6
“L” input
5
/T
/R
X
X
D
D
1
1
2
1
TXD
P4
P4
P4
4
RXD
3
/INT
/INT
CNVSS
2
(LED
(LED
(LED
(LED
(LED
(LED
(LED
(LED
0
)
)
)
)
)
)
)
)
CNVSS
1
2
3
4
5
6
7
RESET
RESET
/INT00/XCIN
P4 /INT40/XCOU
P4
1
0
✽
V
SS
✽ Connect oscillation circuit.
indicates flash memory pin.
Package type: 64P4B
Fig. 90 Connection for standard serial I/O mode 2 (M38049FFHSP)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-97
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION
td(CNVSS-RESET)
td(P4 -RESET)
5
Power source
RESET
CNVSS
P45(TXD)
P46(SCLK)
P47(BUSY)
P44(RXD)
Limits
Notes: In the standard serial I/O mode 1, inpP4
Be sure to set the CNVss pin to “Hg RESET.
Be sure to set the P4 pin to “Hg RESET.
6 pin.
Symbol
Unit
Min.
0
Typ. Max.
–
5
–
ms
ms
td(CNVss-RESET)
td(P4 -RESET)
5
0
Fig. 91 Operating waveform for standard serial I/O mode 1
td(CNV
td(P4
Power source
RESET
CNVSS
P45(T
P46(SC
P47(BUSY)
P44
(RX
D)
Limits
Notes: In the standard serial I/O mode 2, input “H” to the P4
Be sure to set the CNVss pin to “H” before rising RESET.
Be sure to set the P4 pin to “H” before rising RESET.
6 pin.
Symbol
Unit
Min.
0
Typ. Max.
5
–
ms
ms
–
td(CNVss-RESET)
td(P4 -RESET)
5
0
Fig. 92 Operating waveform for standard serial I/O mode 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-98
HARDWARE
3804 Group (Spec.H)
NOTES ON PROGRAMMING
NOTES ON PROGRAMMING
Serial Interface
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1.”
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed. SOUT2 pin for serial I/O2 goes to high
impedance after transfer is completed.
When in serial I/Os 1 and 3 (clock-synchronous mode) or in serial
I/O2, an external clock is used as synchronous clock, write trans-
mission data to the transmit buffer register or serial I/O2 register,
during transfer clock is “H.”
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
A/D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is aon 500 kHz during an
A/D conversion.
Decimal Calculations
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
Do not execute the STP instruan A/D conversion.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
D/A Converter
The accuracy of the erter becomes rapidly poor under
the VCC = 4.0 V oition; a supply voltage of VCC ≥ 4.0 V
is recommendD/A converter is not used, set all values
of D/Ai conisters (i=1, 2) to “0016.”
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
InstExecution Time
Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
Ton execution time is obtained by multiplying the pe-
e internal clock φ by the number of cycles needed to
te an instruction.
• The execution of these instructions does not change the con
tents of the processor status register.
e number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is double of the XIN period in
high-speed mode.
Ports
The contents of the port direction registers cannot The
following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index ag (T) is “1”
• The instruction with the addressing h uses the value
of a direction register as an index
• The bit-test instruction (BBC or to a direction register
• The read-modify-write instrOR, CLB, or SEB, etc.) to
a direction register.
Use instructions such aSTA, etc., to set the port direc-
tion registers.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-99
HARDWARE
3804 Group (Spec.H)
NOTES ON USAGE
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), and between power
source pin (VCC pin) and analog power source input pin (AVSS
pin). Besides, connect the capacitor to as close as possible. For
bypass capacitor which should not be located too far from the pins
to be connected, a ceramic capacitor of 0.01 µF–0.1 µF is recom-
mended.
Power Source Voltage
When the power source voltage value of a microcomputer is less
than the value which is indicated as the recommended operating
conditions, the microcomputer does not operate normally and may
perform unstable operation.
In a system where the power source voltage drops slowly when
the power source voltage drops or the power supply is turned off,
reset a microcomputer when the power source voltage is less than
the recommended operating conditions and design a system not
to cause errors to the system by this unstable operation.
Flash Memory Version
The CNVss pin determines the flash memory mode. To improve
the noise reduction, connect a track between CNVss pin and Vss
pin or Vcc pin with 1 to 10 kΩ resistance. The mask ROM version
track of CNVss pin has no operational interference even if it is
connected to Vss pin or Vcc pin via a resistor.
Electric Characteristic Differences Between
Mask ROM and Flash Memory Version MC
There are differences in electric characteristics, operation
noise immunity, and noise radiation between Mask
Flash Memory version MCUs due to the difference in fac-
turing processes, built-in ROM, and layout p.When
manufacturing an application system with the mory ver-
sion and then switching to use of the Masrsion, please
conduct evaluations equivalent to the valuations con-
ducted for the flash memory version
DATA REQUIRED FOK ORDERS
The following are necessadering a mask ROM produc-
tion:
ꢀ
1.Mask ROM Confirmm
2.Mark Specification For
3.Data to be written to ROM, in EPROM form (three identical cop-
ies)
ꢀ For the mask ROM confirmation and the mark specifications,
refer to the “Renesas Technology Corp.” Homepage
(http://www.renesas.com/en/rom).
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-100
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION SUPPLEMENT
FUNCTIONAL DESCRIPTION SUPPLEMENT
Interrupt
The 3804 group (Spec. H) permits interrupts on the basis of 16
sources. It is vector interrupts with a fixed priority system. Accord-
ingly, when two or more interrupt requests occur during the same
sampling, the higher-priority interrupt is accepted first. This priority
is determined by hardware, but variety of priority processing can
be performed by software, using an interrupt enable bit and an in-
terrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer
to “Table 19”.
Table 19 Interrupt sources, vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
emarks
able
Interrupt Source
Priority
High
Low
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Reset (Note 2)
INT0
At reset
At detection of either rising or
falling edge of INT0 input
l interrupt
ve edge selectable)
Timer Z
INT1
At timer Z underflow
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
3
4
5
External interrupt
(active edge selectable)
At detection of either
falling edge of INT1 i
Serial I/O1
reception
Valid when serial I/O1 is selected
At completion of data
reception
Serial I/O1
transmission
Valid when serial I/O1 is selected
At compleerial I/O1
transmift or when
transmer is empty
At of either rising or
fof SCL or SDA
SCL, SDA
External interrupt
(active edge selectable)
X underflow
mer Y underflow
t timer 1 underflow
At timer 2 underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFE
F
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
8
STP release timer underflow
9
10
At detection of either rising or
falling edge of CNTR0 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of SCL or SDA
SCL, SDA
CNTR1
External interrupt
(active edge selectable)
11
FF
FFE816
At detection of either rising or
falling edge of CNTR1 input
External interrupt
(active edge selectable)
Serial I/O3
reception
At completion of serial I/O3 data Valid when serial I/O3 is selected
reception
12
E716
FFE516
FFE616
FFE416
Serial I/O2
At completion of serial I/O2 data Valid when serial I/O2 is selected
transmission or reception
Timer Z
INT2
At timer Z underflow
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
2
At completion of data transfer
I C
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT3 input
INT3
14
15
FFE316
FFE116
FFE216
FFE016
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT4 input
INT4
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR2 input
CNTR2
A/D converter
At completion of A/D conversion
16
17
FFDF16
FFDD16
FFDE16
FFDC16
Valid when serial I/O3 is selected
Non-maskable software interrupt
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Serial I/O3
transmission
BRK instruction
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-101
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION SUPPLEMENT
Timing After Interrupt
The interrupt processing routine begins with the machine cycle fol-
lowing the completion of the instruction that is currently in
execution.
Figure 93 shows a timing chart after an interrupt occurs, and Fig-
ure 94 shows the time up to execution of the interrupt processing
routine.
φ
SYNC
RD
WR
S, SPS S-1, SPS S-2, SPS
Address bus
Data bus
B
L
B
H
PC
Not used
PC
H
PC
L
PS
A
L
: CPU operation code fetch cycle
SYNC
(This is an internal signal that cannot be obsethe external unit.)
H : Vector address of each interrupt
H : Jump destination address of each inter
B
A
L
L
, B
, A
: “0016” or “0116
”
SPS
Fig. 93 Timing chart after an interrupt occurs
Interrupt request generated
Start of interrupt processing
aiting time for
post-processing
of pipeline
Stack push and
Vector fetch
Interrupt processing routine
Main routine
cycles
2 cycles
5 cycles
7 to 23 cycles
(When f(XIN) = 8.4 MHz, 0.83 µs to 2.74 µs)
Fig. 94 Time up to execution of the interrupt processing routine
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-102
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION SUPPLEMENT
A/D Converter
By repeating the above operations up to the lowest-order bit of the
AD conversion register, an analog value converts into a digital
value.
A/D conversion is started by setting AD conversion completion bit
to “0”. During A/D conversion, internal operations are performed
as follows.
In the 10-bit A/D mode, A/D conversion completes at 61 cycles of
2tc(XIN)* (15.25 µs at f(XIN) = 8.0 MHz) after it is started. In the 8-
bit A/D mode, A/D conversion completes at 50 cycles of 2tc(XIN)
(12.5 µs at f(XIN) = 8.0 MHz) after it is started. And the result of
the conversion is stored into the AD conversion register.
Concurrently with the completion of A/D conversion, the A/D con-
version completion bit is set to “1” and an A/D conversion interrupt
request occurs, so that the AD conversion interrupt request bit is
set to “1”.
1. After the start of A/D conversion, AD conversion register
goes to “0016”.
2. The highest-order bit of AD conversion register is set to
“1”. and the comparison voltage Vref is input to the
comparator. Then, Vref is compared with analog input voltage
VIN.
3. As a result of comparison, when Vref < VIN, the highest-
order bit of AD conversion register becomes “1.” When
Vref > VIN, the highest-order bit becomes “0.”
* tc(XIN) = Main clock input cycle time
Table 20 Relative formula for a reference voltage VREF of A/D converter and Vref (at 10-bit A/D mode
When n = 0
Vref = 0
VREF
When n = 1 to 1023
Vref =
ꢀ n
1024
n : Value of A/D converter (decimal numeral)
Table 21 Relative formula for a reference voltage VREF of A/D converter and VrA/D mode)
When n = 0
Vref = 0
VREF
When n = 1 to 255
Vref =
ꢀ (n – 0.5)
256
n : Value of A/D converter (decimal numeral)
Table 22 Change of AD conversion register during A/D c(at 10-bit A/D mode)
Change of Aon register
Value of comparison voltage (Vref)
0
At start of conversion
First comparison
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
2
VREF
VREF
ꢀ 1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
±
Second comparison
Third comparison
4
2
VREF
VREF
VREF
2
±
±
8
2
4
•
•
•
•
•
•
•
•
•
After completio
tenth comparison
A result of A/D conversion
ꢀ4 ꢀ5 ꢀ6 ꢀ7 ꢀ8 ꢀ9 ꢀ10
VREF
VREF
VREF
±
± •••
±
ꢀ1 ꢀ2 ꢀ3
2
4
1024
ꢀ1–ꢀ10: A result of the first to tenth comparison
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-103
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION SUPPLEMENT
Table 23 Change of AD conversion register during A/D conversion (at 8-bit A/D mode)
Change of AD conversion register
Value of comparison voltage (Vref)
0
At start of conversion
First comparison
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VREF
VREF
–
2
512
VREF
VREF
VREF
ꢀ1
0
1
0
0
0
0
0
0
0
0
–
±
Second comparison
Third comparison
1
0
0
512
4
2
VREF
VREF
VREF
VREF
–
ꢀ1 ꢀ2
±
±
512
8
2
4
•
•
•
•
•
•
•
•
•
After completion of
eighth comparison
A result of A/D conversion
VREF
VREF
VREF
VREF
±
–
••
±
ꢀ 1 ꢀ2 ꢀ3
2
4
ꢀ4 ꢀ5 ꢀ6 ꢀ7 ꢀ8
256
512
ꢀ1–ꢀ8: A result of the first to eighth comparison
Figure 95 shows A/D conversion equivalent circuit, and Figure 96
shows A/D conversion timing chart.
V
CC
V
SS
AVSS
About 2 kΩ
V
IN
AN
AN
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
8
C
Chopper amplifier
AD conversion register 1
AD conversion register 2
AD conversion interrupt request
12
AN13
AN14
AN15
b4 b2 b1 b0
AD/DA control register
V
ref
V
REF
Built-in
D/A converter
Reference
clock
AVSS
Fig. 95 A/D conversion equivalent circuit
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-104
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION SUPPLEMENT
XIN
2
Write signal for AD
control register
At 10-bit A/D mode : 61 cycles
At 8-bit A/D mode : 50 cycles
AD conversion
completion bit
Sampling clock
Fig. 96 A/D conversion timing chart
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-105
HARDWARE
3804 Group (Spec.H)
FUNCTIONAL DESCRIPTION SUPPLEMENT
Memo
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
1-106
HAPTER 2
APPLICATION
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
I/O port
Interrupt
Timer
Serial interface
Multi-master I2C-BUS interface
PWM
A/D converter
D/A converter
Watchdog timer
2.10 Reset
2.11 Clock generating circuit
2.12 Standby function
2.13 Flash memory mode
APPLICATION
2.1 I/O port
3804 Group (Spec.H)
2.1 I/O port
This paragraph describes the setting method of I/O port relevant registers, notes etc.
2.1.1 Memory map
Address
000016 Port P0 (P0)
000116 Port P0 direction register (P0D)
000216 Port P1 (P1)
000316 Port P1 direction register (P1D)
000416 Port P2 (P2)
000516 Port P2 direction register (P2D)
000616 Port P3 (P3)
000716
Port P3 direction register
000816 Port P4 (P4)
000916 Port P4 direction r(P4D)
000A16 Port P5 (P5)
000B16 Port P5 diregister (P5D)
000C16 Port P6
000D16 Port ection register (P6D)
0FPort P0 pull-up control register (PULL0)
16 Port P1 pull-up control register (PULL1)
FF216
0FF316
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
0FF416
0FF516
0FF616
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
Fig. 2.1.1 Memory map of I/O port relevant registers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-2
APPLICATION
2.1 I/O port
3804 Group (Spec.H)
2.1.2 Relevant registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 6)
(Pi: addresses 000016, 000216, 000416, 000616, 000816, 000A16, 000C16
)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi
0
1
2
3
4
5
6
7
0
0
0
0
0
ꢀIn output mode
Write •••••••• Port latch
Read •••••••• Port latch
ꢀIn input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Fig. 2.1.2 Structure of Port Pi (i = 0 to 6)
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction register (3, 4, 5, 6)
(PiD: addresses 0001000516, 000716, 000916, 000B16, 000D16
)
b
0
Nam
Port Pi
regist
Functions
0 : Port Pi0 input mode
1 : Port Pi0 output mode
At reset R W
0
0 : Port Pi1 input mode
1 : Port Pi1 output mode
0
0
0
0
0
0
0
1
4
5
6
7
0 : Port Pi2 input mode
1 : Port Pi2 output mode
0 : Port Pi3 input mode
1 : Port Pi3 output mode
0 : Port Pi4 input mode
1 : Port Pi4 output mode
0 : Port Pi5 input mode
1 : Port Pi5 output mode
0 : Port Pi6 input mode
1 : Port Pi6 output mode
0 : Port Pi7 input mode
1 : Port Pi7 output mode
Fig. 2.1.3 Structure of Port Pi direction register (i = 0 to 6)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-3
APPLICATION
2.1 I/O port
3804 Group (Spec.H)
Port Pi pull-up control register (i = 0 to 2, 4 to 6)
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi pull-up control register (i = 0 to 2, 4 to 6)
(PULLi: addresses 0FF016, 0FF116, 0FF216, 0FF416, 0FF516, 0FF616
)
b
0
Name
pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Functions
0: No pull-up
1: Pull-up
At reset R W
0
Port Pi
0
1
0
0
0
0: No pull-up
1: Pull-up
1
2
3
4
5
6
7
2
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
3
4
0: No pull-up
1: Pull-up
5
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
6
0
0
7
0: No pull-u
1: Pull-up
Fig. 2.1.4 Structure of Port Pi pull-up control regist, 1, 2, 4, 5, 6)
Port P3 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 ntrol register
(PULs 0FF316
)
Name
Functions
0: No pull-up
1: Pull-up
At reset R W
0
ort P3
0
pull-up
control bit
Port P3
control bit
1
pull-up
0
0
0: No pull-up
1: Pull-up
1
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
2
3
0
Port P3
4
pull-up
control bit
Port P3 pull-up
control bit
Port P3 pull-up
control bit
Port P3 pull-up
control bit
0: No pull-up
1: Pull-up
0
4
5
6
7
0
5
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
6
0
0
7
0: No pull-up
1: Pull-up
Fig. 2.1.5 Structure of Port P3 pull-up control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-4
APPLICATION
2.1 I/O port
3804 Group (Spec.H)
2.1.3 Port Pi pull-up control register
Valid/Invalid of pull-up resistor can be set by the pull-up control register by a bit unit. Pull-up control is valid
only when each direction register is set to the input mode.
Note: Ports P3
2
and P3 do not have pull-up control bit because they are N-channel open-drain output.
3
2.1.4 Terminate unused pins
Table 2.1.1 Termination of unused pins (in single-chip mode)
Pins
Termination
P0, P1, P2, P3, • Set to the input mode and connect each to VCC or VSS through a resistor of 1 kΩ to
P4, P5, P6
10 kΩ.
• Set to the output mode and open at “L” or “H” output state.
Connect to Vss (GND).
V
REF
AVSS
Connect to Vss (GND).
X
OUT
Open (only when using external clock)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-5
APPLICATION
2.1 I/O port
3804 Group (Spec.H)
2.1.5 Notes on I/O port
(1) Notes in standby state
In standby stateꢀ1 for low-power dissipation, do not make input levels of an I/O port “undefined”,
especially for I/O ports of the N-channel open-drain.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing out to exte
ꢀ Reason
Even when setting as an output port with its direction register, whcontent of the port latch
is “1”, the transistor becomes the OFF state, which causes thto be the high-impedance
state. Note that the level becomes “undefined” depending onal circuits.
Accordingly, the potential which is input to the input buffeicrocomputer is unstable in the
state that input levels of an I/O port are “undefined”. y cause power source current.
ꢀ1 standby state: stop mode by executing STP ion
wait mode by executing WIT tion
(2) Modifying output data with bit managing ction
When the port latch of an I/O port is moith the bit managing instructionꢀ2, the value of the
unspecified bit may be changed.
ꢀ Reason
The bit managing instructioead-modify-write form instructions for reading and writing data
by a byte unit. Accordingn these instructions are executed on a bit of the port latch of an
I/O port, the following uted to all bits of the port latch.
•As for bit which is input port:
The pin state is the CPU, and is written to this bit after bit managing.
•As for bit whet for output port:
The bit vaead in the CPU, and is written to this bit after bit managing.
Note the wing:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
ꢀ2 Bit managing instructions: SEB and CLB instructions
Rev.1.00 Jan 14, 2005
2-6
REJ09B0212-0100Z
APPLICATION
2.1 I/O port
3804 Group (Spec.H)
2.1.6 Termination of unused pins
(1) Terminate unused pins
➀ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system evaluation on the user
side.
• Since the direction register setup may be changed because of a prograway or noise, set
direction registers by program periodically to increase the reliabilitgram.
➀ The AVss pin when not using the A/D converter :
• When not using the A/D converter, handle a power source the A/D converter, AVss pin
as follows:
AVss: Connect to the Vss pin.
(2) Termination remarks
➀ I/O ports :
Do not open in the input mode.
➀ Reason
• The power source current may e depending on the first-stage circuit.
• An effect due to noise may by produced as compared with proper termination ➀ and
shown on the above.
➀ I/O ports :
When setting for the inde, do not connect to VCC or VSS directly.
➀ Reason
If the direction r setup changes for the output mode because of a program runaway or
noise, a shit may occur between a port and VCC (or VSS).
➀ I/O ports
When sor the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
➀ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.1.00 Jan 14, 2005
2-7
REJ09B0212-0100Z
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
2.2 Interrupt
This paragraph explains the registers setting method and the notes relevant to the interrupt.
2.2.1 Memory map
Interrupt source selection register (INTSEL)
003916
003A16 Interrupt edge selection register (INTEDGE)
003C16 Interrupt request register 1 (IREQ1)
003D16 Interrupt request register 2 (IREQ2)
003E16 Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
003F16
Fig. 2.2.1 Memory map of registers relevant to interrupt
2.2.2 Relevant registers
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selec
(INTSEL: address 0
b
0
N
Functions
interrupt
At reset R W
0
INT
0
/
0: INT
0
intrce
bit (*1)
1: Timer Z interrupt
0: Serial I/O2 interrupt
1: Timer Z interrupt
0
0
I/O2/Timer Z
rrupt source
election bit (*1)
Serial I/O1 transmit/
SCL, SDA interrupt
source selection bit
(*2)
0: Serial I/O1 transmit
interrupt
1: SCL, SDA interrupt
0
0
3
4
0: CNTR
1: SCL, SDA interrupt
0
interrupt
CNTR0/SCL, SDA
interrupt source
selection bit (*2)
0: INT
1: CNTR
4
interrupt
interrupt
INT /CNTR2
4
2
interrupt source
selection bit
0
0
0: INT
2
interrupt
5
6
INT
2
/I2C interrupt
1: I2C interrupt
source selection bit
CNTR /Serial I/O3
receive interrupt
source selection bit
0: CNTR interrupt
1: Serial I/O3 receive
interrupt
1
1
0
7
AD converter/Serial
I/O3 transmit
interrupt source
selection bit
0: A/D converter interrupt
1: Serial I/O3 transmit
interrupt
*1: Do not write 1 to these bits simultaneously.
*2: Do not write 1 to these bits simultaneously.
Fig. 2.2.2 Structure of Interrupt source selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-8
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 003A16
)
b
0
Name
Functions
0: Falling edge active
1: Rising edge active
At reset R W
0
INT
0
active edge
selection bit
INT active edge
selection bit
0: Falling edge active
1: Rising edge active
0
0
1
1
2 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
0
3 INT
selection bit
INT active edge
selection bit
INT active edge
selection bit
INT , INT interrupt
switch bit
2
active edge
0: Falling edge active
1: Rising edge active
3
4
5
6
0: Falling edge active
1: Rising edge active
4
0: Falling edge active
1: Rising edge activ
0
4
0: INT00, INT40 i
1: INT01, INT4t
0
7 Nothing is arranged for this bit. write
disabled bit. When this bit is rhe
contents are “0”.
Fig. 2.2.3 Structure of Interrupt edge selection r
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Intest register 1
(dress 003C16
)
Name
Functions
At reset R W
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
INT
0
/Timer Z
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2 Serial I/O1 receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
3 Serial I/O1
transmit/SCL, SDA
interrupt request bit
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
4 Timer X interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
5
0 : No interrupt request issued
1 : Interrupt request issued
Timer Y interrupt
request bit
6
7
Timer 1 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
Timer 2 interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
0
ꢀ: 0 can be set by software, but 1 cannot be set.
Fig. 2.2.4 Structure of Interrupt request register 1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-9
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 003D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
ꢀ
0
CNTR
0/SCL, SDA
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
0
1 CNTR
/Serial I/O3
1
receive interrupt
request bit
Serial I/O2/Timer Z 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
2
3
4
INT
request bit
INT interrupt
request bit
2
/I2C interrupt
0 : No interrupt request issued
1 : Interrupt request issued
3
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request is
1 : Interrupt request
5 INT
/CNTR
4
2
interrupt request bit
AD converter/Serial
I/O3 transmit
interrupt request bit
0 : No interrupt req
1 : Interrupt reqed
6
0
7
Nothing is arranged for this bia write
disabled bit. When this bit it, the
contents are 0 .
ꢀ: 0 can be set by sut 1 cannot be set.
Fig. 2.2.5 Structure of Interrupt request regis
Interrupt control register
b7 b6 b5 b4 b3 b2 b1 b0
control register 1
N1 : address 003E16
)
b
0
Name
Functions
At reset R W
0
INT
0
/Timer Z
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
0
1 INT
1
interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
2 Serial I/O1 receive
interrupt enable bit
Serial I/O1
3
0 : Interrupt disabled
transmit/SCL, SDA 1 : Interrupt enabled
interrupt enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
4
5
6
7
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Timer 1 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0
0
Timer 2 interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
Fig. 2.2.6 Structure of Interrupt control register 1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-10
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
0
Interrupt control register 2
(ICON2 : address 003F16)
b
0
Name
/SCL, SDA
interrupt enable bit
CNTR / Serial I/O3
receive interrupt
enable bit
Functions
At reset R W
0
CNTR
0
0 : Interrupt disabled
1 : Interrupt enabled
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2/ Timer Z
interrupt enable bit
0
0
0
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
INT
enable bit
INT interrupt
enable bit
2
/I2C interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
3
INT /CNTR2
4
0 : Interrupt disable
1 : Interrupt enab
interrupt enable bit
AD converter/Serial
I/O3 transmit
interrupt enable bit
0 : Interrupt di
1 : Interrupt
7
Fix this bit to “0”.
0
Fig. 2.2.7 Structure of Interrupt control registe
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-11
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
2.2.3 Interrupt source
The 3804 group (Spec. H) ’s interrupts are a type of vector and occur by 16 sources among 23 sources:
nine external, thirteen internal, and one software. These are vector interrupts with a fixed priority system.
Accordingly, when two or more interrupt requests occur during the same sampling, the higher-priority
interrupt is accepted first. This priority is determined by hardware, but a variety of priority processing can
be performed by software, using an interrupt enable bit and an interrupt disable flag.
For interrupt sources, vector addresses and interrupt priority, refer to Tables 2.2.1.
Table 2.2.1 Interrupt sources, vector addresses and priority
Vector Addresses (Note 1)
Interrupt Request
Generating Conditions
Remarks
Non-maskable
Interrupt Source
Priority
High
Low
Reset (Note 2)
INT0
1
2
FFFD16
FFFB16
FFFC16
FFFA16
At reset
At detection of either rising or
falling edge of INT0 input
External rrupt
(active lectable)
Timer Z
INT1
At timer Z underflow
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
3
4
5
terrupt
edge selectable)
At detection of either rising or
falling edge of INT1 input
Serial I/O1
reception
when serial I/O1 is selected
At completion of serial I/O1 d
reception
Serial I/O1
transmission
Valid when serial I/O1 is selected
At completion of ser
transmission shift
transmission buffe
At detection of ing or
falling edge oDA
SCL, SDA
External interrupt
(active edge selectable)
At timer X
At timlow
At erflow
underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
8
STP release timer underflow
9
10
ection of either rising or
g edge of CNTR0 input
External interrupt
(active edge selectable)
t detection of either rising or
falling edge of SCL or SDA
SCL, SDA
CNTR1
External interrupt
(active edge selectable)
11
FFE916
At detection of either rising or External interrupt
falling edge of CNTR1 input
(active edge selectable)
Serial I/O3
reception
At completion of serial I/O3 data Valid when serial I/O3 is selected
reception
12
13
Serial I/O2
FFE
16
FFE616
FFE416
At completion of serial I/O2 data Valid when serial I/O2 is selected
transmission or reception
Timer Z
INT2
At timer Z underflow
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
2
At completion of data transfer
I C
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT3 input
INT3
15
FFE316
FFE116
FFE216
FFE016
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT4 input
INT4
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR2 input
CNTR2
A/D converter
At completion of A/D conversion
16
17
FFDF16
FFDD16
FFDE16
FFDC16
Valid when serial I/O3 is selected
Non-maskable software interrupt
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Serial I/O3
transmission
BRK instruction
At BRK instruction execution
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-12
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
2.2.4 Interrupt operation
When an interrupt request is accepted, the contents of the following registers just before acceptance of the
interrupt requests are automatically pushed onto the stack area in the order of ꢀ, ꢀ and ꢀ.
ꢀHigh-order contents of program counter (PC
H
)
ꢀLow-order contents of program counter (PC
ꢀContents of processor status register (PS)
L
)
After the contents of the above registers are pushed onto the stack area, the accepted interrupt vector
address enters the program counter and consequently the interrupt processing routine is executed.
When the RTI instruction is executed at the end of the interrupt processing routine, the contents of the
above registers pushed onto the stack area are restored to the respective registers in the order of ꢀ, ꢀ
and ꢀ; and the microcomputer resumes the processing executed just before acceptance of the interrupts.
Figure 2.2.8 shows an interrupt operation diagram.
Executing routine
·······
Interrupt occurs
(Accepting interrupt request)
Contents m counter (high-order) are pushed onto stack
Suspended
operation
Coprogram counter (low-order) are pushed onto stack
Resume processing
ents of processor status register are pushed onto stack
·······
Interrupt
processing
routine
RTI instruction
Contents of processor status register are popped from stack
Contents of program counter (low-order) are popped from stack
Contents of program counter (high-order) are popped from stack
: Operation commanded by software
: Internal operation performed automatically
Fig. 2.2.8 Interrupt operation diagram
Rev.1.00 Jan 14, 2005
2-13
REJ09B0212-0100Z
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
(1) Processing upon acceptance of interrupt request
Upon acceptance of an interrupt request, the following operations are automatically performed.
ꢀThe processing being executed is stopped.
ꢀThe contents of the program counter and the processor status register are pushed onto the stack
area. Figure 2.2.9 shows the changes of the stack pointer and the program counter upon acceptance
of an interrupt request.
ꢀConcurrently with the push operation, the jump destination address (the beginning address of the
interrupt processing routine) of the occurring interrupt stored in the vector address is set in the
program counter, then the interrupt processing routine is executed.
ꢀAfter the interrupt processing routine is started, the corresponding interrupt request bit is automatically
cleared to “0”. The interrupt disable flag is set to “1” so that multiple interrupts are disabled.
Accordingly, for executing the interrupt processing routine, it is necessary to set the jump destination
address in the vector area corresponding to each interrupt.
area
Program counter
PC
PC
L
Program counter (low-order)
Program counter (high-order)
Interrupt disable flag = “
H
Stack pointer
(S)
(S)
S
pt
st is
cepted
Program counter
Stack area
PC
L
Vector address
Interrupt disable flag = “1”
(from Interrupt vecto
PC
H
(s) – 3
Processor status register
Program counter (low-order)
(S) Program counter (high-order)
Stack pointer
S
Fig. 2.2.9 Changes of stack pointer and program counter upon acceptance of interrupt request
Rev.1.00 Jan 14, 2005
2-14
REJ09B0212-0100Z
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
(2) Timing after acceptance of interrupt request
The interrupt processing routine begins with the machine cycle following the completion of the
instruction that is currently being executed.
Figure 2.2.10 shows the time up to execution of interrupt processing routine and Figure 2.2.11 shows
the timing chart after acceptance of interrupt request.
Interrupt request generated
Main routine
Start of interrupt processing
Waiting time for
post-processing
of pipeline
Stack push and
Interrupt processing routine
Vector fetch
ꢀ
0 to 16 cycles
2 cycles
5 cycles
7 to 23 cycles
(When f(XIN) = 8 MHz, 1.75 µs to 5.75 µs)
ꢀ When executing DIV instruction
Fig. 2.2.10 Time up to execution of interrupt proceoutine
Waiting time for pipeline
Push onto stack
Interrupt operation starts
post-processing
Vector fetch
φ
SYNC
R
S, SPS S-1, SPS S-2, SPS
Ass bus
Data bus
B
L
B
H
AL, AH
PC
Not used
PC
H
PC
L
PS
A
L
AH
: CPU operation code fetch cycle
SYNC
(This is an internal signal that cannot be observed from the external unit.)
BL, BH : Vector address of each interrupt
AL, AH : Jump destination address of each interrupt
: “0016” or “0116”
SPS
Fig. 2.2.11 Timing chart after acceptance of interrupt request
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-15
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
2.2.5 Interrupt control
The acceptance of all interrupts, excluding the BRK instruction interrupt, can be controlled by the interrupt
request bit, interrupt enable bit, and an interrupt disable flag, as described in detail below. Figure 2.2.12
shows an interrupt control diagram.
Interrupt request bit
Interrupt enable bit
rupt request
Interrupt disable flag
BRK instruction
Reset
Fig. 2.2.12 Interrupt control diagram
The interrupt request bit, interrupt enable bit and pt disable flag function independently and do not
affect each other. An interrupt is accepted whe following conditions are satisfied.
ꢀInterrupt request bit .......... “1”
ꢀInterrupt enable bit ........... “1”
ꢀInterrupt disable flag ........ “0”
Though the interrupt priority is deteby hardware, a variety of priority processing can be performed
by software using the above bits g. Tables 2.2.2 shows list of interrupt control bits according to the
interrupt source.
(1) Interrupt request
The interrupt rbits are allocated to the interrupt request register 1 (address 003C16) and
interrupt reqister 2 (address 003D16).
The occurf an interrupt request causes the corresponding interrupt request bit to be set to
“1”. The intept request bit is held in the “1” state until the interrupt is accepted. When the interrupt
is accepted, this bit is automatically cleared to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to “1”, by software.
(2) Interrupt enable bits
The interrupt enable bits are allocated to the interrupt control register 1 (address 003E16) and the
interrupt control register 2 (address 003F16).
The interrupt enable bits control the acceptance of the corresponding interrupt request.
When an interrupt enable bit is “0”, the corresponding interrupt request is disabled. If an interrupt
request occurs when this bit is “0”, the corresponding interrupt request bit is set to “1” but the
interrupt is not accepted. In this case, unless the interrupt request bit is set to “0” by software, the
interrupt request bit remains in the “1” state.
When an interrupt enable bit is “1”, the corresponding interrupt is enabled. If an interrupt request
occurs when this bit is “1”, the interrupt is accepted (when interrupt disable flag = “0”).
Each interrupt enable bit can be set to “0” or “1” by software.
Rev.1.00 Jan 14, 2005
2-16
REJ09B0212-0100Z
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
(3) Interrupt disable flag
The interrupt disable flag is allocated to bit 2 of the processor status register. The interrupt disable
flag controls the acceptance of interrupt request except BRK instruction.
When this flag is “1”, the acceptance of interrupt requests is disabled. When the flag is “0”, the
acceptance of interrupt requests is enabled. This flag is set to “1” with the SEI instruction and is set
to “0” with the CLI instruction.
When a main routine branches to an interrupt processing routine, this flag is automatically set to “1”,
so that multiple interrupts are disabled. To use multiple interrupts, set this flag to “0” with the CLI
instruction within the interrupt processing routine. Figure 2.2.13 shows an example of multiple interrupts.
Table 2.2.2 List of interrupt bits according to interrupt source
Interrupt enable bit
Interrupt request bit
Interrupt source
Address
Bit
b0
b1
b2
b3
b
7
b0
b1
b2
b3
b4
b5
b6
Bit
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
Add
16
3C16
003C16
003C16
003C16
003C16
003C16
003D16
003D16
003D16
003D16
003D16
003D16
003D16
INT
INT
0
1
/Timer Z
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003E16
003F16
003F
00
16
3F16
003F16
Serial I/O1 reception
Serial I/O1 transmission/SCL, SDA
Timer X
Timer Y
Timer 1
Timer 2
CNTR
CNTR
0
/SCL, SDA
/Serial I/O3 reception
Serial I/O2/Timer Z
1
INT
INT
INT
2
3
4
/I2C
/CNTR
2
A/D converter/Serial I/O3 transmission
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-17
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
Interrupt request
Nesting
Reset
Time
Main routine
I = 1
C1 = 0, C2 = 0
Interrupt
request 1
C1 = 1
I = 0
Interrupt 1
I = 1
Interrupt
request 2
Multiple interrupt
I = 0
Interrupt 2
I = 1
RTI
I = 0
RTI
I = 0
I : Interrupt disable flag
C1 : Interrupt enable bit of interrupt 1
C2 : Interrupt enable bit of interrupt 2
: Set automatically.
: Set by software.
Fig. 2.2.13 Example of multiple interrupts
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-18
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
2.2.6 INT interrupt
The INT interrupt requests is generated when the microcomputer detects a level change of each INT pin
(INT –INT ).
0
4
(1) Active edge selection
INT –INT can be selected from either a falling edge or rising edge detection as an active edge by
0
4
the interrupt edge selection register. In the “0” state, the falling edge of the corresponding pin is
detected. In the “1” state, the rising edge of the corresponding pin is detected.
(2) INT
0
, INT
2
, INT interrupt source selection
4
When using the following interrupt source, select which of the interrupt source by the interrupt source
selection register (address 003916). (Set these bits to “0” when using INT.)
•INT
•INT
•INT
0
4
2
or timer Z (bit 0)
or CNTR (bit 4)
or I2C (bit 5)
2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-19
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
2.2.7 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 003A16
•Timer XY mode register (address 002316
•Timer Z mode register (address 002A16
•I2C START/STOP condition control register (address 001616
)
)
)
)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active edh
bit) or the interrupt (source) select .
↓
NOP (One or more ins)
↓
Set the corresponding inequest bit to “0”
(no interrupt issued).
Set the corresinterrupt enable bit to “1”
(enabled).
Fig. 2.2.14 Sequence of changvant register
■ Reason
When setting twings, the interrupt request bit may be set to “1”.
•When settinnal interrupt active edge
Concernter: Interrupt edge selection register (address 003A16
Timer XY mode register (address 002316
Timer Z mode register (address 002A16
I2C START/STOP condition control register (address 001616
)
)
)
)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt source selection register (address 003916
)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-20
APPLICATION
2.2 Interrupt
3804 Group (Spec.H)
(2) Check of interrupt request bit
ꢀ When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0”, execute one or more instructions before executing
the BBC or BBS instruction.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 2.2.15 Sequence of check of interrupt request bit
ꢀ Reason
If the BBC or BBS instruction is executed immediately after rrupt request bit of an interrupt
request register is cleared to “0”, the value of the interruest bit before being cleared to “0”
is read.
Rev.1.00 Jan 14, 2005
2-21
REJ09B0212-0100Z
APPLICATION
2.3 Timer
3804 Group (Spec.H)
2.3 Timer
This paragraph explains the registers setting method and the notes relevant to the timers.
2.3.1 Memory map
Address
000E16 Timer 12, X count source selection register (T12XCSS)
000F16 Timer Y, Z count source selection register (TYZCSS)
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY
Timer Y (TY)
Timer Z low(TZL)
Timer Z rder (TZH)
Timede register (TZM)
rrupt source selection register (INTSEL)
0039
16
03D16
003E16
003F16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 2.3.1 Memory map of registers relevant to timers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-22
APPLICATION
2.3 Timer
3804 Group (Spec.H)
2.3.2 Relevant registers
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescaler X (PREX), Prescaler Y (PREY)
(addresses 002016, 002416, 002616)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
• Set a count value of each prescaler.
• The value set in this register is written to both
each prescaler and the corresponding
prescaler latch at the same time.
• When this register is read out, the count value
of the corresponding prescaler is read out.
Fig. 2.3.2 Structure of Prescaler 12, Prescaler X, Presc
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Time
(T002116)
Functions
At reset R W
1
2
3
4
5
6
7
1
0
0
0
0
0
0
0
• Set timer 1 count value.
• The value set in this register is written to both
the timer 1 and the timer 1 latch at the same
time.
• When the timer 1 is read out, the count value
of the timer 1 is read out.
Fig. 2.3.3 Structure of Timer 1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-23
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX), Timer Y (TY)
(addresses 002216, 002516, 002716)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
1
1
1
1
1
• Set each timer count value.
• The value set in this register is written to both
each timer and the corresponding timer latch
at the same time.
• When each timer is read out, the count value
of the corresponding timer is read out.
Fig. 2.3.4 Structure of Timer 2, Timer X, Timer Y
Timer Z low-order, Timer Z high-order
b7 b6 b5 b4 b3 b2 b1 b0
Timer Z low-order (TZL), Tiorder (TZH)
(addresses 002816, 0029
b
ctions
At reset R W
• Set eacunt value.
[At writ
1
1
1
1
1
1
1
1
0
1
2
• Deon the write control bit (bit 3 of
value set to this register is written to
mer and the corresponding timer latch
same time, or is written only to the latch.
ead]
The corresponding timer count value is read
out by reading this register.
• Read both registers in order of TZH and TZL
following.
• Write both registers in order of TZL and TZH
following.
6
7
Fig. 2.3.5 Structuf Timer Z (low-order, high-order)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-24
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register
(TM: address 002316)
b
0
Name
Functions
At reset R W
0
b1 b0
Timer X operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
0
1
2
measurement mode
Refer to Table 2.3.1
0 active edge
0
0
CNTR
switch bit
0: Count start
1: Count stop
3 Timer X count stop
bit
4
b5 b4
Timer Y operating
mode bits
0 0: Timer mode
0 1: Pulse output m
1 0: Event count
1 1: Pulse wid
0
5
measurde
Refer to 1
CNTR1 active edge
switch bit
0
0
6
7
0: Ct
1top
Timer Y count stop
bit
Fig. 2.3.6 Structure of Timer XY mode register
Table 2.3.1 CNTR0 /CNTR1 active edge swt function
Timer X /Timer Y operation
modes
CNTR0 / CNTR1 active edge switch bit
(bits 2, 6 of address 002316) contents
Timer mode
NTR0 / CNTR1 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR0 / CNTR1 interrupt request occurrence: Rising edge
; No influence to timer count
Pulse output mode
“0” Pulse output start: Beginning at “H” level
CNTR0 / CNTR1 interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR0 / CNTR1 interrupt request occurrence: Rising edge
“0” Timer X / Timer Y: Rising edge count
Event counter mode
CNTR0 / CNTR1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: Falling edge count
CNTR0 / CNTR1 interrupt request occurrence: Rising edge
“0” Timer X / Timer Y: “H” level width measurement
CNTR0 / CNTR1 interrupt request occurrence: Falling edge
“1” Timer X / Timer Y: “L” level width measurement
CNTR0 / CNTR1 interrupt request occurrence: Rising edge
Pulse width measurement mode
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-25
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Timer Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Z mode register
(TZM: address 002A16
)
b
0
Name
Timer Z operating
mode bits
Functions
At reset R W
0
b2b1b0
0 0 0: Timer/Event counter mode
0 0 1: Pulse output mode
0 1 0: Pulse period
measurement mode
0 1 1: Pulse width
measurement mode
1 0 0: Programmable waveform
generating mode
1
2
0
1 0 1: Programmable one-shot
generating mode
1 1 0: Not available
1 1 1: Not available
0: Writing data to bot
and timer simult
1: Writing data ch
Timer Z write control
bit
0
3
Output level latch
0: “L” output
1: “H” out
0
0
0
0
4
5
6
CNTR active edge
2
Refer t.3.2.
switch bit
0tart
t stop
Timer Z count stop
bit
Timer/Event counmer mode
mode switch biEvent counter mode
7
Note: When selecting the cept the timer/event counter mode, set “0” to this bit.
Fig. 2.3.7 Structure of Timer Z mode
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-26
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Table 2.3.2 CNTR2 active edge switch bit function
Timer Z
CNTR2 active edge switch bit
(bit 5 of address 002A16) contents
operation modes
Timer mode
“0” CNTR2 interrupt request occurrence: Falling edge
; No influence to timer count
“1” CNTR2 interrupt request occurrence: Rising edge
; No influence to timer count
Event counter mode
“0” Timer Z: Rising edge count
CNTR2 interrupt request occurrence: Falling edge
“1” Timer Z: Falling edge count
CNTR2 interrupt request occurrence: Rising edge
“0” Pulse output start: Beginning at “H” level
CNTR2 interrupt request occurrence: Fale
“1” Pulse output start: Beginning at “L” l
CNTR2 interrupt request occurreng edge
“0” Timer Z : Term from one falling eext falling edge measurement
CNTR2 interrupt request oc: Falling edge
“1” Timer Z : Term from one rge to next rising edge measurement
CNTR2 interrupt requrrence: Rising edge
“0” Timer Z: “H” level easurement
Pulse output mode
Pulse period measurement mode
Pulse width measurement mode
CNTR2 interrupt occurrence: Falling edge
“1” Timer Z: “L” idth measurement
CNTR2 inrequest occurrence: Rising edge
“0” Timer se output start from “L” level, and “H” level one-shot
pulse is output.
Programmable one-shot generating
mode
interrupt request occurrence: Falling edge
er Z : Pulse output start from “H” level, and “L” level one-shot
pulse is output.
CNTR2 interrupt request occurrence: Rising edge
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-27
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Timer 12, X count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12, X count source selection register
(T12XCSS: address 000E16
)
b
0
Name
Functions
At reset R W
1
b3b2b1b0
Timer 12 count
source selection
bits
0 0 0 0: f(XIN)/2 or f(XCIN)/2
0 0 0 1: f(XIN)/4 or f(XCIN)/4
0 0 1 0: f(XIN)/8 or f(XCIN)/8
0 0 1 1: f(XIN)/16 or f(XCIN)/16
0 1 0 0: f(XIN)/32 or f(XCIN)/32
0 1 0 1: f(XIN)/64 or f(XCIN)/64
0 1 1 0: f(XIN)/128 or f(XCIN)/128
0 1 1 1: f(XIN)/256 or f(XCIN)/256
1 0 0 0: f(XIN)/512 or f(XCIN)/512
1 0 0 1: f(XIN)/1024 or f(XCIN)/1024
1010 to 1111: Not available
1
2
3
4
1
0
0
1
b7b6b5b4
Timer X count
source selection
bits
0 0 0 0: f(XIN)/2 or f(XCIN)/2
0 0 0 1: f(XIN)/4 or f(XCIN)/
0 0 1 0: f(XIN)/8 or f(XC
0 0 1 1: f(XIN)/16 or f
0 1 0 0: f(XIN)/32 o
0 1 0 1: f(XIN)/6/64
0 1 1 0: f(XIN)N)/128
0 1 1 1: f(XXCIN)/256
1 0 0 0: r f(XCIN)/512
1 0 0 4 or f(XCIN)/1024
5
6
7
0
0
1 0
11: Not available
Fig. 2.3.8 Structure of Timer 12, X count source ion register
Timer Y, Z count source selecgister
b7 b6 b5 b4 b3 b2 b1 b0
Timet source selection register
(Tdress 000F16
)
Name
Functions
At reset R W
1
b3b2b1b0
Timer Y count
source selection
bits
0 0 0 0: f(XIN)/2 or f(XCIN)/2
0 0 0 1: f(XIN)/4 or f(XCIN)/4
0 0 1 0: f(XIN)/8 or f(XCIN)/8
0 0 1 1: f(XIN)/16 or f(XCIN)/16
0 1 0 0: f(XIN)/32 or f(XCIN)/32
0 1 0 1: f(XIN)/64 or f(XCIN)/64
0 1 1 0: f(XIN)/128 or f(XCIN)/128
0 1 1 1: f(XIN)/256 or f(XCIN)/256
1 0 0 0: f(XIN)/512 or f(XCIN)/512
1 0 0 1: f(XIN)/1024 or f(XCIN)/1024
1
2
3
1
0
0
1 0 1 0: f(XCIN
)
1011 to 1111: Not available
b7b6b5b4
Timer Z count
source selection
bits
4
5
6
7
1
1
0
0
0 0 0 0: f(XIN)/2 or f(XCIN)/2
0 0 0 1: f(XIN)/4 or f(XCIN)/4
0 0 1 0: f(XIN)/8 or f(XCIN)/8
0 0 1 1: f(XIN)/16 or f(XCIN)/16
0 1 0 0: f(XIN)/32 or f(XCIN)/32
0 1 0 1: f(XIN)/64 or f(XCIN)/64
0 1 1 0: f(XIN)/128 or f(XCIN)/128
0 1 1 1: f(XIN)/256 or f(XCIN)/256
1 0 0 0: f(XIN)/512 or f(XCIN)/512
1 0 0 1: f(XIN)/1024 or f(XCIN)/1024
1 0 1 0: f(XCIN
)
1011 to 1111: Not available
Fig. 2.3.9 Structure of Timer Y, Z count source selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-28
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register
(INTSEL: address 003916
)
b
0
Name
Functions
interrupt
At reset R W
0
INT
0
/Timer Z
0: INT
0
interrupt source
selection bit (*1)
1: Timer Z interrupt
0: Serial I/O2 interrupt
1: Timer Z interrupt
0
0
Serial I/O2/Timer Z
interrupt source
selection bit (*1)
1
2
Serial I/O1 transmit/
SCL, SDA interrupt
source selection bit
(*2)
0: Serial I/O1 transmit
interrupt
1: SCL, SDA interrupt
0
0
3
4
0: CNTR
1: SCL, SDA interrup
0
interrupt
CNTR0/SCL, SDA
interrupt source
selection bit (*2)
0: INT
1: CNTR
4
interrup
in
INT /CNTR2
4
2
interrupt source
selection bit
/I2C interrupt
0
0
0: INT
5 INT
source selection bit
2
1: I2t
0interrupt
l I/O3 receive
errupt
CNTR /Serial I/O3
receive interrupt
1
6
source selection
0
7 AD converter/
I/O3 transm
A/D converter interrupt
1: Serial I/O3 transmit
interrupt
interrupt
selecti
*1: Do 1 to these bits simultaneously.
*2: rite 1 to these bits simultaneously.
Fig. 2.3.10 Structure of Interruce selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-29
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 003C16
)
b
0
Name
Functions
At reset R W
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
INT
0
/Timer Z
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2 Serial I/O1 receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
3 Serial I/O1
transmit/SCL, SDA
interrupt request bit
ꢀ
ꢀ
ꢀ
ꢀ
0
0
4 Timer X interrupt
request bit
0 : No interrupt request issu
1 : Interrupt request is
5
0 : No interrupt reque
1 : Interrupt requd
Timer Y interrupt
request bit
6
7
Timer 1 interrupt
request bit
0 : No interrussued
1 : Interrut issued
Timer 2 interrupt
request bit
0 : No quest issued
1 : Iequest issued
0
ꢀ: 0 can be set by softwacannot be set.
Fig. 2.3.11 Structure of Interrupt request registe
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Intest register 2
ddress 003D16
)
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
ꢀ
0
CNTR
0/SCL, SDA
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
0
1 CNTR
/Serial I/O3
1
receive interrupt
request bit
Serial I/O2/Timer Z 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
2
3
4
INT
request bit
INT interrupt
request bit
2
/I2C interrupt
0 : No interrupt request issued
1 : Interrupt request issued
3
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 INT
/CNTR
4
2
interrupt request bit
AD converter/Serial
I/O3 transmit
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are 0 .
ꢀ: 0 can be set by software, but 1 cannot be set.
Fig. 2.3.12 Structure of Interrupt request register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-30
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 003E16)
b
0
Name
Functions
At reset R W
0
0
0
0
INT
0
/Timer Z
interrupt enable bit
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1 INT
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 Serial I/O1 receive
interrupt enable bit
Serial I/O1
3
0 : Interrupt disabled
transmit/SCL, SDA 1 : Interrupt enabled
interrupt enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
4
5
6
7
0
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabl
Timer 1 interrupt
enable bit
0 : Interrupt di
1 : Interrupt
Timer 2 interrupt
enable bit
0 : Interred
1 : Intbled
Fig. 2.3.13 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Inteol register 2
(dress 003F16)
0
Name
/SCL, SDA
interrupt enable bit
CNTR / Serial I/O3
receive interrupt
enable bit
Functions
At reset R W
0
CNTR
0
0 : Interrupt disabled
1 : Interrupt enabled
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2/ Timer Z
interrupt enable bit
0
0
0
0
0
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
INT
enable bit
INT interrupt
enable bit
2
/I2C interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
3
INT /CNTR2
4
0 : Interrupt disabled
1 : Interrupt enabled
interrupt enable bit
AD converter/Serial
I/O3 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
7
Fix this bit to “0”.
0
Fig. 2.3.14 Structure of Interrupt control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-31
APPLICATION
2.3 Timer
3804 Group (Spec.H)
2.3.3 Timer application examples
(1) Basic functions and uses
[Function 1] Control of Event interval (Timer X, Timer Y, Timer Z, Timer 1, Timer 2)
When a certain time, by setting a count value to each timer, has passed, the timer interrupt request
occurs.
<Use>
•Generation of an output signal timing
•Generation of a wait time
[Function 2] Control of Cyclic operation (Timer X, Timer Y, Timer Z, Timer 1, Timer 2)
The value of the timer latch is automatically written to the corresponding timer each time the timer
underflows, and each timer interrupt request occurs in cycles.
<Use>
•Generation of cyclic interrupts
•Clock function (measurement of 250 ms); see Application examp
•Control of a main routine cycle
[Function 3] Output of Rectangular waveform (Timer X, TiTimer Z)
The output level of the CNTR pin is inverted each time tunderflows (in the pulse output
mode).
<Use>
•Piezoelectric buzzer output; see Application e2
•Generation of the remote control carrier ws
[Function 4] Count of External pulses (T, Timer Y, Timer Z)
External pulses input to the CNTR pin nted as the timer count source (in the event counter
mode).
<Use>
•Frequency measurement; lication example 3
•Division of external puls
•Generation of interruto a cycle using external pulses as the count source; count of a
reel pulse
[Function 5] Meant of External pulse width (Timer X, Timer Y, Timer Z)
The “H” or “Lwidth of external pulses input to CNTR pin is measured (in the pulse width
measureme).
<Use>
•Measuent of external pulse frequency (measurement of pulse width of FG pulseꢀ for a
motor); see Application example 4
•Measurement of external pulse duty (when the frequency is fixed)
FG pulseꢀ: Pulse used for detecting the motor speed to control the motor speed.
[Function 6] Output of Arbitrary waveform (Timer Z)
The value which is set to the output level latch is output from the CNTR pin each time the timer
underflows. (programmable waveform generating mode)
[Function 7] One-shot pulse output by external trigger (Timer Z)
The value of timer latch is set to timer by trigger signal which is input from the INT pin, and timer
is counted down. When trigger signal is input, “H” or “L” is output from the CNTR pin at the same
time, and “L” or “H” is output by underflow of timer. (programmable one-shot generating mode)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-32
APPLICATION
2.3 Timer
3804 Group (Spec.H)
(2) Timer application example 1: Clock function (measurement of 250 ms)
Outline: The input clock is divided by the timer so that the clock can count up at 250 ms intervals.
Specifications: •The clock f(XIN) = 4.19 MHz (222 Hz) is divided by the timer.
•The clock is counted up in the process routine of the timer X interrupt which occurs
at 250 ms intervals.
Figure 2.3.15 shows the timers connection and setting of division ratios; Figure 2.3.16 shows the
relevant registers setting; Figure 2.3.17 shows the control procedure.
Dividing by 4 with software
Timer X count source
selection bit
Timer X interrupt
request bit
Prescaler X
1/256
Timer X
1/256
f(XIN) = 4.19 MHz
1/16
0 or 1
1/4
1 second
250 ms
0 : No intert issued
1 : Interrissued
Fig. 2.3.15 Timers connection and setting of division ratios
Timer 12, X count source selection regss 000E16
)
b7
b0
T12XCSS
0
0
1 1
ount source : f(XIN)/16
Timer XY mode rdress 002316
)
b7
TM
Timer X operating mode: Timer mode
Timer X count: Stop
Clear to “0” when starting count.
escaler X (address 002416
)
b7
b0
X
256 – 1
Set “division ratio – 1”
Timer X (address 002516
)
b7
b0
TX
256 – 1
Interrupt control register 1 (address 003E16
)
b7
b0
ICON1
1
Timer X interrupt: Enabled
Interrupt request register 1 (address 003C16
)
b7
b0
IREQ1
0
Timer X interrupt request
(becomes “1” at 250 ms intervals)
Fig. 2.3.16 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-33
APPLICATION
2.3 Timer
3804 Group (Spec.H)
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
•All interrupts disabled
Initialization
SEI
TM
IREQ1
ICON1
XXXX1X00
2
•Timer X : Timer mode
•Clear Timer X interrupt request bit
•Timer X interrupt enabled
(address 002316
(address 003C16), bit4
(address 003E16), bit4
)
0
1
•Timer X count source : f(XIN)/16
•Set “division ratio – 1” to Prescaler X and Timer X
0011XXXX
2
(address 000E16
)
T12XCSS
PREX
TX
256 – 1
256 – 1
(address 002416
(address 002516
)
)
(address 002316),
bit3
TM
CLI
0
•Timer X count start
•Interrupts enabled
Main processing
<Procedure for completion of clock set>
•Reset Timecount from 0 second after completion
(Note 1)
of clock s
PREX (address 002416
TX (address 002516
IREQ1 (address 003C16), bit4
)
)
256 – 1
256 – 1
0
Note procedure for completion of clock set only
completing clock set.
Timer X interrupt process
CLT (Note
CLD (No
Push stack
Note 2: When using Index X mode flag (T)
Note 3: When using Decimal mode flag (D)
•Push registers used in interrupt process routine
Y
•Judge whether clock stops
Clock stop ?
N
Clock count up (1/4 second to year)
•Clock count up
•Pop registers pushed to stack
Pop registers
RTI
Fig. 2.3.17 Control procedure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-34
APPLICATION
2.3 Timer
3804 Group (Spec.H)
(3) Timer application example 2: Piezoelectric buzzer output
Outline: The rectangular waveform output function of the timer is applied for a piezoelectric buzzer
output.
Specifications: •The rectangular waveform, dividing the clock f(XIN) = 8 MHz into about 2 kHz (2049
Hz), is output from the P4
7
/CNTR
2
pin.
•The level of the P4
7
/CNTR
2
pin is fixed to “H” while a piezoelectric buzzer output
stops.
Figure 2.3.18 shows a peripheral circuit example, and Figure 2.3.19 shows the timers connection and
setting of division ratios. Figure 2.3.20 shows the relevant registers setting, and Figure 2.3.21 shows
the control procedure.
The “H” level is output while a piezoelectric buzzer output stop
CNTR2 output
R2
PiPiPi.....
244 µs 244 µs
Set a division ratio so that th
3804 Group (Spec. H)
underflow output period of Z
can be 244 µs.
Fig. 2.3.18 Peripheral circuit example
Timer Z count source
selection bit
Timer Z
1/122
= 8 MHz
1/16
CNTR
2
Fig. 2.3.19 Timers onnection and setting of division ratios
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-35
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Timer Y, Z count source selection register (address 000F16
)
b7
b0
0 1
1
TYZCSS
0
Timer Z count source: f(XIN)/16
Timer Z mode register (address 002A16
)
b7
b0
1
1
0
0 0
TM
0
Timer Z operating mode : Pulse output
Write value in latch and timer at the
CNTR active edge switch : Outpat “H” level
2
Timer Z count : Stop
Clear to “0” when starting c
Timer Z high-order (address 002916
)
b7
b0
TZH
TZL
0
“division ratio – 1”
Timer Z low-order (address 00281
b7
b0
122–1
Port P4 directio(address 000916
)
b7
0
P4D
1
P47
/CNTR
2
: Output mode
rt P4 (address 000816
)
b7
b0
1
P4
“H” output at stopping buzzer output
Fig. 2.3.20 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-36
APPLICATION
2.3 Timer
3804 Group (Spec.H)
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
P4 (address 000816), bit7
P4D (address 000916
1
)
1XXXXXXX2
•Timer Z interrupt disabled
•Timer Z count stopped; Buzzer output stopped
•Timer Z: Pulse output mode
ICON1 (address 003E16), bit0
0
X10X0001
2
TZM
(address 002A16
)
•Timer Z count source: f(XIN)/16
•Set (division ratio – 1) to timer Z
0011XXXX
122–1
0
2
TYZCSS(address 000F16
)
TZL
TZH
(address 002816
(address 002916
)
)
Main processing
•Processing bst, generated during main
processingunit
Output unit
Yes
Buzzer request ?
No
(address 002A16), bit6
1
TZM
0
(address 002A16), bit6
Stop of piezoelectric buzzer
output
Start of piezoelectric buzzer output
Fig. 2.3.21 Control procedu
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-37
APPLICATION
2.3 Timer
3804 Group (Spec.H)
(4) Timer application example 3: Frequency measurement
Outline: The following two values are compared to judge whether the frequency is within a valid
range.
•A value by counting pulses input to P5
•A reference value
5
/CNTR
1
pin with the timer.
Specifications: •The pulse is input to the P5
5
/CNTR
1
pin and counted by the timer Y.
•The clock f(XIN) = 8 MHz is dividing by the timer 1, and the interrupt request occurs
at about 2 ms intervals.
•A count value is read out at about 2 ms intervals, the timer 1 interrupt interval.
When the count value is 28 to 40, it is judged that the input pulse is valid.
•Because the timer is a down-counter, the count value is compared with 227 to 215
(Note).
Note: 227 to 215 = {255 (initial value of counter) – 28} to {255 – 40}; 28 to eans the number
of valid count value.
Figure 2.3.22 shows the judgment method of valid/invalid of input pFigure 2.3.23 shows the
relevant registers setting; Figure 2.3.24 shows the control proce
Input pulse
• • • • •
• • • • •
• • • • •
71.4 µs or more
71.4 µs
50 µs
50 µs or less
(less than 14 kHz)
(14 kH
(20 kHz)
(20 kHz or more)
Valid
Invalid
Invalid
2 ms
71.4 µs
2 ms
50 µs
= ts
= 40 counts
Fig. 2.3.22 Judgment methalid/invalid of input pulses
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-38
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Timer XY mode register (address 002316
)
b7
b0
TM
1
1 1
0
Timer Y operating mode: Event counter mode
CNTR1 active edge switch: Falling edge count
Timer Y count: Stop
Clear to “0” when starting count
Timer 12, X count source selection register (address 000E16
)
b7
b0
T12XCSS
0
1 0
0
f(XIN)/32: select
Prescaler 12 (address 002016
)
b7
b0
PRE12
64 – 1
Timer 1 (address 002116
)
b7
b0
T1
8 – 1
Set tio – 1”
Prescaler Y (address 002616
)
b7
b0
PREY
1 – 1
Timer Y (addr6
)
b7
0
Set 255 just before counting pulses
(After a certain time has passed, the number of input
pulses is decreased from this value.)
TY
control register 1 (address 003E16
)
b0
ICO
1
0
Timer Y interrupt: Disabled
Timer 1 interrupt: Enabled
Interrupt request register 1 (address 003C16
)
b7
b0
IREQ1
0
Judgment of Timer Y interrupt request bit
( “1” of this bit when reading the count value indicates the 256 or more
pulses input in the condition of Timer Y = 255)
Fig. 2.3.23 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-39
APPLICATION
2.3 Timer
3804 Group (Spec.H)
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrary.
•All interrupts disabled
Initialization
SEI
1110XXXX
XXXX0100
64 – 1
8 – 1
1 – 1
2
2
•Timer Y operating mode : Event counter mode
(Count a falling edge of pulses input from CNTR1 pin.)
(address 002316
)
)
)
)
)
)
)
TM
(address 000E16
T12XCSS
PRE12
T1
(address 002016
(address 002116
(address 002616
(address 002716
•Set division ratio so that Timer 1 interrupt will occur at
2 ms intervals.
PREY
TY
IREQ1
ICON1
255
(address 003C16
•Timer 1, Y interrupt request bit cleared
•Timer 1 interrupt: Enabled
X00XXXXX
2
(address 003E16), bit6
1
0
•Timer Y count start
•Interrupts enabled
(address 002316), bit7
TM
CLI
Timer 1 interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Note sing Index X mode flag (T)
Nn using Decimal mode flag (D)
sters used in interrupt process routine
1
IREQ1(address 003C16), bit5 ?
0
•Process as out of range when the count value is 256 or more
•Read the count value
•Store the count value into Accumulator (A)
TY (a716
)
(A)
In range
•Compare the read value with
reference value
2228
•Store the comparison result to
flag Fpulse
Out of range
0
lse
1
Fpulse
TY
(address 002716
)
•Initialize the counter value
256 – 1
IREQ1 (address 003C16), bit5
•Clear Timer Y interrupt request bit
•Pop registers pushed to stack
0
Process judgment result
Pop registers
RTI
Fig. 2.3.24 Control procedure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-40
APPLICATION
2.3 Timer
3804 Group (Spec.H)
(5) Timer application example 4: Measurement of FG pulse width for motor
Outline: The timer Z counts the “H” level width of the pulses input to the P4
7
/CNTR
2
pin. An underflow
is detected by the timer Z interrupt and an end of the input pulse “H” level is detected by
the P4 /CNTR interrupt.
7
2
Specifications: •The timer Z counts the “H” level width of the FG pulse input to the P4
7
/CNTR pin.
2
<Example>
When the clock frequency is 8 MHz, the count source is 2 µs, which is obtained by dividing the
clock frequency by 16. Measurement can be made up to 131.072 ms in the range of FFFF16 to
000016
.
Figure 2.3.25 shows the timers connection and setting of division ratio; Figure 2.3.26 shows the
relevant registers setting; Figure 2.3.27 and Figure 2.3.28 show the control procedure.
Timer Z count source
selection bit
Timer Z inte
request b
Timer Z
1/65536
f(XIN) = 8 MHz
1/16
072 ms
terrupt request issued
errupt request issued
Fig. 2.3.25 Timers connection and setting oon ratios
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-41
APPLICATION
2.3 Timer
3804 Group (Spec.H)
Port P4 direction register (address 000916
)
b7
b0
0
P4D
P47
/CNTR
2: Input mode
Timer Z mode register (address 002A16
)
b7
b0
TZM
1
0
0 0 1
1
Timer Z operating mode: Pulse width measurement mode
Write in latch and timer at the same time
CNTR2 active edge switch: “H” level width measurement
Timer Z count: Stop
Clear to “0” when starting count
Timer Y, Z count source selection register (address 000F16
)
b7
b0
TYZCSS
0
0
1 1
Timer Z count source: f(XIN)/16
Timer Z high-order (address 002916
)
b7
b0
TZH
TZL
FF16
Set initial value “FFstarting pulse
width measuremot setting the
initial value, cfrom the timer
value befornt start.)
Timer Z low-order (address 002816
)
b7
b0
FF16
Interrupt source selection register (add6
)
b7
b0
INTSEL
1
1
Z interrupt source: Timer Z interrupt
TR2 interrupt source: CNTR2 interrupt
Interrupt request ddress 003C16
)
b7
IREQ1
Timer Z interrupt request
(Set to “1” automatically when Timer Z underflows)
control register 1 (address 003E16
)
b0
1
IC
IREQ2
Timer Z interrupt: Enabled
Interrupt request register 2 (address 003D16
)
b7
b0
0
CNTR
2
interrupt request
(Set to “1” automatically when “H” level input came to the end)
Interrupt control register 2 (address 003F16
)
b7
b0
ICON2
1
CNTR
2
interrupt: Enabled
Fig. 2.3.26 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-42
APPLICATION
2.3 Timer
3804 Group (Spec.H)
RESET
● x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
•All interrupts disabled
•Set P4 /CNTR pin to input mode
•Timer Z: Pulse width measurement mode
(Measure “H” level of pulses input from CNTR
•Set timer Z initial value
SEI
0XXXXXXX
2
(address 000916
(address 002A16
(address 000F16
)
)
)
7
2
P4D
TZM
TYZCSS
TZL
TZH
INTSEL
IREQ1
ICON1
IREQ2
ICON2
X10X0011
2
0011XXXX
2
2 pin.)
(address 002816
(address 002916
(address 003916
)
)
)
FF16
FF16
XXX1XXX1
2
(address 003C16), bit0
(address 003E16), bit0
(address 003D16), bit5
(address 003F16), bit5
0
1
0
1
•Timer Z interrupt enabled
•CNTR2 interrupt enabled
(address 002A16), bit6
•Timer Z count start
•Interrupts enabled
TZM
CLI
0
Timer Z interrupt process routine
CLT (Note 1)
CLD (Note 2)
Push registers to stack
Nn using Index X mode flag (T)
hen using Decimal mode flag (D)
egisters used in interrupt process routine
Error processing
Pop register
•Pop registers pushed to stack
Note: Tiupt also occurs owing to factors other than measurement level.
ut =“L” in this application)
it by software as error processing is performed for measurement level as necessary.
R input level can be checked by reading the contents of sharing port P4 register.)
2
7
Fig. 2.3.27 Control procedure (1)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-43
APPLICATION
2.3 Timer
3804 Group (Spec.H)
CNTR
2
interrupt process routine (Note 1)
Notes 2: When using Index X mode flag (T)
3: When using Decimal mode flag (D)
CLT (Note 2)
CLD (Note 3)
Push registers to stack
•Pushing registers used in interrupt process routine
•Count value read and storing it to RAM
•Popping registers pushed to stack
(A)
TZH
(A)
TZL
(A)
Measurement result (high-order 8 bits)
(A)
Measurement result (low-order 8 bits)
Pop registers
RTI
Note 1: The first value becomes invalid depending on start timing of Timer Z count shown
by the following figure.
Process it by software as necessary.
[ Example 1] • Start Timer Z count when CNTR
2
input level is “L”.
(CNTR
2
input level can be checked by reading the contents of rt P4
7
register.)
FFFF16
T1
T2
000016
T1 value
T2 value: Valid
CNTR
CNTR
2
Count start of
Timer Z
CNTR
2
interrupt
2
interrupt
[ Example 2] • Start Timwhen CNTR
Invalist CNTR
2
input level is “H”.
2
interrupt after start of Timer Z count.
FFF
T1
T2
000016
T1 value: Invalid
T2 value: Valid
CNTR
2
Count start of
CNTR
2
interrupt
CNTR2 interrupt
Timer z
Fig. 2.3.28 Control procedure (2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-44
APPLICATION
2.3 Timer
3804 Group (Spec.H)
2.3.4 Notes on timer
Notes on 8-bit timer (timer 1, 2, X, Y)
ꢀ If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
ꢀ When switching the count source by the timer 12, X and Y count source selection bits, the value
of timer count is altered in unconsiderable amount owing to generating of thin pulses in the count
input signals.
Therefore, select the timer count source before set the value to the prescaler and the timer.
ꢀ Set the double-function port of the CNTR
0
/CNTR
1
pin and port P5
4
/P5
5
to output in the pulse output
mode.
ꢀ Set the double-function port of CNTR
0
/CNTR pin and port P5
1
4
/P5
5
to input in the event counter
mode and the pulse width measurement mode.
Notes on 16-bit timer (timer Z)
(1) Pulse output mode
ꢀ Set the double-function port of the CNTR
2
pin and port P4
pin and po
7
to
o input.
(2) Pulse period measurement mode
ꢀ Set the double-function port of the CNTR
2
ꢀ A read-out of timer value is impossible in this mode. er can be written to only during timer
stop (no measurement of pulse period).
ꢀ Since the timer latch in this mode is specialthe read-out of measured values, do not
perform any write operation during measur
ꢀ “FFFF16” is set to the timer when the timerflows or when the valid edge of measurement
start/completion is detected. Conseque timer value at start of pulse period measurement
depends on the timer value just beasurement start.
(3) Pulse width measurement mode
ꢀ Set the double-function port oNTR
2
pin and port P4 to input.
7
ꢀ A read-out of timer value is ible in this mode. The timer can be written to only during timer
stop (no measurement operiod).
ꢀ Since the timer latch mode is specialized for the read-out of measured values, do not
perform any write n during measurement.
ꢀ “FFFF16” is set tmer when the timer underflows or when the valid edge of measurement
start/completitected. Consequently, the timer value at start of pulse width measurement
depends omer value just before measurement start.
(4) Programmwaveform generating mode
ꢀ Set the double-function port of the CNTR
2
pin and port P4 to output.
7
(5) Programmable one-shot generating mode
ꢀ Set the double-function port of CNTR
2
pin and port P4
7
to output, and of INT
1
pin and port P4 to
2
input in this mode.
ꢀ This mode cannot be used in low-speed mode.
ꢀ If the value of the CNTR active edge switch bit is changed during one-shot generating enabled
or generating one-shot pulse, then the output level from CNTR pin changes.
2
2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-45
APPLICATION
2.3 Timer
3804 Group (Spec.H)
(6) All modes
ꢀTimer Z write control
Which write control can be selected by the timer Z write control bit (bit 3) of the timer Z mode
register (address 002A16), writing data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected, the value is set to the timer latch
by writing data to the address of timer Z and the timer is updated at next underflow. After reset
release, the operation “writing data to both the latch and the timer at the same time” is selected,
and the value is set to both the latch and the timer at the same time by writing data to the address
of timer Z.
In the case of writing data only to the latch, if writing data to the latch and an underflow are
performed almost at the same time, the timer value may become undefined.
ꢀTimer Z read control
A read-out of timer value is impossible in pulse period measurement mode and width measurement
mode. In the other modes, a read-out of timer value is possible regardcount operating or
stopped.
However, a read-out of timer latch value is impossible.
ꢀSwitch of interrupt active edge of CNTR
2
and INT
1
Each interrupt active edge depends on setting of the CNTR
active edge selection bit.
edge switch bit and the INT
1
ꢀSwitch of count source
When switching the count source by the timer Z corce selection bits, the value of timer
count is altered in inconsiderable amount owing rating of thin pulses on the count input
signals.
Therefore, select the timer count source beting the value to the prescaler and the timer.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-46
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4 Serial interface
This paragraph explains the registers setting method and the notes relevant to Serial I/O.
2.4.1 Memory map
Address
001816 Transmit/Receive buffer register 1 (TB1/RB1)
001916 Serial I/O1 status register (SIO1STS)
001A16 Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
Baud rate generator 1 (BRG1)
001B16
001C16
001D16
Serial I/O2 control register (SIO2C
Serial I/O2 register (SIO2)
001F16
Baud rate generatRG3)
002F16
003016
003116
003216
003316
Transmit/Receive egister 3 (TB3/RB3)
Serial I/O3 register (SIO3STS)
Serial Introl register (SIO3CON)
UAntrol register (UART3CON)
errupt source selection register (INTSEL)
0039
C16
003D16
003E16
003F16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Fig. 2.4.1 Memory map of registers relevant to Serial I/O
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-47
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.2 Relevant registers
Transmit/Receive buffer register 1, Transmit/Receive buffer register 3
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register 1 (TB1/RB1: address 001816)
Transmit/Receive buffer register 3 (TB3/RB3: address 003016)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefind
Und
U
d
fined
The transmission data is written to or the
receive data is read out from this buffer register.
• At write: A data is written to the transmit buffer
register.
• At read: The contents of the receive buffer
register are read out.
Note: The contents of transmit buffer regiot be read out.
The data cannot be written to the uffer register.
Fig. 2.4.2 Structure of Transmit/Receive buffer register 1 ansmit/Receive buffer register 3
Serial I/O1 status register, Serial I/Os register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 stat(SIO1STS: address 001916
Serial I/O3 ser (SIO3STS: address 003116
)
)
b
0
e
t buffer
flag (TBE)
Functions
0: Buffer full
1: Buffer empty
At reset R W
ꢀ
ꢀ
ꢀ
0
0
0
0: Buffer empty
1: Buffer full
eceive buffer full
flag (RBF)
2 Transmit shift register
shift completion flag
(TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag
3
0: No error
1: Overrun error
0
0
0
0
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
(OE)
4
Parity error flag
(PE)
0: No error
1: Parity error
Framing error flag
(FE)
0: No error
1: Framing error
5
6
7
Summing error flag
(SE)
0: (OE) U (PE) U (FE) = 0
1: (OE) U (PE) U (FE) = 1
Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “1”.
Fig. 2.4.3 Structure of Serial I/O1 status register and Serial I/O3 status register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-48
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIO1CON: address 001A16
)
b
Name
Functions
At reset R W
0 BRG count source
selection bit (CSS)
0
0: f(XIN)
1: f(XIN)/4
Serial I/O1
1
0
When clock synchronous
serial I/O is selected,
0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
synchronous clock
selection bit (SCS)
0
0: I/O port (P47)
1: SRDY1 output pin
S
RDY1 output
2
3
enable bit (SRDY)
0: Transmit buffer
1: Transmit shift
completion
Transmit interrupt
source selection
bit (TIC)
0: Transmd
1: Tranled
Transmit enable bit
(TE)
0
0
0
4
5
6
Receive enable bit 0: Rsabled
(RE)
1enabled
T
Serial I/O1 mode
ock synchronous
serial I/O
selection bit (SI
0: Serial I/O1 disabled
Serial I/O1
bit (SIO
0
7
(P4
1: Serial I/O1 enabled
(P4 to P4 : Serial I/O pins)
4
to P4 : normal I/O pins)
7
4
7
Fig. 2.4.4 Structure of Serial I/Ool register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-49
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Serial I/O3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O3 control register
(SIO3CON: address 003216)
b
Name
Functions
At reset R W
0 BRG count source
selection bit (CSS)
0
0: f(XIN)
1: f(XIN)/4
Serial I/O3
1
0
When clock synchronous
serial I/O is selected,
0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
synchronous clock
selection bit (SCS)
0
0
0: I/O port (P37)
1: SRDY3 output pin
SRDY3 output
enable bit (SRDY)
2
3
0: Transmit buffe
1: Transmit shon
completio
Transmit interrupt
source selection
bit (TIC)
Transmit enable bit 0: Tranled
0
0
0
4
5
6
(TE)
1: Trabled
Receive enable bit
(RE)
0: disabled
ve enabled
RT
Serial I/O3 mode
Clock synchronous
serial I/O
selection bit (S
0: Serial I/O3 disabled
(P34 to P37: normal I/O pins)
1: Serial I/O3 enabled
(P34 to P37: Serial I/O pins)
Serial I/O
bit (SI
0
7
Fig. 2.4.5 Structure of Serial I/Orol register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-50
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
UART1 control register
b7 b6 b5 b4 b3 b2 b1 b0
UART1 control register
(UART1CON: address 001B16
)
b
0
Name
Functions
At reset R W
0
0
0
0
Character length
selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit
(PARE)
1
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
Parity selection bit
(PARS)
2
3
Stop bit length
selection bit (STPS) 1: 2 stop bits
0: 1 stop bit
P45
/TxD P-channel
1
4
0: CMOS output
(in output mode)
1: N-channel ope
output (in oue)
output disable bit
(POFF)
5
6
7
Nothing is arranged for these bitare
write disabled bits. When thesread
out, the contents are “1”.
1
1
1
ꢀ
ꢀ
ꢀ
Fig. 2.4.6 Structure of UART1 control register
UART3 control register
b7 b6 b5 b4 b3 b2 b1 b0
ntrol register
3CON: address 003316
)
b
0
Name
Functions
At reset R W
0
Character length
selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit
(PARE)
0
0
0
0
1
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
Parity selection bit
(PARS)
2
3
Stop bit length
selection bit (STPS) 1: 2 stop bits
0: 1 stop bit
P3
5
/TxD P-channel
3
4
0: CMOS output
(in output mode)
1: N-channel open-drain
output (in output mode)
output disable bit
(POFF)
5
6
7
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “1”.
1
1
1
ꢀ
ꢀ
ꢀ
Fig. 2.4.7 Structure of UART3 control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-51
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Baud rate generator i (i = 1, 3)
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate generator i
(BRGi (i=1, 3): address 001C16, 002F16
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefied
Und
Set a count value of baud rate generator.
Note: Write to this register while transmit/receive operopped.
Fig. 2.4.8 Structure of Baud rate generator 1 and Baud rate generat
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 001
b
0
Name
Internal
synchron
selecti
Functions
At reset R W
0
b2b1b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
0
0
0
0
0
0
1
2
5
6
ial I/O2 port
election bit
0: I/O port (P51, P52)
1: SOUT2, SCLK2 signal output
SRDY2 output
enable bit
Transfer direction
selection bit
0: I/O port (P53)
1: SRDY2 signal output
0: LSB first
1: MSB first
0: External clock
1: Internal clock
Serial I/O2
synchronous
clock selection bit
P5
1
/SOUT2
0: CMOS output
0
7
P-channel output
disable bit
(in output mode)
1: N-channel open-drain
output (in output mode)
Fig. 2.4.9 Structure of Serial I/O2 control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-52
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register
(SIO2: address 001F16)
b
Name
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefid
Un
0
1
2
3
4
5
6
7
This register becomes shift register.
At transmit: Set transmit data to this register.
At receive: Received data is stored to this
register.
Fig. 2.4.10 Structure of Serial I/O2 register
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection regi
(INTSEL: address 003916
)
b
0
Name
Functions
interrupt
At reset R W
0
INT
0
/Timer
0: INT
0
interrupt
selecti
1: Timer Z interrupt
0: Serial I/O2 interrupt
1: Timer Z interrupt
0
0
Seimer Z
iource
n bit (*1)
1
al I/O1 transmit/
CL, SDA interrupt
source selection bit
(*2)
0: Serial I/O1 transmit
interrupt
1: SCL, SDA interrupt
0
0
3
4
0: CNTR
1: SCL, SDA interrupt
0
interrupt
CNTR0/SCL, SDA
interrupt source
selection bit (*2)
0: INT
1: CNTR
4
interrupt
interrupt
INT /CNTR2
4
2
interrupt source
selection bit
5 INT
source selection bit
2
/I2C interrupt
0
0
0: INT
2
interrupt
1: I2C interrupt
0: CNTR interrupt
1: Serial I/O3 receive
interrupt
1
CNTR /Serial I/O3
receive interrupt
1
6
source selection bit
0
7 AD converter/Serial
I/O3 transmit
0: A/D converter interrupt
1: Serial I/O3 transmit
interrupt
interrupt source
selection bit
*1: Do not write 1 to these bits simultaneously.
*2: Do not write 1 to these bits simultaneously.
Fig. 2.4.11 Structure of Interrupt source selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-53
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 003C16
)
b
0
Name
Functions
At reset R W
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
INT
0
/Timer Z
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2 Serial I/O1 receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
3 Serial I/O1
transmit/SCL, SDA
interrupt request bit
ꢀ
ꢀ
ꢀ
ꢀ
0
0
4 Timer X interrupt
request bit
0 : No interrupt request issu
1 : Interrupt request iss
5
0 : No interrupt reque
1 : Interrupt requ
Timer Y interrupt
request bit
6
7
Timer 1 interrupt
request bit
0 : No interrupsued
1 : Interrupissued
Timer 2 interrupt
request bit
0 : No iuest issued
1 : Iquest issued
0
ꢀ: 0 can be set by softwacannot be set.
Fig. 2.4.12 Structure of Interrupt request register
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Intest register 2
(Idress 003D16
)
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
ꢀ
0
CNTR
0/SCL, SDA
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
0
1 CNTR
/Serial I/O3
1
receive interrupt
request bit
Serial I/O2/Timer Z 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
2
3
4
INT
request bit
INT interrupt
request bit
2
/I2C interrupt
0 : No interrupt request issued
1 : Interrupt request issued
3
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 INT
/CNTR
4
2
interrupt request bit
AD converter/Serial
I/O3 transmit
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are 0 .
ꢀ: 0 can be set by software, but 1 cannot be set.
Fig. 2.4.13 Structure of Interrupt request register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-54
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 003E16)
b
0
Name
Functions
At reset R W
0
0
0
0
INT
0
/Timer Z
interrupt enable bit
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1 INT
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 Serial I/O1 receive
interrupt enable bit
Serial I/O1
3
0 : Interrupt disabled
transmit/SCL, SDA 1 : Interrupt enabled
interrupt enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
4
5
6
7
0
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabl
Timer 1 interrupt
enable bit
0 : Interrupt di
1 : Interrupt
Timer 2 interrupt
enable bit
0 : Interred
1 : Intbled
Fig. 2.4.14 Structure of Interrupt control register
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Introl register 2
: address 003F16)
0
0
Name
/SCL, SDA
interrupt enable bit
CNTR / Serial I/O3
receive interrupt
enable bit
Functions
At reset R W
0
CNTR
0
0 : Interrupt disabled
1 : Interrupt enabled
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2/ Timer Z
interrupt enable bit
0
0
0
0
0
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
INT
enable bit
INT interrupt
enable bit
2
/I2C interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
3
INT /CNTR2
4
0 : Interrupt disabled
1 : Interrupt enabled
interrupt enable bit
AD converter/Serial
I/O3 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
7
Fix this bit to “0”.
0
Fig. 2.4.15 Structure of Interrupt control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-55
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.3 Serial I/O connection examples
(1) Control of peripheral IC equipped with CS pin
Figure 2.4.16 shows connection examples of a peripheral IC equipped with the CS pin.
There are connection examples using a clock synchronous serial I/O mode.
(1) Only transmission
(2) Transmission and reception
(Using the RXDi pin as an I/O port)
Port
CS
CLK
IN
Port
CS
S
CLKi
S
CLKi
CLK
DATA
TX
D
i
TXDi
RXDi
OU
3804 group
(Spec. H)
3804 group
(Spec. H)
Peripheral IC
(OSD controller etc.)
Pe
(etc.)
(3) Transmission and reception
(When connecting R with TXDi)
(4) Conf plural IC
X
Di
CS
CLK
IN
(When connecting IN with OUT in
peripheral IC)
Ki
T
X
D
D
i
i
Port
CS
CLK
IN
RX
OUT
SCLKi
Peripheral IC 1
Port
TXDi
R
X
D
i
3804 group
(Spec. H)
OUT
3804 group ꢀ1
(Spec. H)
Peripheral ICꢀ2
(E2 PROM etc.)
CS
CLK
IN
ꢀ
1: Select an N-channel openput for T
2: Use the OUT pin of perwhich is an N-channel open-
drain output and beh impedance during receiving data.
XDi pin output control.
OUT
ꢀ
Peripheral IC 2
Notes 1:
2:
“Port” metput port controlled by software.
Use SSIN2 instead of TxD
seri= 1, 3)
i
and RxD for the
i
Fig. 2.4.16 Serial connection examples (1)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-56
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
(2) Connection with microcomputer
Figure 2.4.17 shows connection examples with another microcomputer.
(1) Selecting internal clock
(2) Selecting external clock
S
CLKi
S
CLKi
CLK
IN
CLK
IN
TXDi
T
X
Di
i
R
XDi
R
X
D
OUT
OUT
3804 group
(Spec. H)
Microcomputer
Microcomputer
3804 group
(Spec. H)
ꢀ
(4) In UART
(3) Using
SRDYi signal output function
(Selecting an external clock)
RDY
CLK
IN
S
RDYi
T
X
D
i
D
S
CLKi
T
X
D
i
i
T
X
D
R
X
D
OUT
Microcomputer
oup
c. H)
Microcomputer
3804 group
(Spec. H)
ꢀ UART cannot be used for seri
Note: Use SOUT2 and SIN2 insxD
i
and RxD for the serial I/O2. (i = 1, 3)
i
Fig. 2.4.17 Serial I/O connectmples (2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-57
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.4 Setting of serial I/O transfer data format
A clock synchronous or clock asynchronous (UART) can be selected as a data format of serial I/O1 and
serial I/O3.
Serial I/O2 operates in a clock synchronous.
Figure 2.4.18 shows the serial I/O transfer data format.
1ST-8DATA-1SP
SP
ST
LSB
MSB
SP
1ST-7DATA-1SP
ST
LSB
MSB
MSB
MSB
1ST-8DATA-1PAR-1SP
SP
AR
SP
ST
LSB
PAR
1ST-7DATA-1PAR-1SP
ST
LSB
UART
1ST-8DATA-2SP
2SP
ST
LSB
MSB
2SP
1ST-7DATA-2SP
ST
LSB
Serial I/O1
Serial I/O3
1ST-8DATA-1PA
2SP
PAR
2SP
ST
LS
MSB
PAR
1ST-7DR-2SP
B
Clock synchro
Serial I/O
LSB first
LSB first
MSB first
ST : Start bit
SP : Stop bit
PAR : Parity bit
chronous
/O
Serial I/O2
Fig. 2.4.18 Serial I/O transfer data format
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-58
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.5 Serial I/O1, serial I/O3 operation: stop and initialize
Serial I/O1 and serial I/O3 perform the same operation. In the following explanations when names of serial
I/O1 and serial I/O3 are different, serial I/O1s' are showed first and then serial I/O3s' in the marked ( ).
(1) Clock synchronous serial I/O mode
ꢀStop/initialize transmit operation when only transmitting
When using an internal clock, set the transmit enable bit and serial I/O1 enable bit (serial I/O3
enable bit) to “0”.
When using an external clock, set the transmit enable bit to “0”.
By setting the transmit enable bit to “0”, the transmit operations listed below will be stopped or
initialized. However, when using an internal clock, the clock is output in 8 pulses, even if the
transmit enable bit is set to “0” during transmit operations.
•Stop supply of shift clock to transmit shift register
•Initialize clock control circuit for transmit
•Transmit buffer empty flag = “0”
•Transmit shift register shift complete flag = “0”
•P4
By setting the serial I/O1 enable bit (serial I/O3 enable bit) to s P4
/RxD , P3 /TxD , P3 /Sall become I/O ports. As a
5
/TxD
1
pin: input/output port P4
5
(P3
5
/TxD
3
pin: input/output
5
)
4
/RxD
1
, P4
5
/TxD
1
, P4 /
6
S
CLK1, and P4
7
/SRDY1 (P3
4
3
5
3
6
/SCLK3, P3
7
result, the internal clock cannot be output externally.
ꢀStop/initialize receive operation when only receivi
When using an internal clock, set the receive enand serial I/O1 enable bit (serial I/O3
enable bit) to “0”.
When using an external clock, set the receble bit or serial I/O1 enable bit (serial I/O3
enable bit) to “0”.
By setting the receive enable bit to receive operations listed below will be stopped or
initialized. However, when using anal clock, the clock is output in 8 pulses, even if the
receive enable bit is set to “0” deceive operations.
•Stop supply of shift clock ve shift register
•Initialize clock control cr receive
•Error flags (over-run, framing, and summing error flags) = “0”
•Receive buffer full “0”
•P4
4
/RxD
1
pin: inut port P4
4
(P3
4
/RxD
3
pin: input/output port P3 )
4
By setting the /O1 enable bit (serial I/O3 enable bit) to “0”, the receive operations listed
below will bed or initialized. As a result, the internal clock cannot be output externally.
•Stop f shift clock to receive shift register
•Initiaock control circuit for receive
•Error flags (over-run, parity, framing, and summing error flags) = “0”
•Receive buffer full flag = “0”
•P4
4
/RxD
1
, P4
5
/TxD
1
, P4
6
/SCLK1, P4
7
/SRDY1 pins: I/O ports P4
4
, P4
5
, P4
6
, P4
7
(P3
4
/RxD
3
, P3
5
/TxD
3
, P3
6
/SCLK3, P3
7
/SRDY3 pins: I/O ports P3
4
, P3
5
, P3
6
, P3
7
)
ꢀStop/initialize receive/transmit operation when both receiving and transmitting
Set the transmit enable bit and receive enable bit to “0” simultaneously.
When using an internal clock, also set the serial I/O1 enable bit (serial I/O3 enable bit) to “0”.
(2) UART Mode
ꢀStop/initialize transmit operation
Set the transmit enable bit to “0”.
ꢀStop/initialize receive operation
Set the receive enable bit to “0”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-59
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.6 Serial I/O pin function and selection method
(1) Serial I/O1, serial I/O3
Table 2.4.1 shows the pin function in the clock synchronous serial I/O mode, Table 2.4.2 shows the
pin function in the UART mode.
Table 2.4.1 Pin function in clock synchronous serial I/O mode
Serial I/O1 control register (address 001A16)
Serial I/O3 control register (address 003216)
Corre-
sponding
direction
register
Pin name
(Serial I/O1)
Pin name
(Serial I/O3)
b7
(Note 1)
b6
SIOE SIOM
b5
b4
b3
b2
b1
b0
Function
TE
1
TIC SRDY SCS CSS
RE
1
RxD1, RxD3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
1
✕
✕
✕
✕
1
✕
✕
✕
✕
✕
✕
0/1
✕
P44/RxD1
P45/TxD1
P46/SCLK1
P34/RxD3
P35/TxD3
P36/SCLK3
P44, P34
0
✕
1
TxD1, TxD3
✕
✕
✕
✕
1
P45, P35
0
0/1
SCLK1 (External clock input)
SCLK1 (Internal clock output)
1
1
0
(Note 2)
1
✕
✕
✕
SRDY1, SRDY3
P47, P37
P47/SRDY1
/CNTR2
P37/SRDY3
✕
✕
0
0/1
Note 1: When SIOE is set to “0”, all pins become I/O ports regardless of set value of b6–b0.
Note 2: In the pulse output mode, the programmable waveform generating mode, or the programmable onrating mode of
the timer Z, this pin functions as the timer Z function output pin regardless of b7-b0 setting.
✕: This is not used for the pin’s function setting.
Table 2.4.2 Pin function in UART mode
Serial I/O1 control ress 001A16
)
Corre-
sponding
direction
register
Pin name
(Serial I/O1)
Pin name
(Serial I/O3)
b7
(Note 1)
b6
SIOE SIOM
b5
RE
✕
1
b2
b1
b0
CSS
✕
Function
TIC SRDY SCS
1
1
1
1
0
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
1
✕
0/1
✕
RxD
P4
TxD
P4
CLK1 (External clock input)
P4
4
/RxD
1
P34/RxD3
✕
4
✕
✕
✕
P4
5
/TxD
1
P35/TxD3
5
0
✕
0/1
✕
S
✕
✕
P4
6
/SCLK1
P36/SCLK3
P4
P4
6
7
0/1
0
0
✕
✕
✕
✕
✕
✕
✕
✕
0
✕
✕
(Note 2)
✕
0/1
P4
7
/SRDY1
/CNTR
P37/SRDY3
2
Note 1: When SIOE is set to “0”, all pins becomegardless of set value of b6–b0.
Note 2: In the pulse output mode, the prograveform generating mode, or the programmable one-shot generating mode of
the timer Z, this pin functions as tnction output pin regardless of b7-b0 setting.
✕: This is not used for the pin’s function
(2) Serial I/O2
Table 2.4.3 she pin function in the clock synchronous serial I/O mode.
Table 2.4.3 Pin fin clock synchronous serial I/O mode
Correspond-
ing direction
register
Serial I/O2 control register (address 001D16
)
Fnction
Pin name
b7
✕
✕
0
b6
✕
✕
✕
b5
✕
✕
✕
b4
✕
✕
✕
b3
1
b2
✕
✕
✕
b1
b0
✕
✕
✕
(Note 1)
0
S
IN2
✕
✕
✕
P50/SIN2
P5
0
✕
1
0/1
✕
✕
CMOS output
S
OUT2
P5
1/SOUT2
N-channel open-drain output
1
✕
✕
0
✕
✕
✕
✕
✕
✕
✕
✕
1
0
1
1
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
(Note 3)
P5
CLK2 (External clock input)
CLK2 (Internal clock output)
P5
1
0/1
✕
(Note 2)
S
✕
✕
P5
2/SCLK2
S
1
✕
2
0/1
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
1
0
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
✕
S
RDY2
P5
3/SRDY2
0
0/1
P5
3
Notes 1: Although this pin functions as SIN2 when b3 is set to “0”, set “1” to b3.
Notes 2: Although this pin functions as SCLK2 when b3 and the corresponding direction register are set to “0”, set “1” to b3.
Notes 3: When the corresponding direction register bit is "1", the b7 setting is valid.
✕: This is not used for the pin’s function setting.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-60
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.7 Serial I/O application examples
(1) Communication using clock synchronous serial I/O (transmit/receive)
Outline : 2-byte data is transmitted and received, using the clock synchronous serial I/O.
The SRDY1 signal is used for communication control.
Figure 2.4.19 shows a connection diagram, and Figure 2.4.20 shows a timing chart.
Figure 2.4.21 shows a registers setting relevant to the transmitting side, and Figure 2.4.22 shows
registers setting relevant to the receiving side.
Transmitting side
Receiving side
S
RDY1
CLK1
P42/INT1
S
S
CLK1
RXD1
TXD1
3804 group
(Spec. H)
3804
(S
Note: Use SOUT2 and SIN2 instead of TxD
i
and Re serial I/O2. (i = 1, 3)
Fig. 2.4.19 Connection diagram
Specifications : • Serial I/O is used (clohronous serial I/O is selected.)
• Synchronous clock cy : 125 kHz (f(XIN) = 4 MHz is divided by 32)
• SRDY1 (receivable is used.
• The receiving tputs SRDY1 signal at intervals of 2 ms (generated by timer),
and 2-byte transferred from the transmitting side to the receiving side.
....
....
SRDY1
SCLK1
....
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
TXD
2 ms
Fig. 2.4.20 Timing chart (using clock synchronous serial I/O)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-61
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Transmitting side
Port P4 direction register (Address : 000916
)
b7
b0
0
P4D
Port P42/INT1: Input mode
Serial I/O1 status register (Address : 001916
)
b7
b0
SIO1STS
Transmit buffer empty flag
• Confirm that the data has been trfrom Transmit buffer
register to Transmit shift regis
• When this flag is “1”, it is pwrite the next transmission
data in to Transmit buffr.
Transmit shift register pletion flag
Confirm completiomitting 1-byte data with this flag.
“1” : Transmit seted
Serial I/O1 control register (Address :
b7
b0
SIO1CON
1
1
1
0 0
0
G count source : f(XIN
)
Serial I/O1 synchronous clock : BRG/4
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
te generator 1 (Address : 001C16
)
b0
Set “division ratio – 1”
BRG1
8 – 1
Interrupt edge selection register (Address : 003A16
)
b7
b0
INTEDGE
0
INT
1
falling edge active
Fig. 2.4.21 Registers setting relevant to transmitting side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-62
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Receiving side
Serial I/O1 status register (Address : 001916)
b7
b0
SIO1STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift rile Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occubled parity.
Framing error flag
“1” : When stop bits e detected at the specified timing
Summing error fl
“1” : when of the following errors occurs.
• error
error
aming error
Serial I/O1 control regisress : 001A16)
b7
1 1 1 1
SIO1CON
Serial I/O1 synchronous clock : External clock
SRDY1 output enabled
Transmit enabled
Set this bit to “1”, using SRDY1 output.
Receive enabled
Clock synchronous serial I/O
Serial I/O1 enabled
Fig. 2.4.22 Registers setting relevant to receiving side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-63
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Figure 2.4.23 shows a control procedure of the transmitting side, and Figure 2.4.24 shows a control
procedure of the receiving side.
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
(Address : 001A16
(Address : 001C16
(Address : 003A16), bit1
)
)
SIO1CON
BRG1
INTEDGE
1101xx00
2
8 – 1
0
0
IREQ1 (Address: 003C16), bit1?
• Detection of INT1 falling e
1
0
IREQ1 (Address : 003C16), bit1
The first byte of a
transmission data
TB1/RB1
(Address : 001816
• Tranata write
Trfer empty flag is set to “0”
ting.
)
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
SIO1STS (Address : 001916), bit0?
1
TB1/RB1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
The se of a
trandata
(Address : 001816
)
0
0
SIOdress : 001916), bit0?
1
• Judgment of transferring from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
SIO1STS (Address : 001916), bit2?
1
Fig. 2.4.23 Control procedure of transmitting side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-64
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIO1CON (Address : 001A16
)
1111x11x
2
N
Dummy data
0
Pass 2 ms?
Y
• An interval of 2 ms generated by Timer.
TB1/RB1 (Address : 001816
)
•
S
RDY1 output
RDY1 signal is output by ta to
the TB1/RB1.
Using the RDY1, set enable bit
(bit 4) of the SIO“1”.
S
S
SIO1STS (Address : 001916), bit1?
• Judgment oon of receiving
(Receive flag)
1
• Rof the first byte data.
Read out reception data from
buffer full flag is set to “0” by reading data.
TB1/RB1 (Address : 001816
)
SIO1STS (Address : 001916), bit1
• Judegment of completion of receiving
(Receive buffer full flag)
1
Read out reception
• Reception of the second byte data.
Receive buffer full flag is set to “0” by reading data.
TB1/RB1 (Addres6
)
Fig. 2.4.24 Contrdure of receiving side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-65
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
(2) Output of serial data (control of peripheral IC)
Outline : 4-byte data is transmitted and received, using the clock synchronous serial I/O.
The CS signal is output to a peripheral IC through port P6
3
.
Figure 2.4.25 shows connection diagrams of example for using serial I/O1 and example for using
serial I/O2 with the same specification, and Figure 2.4.26 shows a timing chart.
CS
CS
CS
CS
P63
P63
CLK
DATA
CLK
DATA
S
CLK1
SCLK2
CLK
DATA
CLK
DATA
T
X
D1
SOUT2
3804 group
(Spec. H)
3804 group
(Spec. H)
Peripheral IC
PIC
(1) Example for using Serial I/O1
(2) Example for rial I/O2
Fig. 2.4.25 Connection diagrams
Specifications : • Serial I/O is used (clock synchrorial I/O is selected.)
• Synchronous clock frequency Hz (f(XIN) = 4 MHz is divided by 32)
• Transfer direction : LSB fir
• The Serial I/O interrupt ised.
• Port P6
3
is connected tS pin (“L” active) of the peripheral IC for transmission
control; the output port P6
3
is controlled by software.
CS
CLK
DO0
DO1
DO2
DO3
DA
Note: When using serial I/O2, the SOUT2 pin becomes the high-impedance state
after transfer is completed.
Fig. 2.4.26 Timing chart (serial I/O1)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-66
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Figure 2.4.27 shows registers setting relevant to serial I/O1, and Figure 2.4.28 shows a setting of
serial I/O1 transmission data.
Serial I/O1 control register (Address : 001A16
b7 b0
)
SIO1CON
1 1 0 1 1 0 0 0
BRG count source : f(XIN
)
Serial I/O1 synchronous clock : BRG/4
S
RDY1 output disabled
Transmit interrupt source : Transmit shift operating completion
Transmit enabled
Receive disabled
Clock synchronous serial I/O
Serial I/O1 enabled
UART1 control register (Address : 001B16
b7 b0
)
UART1CON
0
P45/TXD1 pin : CMOS output
Baud rate generator 1 (Address : 001C16
b7 b0
)
BRG1
Set “division ratio – 1”
8 – 1
Interrupt control register 1 (Address : 003E16
b7 b0
)
ICON1
0
Sernsmit interrupt : Disabled
Interrupt request register 1 (AddrC16
b7 b0
)
IREQ1
0
Serial I/O1 transmit interrupt request
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Port P6 (Add0C16
b7 b0
)
P6
Port P63: CS signal to peripheral ICs
"L" active
Port P6 direction register (Address : 000D16
b7 b0
)
P6D
1
Port P6
3: Output mode
Fig. 2.4.27 Registers setting relevant to serial I/O1
Transmit/Receive buffer register 1 (Address : 001816
)
b7
b0
Set a transmission data.
TB1/RB1
Confirm that transmission of the previous data is
completed (bit 3 of the Interrupt request register 1
is “1”) before writing data.
Fig. 2.4.28 Setting of serial I/O1 transmission data
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-67
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
When the registers are set as shown in Fig. 2.4.27, serial I/O1 can transmit 1-byte data by writing
data to the transmit buffer register.
Thus, after setting the CS signal to “L”, write the transmission data to the transmit buffer register by
each 1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.4.29 shows a control procedure of serial I/O1.
ꢀ
RESET
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
• Serial I/O1 setting
SIO1CON
UART1CON
BRG1
ICON1
P6
11011000
2
(Address : 001A16
)
0
(Address : 001B16), bit4
8–1
0
1
(Address : 001C16
)
(Address : 003E16), bit3
(Address : 000C16), bit3
• Serial I/O1 transmit interruped
• CS signal output port se
(“H” level output)
P6D
XXXX1XXX
2
(Address : 000D16
)
P6 (Address : 000C16), bit3
0
• CS sit level to “L” setting
ial I/O1 transmit interrupt request bit to
0” setting
IREQ1 (Address : 003C16), bit3
0
a tran
dat
• Transmission data write
(Start of transmit 1-byte data)
TB1/RB1 (Address : 001816
)
0
• Judgment of completion of transmitting 1-byte
data
IREQ1 (Add3C16), bit3?
1
• Use any of RAM area as a counter for counting
the number of transmitted bytes
• Judgment of completion of transmitting the
target number of bytes
N
Cmplete to transmit data?
Y
• Returning CS signal output level to “H”
when transmission of the target number
of bytes is completed
P6 (Address : 000C16), bit3
1
Fig. 2.4.29 Control procedure of serial I/O1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-68
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Figure 2.4.30 shows registers setting relevant to serial I/O2, and Figure 2.4.31 shows a setting of
serial I/O2 transmission data.
Serial I/O2 control register (Address : 001D16
)
b7
b0
SIO2CON
1 0 0 1 0 1
0
Synchronous clock : f(XIN)/32
Serial I/O2 used
S
RDY2 output disabled
LSB first
Internal clock
Interrupt source selection register (Address : 003916
b7 b0
)
INTSEL
0
Serial I/O2/timer Z interrupt soction : Serial I/O2 interrupt
Interrupt control register 2 (Address : 003F16
)
b7 b0
ICON2
IREQ2
0
Serial I/O2 : Interrupt disabled
Interrupt request register 2 (Address :
b7 b0
0
Serial I/O2 interrupt request
Confirm completion of transmitting
1-byte data by one unit.
“1” : Transmit shift completion
Port P6 (AddreC16
)
b7 b0
P6
Port P63: CS signal to peripheral ICs
"L" active
Port 6 direction register (Address : 000D16
b7 b0
)
P6D
1
Port P63: Output mode
Fig. 2.4.30 Registers setting relevant to serial I/O2
Serial I/O2 register (Address : 001F16)
b7
b0
Set a transmission data.
SIO2
Confirm that transmission of the previous data is
completed (bit 2 of the Interrupt request register 2
is “1”) before writing data.
Fig. 2.4.31 Setting of serial I/O2 transmission data
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-69
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
When the registers are set as shown in Fig. 2.4.30, serial I/O2 can transmit 1-byte data by writing
data to the serial I/O2 register.
Thus, after setting the CS signal to “L”, write the transmission data to the serial I/O2 register by each
1 byte, and return the CS signal to “H” when the target number of bytes has been transmitted.
Figure 2.4.32 shows a control procedure of serial I/O2.
ꢀ
RESET
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SIO2CON
INTSEL
ICON2
P6
(Address : 001D16
)
• Serial I/O2 control register settin
01001010
XXXXXX0X
2
(Address : 003916
)
2
2
(Address : 003F16), bit2
(Address : 000C16), bit3
(Address : 000D16
• Serial I/O2 interrupt : Disabl
• CS signal output port sett
(“H” level output)
0
1
P6D
)
XXXX1XXX
P6 (Address : 000C16), bit3
0
• CS sit level to “L” setting
rial I/O2 interrupt request bit to “0” setting
IREQ2 (Address : 003D16), bit2
0
a trans
data
• Transmission data write
(Start of transmit 1-byte data)
SIO2 (Address : 001F16
)
0
• Judgment of completion of transmitting 1-byte
data
IREQ2 (Add3D16), bit2?
1
• Use any of RAM area as a counter for counting
the number of transmitted bytes.
• Judgment of completion of transmitting the
target number of bytes
N
Cmplete to transmit data?
Y
• Returning CS signal output level to “H”
when transmission of the target number
of bytes is completed
P6 (Address : 000C16), bit3
1
Fig. 2.4.32 Control procedure of serial I/O2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-70
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
(3) Cyclic transmission or reception of block data (data of specified number of bytes) between
two microcomputers
Outline : When the clock synchronous serial I/O is used for communication, synchronization of the
clock and the data between the transmitting and receiving sides may be lost because of
noise included in the synchronous clock. It is necessary to correct that constantly, using
“heading adjustment”.
This “heading adjustment” is carried out by using the interval between blocks in this
example. This example is described for serial I/O1, but this example also can apply serial
I/O3.
Figure 2.4.33 shows connection diagram.
S
CLK1
S
CLK1
R
XD1
T
XD1
TXD1
R
XD
Master unit
aor serial I/O2.
Note: Use SOUT2 and SIN2 instead of TxD
1
Fig. 2.4.33 Connection diagram
Specifications :
• Serial I/O is used (cchronous serial I/O is selected).
• Synchronous clocncy : 131 kHz (f(XIN) = 4.19 MHz is divided by 32)
• Byte cycle: 488
• Number of btransmission or reception : 8 byte/block
• Block trancle : 16 ms
• Block tterm : 3.5 ms
• Interween blocks : 12.5 ms
• Hadjustment time : 8 ms
Limitations oecifications :
eading of the reception data and setting of the next transmission data must be
completed within the time obtained from “byte cycle – time for transferring 1-byte
data” (in this example, the time taken from generating of the serial I/O1 receive
interrupt request to input of the next synchronous clock is 431 µs).
• “Heading adjustment time < interval between blocks” must be satisfied.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-71
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
The communication is performed according to the timing shown in Figure 2.4.34. In the slave unit,
when a synchronous clock is not input within a certain time (heading adjustment time), the next clock
input is processed as the beginning (heading) of a block.
When a clock is input again after one block (8 byte) is received, the clock is ignored.
Figure 2.4.35 shows relevant registers setting.
D
0
D
1
D
2
D
7
D
0
Byte cycle
Interval between blocks
Block transfer term
Block transfer cycle
Heading adjustment ti
Processing for headiment
Fig. 2.4.34 Timing chart
Master unit
Slave unit
Serial I/O1 control register (Address : 001A16
)
Serial I/O1 control register (Address : 001A16
)
b7 b0
b7
b0
SIO1CON
SIO1CON
1 1
0 1
1 1
1 1 1 1 1 0 0 0
BRG count sou
Not be affected by external clock
Synchronous clock : External clock
SynchronouRG/4
RDY1 outd
S
RDY1 output disabled
S
Not use the serial I/O1 transmit interrupt
Transmit enabled
Transt source :
Troperating completion
nabled
Receive enabled
enabled
Clock synchronous serial I/O
Serial I/O1 enabled
k synchronous serial I/O
erial I/O1 enabled
Both of units
UART1 control register (Address : 001B16
)
b7 b0
UART1CON
0
P45/TXD1 pin : CMOS output
Baud rate generator 1 (Address : 001C16
)
b7 b0
BRG1
Set “division ratio – 1”
8 – 1
Fig. 2.4.35 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-72
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Control procedure :
ꢀ Control in the master unit
After setting the relevant registers shown in Figure 2.4.35, the master unit starts transmission or
reception of 1-byte data by writing transmission data to the transmit buffer register.
To perform the communication in the timing shown in Figure 2.4.34, take the timing into account
and write transmission data. Additionally, read out the reception data when the serial I/O1 transmit
interrupt request bit is set to “1,” or before the next transmission data is written to the transmit
buffer register.
Figure 2.4.36 shows a control procedure of the master unit using timer interrupts.
Interrupt processing routine
executed every 488µs
CLT (Note 1)
CLD (Note 2)
Push register to stack
Note 1: When using the Index X mode flag (
Note 2: When using the Decimal mode fla
Push the register used in the interrupt
processing routine into the stack.
ꢀ
N
Within a block transfer
period?
te a certain block interval by
g a timer or other functions.
Y
ꢀ
Check the block interval counter and
determine to start a block transfer.
Count a val counter
Read a reception data
N
Y
Complete to transfer a
block?
tart a block transfer?
Y
N
Write the first transmission data
(first byte) in a block
Write a transmission data
ꢀ
Pop registers which is pushed to stack.
Poers
RTI
Fig. 2.4.36 Control procedure of master unit
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-73
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
ꢀ Control in the slave unit
After setting the relevant registers as shown in Figure 2.4.35, the slave unit becomes the state
where a synchronous clock can be received at any time, and the serial I/O1 receive interrupt
occurs each time an 8-bit synchronous clock is received.
In the serial I/O1 receive interrupt processing routine, the data to be transmitted next is written to
the transmit buffer register after the received data is read out.
However, if no serial I/O1 receive interrupt occurs for a certain time (heading adjustment time or
more), the following processing will be performed.
1. The first 1-byte data of the transmission data in the block is written into the transmit buffer register.
2. The data to be received next is processed as the first 1 byte of the received data in the block.
Figure 2.4.37 shows a control procedure of the slave unit using the serial I/O1 receive interrupt
and any timer interrupt (for heading adjustment).
Timer interrupt processing
routine
Serial I/O1 receive interrupt
processing routine
CLT (Note 1)
CLD (Note 2)
Push register to stack
CLT (Note 1
CLD (Not
Push reack
• Push the register used in
the interrupt processing
routine into the stack.
• Push the register used in
the interrupt processing
routine into the stack.
• Confirm the received
byte counter to judge
the block transfer term.
adjustment
N
unter – 1
Within a block transfer
term?
Y
N
Heading adjustment
counter = 0?
Read a reception data
Y
Write the first transmission
data (first byte) in a block
A received byte counter +1
0
A received byte counter
Y
A received byte
counter ≥ 8?
N
• Pop registers which is pushed
to stack.
Pop registers
RTI
Write dummy data (FF16)
Write a transmissio
tial
value
(Note 3)
Heading
adjustment
counter
Pop registers
• Pop registers which is pushed
to stack.
Notes 1: When using the Index X mode flag (T).
2: When using the Decimal mode flag (D).
RTI
3: In this example, set the value which is equal to the
heading adjustment time divided by the timer interrupt
cycle as the initial value of the heading adjustment
counter.
For example: When the heading adjustment time is 8 ms
and the timer interrupt cycle is 1 ms, set
8 as the initial value.
Fig. 2.4.37 Control procedure of slave unit
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-74
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
(4) Communication (transmit/receive) using asynchronous serial I/O (UART)
Outline : 2-byte data is transmitted and received, using the asynchronous serial I/O.
Port P4 is used for communication control.
0
Figure 2.4.38 shows a connection diagram, and Figure 2.4.39 shows a timing chart.
Transmitting side
Receiving side
P40
P40
T
XD
RXD
3804 group
(Spec. H)
3804 gro
(Spe
Fig. 2.4.38 Connection diagram (Communication using U
Specifications : • Serial I/O1 is used (UART ied).
• Transfer bit rate : 9600 bN) = 4.9152 MHz is divided by 512)
• Communication controport P4
(The output level of is controlled by software.)
0
0
• 2-byte data is tranfrom the transmitting side to the receiving side at intervals
of 10 ms geney the timer.
• • • •
P40
TXD1
• • • •
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0
ST
ST
ST
SP(2)
SP(2)
10 ms
Fig. 2.4.39 Timing chart (using UART)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-75
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Table 2.4.4 shows setting examples of the baud rate generator (BRG) values and transfer bit rate
values; Figure 2.4.40 shows registers setting relevant to the transmitting side; Figure 2.4.41 shows
registers setting relevant to the receiving side.
Table 2.4.4 Setting examples of Baud rate generator (BRG) values and transfer bit rate values
BRG count source
Transfer bit rate (bps) (Note 2)
at f(XIN) = 4.9152 MHZ at f(XIN) = 16 MHZ
BRG setting value
(Note 1)
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)/4
f(XIN)
255(FF16)
127(7F16)
63(3F16)
31(1F16)
15(0F16)
7(0716)
300
600
976.5625
1953.125
3906.25
7812.5
1200
2400
4800
25
9600
1250
3(0316)
19200
38400
76800
15360
30
62500
1(0116)
125000
250000
500000
1000000
3(0316)
f(XIN)
1(0116)
f(XIN)
0(0016)
Notes 1: Select the BRG count source with bit 0 of tl I/O1 control register (Address : 001A16).
2: Equation of transfer bit rate:
Transfer bit rate (bps) =
(BRG seue + 1) ꢀ 16 ꢀꢀmꢀ
ꢀm: When bit 0 of the seriaontrol register (Address : 001A16) is set to “0,” a value of
m is 1.
When bit 0 of the /O1 control register (Address : 001A16) is set to “1,” a value of
m is 4.
Rev.1.00 Jan 14, 2005
2-76
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Transmitting side
Serial I/O1 status register (Address : 001916)
b7
b0
SIO1STS
Transmit buffer empty flag
• Confirm that the data has been transferred from Transmit buffer
register to Transmit shift register.
• When this flag is “1”, it is possible to write the next transmission
data in to Transmit buffer register.
Transmit shift register shift completion flag
Confirm completion of transmitting 1-byte data with this flag.
“1” : Transmit shift completed
Serial I/O1 control register (Address : 001A16)
b7
b0
1
SIO1CON
0 0 1
0 0 1
BRG count source : f(XIN)/4
Synchronous clock : BRG/1
SRDY1 output disabled
Transmit enabled
Receive disabled
Asynchronou(UART)
Serial I/O1
UART1 control register (Address :
b7
b0
UART1CON
0 1
0
0
haracter length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
P4
5/T
X
D1 pin : CMOS output
Baud rate or 1 (Address : 001C16)
b7
b0
f(XIN
)
–1
Set
– 1
BRG1
ꢀ
Transfer bit rate ꢀ 16 ꢀ m
ꢀ When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,”
a value of m is 1.
When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,”
a value of m is 4.
Port P4 (Address : 000816)
b7
b0
P4
0
Port P4
0: Communication control: “H” active
Port P4 direction register (Address : 000916)
b7
b0
1
P4D
Port P40: Communication control: Output mode
Fig. 2.4.40 Registers setting relevant to transmitting side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-77
APPLICATION
3804 Group (Spec.H)
Receiving side
2.4 Serial interface
Serial I/O1 status register (Address : 001916
)
b7
b0
SIO1STS
Receive buffer full flag
Confirm completion of receiving 1-byte data with this flag.
“1” : at completing reception
“0” : at reading out contents of Receive buffer register
Overrun error flag
“1” : When data is ready in Receive shift register while Receive buffer
register contains the data.
Parity error flag
“1” : When a parity error occurs in enabled parity.
Framing error flag
“1” : When stop bits cannot be detected at td timing
Summing error flag
“1” : when any one of the following ers.
• Overrun error
• Parity error
• Framing error
Serial I/O1 control register (Address : 001A16
)
b7
b0
SIO1CON
1 0 1 0
0 0
1
BRG count sour/4
SynchronouRG/16
S
RDY1 ouled
Tranled
Rabled
onous serial I/O(UART)
l I/O1 enabled
UART1 control regdress : 001B16
)
b7
0
UART1CON
Character length : 8 bits
Parity checking disabled
Stop bit length : 2 stop bits
Baud rate generator 1 (Address : 001C16
)
b7
b0
f(XIN
)
–1
ꢀ
Set
8 – 1
BRG1
Transfer bit rate ꢀ 16 ꢀ m
When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “0,”
a value of m is 1.
ꢀ
When bit 0 of Serial I/O1 control register (Address : 001A16) is set to “1,”
a value of m is 4.
Port P4 direction register (Address : 000916
)
b7
b0
P4D
0
Port P4
0: Communication control: Input mode
Fig. 2.4.41 Registers setting relevant to receiving side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-78
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
Figure 2.4.42 shows a control procedure of the transmitting side, and Figure 2.4.43 shows a control
procedure of the receiving side.
ꢀ
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SIO1CON (Address : 001A16
UART1CON (Address : 001B16
)
)
)
1001X001
2
00001000
2
BRG1
P4
(Address : 001C16
(Address : 000816), bit0
8–1
• Port P4 set for communication control
0
0
P4D
(Address : 000916)
XXXXXXX1
2
N
• An interval of 10 ms genTimer
• Communic
Pass 10 ms?
Y
1
P4 (Address : 000816), bit0
• Tradata write
Tuffer empty flag is set to “0”
writing.
TB1/RB1
(Address : 001816
The first byte of a
transmission data
)
udgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIO1STS (Address : 001916), bit0?
1
• Transmission data write
Transmit buffer empty flag is set to “0”
by this writing.
TB1/RB1
(Address : 001816
The yte of
a ion data
)
• Judgment of transferring data from Transmit
buffer register to Transmit shift register
(Transmit buffer empty flag)
0
SIO1STS : 001916), bit0?
1
0
• Judgment of shift completion of Transmit shift register
(Transmit shift register shift completion flag)
SIO1STS (Address : 001916), bit2?
1
0
• Communication completion
P4 (Address : 000816), bit0
Fig. 2.4.42 Control procedure of transmitting side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-79
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
ꢀꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
SIO1CON
UART1CON
BRG1
(Address : 001A16
(Address : 001B16
)
)
)
1010X001
2
00001000
2
(Address : 001C16
(Address : 000916
8–1
XXXXXXX0
P4D
)
2
0
SIO1STS (Address : 001916), bit1?
• Judgment of completion of re
(Receive buffer full flag)
1
• Reception of the firsa
Receive buffer fulet
to “0” by readin
Read out a reception data
from RB1 (Address : 001816
)
• Judgmerror flag
1
SIO1STS (Address : 001916), bit6?
0
• Judgment of completion of
receiving
SIO1STS (Address : 001916), bit
(Receive buffer full flag)
1
• Reception of the second byte data
Receive buffer full flag is set
to “0” by reading data.
Read out a recep
from RB1 (Add816
)
• Judgment of an error flag
1
SIO1STs : 001916), bit6?
0
Processing for error
1
P4 (Address : 000816), bit0?
0
• Countermeasure for a bit slippage
SIO1CON (Address : 001A16
SIO1CON (Address : 001A16
)
)
0000X001
1010X001
2
2
Fig. 2.4.43 Control procedure of receiving side
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-80
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
2.4.8 Notes on serial interface
(1) Notes when selecting clock synchronous serial I/O
ꢀ Stop of transmission operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous
(UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and
transmit disabled).
ꢀ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in
this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O ports, the transmission data is
not output). When data is written to the transmit buffer register in this data starts to be
shifted to the transmit shift register. When the serial I/Oi enable bit is 1” at this time, the
data during internally shifting is output to the TxDi pin and an operilure occurs.
ꢀ Stop of receive operation
As for serial I/Oi (i = 1, 3) that can be used as either a clohronous or an asynchronous
(UART) serial I/O, clear the receive enable bit to “0” (reisabled), or clear the serial I/Oi
enable bit to “0” (serial I/Oi disabled).
ꢀ Stop of transmit/receive operation
As for serial I/Oi (i = 1, 3) that can be used aa clock synchronous or an asynchronous
(UART) serial I/O, clear both the transmit et and receive enable bit to “0” simultaneously
(transmit and receive disabled) in the clohronous serial I/O mode.
(When data is transmitted and receiveclock synchronous serial I/O mode, any one of data
transmission and reception cannot ped.)
ꢀ Reason
In the clock synchronous semode, the same clock is used for transmission and reception.
If any one of transmissioeception is disabled, a bit error occurs because transmission and
reception cannot be sized.
In this mode, the cloit of the transmission circuit also operates for data reception. Accordingly,
the transmission does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Alsansmission circuit is not initialized by clearing the serial I/Oi enable bit to “0”
(serial I/Oi d) (refer to ꢀ in (1) ).
(2) Notes whelecting clock asynchronous serial I/O
ꢀ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled). Transmission operation does not stop by
setting the serial I/Oi enable bit (i = 1, 3) to “0”.
ꢀ Reason
This is the same as ꢀ in (1).
ꢀ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
Rev.1.00 Jan 14, 2005
2-81
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
ꢀ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled). Transmission operation does not stop by
setting the serial I/Oi enable bit (i = 1, 3) to “0”.
ꢀ Reason
This is the same as ꢀ in (1).
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDYi (i = 1, 3) output of reception side
When signals are output from the SRDYi pin on the reception side by using an external clock in the
clock synchronous serial I/O mode, set all of the receive enable bit, the SRDYi output enable bit, and
the transmit enable bit to “1” (transmit enabled).
(4) Setting serial I/Oi (i = 1, 3) control register again
Set the serial I/Oi control register again after the transmission and thion circuits are reset
by clearing both the transmit enable bit and the receive enable bit
Clear both the transmit enable
bit (TE) and the receive enable
bit (RE) to “0”
↓
Set the bits 0 to 3 and b
serial I/Oi control r
Can be set with the
LDM instruction at
Set both the t enable bit
(TE) and eive enable bit
(RE)of them to “1”
the same time
Fig. 2.4.44 Sequence of setting I/Oi (i = 1, 3) control register again
(5) Data transmission cwith referring to transmit shift register completion flag
After the transmit written to the transmit buffer register, the transmit shift register completion
flag changes frto “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled wiring to the flag after writing the data to the transmit buffer register, note the
delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit
buffer register at “H” of the SCLKi input level.
Rev.1.00 Jan 14, 2005
2-82
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.4 Serial interface
(7) Transmit interrupt request when transmit enable bit is set
When the transmit interrupt is used, take the following sequence.
ꢀ Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “0” (disabled).
ꢀ Set the tranasmit enable bit to “1”.
ꢀ Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to “0” after 1 or more instruction has
executed.
ꢀ Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “1” (enabled).
ꢀ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register shift completion flag are also set to “1”.
Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt
request is generated and the transmit interrupt request bit is set at this point.
(8) Writing to baud rate generator i (BRGi) (i = 1, 3)
Write data to the baud rate generator i (BRGi) (i = 1, 3) while the trann/reception operation
is stopped.
Rev.1.00 Jan 14, 2005
2-83
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5 Multi-master I2C-BUS interface
The only 3804 group has functions of the multi-master I2C-BUS interface.
The multi-master I2C-BUS interface is a serial communication circuit, conforming to the Philips I2C-BUS data
transfer format. This paragraph explains the I2C-BUS overview and communication examples.
2.5.1 Memory map
001016
001116
MISRG
2
I C data shift register (S0)
2
I C special mode status register (S3)
001216
001316
001416
001516
001616
001716
2
I C status register (S1)
2
I C control register (S1D)
2
I C clock control register (S2)
2
I C START/STOP condition cregister (S2D)
2
I C special mode control r (S3D)
003916
Interrupt source sn register (INTSEL)
003C16
003D16
Interrupt rregister 1 (IREQ1)
Interruest register 2 (IREQ2)
Incontrol register 1 (ICON1)
upt control register 2 (ICON2)
003E16
003F1
2
I C slave address register 0 (S0D0)
16
F816
2
I C slave address register 1 (S0D1)
2
0FF916
I C slave address register 2 (S0D2)
Fig. 2.5.1 Memory map of registers relevant to I2C-BUS interface
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-84
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5.2 Relevant registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 001016
)
b
0
Name
Functions
At reset R W
Oscillation stabilizing 0: Automatically set (Note 1)
time set after STP
0
1: Autimatically set disabled
instruction released bit
0: Not set automatically
1: Automatic switching
enabled (Notes 2, 3)
Middle-speed mode
automatic switch set
bit
0
1
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
0
2 Middle-speed mode
automatic switch
wait time set bit
Middle-speed mode 0: Invalid
3
automatic switch
start bit
1: Automatic switch s
(Note 3)
(Depending on
program)
4
5
6
7
Nothing is arranged for these be are
write disabled bits. When thre read
out, the contents are 0 .
0
0
0
0
✕
✕
✕
✕
Notes 1: 0116 is set to Timer 1, et to Prescaler 12.
2: During operation in lomode, it is possible automatically to switch to
middle-speed modthe rising of SCL/SDA.
3: When automatimiddle-speed mode from low-speed mode occurs,
the values of e register (003B16) change.
Fig. 2.5.2 Structure of MISRG
2
I C data shift r
b7 b6 b5 bb0
I2C data shift register
(S0: address 001116)
b
Functions
At reset R W
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• 8-bit shift register to store receive data and
write transmit data.
1
2
3
4
5
6
7
Note: When data is written to I2C data shift register after the MST
bit is set to “0” (slave mode), keep the interval for 8 machine
cycles or more.
Also, when the read-modify-write instructions (SEB, CLB) are
used during data transfer, the values may be undefined.
Fig. 2.5.3 Structure of I2C data shift register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-85
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2
I C special mode status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C special mode status register
(S3: address 001216)
b
0
Name
Functions
At reset R W
Slave address 0
comparison flag
(AAS0)
ꢀ
0: Address disagreement
1: Address agreement
(Notes 1, 2)
0
0
ꢀ
ꢀ
1
2
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Slave address 1
comparison flag
(AAS1)
Slave address 2
comparison flag
(AAS2)
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Nothing is arranged for this bit. This is a
disabled bit. When this bit is read out,
contents are 0 .
0
0
1
0
3
4
ꢀ
ꢀ
ꢀ
Nothing is arranged for this bit. write
disabled bit. When this bit is rhe
contents are undefined.
0: ow hold
in low release
tes 1, 3)
SCL pin low hold 2
flag (PIN2)
5
6
7
Nothing is arrahis bit. This is a write
disabled bit. s bit is read out, the
contents
ꢀ
ꢀ
STOP
flag
0: No detection
1: Detection (Notes 1, 4)
0
Notes 1: Thnd flags can be read out, but cannot be written.
2: s can be detected only when the data format selection bit
of I2C control register is set to 0 .
bit is initialized to 1 at reset, when the ACK interrupt control bit
s 0 , or when writing 1 to the SCL pin low hold 2 flag set bit.
: This bit is initialized to 0 at reset, when the I2C-BUS interface
enable bit (ES0) is 0 , or when writing 1 to the STOP condition
flag clear bit.
Fig. 2.5.4 StructuI2C special mode status register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-86
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2
I C status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register
(S1: address 001316)
b
0
Name
Last receive bit
(LRB)
Functions
0: Last bit = 0
1: Last bit = 1 (Note 1)
At reset R W
Undefined
General call
detection flag
(AD0)
0
0
0
0: No general call detected
1: General call detected
(Notes 1, 2)
1
2
Slave address
comparison flag
(AAS)
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Arbitration lost
detection flag (AL)
0: Not detected
1: Detected (Note 1)
3
4
5
6
SCL pin low hold
bit (PIN)
0: SCL pin low hold (Note 3)
1: SCL pin low release
0
Bus busy flag (BB)
0: Bus free
1: Bus busy
b7 b6
0
0
Communication
mode specification
bits (TRX, MST)
0 0: Slave ree
0 1: Slave mode
1 0: Mave mode
1 1: Mnsmit mode
7
Notes 1: These flags and bclusive to input. When writing to
these bits, writse bits.
2: These bits cacted only when the data format
selection of I2C control register is set to 0 .
3: This bit t to 1 by program, but cannot be cleared
to 0
4: All hanged by hardware. Do not use the read-
ite instructions (SEB, CLB).
Fig. 2.5.5 Structure of I2C status r
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-87
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2
I C control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register
(S1D: address 001416
)
b
0
Name
Bit counter
(Number of
transmit/receive
bits)
(BC0, BC1, BC2)
Functions
At reset R W
0
b2b1b0
0 0 0: 8
0 0 1: 7
0 1 0: 6
0 1 1: 5
1 0 0:
1 0 1:
1 1 0:
1 1 1:
1
2
0
0
4
3
2
1
I2C-BUS interface
enable bit (ES0)
Data format
0: Disabled
1: Enabled
3
4
5
0: Addressing format
selection bit (ALS) 1: Free data format
Addressing format
selection bit
(10BIT SAD)
0
0
0: 7-bit addressing
1: 10-bit addresat
6
7
Nothing is arranged for this bit. write
disabled bit. When this bit is the
contents are 0 .
ꢀ
I2C-BUS interface pin 0input
input level selection S input
bit (TISS)
0
Note: Do not use modify-write instruction because some bits
change bre when the start condition is detected and
the byr is completed.
Fig. 2.5.6 Structure of I2C control regi
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-88
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2
I C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register
(S2: address 001516
)
b
0
Name
SCL frequency
control bits
(CCR0, CCR1,
CCR2, CCR3,
CCR4)
Functions
At reset R W
Standard High-speed
clock mode clock mode
Disabled Disabled
Disabled 333
Setting value
0
0
0
0
b4b3b2b1b0
00 to 02
03
1
2
04
(Note 2) 250
05
100
400 (Note 3)
06
83.3
166
500/CCR value 1000/CCR value
(Note 3) (Note 3)
3
4
5
1D
1E
1F
17.2
16.6
16.1
34.5
33.3
32.3
(φ = 4 MHz, Unit: kHz) (N
SCL mode
specification bit
(FAST MODE)
0: Standard clock m
1: High-speed clo
6
7
ACK bit
(ACK BIT)
0
0
0: ACK is r
1: ACK is ned.
0: No k
1: A
ACK clock bit
(ACK)
Notes 1: Duty of SCL clock output is 50 %. The mes 35 to 45 % only when the high-
speed clock mode is selected and CC5 (400 kHz, at φ = 4 MHz). H
duration of the clock fluctuates from 2 machine cycles in the standard clock
mode, and fluctuates from —2 tine cycles in the high-speed clock mode. In
the case of negative fluctuatioquency does not increase because L
duration is extended insteauration reduction.
These are values when synchronization by the synchronous function is not
performed. CCR valucimal notation value of the SCL frequency control bits
CCR4 to CCR0.
2: Each value of Sncy exceeds the limit at φ = 4 MHz or more. When using
these setting φ of 4 MHz or less.
3: The data foSCL frequency is described below:
φ/(8 ꢀ C) Standard clock mode
φ/(4 ꢀ ue) High-speed clock mode (CCR value ≠ 5)
φ/(value) High-speed clock mode (CCR value = 5)
0 to 2 as CCR value regardless of φ frequency.
kHz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed
mode to the SCL frequency by setting the SCL frequency control bits CCR4 to
CR0.
Fig. 2.5.7 Structure of I2C clock control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-89
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2
I C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
0
I2C START/STOP condition control register
(S2D: address 001616)
b
0
1
Name
Functions
At reset R W
START/STOP
condition set bits
(SSC0, SSC1,
SSC2, SSC3,
SSC4)
0
SCL release time
= φ (µs) ꢀ (SSC+1)
Setup time
= φ (µs) ꢀ (SSC+1)/2
Hold time
1
0
1
1
2
3
4
5
= φ (µs) ꢀ (SSC+1)/2
SCL/SDA interrupt
pin polarity selection
bit (SIP)
0: Falling edge active
1: Rising edge active
6
SCL/SDA interrupt
pin selection bit
(SIS)
0: SDA valid
1: SCL valid
0
7 Fix this bit to 0 .
Note: Fix SSC0 to 0 . Also, do not set SSC4 to Sd values or 000002 .
Fig. 2.5.8 Structure of I2C START/STOP condition control r
2
I C special mode control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C special moegister
(S3D: addre
0
0
b
e
Functions
At reset R W
bit to 0 .
nterrupt control
(ACKICON)
0
0
0
0: At communication
completion
1: At falling of ACK clock and
communication completion
0
2 Slave address
0: One-byte slave address
compare mode
control bit (MSLAD)
1: Three-byte slave address
compare mode
0
ꢀ
3 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are 0 .
4
0
0
Fix this bit to 0 .
SCL pin low hold 2
flag set bit (PIN2IN)
5
Writing 1 to this bit initializes
the SCL pin low hold 2 flag
to 1 . (Notes 1, 2)
SCL pin low hold
set bit (PIN2HD)
Writing 1 to this bit clears
the SCL pin low hold 2 flag to
0 and holds the SCL pin low.
(Notes 1, 2)
0
0
6
STOP condition flag Writing 1 to this bit initializes
clear bit (SPFCL)
7
the STOP condition flag to
0 . (Note 1)
Notes 1: When 0 is written to these bits, nothing is happened.
2: Do not write 1 to these bits at the same time.
Fig. 2.5.9 Structure of I2C special mode control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-90
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2
I C slave address register i (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
I2C slave address register i (i = 0 to 2)
(S0D0, S0D1, S0D2: addresses 0FF716, 0FF816, 0FF916
)
b
Name
Functions
At reset R W
0: Write bit
1: Read bit
0 Read/Write bit
(RWB)
0
1
0
0
0
0
0
Slave address
The contents of these bits
(SAD0, SAD1, SAD2, are compared with the
SAD3, SAD4, SAD5, address data transmitted
2
3
4
5
6
7
SAD6)
from master.
Note: When the read-modify-write instructions (SEre used at
detection of stop condition, the values mafined.
Fig. 2.5.10 Structure of I2C slave address register i (i = 0 to 2)
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection r
(INTSEL: address 0039
b
0
Name
Functions
interrupt
At reset R W
0
INT
0
/Tim
0: INT
0
interru
sele*1)
1: Timer Z interrupt
0: Serial I/O2 interrupt
1: Timer Z interrupt
0
0
2/Timer Z
t source
ction bit (*1)
1
erial I/O1 transmit/
SCL, SDA interrupt
source selection bit
(*2)
0: Serial I/O1 transmit
interrupt
1: SCL, SDA interrupt
0
0
3
4
0: CNTR
1: SCL, SDA interrupt
0
interrupt
CNTR0/SCL, SDA
interrupt source
selection bit (*2)
0: INT
1: CNTR
4
interrupt
interrupt
INT /CNTR2
4
2
interrupt source
selection bit
/I2C interrupt
0
0
0: INT
2
interrupt
5 INT
source selection bit
2
1: I2C interrupt
0: CNTR interrupt
1: Serial I/O3 receive
interrupt
1
CNTR /Serial I/O3
receive interrupt
1
6
source selection bit
0
7 AD converter/Serial
I/O3 transmit
0: A/D converter interrupt
1: Serial I/O3 transmit
interrupt
interrupt source
selection bit
*1: Do not write 1 to these bits simultaneously.
*2: Do not write 1 to these bits simultaneously.
Fig. 2.5.11 Structure of Interrupt source selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-91
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 003C16
)
b
0
Name
Functions
At reset R W
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
INT
0
/Timer Z
0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
1 INT
1 interrupt
0 : No interrupt request issued
1 : Interrupt request issued
request bit
2 Serial I/O1 receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
3 Serial I/O1
transmit/SCL, SDA
interrupt request bit
ꢀ
ꢀ
ꢀ
ꢀ
0
0
4 Timer X interrupt
request bit
0 : No interrupt request issu
1 : Interrupt request iss
5
0 : No interrupt reque
1 : Interrupt requ
Timer Y interrupt
request bit
6
7
Timer 1 interrupt
request bit
0 : No interrupsued
1 : Interrupissued
Timer 2 interrupt
request bit
0 : No iuest issued
1 : Iquest issued
0
ꢀ: 0 can be set by softwacannot be set.
Fig. 2.5.12 Structure of Interrupt request registe
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Intest register 2
ddress 003D16
)
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
ꢀ
0
CNTR
0/SCL, SDA
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
ꢀ
0
1 CNTR
/Serial I/O3
1
receive interrupt
request bit
Serial I/O2/Timer Z 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
0
0
0
0
0
2
3
4
INT
request bit
INT interrupt
request bit
2
/I2C interrupt
0 : No interrupt request issued
1 : Interrupt request issued
3
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 INT
/CNTR
4
2
interrupt request bit
AD converter/Serial
I/O3 transmit
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are 0 .
ꢀ: 0 can be set by software, but 1 cannot be set.
Fig. 2.5.13 Structure of Interrupt request register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-92
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 003E16)
b
0
Name
Functions
At reset R W
0
INT
0
/Timer Z
0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
0
0
0
1 INT
interrupt
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
enable bit
2 Serial I/O1 receive
interrupt enable bit
Serial I/O1
3
0 : Interrupt disabled
transmit/SCL, SDA 1 : Interrupt enabled
interrupt enable bit
4 Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enable
0
0
0
Timer Y interrupt
5
enable bit
Timer 1 interrupt
6
0 : Interrupt disa
1 : Interrupt e
enable bit
Timer 2 interrupt
7
0 : Interrud
1 : Interled
enable bit
Fig. 2.5.14 Structure of Interrupt control register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interruegister 2
0
(ICess 003F16
)
Name
/SCL, SDA
interrupt enable bit
CNTR / Serial I/O3
receive interrupt
enable bit
Functions
At reset R W
0
CNTR
0
0 : Interrupt disabled
1 : Interrupt enabled
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
Serial I/O2/ Timer Z
interrupt enable bit
0
0
0
0
0
2
3
4
5
0 : Interrupt disabled
1 : Interrupt enabled
INT
enable bit
INT interrupt
enable bit
INT /CNTR
2
/I2C interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
3
4
2
0 : Interrupt disabled
interrupt enable bit 1 : Interrupt enabled
6 AD converter/Serial
I/O3 transmit
0 : Interrupt disabled
1 : Interrupt enabled
interrupt enable bit
7
Fix this bit to 0 .
0
Fig. 2.5.15 Structure of Interrupt control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-93
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5.3 I2C-BUS overview
The I2C-BUS is a both directions serial bus connected with two signal lines; the SCL which transmits a
clock and the SDA which transmits data.
Each port of the 3804 group has an N-channel open-drain structure for output and a CMOS structure for
input. The devices connected with the I2C-BUS interface use an open drain, so that external pull-up
resistors are required. Accordingly, while any one of devices always outputs “L”, other devices cannot
output “H”.
Figure 2.5.16 shows the I2C-BUS connection structure.
SCL output
utput
SCL input
SCL input
SDA output
SDA output
SDA input
SDA input
SCL output
SCL input
SDA output
SDA input
Fig. 2.5.16 I2C-BUS connection structure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-94
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5.4 Communication format
Figure 2.5.17 shows an I2C-BUS communication format example.
The I2C-BUS consists of the following:
•START condition to indicate communication start
•Slave address and data to specify each device
•ACK to indicate acknowledgment of address and data
•STOP condition to indicate communication completion.
Bus busy term
Slave address
7 bits
Data
8 bits
Data
8 bits
S
R/W A
A
A P
SCL
SDA
0 to 7
Start
W ACK
AC
ACK Stop
Addresses 0 to 6
Data 0 to 7
Fig. 2.5.17 I2C-BUS communication format example
(1) START condition
When communication starts, the masteoutputs the START condition to the slave device. The
I2C-BUS defines that data can be cwhen a clock line is “L”. Accordingly, data change when
a clock line is “H” is treated as r START condition.
The data line change from “Hwhen a clock line is “H” is START condition.
(2) STOP condition
Just as in START conhe data line change from “L” to “H” when a clock line is “H” is STOP
condition.
The term from condition to STOP condition is called “Bus busy”. The master device is
inhibited from data transfer during that term.
The Bus bus can be judged by using the BB flag of I2C status register (bit 5 of address 001316).
(3) Slave address
The slave address is transmitted after START condition. This address consists of 7 bits and the 7-
th bit functions as the read/write (R/W) bit which indicates a data transmission method. The slave
devices connected with the same I2C-BUS must have their addresses, individually. It is because that
address is defined for the master to specify the transmitted/received slave device.
The read/write (R/W) bit indicates a data transmission direction; “L” means write from the master to
the slave, and “H” means read in.
(4) Data
The data has an 8-bit length. There are two cases depending on the read/write (R/W) bit of a slave
address; one is from the master to the slave and the other is from the slave to the master.
Rev.1.00 Jan 14, 2005
2-95
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
(5) ACK bit
The ACK bit clock is generated by the master. This is used for indication of acknowledgment on the
SDA line, the slave’s busy and the data end.
For example, the slave device makes the SDA line “L” for acknowledgment when confirming the slave
address following the START condition. The built-in I2C-BUS interface has the slave address automatic
judgment function and the ACK acknowledgment function. “L” is automatically output when the ACK
bit of I2C clock control register (bit 6 of address 001516) is “0” and an address data is received. When
the slave address and the address data do not correspond, “H” (NACK) is automatically output.
In case the slave device cannot receive owing to an interrupt process, performing operation or
others, the master can output STOP condition and complete data transfer by making the ACK data
of the slave address “H” for acknowledgment. Even in case the slave device cannot receive data
during data transferring, the communication can be interrupted by performing NACK acknowledgment
to the following data.
When the master is receiving the data from the slave, the master can notlave of completion
of data reception by performing NACK acknowledgment to the last daved from the slave.
(6) RESTART condition
The master can receive or transmit data without transmission ocondition while the master is
transmitting or receiving a data.
For example, after the master transmitted a data to the transmitting a slave address + R
(Read) following RESTART condition can make the fodata treat as a reception data.
Additionally, transmitting a slave address + W (Wriwing RESTART condition can make the
following data treat as a transmission data.
START condition
RESTART co
Master reception
1st-byte
Master reception
2nd-byte
Upper data
8 bits
S
Slave address R/W A
Dat
Slave address R/W A Lower data
A
A P
7 bits
7 bits
8 bits
“0”
“1”
Write
Read
NACK expression end of
master reception data
S: START condi
A: ACK bit
STOP condition
R/W: Read/Write bit
Master to slave
Slave to master
Sr: RESTtion
Fig. 2.5.18 RESTART condition of master reception
2.5.5 Synchronization and arbitration lost
(1) Synchronization
When a plural master exists on the I2C-BUS and the masters, which have different speed, are going
to simultaneously communicate; there is a rule to unify clocks so that a clock of each bit can be
output correctly.
Figure 2.5.19 shows a synchronized SCL line example. The SCL (A) and the SCL (B) are the master
devices having a different speed. The SCL is synchronized waveforms.
As shown by Figure 2.5.19, the SCL lines can be synchronized by the following method; the device
which first finishes “H” term makes the SCL line “L” and the device which last remains “L” makes the
SCL line “H”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-96
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ
SCL(A)
SCL(B)
SCL
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Fig. 2.5.19 SCL waveforms when synchronizing clocks
ꢀ After START condition, the masters, which have different speedneously start clock transmission.
ꢀ The SCL outputs “L” because (A) finished counting “H” then (B)’s “H” output counting is
interrupted and (B) starts counting “L” output.
ꢀ The (A) outputs “H” because (A) finished counting m; the SCL level does not become “H”
because (B) outputs “L”, and counting “H” term ot start but stop.
ꢀ (B) outputs “L” term.
ꢀ The SCL outputs “H” because (B) finisheng “L” term; then (B)’s “H” output counting is
started at the same time as (A).
ꢀ The SCL outputs “L” because (A) firsd counting “H” output; then (B)’s “H” output counting
is interrupted and (B) starts countoutput.
ꢀ The above are repeatedly perfo
(2) Clock synchronization durimunication
In the I2C-BUS, the slave s permitted to retain the SCL line “L” and become waiting status
for transmission from thr. By byte unit, for the reception preparation of the slave device, the
master can become status by making the SCL line “L”, which is after completion of byte
reception or the A
By bit unit, it is e to slow down a clock speed by retaining the clock line “L” for slave devices
having limiteare.
The 3804 grp can transmit data correctly without reduction of data bits toward waiting status
request from the slave device. It is because the synchronization circuit is included for the case when
retaining the SCL line “L” as an internal hardware.
After the last bit, including the ACK bit, of a transmission/reception data byte, the SCL line automatically
remains “L” and waiting status is generated until completion of an interrupt process or reception
preparation.
(3) Arbitration lost
A plural master exists on the same bus in the I2C-BUS and there are possibility to start communication
simultaneously. Even when the master devices having the same transmission frequency start
communication simultaneously, which device must transmit data correctly. Accordingly, there is the
definition to detect a communication confliction on the SDA line in the I2C-BUS.
The SDA line is output at the timing synchronized by the SCL, however, the synchronization among
the SDA signals is not performed.
Rev.1.00 Jan 14, 2005
2-97
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5.6 SMBUS communication usage example
This clause explains a SMBUS communication control example using the I2C-BUS. This is a control example
as the master device and the slave device in the Read Word protocol of SMBUS protocol.
The following is a communication example of the “Voltage () command” of the Smart battery data.
Communication specifications:
•Communication frequency = 100 kHz
•Slave address of itself, battery, = “0001011X
•Slave address of communication destination, host, = “0001000X
•Voltage () command = “0916
•Voltage value of acknowledgment = “2EE016” (12000 mV)
2
” (X means the read/write bit)
2
” (X means the read/write bit)
”
•The communication process is performed in the interrupt process. However, the main process performs
an occurrence of the first START condition and a slave address set.
•A communication buffer is established. Data transfer between the main process ainterrupt process
is performed through the communication buffer.
(1) Initial setting
Figure 2.5.20 shows an initial setting example using SMBUS coation.
Rev.1.00 Jan 14, 2005
2-98
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
I2C special mode control register (address 001716
)
b7
b0
0
0
0 0
0 0 0
S3D
0
Fix to “0”
ACK interrupt control : At communication completion
One-byte slave address compare mode
Fix to “0”
This setting can be omitted.
Fix to “0”
SCL pin low hold 2 flag set bit : Not used
SCL pin low hold set bit : Not set
STOP condition flag clear bit : Not used
I2C slave address register 0 (address 0FF716
)
b7
b0
0
0
1
0
0
1 1
0
S0D0
Set slave address value 001616
.
I2C clock control register (address 001516
b7
)
b0
S2
1
0
0
0
0
1 0
1
Set clock 100 kHz (XIN = 8MH
Standard clock mode
ACK is returned
ACK clock
I2C status register (address 001316
)
b0
b7
0
0
1
S1
ow hold bit: Fix to “1”
e receive mode
I2C START/STOP ontrol register (address 001616
)
b7
S2D
0
0
0 1
0
Set setup time, hold time to 27 cycles (6.75 µs: XIN = 8 MHz).
SCL/SDA interrupt: Falling edge active
SCL/SDA interrupt: SDA valid
Fix to “0”
I2C control register (address 001416
)
b7
b0
S1D
0
0
0 0 1 0 0
0
Set number of transmit/receive bits to “8”.
I2C-BUS interface: Enabled
Addressing format
7-bit addressing format
Fix to “0”
Set SMBUS input level.
Fig. 2.5.20 Initial setting example for SMBUS communication
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-99
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
(2) Communication example in master device
The master device follows the procedures ꢀ to ꢀ shown by Figure 2.5.21.
Additionally, the shaded area in the figure is a transmission data from the master device and the
white area is a transmission data from the slave device.
ꢀ Generating of START condition; Transmission of slave address + write bit
ꢀ Transmission of command
ꢀ Generating of RESTART condition; Transmission of slave address + read bit
ꢀ Reception of lower data
ꢀ Reception of upper data
ꢀ Generating of STOP condition
Figures 2.5.22 to 2.5.27 show the procedures ꢀ to ꢀ.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Upper data
8 bits
S
Slave address R/W A Command A Sr Slave address R/W A ta
A
A P
7 bits
8 bits
7 bits
8 bits
“0”
“1”
Write
Interrupt request Interrupt request
request Interrupt request Interrupt request
S: START condition
A: ACK bit
P: STOP condition
R/W: Read/Write bit
ster to slave
Slave to master
Sr: RESTART condition
Fig. 2.5.21 Read Word protocol comation as SMBUS master device
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-100
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Generating of START condition; Transmission of slave address + write bit
After confirming that other master devices do not use the bus, generate the START condition,
because the SMBUS is a multi-master.
Write “slave address + write bit” to the I2C data shift register (address 001116) before performing
to make the START condition generate. It is because the SCL of 1-byte unit is output, following
occurrence of the START condition.
If other master devices start communication until an occurrence of the START condition after
confirming the bus use, it cannot communicate correctly. However in this case, that situation does
not affect other master devices owing to detection of an arbitration lost or the START condition
duplication preventing function.
1
(A)←00010000
SEI (Note 1)
2
• Interrupts
1 (used)
BB (address 001316), bit5 ? (Note 2)
confirmation
0 (not used)
S0 (address 001116) ← (A)
• Slave address value write
S1 (address 001316) ←1
• START condition occurrence
• Interrupt enabled
CLI
Notes 1: In tple, the SEI instruction to disable interrupts need not be executed
bhis processing is going to be performed in the interrupt processing.
he START condition is generated out of the interrupt processing, execute
EI instruction to disable interrupts.
the branch bit instruction to confirm bus busy.
Fig. 2.5.22 Generating of START condition and transmission process of slave address + write bit
Rev.1.00 Jan 14, 2005
2-101
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Transmission of command
Confirm correct completion of communication at ꢀ before command transmission. When receiving
the STOP condition, a process not to transmit a command is required, because the internal I2C-
BUS generates an interrupt request also owing to the STOP condition transmitted to other devices.
After confirming correct completion of communication, write a command to the I2C data shift
register (address 001116).
In case the AL bit (bit 3 of address 001316) is “1”, check the slave address comparison flag (AAS
bit; bit 2 of address 001316) to judge whether the device given a right of master transmission owing
to an arbitration specifies itself as a slave address. When it is “1”, perform the slave reception;
when “0”, wait for a STOP condition occurrence caused by other devices and the communication
completion.
In case the AL bit is “0”, check the last received bit (LRB bit; bit 0 of address 001316). When it is
“1”, make the STOP condition generate and release the bus use, becae specified slave
device does not exist on the SMBUS.
2
1(error)
ment of bus hold
PIN (address 001316), bit 4 ?
0 (slave amitted)
1(detected)
1(NACK)
• Judgment of arbitration lost detection
AL (address 001316
etected)
• ACK confirmation
LRB (a16), bit 0 ?
0 (ACK)
• Command data write to I2C data shift register
s 001116) ← 00001001
2
End
STOP condition output
0 (address not corresponded)
AAS (address 001316), bit 2 ?
• Judgment of slave address comparison
1 (address corresponded)
Slave reception
Re-transmission preparation
Fig. 2.5.23 Transmission process of command
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-102
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Generating of RESTART condition; Transmission of slave address + read bit
Confirm correct completion of communication at ꢀ before generating the RESTART condition.
After confirming correct completion, generate the RESTART condition and perform the transmission
process of “slave address + read bit”. Note that procedure because that is different from ꢀ’s
process.
As the same reason as ꢀ, write “slave address + read bit” to the I2C data shift register (address
001116) before performing to make the START condition generate. However, when writing a slave
address to the I2C data shift register in this condition, a slave address is output at that time.
Consequently, the RESTART condition cannot be generated. Therefore, follow the slave reception
procedure before those processes.
In case the arbitration lost detecting flag (AL bit, bit 3 of address 001316) is “1”, return to the
process ꢀ, because other master devices will have priority to communicate.
When the last received bit (LRB bit; bit 0 of address 001316) is “1”, genere STOP condition
and make the bus release, because acknowledgment cannot be done oBUSY status of the
slave device specified on the SMBUS or other reasons.
3
1 (STOP condition)
PIN (address 001316), bit
0 (cansmission)
• Bus judgment during hold
1 (detected)
1 (NACK)
• Judgment of arbitration lost detection
AL (address 03 ?
(not detected)
Ls 001316), bit 0 ?
0 (ACK)
• ACK confirmation
ess 001316) ← 000000002 (Note 1)
• Slave receive mode set
• Slave address read out
• Interrupt disabled
(A) ← 00010001
SEI (Note 2)
2
S0 (address 001116) ← (A)
• Slave address value write
• RESTART condition occurrence
• Interrupt enabled
S1 (address 001316) ← 11110000
CLI (Note 2)
2
End
Re-transmission preparation
STOP condition output
Notes 1: Set to the receive mode while the PIN bit is “0”. Do not write “1” to the PIN bit.
2: In this example, the SEI instruction to disable interrupts need not be executed because this
processing is going to be performed in the interrupt processing.
When the START condition is generated out of the interrupt processing, execute the SEI
instruction to disable interrupts.
Fig. 2.5.24 Transmission process of RESTART condition and slave address + read bit
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-103
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Reception of lower data
Confirm correct completion of communication at ꢀ before receiving the lower data. After confirming
correct completion, clear the ACK bit (bit 6 of address 001516) to “0”, in which ACK is returned,
and set to the master receive mode. After that, write dummy data to the I2C data shift register
(address 001116).
When the MST bit (bit 7 of address 001316) is “0”, perform the error process explained as follows
and return to the process ꢀ.
When the last receive bit (LRB bit; bit 0 of address 001316) is “1”, generate the STOP condition
and make the bus release, because the slave device specified on the SMBUS does not exist.
4
1 (STOP condition)
PIN (address 001316), bit 4 ?
0 (transmission of RESTART
• Judgmeold
condition)
0 (slave)
MST (address 001316), bit 7 ?
ment of slave mode detection
• ACK confirmation
1 (master)
1 (NACK)
LRB (address 001316), bit
0
• “ACK clock is used” select and
“ACK is returned” set
S2 (address 0015101
2
2
S1 (addres10100000
2
• Master receive mode set
• Dummy data to I2C data shift register write
S0 (1116) ← 11111111
End
STOP condition output
1 (detected)
• Judgment of arbitration lost detection
AL (address 001316), bit 3 ?
0 (not detected)
Error processing
Re-transmission preparation
Fig. 2.5.25 Reception process of lower data
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-104
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Transmission of upper data
Confirm correct completion of communication at ꢀ before receiving the upper data. After confirming
correct completion, store the received data (lower data).
Set the ACK bit (bit 6 of address 001516) to “1”, in which ACK is not returned and write dummy
data to the I2C data shift register (address 001116).
When the MST bit (bit 7 of address 001316) is “0”, return to the process ꢀ, because other devices
have priority to communicate.
5
1 (STOP condition)
• Judgment of buld
PIN (address 001316), bit 4 ?
0 (lower data transmitted)
0 (slave)
MST (address 001316), bit 7 ?
• Jslave mode detection
1 (Master)
Receive data buffer ← S0 (address 001116
)
ceive data read and save
• “NACK is returned” set
S2 (address 001516) ←110001
• Dummy data to I2C data shift register write
S0 (address 001116) ←
1(detected)
• Judgment of arbitration lost detection
ddress 001316), bit 3 ?
0 (not detected)
Error processing
Re-transmission preparation
Fig. 2.5.26 Reception of upper data
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-105
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Generating of STOP condition
Confirm correct completion of communication at ꢀ before generating the STOP condition. After
confirming correct completion, store the received data (upper data).
Clear the ACK bit (bit 6 of address 001516) to “0”, in which ACK is returned, and generate the
STOP condition. The communication mode is set to the slave receive mode by the occurrence of
STOP condition.
When the MST bit (bit 7 of address 001316) is “0”, return to the process ꢀ, because other devices
have priority to communicate.
6
1 (STOP condition)
PIN (address 001316), bit 4 ?
0 (upper data transmitted)
• Judgmeld
1 (detected)
ent of arbitration lost detection
• Receive data read and save
AL (address 001316), bit 3 ?
0 (not detected)
Receive data buffer ← S0 (address 0
S2 (address 001516) ← 10
S1 (address 00131002
• Set “ACK is returned”
• STOP condition occurrence
1 (bus busy)
• Judgment of bus busy
BB (a316), bit5 ? (Note)
0 (bus free)
Re-transmission preparation
End
te: Use the branch bit instruction to check bus busy.
Also, execute the time out processing separately, if neccessary.
Fig. 2.5.27 Generating P condition
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-106
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
(3) Communication example in slave device
The slave device follows the procedures ꢀ to ꢀ shown by Figure 2.5.28.
The only difference from the master device’s communication is an occurrence of interrupt request
after detection of STOP condition.
ꢀ Reception of START condition; Transmission of ACK bit due to slave address correspondence
ꢀ Reception of command
ꢀ Reception of RESTART condition; Reception of slave address + read bit
ꢀ Transmission of lower data
ꢀ Transmission of upper data
ꢀ Reception of STOP condition
Figures 2.5.29 to 2.5.34 show the procedures ꢀ to ꢀ.
ꢀ
ꢀ
ꢀ
ꢀꢀ
S
Slave address R/W A Command A Sr Slave address R/W A Lo
A
Upper data A P
8 bits
7 bits
8 bits
7 bits
s
“0”
“1”
Write
Rea
Interrupt request
Interrupt request
Inuest Interrupt request Interrupt Interrupt request
request
S: START condition
A: ACK bit
P: STOP condition
R/W: Read/Write bit
to slave
ve to master
Sr: RESTART condition
Fig. 2.5.28 Communication example BUS slave device
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-107
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Reception of START condition; Transmission of ACK bit due to slave address correspondence
In the case of operation as the slave, all processes are performed in the interrupt after setting of
the slave reception in the main process, because an interrupt request does not occur until
correspondence of a slave address.
In the first interrupt, after confirming correspondence of the slave address, write dummy data to
receive a command into the I2C data shift register.
1
1 (STOP condition)
• Judgment of bus hold
PIN (address 001316), bit 4 ?
0 (slave address received)
0 (not corresponded)
AAS (address 001316), bit 2 ?
1 (corresponded)
• Judgmeaddress correspondence
data write to I2C data shift register
S0 (address 001116) ← 111111112
End
S1 (address 001316) ← 2
• Slave receive mode set
Errog
Fig. 2.5.29 Reception process oT condition and slave address
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-108
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Reception of command
Confirm correct completion of the command reception in the interrupt after receiving the command.
After confirming correct command from the host, write dummy data to the I2C data shift register
to wait for reception of the next slave address.
2
1 (STOP condition)
• Judgment of bus hold
PIN (address 001316), bit 4 ?
0 (command received)
• Receive data read and save
Receive data buffer ← S0 (address 001116
)
Judgment of receive command
• “ACK clock is ct and “ACK is returned” set
• Dumme to I2C data shift register
S2 (address 001516) ← 10000101
2
S0 (address 001116) ← 11111111
2
End
• Slave receive mode set
S1 (address 001316) ← 0001000
Error en
Fig. 2.5.30 Reception process oand
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-109
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Reception of RESTART condition and slave address
After receiving a slave address, prepare transmission data.
Judgment whether receiving data or transmitting is required, because the mode is automatically
switched between the receive mode and the transmit mode depending on the R/W bit of the
received slave address. Accordingly, judge whether read or write referring the slave address
comparison flag (AAS bit; bit 2 of address 001316).
3
1 (STOP condition)
• Judgment of bus hold
PIN (address 001316), bit 4 ?
0 (lower data received)
0 (not corresponded)
AAS (address 001316), bit 2 ?
1 (corresponded)
0 (received)
of transmit/receive mode
TRX (address 001316), bit 6 ?
1 (transmitted)
• Output lower data write to I2C data shift register
S0 (address 001116) ← lower data
End
Slave receing, etc.
nd
• Slave receive mode set
(address 001316) ← 00010000
2
Error end
Fig. 2.5.31 Reception process of RESTART condition and slave address
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-110
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Transmission of lower data
Before transmitting the upper data, restart to transmit the data at ꢀ and confirm correct completion
of transmission of the lower data set in the slave address reception interrupt.
After that, transmit the upper data.
4
1 (STOP condition)
• Judgment of bus hold
PIN (address 001316), bit 4 ?
0 (lower data transmission completed)
1(NACK)
• ACK confirmation
LRB (address 001316), bit 0 ?
0 (ACK)
• Output uprite to I2C data shift register
S0 (address 001116) ←Upper data
End
S1 (address 001316) ← 00010000
2
• Slave receive mode set
Error end
Fig. 2.5.32 Transmission process of data
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-111
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Transmission of upper data
Confirm correct completion of the upper data transmission. The master returns the NACK toward
the transmitted second-byte data, the upper data. Accordingly, confirm that the last receive bit
(LRB bit; bit 0 of address 001316) is “1”.
After that, write dummy data to the I2C data shift register and wait for the interrupt of STOP
condition.
5
1 (STOP condition)
PIN (address 001316), bit 4 ?
LRB (address 001316), bit 0 ?
• Judgment of bus hold
0 (upper data transmission completed)
0 (ACK)
• ACK confirm
1 (NACK)
• ta write to I2C data shift register
S0 (address 001116) ← 11111111
2
End
• Slave receive mode set
S1 (address 001316) ←
2
Note: Use the brtruction to check bus busy.
Fig. 2.5.33 Transmission s of upper data
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-112
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
ꢀ Reception of STOP condition
Confirm that the STOP condition is correctly output and the bus is released.
6
0 (address or data received)
PIN (address 001316), bit 4 ?
1 (STOP condition)
• Judgment of bus hold
• Slave recset
End processing
S1 (address 001316) ← 00010000
2
End
S1(address 001316) ← 00010000
• Slave receive mode set
Error end
Fig. 2.5.34 Reception of STOP condition
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-113
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5.7 Notes on multi-master I2C-BUS interface
(1) Read-modify-write instruction
Each register of the multi-master I2C-BUS interface has bits to change by hardware. The precautions
when the read-modify-write instruction such as SEB, CLB etc. is executed for each register of the
multi-master I2C-BUS interface are described below.
➀ I2C data shift register (S0: address 001116
)
When executing the read-modify-write instruction for this register during transfer, data may become
a value not intended.
➀ I2C slave address registers 0 to 2 (S0D0 to S0D2: addresses 0FF716 to 0FF916
)
When the read-modify-write instruction is executed for this register at detecting the STOP condition,
data may become a value not intended.
➀ Reason
It is because hardware changes the read/write bit (RWB) at detecting OP condition.
➀ I2C status register (S1: address 001316
)
Do not execute the read-modify-write instruction for this register e all bits of this register
are changed by hardware.
➀ I2C control register (S1D: address 001416
)
When the read-modify-write instruction is executed for this at detecting the START condition
or at completing the byte transfer, data may become not intended.
➀ Reason
Because hardware changes the bit counter (BC2).
➀ I2C clock control register (S2: address 00
The read-modify-write instruction can be efor this register.
➀ I2C START/STOP condition control reS2D: address 001616
The read-modify-write instruction can cuted for this register.
)
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-114
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
(2) START condition generating procedure using multi-master
ꢀ Procedure example (The necessary conditions of the generating procedure are described as the
following ꢀ to ꢀ).
LDA #SLADR
SEI
(Taking out of slave address value)
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
LDM #$F0, S1
CLI
:
:
BUSBUSY:
CLI
(Interrupt enabled)
:
:
ꢀ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirmbranch process.
ꢀ Use “STA, STX” or “STY” of the zero page addressing instructiriting the slave address
value to the I2C data shift register (S0: address 001116).
ꢀ Execute the branch instruction of above ꢀ and the store instf above ꢀ continuously shown
by the above procedure example.
ꢀ Disable interrupts during the following three process
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
(3) RESTART condition generating proceduaster
ꢀ Procedure example (The necessary cs of the generating procedure are described as the
following ꢀ to ꢀ). Execute the follrocedure when the PIN bit is “0”.
LDM #$00, S1
LDA #SLADR
SEI
slave receive mode)
ng out of slave address value)
terrupt disabled)
STA S0
LDM #$F0, S
(Writing of slave address value)
(Trigger of RESTART condition generating)
(Interrupt enabled)
CLI
:
:
ꢀ Select the seive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. The TRX bit
becomes the SDA pin is released.
ꢀ The SCis released by writing the slave address value to the I2C data shift register.
ꢀ Disable interrupts during the following two process steps:
• Writing of slave address value
• Trigger of RESTART condition generating
(4) Writing to I2C status register (S1: address 001316
)
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine cycle. Do not execute an instruction
to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it
may become the same as above.
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-115
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
(5) Writing to I2C clock control register (S2: address 001516
)
Do not write data into the I2C clock control register during transfer. If data is written during transfer,
the I2C clock generator is reset, so that data cannot be transferred normally.
(6) Switching of SCL/SDA interrupt pin polarity selection bit, SCL/SDA interrupt pin selection bit,
I2C-BUS interface enable bit
When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt
pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt
pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt.
(7) Process of after STOP condition generating in master mode
Do not write data in the I2C data shift register (S0) and the I2C status registeuntil the bus busy
flag BB becomes “0” after generating the STOP condition in the mast. It is because the
STOP condition waveform might not be normally generated. Reading tove registers does not
have the problem.
(8) ES0 bit switch
In standard clock mode when SSC = “00010
“1” if ES0 bit is set to “1” when SDA is “L”.
Countermeasure:
2
” or in high-sock mode, flag BB may switch to
Set ES0 to “1” when SDA is “H”.
Rev.1.00 Jan 14, 2004
REJ09B0212-0100Z
2-116
APPLICATION
3804 Group (Spec.H)
2.5 Multi-master I2C-BUS interface
2.5.8 Notes on programming for SMBUS interface
(1) Time out process
For a smart battery system, the time out process with a program is required so that the communication
can be completed even when communication is interrupted. It is because there is possibility of
extracting a battery from a PC.
The specifications are defined so that communication has been able to be completed within 25 ms
from START condition to STOP condition and within 10 ms from the ACK pulse to the ACK pulse of
each byte. Accordingly, the following two should be considered as count start conditions.
ꢀ SDA falling edge caused by SCL/SDA interrupt
This is the countermeasure for a communication interrupt in the middle of from START condition
to a slave address. However, the detection condition must be considered cause a interrupt is
also generated by communication from other masters to other slaves.
ꢀ SMBUS interrupt after receiving slave address
This is the countermeasure for when communication is interrupted feiving a slave address
until receiving a command.
(2) Low hold of communication line
The I2C-BUS interface conforms to the I2C-BUS Standard Stions. However, because the use
condition of SMBUS differs from the I2C-BUS’s, there ibility of occurrence of the following
problem.
ꢀ Low hold of SDA line caused by ACK pulse ge drop of communication line
When the SMBUS voltage slowly drops, that id by extracting a battery from equipment or
turning off a PC’s power or etc., it might be tly treated as the SCL pulse near the threshold
level voltage.
When the SDA is judged “L” in that conbecomes the general call and the ACK is transmitted.
However, when the SCL remains e ACK pulse, the SDA continuously remains “L” until
input of the next SCL pulse.
Countermeasure:
As explained before, stame out count at the falling of SDA line of START condition and
reset ES0 bit of the ister when the time out is satisfied (Note).
Note: Do not use -modify-write instruction at this time. Furthermore, when the ES0 bit is
set to “0”mes a general-purpose port ; so that the port must be set to input mode
or “H”.
Rev.1.00 Jan 14, 2004
2-117
REJ09B0212-0100Z
APPLICATION
2.6 PWM
3804 Group (Spec.H)
2.6 PWM
This paragraph explains the registers setting method and the notes relevant to the PWM.
2.6.1 Memory map
Address
002B16 PWM control register (PWMCON)
002C16 PWM prescaler (PREPWM)
PWM register (PWM)
002D16
Fig. 2.6.1 Memory map of registers relevant to PWM
2.6.2 Relevant registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control regisON: address 002B16
)
b
0
Pon
t
Functions
At reset R W
0
0 : PWM disabled
1 : PWM enabled
source
ection bit
0
0 : f(XIN
1 : f(XIN)/2
)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
3
4
5
6
7
0
0
0
0
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
0
Fig. 2.6.2 Structure of PWM control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-118
APPLICATION
2.6 PWM
3804 Group (Spec.H)
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler
(PREPWM: address 002C16
)
b
0
1
2
3
4
5
6
7
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Un
ined
ndefined
•Set the PWM period.
•The value set in this register is written to both
PWM prescaler pre-latch and PWM prescaler
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the count value
of the PWM prescaler latch is read out.
Fig. 2.6.3 Structure of PWM prescaler
PWM register
b7 b6 b5 b4 b3 b2 b1 b0
PWM registe
(PWM: add16
)
b
0
3
4
5
6
7
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
e PWM “H” level output interval.
value set in this register is written to both
WM register pre-latch and PWM register
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the contents of
the PWM register latch is read out.
Fig. 2.6.4 Structure of PWM register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-119
APPLICATION
2.6 PWM
3804 Group (Spec.H)
2.6.3 PWM output circuit application example
<Motor control>
Outline : The rotation speed of the motor is controlled by using PWM (pulse width modulation) output.
Figure 2.6.5 shows a connection diagram ; Figures 2.6.6 shows PWM output timing, and Figure 2.6.7
shows a setting of the related registers.
M
P56/PWM
D/A converter
Motor driver
3804 group
(Spec. H)
Fig. 2.6.5 Connection diagram
Specifications : • Motor is controlled by using the tput function of 8-bit resolution.
• Clock f(XIN) = 5 MHz
• “T”, PWM cycle : 102 µs
• “t”, “H” level width of out: 40 µs (Fixed speed)
ꢀ A motor speed can be cy modifying the “H” level width of output pulse.
t = 40 µs
utput
T = 102 µs
Fig. 2.6.6 PWM output timing
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-120
APPLICATION
2.6 PWM
3804 Group (Spec.H)
PWM control register (Address : 002B16
)
b7
b0
0 1
PWMCON
PWM output: Enabled (Note)
Count source: f(XIN
)
PWM prescaler (Address : 002C16
b7 b0
)
[Equation]
Set “T”, PWM cycle
n = 1
PREPWM
PWM
n
255 ꢀꢀ(n + 1)
T =
f(XIN
)
PWM register (Address : 002D16
b7 b0
)
quation]
Set “t”, “H” level width of PWM
m = 100
m
T ꢀꢀm
255
t =
Note:
The PWM output function has priority even wheresponding bit to P5 pin)
6
of Port P5 direction register is set to “0” (inpu
Fig. 2.6.7 Setting of relevant registers
<About PWM output>
1. Set the PWM function enable bit to “1” : The P56/PWused as the PWM pin.
The pulsing with “H” level pulse is output.
2. Set the PWM function enable bit to “0” : The Ppin is used as the port P56.
Thufixing the output level, take the following procedure:
(1) Write an output value to bit 6 of the poister.
(2) Write “010000002” to the port P5 diegister.
3. After data is set to the PWM prescahe PWM register, the PWM waveforms corresponding to updated
data will be output from the next e cycle.
output
Change PWM
output data
From the next repetitive cycle,
output modified data
Fig. 2.6.8 PWM output
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-121
APPLICATION
2.6 PWM
3804 Group (Spec.H)
By setting the related registers as shown by Figure 2.6.7, PWM waveforms are output to the externals.
This PWM output is integrated through the low pass filter, and that converted into DC signals is used
for control of the motor. Figure 2.6.9 shows control procedure.
• X : This bit is not used here.
Set it to “0” or “1” arbitrarily.
~
~
• “L” level output from P5
6
/PWM pin
P5 (Address : 000A16), bit6
0
P5D (Address : 000B16
)
X1XXXXXX
2
• PWM period setting
• “H” level width of PWM setting
• PWM count source selected, PWM outpu
1
100
XXXXXX01
PREPWM (Address : 002C16
PWM (Address : 002D16
PWMCON (Address : 002B16
)
)
)
2
~
~
Fig. 2.6.9 Control procedure
2.6.4 Notes on PWM
The PWM starts after the PWM enable bit is set to enab“L” level is output from the PWM pin.
The length of this “L“ level output is as follows:
n + 1
2 • f(XIN
(s)
(s)
(Count source selection bhere n is the value set in the prescaler)
(Count source selt = 1, where n is the value set in the prescaler)
)
n + 1
f(XIN
)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-122
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
2.7 A/D converter
This paragraph explains the registers setting method and the notes relevant to the A/D converter.
2.7.1 Memory map
Address
003416 AD/DA control register (ADCON)
003516 AD conversion register 1 (AD1)
003816 AD conversion register 2 (AD2)
003916 Interrupt source selection register (INTSEL)
003D16 Interrupt request register 2 (IREQ2)
003F16 Interrupt control register 2 (IC
Fig. 2.7.1 Memory map of registers relevant to A/D cr
2.7.2 Relevant registers
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
Arol register
address 003416
)
0
Name
Analog input pin
selection bits 1
Functions
At reset R W
0
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
0
1
2
3
4
5
6
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
or P0
or P0
or P0
or P0
or P0
or P0
or P0
0
1
2
3
4
5
6
/AN
/AN
/AN10
/AN11
/AN12
/AN13
/AN14
8
9
1
2
0
0
1 1 1: P67/AN7 or P07/AN15
0: Conversion in progress
1: Conversion completed
3
4
5
AD conversion
completion bit
1
0
0
0: AN
1: AN
0
8
to AN
to AN15 side
7 side
Analog input pin
selection bit 2
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0: DA
1: DA
1
1
output disabled
output enabled
DA
bit
1
output enable
0
0
6
7
0: DA
1: DA
2
2
output disabled
output enabled
DA
bit
2
output enable
Fig. 2.7.2 Structure of AD/DA control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-123
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
AD conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 1
(AD1: address 003516
)
b
Functions
At reset R W
Undefined
0
1
2
3
4
5
6
7
This is A/D conversion result stored bits. This is
read exclusive register.
Undefined
Undefined
8-bit read
b7
b0
Undefined
b9b8b7b6b5b4b3b2
10-bit read
Undefined
Undefined
b7
b0
Unde
b7b6b5b4b3b2b1b0
U
Fig. 2.7.3 Structure of AD conversion register 1
AD conversion register 2
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 2
(AD2: address 003816)
b
tions
At reset R W
Undefined
This is A/D n result stored bits. This is
read exclster.
0
10-bit read
b0
Undefined
1
b9b8
0
s arranged for these bits. These are
isabled bits. When these bits are read out,
contents are “0”.
2
7
0
0
0
0
0
Conversion mode
selection bit
0: 10-bit A/D mode
1: 8-bit A/D mode
Fig. 2.7.4 StructAD conversion register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-124
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register
(INTSEL: address 003916
)
b
0
Name
Functions
interrupt
At reset R W
0
INT
0
/Timer Z
0: INT
0
interrupt source
selection bit (*1)
1: Timer Z interrupt
0: Serial I/O2 interrupt
1: Timer Z interrupt
0
Serial I/O2/Timer Z
interrupt source
selection bit (*1)
1
2
Serial I/O1 transmit/
SCL, SDA interrupt
source selection bit
(*2)
0: Serial I/O1 transmit
interrupt
1: SCL, SDA interrupt
0
0
3
4
0: CNTR
1: SCL, SDA inter
0
interrupt
CNTR0/SCL, SDA
interrupt source
selection bit (*2)
0: INT
1: CNTR
4
interr
INT /CNTR2
4
interrupt source
selection bit
/I2C interrupt
0
0
0: IN
pt
5 INT
source selection bit
2
1upt
R interrupt
rial I/O3 receive
interrupt
1
CNTR /Serial I/O3
receive interrupt
1
6
source selecti
0
7 AD convert
I/O3 tran
0: A/D converter interrupt
1: Serial I/O3 transmit
interrupt
interru
sele
*1: ite 1 to these bits simultaneously.
*write 1 to these bits simultaneously.
Fig. 2.7.5 Structure of Interrurce selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-125
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 2
(IREQ2 : address 003D16
)
b
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✽
0
CNTR
0/SCL, SDA
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
✽
0
1 CNTR
/Serial I/O3
1
receive interrupt
request bit
Serial I/O2/Timer Z 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
✽
✽
✽
✽
✽
0
0
0
2
3
4
INT
request bit
INT interrupt
request bit
2
/I2C interrupt
0 : No interrupt request issued
1 : Interrupt request issued
3
0 : No interrupt request issue
1 : Interrupt request iss
0 : No interrupt reques
1 : Interrupt reque
5 INT
/CNTR
4
2
interrupt request bit
AD converter/Serial
I/O3 transmit
interrupt request bit
0 : No interrupt ued
1 : Interrupt sued
6
0
7
Nothing is arranged for this is a write
disabled bit. When this bout, the
contents are 0 .
✽: 0 can be set be, but 1 cannot be set.
Fig. 2.7.6 Structure of Interrupt request regi
Interrupt control registe
b7 b6 b5 b4 b3 b2 b1 b0
pt control register 2
0
ON2 : address 003F16
)
b
0
Name
Functions
At reset R W
0
CNTR
interrupt enable bit
CNTR / Serial I/O3
0
/SCL, SDA
0 : Interrupt disabled
1 : Interrupt enabled
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
receive interrupt
enable bit
Serial I/O2/ Timer Z
interrupt enable bit
0
0
0
0
0
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
INT
enable bit
INT interrupt
enable bit
2
/I2C interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
3
INT /CNTR2
4
0 : Interrupt disabled
1 : Interrupt enabled
interrupt enable bit
AD converter/Serial
I/O3 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
7
Fix this bit to “0”.
0
Fig. 2.7.7 Structure of Interrupt control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-126
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
2.7.3 A/D converter application examples
(1) Conversion of analog input voltage 1
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.7.8 shows a connection diagram, and Figure 2.7.9 shows the relevant registers setting.
P60/AN
0
Sensor
3804 Group
(Spec. H)
Fig. 2.7.8 Connection diagram
Specifications : •The analog input voltage input from r is converted to digital values.
•P6 /AN pin is used as an analog n.
0
0
•10-bit A/D mode
AD/DA control register (addres
b7
b0
ADCON
0 0 0 0
Analog input pin : P60/AN0 selected
A/D conversion start
Analog input pin : AN0–AN7 selected
rsion register 2 (address 003816
)
b0
A result of A/D conversion is stored (read-only) (Note).
10-bit A/D mode
AD conversion register 1 (address 003516
)
b7 b0
(Read-only)
AD1
A result of A/D conversion is stored (Note).
Note: After bit 3 of AD/DA control register (ADCON) is set to “1”, read out that contents.
When reading 10-bit data, read address 003816 before address 003516
.
When reading 10-bit data, bits 2 to 6 of address 003816 become “0”.
Fig. 2.7.9 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-127
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.7.9. Figure 2.7.10 shows the control procedure for 10-bit A/D
mode.
ꢀ X: This bit is not used here. Set it to “0” or “1” arbitrarily.
AD2 (address 003816
)
•10-bit A/D mode selected
0XXXXXXX
2
•P60/AN0 pin selected as analog input pin
•A/D conversion start
ADCON (address 003416
)
XX000000
2
0
•Judgment of A/D conversion compl
ADCON (address 003416), bit3 ?
1
Read out AD2 (address 003816
)
•Read out of high-ordb8) of conversion result
•Read out er digit (b7 – b0) of conversion result
Read out AD1 (address 003516
)
Fig. 2.7.10 Control procedure (10-bit A/D m
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-128
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
(2) Conversion of analog input voltage 2
Outline : The analog input voltage input from a sensor is converted to digital values.
Figure 2.7.11 shows a connection diagram, and Figure 2.7.12 shows the relevant registers setting.
P60/AN
0
Sensor
3804 Group
(Spec. H)
Fig. 2.7.11 Connection diagram
Specifications : •The analog input voltage input from a s converted to digital values.
•P6 /AN pin is used as an analog in
0
0
•8-bit A/D mode
AD/DA control register (addres
b7
b0
ADCON
0 0 0 0
0
Analog input pin : P60/AN0 selected
A/D conversion start
Analog input pin : AN0–AN7 selected
sion register 2 (address 003816
)
b0
AD1
8-bit A/D mode
AD conversion register 1 (address 003516
b7 b0
)
(Read-only)
A result of A/D conversion is stored (Note).
Note: After bit 3 of AD/DA control register (ADCON) is set to “1”, read out that contents.
When reading 8-bit data, read address 003516 only.
Fig. 2.7.12 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-129
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
An analog input signal from a sensor is converted to the digital value according to the relevant
registers setting shown by Figure 2.7.12. Figure 2.7.13 shows the control procedure for 8-bit A/D
mode.
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
AD2 (address 003816
)
1XXXXXXX
2
•8-bit A/D mode selected
•P60/AN0 pin selected as analog input pin
•A/D conversion start
ADCON (address 003416
)
XX000000
2
0
•Judgment of A/D conversion
•Read out of cosult
ADCON (address 003416), bit3 ?
1
Read out AD1 (address 003516
)
Fig. 2.7.13 Control procedure (8-bit A/D mode)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-130
APPLICATION
3804 Group (Spec.H)
2.7 A/D converter
2.7.4 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog input low, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be sure to verify the operation of application products on the
user side.
ꢀ Reason
An analog input pin includes the capacitor for analog voltage comparison. Accordingly, when
signals from signal source with high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion precision to be worse.
(2) A/D converter power source pin
The AVSS pin is A/D converter power source pins. Regardless of using the Aonversion function
or not, connect it as following :
• AVSS : Connect to the VSS line
ꢀ Reason
If the AVSS pin is opened, the microcomputer may have a fecause of noise or others.
(3) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following an A/D conversion.
• f(XIN) is 500 kHz or more
• Do not execute the STP instruction
(4) Difference between at 8-bit reading it A/D mode and at 8-bit A/D mode
At 8-bit reading in the 10-bit A/D mo2 LSB” correction is not performed to the A/D conversion
result.
In the 8-bit A/D mode, the A/D ion characteristics is the same as 3802 group’s characteristics
because “–1/2 LSB” correcterformed.
Rev.1.00 Jan 14, 2005
2-131
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
2.8 D/A Converter
This paragraph explains the registers setting method and the notes relevant to the D/A converter.
2.8.1 Memory map
000716 Port P3 direction register (P3D)
003416 AD/DA control register (ADCON)
003616 DA1 conversion register (DA1)
003716 DA2 conversion register (DA2)
Fig. 2.8.1 Memory map of registers relevant to D/A rter
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-132
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
2.8.2 Relevant registers
Port P3 direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port P3 direction register
(P3D: address 000716
)
b
0
Name
Port P3 direction
register
Functions
0 : Port P30 input mode
1 : Port P30 output mode
At reset R W
0
0
0
0
0
0
0 : Port P31 input mode
1 : Port P31 output mode
1
2
3
4
5
6
7
0 : Port P32 input mode
1 : Port P32 output mode
0 : Port P33 input mode
1 : Port P33 output mode
0 : Port P34 input mode
1 : Port P34 output m
0 : Port P35 input
1 : Port P35 out
0 : Port P36 e
1 : Port Pmode
0 : Port mode
1 : Putput mode
Fig. 2.8.2 Structure of Port P5 direction register
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
ADregister
(ddress 003416
)
Name
Analog input pin
selection bits 1
Functions
At reset R W
0
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
0
1
2
3
4
5
6
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
or P0
or P0
or P0
or P0
or P0
or P0
or P0
0
1
2
3
4
5
6
/AN
/AN
/AN10
/AN11
/AN12
/AN13
/AN14
8
9
1
2
0
0
1 1 1: P67/AN7 or P07/AN15
0: Conversion in progress
1: Conversion completed
3
4
5
AD conversion
completion bit
1
0
0
0: AN
1: AN
0
8
to AN
to AN15 side
7 side
Analog input pin
selection bit 2
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0: DA
1: DA
1
1
output disabled
output enabled
DA
bit
1
output enable
0
0
6
7
0: DA
1: DA
2
2
output disabled
output enabled
DA
bit
2
output enable
Fig. 2.8.3 Structure of AD/DA control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-133
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
DAi conversion register
b7 b6 b5 b4 b3 b2 b1 b0
DAi conversion register (i = 1, 2)
(DAi: addresses 003616, 003716
)
b
Functions
At reset R W
0
0
0
1
2
3
This is D/A output value stored bits. This is write
exclusive register.
0
4
5
6
7
0
0
Fig. 2.8.4 Structure of DAi converter register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-134
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
2.8.3 D/A converter application example
(1) Speaker output volume modulation
Outline: The volume of a speaker output is modulated by using D/A converter.
Specifications: •Timer X modulates the period of sound for the pitch interval, so that a fixed pitch
(“la”: approx. 440 Hz) can be output. Modulating the amplitude with the D/A output
value controls the volume.
•Use f(XIN) = 6 MHz.
•Use DA1 (P3
0
/DA pin) as D/A converter.
1
Figure 2.8.5 shows a peripheral circuit example and Figure 2.8.6 shows a speaker output example.
Figure 2.8.7 shows the relevant registers setting.
3804 Group (Spec. H)
Amplification
+
circuit
P30
/DA1
Po
a
Fig. 2.8.5 Peripheral circuit e
Modulation of vol
(amplitude is s
by D/A1 output)
F
VSS
Timer X
interrupt
Timer X
interrupt
Timer X
interrupt
Timer X
interrupt
Timer X
interrupt
Timer X
interrupt
Modulation of pitch interval: 440 Hz
(Cycle is set by timer X)
Fig. 2.8.6 Speaker output example
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-135
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
b7
b0
0
Port P3 direction register (P3D) (address 000716)
P30/DA1: Input mode
b7
b0
1
AD/DA control register (ADCON) (address 003416)
DA1 output enabled
b7
b0
Timer XY mode register (TM) (address 002316)
0 0
1
Timer X count: Stop
Timer mode
b7
b0
b0
b0
0 0 1 1
Timer 12, X count source serection register (T12XCSS) 000E16)
Timer X count source: f(XIN)/16
b7
2 – 1
Prescaler X (PREX) (address 002416)
Set “division ratio –1”
b7
b7
b7
D616 – 1
Timer X (TX) (address 0
Set “division ratio –
b0
b0
0
1
Interrupt egister 1 (IREQ1) (address 003C16)
Trupt request
errupt control register 1 (ICON1) (address 003E16)
Timer X interrupt: Enabled
b7
DA1 conversion register (DA1) (address 003616)
Set conversion value (n)
VREF × n
Analog voltage V =
(n=0 to 255)
256
b7
b0
Timer XY mode register (TM) (address 002316 )
Timer X count: Start
0 0
0
Fig. 2.8.7 Relevant registers setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-136
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
When the registers are set as shown in Figure 2.8.7, the speaker output volume is modulated by the
D/A output value. Figure 2.8.8 shows the control procedure.
RESET
ꢀ x: This bit is not used here. Set it to “0” or “1” arbitrarily.
Initialization
SEI
CLT (Note 1)
CLD (Note 2)
•All interrupts disabled
•Timer X interrupt disabled
•Set port P30 to input mode
•DA1 output enabled
•Timer Y: Timer mode, Timer X count: Stop
•Timer X count source: f(XIN)/16
•Set “division ratio – 1” to Prescaler X
•Set “division ratio – 1” to Timer X
(address 003E16), bit4
0
0
ICON1
P3D
ADCON
TM
T12XCSS
PREX
TX
(address 000716), bit0
(address 003416)
(address 002316)
(address 000E16)
(address 002416)
(address 002516)
X1XXXXXX2
XX001XXX2
0011XXXX2
2 – 1
D616 – 1
1
WORK flag (Note 3)
(address 003C16), bit4
•Timer X interrupt request bit clea
•Timer X interrupt: Enabled
•D/A converter start
•All interrupts enabled
•Timer X count start
0
1
IREQ1
ICON1
DA1
CLI
TM
(address 003E16), bit4
(address 003616)
Set output value (volume)
(address 002316)
Main processing
XX000XXX2
Notes 1: When x X mode flag
2: Wecimal mode flag
3: flag is a user flag for work. When this flag is “1
e other than Vss is output from the DA output pin.
this flag is “0”, Vss is output from the DA output pin.
Timer X interrupt process routine
Push registers to stac
•Push registers used in interrupt process routine
“0”
Value of ?
”
Set valuss to DA1 conversion
register.
Set value of Vss to DA1 conversion register.
Set “1” to WORK flag.
Set “0” to WORK flag.
Pop registers
RTI
•Pop registers pushed to stack
ꢀ Decide an D/A value from several times of D/A conversion results.
Fig. 2.8.8 Control procedure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-137
APPLICATION
3804 Group (Spec.H)
2.8 D/A converter
2.8.4 Notes on D/A converter
(1) Vcc when using D/A converter
The D/A converter accuracy when Vcc is 4.0 V or less differs from that of when Vcc is 4.0 V or more.
When using the D/A converter, we recommend using a Vcc of 4.0 V or more.
(2) DAi conversion register when not using D/A converter
When a D/A converter is not used, set all values of the DAi conversion registers (i = 1, 2) to “0016”.
The initial value after reset is “0016”.
Rev.1.00 Jan 14, 2005
2-138
REJ09B0212-0100Z
APPLICATION
3804 Group (Spec.H)
2.9 Watchdog timer
2.9 Watchdog timer
This paragraph explains the registers setting method and the notes relevant to the watchdog timer.
2.9.1 Memory map
Address
001E16 Watchdog timer control register (WDTCON)
CPU mode register (CPUM)
003B16
Fig. 2.9.1 Memory map of registers relevant to watchdog ti
2.9.2 Relevant registers
Watchdog timer control regi
b7 b6 b5 b4 b3 b2 b1 b0
Wer control register
: address 001E16)
0
1
2
3
4
5
6
Name
Watchdog timer H
(for read-out of high-order 6 bit)
Functions
At reset R W
1
1
1
1
1
1
0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
STP instruction
disable bit
0: STP instruction enabled
1: STP instruction disabled
7
0
Watchdog timer H 0: Watchdog timer L
count source selection
bit
underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 2.9.2 Structure of Watchdog timer control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-139
APPLICATION
3804 Group (Spec.H)
2.9 Watchdog timer
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
1
CPU mode register
(CPUM: address 003B16
)
b
0
Name
Functions
At reset R W
b1 b0
0
Processor mode
bits
00 : Single-chip mode
01 :
1
2
10 :
11 :
0 : 0 page
1 : 1 page
Not available
0
Stack page
selection bit
0
Fix this bit to “1”.
3
4
Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT os
function
Main clock (XIN
-
0: Oscillati
1: Stopp
b7 b6
0
1
5
6
XOUT) stop bit
Main clock division
ratio selection bits
0 0: 2
peed mode)
XIN)/8
middle-speed mode)
: φ=f(XCIN)/2
0
7
(low-speed mode)
1 1: Not available
Fig. 2.9.3 Structure of CPU mode r
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-140
APPLICATION
3804 Group (Spec.H)
2.9 Watchdog timer
2.9.3 Watchdog timer application examples
(1) Detection of program runaway
Outline: If program runaway occurs, let the microcomputer reset, using the internal timer for detection
of program runaway.
Specifications: •High-speed mode is used as a main clock division ratio.
•An underflow signal of the watchdog timer L is supplied as the count source of
watchdog timer H.
•1 cycle of main routine is 65.536 ms or less.
•Before the watchdog timer H underflows, “0” is set into bit 7 of the watchdog timer
control register at every cycle in a main routine.
•An underflow of watchdog timer H is judged to be program runaway, and the
microcomputer is returned to the reset status.
Figure 2.9.4 shows a watchdog timer connection and division ratio segure 2.9.5 shows the
relevant registers setting; Figure 2.9.6 shows the control procedure
Fixed
1/16
Watchdog timer L Watchdog
1/256 1/25
f(XIN) = 16 MHz
Reset
circuit
Internal reset
RESET
STP instruction disable
STP inst
Fig. 2.9.4 Watchdog timection and division ratio setting
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-141
APPLICATION
3804 Group (Spec.H)
2.9 Watchdog timer
CPU mode register (address 003B16
)
b7
b0
1
0
0
0
0
CPUM
0
Processor mode: Single-chip mode
Fix to “1”
Main clock (XIN-XOUT): Operating
Main clock division ratio: f(XIN)/2 (high-speed mode)
Watchdog timer control register (address 001E16
)
b7
b0
WDTCON
0
0
Watchdog timer H (for read-out of high-order
Enable STP instruction
Watchdog timer H count source: WatcL underflow
Fig. 2.9.5 Relevant registers setting
RESET
Initialization
All interrupts disabled
SEI
CLT
•Processor mode: Single-chip mode
•Main clock f(XIN): Operating
CLD
CPUM (address 003B16)
002
•High-speed mode selected as main clock division ratio
:
:
•Interrupts enabled
CLI
WDTCOs 001E16)
•Watchdog timer L underflow selected as Watchdog
timer H count source
000XXXXX2
•STP instruction enabled
rocessing
:
Fig. 2.9.6 Control procedure
2.9.4 Notes on watchdog timer
ꢀMake sure that the watchdog timer H does not underflow while waiting Stop release, because the
watchdog timer keeps counting during that term.
ꢀWhen the STP instruction disable bit has been set to “1”, it is impossible to switch it to “0” by a program.
Rev.1.00 Jan 14, 2005
2-142
REJ09B0212-0100Z
APPLICATION
2.10 Reset
3804 Group (Spec.H)
2.10 Reset
2.10.1 Connection example of reset IC
V
CC
1
Power source
5
Output
M62022L
RESET
Delay capacity
4
GND
3
0.1 µF
VSS
3804 Group H)
Fig. 2.10.1 Example of poweron reset circuit
Figure 2.10.2 shows the system example which switches tAM backup mode by detecting a drop of
the system power source voltage with the INT interrup
System power
source voltage
+5 V
VCC
7
VCC1
5
RESET
RESET
2
1
3
6
INT
VSS
INT
VCC2
V1
Cd
3804 Group
(Spec. H)
GND
4
M62009L,M62009P,M62009FP
Fig. 2.10.2 RAM backup system
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-143
APPLICATION
2.10 Reset
3804 Group (Spec.H)
2.10.2 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect a ceramic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more capacitor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connected to a capacitor as short as possible.
• Be sure to verify the operation of application products on the user side.
ꢀ Reason
If the several nanosecond or several ten nanosecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-144
APPLICATION
3804 Group (Spec.H)
2.11 Clock generating circuit
2.11 Clock generating circuit
This paragraph explains how to set the registers relevant to the clock generating circuit and describes an
application example.
2.11.1 Relevant registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPU mode register
(CPUM: address 003B16
1
)
b
0
Name
Functions
At W
b1 b0
Processor mode
bits
00 : Single-chip mode
01 : Not available
10 : Not available
11 : Not available
0 : 0 page
1
2
0
0
Stack page
selection bit
1 : 1 page
1
0
Fix this bit to “1”.
3
4
Port Xc switch bit
0: I/O on
(stopped)
1OUT oscillation
on
Main clock (XIN
-
scillating
Stopped
b7 b6
0
1
5
6
XOUT) stop bit
Main clock
ratio sel
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
0
7
(low-speed mode)
1 1: Not available
Fig. 2.11.1 Struf CPU mode register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-145
APPLICATION
3804 Group (Spec.H)
2.11 Clock generating circuit
2.11.2 Clock generating circuit application example
(1) Status transition during power failure
Outline: The clock counts up every second by using the timer interrupt during a power failure.
Input port
Power failure detection signal
(Note)
3804 Group (Spec. H)
Note: A signal is detected when input to input port, interrupt
input pin, or analog input pin.
Fig. 2.11.2 Connection diagram
Specifications: •Reducing power dissipation as low as possible aintaining clock function
•Clock: f(XIN) = 8 MHz, f(XCIN) = 32.768 kHz
•Port processing
Input port: Fixed to “H” or “L” level ex.
Output port: Fixed to output level thanot cause current flow to the external.
(Example) Fix to “HLED circuit that turns on at “L” output
level.
I/O port: Input port → Fixeor “L” level externally.
Output port → of data that does not consume current
V
REF pin: Terminate Aersion operation
Stop VREF dissipation by setting value of DAi conversion register
to “00
Figure 2.11.3 shows the status on diagram during power failure and Figure 2.11.4 shows the
setting of relevant registers
Rased
Power failure detected
X
IN
XCIN
Middle-speed
mode
Low-speed mode
High-speed mode
Internal system clock
After detection, change internal system clock to
low-speed mode and stop oscillating XIN-XOUT
Change internal system
clock to high-speed mode
XCIN-XCOUT oscillation function selected
Fig. 2.11.3 Status transition diagram during power failure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-146
APPLICATION
3804 Group (Spec.H)
2.11 Clock generating circuit
b7
b0
0 0 0 0 1
0 0
CPU mode register (CPUM) (address 003B16
)
CPUM
Main clock: High-speed mode (f(XIN)/2) (Note 1)
b7
b0
0 0 0 1 1
(Note 2)
0 0 CPU mode register (CPUM) (address 003B16
)
)
CPUM
CPUM
Port X
C
: XCIN–XCOUT oscillation function
b7
b0
1 0 0 1 1
0 0 CPU mode register (CPUM) (address 003B16
Internal system clock: Low-speed mode (f(XC
b7
b0
1 0 1 1 1
0 0 CPU mode register (CPUM) 003B16
)
CPUM
Main clock f(XIN): Stopp
Notes 1: This setting is necessary onlcting the high-speed mode.
2: When selecting the middode, bit 6 is “1”.
Fig. 2.11.4 Setting of relevant registers
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-147
APPLICATION
3804 Group (Spec.H)
2.11 Clock generating circuit
Control procedure: To prepare for a power failure, set the relevant registers in the order shown
below.
ꢀX: This bit is not used here. Set it to “0” or “1” arbitrarily.
RESET
Initialization
CPUM (address 003B16), bit7, bit 6
CPUM (address 003B16), bit 4
0, 0
1
When selecting main clock f(XIN)/2 (high-speed mode)
Port X : XCIN-XCOUT oscillation function
C
N
Detect power failure ?
Y
Internal ock: f(XCIN)/2 (low-speed mode)
Main IN) oscillation stopped
CPUM (address 003B16), bit7, bit 6
CPUM (address 003B16), bit5
1, 0 (Note)
1 (Note)
t power failure, clock count is performed during
timer interrupt processing (every second).
Set timer interrupt to occurs every second.
Execute WIT instruction.
N
Return condition from ure
complet
Return g from power failure
Note: Do not switch simultaneously.
Fig. 2.11.5 Control procedure
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-148
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
2.12 Standby function
The 3804 group (Spec. H) is provided with standby functions to stop the CPU by software and put the CPU
into the low-power operation.
The following two types of standby functions are available.
•Stop mode using STP instruction
•Wait mode using WIT instruction
2.12.1 Stop mode
The stop mode is set by executing the STP instruction. In the stop mode, the oscillation of both clocks (XIN
–
X
OUT, XCIN–XCOUT) stop and the internal clock φ stops at the “H” level. The CPU stops and peripheral units
stop operating. As a result, power dissipation is reduced.
(1) State in stop mode
Table 2.12.1 shows the state in the stop mode.
Table 2.12.1 State in stop mode
Item
State imode
Stopped.
Oscillation
CPU
Stopped.
Stopped at “H” le
Internal clock φ
I/O ports P0–P6
Timer
Retains the ste STP instruction execution.
Stopped. (T, 2, X, Y, Z)
HoweverX, Y, Z can be operated in the event counter
mode
St
PWM
d.
Watchdog timer
pped.
Serial I/O1, Serial I/O2, Serial I/O3
However, these can be operated only when an external clock
is selected.
I2C-BUS interface
A/D converter
D/A converter
Stopped.
Stopped.
Retains output voltage.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-149
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
(2) Release of stop mode
The stop mode is released by a reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
ꢀRestoration by reset input
The stop mode is released by holding the RESET pin to the “L” input level during the stop mode.
Oscillation is started when all ports are in the input state and the stop mode of the main clock (XIN
OUT) is released.
-
X
Oscillation is unstable when restarted. For this reason, time for stabilizing of oscillation (oscillation
stabilizing time) is required. The input of the RESET pin should be held at the “L” level until oscillation
stabilizes.
When the RESET pin is held at the “L” level for 16 cycles or more of XIN aftthe oscillation has
stabilized, the microcomputer will go to the reset state. After the input levhe RESET pin is
returned to “H”, the reset state is released in approximately 10.5 to 18.of the XIN input.
Figure 2.12.1 shows the oscillation stabilizing time at restoration by rut.
At release of the stop mode by reset input, the internal RAM retacontents previous to the
reset. However, the previous contents of the CPU register and e not retained.
For more details concerning reset, refer to “2.10 Reset”.
Oscilla
16 cycles or
stabilimore of XIN
Stop mode
Operating mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
RESET
XIN
(Note)
e Stop instruction
e: Some cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.12.1 Oscillation stabilizing time at restoration by reset input
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-150
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
ꢀRestoration by interrupt request
The occurrence of an interrupt request in the stop mode releases the stop mode. As a result,
oscillation is resumed. The interrupts available for restoration are:
•INT
0
–INT
4
•CNTR
0
, CNTR
1
, CNTR
2
•Serial I/O (1, 2, 3) using an external clock
•Timer X, Y, Z using an external event count
•SCL/SDA
However, when using any of these interrupt requests for restoration from the stop mode, in order to
enable the selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
ꢀ Interrupt disable flag I = “0” (interrupt enabled)
ꢀ Timer 1 interrupt enable bit = “0” (interrupt disabled)
ꢀ Interrupt request bit of interrupt source to be used for restoration = interrupt request
issued)
ꢀ Interrupt enable bit of interrupt source to be used for restoration interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts
Oscillation is unstable when restarted. For this reason, tstabilizing of oscillation (oscillation
stabilizing time) is required. For restoration by an intequest, waiting time prior to supplying
internal clock φ to the CPU is automatically generatPrescaler 12 and Timer 1ꢀ1. This waiting
time is reserved as the oscillation stabilizing time system clock side. The supply of internal
clock φ to the CPU is started at the Timer 1 ow.
Figure 2.12.2 shows an execution sequample at restoration by the occurrence of an INT
interrupt request.
0
ꢀ1: If the STP instruction is exehen the oscillation stabilizing time set after STP instruction
released bit is “0”, “FF16” 16” are automatically set in the Prescaler 12 counter/latch and
Timer 1 counter/latch, vely. When the oscillation stabilizing time set after STP instruction
released bit is “1”, ns automatically set to either Prescaler 12 or Timer 1. For this reason,
any suitable value set to Prescaler 12 and Timer 1 for the oscillation stabilizing time.
ꢀ2: Immediately aoscillation is started, the count source is supplied to the prescaler 12 so
that a counion is started.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-151
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
ꢀWhen restoring microcomputer from stop mode by INT
0
interrupt
(oscillation stabilizing time set after STP instruction released bit = “0”, rising edge selected)
Stop mode
Oscillation stabilizing time
X
IN or XCIN
X
IN; “H”
(System clock)
X
CIN; in high-impedance state
INT pin
0
512 counts
“FF16
”
Prescaler 12 counter
Timer 1 counter
“0116
”
INT
0
interrupt request bit
Peripheral device
CPU
Operating
Operating
O
Stopped
Stopped
Operating
Execute STP INT
0
interrupt signa
512 counts down by
prescaler 12
Start supplying internal
clock φ to CPU
instruction
input (INT interr
0
request occur
Oscillation
Prescalet start
Accept INT
0
interrupt
request
Note: The count source set at Stion execution is connected as the prescaler 12 count source.
Fig. 2.12.2 Execution sequence e at restoration by occurrence of INT interrupt request
0
(3) Notes on using stop
ꢀRegister setting
Since values oescaler 12 and Timer 1 are automatically reloaded when returning from the
stop mode, m again, respectively. (When the oscillation stabilizing time set after STP
instructiosed bit is “0”)
ꢀClock restoration
After restoration from the stop mode to the normal mode by an interrupt request, the contents of
the CPU mode register previous to the STP instruction execution are retained. Accordingly, if both
main clock and sub clock were oscillating before execution of the STP instruction, the oscillation
of both clocks is resumed at restoration.
In the above case, when the main clock side is set as a system clock, the oscillation stabilizing
time until the timer 1 underflow is reserved at restoration from the stop mode.
When the oscillation stabilizing time set after STP instruction released bit is “0”, the time for 512
counts of the count source become the oscillation stabilizing time. When the oscillation stabilizing
time set after STP instruction released bit is “1”, an arbitrarily count value set to the prescaler 12
and the timer 1 become the oscillation stabilizing time.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-152
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
2.12.2 Wait mode
The wait mode is set by execution of the WIT instruction. In the wait mode, oscillation continues, but the
internal clock φ stops at the “H” level.
The CPU stops, but most of the peripheral units continue operating.
(1) State in wait mode
The continuation of oscillation permits clock supply to the peripheral units. Table 2.12.2 shows the
state in the wait mode.
Table 2.12.2 State in wait mode
Item
State in wait mode
Operating.
Oscillation
CPU
Stopped.
Stopped at “H” level.
Internal clock φ
I/O ports P0–P6
Timer
Retains the state at the WIT inexecution.
Operating.
PWM
Operating.
Operating.
Watchdog timer
Operating.
Serial I/O1, Serial I/O2, Serial I/O3
I2C-BUS interface
Stopped.
Operating.
A/D converter
D/A converter
Retains oltage.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-153
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
(2) Release of wait mode
The wait mode is released by reset input or by the occurrence of an interrupt request. Note the
differences in the restoration process according to reset input or interrupt request, as described
below.
In the wait mode, oscillation is continued, so an instruction can be executed immediately after the
wait mode is released.
ꢀRestoration by reset input
The wait mode is released by holding the input level of the RESET pin at “L” in the wait mode.
Upon release of the wait mode, all ports are in the input state, and supply of the internal clock
φ to the CPU is started. To reset the microcomputer, the RESET pin should be held at an “L” level
for 16 cycles or more of XIN. The reset state is released in approximately 10.5 cycles to 18.5 cycles
of the XIN input after the input of the RESET pin is returned to the “H” lev.
At release of wait mode, the internal RAM retains its contents previous to set. However, the
previous contents of the CPU register and SFR are not retained.
Figure 2.12.3 shows the reset input time.
For more details concerning reset, refer to “2.10 Reset”.
Operating mode
Wait mode
Vcc
Time to hold internal reset state =
approximately 10.5 to 18.5 cycles of XIN input
16 f XIN
RESET
X
IN
ote)
Execute ruction
Noe cases may occur in which no waveform is input to XIN (in low-speed mode).
Fig. 2.12.3 Reset input time
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-154
APPLICATION
2.12 Standby function
3804 Group (Spec.H)
ꢀRestoration by interrupt request
In the wait mode, the occurrence of an interrupt request releases the wait mode and supply of the
internal clock φ to the CPU is started. At the same time, the interrupt request used for restoration
is accepted, so the interrupt processing routine is executed.
However, when using an interrupt request for restoration from the wait mode, in order to enable the
selected interrupt, you must execute the STP instruction after setting the following conditions.
[Necessary register setting]
ꢀ Interrupt disable flag I = “0” (interrupt enabled)
ꢀ Interrupt request bit of interrupt source to be used for restoration = “0” (no interrupt request issued)
ꢀ Interrupt enable bit of interrupt source to be used for restoration = “1” (interrupts enabled)
For more details concerning interrupts, refer to “2.2 Interrupts”.
(3) Notes on wait mode
ꢀClock restoration
If the wait mode is released by a reset when XCIN is set as the sock and XIN oscillation is
stopped during execution of the WIT instruction, XCIN oscillatio, XIN oscillations starts, and
X
IN is set as the system clock.
In the above case, the RESET pin should be held at “Lhe oscillation is stabilized.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-155
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
2.13 Flash memory mode
This paragraph explains the registers setting method and the notes relevant to the flash memory mode of
M38049FFHSP/FP/HP/KP.
2.13.1 Overview
The functions of the flash memory version are similar to those of the mask ROM version except that the
flash memory is built-in and some of the SFR area differ from that of the mask ROM version (refer to
“2.13.2 Memory map”).
In the flash memory version, the built-in flash memory can be programmed or erased by using the following
three modes.
• CPU rewrite mode
• Parallel I/O mode
• Standard serial I/O mode
2.13.2 Memory map
M38049FFHSP/FP/HP/KP have 60 Kbytes of built-in flash memory.
Figure 2.13.1 shows the memory map of the flash memory version.
000016
User ROM area
Data block B:
2 Kbytes
Data block A
2 Kbyte
SFR area
100016
180016
200016
004016
083F16
Internal RAM area
(2 Kbytes)
RAM
Bloes
Notes 1: The boot ROM area can be rewritten in a paral-
lel I/O mode. (Access to except boot ROM
area is disabled.)
0FE016
ck 2: 16 Kbytes
Block 1: 8 Kbytes
SFR area
0FFF16
100016
2: To specify a block, use the maximum address
in the block.
00016
FFFF16
Internal flash memory area
(60 Kbytes)
F00016
Boot ROM area
4 Kbytes
Block 0: 8 Kbytes
FFFF16
FFFF16
Fig. 2.13.1 Memoap of M38049FFHSP/FP/HP/KP
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-156
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
2.13.3 Relevant registers
Address
0FE016 Flash memory control register 0 (FMCR0)
0FE116
0FE216
Flash memory control register 1 (FMCR1)
Flash memory control register 2 (FMCR2)
Fig. 2.13.2 Memory map of registers relevant to flash memory
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register 0
(FMCR0 : address 0FE016
)
b
Name
Functions
At reset R W
1
Busy (being automatic written
or automatic erased)
1 : Ready
0 RY/BY status f
0
1
CPU rde 0 : CPU rewrite mode invalid
selte 1)
(software commandes invalid)
1 : CPU rewrite mode valid
(Software commands
acceptable)
3
B user block E/W
enable bit (Notes 1,
2)
0: E/W disabled
1: E/W enabled
0
0
Flash memory reset
bit (Notes 3, 4)
0: Normal operation
1: Reset
Not used (Do not write “1” to this bit.)
4
5
0
0
User ROM area
0: User ROM area is accessed
1: Boot ROM area is accessed
select bit (Note 5)
6
7
Program status flag 0: Pass
1: Error
0
0
Erase status flag
0: Pass
1: Error
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: This bit can be written only when the CPU rewrite mode select bit
is “1”.
3: Effective only when the CPU rewrite mode select bit = “1”. Fix this
bit to “0” when the CPU rewrite mode select bit is “0”.
4: When setting this bit to “1” (when the control circuit of flash memory
is reset), the flash memory cannot be accessed for 10 µs.
5: Write to this bit from program on RAM.
Fig. 2.13.3 Structure of Flash memory control register 0
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-157
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register 1
(FMCR1 : address 0FE116)
b
Name
Functions
At reset R W
0
0 : Suspend invalid
1 : Suspend valid
0 Erase suspend
enable bit (Note 1)
0
1
Erase suspend
request bit (Note 2)
0 : Erase restart (no
request issued)
1 : Suspend request
(request issued)
2
3
4
5
Nothing is arranged for these bits. If writing to
these bits, write “0”. The contents are undefined
at reading.
0
0 : Erase active
1 : Erase inactive (E
suspend mode
1
6 Erase suspend flag
Nothing is arranged for these bits. If
these bits, write “0”. The contents fined
at reading.
0
7
Notes 1: For this bit to be set to “r needs to write a “0” and then
a “1” to it in successio
2: Only when the erad bit is “1”, this bit is valid.
Fig. 2.13.4 Structure of Flash memory control r1
Flash memory control regist
b7 b6 b5 b4 b3 b2 b1 b0
Fly control register 2
address 0FE216)
Name
Functions
At reset R W
Nothing is arranged for these bits. If writing to
these bits, write “0”. The contents are undefined
at reading.
0
1
2
3
1
0
All user block E/W
4
0 : E/W disabled
1 : E/W enabled
enable bit (Notes 1, 2)
0
1
0
5
6
Nothing is arranged for these bits. If writing to
these bits, write “0”. The contents are undefined
at reading.
7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then
a “1” to it in succession.
2: Effective only when the CPU rewrite mode select bit = “1”.
Fig. 2.13.5 Structure of Flash memory control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-158
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
2.13.4 Parallel I/O mode
In the parallel I/O mode, program/erase to the built-in flash memory can be performed by a flash memory
programmer (EFP-I etc.).
The memory area of program/erase is from 0F00016 to 0FFFF16 (boot ROM area) or from 0100016 to
0FFFF16 (user ROM area). Be especially careful when erasing; if the memory area is not set correctly, the
products will be damaged eternally.
Table 2.13.1 shows the parallel unit when programming by EFP-I in the parallel I/O mode.
•EFP-I provided by Suisei Electronics System Co., Ltd. (http://www.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.13.1 Parallel unit when parallel programming (when using EFP-I provided by Suisei Electronics
System Co., Ltd.)
Products
Parallel unit
EF3803F-64S
EF3803F-64F
EF3803F-64H
EF3803F-64U
Boot ROM area
Uer ROM area
M38049FFHSP
M38049FFHFP
M38049FFHHP
M38049FFHKP
0F00016 to 0FFFF16
00016 to 0FFFF16
2.13.5 Standard serial I/O mode
Table 2.13.2 shows a pin connection example (4 wires) bete programmer (EFP-I; Serial unit
EF1SRP-01U is required additionally) and the microcomputprogramming in the standard serial
I/O mode 1.
•EFP-I provided by Suisei Electronics System Co., Ltdwww.suisei.co.jp/index_e.htm)
(product available in Asia and Oceania only)
Table 2.13.2 Connection example to programen serial programming (4 wires)
Flash memory version
EFP-I (EF1SRP
1U side
Signal name
Function
Pin name
M38049FFHSP
M38049FFHSP
r Line number
pin number
pin number
9
T_SCLK
T_TX
13
15
14
12
Transfer clock input
Serial data input
Serial data output
Transmit/Receive
enable output
“H” input
P4
P4
P4
P4
6
4
5
7
/SCLK1
21
23
22
10
11
12
/RxD
/TxD
1
T_
1
/SRDY1/CNTR
2
20
3
14
4
_VPP
T_RESET
18
19
57
CNVSS
26
27
1
Reset input
RESET (Note 1)
T_VDD (Note 2)
Target board power
source monitor input
GND
V
CC (Note 2)
1, 2, 15, 16
GND (Note 3)
V
SS, AVSS (Note 3)
24, 59
32, 3
Notes 1: Since reset release after write verification is not performed, when operating MCU after writing,
separate a target connection cable.
2: Supply Vcc of EFP-I side from user side so that the power supply voltage of the output buffer used
by the EFP-I side becomes the same as user side power supply voltage (Vcc).
3: Four pins (No. 1, 2, 15, and 16) of the EF1SRP-01U side connector are prepared for GND signal.
When connecting with a target board, although connection of only one pin does not have a
problem, we recommend connecting with two or more pins.
Rev.1.00 Jan 14, 2005
2-159
REJ09B0212-0100Z
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
2.13.6 CPU rewrite mode
In the CPU rewrite mode, issuing software commands through the Central Processing Unit (CPU) can
rewrite the built-in flash memory. Accordingly, the contents of the built-in flash memory can be rewritten
with the microcomputer itself mounted on board, without using the programmer.
Store the rewrite control program to the built-in flash memory in advance. The built-in flash memory cannot
be read in the CPU rewrite mode. Accordingly, after transferring the rewrite control program to RAM,
execute it on the RAM.
The following commands can be used in the CPU rewrite mode: read array, read status register, clear
status register, program, and block erase. For details concerning each command, refer to “CHAPTER 1
Flash memory mode (CPU rewrite mode)”.
(1) CPU rewrite mode beginning/release procedures
Operation procedure in the CPU rewrite mode for the built-in flash memory is described below.
[Beginning procedure]
➀ Apply “H” to the CNVSS pin and P4
➀ Release reset.
5
/TxD pin (at selecting boot Ra).
1
➀ Set bits 6 and 7 (main clock division ratio selection bits) of tmode register. (Make sure
that system clock φ is less than 4.0 MHz.)
➀ After CPU rewrite mode control program is transferreernal RAM, jump to this control
program on RAM. (The following operations are conby this control program).
➀ Set “1” to the CPU rewrite mode select bit (bit 1 ess 0FFE16).
For this bit to be set to “1”, the user needs to 0” and then “1” to it in succession.
➀ Set “1” to the all user block E/W enable bit address 0FE216). Set the 8 KB user block
➀
E/W enable bit. (Set to “0” when E/W is d, and set to “1” when E/W is enabled.)
➀
For these bits to be set to “1”, the useto write “0” and then “1” to those in succession.
➀ Flash memory operations are execuusing software commands.
Note 1: The following procedureso necessary.
• Control for data whict from the external (serial I/O etc.) and to be programmed
to the flash memo
• Initial setting for etc.
• Writing to the og timer
[Release procedur
➀ Execute the rray command.
➀ In order te E/W to the user ROM area (except for data block), set “0” to the all user block E/
W enabit 4 of 0FE216) and the 8 KB user block E/W enable bit (bit 2 of 0FE016) (Note 2).
➀ Set thU rewrite mode select bit (bit 1 of address 0FFE16) to “0”.
➀ Jump from the CPU rewriting control program on RAM to the user program on the flash memory.
Note 2: Although E/W inhibition is not indispensable, the safety of system improves by disabling
E/W except the time of E/W execution.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-160
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
Also, execute the following processing before the CPU reprogramming mode is selected so that
interrupts will not occur during the CPU reprogramming mode.
• Set the interrupt disable flag (I) to “1”
When the watchdog timer has already started, write to the watchdog timer control register (address
001E16) periodically during the CPU reprogramming mode in order not to generate the reset by the
underflow of the watchdog timer H.
During the program or erase execution, watchdog timer is automatically cleared. Accordingly, the
inernal reset by underflow does not occur.
When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer
enters the following state;
• Interrupt occurs
This may cause a program runaway because the read from the flash memory which has the interrupt
vector area cannot be performed.
• Underflow of watchdog timer H, reset
This may cause a microcomputer reset; the built-in flash memory control cid the flash memory
control register are reset. When reset state is released with CNVss = P4
5
/TxD = “H”, CPU
1
starts in the boot mode.
Also, when the above interrupt and reset occur during program/eror data may still exist after
reset release because the reprogramming of the flash memory is pleted, so that reprogramming
of the flash memory in the parallel I/O mode or serial I/O required.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-161
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
2.13.7 Flash memory mode application examples
The control pin processing example on the system board in the standard serial I/O mode and the control
example in the CPU rewrite mode are described below.
(1) Control pin connection example on system board in standard serial I/O mode
As shown in Figure 2.13.6, in the standard serial I/O mode, the built-in flash memory can be rewritten
with the microcomputer mounted on board. Connection examples of control pins (P4
P4 , CNVSS, and RESET pin) in the standard serial I/O mode are described
below.
4
/RxD, P4 /TxD,
5
6
/SCLK1, P4
7
/SRDY1/CNTR
2
RS-232C
Serial programmer
M38049FFHSP/FP/HP/KP
Fig. 2.13.6 Rewrite example of builh memory in standard serial I/O mode
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-162
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
ꢀ When control signals are not affected to user system circuit
When the control signals in the standard serial I/O mode are not used or not affected to the user
system circuit, they can be connected as shown in Figure 2.13.7.
Target board
ꢀ1
Not used or to user system circuit
M38049FFHSP/FP/HP/KP
TXD(P45)
ꢀ2
SCLK1(P46)
VCC
RXD(P44)
BUSY(P47)
CNVSS
SS
RESET
X
IN
User reset signal (Low active)
ꢀ1: When not used, set to input mode and pull up or pult to output mode and open.
ꢀ2: It is necessary to apply Vcc to SCLK1 (P4 ) pin onlis released in the serial I/O mode 1.
It is necessary to apply Vss to SCLK1 (P4 ) pin set is released in the serial I/O mode 2.
6
6
Fig. 2.13.7 Connection example in standard seriode (1)
ꢀ When control signals are affected tsystem circuit-1
Figure 2.13.8 shows an example thumper switch cut-off the control signals not to supply
to the user system circuit in the d serial I/O mode.
Target board
To user system circuit
M38049FFHSP/FP/HP/KP
TXD(P45)
ꢀ
SCLK1(P46)
VCC
R
B
XD(P44)
USY(P47)
AVSS
VSS
CNVSS
RESET
X
OUT
X
IN
User reset signal (Low active)
ꢀ: It is necessary to apply Vcc to SCLK1 (P4
6
) pin only when reset is released in the serial I/O mode 1.
) pin only when reset is released in the serial I/O mode 2.
It is necessary to apply Vss to SCLK1 (P4
6
Fig. 2.13.8 Connection example in standard serial I/O mode (2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-163
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
ꢀ When control signals are affected to user system circuit-2
Figure 2.13.9 shows an example that the analog switch (74HC4066) cut-off the control signals not
to supply to the user system circuit in the standard serial I/O mode.
Target board
74HC4066
To user system circuit
M38049FFHSP/KP
T
X
D(P4 )
5
ꢀ
S
CLK1(P4 )
6
VCC
RX
D(P4 )
4
B
USY(
AVSS
VSS
ESET
XIN
X
OUT
User reset active)
ꢀ: It is necessary to apply Vcc 4
6
) pin only when reset is released in the serial I/O mode 1.
) pin only when reset is released in the serial I/O mode 2.
It is necessary to apply V(P4
6
Fig. 2.13.9 Connection exastandard serial I/O mode (3)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
2-164
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
(2) Control pin termination example in CPU rewrite mode
In this example, data is received by using serial I/O, and the data is programmed to the built-in flash
memory in the CPU rewrite mode.
Figure 2.13.10 shows an example of the reprogramming system for the built-in flash memory in the
CPU rewrite mode. For the CPU rewrite mode beginning/release method, refer to “2.13.6 CPU rewrite
mode.”
M38049FFHSP/FP/HP/KP
V
CC
Clock input
BUSY output
Data input
S
CLK1
S
RDY1(BUSY)
AVSS
R
X
D
V
Data output
TX
D
ESET
CNVSS
User reset signal
IN
X
OUT
Fig. 2.13.10 Example of restem for built-in flash memory in CPU rewrite mode (single-chip mode)
Rev.1.00 Jan 14, 2005
2-165
REJ09B0212-0100Z
APPLICATION
2.13 Flash memory mode
3804 Group (Spec.H)
2.13.8 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the system clock φ 4.0 MHz or less using the main clock division ratio
selection bits (bits 6 and 7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannot be used during the CPU
rewrite mode.
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode because they refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the internal reset generated by watchdog
timer underflow does not happen, because of watchdog timer is always cleduring program or
erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “H” when reset is releasmode is active. So the
program starts from the address contained in address FFFC16 a16 in boot ROM area.
Rev.1.00 Jan 14, 2005
2-166
REJ09B0212-0100Z
HAPTER 3
APPENDIX
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Electrical characteristics
Standard characteristics
Notes on use
Countermeasures against noise
List of registers
Package outline
Machine instructions
List of instruction code
SFR memory map
3.10 Pin configurations
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
3.1 ELECTRICAL CHARACTERISTICS
3.1.1 Absolute maximum ratings
Table 3.1.1 Absolute maximum ratings
Symbol
Parameter
Power source voltages
Conditions
Ratings
–0.3 to 6.5
Unit
V
VCC
All voltages are based on Vss.
Output transistors are cut off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
–0.3 to VCC +0.3
V
P50–P57, P60–P67, VREF
VI
Input voltage P32, P33
–0.3 to 5.8
V
V
V
V
____________
VI
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VI
VO
Output voltage P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67, XOUT
VO
Output voltage P32, P33
Power dissipation
–.3 to 5.8
Note)
to 85
V
mW
°C
Pd
Ta = 25°C
Topr
Tstg
Operating temperature
Storage temperature
5 to 125
°C
Note: This value is 300 mW except SP package.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-2
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
3.1.2 Recommended operating conditions
Table 3.1.2 Recommended operating conditions (1)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Power source voltage
Conditions
Min.
2.7
2.7
4.0
4.5
2.7
4.5
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
When start oscillating (Note 2)
V
V
V
V
V
V
V
V
VCC
High-speed mode
f(XIN) ≤ 8.4 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
f(XIN) ≤ 12.5 MHz
f(XIN) ≤ 16.8 MHz
(Note 1)
f(φ) = f(XIN)/2
Middle-speed mode
f(φ) = f(XIN)/8
Power source voltage
“H” input voltage
VSS
VIH
VCC
0.8VCC
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67
“H” input voltage
5.5
5.5
V
V
0
CC
VIH
VIH
P32, P33
“H” input voltage
2
(when I C-BUS input level is selected)
SDA, SCL
5.5
VIH
VIH
“H” input voltage
(when SMBUS input level is selected)
SDA, SCL
1.4
V
“H” input voltage
VCC
VCC
V
V
V
0.8VCC
____________
RESET, XIN, CNVSS
“H” input voltage
XCIN
VIH
VIL
2
0
“L” input voltage
P00–P07, P10–P17, P20–P27,
P30–P37,P40–P47,
P50–P57, P60–P67
“L” input voltage
0.2VCC
VIL
VIL
0.3Vcc
0.6
V
V
0
0
0
2
(when I C-BUS input level is selected)
SDA, SCL
“L” input voltage
(when SMBUS input level is sel
SDA, SCL
“L” input voltage
0.2VCC
0.16VCC
0.4
VIL
VIL
VIL
V
V
V
____________
RESET, CNVSS
“L” input voltage
XIN
“L” input volt
XCIN
Notes 1: When using rter, see A/D converter recommended operating conditions.
2: The start vod the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating
temperature rae, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-3
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Table 3.1.3 Recommended operating conditions (2)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Conditions
Symbol
f(XIN)
Parameter
Unit
Min.
Typ.
Max.
(9✕VCC-0.3)✕1.05
Main clock input oscillation High-speed mode
MHz
MHz
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
3
frequency (Note 1)
f(φ) = f(XIN)/2
(24✕VCC-60)✕1.05
3
16.8
MHz
MHz
4.5 ≤ VCC ≤ 5.5 V
2.7 ≤ VCC < 4.5 V
Middle-speed mode
(15✕VCC+39)✕1.1
f(φ) = f(XIN)/8
7
16.8
50
MHz
kHz
4.5 ≤ VCC ≤ 5.5 V
Sub-clock input oscillation
32.768
f(XCIN)
frequency (Notes 1, 2)
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frency on condition that
f(XCIN) < f(XIN)/3.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-4
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Table 3.1.4 Recommended operating conditions (3)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
–P0 , P1 –P1
Min.
Typ.
Max.
–80
–80
80
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47, P50–P57, P60–P67 (Note 1)
P0 –P0 , P1 –P1 , P3 –P3 (Note 1)
P20–P27 (Note 1)
P40–P47,P50–P57, P60–P67 (Note 1)
–P0 , P1 –P1 , P2 –P2 , P3 , P3 , P3
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current P0 –P0 , P1 –P1 , P3 –P3 (Note 1)
“L” total average output current P20–P27 (Note 1)
“L” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
0
7
0
7
, P2
0
–P2
7
, P3
0
, P3
1
, P3
4
–P3
7
7
(Note 1)
(Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
0
7
0
7
0
7
80
80
“H” total average output current P0
0
7
0
7
0
7
0
1
4
–P3
–40
–40
40
0
7
0
7
0
7
40
40
“H” peak output current
P00–P07, P10–P17, P20–P27, P30, P31, P34–P37,
P40–P47, P50–P57, P60–P67 (Note 2)
–10
IOL(peak)
“L” peak output current
P00–P07, P10–P17, P30–P37, P40–P47, P50–P57,
P60–P67 (Note 2)
10
mA
IOL(peak)
IOH(avg)
“L” peak output current
P20–P27 (Note 2)
20
mA
mA
“H” average output current
P00–P07, P10–P17, P20–P27, P30, P31, P34–P37,
P40–P47, P50–P57, P60–P67 (Note 3)
–5
IOL(avg)
IOL(avg)
“L” average output current
“L” average output current
P00–P07, P10–P17, P30–P37, P40–P47, P50–P
P60–P67 (Note 3)
5
mA
mA
P20–P27 (Note 3)
10
Notes 1: The total output current is the sum of all the currents flowing through all the ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak valucurrents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) are average value mer 100 ms.
Rev.1.00 Jan 14, 2005
3-5
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
3.1.3 Electrical characteristics
Table 3.1.5 Electrical characteristics (1)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
“H” output voltage
P00–P07, P10–P17, P20–P27,
P30, P31, P34–P37, P40–P47,
P50–P57, P60–P67 (Note 1)
Test conditions
IOH = –10 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
Unit
Min.
Typ.
Max.
VOH
VOL
VOL
VCC–2.0
V
V
VCC–1.0
VCC = 1.8 to 5.5 V
“L” output voltage
IOL = 10 mA
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
2.0
1.0
V
V
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67
VCC = 1.8 to 5.5 V
“L” output voltage
P20–P27
IOL = 20 mA
VCC = 4.0 to 5.5 V
IOL = 1.6 mA
2.0
0.4
V
V
VCC = 1.8 to 5.5 V
VT+–VT–
VT+–VT–
Hysteresis
CNTR0, CNTR1, CNTR2,
INT0–INT4
5
0.5
V
V
Hysteresis
RxD1, SCLK1, SIN2, SCLK2, RxD3,
SCLK3
____________
VT+–VT–
Hysteresis RESET
V
IIH
“H” input current
VI = VCC
5.0
µA
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
(Pin floating. Pull-up
transistors “off”)
P60–P67
____________
IIH
IIH
IIL
“H” input current RESET, CNVSS
“H” input current XIN
VI = VCC
VI = VCC
5.0
µA
µA
µA
4.0
“L” input current
VI = VSS
–5.0
P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
(Pin fl-up
tran”)
P60–P67
____________
IIL
IIL
IIL
“L” input current RESET,CNVSS
SS
–5.0
µA
µA
µA
“L” input current
XIN
–4.0
“L” input current (at Pull-up)
P00–P07, P10–P17, P20–
P30, P31, P34–P37, P4
P50–P57, P60–P67
= VSS
VCC = 5.0 V
VI = VSS
–80
–30
–210
–420
–140
–70
µA
VCC = 3.0 V
VRAM
RAM hold voltage
When clock stopped
1.8
VCC
V
Note 1: P35 is measured when the Pchannel output disable bit of the UART3 control register (bit 4 of address 003316) is “0”.
P45 is measured when the P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-6
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Table 3.1.6 Electrical characteristics (2)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, f(XCIN)=32.768kHZ (Stoped in middle-speed mode), Output transistors “off”,
AD converter not operated)
Limits
Unit
Symbol
ICC
Parameter
Test conditions
f(XIN) = 16.8 MHz
Max.
Typ.
Min.
Power source
current
High-speed
mode
VCC = 5V
5.5
4.5
3.5
2.2
2.2
2.7
1.8
1.1
3.0
2.4
2.0
2.1
1.7
1.5
1.3
410
4.5
400
3.7
0.55
0.75
1000
8,3
6.8
5.3
3.3
3.3
4.1
2.7
1.7
4.5
3.6
3.0
3.2
2.6
2.3
2.0
630
6.8
600
5.6
3.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 16.8 MHz (in WIT state)
f(XIN) = 8.4 MHz
f(XIN) = 4.2 MHz
f(XIN) = 2.1 MHz
f(XIN) = 16.8 MHz
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 16.8 MHz (in WIT state)
f(XIN) = 12.5 MHz
f(XIN) = 8.4 MHz
f(XIN) = 6.3 MHz
f(XIN) = stopped
In WIT state
VCC = 3V
VCC = 5V
Middle-speed
mode
VCC = 3V
Low-speed
mode
VCC = 5V
VCC = 3V
µA
f(XIN) = stopped
In WIT state
µA
µA
In STP state
(All oscillation stopped)
Ta = 25 °C
µA
Ta = 85
µA
Increment when A/D conversion
is executed
f(XIHz, VCC = 5V
In igh-speed mode
µA
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-7
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
3.1.4 A/D converter characteristics
Table 3.1.7 A/D converter recommended operating conditions
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V,Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Conditions
8-bit A/D mode (Note 1)
Symbol
VCC
Parameter
Max.
Min.
Typ.
5.0
5.0
V
Power source voltage
2.7
2.7
2.0
5.5
5.5
(When A/D converter is used)
Analog reference voltage
Analog power source voltage
Analog input voltage
10-bit A/D mode (Note 2)
V
V
VREF
AVSS
VIA
VCC
0
V
0
VCC
MHZ
Main clock oscillation frequency
2.7 ≤ VCC < 4.0 V
4.0 ≤ VCC < 4.5 V
4.5 ≤ VCC ≤ 5.5 V
0.5
(9✕VCC-0.3)✕1.05
f(XIN)
3
(When A/D converter is used)
0.5
0.5
(24✕VCC-60)✕1.05
3
16.8
Note 1: 8-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “1”.
2: 10-bit A/D mode: When the conversion mode selection bit (bit 7 of address 003816) is “0”.
Table 3.1.8 A/D converter characteristics
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Unit
Parameter
Test conditions
.
Typ.
Max.
–
Resolution
8-bit A/D mode (Note 1)
10-bit A/D mode (Note 2)
8
10
±2
±4
50
61
100
200
5
bit
–
Absolute accuracy
(excluding quantization error)
Conversion time
8-bit A/D mode (Note 1) 2.7 ≤ 5 V
10-bit A/D mode (Note 2) 25.5 V
8-bit A/D mode (Note 1)
LSB
tCONV
2tc(XIN)
10-bit A/D mode (Note
RLADDER Ladder resistor
12
50
35
kΩ
µA
µA
µA
IVREF
Reference power
atA/D converter operated VREF = 5.0 V
150
source input current atA/D converter stopped VREF = 5.0 V
A/D port inout current
II(AD)
5
Note 1: 8-bit A/D mode: When the conversion mode selection bit (bit 7 003816) is “1”.
2: 10-bit A/D mode: When the conversion mode selection bit ess 003816) is “0”.
3.1.5 D/A converter characteristics
Table 3.1.9 D/A converter characteristics
(VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Par
Test conditions
Unit
Min.
Typ.
Max.
–
–
Resolution
Absolute accur
8
1.0
2.5
3
bit
%
.0 ≤ VREF ≤ 5.5 V
2.7 ≤ VREF < 4.0 V
%
tsu
RO
Setting ti
Outpu
µs
kΩ
mA
2
3.5
5
IVREF
Refwer source input current (Note 1)
3.2
Note 1: Using one D/A convter, with the value in the DA conversion register of the other D/A converter being “0016”.
3.1.6 Power source circuit timing characteristics
Table 3.1.10 Power source circuit timing characteristics
(VCC = 2.7 to 5.5 V, VREF = 2.7 V to VCC, VSS = AVSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
td(P–R)
Parameter
Test conditions
Unit
ms
Min.
Max.
2
Internal power source stable time at power-on
2.7 ≤ Vcc < 5.5 V
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-8
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
3.1.7 Timing requirements and switching characteristics
Table 3.1.11 Timing requirements (1)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Typ.
Min.
td(P-R) ms + 16
59.5
Max.
tW(RESET)
tC(XIN)
Reset input “L” pulse width
Main clock XIN
XIN cycle
ns
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
input cycle time
10000/(86VCC-219)
26✕103/(82VCC-3)
tWH(XIN)
tWL(XIN)
Main clock XIN
ns
ns
25
input “H” pulse width
4000/(86VCC-219)
10000/(82VCC-3)
Main clock XIN
25
input “L” pulse width
4000/(86VCC-219)
10000/(82VCC-3
tC(XCIN)
Sub-clock XCIN input cycle time
Sub-clock XCIN input “H” pulse width
Sub-clock XCIN input “L” pulse width
CNTR0–CNTR2
µs
µs
µs
ns
20
5
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
250
48
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5
2.7≤VCC<4
4.5≤VC
4.0
.0 V
C≤5.5 V
VCC<4.5 V
.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
input cycle time
tWH(CNTR)
tWL(CNTR)
tWH(INT)
CNTR0–CNTR2
ns
ns
ns
ns
input “H” pulse width
64
115
48
CNTR0–CNTR2
input “L” pulse width
64
115
48
INT00, INT01, INT1, INT2, INT3, INT40, INT41
input “H” pulse width
64
115
48
tWL(INT)
INT00, INT01, INT1, INT2, INT3, INT40,
input “L” pulse width
64
115
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-9
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Table 3.1.12 Timing requirements (2)
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Typ.
Min.
250
320
500
120
150
240
120
150
240
70
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5
2.7≤VCC<
4.5≤V
4.0V
.0 V
C≤5.5 V
VCC<4.5 V
.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
t
t
t
C(SCLK1), tC(SCLK3)
Serial I/O1, serial I/O3
clock input cycle time (Note)
WH(SCLK1), tWH(SCLK3
)
Serial I/O1, serial I/O3
clock input “H” pulse width (Note)
WL(SCLK1), tWL(SCLK3
)
Serial I/O1, serial I/O3
clock input “L” pulse width (Note)
tsu(RxD1-SCLK1),
tsu(RxD3-SCLK3)
Serial I/O1, serial I/O3
clock input setup time
90
100
32
th(SCLK1-RxD1),
th(SCLK3-RxD3)
Serial I/O1, serial I/O3
clock input hold time
50
1000
200
260
400
200
260
400
100
130
200
100
130
150
tC(SCLK2)
Serial I/O2
clock input cycle time
tWH(SCLK2)
tWL(SCLK2)
Serial I/O2
clock input “H” pulse width
Serial I/O2
clock input “L” pulse width
tsu(SIN2-SCLK2)
th(SCLK2-SIN2)
Serial I/O2
clock input setup time
Serial I/O2
clock input hold time
Note : When bit 6 of address 001A16 and bit 6 of address “1” (clock synchronous).
Divide this value by four when bit 6 of address 0it 6 of address 003216 are “0” (UART).
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-10
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Table 3.1.13 Switching characteristics
(VCC = 2.7 to 5.5 V, VSS = 0V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Test
conditions
Symbol
Parameter
Serial I/O1, serial I/O3
Unit
ns
Min.
Typ.
Max.
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5
2.7≤VCC<4
4.5≤VC
4.0≤
20 V
≤5.5 V
CC<4.5 V
7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
4.5≤VCC≤5.5 V
4.0≤VCC<4.5 V
2.7≤VCC<4.0 V
tC(SCLK1)2-30, tC(SCLK3)/2-30
tC(SCLK1)2-35, tC(SCLK3)/2-35
tC(SCLK1)2-40, tC(SCLK3)/2-40
tC(SCLK1)2-30, tC(SCLK3)/2-30
tC(SCLK1)2-35, tC(SCLK3)/2-35
tC(SCLK1)2-40, tC(SCLK3)/2-40
t
t
WH(SCLK1
WH(SCLK3
)
)
clock output “H” pulse width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
WL(SCLK1
WL(SCLK3
)
Serial I/O1, serial I/O3
)
clock output “L” pulse width
140
200
350
td(
td(
S
S
CLK1-TxD1)
CLK3-TxD3)
Serial I/O1, serial I/O3
output delay time (Note)
-30
-30
-30
tV(
tV(
S
CLK1-TxD1)
Serial I/O1, serial I/O3
S
CLK3-TxD3)
output valid time (Note)
30
35
40
30
35
40
tr(SCLK1)
tr(SCLK3)
Serial I/O1, serial I/O3
rise time of clock output
tf(SCLK1)
tf(SCLK3)
Serial I/O1, serial I/O3
fall time of clock output
Fig. 3.1.1
2-160
K2)/2-200
SCLK2)/2-240
C(SCLK2)/2-160
tC(SCLK2)/2-200
tC(SCLK2)/2-240
tWH(SCLK2)
tWL(SCLK2)
Serial I/O2
clock output “H” pulse width
Serial I/O2
clock output “L” pulse width
200
250
300
td(SCLK2-SOUT2)
Serial I/O2
output delay time
0
0
0
tV(SCLK2-SOUT2)
Serial I/O2
output valid time
30
35
40
30
35
40
30
35
40
t
t
t
f
(SCLK2
)
Serial I/O2
fall time of clock output
10
12
15
10
12
15
r
(CMOS)
CMOS
rise time of output
f
(CMOS)
CMOS
fall time oote)
Note: When the P45/Tnnel output disable bit of the UART1 control register (bit 4 of address 001B16) is “0”.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-11
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Measurement output pin
1kΩ
Measurement output pin
100pF
100pF
CMOS output
N-channel open-drain output
Fig. 3.1.1 Circuit for measuring output switching characteristics (1)
Fig. 3.1.2 Circuit for measuring output switching characteristics (2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-12
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
Single-chip mode timing diagram
t
C(CNTR)
t
WL(CNTR)
t
WH(CNTR)
0.8VCC
CNTR0, CNTR1, CNTR2
0.2VCC
0.2VCC
t
WL(INT)
t
WH(INT)
INT1,INT2,INT
3
0.8VCC
INT00,INT40
INT01,INT41
t
W(RESET)
.8VCC
RESET
0.2VCC
t
t
C(XI
t
t
WL(XIN)
t
WH(XIN)
0.8VCC
X
IN
0.2VCC
0.2VCC
C(XCIN
)
WL(XCIN
)
IN)
X
CIN
t
C(SCLK1),
WL(SCLK3
t
C(SCLK2),
t
C(SCLK3),
t
f
t
WL(SCLK1),
t
WL(SCLK2),
t
)
t
WH(SCLK1), WH(SCLK2), tWH(SCLK3)
t
t
r
S
S
S
CLK1
CLK2
CL
0.8VCC
0.2VCC
t
t
t
su(R
su(SIN2-
su(R D3
x
D1
S
-
-
S
CLK1),
t
t
t
h(SCLK1-
h(SCLK2-
h(SCLK3-
R
S
R
x
D1),
IN2),
D3)
CLK2),
x
S
CLK3
)
x
R
X
X
IN2
D
1
3
0.8V
0.2VCCCC
R
D
S
t
t
t
v
v
v
(SCLK1-T
(SCLK2-SOUT2),
(SCLK3-T D3)
xD1),
t
d(SCLK1-T
x
D1), td(SCLK2-SOUT2), td(SCLK3-TxD3)
x
T
T
X
X
OUT2
D
1
3
D
S
Fig. 3.1.3 Timing diagram (in single-chip mode)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-13
APPENDIX
3804 Group (Spec.H)
3.1 Electrical characteristics
2
3.1.8 Multi-master I C-BUS bus line characteristics
Table 3.1.14 Multi-master I2C-BUS bus line characteristics
Standard clock mode
High-speed clock mode
Unit
Symbol
Parameter
Min.
4.7
Max.
Max.
Min.
1.3
tBUF
Bus free time
µs
µs
µs
ns
µs
µs
ns
ns
µs
µs
tHD;STA
tLOW
0.6
1.3
Hold time for START condition
Hold time for SCL clock = “0”
Rising time of both SCL and SDA signals
Data hold time
4.0
4.7
tR
20+0.1Cb
0
300
0.9
1000
300
tHD;DAT
tHIGH
tF
0
Hold time for SCL clock = “1”
Falling time of both SCL and SDA signals
Data setup time
4.0
0.6
20+0.1Cb
100
300
tSU;DAT
tSU;STA
tSU;STO
250
4.7
4.0
Setup time for repeated START condition
Setup time for STOP condition
0.6
Note: Cb = total capacitance of 1 bus line
SDA
t
su:STO
t
BUF
t
LOW
t
R
t
F
S
P
P
SCL
t
HD:DAT
t
HD:STA
t
HIGH
t
su:STA
S : START condition
Sr: RESTART condition
P : STOP condition
Fig. 3.1.4 Timing diagram of multi-maUS
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-14
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
3.2 Standard characteristics
Standard characteristics described below are just examples of the 3804 Group (spec. H)’s characteristics
and are not guaranteed. For rated values, refer to “3.1 Electrical characteristics”.
3.2.1 Power source current standard characteristics
High-speed mode (TYP, 25 °C)
[φ = XIN/2, XCIN = 32.768 kHz]
8.0
6.0
4.0
2.0
0.0
2.5
3.0
3.5
4.0
5.0
5.5
6.0
Vcc (
16.8 MHz
12.5 MHz
4.2 MHz
2.1 MHz
Fig. 3.2.1 Power source current standarcteristics (in high-speed mode)
le-speed mode (TYP, 25 °C)
[φ = XIN/8, XCIN = stopped]
4.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Vcc (V)
16.8 MHz
12.5 MHz
8.4 MHz
6.3 MHz
Fig. 3.2.2 Power source current standard characteristics (in middle-speed mode)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-15
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
Low-speed mode (TYP, 25 °C)
[φ = XCIN/2, XIN = stopped]
800.0
600.0
400.0
200.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
6.0
Vcc (V)
32.768 kHz
Fig. 3.2.3 Power source current standard characteristicw-speed mode)
High-spee, WAIT state (TYP, 25 °C)
[φ = X= 32.768 kHz]
8.0
6.0
2.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Vcc (V)
16.8 MHz
Fig. 3.2.4 Power source current standard characteristics (in high-speed mode, f(XIN) = 16.8 MHz, WAIT state)
Rev.1.00 Jan 14, 2005
3-16
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
Middle-speed mode, WAIT state (TYP, 25 °C)
[φ = XIN/8, XCIN = stopped]
4.0
3.0
2.0
1.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5
.0
Vcc (V)
16.8 MHz
Fig. 3.2.5 Power source current standard characteristics (in peed mode, f(XIN) = 16.8 MHz, WAIT state)
Low-speed moIT state (TYP, 25 °C)
[φ = XCIN/2, opped, XCIN = 32.768 kHz]
8.0
6.0
4.
.0
0.0
2.5
3.0
3.5
4.0
4.5
5.0
32.768 kHz
5.5
6.0
Vcc (V)
Fig. 3.2.6 Power source current standard characteristics (in low-speed mode, WAIT state)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-17
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
High-speed mode, A/D converter operating (TYP, 25 °C)
[φ = XIN/2, XCIN = 32.768 kHz]
8.0
6.0
4.0
2.0
0.0
2.5
3.0
3.5
4.0
4.5
CC(V)
5.0
5
.0
V
16.8 MHz
Fig. 3.2.7 Power source current standard characteristics (in high-sde, f(XIN) = 16.8 MHz, A/D converter operating)
Oscillation de (TYP, 25 °C)
[STP instruction exeXIN = stopped, XCIN = stopped]
1.0
0.8
0.6
.2
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Vcc (V)
Stopped
Fig. 3.2.8 Power source current standard characteristics (at oscillation stopping)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-18
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
3.2.2 Port standard characteristics
Port P60 IOH–VOH characteristics (P-channel drive) [Ta = 25 °C]
(Same characteristics pins: P0, P1, P2, P30, P31, P34–P37, P4, P5, P6)
–50
–45
–40
–35
Vcc = 5.0 V
Vcc = 4.0V
–30
IOH
[mA]
–25
–20
–15
–10
Vcc = 2.7V
–5
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OH [V]
5.5
V
Fig. 3.2.9 CMOS output port P-channel side charac(Ta = 25 °C)
Port P60 IOaracteristics (N-channel drive) [Ta = 25 °C]
(Sacteristics pins: P0, P1, P3, P4, P5, P6)
5
5
30
Vcc = 5.0 V
Vcc = 4.0 V
A]
25
20
15
10
Vcc = 2.7 V
5
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OL[V]
V
Fig. 3.2.10 CMOS output port N-channel side characteristics (Ta = 25 °C)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-19
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
Port P32 IOL–VOL characteristics (N-channel drive) [Ta = 25 °C]
(Same characteristics pins: P32, P33)
50
45
40
Vcc = 5.0 V
35
30
IOL
Vcc = 4.0 V
[mA]
25
20
15
Vcc = 2.7 V
10
5
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VOL[V]
Fig. 3.2.11 N-channel open-drain output port N-channel aracteristics (Ta = 25 °C)
Port P2
0
IOL–VOristics (N-channel drive) [Ta = 25 °C]
characteristics pins: P2)
100
90
8
Vcc = 5.0 V
Vcc = 4.0 V
I
50
40
30
20
Vcc = 2.7 V
10
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OL[V]
5.5
V
Fig. 3.2.12 CMOS large current output port N-channel side characteristics (Ta = 25 °C)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-20
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
Port P60 IIL–VIL characteristics (at pull-up) [Ta = 25 °C]
(Same characteristics pins: P0, P1, P2, P30, P31, P34–P37, P4, P5, P6)
–400
–360
–320
Vcc = 6.0 V
Vcc = 5.0 V
–280
–240
I
IL
[mA]
–200
–160
–120
–80
Vcc = 3.0 V
–40
0
0
0.5 1.0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 6.0
IL[V]
V
Fig. 3.2.13 CMOS input port at pull-up characteristics (T°C)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-21
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
3.2.3 A/D conversion standard characteristics
Figure3.2.14, Figure 3.2.15, and Figure 3.2.16 show the A/D conversion standard characteristics.
The thick lines of the graph indicate the absolute precision errors, These are expressed as the deviation
from the ideal value when the output code changes. For example, the change in output code from 512 to
513 should occur at 2560 mV, but the measured value is –10 mV. Accordingly, the measured point of
change is 2560 – 10 = 2550 mV.
The thin lines of the graph indicate the input voltage width for which the output code is constant. For
example, the measured input voltage width for which the output code is 512 is 5.0 mV, so that the
differential non-linear error is 5.0 – 5.0 = 0.0 mV (0 LSB).
Rev.1.00 Jan 14, 2005
3-22
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
M38049FFHSP A/D CONV. ERROR & STEP WIDTH
V
X
DD = 5.12 [V], VREF = 5.12 [V]
IN = 8 [MHz], Ta = 25 [deg.]
Error
1 LSB Width
Fig. 3.2.14 A/D conversion standard characteristics (f(XIN) = 8 MHz)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-23
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
M38049FFHSP A/D CONV. ERROR & STEP WIDTH
V
X
DD = 5.12 [V], VREF = 5.12 [V]
IN = 12 [MHz], Ta = 25 [deg.]
Error
1 LSB Width
Fig. 3.2.15 A/D conversion standard characteristics (f(XIN) = 12 MHz)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-24
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
M38049FFHSP A/D CONV. ERROR & STEP WIDTH
V
X
DD = 5.12 [V], VREF = 5.12 [V]
IN = 16 [MHz], Ta = 25 [deg.]
Error
1 LSB Width
Fig. 3.2.16 A/D conversion standard characteristics (f(XIN) = 16 MHz)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-25
APPENDIX
3804 Group (Spec.H)
3.2 Standard characteristics
3.2.4 D/A conversion standard characteristics
Figure 3.2.17 shows the D/A conversion standard characteristics.
M38049FFHSP D/A CONV. STEP WIDTH MEASUREMENT
V
X
CC = 5.12 [V], VREF = 5.12 [V]
IN = 16 [MHz], Ta = 25 [deg.]
Error
1 LSB Width
Fig. 3.2.17 D/A con standard characteristics
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-26
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3 Notes on use
3.3.1 Notes on input and output ports
(1) Notes in standby state
In standby state✕1 for low-power dissipation, do not make input levels of an I/O port “undefined”.
Even when an I/O port of N-channel open-drain is set as output mode, if output data is “1”, the
aforementioned notes are necessary.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through a
resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
When using built-in pull-up resistor, note on varied current values:
• When setting as an input port : Fix its input level
• When setting as an output port : Prevent current from flowing external
✕ Reason
Exclusive input ports are always in a high-impedance stoutput transistor becomes an OFF
state when an I/O port is set as input mode by the diegister, so that the port enter a high-
impedance state. At this time, the potential which ito the input buffer in a microcomputer is
unstable in the state that input levels are “undefhis may cause power source current. Even
when an I/O port of N-channel open-drain is output mode by the direction register, if the
contents of the port latch is “1”, the same enon as that of an input port will occur.
✕1 standby state: Stop mode by eSTP instruction
Wait mode by ng WIT instruction
(2) Modifying output data with naging instruction
When the port latch of an is modified with the bit managing instruction✕2, the value of the
unspecified bit may be d.
✕ Reason
The bit manatructions are read-modify-write form instructions for reading and writing data
by a byte cordingly, when these instructions are executed on a bit of the port latch of an
I/O portlowing is executed to all bits of the port latch.
•As for bhich is set for input port:
The pin state is read in the CPU, and is written to this bit after bit managing.
•As for bit which is set for output port:
The bit value is read in the CPU, and is written to this bit after bit managing.
Note the following:
•Even when a port which is set as an output port is changed for an input port, its port latch holds
the output data.
•As for a bit of which is set for an input port, its value may be changed even when not specified
with a bit managing instruction in case where the pin state differs from its port latch contents.
✕2 Bit managing instructions: SEB and CLB instructions
Rev.1.00 Jan 14, 2005
3-27
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3.2 Termination of unused pins
(1) Terminate unused pins
✕ I/O ports :
• Set the I/O ports for the input mode and connect them to VCC or VSS through each resistor of
1 kΩ to 10 kΩ.
Ports that permit the selecting of a built-in pull-up resistor can also use this resistor. Set the
I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until the
mode of the ports is switched over to the output mode by the program after reset. Thus, the
potential at these pins is undefined and the power source current may increase in the input
mode. With regard to an effects on the system, thoroughly perform system ealuation on the user
side.
• Since the direction register setup may be changed because of a progaway or noise, set
direction registers by program periodically to increase the reliabiliogram.
✕ The AVss pin when not using the A/D converter :
• When not using the A/D converter, handle a power sourcr the A/D converter, AVss pin
as follows:
AVss: Connect to the Vss pin.
(2) Termination remarks
✕ I/O ports :
Do not open in the input mode.
✕ Reason
• The power source current may se depending on the first-stage circuit.
• An effect due to noise may ly produced as compared with proper termination ✕ and
shown on the above.
✕ I/O ports :
When setting for the iode, do not connect to VCC or VSS directly.
✕ Reason
If the directioer setup changes for the output mode because of a program runaway or
noise, a shuit may occur between a port and VCC (or VSS).
✕ I/O ports
When sefor the input mode, do not connect multiple ports in a lump to VCC or VSS through
a resistor.
✕ Reason
If the direction register setup changes for the output mode because of a program runaway or
noise, a short circuit may occur between ports.
• At the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less)
from microcomputer pins.
Rev.1.00 Jan 14, 2005
3-28
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3.3 Notes on interrupts
(1) Change of relevant register settings
When the setting of the following registers or bits is changed, the interrupt request bit may be set
to “1”. When not requiring the interrupt occurrence synchronized with these setting, take the following
sequence.
•Interrupt edge selection register (address 003A16
•Timer XY mode register (address 002316
•Timer Z mode register (address 002A16
•I2C START/STOP condition control register (address 001616
)
)
)
)
Set the above listed registers or bits as the following sequence.
Set the corresponding interrupt enable bit to “0”
(disabled) .
↓
Set the interrupt edge select bit (active itch
bit) or the interrupt (source) sele1”.
↓
NOP (One or more ins)
↓
Set the corresponding t request bit to “0”
(no interest issued).
↓
Set the corrng interrupt enable bit to “1”
(enabled).
Fig. 3.3.1 Sequence of chanevant register
■ Reason
When setting lowings, the interrupt request bit may be set to “1”.
•When seternal interrupt active edge
Concegister: Interrupt edge selection register (address 003A16
Timer XY mode register (address 002316
Timer Z mode register (address 002A16
I2C START/STOP condition control register (address 001616
)
)
)
)
•When switching interrupt sources of an interrupt vector address where two or more interrupt
sources are allocated.
Concerned register: Interrupt source selection register (address 003916
)
(2) Check of interrupt request bit
■ When executing the BBC or BBS instruction to an interrupt request bit of an interrupt request
register immediately after this bit is set to “0”, execute one or more instructions before executing
the BBC or BBS instruction.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-29
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
■ Reason
If the BBC or BBS instruction is executed immediately after an interrupt request bit of an interrupt
request register is cleared to “0”, the value of the interrupt request bit before being cleared to “0”
is read.
Clear the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 3.3.2 Sequence of check of interrupt request bit
3.3.4 Notes on 8-bit timer (timer 1, 2, X, Y)
■ If a value n (between 0 and 255) is written to a timer latch, thency division ratio is 1/(n+1).
■ When switching the count source by the timer 12, X and source selection bits, the value
of timer count is altered in unconsiderable amount owinerating of thin pulses in the count
input signals.
Therefore, select the timer count source before salue to the prescaler and the timer.
■ Set the double-function port of the CNTR
0
/CNTR
d port P5
4
/P5
5
to output in the pulse output
mode.
■ Set the double-function port of CNTR
0
/CNand port P5
4
/P5
5
to input in the event counter
mode and the pulse width measureme.
3.3.5 Notes on 16-bit timer (timer Z)
(1) Pulse output mode
■ Set the double-function phe CNTR
2
pin and port P4
7
7
to output.
to input.
(2) Pulse period measurmode
■ Set the double-fuport of the CNTR
2
pin and port P4
■ A read-out of tue is impossible in this mode. The timer can be written to only during timer
stop (no ment of pulse period).
■ Since thlatch in this mode is specialized for the read-out of measured values, do not
perform rite operation during measurement.
■ “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement
start/completion is detected. Consequently, the timer value at start of pulse period measurement
depends on the timer value just before measurement start.
(3) Pulse width measurement mode
■ Set the double-function port of the CNTR
2
pin and port P4 to input.
7
■ A read-out of timer value is impossible in this mode. The timer can be written to only during timer
stop (no measurement of pulse period).
■ Since the timer latch in this mode is specialized for the read-out of measured values, do not
perform any write operation during measurement.
■ “FFFF16” is set to the timer when the timer underflows or when the valid edge of measurement
start/completion is detected. Consequently, the timer value at start of pulse width measurement
depends on the timer value just before measurement start.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-30
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
(4) Programmable waveform generating mode
✕ Set the double-function port of the CNTR
2
pin and port P4 to output.
7
(5) Programmable one-shot generating mode
✕ Set the double-function port of CNTR
2
pin and port P4
7
to output, and of INT
1
pin and port P4 to
2
input in this mode.
✕ This mode cannot be used in low-speed mode.
✕ If the value of the CNTR active edge switch bit is changed during one-shot generating enabled
or generating one-shot pulse, then the output level from CNTR pin changes.
2
2
(6) All modes
✕Timer Z write control
Which write control can be selected by the timer Z write control bit (bit 3) f the timer Z mode
register (address 002A16), writing data to both the latch and the timer at e time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected, the set to the timer latch
by writing data to the address of timer Z and the timer is updatxt underflow. After reset
release, the operation “writing data to both the latch and the tthe same time” is selected,
and the value is set to both the latch and the timer at the saby writing data to the address
of timer Z.
In the case of writing data only to the latch, if writito the latch and an underflow are
performed almost at the same time, the timer valuecome undefined.
✕Timer Z read control
A read-out of timer value is impossible in pulse peasurement mode and pulse width measurement
mode. In the other modes, a read-out of tie is possible regardless of count operating or
stopped.
However, a read-out of timer latch vampossible.
✕Switch of interrupt active edge o
2
and INT
1
Each interrupt active edge depesetting of the CNTR
active edge selection bit.
2
active edge switch bit and the INT
1
✕Switch of count source
When switching the couce by the timer Z count source selection bits, the value of timer
count is altered in inrable amount owing to generating of thin pulses on the count input
signals.
Therefore, selecmer count source before setting the value to the prescaler and the timer.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-31
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3.6 Notes on serial interface
(1) Notes when selecting clock synchronous serial I/O
✕ Stop of transmission operation
As for serial I/Oi (i = 1, 3) that can be used as either a clock synchronous or an asynchronous
(UART) serial I/O, clear the serial I/Oi enable bit and the transmit enable bit to “0” (serial I/Oi and
transmit disabled).
✕ Reason
Since transmission is not stopped and the transmission circuit is not initialized even if only the
serial I/Oi enable bit is cleared to “0” (serial I/Oi disabled), the internal transmission is running (in
this case, since pins TxDi, RxDi, SCLKi, and SRDYi function as I/O ports, thransmission data is
not output). When data is written to the transmit buffer register in this data starts to be
shifted to the transmit shift register. When the serial I/Oi enable bit is “1” at this time, the
data during internally shifting is output to the TxDi pin and an opeailure occurs.
✕ Stop of receive operation
As for serial I/Oi (i = 1, 3) that can be used as either a clchronous or an asynchronous
(UART) serial I/O, clear the receive enable bit to “0” (rdisabled), or clear the serial I/Oi
enable bit to “0” (serial I/Oi disabled).
✕ Stop of transmit/receive operation
As for serial I/Oi (i = 1, 3) that can be used r a clock synchronous or an asynchronous
(UART) serial I/O, clear both the transmit bit and receive enable bit to “0” (transmit and
receive disabled).
(when data is transmitted and receiveclock synchronous serial I/O mode, any one of data
transmission and reception cannot ped.)
✕ Reason
In the clock synchronous smode, the same clock is used for transmission and reception.
If any one of transmissireception is disabled, a bit error occurs because transmission and
reception cannot be nized.
In this mode, the cluit of the transmission circuit also operates for data reception. Accordingly,
the transmissiot does not stop by clearing only the transmit enable bit to “0” (transmit
disabled). Alsransmission circuit is not initialized by clearing the serial I/Oi enable bit to “0”
(serial I/Oed) (refer to ✕ in (1) ).
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-32
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
(2) Notes when selecting clock asynchronous serial I/O
✕ Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled). The transmission operation does not stop
by clearing the serial I/Oi enable bit (i = 1, 3) to “0”.
✕ Reason
This is the same as ✕ in (1).
✕ Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
✕ Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled). The transmission otion does not stop
by clearing the serial I/Oi enable bit (i = 1, 3) to “0”.
✕ Reason
This is the same as ✕ in (1).
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
(3) SRDYi (i = 1, 3) output of reception side
When signals are output from the SRDYi pin on the rside by using an external clock in the
clock synchronous serial I/O mode, set all of the renable bit, the SRDYi output enable bit, and
the transmit enable bit to “1” (transmit enabled)
(4) Setting serial I/Oi (i = 1, 3) control regisin
Set the serial I/Oi control register again e transmission and the reception circuits are reset
by clearing both the transmit enable bhe receive enable bit to “0.”
Cleae transmit enable
bnd the receive enable
E) to “0”
↓
Set the bits 0 to 3 and bit 6 of the
serial I/Oi control register
Can be set with the
↓
LDM instruction at
Set both the transmit enable bit
(TE) and the receive enable bit
(RE), or one of them to “1”
the same time
Fig. 3.3.3 Sequence of setting serial I/Oi (i = 1, 3) control register again
(5) Data transmission control with referring to transmit shift register completion flag
After the transmit data is written to the transmit buffer register, the transmit shift register completion flag
changes from “1” to “0” with a delay of 0.5 to 1.5 shift clocks. When data transmission is controlled with
referring to the flag after writing the data to the transmit buffer register, note the delay.
(6) Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLKi (i = 1, 3) input level. Also, write the transmit data to the transmit
buffer register at “H” of the SCLKi input level.
Rev.1.00 Jan 14, 2005
3-33
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
(7) Transmit interrupt request when transmit enable bit is set
When using the transmit interrupt, take the following sequence.
➀ Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “0” (disabled).
➀ Set the tranasmit enable bit to “1”.
➀ Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to “0” after 1 or more instruction has
executed.
➀ Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to “1” (enabled).
➀ Reason
When the transmission enable bit is set to “1”, the transmit buffer empty flag and transmit shift
register shift completion flag are also set to “1”.
Therefore, regardless of selecting which timing for the generating of transmit interrupts, the interrupt
request is generated and the transmit interrupt request bit is set at this pot.
(8) Writing to baud rate generator i (BRGi) (i = 1, 3)
Write data to the baud rate generator i (BRGi) (i = 1, 3) while the traon/reception operation
is stopped.
3.3.7 Notes on multi-master I2C-BUS interface
(1) Read-modify-write instruction
Each register of the multi-master I2C-BUS interface hto change by hardware. The precautions
when the read-modify-write instruction such as SB etc. is executed for each register of the
multi-master I2C-BUS interface are described
➀ I2C data shift register (S0: address
When executing the read-modify-writction for this register during transfer, data may become
a value not intended.
➀ I2C slave address registers S0D0 to S0D2: addresses 0FF716 to 0FF916
)
When the read-modify-write on is executed for this register at detecting the STOP condition,
data may become a valutended.
➀ Reason
________
It is because hardwnges the read/write bit (RWB) at detecting the STOP condition.
➀ I2C status regisaddress 001316
)
Do not executad-modify-write instruction for this register because all bits of this register
are changerdware.
➀ I2C contster (S1D: address 001416
)
When the d-modify-write instruction is executed for this register at detecting the START condition
or at completing the byte transfer, data may become a value not intended.
➀ Reason
Because hardware changes the bit counter (BC0 to BC2).
➀ I2C clock control register (S2: address 001516
)
The read-modify-write instruction can be executed for this register.
➀ I2C START/STOP condition control register (S2D: address 001616
The read-modify-write instruction can be executed for this register.
)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-34
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
(2) START condition generating procedure using multi-master
✕ Procedure example (The necessary conditions of the generating procedure are described as the
following ✕ to ✕).
LDA #SLADR
SEI
(Taking out of slave address value)
(Interrupt disabled)
BBS 5, S1, BUSBUSY (BB flag confirming and branch process)
BUSFREE:
STA S0
(Writing of slave address value)
(Trigger of START condition generating)
(Interrupt enabled)
LDM #$F0, S1
CLI
:
:
BUSBUSY:
CLI
(Interrupt enabled)
:
:
✕ Use “Branch on Bit Set” of “BBS 5, S1, –” for the BB flag confirmbranch process.
✕ Use “STA, STX” or “STY” of the zero page addressing instructiriting the slave address
value to the I2C data shift register (S0: address 001116).
✕ Execute the branch instruction of above ✕ and the store instf above ✕ continuously shown
by the above procedure example.
✕ Disable interrupts during the following three process
• BB flag confirming
• Writing of slave address value
• Trigger of START condition generating
(3) RESTART condition generating proceduaster
✕ Procedure example (The necessary cs of the generating procedure are described as the
following ✕ to ✕). Execute the follrocedure when the PIN bit is “0”.
LDM #$00, S1
LDA #SLADR
SEI
slave receive mode)
ng out of slave address value)
terrupt disabled)
STA S0
LDM #$F0, S
(Writing of slave address value)
(Trigger of RESTART condition generating)
(Interrupt enabled)
CLI
:
:
✕ Select the seive mode when the PIN bit is “0”. Do not write “1” to the PIN bit. The TRX bit
becomes the SDA pin is released.
✕ The SCis released by writing the slave address value to the I2C data shift register.
✕ Disable interrupts during the following two process steps:
• Writing of slave address value
(4) Writing to I2C status register (S1: address 001316
)
Do not execute an instruction to set the PIN bit to “1” from “0” and an instruction to set the MST and
TRX bits to “0” from “1” simultaneously. It is because it may enter the state that the SCL pin is
released and the SDA pin is released after about one machine cycle. Do not execute an instruction
to set the MST and TRX bits to “0” from “1” simultaneously when the PIN bit is “1”. It is because it
may become the same as above.
(5) Writing to I2C clock control register (S2: address 001516
)
Do not write data into the I2C clock control register during transfer. If data is written during transfer,
the I2C clock generator is reset, so that data cannot be transferred normally.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-35
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
(6) Switching of SCL/SDA interrupt pin polarity selection bit, SCL/SDA interrupt pin selection bit,
I2C-BUS interface enable bit
When changing the setting of the SCL/SDA interrupt pin polarity selection bit, the SCL/SDA interrupt
pin selection bit, or the I2C-BUS interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the interrupt before the SCL/SDA interrupt
pin polarity selection bit, the SCL/SDA interrupt pin selection bit, or the I2C-BUS interface enable bit
ES0 is set. Reset the request bit to “0” after setting these bits, and enable the interrupt.
(7) Process of after STOP condition generating in master mode
Do not write data in the I2C data shift register (S0) and the I2C status register (S1) until the bus busy
flag BB becomes “0” after generating the STOP condition in the master mode. It is because the
STOP condition waveform might not be normally generated. Reading to the above registers does not
have the problem.
(8) ES0 bit switch
In standard clock mode when SSC = “00010
“1” if ES0 bit is set to “1” when SDA is “L”.
Countermeasure:
2
” or in high-speed clock flag BB may switch to
Set ES0 to “1” when SDA is “H”.
• Trigger of RESTART condition generating
3.3.8 Notes on programming for SMBUS interface
(1) Time out process
For a smart battery system, the time out prith a program is required so that the communication
can be completed even when commuis interrupted. It is because there is possibility of
extracting a battery from a PC.
The specifications are defined so mmunication has been able to be completed within 25 ms
from START condition to STOP on and within 10 ms from the ACK pulse to the ACK pulse of
each byte. Accordingly, the g two should be considered as count start conditions.
✕ SDA falling edge cby SCL/SDA interrupt
This is the countere for a communication interrupt in the middle of from START condition
to a slave addwever, the detection condition must be considered because a interrupt is
also generaommunication from other masters to other slaves.
✕ SMBUS it after receiving slave address
This is tntermeasure for when communication is interrupted from receiving a slave address
until receivng a command.
(2) Low hold of communication line
The I2C-BUS interface conforms to the I2C-BUS Standard Specifications. However, because the use
condition of SMBUS differs from the I2C-BUS’s, there is possibility of occurrence of the following
problem.
✕ Low hold of SDA line caused by ACK pulse at voltage drop of communication line
When the SMBUS voltage slowly drops, that is caused by extracting a battery from equipment or
turning off a PC’s power or etc., it might be incorrectly treated as the SCL pulse near the threshold
level voltage.
When the SDA is judged “L” in that condition, it becomes the general call and the ACK is transmitted.
However, when the SCL remains “L” at the ACK pulse, the SDA continuously remains “L” until
input of the next SCL pulse.
Rev.1.00 Jan 14, 2005
3-36
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
Countermeasure:
As explained before, start the time out count at the falling of SDA line of START condition and
reset ES0 bit of the S1D register when the time out is satisfied (Note).
Note: Do not use the read-modify-write instruction at this time. Furthermore, when the ES0 bit is
set to “0”, it becomes a general-purpose port ; so that the port must be set to input mode
or “H”.
3.3.9 Notes on PWM
The PWM starts from “H” level after the PWM enable bit is set to enable and “L” level is temporarily output
from the PWM pin.
The length of this “L“ level output is as follows:
n + 1
2 • f(XIN
(s)
(s)
(Count source selection bit = “0”, where n is the value sprescaler)
(Count source selection bit = “1”, where n is the et in the prescaler)
)
n + 1
f(XIN
)
3.3.10 Notes on A/D converter
(1) Analog input pin
Make the signal source impedance for analog i, or equip an analog input pin with an external
capacitor of 0.01 µF to 1 µF. Further, be serify the operation of application products on the
user side.
✕ Reason
An analog input pin includes acitor for analog voltage comparison. Accordingly, when
signals from signal source gh impedance are input to an analog input pin, charge and
discharge noise generatemay cause the A/D conversion precision to be worse.
(2) A/D converter power e pin
The AVSS pin is A/rter power source pins. Regardless of using the A/D conversion function
or not, connect owing :
• AVSS : Conthe VSS line
✕ Reason
If the AVSS pin is opened, the microcomputer may have a failure because of noise or others.
(3) Clock frequency during A/D conversion
The comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock
frequency is too low. Thus, make sure the following during an A/D conversion.
• f(XIN) is 500 kHz or more
• Do not execute the STP instruction
(4) Difference between at 8-bit reading in 10-bit A/D mode and at 8-bit A/D mode
At 8-bit reading in the 10-bit A/D mode, “–1/2 LSB” correction is not performed to the A/D conversion
result.
In the 8-bit A/D mode, the A/D conversion characteristics is the same as 3802 group’s characteristics
because “–1/2 LSB” correction is performed.
Rev.1.00 Jan 14, 2005
3-37
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3.11 Notes on D/A converter
(1) Vcc when using D/A converter
The D/A converter accuracy when Vcc is 4.0 V or less differs from that of when Vcc is 4.0 V or more.
When using the D/A converter, we recommend using a Vcc of 4.0 V or more.
(2) DAi conversion register when not using D/A converter
When a D/A converter is not used, set all values of the DAi conversion registers (i = 1, 2) to “0016”.
The initial value after reset is “0016”.
3.3.12 Notes on watchdog timer
✕Make sure that the watchdog timer H does not underflow while waiting Stop rease, because the
watchdog timer keeps counting during that term.
✕When the STP instruction disable bit has been set to “1”, it is impossible to so “0” by a program.
3.3.13 Notes on RESET pin
Connecting capacitor
In case where the RESET signal rise time is long, connect ic capacitor or others across the
RESET pin and the VSS pin. Use a 1000 pF or more tor for high frequency use. When
connecting the capacitor, note the following :
• Make the length of the wiring which is connecteapacitor as short as possible.
• Be sure to verify the operation of application s on the user side.
✕ Reason
____________
If the several nanosecond or several tsecond impulse noise enters the RESET pin, it may
cause a microcomputer failure.
3.3.14 Notes on low-speed operatie
(1) Using sub-clock
To use a sub-clock, fix the CPU mode
X
CIN
XCOUT
register to “1” or conRd (refer to Figure
3.3.4) resistance o a certain level to
stabilize an os. For resistance value
of Rd, consoscillator manufacturer.
Rf
Rd
C
CIN
CCOUT
✕ Reason
When bit 3 of the CPU mode register is set
to “0”, the sub-clock oscillation may stop.
Fig. 3.3.4 Ceramic resonator circuit
(2) Switch between middle/high-speed mode and low-speed mode
If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations.
The sufficient time is required for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode between middle/high-speed and low-
speed, set the frequency on condition that f(XIN) > 3f(XCIN).
Rev.1.00 Jan 14, 2005
3-38
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3.15 Quartz-crystal oscillator
When using the quartz-crystal oscillator of high frequency, such as 16 MHz etc., it may be necessary to
select a specific oscillator with the specification demanded.
3.3.16 Notes on restarting oscillation
(1) Restarting oscillation
Usually, when the MCU stops the clock oscillation by STP instruction and the STP instruction has
been released by an external interrupt source, the fixed values of Timer 1 and Prescaler 12 (Timer
1 = “0116”, Prescaler 12 = “FF16”) are automatically reloaded in order for the oscillation to stabilize.
The user can inhibit the automatic setting by writing “1” to bit 0 of MISRG (address 001016).
However, by setting this bit to “1”, the previous values, set just before the TP instruction was
executed, will remain in Timer 1 and Prescaler 12. Therefore, you will neet an appropriate
value to each register, in accordance with the oscillation stabilizing timeexecuting the STP
instruction.
✕ Reason
Oscillation will restart when an external interrupt is receiveder, internal clock φ is supplied
to the CPU only when Timer 1 starts to underflow. This eime for the clock oscillation using
the ceramic resonators to be stabilized.
3.3.17 Notes on using stop mode
✕Register setting
Since values of the prescaler 12 and Tie automatically reloaded when returning from the
stop mode, set them again, respectWhen the oscillation stabilizing time set after STP
instruction released bit is “0”)
✕Clock restoration
After restoration from the de to the normal mode by an interrupt request, the contents of
the CPU mode register to the STP instruction execution are retained. Accordingly, if both
main clock and sub cre oscillating before execution of the STP instruction, the oscillation
of both clocks is rat restoration.
In the above can the main clock side is set as a system clock, the oscillation stabilizing
time until the underflow is reserved at restoration from the stop mode.
When the on stabilizing time set after STP instruction released bit is “0”, the time for 512
counts ount source become the oscillation stabilizing time. When the oscillation stabilizing
time set ar STP instruction released bit is “1”, an arbitrarily count value set to the prescaler 12
and the timer 1 become the oscillation stabilizing time.
At this time, note that the oscillation on the sub clock side may not be stabilized even after the
lapse of the oscillation stabilizing time of the main clock side.
Rev.1.00 Jan 14, 2005
3-39
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
3.3.18 Notes on wait mode
✕Clock restoration
If the wait mode is released by a reset when XCIN is set as the system clock and XIN oscillation is
stopped during execution of the WIT instruction, XCIN oscillation stops, XIN oscillations starts, and
X
IN is set as the system clock.
In the above case, the RESET pin should be held at “L” until the oscillation is stabilized.
3.3.19 Notes on CPU rewrite mode
(1) Operation speed
During CPU rewrite mode, set the system clock φ 4.0 MHz or less using the main clock division ratio
selection bits (bits 6 and 7 of address 003B16).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash memory cannsed during the CPU
rewrite mode.
(3) Interrupts inhibited against use
The interrupts cannot be used during the CPU rewrite mode becey refer to the internal data
of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running alreadternal reset generated by watchdog
timer underflow does not happen, because of watchdr is always clearing during program or
erase operation.
(5) Reset
Reset is always valid. In case of CNVSS = “Hreset is released, boot mode is active. So the
program starts from the address containeress FFFC16 and FFFD16 in boot ROM area.
3.3.20 Notes on programming
(1) Processor status register
✕ Initializing of processs register
Flags which affect pexecution must be initialized after a reset.
In particular, it is al to initialize the T and D flags because they have an important effect
on calculations
✕ Reason
After , the contents of the processor status register (PS) are undefined except for the I
flag whis “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig. 3.3.5 Initialization of processor status register
Rev.1.00 Jan 14, 2005
3-40
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
✕ How to reference the processor status register
To reference the contents of the processor status register (PS), execute the PHP instruction once
then read the contents of (S+1). If necessary, execute the PLP instruction to return the PS to its
original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction execution
(S)
↓
(S)+1
Stored PS
NOP
Fig. 3.3.6 Sequence of PLP instruction execution
Fig. 3.3.7 Stack mcontents after PHP
instruxecution
(2) BRK instruction
✕ Interrupt priority level
When the BRK instruction is executed with the follonditions satisfied, the interrupt execution
is started from the address of interrupt vector as the highest priority.
• Interrupt request bit and interrupt enable bet to “1”.
• Interrupt disable flag (I) is set to “1” to interrupt.
(3) Decimal calculations
✕ Execution of decimal calculat
The ADC and SBC are the tructions which will yield proper decimal notation, set the
decimal mode flag (D) to “1e SED instruction. After executing the ADC or SBC instruction,
execute another instructre executing the SEC, CLC, or CLD instruction.
✕ Notes on status flecimal mode
When decimal melected, the values of three of the flags in the status register (the N, V,
and Z flags) aid after a ADC or SBC instruction is executed.
The carry fls set to “1” if a carry is generated as a result of the calculation, or is cleared
to “0” if a is generated. To determine whether a calculation has generated a carry, the C
flag musnitialized to “0” before each calculation. To check for a borrow, the C flag must be
initialized t“1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 3.3.8 Status flag at decimal calculations
Rev.1.00 Jan 14, 2005
3-41
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.3 Notes on use
(4) JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address on a
page as an indirect address.
(5) Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
• The execution of these instructions does not change the contents of the processor status register.
(6) Ports
The contents of the port direction registers cannot be read. The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The instruction with the addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direister.
Use instructions such as LDM and STA, etc., to set the port directiors.
3.3.21 Notes on flash memory version
The CNVss pin determines the flash memory mode. To improve se reduction, connect a track
between CNVss pin and Vss pin or Vcc pin with 1 to 10km resiThe mask ROM version track of
CNVss pin has no operational interference even if it is conneVss pin or Vcc pin via a resistor.
3.3.22 Notes on electric characteristic differences betwsk ROM and flash nemory version MCUs
There are differences in electric characteristics, opeargin, noise immunity, and noise radiation
between Mask ROM and Flash Memory version MCUthe difference in the manufacturing processes,
built-in ROM, and layout pattern etc. When manng an application system with the Flash Memory
version and then switching to use of the Mask ersion, please conduct evaluations equivalent to the
system evaluations conducted for the flash y version.
3.3.23 Notes on handling of power pins
In order to avoid a latch-up occuconnect a capacitor suitable for high frequencies as bypass
capacitor between power source c pin) and GND pin (Vss pin), and between power source pin (Vcc
pin) and analog power source n (AVss pin). Besides, connect the capacitor to as close as possible.
For bypass capacitor whild not be located too far from the pins to be connected, a ceramic
capacitor of 0.01 µF–0.recommended.
3.3.24 Power Soutage
When the power voltage value of a microcomputer is less than the value which is indicated as the
recommended openg conditions, the microcomputer does not operate normally and may perform unstable
operation.
In a system where the power source voltage drops slowly when the power source voltage drops or the
power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended
operating conditions and design a system not to cause errors to the system by this unstable operation.
Rev.1.00 Jan 14, 2005
3-42
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
3.4 Countermeasures against noise
Countermeasures against noise are described below. The following countermeasures are effective against
noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use.
3.4.1 Shortest wiring length
The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer.
(1) Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as short as possible. Especially,
connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within
20 mm).
✕ Reason
The width of a pulse input into the RESET pin is determined by the timing cessary conditions.
If noise having a shorter pulse width than the standard is input to the pin, the reset is
released before the internal state of the microcomputer is completely d. This may cause
a program runaway.
Noise
Reset
circuit
Reset
circuit
RESET
RESET
V
SS
V
SS
V
SS
V
SS
N.G.
O.K.
Fig. 3.4.1 Wiring for the RESE
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-43
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
(2) Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is
connected to an oscillator and the VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns.
✕ Reason
If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program
failure or program runaway. Also, if a potential difference is caused by the noise between the VSS
level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in
the microcomputer.
Noise
X
X
V
IN
X
OUT
SS
O.K.
N.G.
Fig. 3.4.2 Wiring for clock I/O pins
(3) Wiring to CNVss pin
Connect the CNVss pin to the Vss pthe shortest possible wiring.
✕ Reason
The processor mode of a omputer is influenced by a potential at the CNVss pin. If a
potential difference is cathe noise between pins CNVss and Vss, the processor mode may
become unstable. Thcause a microcomputer malfunction or a program runaway.
Noise
CNVSS
CNVSS
V
SS
V
SS
O.K.
N.G.
Fig. 3.4.3 Wiring for CNVss pin
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-44
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
3.4.2 Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin.
V
CC
V
CC
V
SS
V
SS
N.G.
O
Fig. 3.4.4 Bypass capacitor across the VSS line and the VC
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-45
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
3.4.3 Wiring to analog input pins
• Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog
input pin in series. Besides, connect the resistor to the microcomputer as close as possible.
• Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides,
connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog
input pin and the VSS pin at equal length.
✕ Reason
Signals which is input in an analog input pin (such as an A/D converter/comparator input pin) are
usually output signals from sensor. The sensor which detects a change of event is installed far
from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer
necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer,
which causes noise to an analog input pin.
If a capacitor between an analog input pin and the VSS pin is grounded at ion far away from
the VSS pin, noise on the GND line may enter a microcomputer throuapacitor.
Noise
(Note)
Micuter
nalog
Thermistor
input pin
N.
.K.
V
SS
he resistor is used for dividing
resistance with a thermistor.
Fig. 3.4.5 Analog signal line resistor and a capacitor
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-46
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
3.4.4 Oscillator concerns
Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected
by other signals.
(1) Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a
current larger than the tolerance of current value flows.
✕ Reason
In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and
thermal heads or others. When a large current flows through those signal lines, strong noise
occurs because of mutual inductance.
Microcomputer
Mutual inductance
M
X
X
IN
Large
current
OUT
V
SS
GND
Fig. 3.4.6 Wiring for a large current signal line
(2) Installing oscillator away from signal lines wotential levels change frequently
Install an oscillator and a connecting pattern scillator away from signal lines where potential
levels change frequently. Also, do not crossignal lines over the clock lines or the signal lines
which are sensitive to noise.
✕ Reason
Signal lines where potential lenge frequently (such as the CNTR pin signal line) may affect
other lines at signal rising ealling edge. If such lines cross over a clock line, clock waveforms
may be deformed, whics a microcomputer failure or a program runaway.
N.G.
CNTR
Do not cross
X
X
V
IN
OUT
SS
Fig. 3.4.7 Wiring of signal lines where potential levels change frequently
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-47
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
(3) Oscillator protection using VSS pattern
As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the
position (on the component side) where an oscillator is mounted.
Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides,
separate this VSS pattern from other VSS patterns.
An example of VSS patterns on the
underside of a printed circuit board
Oscillator wiring
pattern example
X
X
V
IN
OUT
SS
Separate the VSS line for oscillation from other VSS l
Fig. 3.4.8 VSS pattern on the underside of an oscillator
3.4.5 Setup for I/O ports
Setup I/O ports using hardware and software as follows:
<Hardware>
• Connect a resistor of 100 Ω or more to an in series.
<Software>
• As for an input port, read data seves by a program for checking whether input levels are
equal or not.
• As for an output port, since the data may reverse because of noise, rewrite data to its port
latch at fixed periods.
• Rewrite data to direction s and pull-up control registers at fixed periods.
Noise
O.K.
Data bus
Noise
Direction register
N.G.
Port latch
I/O port
pins
Fig. 3.4.9 Setup for I/O ports
Rev.1.00 Jan 14, 2005
3-48
REJ09B0212-0100Z
APPENDIX
3804 Group (Spec.H)
3.4 Countermeasures against noise
3.4.6 Providing of watchdog timer function by software
If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer
and the microcomputer can be reset to normal operation. This is equal to or more effective than program
runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer
provided by software.
In the following example, to reset a microcomputer to normal operation, the main routine detects errors of
the interrupt processing routine and the interrupt processing routine detects errors of the main routine.
This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
<The main routine>
• Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value
N in the SWDT once at each execution of the main routine. The initial value N should satisfy the
following condition:
N+1 ≥ ( Counts of interrupt processing executed in each main routine)
As the main routine execution cycle may change because of an intecessing or others,
the initial value N should have a margin.
• Watches the operation of the interrupt processing routine by comthe SWDT contents with
counts of interrupt processing after the initial value N has b
• Detects that the interrupt processing routine has failed and ines to branch to the program
initialization routine for recovery processing in the follose:
If the SWDT contents do not change after interrupt ing.
<The interrupt processing routine>
• Decrements the SWDT contents by 1 at eacupt processing.
• Determines that the main routine operatelly when the SWDT contents are reset to the
initial value N at almost fixed cycles (aed interrupt processing count).
• Detects that the main routine has fadetermines to branch to the program initialization
routine for recovery processing in owing case:
If the SWDT contents are not ito the initial value N but continued to decrement and if
they reach 0 or less.
Interrupt processing routine
(SWDT) ← (SWDT)—1
Interrupt processing
Main routine
(SWDT)← N
CLI
Main processing
>0
(SWDT)
≤0?
RTI
≠N
≤0
(SWDT)
=N?
Return
N
Interrupt processing
routine errors
Main routine
errors
Fig. 3.4.10 Watchdog timer by software
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-49
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
3.5 Control registers
Port Pi
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi (i = 0, 1, 2, 3, 4, 5, 6)
(Pi: addresses 000016, 000216, 000416, 000616, 000816, 000A16, 000C16
)
b
Name
Functions
At reset R W
0
1
2
3
4
5
6
7
Port Pi
0
1
2
3
4
5
6
7
0
0
0
0
0
✕In output mode
Write •••••••• Port latch
Read •••••••• Port latch
✕In input mode
Write •••••••• Port latch
Read •••••••• Value of pin
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Port Pi
Fig. 3.5.1 Structure of Port Pi
Port Pi direction register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi direction registe2, 3, 4, 5, 6)
(PiD: addresses 000, 000516, 000716, 000916, 000B16, 000D16)
b
0
Na
Port P
regi
Functions
At reset R W
0
0 : Port Pi
0
input mode
output mode
1 : Port Pi
0
0 : Port Pi
1 : Port Pi
1
1
input mode
output mode
0
0
0
0
0
0
0
1
4
5
6
7
0 : Port Pi
1 : Port Pi
2
2
input mode
output mode
0 : Port Pi
1 : Port Pi
3
3
input mode
output mode
0 : Port Pi
1 : Port Pi
4
4
input mode
output mode
0 : Port Pi
1 : Port Pi
5
5
input mode
output mode
0 : Port Pi
1 : Port Pi
6
6
input mode
output mode
0 : Port Pi
1 : Port Pi
7
7
input mode
output mode
Fig. 3.5.2 Structure of Port Pi direction register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-50
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Timer 12, X count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer 12, X count source selection register
(T12XCSS: address 000E16
)
b
0
Name
Functions
At reset R W
b3b2b1b0
Timer 12 count
source selection
bits
1
1
0
1
1
0 0 0 0: f(XIN)/2 or f(XCIN)/2
0 0 0 1: f(XIN)/4 or f(XCIN)/4
0 0 1 0: f(XIN)/8 or f(XCIN)/8
0 0 1 1: f(XIN)/16 or f(XCIN)/16
0 1 0 0: f(XIN)/32 or f(XCIN)/32
0 1 0 1: f(XIN)/64 or f(XCIN)/64
0 1 1 0: f(XIN)/128 or f(XCIN)/128
0 1 1 1: f(XIN)/256 or f(XCIN)/256
1 0 0 0: f(XIN)/512 or f(XCIN)/512
1 0 0 1: f(XIN)/1024 or f(XCIN)/1024
1010 to 1111: Not available
1
2
3
4
b7b6b5b4
Timer X count
source selection
bits
0 0 0 0: f(XIN)/2 or f(X
0 0 0 1: f(XIN)/4 or f
0 0 1 0: f(XIN)/8 o
0 0 1 1: f(XIN)/)/16
0 1 0 0: f(XICIN)/32
0 1 0 1: f(f(XCIN)/64
0 1 1 0or f(XCIN)/128
0 1 56 or f(XCIN)/256
1 )/512 or f(XCIN)/512
XIN)/1024 or f(XCIN)/1024
5
6
7
0
0
f(XCIN
)
to 1111: Not available
Fig. 3.5.3 Structure of Timer 12, X coune selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-51
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Timer Y, Z count source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Y, Z count source selection register
(TYZCSS: address 000F16
)
b
0
Name
Functions
At reset R W
b3b2b1b0
Timer Y count
source selection
bits
1
1
0
1
1
0
0 0 0 0: f(XIN)/2 or f(XCIN)/2
0 0 0 1: f(XIN)/4 or f(XCIN)/4
0 0 1 0: f(XIN)/8 or f(XCIN)/8
0 0 1 1: f(XIN)/16 or f(XCIN)/16
0 1 0 0: f(XIN)/32 or f(XCIN)/32
0 1 0 1: f(XIN)/64 or f(XCIN)/64
0 1 1 0: f(XIN)/128 or f(XCIN)/128
0 1 1 1: f(XIN)/256 or f(XCIN)/256
1 0 0 0: f(XIN)/512 or f(XCIN)/512
1 0 0 1: f(XIN)/1024 or f(XCIN)/1024
1
2
3
4
5
1 0 1 0: f(XCIN
)
1011 to 1111: Not available
b7b6b5b4
Timer Z count
source selection
bits
0 0 0 0: f(XIN)/2 or f(X
0 0 0 1: f(XIN)/4 or
0 0 1 0: f(XIN)/8
0 0 1 1: f(XIN)N)/16
0 1 0 0: f(XCIN)/32
0 1 0 1: ff(XCIN)/64
0 1 1 or f(XCIN)/128
0 1 56 or f(XCIN)/256
1 )/512 or f(XCIN)/512
XIN)/1024 or f(XCIN)/1024
6
7
0
: f(XCIN
)
to 1111: Not available
Fig. 3.5.4 Structure of Timer Y, Z corce selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-52
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
MISRG
b7 b6 b5 b4 b3 b2 b1 b0
MISRG
(MISRG: address 001016
)
b
Name
Functions
At reset R W
0 Oscillatin stabilizing 0: Automatically set (Note 1)
0
time set after STP
1: Autimatically set disabled
instrution released bit
0: Not set automatically
1: Automatic switching
enabled (Notes 2, 3)
Middle-speed mode
automatic switch set
bit
0
1
0: 4.5 to 5.5 machine cycles
1: 6.5 to 7.5 machine cycles
0
2 Middle-speed mode
automatic switch
wait time set bit
Middle-speed mode 0: Invalid
3
automatic switch
start bit
1: Automatic switch start
(Note 3)
(Depending on
program)
4
5
6
7
Nothing is arranged for these bits. The
write disabled bits. When these bits
out, the contents are “0”.
0
0
0
0
✕
✕
✕
✕
Notes 1: “0116” is set to Timer 1, “FF16” is scaler 12.
2: During operation in low-speed is possible automatically to switch to
middle-speed mode owing ng of SCL/SDA.
3: When automatic switch speed mode from low-speed mode occurs,
the values of CPU mer (003B16) change.
Fig. 3.5.5 Structure of MISRG
2
I C data shift regi
b7 b6 b5 b4 b3 b
I2C data shift register
(S0: address 001116
)
b
Functions
At reset R W
0
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
• 8-bit shift register to store receive data and
write transmit data.
1
2
3
4
5
6
7
Note: When data is written to I2C data shift register after the MST
bit is set to “0” (slave mode), keep the interval for 8 machine
cycles or more.
Also, when the read-modify-write instructions (SEB, CLB) are
used during data transfer, the values may be undefined.
Fig. 3.5.6 Structure of I2C data shift register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-53
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
2
I C special mode status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C special mode status register
(S3: address 001216
)
b
0
Name
Functions
At reset R W
Slave address 0
comparison flag
(AAS0)
✕
0: Address disagreement
1: Address agreement
(Notes 1, 2)
0
0
0
✕
1
2
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Slave address 1
comparison flag
(AAS1)
Slave address 2
comparison flag
(AAS2)
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
1
0
3
4
✕
✕
✕
Nothing is arranged for this bit. This is
disabled bit. When this bit is read o
contents are undefined.
0: SCL pld
1: SCrelease
(3)
SCL pin low hold 2
flag (PIN2)
5
6
7
Nothing is arranged fThis is a write
disabled bit. When read out, the
contents are “0”
✕
✕
STOP condi
flag (SPC
: No detection
1: Detection (Notes 1, 4)
0
Notes 1: These bigs can be read out, but cannot be written.
2: These be detected only when the data format selection bit
(Acontrol register is set to “0”.
3: Tinitialized to “1” at reset, when the ACK interrupt control bit
r when writing “1” to the SCL pin low hold 2 flag set bit.
bit is initialized to “0” at reset, when the I2C-BUS interface
nable bit (ES0) is “0”, or when writing “1” to the STOP condition
flag clear bit.
Fig. 3.5.7 StructI2C special mode status register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-54
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
2
I C status register
b7 b6 b5 b4 b3 b2 b1 b0
I2C status register
(S1: address 001316)
b
0
Name
Last receive bit
(LRB)
Functions
0: Last bit = “0”
1: Last bit = “1” (Note 1)
At reset R W
Undefined
General call
detection flag
(AD0)
0
0: No general call detected
1: General call detected
(Notes 1, 2)
1
2
Slave address
comparison flag
(AAS)
0
0: Address disagreement
1: Address agreement
(Notes 1, 2)
Arbitration lost
detection flag (AL)
0: Not detected
1: Detected (Note 1)
3
4
5
6
SCL pin low hold
bit (PIN)
0: SCL pin low hold (Note 3
1: SCL pin low release
0
Bus busy flag (BB)
0: Bus free
1: Bus busy
b7 b6
0
0
Communication
mode specification
bits (TRX, MST)
0 0: Slave rede
0 1: Slave mode
1 0: Mave mode
1 1: nsmit mode
7
Notes 1: These flags and bclusive to input. When writing to
these bits, writese bits.
2: These bits cected only when the data format
selection of I2C control register is set to “0”.
3: This bit et to “1” by program, but cannot be cleared
to “0
4: All hanged by hardware. Do not use the read-
rite instructions (SEB, CLB).
Fig. 3.5.8 Structure of I2C staister
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-55
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
2
I C control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C control register
(S1D: address 001416
)
b
0
Name
Bit counter
(Number of
transmit/receive
bits)
(BC0, BC1, BC2)
Functions
At reset R W
b2b1b0
0 0 0: 8
0
0
0
0 0 1: 7
0 1 0: 6
0 1 1: 5
1 0 0:
1 0 1:
1 1 0:
1 1 1:
1
2
4
3
2
1
I2C-BUS interface
enable bit (ES0)
Data format
0
0: Disabled
1: Enabled
3
4
5
0: Addressing format
selection bit (ALS) 1: Free data format
Addressing format
selection bit
(10BIT SAD)
0: 7-bit addressing form
1: 10-bit addressing fo
6
7
Nothing is arranged for this bit. This i
disabled bit. When this bit is read o
contents are “0”.
0
0
✕
I2C-BUS interface pin 0: SMB
input level selection 1: Ct
bit (TISS)
Note: Do not use the re-write instruction because some bits
change by haren the start condition is detected and
the byte-tranmpleted.
Fig. 3.5.9 Structure of I2C control reg
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-56
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
2
I C clock control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C clock control register
(S2: address 001516
)
b
0
Name
SCL frequency
control bits
(CCR0, CCR1,
CCR2, CCR3,
CCR4)
Functions
At reset R W
Standard High-speed
clock mode clock mode
Disabled Disabled
Disabled 333
Setting value
0
0
0
0
b4b3b2b1b0
00 to 02
03
1
2
04
(Note 2) 250
05
100
400 (Note 3)
06
83.3
166
500/CCR value 1000/CCR value
(Note 3) (Note 3)
3
4
5
1D
1E
1F
17.2
16.6
16.1
34.5
33.3
32.3
(φ = 4 MHz, Unit: kHz) (Note 1
SCL mode
specification bit
(FAST MODE)
0: Standard clock mode
1: High-speed clock m
6
7
ACK bit
(ACK BIT)
0
0
0: ACK is return
1: ACK is not
0: No ACK
1: ACK
ACK clock bit
(ACK)
Notes 1: Duty of SCL clock output is 50 %. The duty 35 to 45 % only when the high-
speed clock mode is selected and CCR v400 kHz, at φ = 4 MHz). H
duration of the clock fluctuates from —achine cycles in the standard clock
mode, and fluctuates from —2 to +2 cycles in the high-speed clock mode. In
the case of negative fluctuation, thcy does not increase because L
duration is extended instead of on reduction.
These are values when SCL chronization by the synchronous function is not
performed. CCR value is tal notation value of the SCL frequency control bits
CCR4 to CCR0.
2: Each value of SCL frexceeds the limit at φ = 4 MHz or more. When using
these setting valuf 4 MHz or less.
3: The data formufrequency is described below:
φ/(8 ✕ CCR ndard clock mode
φ/(4 ✕ CCHigh-speed clock mode (CCR value ≠ 5)
φ/(2 ✕ e) High-speed clock mode (CCR value = 5)
Do n2 as CCR value regardless of φ frequency.
Sz (max.) in the standard clock mode and 400 kHz (max.) in the high-speed
de to the SCL frequency by setting the SCL frequency control bits CCR4 to
.
Fig. 3.5.10 Structure of I2C clock control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-57
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
2
I C START/STOP condition control register
b7 b6 b5 b4 b3 b2 b1 b0
0
I2C START/STOP condition control register
(S2D: address 001616)
b
0
1
Name
Functions
At reset R W
START/STOP
condition set bits
(SSC0, SSC1,
SSC2, SSC3,
SSC4)
0
1
0
1
1
0
SCL release time
= φ (µs) ✕ (SSC+1)
Setup time
= φ (µs) ✕ (SSC+1)/2
Hold time
2
3
4
5
= φ (µs) ✕ (SSC+1)/2
SCL/SDA interrupt
pin polarity selection
bit (SIP)
0: Falling edge active
1: Rising edge active
6
SCL/SDA interrupt
pin selection bit
(SIS)
0: SDA valid
1: SCL valid
0
7 Fix this bit to 0 .
Note: Fix SSC0 to 0 . Also, do not set SSC4 to SSCalues or 000002 .
Fig. 3.5.11 Structure of I2C START/STOP condition controer
2
I C special mode control register
b7 b6 b5 b4 b3 b2 b1 b0
I2C special mode coer
0
0
(S3D: address 00
b
Functions
At reset R W
0
0
Fix 0 .
upt control
KICON)
0
1
0: At communication
completion
1: At falling of ACK clock and
communication completion
0
Slave address
0: One-byte slave address
compare mode
control bit (MSLAD)
1: Three-byte slave address
compare mode
0
✕
3
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are 0 .
4
5
Fix this bit to 0 .
SCL pin low hold 2
flag set bit (PIN2IN)
0
0
Writing 1 to this bit initializes
the SCL pin low hold 2 flag
to 1 . (Notes 1, 2)
SCL pin low hold
set bit (PIN2HD)
Writing 1 to this bit clears
the SCL pin low hold 2 flag to
0 and holds the SCL pin low.
(Notes 1, 2)
0
0
6
7
STOP condition flag
clear bit (SPFCL)
Writing 1 to this bit initializes
the STOP condition flag to
0 . (Note 1)
Notes 1: When 0 is written to these bits, nothing is happened.
2: Do not write 1 to these bits at the same time.
Fig. 3.5.12 Structure of I2C special mode control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-58
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Transmit/Receive buffer register 1, Transmit/Receive buffer register 3
b7 b6 b5 b4 b3 b2 b1 b0
Transmit/Receive buffer register 1 (TB1/RB1: address 001816
Transmit/Receive buffer register 3 (TB3/RB3: address 003016
)
)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
The transmission data is written to or the
receive data is read out from this buffer register.
• At write: A data is written to the transmit buffer
register.
• At read: The contents of the receive buffer
register are read out.
Note: The contents of transmit buffer register cannot be .
The data cannot be written to the receive buffe.
Fig. 3.5.13 Structure of Transmit/Receive buffer register 1, Transmit/e buffer register 3
Serial I/O1 status register, Serial I/O3 status regis
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 status register (SIO1ST001916)
Serial I/O3 status register (SIO3ss 003116)
b
0
Name
Transmit buffer
empty flag (T
Functions
uffer full
Buffer empty
At reset R W
✕
✕
✕
0
0
0
0: Buffer empty
1: Buffer full
Receive
flag (RB
1
2 Tran
ret
n flag
0: Transmit shift in progress
1: Transmit shift completed
errun error flag
0: No error
1: Overrun error
0
0
0
0
1
✕
✕
✕
✕
✕
(OE)
4
Parity error flag
(PE)
0: No error
1: Parity error
Framing error flag
(FE)
0: No error
1: Framing error
5
6
7
Summing error flag
(SE)
0: (OE) U (PE) U (FE) = 0
1: (OE) U (PE) U (FE) = 1
Nothing is arranged for this bit. This bit is a
write disabled bit. When this bit is read out, the
contents are “1”.
Fig. 3.5.14 Structure of Serial I/O1 status register, Serial I/O3 status register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-59
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIO1CON: address 001A16
)
b
Name
Functions
At reset R W
0 BRG count source
selection bit (CSS)
0
0: f(XIN)
1: f(XIN)/4
Serial I/O1
1
0
When clock synchronous
serial I/O is selected,
0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
synchronous clock
selection bit (SCS)
0: I/O port (P47)
1: SRDY1 output pin
S
RDY1 output
2
3
enable bit (SRDY)
0: Transmit buffer empty
1: Transmit shift operat
completion
Transmit interrupt
source selection
bit (TIC)
0: Transmit disa
1: Transmit en
Transmit enable bit
(TE)
0
0
0
4
5
6
Receive enable bit 0: Receive
(RE)
1: Receid
0: UA
Serial I/O1 mode
1: chronous
/O
selection bit (SIOM)
ial I/O1 disabled
Serial I/O1 enabl
bit (SIOE)
0
7
P4
: Serial I/O1 enabled
(P4 to P4 : Serial I/O pins)
4
to P4 : normal I/O pins)
7
4
7
Fig. 3.5.15 Structure of Serial I/O1 l register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-60
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
UART1 control register
b7 b6 b5 b4 b3 b2 b1 b0
UART1 control register
(UART1CON: address 001B16
)
b
0
Name
Functions
At reset R W
0
0
0
0
Character length
selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit
(PARE)
1
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
Parity selection bit
(PARS)
2
3
Stop bit length
selection bit (STPS) 1: 2 stop bits
0: 1 stop bit
P45
/TxD P-channel
1
4
0: CMOS output
(in output mode)
1: N-channel open-drain
output (in output m
output disable bit
(POFF)
5
6
7
Nothing is arranged for these bits. The
write disabled bits. When these bits
out, the contents are “1”.
1
1
1
✕
✕
✕
Fig. 3.5.16 Structure of UART1 control register
Baud rate generator i (i = 1, 3)
b7 b6 b5 b4 b3 b2 b1 b0
Baud rate i
(BRGi (dress 001C16, 002F16
)
b
Functions
At reset R W
3
4
5
6
7
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
a count value of baud rate generator.
Note: Write to this register while transmit/receive operation is stopped.
Fig. 3.5.17 Structure of Baud rate generator i
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-61
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Serial I/O2 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 control register
(SIO2CON: address 001D16
)
b
0
Name
Internal
synchronous clock
selection bits
Functions
At reset R W
b2b1b0
0
0
0
0
0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
1
2
3
4
5
6
Serial I/O2 port
selection bit
0: I/O port (P51, P52)
1: SOUT2, SCLK2 signal output
SRDY2 output
enable bit
Transfer direction
selection bit
0: I/O port (P53)
1: SRDY2 signal output
0: LSB first
1: MSB first
0: External clock
1: Internal clock
Serial I/O2
synchronous
clock selection bit
P5
1
/SOUT2
0: CMOS outpu
0
7
P-channel output
disable bit
(in output
1: N-chandrain
outpuut mode)
Fig. 3.5.18 Structure of Serial I/O2 control regist
Watchdog timer control register
b7 b6 b5 b4 b3 b2 b1 b0
Watchdog ol register
(WDTCs 001E16)
b
3
4
5
6
ame
hdog timer H
r read-out of high-order 6 bit)
Functions
At reset R W
1
1
1
1
1
1
0
✕
✕
✕
✕
✕
✕
STP instruction
disable bit
0: STP instruction enabled
1: STP instruction disabled
7
0
Watchdog timer H 0: Watchdog timer L
count source selection
bit
underflow
1: f(XIN)/16 or f(XCIN)/16
Fig. 3.5.19 Structure of Watchdog timer control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-62
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Serial I/O2 register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O2 register
(SIO2: address 001F16
)
b
Name
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefine
Undefi
0
1
2
3
4
5
6
7
This register becomes shift register.
At transmit: Set transmit data to this register.
At receive: Received data is stored to this
register.
Fig. 3.5.20 Structure of Serial I/O2 register
Prescaler 12, Prescaler X, Prescaler Y
b7 b6 b5 b4 b3 b2 b1 b0
Prescaler 12 (PRE12), Prescal), Prescaler Y (PREY)
(addresses 002016, 002416,
b
ons
At reset R W
0
1
2
3
4
5
1
1
1
1
1
1
1
1
• Set a couneach prescaler.
• The valuis register is written to both
each and the corresponding
preh at the same time.
• Wregister is read out, the count value
orresponding prescaler is read out.
Fig. 3.5.21 Structurescaler 12, Prescaler X, Prescaler Y
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-63
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Timer 1
b7 b6 b5 b4 b3 b2 b1 b0
Timer 1
(T1: address 002116)
b
Functions
At reset R W
0
1
2
3
4
5
6
7
1
0
0
0
0
0
0
• Set timer 1 count value.
• The value set in this register is written to both
the timer 1 and the timer 1 latch at the same
time.
• When the timer 1 is read out, the count value
of the timer 1 is read out.
Fig. 3.5.22 Structure of Timer 1
Timer 2, Timer X, Timer Y
b7 b6 b5 b4 b3 b2 b1 b0
Timer 2 (T2), Timer X (TX)TY)
(addresses 002216, 002)
b
nctions
At reset R W
0
1
2
3
4
1
1
1
1
1
1
1
1
• Set eacunt value.
• The n this register is written to both
eand the corresponding timer latch
me time.
each timer is read out, the count value
e corresponding timer is read out.
Fig. 3.5.23 Strucf Timer 2, Timer X, Timer Y
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-64
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Timer XY mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer XY mode register
(TM: address 002316
)
b
0
Name
Functions
At reset R W
b1 b0
Timer X operating
mode bits
0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width
0
1
2
measurement mode
Refer to Table 3.5.1
0 active edge
0
0
CNTR
switch bit
0: Count start
1: Count stop
3 Timer X count stop
bit
4
b5 b4
Timer Y operating
mode bits
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mod
1 1: Pulse width
0
5
measurement
Refer to Table
CNTR1 active edge
switch bit
0
0
6
7
0: Count
1: Cou
Timer Y count stop
bit
Fig. 3.5.24 Structure of Timer XY mode regist
Table 3.5.1 CNTR /CNTR active edge swfunction
0
1
Timer X/Timer Y operation modes
Timer mode
CNT
R active edge switch bit (bits 2 and 6 of address 002316) contents
1
“R
0
/CNTR
1
interrupt request occurrence: Falling edge
; No influence to timer count
interrupt request occurrence: Rising edge
; No influence to timer count
“0” Pulse output start: Beginning at “H” level
CNTR /CNTR interrupt request occurrence: Falling edge
“1” Pulse output start: Beginning at “L” level
CNTR /CNTR interrupt request occurrence: Rising edge
“0” Timer X/Timer Y: Rising edge count
CNTR /CNTR interrupt request occurrence: Falling edge
“1” Timer X/Timer Y: Falling edge count
CNTR /CNTR interrupt request occurrence: Rising edge
“0” Timer X/Timer Y: “H” level width measurement
CNTR /CNTR interrupt request occurrence: Falling edge
“1” Timer X/Timer Y: “L” level width measurement
CNTR /CNTR interrupt request occurrence: Rising edge
” CNTR
0
/CNTR
1
Pulse output mode
0
1
0
1
Event counter mode
0
1
0
1
Pulse width measurement mode
0
1
0
1
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-65
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Timer Z low-order, Timer Z high-order
b7 b6 b5 b4 b3 b2 b1 b0
Timer Z low-order (TZL), Timer Z high-order (TZH)
(addresses 002816, 002916
)
b
Functions
At reset R W
• Set each timer count value.
[At write]
1
1
1
1
1
1
0
1
2
3
• Depending on the write control bit (bit 3 of
TZM), the value set to this register is written to
each timer and the corresponding timer latch
at the same time, or is written only to the latch.
[At read]
• The corresponding timer count value is read
out by reading this register.
• Read both registers in order of TZH and TZL
following.
• Write both registers in order of TZL and TZH
following.
4
5
6
7
Fig. 3.5.25 Structure of Timer Z low-order, Timer Z high-order
Timer Z mode register
b7 b6 b5 b4 b3 b2 b1 b0
Timer Z mode register
(TZM: address 002A16
)
b
0
Name
Timer Z op
mode bit
Functions
At reset R W
0
b2b1b0
0 0 0: Timer/Event counter mode
0 0 1: Pulse output mode
0 1 0: Pulse period
measurement mode
0 1 1: Pulse width
measurement mode
1 0 0: Programmable waveform
generating mode
1
0
0
1 0 1: Programmable one-shot
generating mode
1 1 0: Not available
1 1 1: Not available
0: Writing data to both latch
and timer simultaneousuly
1: Writing data only to latch
Timer Z write control
bit
0
3
Output level latch
0: “L” output
1: “H” output
0
0
0
0
4
5
6
CNTR active edge
2
Refer to Table 3.5.2.
switch bit
0: Count start
1: Count stop
Timer Z count stop
bit
Timer/Event counter 0: Timer mode
mode switch bit (Note) 1: Event counter mode
7
Note: When selecting the modes except the timer/event counter mode, set “0” to this bit.
Fig. 3.5.26 Structure of Timer Z mode register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-66
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Table 3.5.2 CNTR
Timer Z operation modes
Timer mode
2
active edge switch bit function
CNTR
2
active edge switch bit (bit 5 of address 002A16) contents
interrupt request occurrence: Falling edge
; No influence to timer count
“0” CNTR
“1” CNTR
2
2
interrupt request occurrence: Rising edge
; No influence to timer count
Event counter mode
“0” Timer Z: Rising edge count
CNTR interrupt request occurrence: Falling edge
“1” Timer Z: Falling edge count
CNTR interrupt request occurrence: Rising edge
“0” Pulse output start: Beginning at “H” level
CNTR interrupt request occurrence: Fallin
“1” Pulse output start: Beginning at “L” lev
CNTR interrupt request occurrence: edge
“0” Timer Z: Period from falling edge to t falling edge measurement
CNTR interrupt request occurFalling edge
“1” Timer Z: Period from rising ehe next rising edge measurement
CNTR interrupt requesence: Rising edge
“0” Timer Z: “H” level wasurement
CNTR interrupt roccurrence: Falling edge
“1” Timer Z: “L” leh measurement
CNTR intequest occurrence: Rising edge
“0” Timer Ztart outputting “L”, “H” one-shot pulse generated
CNTupt request occurrence: Falling edge
“1” Tiafter start outputting “H”, “L” one-shot pulse generated
interrupt request occurrence: Rising edge
2
2
Pulse output mode
2
2
Pulse period measurement mode
Pulse width measurement mode
2
2
2
2
Programmable one-shot generating
mode
2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-67
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
PWM control register
b7 b6 b5 b4 b3 b2 b1 b0
PWM control register (PWMCON: address 002B16)
b
0
Name
PWM function
enable bit
Functions
At reset R W
0
0 : PWM disabled
1 : PWM enabled
Count source
selection bit
0
1
0 : f(XIN
1 : f(XIN)/2
)
✕
✕
✕
✕
✕
✕
2
3
4
5
6
7
0
0
0
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
Fig. 3.5.27 Structure of PWM control register
PWM prescaler
b7 b6 b5 b4 b3 b2 b1 b0
PWM prescaler
(PREPWM: address 002C16
)
b
0
1
2
3
4
5
Fu
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
•Set the PWM per
•The value set iister is written to both
PWM prescatch and PWM prescaler
latch at time.
• When itten to this register during
PWthe pulse corresponding to
calue is output at the next period.
is register is read out, the count value
PWM prescaler latch is read out.
Fig. 3.5.28 Structure of escaler
PWM re
b7 b3 b2 b1 b0
PWM register
(PWM: address 002D16
)
b
Functions
At reset R W
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
1
2
3
4
5
6
7
• Set the PWM “H” level output interval.
• The value set in this register is written to both
PWM register pre-latch and PWM register
latch at the same time.
• When data is written to this register during
PWM output, the pulse corresponding to
changed value is output at the next period.
• When this register is read out, the contents of
the PWM register latch is read out.
Fig. 3.5.29 Structure of PWM register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-68
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Serial I/O3 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O3 control register
(SIO3CON: address 003216)
b
Name
Functions
At reset R W
0 BRG count source
selection bit (CSS)
0
0: f(XIN)
1: f(XIN)/4
Serial I/O3
1
0
When clock synchronous
serial I/O is selected,
0: BRG output divided by 4
1: External clock input
When UART is selected,
0: BRG output divided by 16
1: External clock input
divided by16
synchronous clock
selection bit (SCS)
0
0: I/O port (P37)
1: SRDY3 output pin
SRDY3 output
enable bit (SRDY)
2
3
0: Transmit buffer em
1: Transmit shift o
completion
Transmit interrupt
source selection
bit (TIC)
Transmit enable bit 0: Transmit
0
0
0
4
5
6
(TE)
1: Transd
Receive enable bit
(RE)
0: Rebled
1: nabled
Serial I/O3 mode
k synchronous
erial I/O
selection bit (SIOM
Serial I/O3 disabled
(P34 to P37: normal I/O pins)
1: Serial I/O3 disabled
(P34 to P37: Serial I/O pins)
Serial I/O3 e
bit (SIOE)
0
7
Fig. 3.5.30 Structure of Serial ntrol register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-69
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
UART3 control register
b7 b6 b5 b4 b3 b2 b1 b0
UART3 control register
(UART3CON: address 003316
)
b
0
Name
Functions
At reset R W
0
0
0
0
Character length
selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit
(PARE)
1
0: Parity checking disabled
1: Parity checking enabled
0: Even parity
1: Odd parity
Parity selection bit
(PARS)
2
3
Stop bit length
selection bit (STPS) 1: 2 stop bits
0: 1 stop bit
P35
/TxD P-channel
3
4
0: CMOS output
(in output mode)
1: N-channel open-dr
output (in output
output disable bit
(POFF)
5
6
7
Nothing is arranged for these bits. Th
write disabled bits. When these bitd
out, the contents are “1”.
1
1
1
✕
✕
✕
Fig. 3.5.31 Structure of UART3 control register
AD/DA control register
b7 b6 b5 b4 b3 b2 b1 b0
AD/DA ster
(ADCss 003416
)
Name
alog input pin
selection bits 1
Functions
At reset R W
0
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
0
1
2
3
4
5
6
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
or P0
or P0
or P0
or P0
or P0
or P0
or P0
0
1
2
3
4
5
6
/AN
/AN
/AN10
/AN11
/AN12
/AN13
/AN14
8
9
1
2
0
0
1 1 1: P67/AN7 or P07/AN15
0: Conversion in progress
1: Conversion completed
3
4
5
AD conversion
completion bit
1
0
0
0: AN
1: AN
0
8
to AN
to AN15 side
7 side
Analog input pin
selection bit 2
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0: DA
1: DA
1
1
output disabled
output enabled
DA
bit
1
output enable
0
0
6
7
0: DA
1: DA
2
2
output disabled
output enabled
DA
bit
2
output enable
Fig. 3.5.32 Structure of AD/DA control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-70
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
AD conversion register 1
b7 b6 b5 b4 b3 b2 b1 b0
AD conversion register 1
(AD1: address 003516
)
b
Functions
At reset R W
Undefined
0
1
2
3
4
5
6
7
This is A/D conversion result stored bits. This is
read exclusive register.
Undefined
Undefined
8-bit read
b7
b0
Undefined
b9b8b7b6b5b4b3b2
10-bit read
Undefined
Undefined
b7
b0
Undefined
b7b6b5b4b3b2b1b0
Unde
Fig. 3.5.33 Structure of AD conversion register 1
DAi conversion register
b7 b6 b5 b4 b3 b2 b1 b0
DAi conversion register (i = 1, 2)
(DAi: addresses 003616, 003716
)
b
Fun
At reset R W
0
0
1
2
3
This is D/A output ved bits. This is write
exclusive registe
0
0
4
5
6
7
0
0
Fig. 3.5.34 Structure of DAi con register (i = 1, 2)
AD conveegister 2
b7 b6 b2 b1 b0
AD conversion register 2
(AD2: address 003816)
b
0
Functions
At reset R W
Undefined
This is A/D conversion result stored bits. This is
read exclusive register.
10-bit read
b7
b0
Undefined
1
b9b8
0
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read out,
the contents are “0”.
2
3
4
5
6
7
0
0
0
0
0
Conversion mode
selection bit
0: 10-bit A/D mode
1: 8-bit A/D mode
Fig. 3.5.35 Structure of AD conversion register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-71
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Interrupt source selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt source selection register
(INTSEL: address 003916
)
b
0
Name
Functions
interrupt
At reset R W
0
INT
0
/Timer Z
0: INT
0
interrupt source
selection bit (*1)
1: Timer Z interrupt
0: Serial I/O2 interrupt
1: Timer Z interrupt
0
0
Serial I/O2/Timer Z
interrupt source
selection bit (*1)
1
2
Serial I/O1 transmit/
SCL, SDA interrupt
source selection bit
(*2)
0: Serial I/O1 transmit
interrupt
1: SCL, SDA interrupt
0
0
3
4
0: CNTR
1: SCL, SDA interrup
0
interrupt
CNTR0/SCL, SDA
interrupt source
selection bit (*2)
0: INT
1: CNTR
4
interrup
in
INT /CNTR2
4
2
interrupt source
selection bit
/I2C interrupt
0
0
0: INT
5 INT
source selection bit
2
1: I2t
interrupt
l I/O3 receive
errupt
CNTR /Serial I/O3
receive interrupt
1
6
source selection
0
7 AD converter
I/O3 transm
A/D converter interrupt
1: Serial I/O3 transmit
interrupt
interrupt
select
*1: D1 to these bits simultaneously.
*2: rite 1 to these bits simultaneously.
Fig. 3.5.36 Structure of Inteource selection register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-72
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Interrupt edge selection register
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt edge selection register
(INTEDGE: address 003A16
)
b
0
Name
Functions
0: Falling edge active
1: Rising edge active
At reset R W
0
0
0
INT
0
active edge
selection bit
INT active edge
selection bit
0: Falling edge active
1: Rising edge active
1
1
2 Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are “0”.
0
0
3 INT
selection bit
INT active edge
selection bit
INT active edge
selection bit
INT , INT interrupt
switch bit
2
active edge
0: Falling edge active
1: Rising edge active
3
4
5
6
0: Falling edge active
1: Rising edge active
4
0: Falling edge active
1: Rising edge active
0
4
0: INT00, INT40 int
1: INT01, INT41
0
7 Nothing is arranged for this bit. Tite
disabled bit. When this bit is ree
contents are “0”.
Fig. 3.5.37 Structure of Interrupt edge selection r
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
CPister
(ress 003B16
1
)
Name
Functions
At reset R W
0
b1 b0
Processor mode
bits
00 : Single-chip mode
01 :
1
2
10 :
11 :
0 : 0 page
1 : 1 page
Not available
0
0
Stack page
selection bit
1
0
Fix this bit to “1”.
3
4
Port Xc switch bit
0: I/O port function
(stop oscillating)
1: XCIN-XCOUT oscillation
function
Main clock (XIN
-
0: Oscillating
1: Stopped
b7 b6
0
1
5
6
XOUT) stop bit
Main clock division
ratio selection bits
0 0: φ=f(XIN)/2
(high-speed mode)
0 1: φ=f(XIN)/8
(middle-speed mode)
1 0: φ=f(XCIN)/2
0
7
(low-speed mode)
1 1: not available
Fig. 3.5.38 Structure of CPU mode register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-73
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt request register 1
(IREQ1 : address 003C16
)
b
0
Name
Functions
At reset R W
✕
✕
✕
✕
0
0
0
0
INT
0
/Timer Z
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
1 INT
1
interrupt
request bit
0 : No interrupt request issued
1 : Interrupt request issued
2 Serial I/O1 receive
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
3 Serial I/O1
transmit/SCL, SDA
interrupt request bit
✕
✕
✕
✕
0
0
4 Timer X interrupt
request bit
0 : No interrupt request issu
1 : Interrupt request is
5
0 : No interrupt requ
1 : Interrupt reqd
Timer Y interrupt
request bit
6
7
Timer 1 interrupt
request bit
0 : No interrussued
1 : Interrut issued
Timer 2 interrupt
request bit
0 : No quest issued
1 : Iequest issued
0
✕: 0 can be set by softwcannot be set.
Fig. 3.5.39 Structure of Interrupt request regist
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0
Inest register 2
ddress 003D16
)
0
Name
Functions
0 : No interrupt request issued
1 : Interrupt request issued
At reset R W
✕
0
CNTR
0/SCL, SDA
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
✕
0
1 CNTR
/Serial I/O3
1
receive interrupt
request bit
Serial I/O2/Timer Z 0 : No interrupt request issued
interrupt request bit 1 : Interrupt request issued
✕
✕
✕
✕
✕
0
0
0
0
0
2
3
4
INT
request bit
INT interrupt
request bit
2
/I2C interrupt
0 : No interrupt request issued
1 : Interrupt request issued
3
0 : No interrupt request issued
1 : Interrupt request issued
0 : No interrupt request issued
1 : Interrupt request issued
5 INT
/CNTR
4
2
interrupt request bit
AD converter/Serial
I/O3 transmit
interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
6
0
7
Nothing is arranged for this bit. This is a write
disabled bit. When this bit is read out, the
contents are 0 .
✕: 0 can be set by software, but 1 cannot be set.
Fig. 3.5.40 Structure of Interrupt request register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-74
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1
(ICON1 : address 003E16)
b
0
Name
Functions
At reset R W
0
0
0
INT
0
/Timer Z
interrupt enable bit
interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
1 INT
1
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
2 Serial I/O1 receive
interrupt enable bit
Serial I/O1
3
0 : Interrupt disabled
transmit/SCL, SDA 1 : Interrupt enabled
interrupt enable bit
Timer X interrupt
enable bit
0 : Interrupt disabled
1 : Interrupt enabled
4
5
6
7
0
0
0
Timer Y interrupt
enable bit
0 : Interrupt disabl
1 : Interrupt ena
Timer 1 interrupt
enable bit
0 : Interrupt
1 : Interrud
Timer 2 interrupt
enable bit
0 : Intebled
1 : Inabled
Fig. 3.5.41 Structure of Interrupt control register
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0
Inteol register 2
0
(dress 003F16
)
Name
Functions
At reset R W
0
CNTR
enable bit
CNTR / Serial I/O3
0
interrupt
0 : Interrupt disabled
1 : Interrupt enabled
1
0
1
0 : Interrupt disabled
1 : Interrupt enabled
receive interrupt
enable bit
Serial I/O2/ Timer Z
interrupt enable bit
0
0
0
0
0
2
3
4
5
6
0 : Interrupt disabled
1 : Interrupt enabled
INT
enable bit
INT interrupt
enable bit
2
interrupt
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
3
INT /CNTR2
4
0 : Interrupt disabled
1 : Interrupt enabled
interrupt enable bit
AD converter/Serial
I/O3 transmit
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
7
Fix this bit to “0”.
0
Fig. 3.5.42 Structure of Interrupt control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-75
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register 0
(FMCR0 : address 0FE016
)
b
Name
Functions
At reset R W
1
0 : Busy (being automatic written
or automatic erased)
1 : Ready
0 RY/BY status flag
0
1
CPU rewrite mode 0 : CPU rewrite mode invalid
select bit (Note 1)
(software commandes invalid)
1 : CPU rewrite mode valid
(Software commands
acceptable)
2
3
8 KB user block E/W
enable bit (Notes 1,
2)
0: E/W disabled
1: E/W enabled
0
Flash memory reset
bit (Note 3)
0: Normal operatio
1: Reset
Not used (Do not write “1” to this bit
4
5
0
0
User ROM area
select bit
0: User ROccessed
1: Boot Rs accessed
6
7
Program status flag 0: Pa
1:
0
0
Erase status flag
r
Notes 1: For this bit o “1”, the user needs to write a “0” and then a
“1” to it ion. For this bit to be set to “0”, write “0” only to
this
2: Tbe written only when the CPU rewrite mode select bit
ive only when the CPU rewrite mode select bit = “1”. Fix this
to “0” when the CPU rewrite mode select bit is “0”.
When setting this bit to “1” (when the control circuit of flash memory
is reset), the flash memory cannot be accessed for 10 µs.
5: Write to this bit from program on RAM.
Fig. 3.5.43 Structure sh memory control register 0
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-76
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
Flash memory control register 1
(FMCR1 : address 0FE116)
b
Name
Functions
At reset R W
0
0 : Suspend invalid
1 : Suspend valid
0 Erase suspend
enable bit (Note 1)
0
1
Erase suspend
request bit (Note 2)
0 : Erase restart (no
request issued)
1 : Suspend request
(request issued)
2
3
4
5
Nothing is arranged for these bits. If writing to
these bits, write “0”. The contents are undefined
at reading.
0
0
0 : Erase active
1 : Erase inactive (Era
suspend mode)
6 Erase suspend flag
Nothing is arranged for these bits. If w
these bits, write “0”. The contents aed
at reading.
0
7
Notes 1: For this bit to be set to “1”, eeds to write a “0” and then
a “1” to it in succession
2: Only when the erase bit is “1”, this bit is valid.
Fig. 3.5.44 Structure of Flash memory congister 1
Flash memory controer 2
b7 b6 b5 b4 b3 b2 b1
sh memory control register 2
(FMCR2 : address 0FE216
)
b
Name
Functions
At reset R W
Nothing is arranged for these bits. If writing to
these bits, write “0”. The contents are undefined
at reading.
0
1
2
3
1
0
All user block E/W
4
0 : E/W disabled
1 : E/W enabled
enable bit (Notes 1, 2)
0
1
0
5
6
Nothing is arranged for these bits. If writing to
these bits, write “0”. The contents are undefined
at reading.
7
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then
a “1” to it in succession.
2: Effective only when the CPU rewrite mode select bit = “1”.
Fig. 3.5.45 Structure of Flash memory control register 2
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-77
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
Port Pi pull-up control register (i = 0 to 2, 4 to 6)
b7 b6 b5 b4 b3 b2 b1 b0
Port Pi pull-up control register (i = 0 to 2, 4 to 6)
(PULLi: addresses 0FF016, 0FF116, 0FF216, 0FF416, 0FF516, 0FF616
)
b
0
Name
pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Port Pi pull-up
control bit
Functions
0: No pull-up
1: Pull-up
At reset R W
0
Port Pi
0
1
0
0
0
0: No pull-up
1: Pull-up
1
2
3
4
5
6
7
2
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
3
4
0: No pull-up
1: Pull-up
0
5
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
6
0
0
7
0: No pull-
1: Pull-u
Fig. 3.5.46 Structure of Port Pi pull-up control regis0 to 2, 4 to 6)
Port P3 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0
Port Pontrol register
(PUss 0FF316
)
Name
ort P30 pull-up
control bit
Functions
0: No pull-up
1: Pull-up
At reset R W
0
Port P31 pull-up
control bit
0
0
0: No pull-up
1: Pull-up
1
Nothing is arranged for these bits. These are
write disabled bits. When these bits are read
out, the contents are “0”.
2
3
0
Port P34 pull-up
control bit
0: No pull-up
1: Pull-up
0
4
5
6
7
0
Port P35 pull-up
control bit
Port P36 pull-up
control bit
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0
0
Port P37 pull-up
control bit
0: No pull-up
1: Pull-up
Fig. 3.5.47 Structure of Port P3 pull-up control register
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-78
APPENDIX
3804 Group (Spec.H)
3.5 Control registers
2
I C slave address register i (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
I2C slave address register i (i = 0 to 2)
(S0D0, S0D1, S0D2: addresses 0FF716, 0FF816, 0FF916
)
b
Name
Functions
At reset R W
0: Write bit
1: Read bit
0 Read/Write bit
(RWB)
0
1
0
0
0
0
0
Slave address
The contents of these bits
(SAD0, SAD1, SAD2, are compared with the
SAD3, SAD4, SAD5, address data transmitted
2
3
4
5
6
7
SAD6)
from master.
Note: When the read-modify-write instructions (SEre used at
detection of stop condition, the values mafined.
Fig. 3.5.48 Structure of I2C slave address register i (i = 0 to 2)
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-79
APPENDIX
3804 Group (Spec.H)
3.6 Package outline
3.6 Package outline
64P6N-A
Plastic 64pin 14✕14mm body QFP
EIAJ Package Code
QFP64-P-1414-0.80
JEDEC Code
Weight(g)
1.11
Lead Material
Alloy 42
–
MD
HD
D
64
49
1
48
I2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
–
16.5
16.5
0.4
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
14.2
–
17.1
17.1
0.8
–
0.1
10°
–
A
A1
A2
b
c
D
35
0.15
14.0
14.0
0.8
16.8
16.8
0.6
1.4
–
–
0.5
–
14.6
14.6
16
33
A
17
32
L1
L
L1
y
–
0°
–
1.3
–
F
e
b
b2
I2
MD
ME
–
–
y
Detai
–
–
64P4B
Plastic 64pin 750mil SDIP
EIAJ Package Code
SDIP64-P-750-1.78
JEDEC Code
Weight(g)
7.9
erial
/Cu Alloy
–
64
33
1
32
Dimension in Millimeters
Symbol
Min
–
0.38
–
Nom
–
–
Max
5.08
–
D
A
A1
A2
b
b1
b2
c
D
E
e
e1
3.8
–
0.4
0.9
0.65
0.2
56.2
16.85
–
–
2.8
0°
0.5
1.0
0.59
1.3
1.05
0.32
56.6
17.15
–
–
–
15°
0.75
0.25
56.4
17.0
1.778
19.05
–
e
b1
b
b2
SEATING PLANE
L
–
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-80
APPENDIX
3804 Group (Spec.H)
3.6 Package outline
64P6Q-A
Plastic 64pin 10✕10mm body LQFP
EIAJ Package Code
LQFP64-P-1010-0.5
JEDEC Code
Weight(g)
Lead Material
Cu Alloy
MD
—
HD
D
48
33
I2
Recommended Mount Pad
49
32
Dimension in Millimeters
Symbol
Min
—
0
Nom
—
0.1
Max
1.7
0.2
—
A
A1
A2
b
c
D
—
1.4
0.13
0.105
9.9
9.9
—
0.18
0.125
0.0
0.28
0.175
10.1
10.1
—
64
17
E
e
1
16
A
HD
HE
L
1
.45
—
—
—
0¡
—
0
2.0
0.5
1.0
0.6
0.25
—
—
—
0.225
—
12.2
12.2
0.7
—
0.75
—
0.08
0.1
10¡
—
F
e
L1
y
L
b
b2
I2
MD
ME
x
M
Lp
1.0
—
—
—
—
—
Detail F
10.4
10.4
64P6U-A
Plastic 64pin 14✕14mm body LQFP
EIAJ Package Code
LQFP64-P-1414-0.8
JEDEC Code
Weight(g)
Le
—
MD
HD
D
48
33
l2
49
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
—
0
Nom
—
0.1
Max
1.7
0.2
—
0.45
0.175
14.1
14.1
—
A
A1
A2
b
c
D
—
1.4
0.32
0.105
13.9
13.9
—
0.37
0.125
14.0
14.0
0.8
64
17
E
e
1
16
A
16.0
16.0
0.5
1.0
0.6
0.25
—
—
—
0.5
HD
HE
L
L1
Lp
A3
x
15.8
15.8
0.3
—
0.45
—
—
—
0¡
—
16.2
16.2
0.7
—
0.75
—
0.2
0.1
8¡
—
—
—
—
L1
F
e
L
b
y
y
M
x
Lp
b2
I2
MD
ME
0.95
—
—
—
14.4
14.4
Detail F
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-81
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
69
A
n
BIT,A, R
ZP
n
BIT,ZP, R
OP
#
n
# OP
2
#
OP
n
# OP
65
#
2
OP
n
#
ADC
(Note 1)
(Note 5)
When T = 0
When T = 0, this instruction adds the contents
M, C, and A; and stores the results in A and C.
When T = 1, this instruction adds the contents
of M(X), M and C; and stores the results in
M(X) and C. When T=1, the contents of A re-
main unchanged, but the contents of status
flags are changed.
2
3
←
A
A + M + C
When T = 1
←
M(X)
M(X) + M + C
M(X) represents the contents of memory
where is indicated by X.
AND
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise AND operation and stores the result
back in A.
When T = 1, this instruction transfers the con-
tents M(X) and M to the ALU which performs a
bit-wise AND operation and stores the results
back in M(X). When T = 1, the contents of A
remain unchanged, but status flags are
changed.
29
2
2
25
3
2
V
←
A
A
M
When T = 1
V
←
M(X)
M(X)
M
M(X) represents the contents of memory
where is indicated by X.
7
0
ASL
This instruction shifts the content of A or M by
one bit to the left, with bit 0 always being set to
0 and bit 7 of A or M always being contained in
C.
0A
2
1
06
5
2
←
←
0
C
BBC
(Note 4)
Ai or Mi = 0?
Ai or Mi = 1?
This instruction tests the designated bit i of
or A and takes a branch if the bit is 0
branch address is specified by a rela
dress. If the bit is 1, next inst
executed.
13
+
4
2
17
+
5
5
3
3
20i
20i
BBS
(Note 4)
This instruction tests the desof the
M or A and takes a brancs 1. The
branch address is speelative ad-
dress. If the bit is struction is
executed.
03
+
4
2
07
+
20i
20i
C = 0?
C = 1?
BCC
(Note 4)
This instructbranch to the ap-
pointed ad0. The branch address
is speciftive address. If C is 1, the
next iexecuted.
BCS
(Note 4)
Tion takes a branch to the ap-
dress if C is 1. The branch address
ied by a relative address. If C is 0, the
nstruction is executed.
Z = 1?
BEQ
(Note 4)
This instruction takes a branch to the ap-
pointed address when Z is 1. The branch
address is specified by a relative address.
If Z is 0, the next instruction is executed.
V
A
M
BIT
This instruction takes a bit-wise logical AND of
A and M contents; however, the contents of A
and M are not modified.
24
3
2
The contents of N, V, Z are changed, but the
contents of A, M remain unchanged.
N = 1?
Z = 0?
BMI
(Note 4)
This instruction takes a branch to the ap-
pointed address when N is 1. The branch
address is specified by a relative address.
If N is 0, the next instruction is executed.
BNE
(Note 4)
This instruction takes a branch to the ap-
pointed address if Z is 0. The branch address
is specified by a relative address. If Z is 1, the
next instruction is executed.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-82
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
75
n
4
#
2
n
#
OP
6D
n
4
#
3
OP
7D
n
5
#
OP
79
n
5
#
3
OP
#
n
#
OP
61
n
6
#
OP
71
n
6
#
OP
#
OP
#
N
N
V
V
3
2
2
•
35
4
2
2D
4
3
3D
5
3
39
5
3
21
6
2
31
6
2
N
•
•
•
•
•
Z
•
16
6
2
0E
6
3
1E
7
3
N
•
•
•
•
•
•
•
•
•
•
Z
C
•
•
•
•
•
•
•
•
•
•
•
2
2
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
90
B0
F0
•
M7 M6
Z
2C
4
3
30
2
2
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D0
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-83
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
n
# OP
#
n
# OP
#
BPL
(Note 4)
N = 0?
This instruction takes a branch to the ap-
pointed address if N is 0. The branch address
is specified by a relative address. If N is 1, the
next instruction is executed.
←
BRA
BRK
PC
PC ± offset
This instruction branches to the appointed ad-
dress. The branch address is specified by a
relative address.
←
B
1
When the BRK instruction is executed, the
CPU pushes the current PC contents onto the
stack. The BADRS designated in the interrupt
vector table is stored into the PC.
00
7
1
←
(PC)
(PC) + 2
PCH
←
M(S)
←
S
S – 1
←
M(S)
PCL
←
S
S – 1
←
PS
S – 1
M(S)
←
S
←
I
1
←
←
PCL
PCH
ADL
ADH
BVC
(Note 4)
V = 0?
V = 1?
Ai or Mi
This instruction takes a branch to the ap-
pointed address if V is 0. The branch address
is specified by a relative address. If V is 1, the
next instruction is executed.
BVS
(Note 4)
This instruction takes a branch to the ap-
pointed address when V is 1. The branch
address is specified by a relative address.
When V is 0, the next instruction is execu
1B
+
2
1
1F
+
5
2
←
CLB
CLC
CLD
CLI
0
This instruction clears the designate
or M.
20i
20i
18
D8
58
12
B8
2
2
2
2
2
1
1
1
1
1
←
←
C
D
0
0
This instruction clears C.
This instruction clear
This instructio
This iars T.
ction clears V.
←
I
0
←
←
CLT
CLV
T
V
0
0
C9
2
2
C5
3
2
CMP
(Note 3)
When T = 0
A – M
When T = 1
M(X) – M
en T = 0, this instruction subtracts the con-
ents of M from the contents of A. The result is
not stored and the contents of A or M are not
modified.
When T = 1, the CMP subtracts the contents
of M from the contents of M(X). The result is
not stored and the contents of X, M, and A are
not modified.
M(X) represents the contents of memory
where is indicated by X.
__
M
44
E4
5
3
2
2
←
COM
CPX
M
This instruction takes the one’s complement of
the contents of M and stores the result in M.
E0
C0
2
2
2
X – M
Y – M
This instruction subtracts the contents of M
from the contents of X. The result is not stored
and the contents of X and M are not modified.
2
C4
C6
3
5
2
2
CPY
DEC
This instruction subtracts the contents of M
from the contents of Y. The result is not stored
and the contents of Y and M are not modified.
1A
2
1
←
←
A
M
A – 1 or
M – 1
This instruction subtracts 1 from the contents
of A or M.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-84
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
V
•
5
4
B
•
3
D
•
2
I
1
Z
•
0
C
•
OP
n
#
n
#
OP
#
OP
n
#
OP
#
n
#
#
#
OP
10
#
2
OP
#
N
T
2
•
•
•
80
4
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
70
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
0
•
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
0
•
•
•
•
•
D5
4
CD
4
3
D9
5
3
C1
6
2
D1
6
2
2
N
•
•
•
Z
C
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
EC
CC
CE
4
4
6
3
3
3
C
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
C
D6
6
DE
7
3
2
•
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-85
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
OP n
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
CA
#
1
# OP
#
n
# OP
#
n
←
←
←
2
DEX
DEY
DIV
X
Y
A
X – 1
This instruction subtracts one from the current
contents of X.
88
1
2
Y – 1
This instruction subtracts one from the current
contents of Y.
(M(zz + X + 1),
M(zz + X )) / A
This instruction divides the 16-bit data in
M(zz+(X)) (low-order byte) and M(zz+(X)+1)
(high-order byte) by the contents of A. The
quotient is stored in A and the one's comple-
ment of the remainder is pushed onto the stack.
←
M(S)
one's comple-
ment of Remainder
←
S
S – 1
2
2
45
3
2
49
EOR
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of the M and A to the ALU which
performs a bit-wise Exclusive OR, and stores
the result in A.
When T = 1, the contents of M(X) and M are
transferred to the ALU, which performs a bit-
wise Exclusive OR and stores the results in
M(X). The contents of A remain unchanged,
but status flags are changed.
–
←
A
A V M
When T = 1
–
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
E6
5
2
←
←
3A
2
1
INC
INX
A
M
A + 1 or
M + 1
This instruction adds one to the contents of A
or M.
1
←
2
X
X + 1
Y + 1
This instruction adds one to the contents of X.
This instruction adds one to the conten
←
INY
Y
JMP
If addressing mode is ABS
This instruction jumps to the ad
nated by the following threng
modes:
←
←
PCL
PCH
ADL
ADH
If addressing mode is IND
Absolute
←
←
PCL
PC
M (ADH, ADL)
M (AD , AD + 1)
Indirect Absolute
Zero Page Indirect A
H
H
L
If addressing mode is ZP, IND
←
←
PCL
PCH
M(00, ADL)
M(00, ADL + 1)
←
JSR
M(S)
PCH
S – 1
This insts the contents of the PC
in the umps to the address desig-
natowing addressing modes:
A
←
S
←
PCL
S – 1
M(S)
←
S
After executing the above,
ge
if addressing mode is ABS
ge Indirect Absolute
←
←
PCL
PCH
ADL
ADH
if addressing mo
←
←
PCL
PCH
ADL
FF
If addressing mIND,
←
←
PCL
PCH
M(00, L)
M(00, ADL + 1)
A9
2
2
A5
3C
3
4
2
3
LDA
(Note 2)
When T = 0
When T = 0, this instruction transfers the con-
tents of M to A.
←
A
M
When T = 1
When T = 1, this instruction transfers the con-
tents of M to (M(X)). The contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory
where is indicated by X.
←
M(X)
M
←
LDM
M
nn
This instruction loads the immediate value in
M.
←
←
A2
A0
2
2
2
2
A6
A4
3
3
2
2
LDX
LDY
X
Y
M
M
This instruction loads the contents of M in X.
This instruction loads the contents of M in Y.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-86
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
n
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
n
#
#
OP
#
OP
n
#
OP
#
OP
n
#
#
#
OP
#
OP
#
N
N
V
T
B
D
I
Z
Z
C
•
•
•
•
•
•
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
•
E2 16
2
2
4
4D
4
3
5D
5
3
59
5
3
41
6
2
51
6
2
55
•
•
•
•
•
Z
•
6
EE
4C
6
3
3
FE
7
3
F6
2
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
3
6C
5
3
B2
•
•
20
6
3
02
7
2
22
5
2
•
•
•
•
•
•
•
•
B5
4
2
AD
4
3
BD
5
3
B9
5
3
A1
6
2
B1
6
2
N
•
•
•
•
•
•
•
•
•
•
Z
•
•
•
•
B6
4
2
AE
AC
4
4
3
3
BE
5
3
N
N
•
•
•
•
•
•
•
•
•
•
Z
Z
•
•
B4
4
2
BC
5
3
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-87
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Symbol
LSR
Function
Details
IMP
n
IMM
OP n
A
n
2
BIT, A
OP
ZP
n
BIT, ZP
OP #
OP
#
# OP
4A
#
1
n
# OP
46
#
2
n
5
This instruction shifts either A or M one bit to
the right such that bit 7 of the result always is
set to 0, and the bit 0 is stored in C.
7
0
→
C
→
0
←
M(S) •✕A A ✕ M(zz + X) This instruction multiply Accumulator with the
MUL
←
S
S – 1
memory specified by the Zero Page X address
mode and stores the high-order byte of the re-
sult on the Stack and the low-order byte in A.
←
NOP
PC
PC + 1
This instruction adds one to the PC but does EA
no other operation.
2
1
09
2
2
3
2
ORA
(Note 1)
When T = 0
When T = 0, this instruction transfers the con-
tents of A and M to the ALU which performs a
bit-wise “OR”, and stores the result in A.
When T = 1, this instruction transfers the con-
tents of M(X) and the M to the ALU which
performs a bit-wise OR, and stores the result
in M(X). The contents of A remain unchanged,
but status flags are changed.
05
←
A
A V M
When T = 1
←
M(X)
M(X) V M
M(X) represents the contents of memory
where is indicated by X.
←
S – 1
PHA
PHP
PLA
PLP
ROL
M(S)
A
This instruction pushes the contents of A to
the memory location designated by S, and
decrements the contents of S by one.
48
3
4
4
1
1
1
←
S
←
S – 1
M(S)
PS
This instruction pushes the contents of PS to
the memory location designated by S and d
rements the contents of S by one.
←
S
←
←
S
A
S + 1
M(S)
This instruction increments S by
stores the contents of the memor
by S in A.
68
←
S
S + 1
This instruction incremene and
stores the contents of y location
designated by S in P
28
←
PS
M(S)
2A
6A
2
2
1
1
26
66
82
5
5
8
2
2
2
This instruction A or M one bit left
through C. C n bit 0 and bit 7 is
stored in C
7
←
0
←
←
C
ROR
Thishifts either A or M one bit
riC. C is stored in bit 7 and bit 0 is
.
7
→
0
→
C
RRF
RTI
s instruction rotates 4 bits of the M content
o the right.
7
0
→
→
←
S
S + 1
M(S)
S + 1
←
S + 1
This instruction increments S by one, and
stores the contents of the memory location
40
6
6
1
1
←
PS
←
PCL
←
S
designated by S in PS. S is again incremented
by one and stores the contents of the memory
location designated by S in PCL. S is again
incremented by one and stores the contents of
memory location designated by S in PCH.
M(S)
S
←
PCH
M(S)
←
PCL
RTS
S
S + 1
←
This instruction increments S by one and
stores the contents of the memory location
60
M(S)
←
S
S + 1
designated by S in PCL. S is again
←
←
PCH
(PC)
M(S)
(PC) + 1
incremented by one and the contents of the
memory location is stored in PCH. PC is
incremented by 1.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-88
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP
ABS
ABS, X
ABS, Y
OP n #
IND
n
ZP, IND
OP
IND, X
OP n
IND, Y
OP n
REL
n
SP
n
7
6
5
4
3
2
1
0
OP
56
n
6
#
2
n
#
OP
4E
n
6
#
3
OP
5E
n
7
#
OP
#
n
#
#
#
OP
#
OP
#
N
0
V
T
B
D
I
Z
Z
C
C
3
•
•
•
•
•
62 15
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
15
4
2
0D
4
3
1D
5
3
5
3
01
6
2
11
6
2
Z
19
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
N
Z
(Value saved in stack)
N
N
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Z
Z
•
C
C
•
36
76
6
6
2
2
2E
6E
6
6
3
3
3E
7E
7
7
3
(Value saved in stack)
•
•
•
•
•
•
•
•
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-89
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Symbol
Function
Details
IMP
n
IMM
A
n
BIT, A
OP
ZP
n
BIT, ZP
OP n #
OP
#
OP
E9
n
2
# OP
2
#
n
# OP
E5
#
2
When T = 0, this instruction subtracts the
value of M and the complement of C from A,
and stores the results in A and C.
When T = 1, the instruction subtracts the con-
tents of M and the complement of C from the
contents of M(X), and stores the results in
M(X) and C.
3
SBC
(Note 1)
(Note 5)
When T = 0
_
←
A
A – M – C
When T = 1
_
←
M(X)
M(X) – M – C
A remain unchanged, but status flag are
changed.
M(X) represents the contents of memory
where is indicated by X.
←
SEB
SEC
SED
SEI
Ai or Mi
1
This instruction sets the designated bit i of A
or M.
1
0F
+
5
2
20i
←
←
C
D
1
1
This instruction sets C.
This instruction set D.
This instruction set I.
This instruction set T.
38
F8
78
32
2
2
2
1
1
1
←
I
1
←
←
SET
STA
STP
T
M
1
A
This instruction stores the contents of A in M.
The contents of A does not change.
85
4
2
This instruction resets the oscillation co
F and the oscillation stops. Reset o
input is needed to wake up from t
2
1
←
←
←
←
STX
STY
TAX
TAY
TST
TSX
TXA
TXS
TYA
WIT
M
M
X
X
Y
This instruction stores the cin M.
The contents of X does no
86
84
4
4
2
2
This instruction storets of Y in M.
The contents of Y nge.
A
This instructie contents of A in X. AA
The contennot change.
2
2
1
1
Y
A
This iores the contents of A in Y. A8
The A does not change.
M = 0?
ction tests whether the contents of
” or not and modifies the N and Z.
64
3
2
←
←
←
←
X
A
S
A
S
X
X
Y
s instruction transfers the contents of S in BA
.
2
2
2
2
2
1
1
1
1
1
This instruction stores the contents of X in A.
This instruction stores the contents of X in S.
This instruction stores the contents of Y in A.
8A
9A
98
The WIT instruction stops the internal clock C2
but not the oscillation of the oscillation circuit
is not stopped.
CPU starts its function after the Timer X over
flows (comes to the terminal count). All regis-
ters or internal memory contents except Timer
X will not change during this mode. (Of course
needs VDD).
Notes 1 : The number of cycles “n” is increased by 3 when T is 1.
2 : The number of cycles “n” is increased by 2 when T is 1.
3 : The number of cycles “n” is increased by 1 when T is 1.
4 : The number of cycles “n” is increased by 2 when branching has occurred.
5 : N, V, and Z flags are invalid in decimal operation mode.
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-90
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Addressing mode
Processor status register
ZP, X
ZP, Y
OP n
ABS
ABS, X
ABS, Y
IND
n
ZP, IND
OP
IND, X
IND, Y
REL
n
SP
n
7
6
5
T
•
4
B
•
3
D
•
2
I
1
Z
Z
0
C
C
OP
n
4
#
2
#
OP
ED
n
4
#
3
OP
FD
n
5
#
OP
F9
n
5
#
3
OP
#
n
#
OP
E1
n
6
#
OP
F1
n
6
#
OP
#
OP
#
N
N
V
V
F5
3
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
1
•
•
•
1
•
•
1
•
•
•
95
5
81
7
2
2
8D
5
3
9D
6
3
99
6
3
•
•
•
•
•
•
•
5
2
96
8E
8C
5
5
3
3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
94
5
•
2
N
N
N
N
N
•
Z
Z
Z
Z
Z
•
N
•
Z
•
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-91
APPENDIX
3804 Group (Spec.H)
3.7 Machine instructions
Symbol
Contents
Symbol
Contents
IMP
IMM
A
Implied addressing mode
Immediate addressing mode
Accumulator or Accumulator addressing mode
Accumulator bit addressing mode
Accumulator bit relative addressing mode
Zero page addressing mode
Zero page bit addressing mode
Zero page bit relative addressing mode
Zero page X addressing mode
Zero page Y addressing mode
Absolute addressing mode
+
–
✕
Addition
Subtraction
Multiplication
Division
Logical OR
Logical AND
Logical exclusive OR
Negation
Shows direction of data flow
Index register X
Index register Y
BIT, A
BIT, A, R
ZP
BIT, ZP
BIT, ZP, R
ZP, X
ZP, Y
ABS
/
V
V
–
V
–
←
X
Y
ABS, X
ABS, Y
IND
Absolute X addressing mode
Absolute Y addressing mode
Indirect absolute addressing mode
S
Stack pointer
Program counter
PC
PS
PCH
PCL
ADH
ADL
FF
nn
Processor status register
8 high-order bits of program counter
8 low-order bits of progunter
8 high-order bits of
8 low-order bits o
FF in Hexadecn
Immediate
Zero pag
Memoby address designation of any ad-
dre
ZP, IND
Zero page indirect absolute addressing mode
IND, X
IND, Y
REL
SP
C
Indirect X addressing mode
Indirect Y addressing mode
Relative addressing mode
Special page addressing mode
Carry flag
zz
M
Z
Zero flag
I
D
B
T
V
N
Interrupt disable flag
Decimal mode flag
Break flag
X-modified arithmetic mode flag
Overflow flag
M(X)
M(S)
address indicated by contents of index
y of address indicated by contents of stack
ter
ontents of memory at address indicated by ADH and
ADL, in ADH is 8 high-order bits and ADL is 8 low-or-
der bits.
M(ADH, A
Negative flag
M
Contents of address indicated by zero page ADL
Bit i (i = 0 to 7) of accumulator
Bit i (i = 0 to 7) of memory
Opcode
Number of cycles
#
Number of bytes
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-92
APPENDIX
3804 Group (Spec.H)
3.8 List of instruction code
3.8 List of instruction code
D3 – D0
0000
0001
0010
0011
0100
0101
5
0110
6
0111
7
1000
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
E
1111
F
Hexadecimal
notation
0
1
2
3
4
D7 – D4
ORA
JSR
BBS
ORA
ZP
ASL
ZP
BBS
0, ZP
ORA
IMM
ASL
A
SEB
0, A
ORA
ABS
ASL
ABS
SEB
0, ZP
BRK
—
PHP
CLC
PLP
SEC
PHA
CLI
—
0000
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IND, X ZP, IND 0, A
ORA
IND, Y
BBC
0, A
ORA
ASL
BBC
ORA
ABS, Y
DEC
A
CLB
0, A
ORA
ASL
CLB
BPL
JSR
CLT
—
—
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ZP, X ZP, X 0, ZP
ABS, X ABS, X 0, ZP
AND
ABS IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
AND
ABS
ROL
ABS
SEB
1, ZP
AND
BMI
BBC
1, A
AND
ROL
BBC
AND
ABS, Y
INC
A
CLB
1, A
LD
AND
ROL
CLB
SET
STP
—
IND, Y
ZP, X ZP, X 1, ZP
, X ABS, X 1, ZP
EOR
RTI
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
EOR
IMM
LSR
A
SE
EOR
ABS
LSR
ABS
SEB
2, ZP
IND, X
EOR
BVC
BBC
2, A
EOR
LSR
BBC
EOR
ABS, Y
EOR
LSR
CLB
—
—
—
IND, Y
ZP, X ZP, X 2, ZP
ABS, X ABS, X 2, ZP
ADC
RTS
MUL
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
AD
SEB
3, A
JMP
IND
ADC
ABS
ROR
ABS
SEB
3, ZP
PLA
S
IND, X ZP, X
ADC
—
BBC
3, A
ADC
ROR
BBC
Y
CLB
3, A
ADC
ROR
CLB
BVS
BRA
—
—
TXA
TXS
TAX
TSX
DEX
—
—
IND, Y
ZP, X ZP, X 3, ZP
ABS, X ABS, X 3, ZP
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BB
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
TYA
TAY
CLV
INY
—
STA
IND, Y
BBC
4, A
STY
STA
S
STA
ABS, Y
CLB
4, A
STA
ABS, X
CLB
4, ZP
BCC
LDY
—
—
—
ZP, X ZP, X P
LDA
LDX
BBS
5, A
LDY
ZP
L
BBS
5, ZP
LDA
IMM
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
IMM IND, X IMM
LDA
JMP
BBC
L
LDX
BBC
LDA
ABS, Y
CLB
LDY
LDA
LDX
CLB
BCS
IND, Y ZP, IND 5, A
X ZP, Y 5, ZP
5, A ABS, X ABS, X ABS, Y 5, ZP
CPY
CMP
IMM IND, X
B
CMP
ZP
DEC
ZP
BBS
6, ZP
CMP
IMM
SEB
6, A
CPY
ABS
CMP
ABS
DEC
ABS
SEB
6, ZP
WIT
CMP
BNE
A
CMP
DEC
BBC
CMP
ABS, Y
CLB
6, A
CMP
DEC
CLB
—
CLD
INX
—
IND, Y
ZP, X ZP, X 6, ZP
ABS, X ABS, X 6, ZP
CPX
S
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
SBC
IMM
SEB
7, A
CPX
ABS
SBC
ABS
INC
ABS
SEB
7, ZP
NOP
—
IMM X
, Y
BBC
7, A
SBC
INC
BBC
SBC
ABS, Y
CLB
7, A
SBC
INC
CLB
—
—
SED
—
ZP, X ZP, X 7, ZP
ABS, X ABS, X 7, ZP
: 3-byte instruction
: 2-byte instruction
: 1-byte instruction
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-93
APPENDIX
3804 Group (Spec.H)
3.9 SFR memory map
3.9 SFR memory map
Port P0 (P0)
000016
Prescaler 12 (PRE12)
Timer 1 (T1)
002016
002116
002216
Port P0 direction register (P0D)
Port P1 (P1)
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
002316 Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
002416
002516
002616
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Port P3 direction register (P3D)
Port P4 (P4)
002716 Timer Y (TY)
Timer Z low-order (TZL)
Timer Z high-order (TZH)
002816
002916
Port P4 direction register (P4D)
Port P5 (P5)
002A16 Timer Z mode register (TZM)
Port P5 direction register (P5D)
Port P6 (P6)
002B16
002C16
PWM control register (PWMCON
PWM prescaler (PREPWM)
Port P6 direction register (P6D)
Timer 12, X count source selection register (T12XCSS)
Timer Y, Z count source selection register (TYZCSS)
002D16 PWM register (PWM)
002E16
002F16
003016
003116
003216
Baud rate gener3)
Transmit/Reregister 3 (TB3/RB3)
001016 MISRG
2
001116
C data shift register (S0)
Serial I/gister (SIO3STS)
Seriol register (SIO3CON)
I
2
001216 I C special mode status register (S3)
2
001316
001416
001516
001616
001716
003316 rol register (UART3CON)
I C status register (S1)
2
ontrol register (ADCON)
onversion register 1 (AD1)
00341
00
I C control register (S1D)
2
I C clock control register (S2)
2
DA1 conversion register (DA1)
I C START/STOP condition control register (S2D)
2
DA2 conversion register (DA2)
AD conversion register 2 (AD2)
3816
I C special mode control register (S3D)
001816 Transmit/Receive buffer register 1 (TB1/RB1)
001916 Serial I/O1 status register (SIO1STS)
003916 Interrupt source selection register (INTSEL)
003A16 Interrupt edge selection register (INTEDGE)
Serial I/O1 control register (SIO1CON)
UART1 control register (UART1CON)
001A16
001B16
CPU mode register (CPUM)
003B16
003C16
003D16
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
001C16 Baud rate generator 1 (BRG1)
001D16 Serial I/O2 control register (SIO2CO
001E16 Watchdog timer control register
003E16 Interrupt control register 1 (ICON1)
003F16 Interrupt control register 2 (ICON2)
001F16
Serial I/O2 register (SIO2)
Flash memory cr 0 (FMCR0)
Flash memogister 1 (FMCR1)
Flash memorl register 2 (FMCR2)
Port P0 pull-up control register (PULL0)
Port P1 pull-up control register (PULL1)
Port P2 pull-up control register (PULL2)
Port P3 pull-up control register (PULL3)
Port P4 pull-up control register (PULL4)
Port P5 pull-up control register (PULL5)
Port P6 pull-up control register (PULL6)
0FE016
0FE116
0FE216
0FE316
0FE416
0FE516
0FE616
0FE716
0FF016
0FF116
0FF216
0FF316
0FF416
0FF516
0FF616
0FF716
0FF816
0FF916
Reserved ✕
Reserved ✕
Reserved ✕
Reserved ✕
Reserved ✕
2
I C slave address register 0 (S0D0)
2
0FE816 Reserved ✕
0FE916 Reserved ✕
0FEA16 Reserved ✕
I C slave address register 1 (S0D1)
2
I C slave address register 2 (S0D2)
Reserved ✕
0FEC16 Reserved ✕
Reserved ✕
✕ Reserved area: Do not write any data to these addresses,
0FEB16
because these areas are reserved.
0FED16
0FEE16 Reserved ✕
0FEF16 Reserved ✕
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-94
APPENDIX
3804 Group (Spec.H)
3.10 Pin configurations
3.10 Pin configurations
(TOP VIEW)
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
P20(LED0)
P21(LED1)
P22(LED2)
P23(LED3)
P24(LED4)
P25(LED5)
P26(LED
P3
7
/SRDY3
/SCLK3
P3
6
P3
5
/T
X
D
3
3
P3
4
/R
X
D
P3
3
/SCL
/SDA
/DA
/DA
P3
2
P3
1
2
P3
0
1
P27(L
M38049FFHFP/HP/KP
VCC
V
V
REF
AVSS
/AN
P6
7
7
4
T40/XCOUT
P6
P6
P6
6/AN
5/AN
4/AN
6
5
4
1/INT00/XCIN
RESET
CNVSS
P63/AN3
P42/INT1
Package ty6N-A/64P6Q-A/64P6U-A
(TOP VIEW)
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
N
/AN
/AN
P3
P3
0
1
/DA
/DA
1
2
P3
2
/SDA
/SCL
/R
/T
/
/
6
6
5
7
6
5
P3
3
P34
X
D
3
P35
X
D
3
P64/AN4
P36
P37
P00
P01
P02
P03
P04
P05
P06
P07
SCLK3
P63
P62
P61
P60
/AN
/AN
/AN
/AN
7/INT
/PWM
3
2
1
0
3
S
RDY3
9
/AN
/AN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
/AN10
/AN11
/AN12
/AN13
/AN14
/AN15
/INT41
/INT01
P5
P56
P5
P5
5
/CNTR
/CNTR
1
4
0
P5
P5
P5
P5
CNTR
P4
P4
3
/SRDY2
/SCLK2
/SOUT2
/SIN2
2
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
1
0
P4
7
/SRDY1
/
2
6
/SCLK1
5
/T
/R
X
D
D
1
1
2
P4
P4
4
X
3
/INT
/INT
CNVSS
RESET
P42
1
0
(LED
(LED
(LED
(LED
(LED
(LED
(LED
(LED
0
)
)
)
)
)
)
)
)
1
2
3
4
5
6
7
1
2
3
4
5
6
7
P4
1
/INT00/XCIN
/INT40/XCOUT
P4
0
X
IN
OUT
SS
X
V
Package type : 64P4B
Rev.1.00 Jan 14, 2005
REJ09B0212-0100Z
3-95
3804 Group (Spec. H) User’s Manual
Publication Data : Rev.1.00 Jan 14, 2005
Published by :
Sales Strategic Planning Div.
Renesas Technology Corp.
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
3804 Group (Spec. H)
User’s Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明