M38062M4A-XXXFP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38062M4A-XXXFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总59页 (文件大小：883K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3822 Group (A ver.)
REJ03B0076-0120Z
Rev.1.20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
2003.12.24
●LCD drive control circuit
DESCRIPTION
Bias ................................................................................... 1/2, 1/3
Duty ...........................................................................1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 32
●2 clock generating circuits
The 3822 group (A version) is the 8-bit microcomputer based on
the 740 family core technology.
The 3822 group (A version) has the LCD drive control circuit, an 8-
channel A-D converter, and a serial I/O as additional functions.
The various microcomputers in the 3822 group (A version) include
variations of internal memory size and packaging. For details, re-
fer to the section on part numbering.
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage
In high-speed mode
(at f(XIN) ≤ 10 MHz) ................................................... 4.5 to 5.5 V
(at f(XIN) ≤ 8 MHz) ..................................................... 4.0 to 5.5 V
In middle-speed mode (at f(XIN) ≤ 6 MHz) ............... 1.8 to 5.5 V
In low-speed mode .................................................... 1.8 to 5.5 V
●Power dissipation
FEATURES
●Basic machine-language instructions ...................................... 71
●The minimum instruction execution time ........................... 0.4 µs
(at f(XIN) = 10 MHz, High-speed mode)
●Memory size
In high-speed mode ................................................ 15 mW (std.)
(at f(XIN) = 8 MHz, Vcc = 5 V, Ta = 25 °C)
ROM ............................................................... 16 K to 48 K bytes
RAM ................................................................. 512 to 1024 bytes
●Programmable input/output ports ............................................ 49
In low-speed mode ................................................... 24 µW (std.)
(at f(XIN) stopped, f(XCIN) = 32 kHz, Vcc = 3 V, Ta = 25 °C)
●Operating temperature range..................................– 20 to 85 °C
●Software pull-up/pull-down resistors (Ports P0-P7 except port P40)
●Interrupts ................................................. 17 sources, 16 vectors
(includes key input interrupt)
APPLICATIONS
Camera, household appliances, consumer electronics, etc.
●Timers ........................................................... 8-bit ● 3, 16-bit ● 2
●Serial I/O...................... 8-bit ● 1 (UART or Clock-synchronized)
●A-D converter ................................................. 8-bit ● 8 channels
PIN CONFIGURATION (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
7
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
M3822XMXA-XXXFP
V
CC
V
X
X
SS
V
REF
OUT
IN
AVSS
COM
COM
COM
COM
VL
3
2
1
P7
P7
RESET
P4
P4
0
/XCOUT
/XCIN
1
0
3
0
1
/φ
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Package type : 80P6N-A (80-pin plastic-molded QFP)
Fig. 1 M3822XMXA-XXXFP pin configuration
Rev.1.20 Dec 24, 2003 page 1 of 57
3822 Group (A ver.)
PIN CONFIGURATION (TOP VIEW)
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P1
P1
P2
P2
P2
P2
P2
P2
P2
P2
6
7
0
1
2
3
4
5
6
7
/SEG30
/SEG31
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
9
8
7
6
5
4
3
2
1
0
M3822XMXA-XXXHP
V
CC
REF
AVSS
V
X
X
SS
V
OUT
IN
COM
COM
COM
COM
3
2
1
0
P7
P7
RESET
P4
P4
0/XCOUT
1
/XCIN
0
1/φ
V
V
V
L3
L2
L1
P4
P4
2
/INT
/INT
0
1
3
Package type : 80P6Q-A
(80-pin plastic-molded QFP)
Fig. 2 M3822XMXA-XXXHP pin configuration
Rev.1.20 Dec 24, 2003 page 2 of 57
FUNCTIONAL BLOCK DIAGRAM (Package type : 80P6Q-A)
Main Clock
Output XOUT
Reset Input
RESET
25
( 5 V )
VCC
71
Main Clock
Input XIN
( 0 V )
VSS
30
29
28
Data bus
Clock generating
circuit
C P U
80 VL1
79 VL2
78 VL3
R A M
A
X
Y
S
R O M
LCD display
RAM
(16 bytes)
77 COM
76 COM
75 COM
74 COM
0
1
2
3
LCD
drive control
circuit
XCIN
Sub-Clock Sub-Clock
Input Output
XCOUT
φ
PC
H
PC
L
70
SEG
69 SEG
68 SEG
0
Timer X(16)
Timer Y(16)
1
PS
2
3
4
5
6
7
8
9
67
SEG
Timer 1(8)
Timer 2(8)
Timer 3(8)
66 SEG
65 SEG
64 SEG
63 SEG
62 SEG
61 SEG
60 SEG10
59 SEG11
A-D
converter(8)
SI/O(8)
TOUT
CNTR
0
,CNTR1
XCOUT
XCIN
RTP0,RTP1
P5(8)
P4(8)
P2(8)
P1(8)
P0(8)
P6(8)
P3(4)
P7(2)
9
10 11 12 13 14 15 16
17 18 19 20 21 22 23 24
55 56 57 58
39 40 41 42 43 44 45 46
48
50
52 53 54
51
31 32 33 34 35 36 37 38
47
49
7
8
72 73
1
2
3
4
26 27
5
6
VREF
AVSS
( 0 V )
Input Port P3
I/O Port P2
I/O Port P1
I/O Port P0
I/O Port P6
I/O Port P5
I/O Port P4
I/O Port P7
3822 Group (A ver.)
PIN DESCRIPTION
Table 1 Pin description (1)
Pin
Name
Function
Function except a port function
VCC, VSS
Power source
•Apply voltage of power source to VCC, and 0 V to VSS. (For the limits of VCC, refer to “Recom-
mended operating conditions”).
VREF
AVSS
Analog refer-
ence voltage
•Reference voltage input pin for A-D converter.
Analog power
source
•GND input pin for A-D converter.
•Connect to VSS.
Reset input
Clock input
•Reset input pin for active “L”.
RESET
XIN
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
XOUT
Clock output
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
•This clock is used as the oscillating source of system clock.
LCD power
source
•Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
VL1–VL3
•Input 0 – VL3 voltage to LCD.
Common output
•LCD common output pins.
COM0–COM3
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
SEG0–SEG11
Segment output
I/O port P0
•LCD segment output pins.
P00/SEG16–
P07/SEG23
•8-bit I/O port.
•LCD segment output pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each port to be individually
programmed as either input or output.
P10/SEG24–
P17/SEG31
I/O port P1
I/O port P2
•Pull-down control is enabled.
•8-bit I/O port.
•Key input (key-on wake-up) interrupt
input pins
P20 – P27
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•4-bit input port.
•LCD segment output pins
P3
P3
4
7
/SEG12
/SEG15
–
Input port P3
•CMOS compatible input level.
•Pull-down control is enabled.
Rev.1.20 Dec 24, 2003 page 4 of 57
3822 Group (A ver.)
Table 2 Pin description (2)
Pin
Name
Function
Function except a port function
Input port P4
P40
•1-bit Input port.
•CMOS compatible input level.
•7-bit I/O port.
•φ clock output pin
P41/φ
I/O port P4
•Interrupt input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
P46/SCLK,
P47/SRDY
•Serial I/O function pins
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•8-bit I/O port.
I/O port P5
•Interrupt input pins
P50/INT2,
P51/INT3
•CMOS compatible input level.
•CMOS 3-state output structure.
•Real time port function pins
•Timer X, Y function pins
P52/RTP0,
P53/RTP1
•I/O direction register allows each pin to be individually
programmed as either input or output.
P54/CNTR0,
P55/CNTR1
•Pull-up control is enabled.
P56/TOUT
P57/ADT
•Timer 2 output pins
•A-D trigger input pins
P60/AN0–
P67/AN7
I/O port P6
•8-bit I/O port.
•A-D conversion input pins
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•2-bit I/O port.
I/O port P7
•Sub-clock generating circuit I/O pins.
P70/XCOUT,
P71/XCIN
•CMOS compatible input level.
•CMOS 3-state output structure.
(Connect a resonator. External clock
cannot be used.)
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
Rev.1.20 Dec 24, 2003 page 5 of 57
3822 Group (A ver.)
PART NUMBERING
Product
M38224
M
6
A- XXX
FP
Package type
FP : 80P6N-A package
HP : 80P6Q-A package
ROM number
Omitted in One Time PROM version shipped in blank and EPROM version.
When electrical characteristic, or division of identification code using
alaphanumeric character
A– : A version
ROM/PROM size
9 : 36864 bytes
A : 40960 bytes
B : 45056 bytes
C : 49152 bytes
1 : 4096 bytes
2 : 8192 bytes
3 : 12288 bytes
4 : 16384 bytes
5 : 20480 bytes
6 : 24576 bytes
7 : 28672 bytes
8 : 32768 bytes
The first 128 bites and the last 2 bytes of ROM are
reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
RAM size
0 : 192 bytes
1 : 256 bytes
2 : 384 bytes
3 : 512 bytes
4 : 640 bytes
5 : 768 bytes
6 : 896 bytes
7 : 1024 bytes
Fig. 4 Part numbering
Rev.1.20 Dec 24, 2003 page 6 of 57
3822 Group (A ver.)
GROUP EXPANSION (A VERSION)
Mitsubishi plans to expand the 3822 group (A version) as follows:
Package
80P6N-A .................................... 0.8 mm-pitch plastic molded QFP
80P6Q-A .................................... 0.5 mm-pitch plastic molded QFP
Memory Type
Support for Mask ROM version.
Memory Size
ROM size ........................................................... 16 K to 48 K bytes
RAM size ............................................................ 512 to 1024 bytes
Memory Expansion Plan
ROM size (bytes)
48K
M38227MCA
M38227M8A
32K
28K
24K
20K
M38224M6A
M38223M4A
16K
12K
8K
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Fig. 5 Memory expansion plan for A version
Currently products are listed below.
Table 3 List of products for H version
As of Sep. 2002
ROM size (bytes) ROM
Part number
RAM size (bytes)
512
Package
Remarks
size for User in (
)
M38223M4A-XXXFP
M38223M4A-XXXHP
M38224M6A-XXXFP
M38224M6A-XXXHP
M38227M8A-XXXFP
M38227M8A-XXXHP
M38227MCA-XXXFP
M38227MCA-XXXHP
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
80P6N-A
80P6Q-A
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
16384
(16254)
24576
(24446)
640
32768
(32638)
1024
49152
(49022)
Rev.1.20 Dec 24, 2003 page 7 of 57
3822 Group (A ver.)
FUNCTIONAL DESCRIPTION
[Stack Pointer (S)]
CENTRAL PROCESSING UNIT (CPU)
The 3822 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[Accumulator (A)]
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 7.
Store registers other than those described in Figure 7 with pro-
gram when the user needs them during interrupts or subroutine
calls.
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
b0
b7
A
Accumulator
b0
b7
X
Index register X
b7
b0
Y
Index register Y
b7
b0
S
Stack pointer
b15
b7
b0
PCH
PCL
Program counter
b7
b0
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Fig. 6 740 Family CPU register structure
Rev.1.20 Dec 24, 2003 page 8 of 57
3822 Group (A ver.)
On-going Routine
Execute JSR
Interrupt request
(Note)
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S) – 1
M (S) (PS)
(S) (S) – 1
Push return address
on stack
M (S) (PCH)
(S) (S) – 1
M (S) (PCL)
(S) (S)– 1
Subroutine
Push return address
on stack
Push contents of processor
status register on stack
Interrupt
Service Routine
I Flag is set from “0” to “1”
Fetch the jump vector
Execute RTS
(S) (S) + 1
Execute RTI
(S) (S) + 1
POP return
POP contents of
processor status
register from stack
address from stack
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
(PS)
M (S)
(S) (S) + 1
(PCL) M (S)
(S) (S) + 1
(PCH) M (S)
POP return
address
from stack
Note: Condition for acceptance of an interrupt
Interrupt enable flag is “1”
Interrupt disable flag is “0”
Fig. 7 Register push and pop at interrupt generation and subroutine call
Table 4 Push and pop instructions of accumulator or processor status register
Push instruction to stack
Pop instruction from stack
Accumulator
PHA
PHP
PLA
PLP
Processor status register
Rev.1.20 Dec 24, 2003 page 9 of 57
3822 Group (A ver.)
•Bit 4: Break flag (B)
[Processor status register (PS)]
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Table 5 Set and clear instructions of each bit of processor status register
N flag
C flag
SEC
CLC
Z flag
I flag
SEI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
–
–
–
–
–
–
–
Set instruction
CLI
CLV
Clear instruction
Rev.1.20 Dec 24, 2003 page 10 of 57
3822 Group (A ver.)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B16.
b7
b0
CPU mode register
(CPUM (CM) : address 003B16
)
Processor mode bits
b1 b0
0
0
1
1
0 : Single-chip mode
1 :
0 :
1 :
Not available
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit)
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : f(XIN)/2 (high-speed mode)
1 : f(XIN)/8 (middle-speed mode)
Internal system clock selection bit
0 : XIN–XOUT selected (middle-/high-speed mode)
1 : XCIN–XCOUT selected (low-speed mode)
Fig. 8 Structure of CPU mode register
Rev.1.20 Dec 24, 2003 page 11 of 57
3822 Group (A ver.)
MEMORY
Zero Page
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ter (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special Page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area.
Access to this area with only 2 bytes is possible in the special
page addressing mode.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
RAM area
000016
RAM size
(bytes)
Address
XXXX16
SFR area
Zero page
004016
005016
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
LCD display RAM area
010016
RAM
XXXX16
084016
Reserved area
Not used
ROM area
Address
YYYY16
Address
ZZZZ16
ROM size
(bytes)
YYYY16
ZZZZ16
Reserved ROM area
(128 bytes)
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 9 Memory map diagram
Rev.1.20 Dec 24, 2003 page 12 of 57
3822 Group (A ver.)
Port P0 (P0)
000016
002016
002116
002216
002316
002416
Timer X (low) (TXL)
Timer X (high) (TXH)
Timer Y (low) (TYL)
Timer Y (high) (TYH)
Timer 1 (T1)
000116 Port P0 direction register (P0D)
Port P1 (P1)
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
Port P1 output control register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
002516 Timer 2 (T2)
Timer 3 (T3)
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer X mode register (TXM)
Timer Y mode register (TYM)
Timer 123 mode register (T123M)
φ output control register (CKOUT)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
A-D control register (ADCON)
A-D conversion register (AD)
001616 PULL register A (PULLA)
PULL register B (PULLB)
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Transmit/Receive buffer register
Segment output enable register (SEG)
LCD mode register (LM)
(TB/RB)
Serial I/O status register (SIOSTS)
Serial I/O control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Fig. 10 Memory map of special function register (SFR)
Rev.1.20 Dec 24, 2003 page 13 of 57
3822 Group (A ver.)
I/O PORTS
b7
b0
Direction Registers (ports P2, P41-P47, and
P5-P7)
PULL register A
(PULLA: address 001616
)
The 3822 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0–P2, P41–P47 and P5-P7). The I/O ports P2,
P41–P47 and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
P0
P1
P2
P3
P7
0
0
0
4
0
–P0
–P1
–P2
–P3
, P7
7
7
7
7
1
pull-down
pull-down
pull-up
pull-down
pull-up
Not used (return “0” when read)
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
b7
b0
PULL register B
(PULLB : address 001716
)
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
P41
P44
P50
P54
P60
P64
–P4
–P4
–P5
–P5
–P6
–P6
3
7
3
7
3
7
pull-up
pull-up
pull-up
pull-up
pull-up
pull-up
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the in-
put/output direction of each individual port.
Not used (return “0” when read)
0: Disable
1: Enable
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
Fig. 11 Structure of PULL register A and PULL register B
Ports P3 and P40
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL reg-
ister B (address 001716), ports except for port P40 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Rev.1.20 Dec 24, 2003 page 14 of 57
3822 Group (A ver.)
Table 6 List of I/O port function
Name
Pin
Input/Output
Input/output,
individual ports input level
Non-Port Function
I/O Format
Related SFRs
Diagram No.
P00/SEG16–
P07/SEG23
Port P0
CMOS compatible
LCD segment output
PULL register A
(1)
Segment output enable
register
CMOS 3-state output
P10/SEG24–
P17/SEG31
Port P1
Input/output,
individual bits
CMOS compatible
input level
(2)
(3)
(4)
PULL register A
P20–P27
Port P2
Key input (key-on
wake-up) interrupt
input
Interrupt control register 2
CMOS 3-state output
Input
Input
CMOS compatible
input level
PULL register A
P34/SEG12–
P37/SEG15
LCD segment output
Port P3
Port P4
Segment output enable
register
CMOS compatible
input level
P40
(5)
(2)
P41/φ
φ clock output
CMOS compatible
input level
PULL register B
Input/output,
individual bits
φ
output control register
CMOS 3-state output
P42/INT0,
P43/INT1
PULL register B
External interrupt input
Interrupt edge selection
register
(6)
(7)
(8)
(9)
(2)
Serial I/O function I/O
External interrupt input
PULL register B
P44/RXD
P45/TXD
P46/SCLK
Serial I/O control register
Serial I/O status register
UART control register
P47/SRDY
CMOS compatible
input level
P50/INT2,
P51/INT3
PULL register B
Input/output,
individual bits
Port P5
Interrupt edge selection
register
CMOS 3-state output
Real time port
function output
PULL register B
P52/RTP0,
P53/RTP1
(10)
(11)
Timer X mode register
PULL register B
Timer X function I/O
P54/CNTR0
Timer X mode register
P55/CNTR1
Timer Y function input
Timer 2 function output
PULL register B
(12)
(13)
Timer Y mode register
PULL register B
P56/TOUT
P57/ADT
Timer 123 mode register
A-D trigger input
(12)
(14)
PULL register B
A-D control register
P60/AN0–
P67/AN7
Input/output,
individual bits
Port P6
Port P7
CMOS compatible
input level
A-D conversion input
CMOS 3-state output
(15)
(16)
CMOS compatible
input level
P70/XCOUT
P71/XCIN
Input/output,
individual bits
PULL register A
Sub-clock
CPU mode register
generating circuit I/O
CMOS 3-state output
LCD common output
LCD segment output
COM0–COM3
SEG0–SEG11
Output
Output
LCD mode register
(17)
(18)
Common
Segment
Notes 1: For details of how to use double function ports as function I/O ports, refer to the applicable sections.
2: When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
Especially, power source current may increase during execution of the STP and WIT instructions.
Fix the unused input pins to “H” or “L” through a resistor.
Rev.1.20 Dec 24, 2003 page 15 of 57
3822 Group (A ver.)
(1) Ports P0, P1
(2) Ports P2, P42, P43, P50, P51
VL2/VL3
VL1/VSS
Pull-up control
Segment output enable bit
(Note)
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Key input (Key-on wake-up) interrupt input
INT0–INT3 interrupt input
Pull-down control
Segment output enable bit
Note: Bit 0 of direction register.
(3) Ports P34–P37
(4) Port P40
VL2/VL3
VL1/VSS
Data bus
Data bus
Pull-down control
Segment output enable bit
(6) Port P44
(5) Port P41
Pull-up control
Pull-up control
Serial I/O enable bit
Receive enable bit
Direction register
Direction register
Port latch
Data bus
Data bus
Port latch
φ output control bit
φ
Serial I/O input
Fig. 12 Port block diagram (1)
Rev.1.20 Dec 24, 2003 page 16 of 57
3822 Group (A ver.)
(8) Port P4
6
(7) Port P4
5
Serial I/O clock-
synchronized selection bit
Serial I/O enable bit
Pull-up control
Pull-up control
P45
/T
x
D P-channel output disable bit
Serial I/O enable bit
Transmit enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Serial I/O output
Serial I/O clock output
Serial I/O clock input
(9) Port P4
7
(10) Ports P52, P53
Pull-up control
Pull-up control
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY output enable bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Real time port control bit
Data for real time port
Serial I/O ready output
(11) Port P5
4
(12) Ports P55, P5
7
Pull-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Timer X operating mode bit
(Pulse output mode selection)
Timer output
CNTR
1 interrupt input
A-D trigger interrupt input
CNTR
0
interrupt input
Fig. 13 Port block diagram (2)
Rev.1.20 Dec 24, 2003 page 17 of 57
3822 Group (A ver.)
(14) Port P6
(13) Port P56
Pul-up control
Pull-up control
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
T
OUT output control bit
Timer output
A-D conversion input
Analog input pin selection bit
(15) Port P70
(16) Port P71
Port X
C
switch bit + Pull-up control
Port XC switch bit + Pull-up control
Port X
C
switch bit
Port X
C
switch bit
Direction register
Direction register
Data bus
Port latch
Data bus
Port latch
Oscillation circuit
Port P7
Sub-clock generating circuit input
1
Port XC switch bit
(17) COM0–COM3
(18) SEG0–SEG11
V
L2/VL3
V
L3
The voltage applied to the sources of
V
L1/VSS
P-channel and N-channel transistors
is the controlled voltage by the bias
value.
V
V
L2
L1
The gate input signal of each transistor is
controlled by the LCD duty ratio and the
bias value.
Fig. 14 Port block diagram (3)
Rev.1.20 Dec 24, 2003 page 18 of 57
3822 Group (A ver.)
INTERRUPTS
Interrupts occur by seventeen sources: eight external, eight inter-
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
nal, and one software.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software
interrupt set by the BRK instruction. An interrupt occurs if the cor-
responding interrupt request and enable bits are “1” and the
interrupt disable flag is “0”.
●Notes on interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X mode register (address 2716)
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
Timer Y mode register (address 2816)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: A-D control regsiter (address 3416)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
The BRK instruction cannot be disabled with any flag or bit. The I
flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
●Set the corresponding interrupt enable bit to “0” (disabled).
●Set the interrupt edge select bit or the interrupt source select bit.
●Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
●Set the corresponding interrupt enable bit to “1” (enabled).
Table 7 Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Priority
High
Low
Generating Conditions
Reset (Note 2)
At reset
1
2
FFFD16
FFFB16
FFFC16
FFFA16
Non-maskable
INT0
At detection of either rising or
falling edge of INT0 input
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of INT1 input
INT1
FFF916
FFF716
FFF516
FFF816
FFF616
FFF416
External interrupt
(active edge selectable)
3
4
Serial I/O
reception
At completion of serial I/O data
reception
Valid when serial I/O is selected
Valid when serial I/O is selected
At completion of serial I/O trans-
mit shift or when transmission
buffer is empty
Serial I/O
transmission
5
Timer X
At timer X underflow
At timer Y underflow
At timer 2 underflow
At timer 3 underflow
6
7
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFF216
FFF016
FFEE16
FFEC16
FFEA16
Timer Y
Timer 2
Timer 3
8
9
CNTR0
At detection of either rising or
falling edge of CNTR0 input
10
External interrupt
(active edge selectable)
At detection of either rising or
falling edge of CNTR1 input
CNTR1
11
FFE916
FFE816
External interrupt
(active edge selectable)
FFE616
FFE416
At timer 1 underflow
Timer 1
INT2
12
13
FFE716
FFE516
At detection of either rising or
falling edge of INT2 input
External interrupt
(active edge selectable)
INT3
At detection of either rising or
falling edge of INT3 input
14
15
16
FFE316
FFE116
FFDF16
FFE216
FFE016
FFDE16
External interrupt
(active edge selectable)
Key input
(Key-on wake-up)
At falling of conjunction of input External interrupt
level for port P2 (at input mode)
(Valid at falling)
Valid when ADT interrupt is se-
lected, External interrupt
(Valid at falling)
ADT
At falling of ADT input
At completion of A-D conversion
At BRK instruction execution
A-D conversion
BRK instruction
Valid when A-D interrupt is se-
lected
17
FFDD16
FFDC16
Non-maskable software interrupt
Notes1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Rev.1.20 Dec 24, 2003 page 19 of 57
3822 Group (A ver.)
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
Interrupt request
BRK instruction
Reset
Fig. 15 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
INT
INT
0
1
2
3
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (return “0” when read)
b7
b0
b7
b0
Interrupt request register 2
Interrupt request register 1
(IREQ2 : address 003D16
)
(IREQ1 : address 003C16
)
INT
INT
0
1
interrupt request bit
interrupt request bit
CNTR
CNTR
0
1
interrupt request bit
interrupt request bit
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
Timer X interrupt request bit
Timer 1 interrupt request bit
INT
INT
2
interrupt request bit
interrupt request bit
3
Timer Y interrupt request bit
Key input interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0
b7
b0
Interrupt control register 1
Interrupt control register 2
(ICON1 : address 003E16
)
(ICON2 : address 003F16
)
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
CNTR
0
1
interrupt enable bit
interrupt enable bit
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
Timer X interrupt enable bit
Timer 1 interrupt enable bit
INT
INT
2
interrupt enable bit
interrupt enable bit
3
Timer Y interrupt enable bit
Key input interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers
Rev.1.20 Dec 24, 2003 page 20 of 57
3822 Group (A ver.)
“1” to “0”. An example of using a key input interrupt is shown in
Figure 17, where an interrupt request is generated by pressing
one of the keys consisted as an active-low key matrix which inputs
to ports P20–P23.
Key Input Interrupt (Key-on wake-up)
A Key-on wake-up interrupt request is generated by applying a
falling edge to any pin of port P2 that have been set to input mode.
In other words, it is gener1ated when AND of input level goes from
Port PX
X
“L” level output
PULL register A bit 2 = “1”
Port P2
direction register = “1”
7
Key input interrupt request
●
●●
●●
●●
●●
Port P2
latch
7
P2
7
output
output
Port P2
6
direction register = “1”
●
Port P2
latch
6
P2
6
Port P2
5
direction register = “1”
●
●
Port P2
latch
5
P2
5
output
output
Port P2
4
direction register = “1”
Port P2
latch
4
P2
4
Port P2
direction register = “0”
3
Port P2
●
●
●●
●●
Input reading circuit
Port P2
latch
3
P2
P2
3
input
Port P2
direction register = “0”
2
Port P2
latch
2
2
input
input
Port P2
direction register = “0”
1
●
●●
Port P2
latch
1
P2
1
Port P2
0
direction register = “0”
●
●
Port P2
latch
0
P2
0
input
● P-channel transistor for pull-up
●● CMOS output buffer
Fig. 17 Connection example when using key input interrupt and port P2 block diagram
Rev.1.20 Dec 24, 2003 page 21 of 57
3822 Group (A ver.)
responding to that timer is set to “1”.
TIMERS
Read and write operation on 16-bit timer must be performed for
both high and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
The 3822 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is
continued. When a timer underflows, the interrupt request bit cor-
Real time port
control bit “1”
Q D
Data bus
P52
data for real time port
P52
Latch
“0”
P5 latch
P5
2
direction register
2
Real time port
control bit “1”
Q D
P53
data for real time port
P5
3
Real time port
control bit “0”
Latch
“0”
P53 direction register
Timer X mode register
write signal
P53 latch
“1”
f(XIN)/16
(f(XIN)/16 in low-speed mode●)
Timer X stop
control bit
Timer X write
control bit
Timer X operat-
ing mode bits
“00”,“01”,“11”
CNTR0 active
edge switch bit
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer X
interrupt
request
“0”
P54/CNTR0
Timer X (low) (8)
Timer X (high) (8)
“10”
“1”
Pulse width
CNTR
0
measurement
interrupt
request
mode
CNTR
edge switch bit
0
active
Pulse output mode
“0”
“1”
S
Q
Q
Timer Y operating mode bits
“00”,“01”,“10”
T
CNTR
interrupt
request
1
P54 direction register
Pulse width HL continuously measurement mode
Rising edge detection
P54 latch
“11”
Pulse output mode
Period
measurement mode
Falling edge detection
f(XIN)/16
(f(XCIN)516 in low-speed mode
●
)
Timer Y stop
control bit
CNTR1 active
edge switch bit
“0”
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Timer Y (high) (8)
“00”,“01”,“11”
Timer Y
interrupt
request
P55
/CNTR
1
Timer Y (low) (8)
“10” Timer Y operating
mode bits
“1”
f(XIN)/16
Timer 1
interrupt
request
(f(XCIN)/16 in low-speed mode])
Timer 1 count source
selection bit
“0”
Timer 2 write
control bit
Timer 2 count source
selection bit
Timer 2 latch (8)
Timer 1 latch (8)
Timer 1 (8)
“0”
Timer 2
interrupt
request
X
CIN
Timer 2 (8)
“1”
“1”
f(XIN)/16
●
(f(XCIN)/16 in low-speed mode
)
T
OUT output
T
OUT output
control bit
active edge
switch bit
T
OUT output
control bit
“0”
S
Q
Q
P56/TOUT
T
“1”
P5
6
latch
P5
6
direction register
Timer 3 latch (8)
Timer 3 (8)
“0”
Timer 3
interrupt
request
f(XIN)/16(f(XCIN)/16 in low-speed mode●)
“1”
Timer 3 count
source selection bit
●
Internal clock
φ =XCIN /2
Fig. 18 Timer block diagram
Rev.1.20 Dec 24, 2003 page 22 of 57
3822 Group (A ver.)
Timer X
ꢀReal time port control
Timer X is a 16-bit timer that can be selected in one of four modes
and can be controlled the timer X write and the real time port by
setting the timer X mode register.
While the real time port function is valid, data for the real time port
are output from ports P52 and P53 each time the timer X
underflows. (However, after rewriting a data for real time port, if
the real time port control bit is changed from “0” to “1”, data are
output independent of the timer X operation.) If the data for the
real time port is changed while the real time port function is valid,
the changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction
registers to output mode.
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
(2) Pulse Output Mode
Each time the timer underflows, a signal output from the CNTR0
pin is inverted. Except for this, the operation in pulse output mode
is the same as in timer mode. When using a timer in this mode,
set the corresponding port P54 direction register to output mode.
ꢀNote on CNTR0 interrupt active edge
selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
(3) Event Counter Mode
switch bit.
The timer counts signals input through the CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P54 direction register to input mode.
b7
b0
Timer X mode register
(TXM : address 002716
)
(4) Pulse Width Measurement Mode
The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode). If
CNTR0 active edge switch bit is “0”, the timer counts while the in-
put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while
the input signal of CNTR0 pin is at “L”. When using a timer in this
mode, set the corresponding port P54 direction register to input
mode.
Timer X write control bit
0 : Write value in latch and counter
1 : Write value in latch only
Real time port control bit
0 : Real time port function invalid
1 : Real time port function valid
P5
2
data for real time port
data for real time port
P53
Timer X operating mode bits
b5 b4
0
0
1
1
0 : Timer mode
ꢀTimer X write control
1 : Pulse output mode
0 : Event counter mode
1 : Pulse width measurement mode
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch
at the same time.
CNTR0 active edge switch bit
0 : Count at rising edge in event counter mode
Start from “H” output in pulse output mode
Measure “H” pulse width in pulse width
measurement mode
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value
in the latch is loaded in timer X after timer X underflows.
If the value is written in latch only, when writing in the timer latch at
the timer underflow, the value is set in the timer and the latch at
one time. Additionally, unexpected value may be set in the high-or-
der counter when the writing in high-order latch and the underflow
of timer X are performed at the same timing.
Falling edge active for CNTR0 interrupt
1 : Count at falling edge in event counter mode
Start from “L” output in pulse output mode
Measure “L” pulse width in pulse width
measurement mode
Rising edge active for CNTR
Timer X stop control bit
0 : Count start
0 interrupt
1 : Count stop
Fig. 19 Structure of timer X mode register
Rev.1.20 Dec 24, 2003 page 23 of 57
3822 Group (A ver.)
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
b7
b0
(1) Timer Mode
The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode).
Timer Y mode register
(TYM : address 002816
)
Not used (return “0” when read)
Timer Y operating mode bits
b5 b4
(2) Period Measurement Mode
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
0
0
1
0 : Timer mode
1 : Period measurement mode
0 : Event counter mode
1 : Pulse width HL continuously measurement
mode
1
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge to falling edge
period in period measurement mode
The timer value just before the reloading at rising/falling of CNTR1
pin input signal is retained until the timer Y is read once after the
reload.
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR
Timer Y stop control bit
0 : Count start
The rising/falling timing of CNTR1 pin input signal is found by
CNTR1 interrupt. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
1 interrupt
1 : Count stop
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P55 direction register to input mode.
Fig. 20 Structure of timer Y mode register
(4) Pulse Width HL Continuously Measurement
Mode
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P55 direction register to input mode.
ꢀNote on CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and
falling edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Rev.1.20 Dec 24, 2003 page 24 of 57
3822 Group (A ver.)
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register. The timer
latch value is not affected by a change of the count source. How-
ever, because changing the count source may cause an
inadvertent count down of the timer, rewrite the value of timer
whenever the count source is changed.
b7
b0
Timer 123 mode register
(T123M :address 002916
)
T
OUT output active edge switch bit
0 : Start at “H” output
1 : Start at “L” output
T
OUT output control bit
0 : TOUT output disabled
1 : TOUT output enabled
ꢀTimer 2 write control
If the timer 2 write control bit is “0”, when the value is written in the
address of timer 2, the value is loaded in the timer 2 and the latch
at the same time.
Timer 2 write control bit
0 : Write data in latch and counter
1 : Write data in latch only
Timer 2 count source selection bit
0 : Timer 1 output
If the timer 2 write control bit is “1”, when the value is written in the
address of timer 2, the value is loaded only in the latch. The value
in the latch is loaded in timer 2 after timer 2 underflows.
1 : f(XIN)/16
(or f(XCIN)/16 in low-speed mode)
Timer 3 count source selection bit
0 : Timer 1 output
1 : f(XIN)/16
ꢀTimer 2 output control
(or f(XCIN)/16 in low-speed mode)
Timer 1 count source selection bit
0 : f(XIN)/16
When the timer 2 (TOUT) is output enabled, an inversion signal
from the TOUT pin is output each time timer 2 underflows.
In this case, set the port shared with the TOUT pin to the output
mode.
(or f(XCIN)/16 in low-speed mode)
1 : f(XCIN
)
Not used (return “0” when read)
Note: Internal clock φ is f(XCIN)/2 in the low-speed mode.
ꢀNotes on timer 1 to timer 3
When the count source of timer 1 to 3 is changed, the timer count-
ing value may be changed large because a thin pulse is generated
in count input of timer . If timer 1 output is selected as the count
source of timer 2 or timer 3, when timer 1 is written, the counting
value of timer 2 or timer 3 may be changed large because a thin
pulse is generated in timer 1 output.
Fig. 21 Structure of timer 123 mode register
Therefore, set the value of timer in the order of timer 1, timer 2
and timer 3 after the count source selection of timer 1 to 3.
Rev.1.20 Dec 24, 2003 page 25 of 57
3822 Group (A ver.)
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O can be selected by setting the mode
selection bit of the serial I/O control register to “1”.
SERIAL I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the transmit/receive buffer register.
Data bus
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
Address 001816
Receive buffer register
Receive shift register
Receive interrupt request (RI)
P44/RXD
Shift clock
Clock control circuit
P46/SCLK
Serial I/O
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
f(XIN
)
Baud rate generator
Address 001C16
1/4
(f(XCIN) in low-speed mode)
1/4
P47/SRDY1
Clock control circuit
Falling-edge detector
F/F
Shift clock
Transmit shift register shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit shift register
Transmit buffer register
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Address 001916
Serial I/O status register
Address 001816
Data bus
Fig. 22 Block diagram of clock synchronous serial I/O
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
D
0
0
D
1
1
D
2
D
3
3
D
4
4
D
5
5
D
6
6
D
7
7
Serial output T
XD
Serial input R
X
D
D
D
D
D
D
D
D
D
2
Receive enable signal SRDY
Write signal to receive/transmit
buffer register (address 001816
)
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
1 : The transmit interrupt (TI) can be generated either when the transmit buffer register has emptied (TBE=1) or after the transmit
shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is
Notes
output continuously from the T
XD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 23 Operation of clock synchronous serial I/O function
Rev.1.20 Dec 24, 2003 page 26 of 57
3822 Group (A ver.)
ter, but the two buffers have the same address in memory. Since
the shift register cannot be written to or read from directly, transmit
data is written to the transmit buffer, and receive data is read from
the receive buffer.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer register can hold a character while the next
character is being received.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer regis-
Data bus
Address 001816
Address 001A16
Receive buffer full flag (RBF)
Serial I/O control register
OE
Receive buffer register
Receive interrupt request (RI)
Character length selection bit
7 bits
P44/RXD
STdetector
Receive shift register
1/16
8 bits
PE FE
UART control register
SP detector
Address 001B16
Clock control circuit
Serial I/O synchronous clock selection bit
P46/SCLK
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
(f(XCIN) in low-speed mode)
ST/SP/PA generator
Transmit shift register shift completion flag (TSC)
1/16
Transmit interrupt source selection bit
P45
/T
X
D
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer register
Address 001916
Serial I/O status register
Address 001816
Data bus
Fig. 24 Block diagram of UART serial I/O
Transmit or receive clock
Transmit buffer write signal
TBE=0
TSC=0
TBE=0
TSC=1ꢀ
SP
TBE=1
TBE=1
ST
D0
D1
ST
D0
D1
SP
Serial output TXD
1 start bit
ꢀGenerated at 2nd bit in 2-stop-bit mode
7 or 8 data bits
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
D0
D1
ST
D0
D1
Serial input RXD
Notes
1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1” by the setting of the transmit interrupt source
selection bit (TIC) of the serial I/O control register.
3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.
4 : After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 25 Operation of UART serial I/O function
Rev.1.20 Dec 24, 2003 page 27 of 57
3822 Group (A ver.)
[Transmit Buffer/Receive Buffer Register
(TB/RB)] 001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer register is
write-only and the receive buffer register is read-only. If a charac-
ter bit length is 7 bits, the MSB of data stored in the receive buffer
register is “0”.
[Serial I/O Status Register (SIOSTS)] 001916
The read-only serial I/O status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O
status register clears all the error flags OE, PE, FE, and SE. Writ-
ing “0” to the serial I/O enable bit (SIOE) also clears all the status
flags, including the error flags.
All bits of the serial I/O status register are initialized to “0” at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to “1”, the transmit shift register shift completion flag
(bit 2) and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIOCON)] 001A16
The serial I/O control register contains eight control bits for the se-
rial I/O function.
[UART Control Register (UARTCON) ]001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial trans-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
ꢀNotes on serial I/O
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission
enalbed, take the following sequence.
ꢀSet the serial I/O transmit interrupt enable bit to “0” (disabled).
ꢀSet the transmit enable bit to “1”.
ꢀSet the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
ꢀSet the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.1.20 Dec 24, 2003 page 28 of 57
3822 Group (A ver.)
b7
b0
b7
b0
Serial I/O status register
(SIOSTS : address 001916
Serial I/O control register
(SIOCON : address 001A16
)
)
BRG count source selection bit (CSS)
0: f(XIN) (f(XCIN) in low-speed mode)
1: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Serial I/O synchronization clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronized serial
I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronized serial I/O is
selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
External clock input divided by 16 when UART is selected.
S
0: P4
1: P4
RDY output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinary I/O pin
pin operates as SRDY output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE) =0
1: (OE) U (PE) U (FE) =1
Serial I/O mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Not used (returns “1” when read)
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
b7
b0
UART control register
(UARTCON : address 001B16
(pins P4
1: Serial I/O enabled
(pins P4 –P4 operate as serial I/O pins)
4–P47 operate as ordinary I/O pins)
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return “1” when read)
Fig. 26 Structure of serial I/O control registers
Rev.1.20 Dec 24, 2003 page 29 of 57
3822 Group (A ver.)
A-D CONVERTER
[A-D Conversion Register (AD)] 003516
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
b7
b0
A-D control register
(ADCON : address 003416
)
Analog input pin selection bits
0 0 0 : P6
0 0 1 : P6
0 1 0 : P6
0 1 1 : P6
1 0 0 : P6
1 0 1 : P6
1 1 0 : P6
1 1 1 : P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[A-D Control Register (ADCON)] 003416
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at “0” during an A-D conversion, then changes to “1” when the
A-D conversion is completed. Writing “0” to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to “1”, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
V
REF input switch bit
0 : ON during conversion
1 : Always ON
AD external trigger valid bit
0 : A-D external trigger invalid
1 : A-D external trigger valid
Interrupt source selection bit
0 : Interrupt request at A-D
conversion completed
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 256, and outputs the divided voltages.
1 : Interrupt request at ADT
input falling
Not used (returns “0” when read)
[Channel Selector]
The channel selector selects one of the input ports P67/AN7–P60/
AN0, and inputs it to the comparator.
Fig. 27 Structure of A-D control register
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to at least 500 kHz during A-D conversion.
Use the clock divided from the main clock XIN as the internal clock φ.
Data bus
b7
b0
A-D control register
P57/ADT
3
ADT/A-D interrupt request
A-D control circuit
P60
P61
P62
P63
P64
P65
P66
P67
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
A-D conversion
register
Comparator
8
Resistor ladder
AVSS
VREF
Fig. 28 A-D converter block diagram
Rev.1.20 Dec 24, 2003 page 30 of 57
3822 Group (A ver.)
enable bit is set to “1” after data is set in the LCD mode register,
the segment output enable register and the LCD display RAM, the
LCD drive control circuit starts reading the display data automati-
cally, performs the bias control and the duty ratio control, and
displays the data on the LCD panel.
LCD DRIVE CONTROL CIRCUIT
The 3822 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
ꢀLCD display RAM
ꢀSegment output enable register
ꢀLCD mode register
ꢀSelector
Table 8 Maximum number of display pixels at each duty ratio
ꢀTiming controller
Duty ratio
2
Maximum number of display pixel
64 dots
ꢀCommon driver
ꢀSegment driver
or 8 segment LCD 8 digits
96 dots
ꢀBias control circuit
A maximum of 32 segment output pins and 4 common output pins
can be used.
3
4
or 8 segment LCD 12 digits
128 dots
Up to 128 pixels can be controlled for LCD display. When the LCD
or 8 segment LCD 16 digits
b7
b0
Segment output enable register
(SEG : address 003816
)
Segment output enable bit 0
0 : Input port P3 –P3
4
7
1 : Segment output SEG12–SEG15
Segment output enable bit 1
0 : I/O port P00,P01
1 : Segment output SEG16, SEG17
Segment output enable bit 2
0 : I/O port P02–P07
1 : Segment output SEG18–SEG23
Segment output enable bit 3
0 : I/O port P10,P11
1 : Segment output SEG24, SEG25
Segment output enable bit 4
0 : I/O port P1
2
1 : Segment output SEG26
Segment output enable bit 5
0 : I/O port P13–P17
1 : Segment output SEG27–SEG31
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
LCD mode register
(LM : address 003916
)
Duty ratio selection bits
0 0 : Not used
0 1 : 2 (use COM
1 0 : 3 (use COM
1 1 : 4 (use COM
Bias control bit
0 : 1/3 bias
0
0
0
, COM
–COM
–COM
1
2
3
)
)
)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
Not used (returns “0” when read)
(Do not write “1” to this bit)
LCD circuit divider division ratio selection bits
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(XCIN)/32
1 : f(XIN)/8192 (or f(XCIN)/8192 in low-speed
mode)
Note: LCDCK is a clock for a LCD timing controller.
Fig. 29 Structure of segment output enable register and LCD mode register
Rev.1.20 Dec 24, 2003 page 31 of 57
3822 Group (A ver.)
Fig. 30 Block diagram of LCD controller/driver
Rev.1.20 Dec 24, 2003 page 32 of 57
3822 Group (A ver.)
Table 9 Bias control and applied voltage to VL1–VL3
Bias Control and Applied Voltage to LCD
Power Input Pins
Bias value
Voltage value
To the LCD power input pins (VL1–VL3), apply the voltage shown
VL3=VLCD
in Table 9 according to the bias value.
1/3 bias
VL2=2/3 VLCD
VL1=1/3 VLCD
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
VL3=VLCD
1/2 bias
VL2=VL1=1/2 VLCD
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by
duty ratio.
Note 1: VLCD is the maximum value of supplied voltage for the
LCD panel.
Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the
LCD mode register).
Table 10 Duty ratio control and common pins used
Duty ratio selection bit
Duty
Common pins used
ratio
Bit 1
Bit 0
2
3
4
0
1
1
1
0
1
COM0, COM1 (Note 1)
COM0–COM2 (Note 2)
COM0–COM3
Notes1: COM2 and COM3 are open.
2: COM3 is open.
Contrast control
Contrast control
V
L3
V
L3
R1
R4
V
L2
V
L2
R2
R3
V
L1
V
L1
R5
R4 = R5
R1 = R2 = R3
1/3 bias
1/2 bias
Fig. 31 Example of circuit at each bias
Rev.1.20 Dec 24, 2003 page 33 of 57
3822 Group (A ver.)
LCD Drive Timing
LCD Display RAM
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
Address 004016 to 004F16 is the designated RAM for the LCD dis-
play. When “1” are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
(frequency of count source for LCDCK)
f(LCDCK) =
(divider division ratio for LCD)
f(LCDCK)
Frame frequency =
(duty ratio)
Bit
7
6
5
4
3
1
0
2
Address
SEG
SEG
SEG
SEG
SEG
0
004016
004116
004216
004316
004416
004516
004616
004716
004816
004916
004A16
004B16
004C16
004D16
004E16
004F16
SEG
SEG
SEG
SEG
SEG
1
2
4
6
8
3
5
7
9
SEG10
SEG12
SEG14
SEG16
SEG18
SEG20
SEG22
SEG24
SEG26
SEG28
SEG30
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
SEG25
SEG27
SEG29
SEG31
COM
0
COM
3
COM
COM
COM3
2
COM
1
2
COM
1
COM0
Fig. 32 LCD display RAM map
Rev.1.20 Dec 24, 2003 page 34 of 57
3822 Group (A ver.)
Internal logic
LCDCK timing
1/4 duty
Voltage level
V
V
V
L3
L2=VL1
SS
COM
COM
COM
COM
0
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
V
V
V
L3
L2=VL1
SS
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
0
COM
2
COM
1
COM
2
COM
1
COM
0
COM2
1/2 duty
V
V
V
L3
L2=VL1
SS
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
1
COM
0
COM
1
COM
1
COM
0
COM
1
COM0
Fig. 33 LCD drive waveform (1/2 bias)
Rev.1.20 Dec 24, 2003 page 35 of 57
3822 Group (A ver.)
Internal logic
LCDCK timing
1/4 duty
Voltage level
VL3
V
VL2
COM
0
VSL1S
COM
COM
COM
1
2
3
V
V
L3
SEG
0
SS
OFF
ON
OFF
ON
COM
3
COM3
COM
2
COM
1
COM
0
COM
2
COM
1
COM0
1/3 duty
VL3
VL2
VSL1S
V
COM
COM
COM
0
1
2
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
COM
0
COM
2
COM
1
COM
0
COM2
COM
2
COM
1
COM0
1/2 duty
VL3
VL2
VSL1S
V
COM
COM
0
1
V
V
L3
SEG
0
SS
ON
OFF
ON
OFF
ON
OFF
ON
OFF
COM
1
COM
0
COM
1
COM
0
COM
1
COM0
COM
1
COM0
Fig. 34 LCD drive waveform (1/3 bias)
Rev.1.20 Dec 24, 2003 page 36 of 57
3822 Group (A ver.)
φ CLOCK SYSTEM OUTPUT FUNCTION
The internal system clock φ can be output from port P41 by setting
the φ output control register. Set bit 1 of the port P4 direction reg-
ister to “1” when outputting φ clock.
b7
b0
φ output control register
(CKOUT : address 002A16)
φ output control bit
0 : port function
1 : φ clock output
Not used (return “0” when read)
Fig. 35 Structure of φ output control register
Rev.1.20 Dec 24, 2003 page 37 of 57
3822 Group (A ver.)
RESET CIRCUIT
Power on
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H”
level (the power source voltage should be between VCC(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD16 (high-order byte) and ad-
dress FFFC16 (low-order byte). Make sure that the reset input
voltage meets VIL spec. when a power source voltage passes
VCC(min.).
Power
source
voltage
RESET
VCC
0V
Reset input
voltage
V
IL spec.
0V
RESET
VCC
Power source voltage
detection circuit
Fig. 36 Reset Circuit Example
X
IN
φ
RESET
Internal
reset
Reset address from
vector table
Address
Data
?
?
?
?
FFFC
FFFD
ADH, ADL
AD
L
ADH
SYNC
X
IN : about 8000 cycles
Notes 1: The frequency relation of f(XIN) and f(φ) is f(XIN) =8•f(φ)
2: The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 37 Reset Sequence
Rev.1.20 Dec 24, 2003 page 38 of 57
3822 Group (A ver.)
Register Contents
0016
Address
000116
(1)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
PULL register A
0016
0016
0016
0016
0016
0016
000316
000516
000916
000B16
000D16
000F16
001616
001716
001916
001A16
001B16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
003416
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
(PS)
(2)
(3)
(4)
(5)
(6)
(7)
0
1
1
0
0
1
0
0
1
0
0
0
1
0
0
0
1
0
0
1
0
0
(8)
0016
0
(9)
PULL register B
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
Sirial I/O status register
Sirial I/O control register
UART control register
Timer X(Low)
0016
0
FF16
FF16
FF16
FF16
FF16
0116
FF16
0016
0016
0016
0016
1
Timer X(High)
Timer Y(Low)
Timer Y(High)
Timer 1
Timer 2
Timer 3
Timer X mode register
Timer Y mode register
Timer 123 mode register
φ output control register
A-D control register
Segment output enable register
LCD mode register
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0016
0016
0016
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt request register 2
Interrupt control register 1
Interrupt control register 2
Processor status register
Program counter
1
0016
0016
0016
0016
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Contents of address FFFD16
Contents of address FFFC16
(PCH)
(PCL)
Note: The contents of all other registers and RAM are undefined after reset, so they must be
initialized by software.
ꢀ: undefined
Fig. 38 Initial status of microcomputer after reset
Rev.1.20 Dec 24, 2003 page 39 of 57
3822 Group (A ver.)
CLOCK GENERATING CIRCUIT
Oscillation Control
The 3822 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between XIN and
XOUT (XCIN and XCOUT). Use the circuit constants in accordance
with the resonator manufacturer's recommended values. No exter-
nal resistor is needed between XIN and XOUT since a feed-back
resistor exists on-chip. However, an external feed-back resistor is
needed between XCIN and XCOUT.
(1) Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either XIN or XCIN divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0”. Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock φ is
not supplied to the CPU until timer 2 underflows. This allows timer
for the clock circuit oscillation to stabilize.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit
cannot directly input clocks that are externally generated. Accord-
ingly, be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
(2) Wait Mode
Frequency Control
If the WIT instruction is executed, the internal clock φ stops at an
“H” level. The states of XIN and XCIN are the same as the state be-
fore the executing the WIT instruction. The internal clock restarts
at reset or when an interrupt is received. Since the oscillator does
not stop, normal operation can be started immediately after the
clock is restarted.
(1) Middle-speed Mode
The internal clock φ is the frequency of XIN divided by 8.
After reset, this mode is selected.
(2) High-speed Mode
The internal clock φ is half the frequency of XIN.
(3) Low-speed Mode
ꢀThe internal clock φ is half the frequency of XCIN.
ꢀA low-power consumption operation can be realized by stopping
the main clock XIN in this mode. To stop the main clock, set bit 5
of the CPU mode register to “1”.
X
CIN
X
COUT
X
IN
XOUT
When the main clock XIN is restarted, set enough time for oscil-
lation to stabilize by programming.
Rf
Rd
Note: If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The
sufficient time is required for the sub-clock to stabilize, es-
pecially immediately after poweron and at returning from
stop mode. When switching the mode between middle/high-
speed and low-speed, set the frequency on condition that
f(XIN) > 3f(XCIN).
C
COUT
CIN
C
CIN
C
OUT
Fig. 39 Ceramic resonator circuit example
X
COUT
X
CIN
XIN
X
OUT
Rf
Open
Rd
External oscillation circuit
C
CIN
CCOUT
V
CC
V
SS
Fig. 40 External clock input circuit
Rev.1.20 Dec 24, 2003 page 40 of 57
3822 Group (A ver.)
X
COUT
X
CIN
“1”
“0”
Port X
C
switch bit
Timer 1 count
source selection
bit
Timer 2 count
source selection
bit
Internal system clock selection bit
X
IN
X
OUT
(Note)
Low-speed mode
“1”
“1”
“0”
Timer 1
Timer 2
1/2
1/2
1/4
“0”
“0”
“1”
Middle-/High-speed mode
Main clock division ratio selection bit
Middle-speed mode
“1”
“0”
Timing φ
(Internal system clock)
High-speed mode
or Low-speed mode
Main clock stop bit
Q
Q
S
R
S
R
S
R
Q
WIT
instruction
STP instruction
STP instruction
Reset
Interrupt disable flag I
Interrupt request
Note : When using the low-speed mode, set the port X
C
switch bit to “1” .
Fig.41 Clock generating circuit block diagram
Rev.1.20 Dec 24, 2003 page 41 of 57
3822 Group (A ver.)
Reset
CM
“1”
6
Middle-speed mode (f(φ) = 1 MHz)
High-speed mode (f(φ) = 4 MHz)
“0”
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 0 (32 kHz stopped)
”
0
“
M4
”
C
0
“
”
M6
1
“
C
”
1
“
CM
“1”
6
Middle-speed mode (f(φ) = 1 MHz)
High-speed mode (f(φ) = 4 MHz)
“0”
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 0 (8 MHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
CM
“1”
6
Low-speed mode (f(φ) =16 kHz)
Low-speed mode (f(φ) = 16 kHz)
“0”
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 0 (High-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 0 (8 MHz oscillating)
= 1 (32 kHz oscillating)
b7
b4
CPU mode register
(CPUM : address 003B16
)
CM
CM
CM
CM
4 : Port Xc switch bit
0: I/O port
1: XCIN, XCOUT
5 : Main clock (XIN–XOUT) stop bit
0: Oscillating
1: Stopped
”
0
“
M5
”
C
0
“
”
M6
1
“
C
”
1
“
6
: Main clock division ratio selection bit
CM
“1”
6
0: f(XIN)/2 (high-speed mode)
1: f(XIN)/8 (middle-speed mode)
Low-speed mode (f(φ) =16 kHz)
Low-speed mode (f(φ) = 16 kHz)
“0”
CM
CM
CM
CM
7
6
5
4
= 1 (32 kHz selected)
= 1 (Middle-speed)
= 1 (8 MHz stopped)
= 1 (32 kHz oscillating)
CM
CM
CM
CM
7
6
5
4
=1(32 kHz selected)
=0(High-speed)
=1(8 MHz stopped)
=1(32 kHz oscillating)
7
: Internal system clock selection bit
0: XIN–XOUT selected
(middle-/high-speed mode)
1: XCIN–XCOUT selected
(low-speed mode)
Notes
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wait mode is
ended.
3 : Timer and LCD operate in the wait mode.
4 : When the stop mode is ended, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2 in middle-/high-speed mode.
5 : When the stop mode is ended, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 2 in low-speed mode.
6 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle-/high-speed mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.
Fig. 42 State transitions of system clock
Rev.1.20 Dec 24, 2003 page 42 of 57
3822 Group (A ver.)
NOTES ON PROGRAMMING
A-D Converter
Processor Status Register
The comparator uses internal capacitors whose charge will be lost
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz during an A-D conver-
sion.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
Interrupt
Instruction Execution Time
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perform-
ing a BBC or BBS instruction.
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Decimal Calculations
The frequency of the internal clock φ is half of the XIN frequency.
• To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instruction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
• In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n + 1).
Multiplication and Division Instructions
The index mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an ex-
ternal clock and it is to output the SRDY signal, set the transmit
enable bit, the receive enable bit, and the SRDY output enable bit
to “1”.
Serial I/O continues to output the final bit from the TXD pin after
transmission is completed.
Rev.1.20 Dec 24, 2003 page 43 of 57
3822 Group (A ver.)
NOTES ON USE
Countermeasures against noise
Noise
(1) Shortest wiring length
ꢀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin
as short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring
(within 20mm).
X
X
V
IN
X
X
V
IN
OUT
OUT
SS
SS
ꢀ Reason
O.K.
N.G.
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
Fig. 44 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
In order to stabilize the system operation and avoid the latch-up,
connect an approximately 0.1 µF bypass capacitor across the VSS
line and the VCC line as follows:
Noise
• Connect a bypass capacitor across the VSS pin and the VCC pin
at equal length.
Reset
RESET
circuit
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
V
SS
VSS
• Use lines with a larger diameter than other signal lines for VSS
line and VCC line.
N.G.
• Connect the power source wiring via a bypass capacitor to the
VSS pin and the VCC pin.
Reset
circuit
RESET
V
CC
V
CC
V
SS
VSS
O.K.
Fig. 43 Wiring for the RESET pin
ꢀ Wiring for clock input/output pins
V
SS
V
SS
• Make the length of wiring which is connected to clock I/O pins
as short as possible.
N.G.
O.K.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS
patterns.
Fig. 45 Bypass capacitor across the VSS line and the VCC line
ꢀ Reason
If noise enters clock I/O pins, clock waveforms may be de-
formed. This may cause a program failure or program runaway.
Also, if a potential difference is caused by the noise between
the VSS level of a microcomputer and the VSS level of an oscil-
lator, the correct clock will not be input in the microcomputer.
Rev.1.20 Dec 24, 2003 page 44 of 57
3822 Group (A ver.)
(4) Analog input
(3) Oscillator concerns
The analog input pin is connected to the capacitor of a voltage
In order to obtain the stabilized operation clock on the user system
and its condition, contact the oscillator manufacturer and select
the oscillator and oscillation circuit constants. Be careful espe-
cially when range of votage and temperature is wide.
Also, take care to prevent an oscillator that generates clocks for a
microcomputer operation from being affected by other signals.
comparator. Accordingly, sufficient accuracy may not be obtained
by the charge/discharge current at the time of A-D conversion
when the analog signal source of high-impedance is connected to
an analog input pin. In order to obtain the A-D conversion result
stabilized more, please lower the impedance of an analog signal
source, or add the smoothing capacitor to an analog input pin.
ꢀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as
possible from signal lines where a current larger than the toler-
ance of current value flows.
(5) Difference of memory type and size
When Mask ROM and PROM version and memory size differ in
one group, actual values such as an electrical characteristics, A-D
conversion accuracy, and the amount of -proof of noise incorrect
operation may differ from the ideal values.
ꢀ Reason
When these products are used switching, perform system evalua-
tion for each product of every after confirming product
specification.
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise oc-
curs because of mutual inductance.
(6) Wiring to VPP pin of One Time PROM version
Connect an approximately 5 kΩ resistor to the VPP pin the
shortest possible in series and also to the VSS pin.
ꢀ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator
away from signal lines where potential levels change frequently.
Also, do not cross such signal lines over the clock lines or the
signal lines which are sensitive to noise.
Note: Even when a circuit which included an approximately 5 kΩ
resistor is used in the Mask ROM version, the microcomputer
operates correctly.
ꢀ Reason
ꢀ Reason
The VPP pin of the One Time PROM version is the power source
input pin for the built-in PROM. When programming in the built-in
PROM, the impedance of the VPP pin is low to allow the electric
current for writing flow into the built-in PROM. Because of this,
noise can enter easily. If noise enters the VPP pin, abnormal in-
struction codes or data are read from the built-in PROM, which
may cause a program runaway.
Signal lines where potential levels change frequently (such as
the CNTR pin signal line) may affect other lines at signal rising
edge or falling edge. If such lines cross over a clock line, clock
waveforms may be deformed, which causes a microcomputer
failure or a program runaway.
ꢀ Keeping oscillator away from large current signal lines
Microcomputer
About 5kΩ
Mutual inductance
M
P40/VPP
X
X
IN
VSS
Large
current
OUT
V
SS
GND
Fig. 47 Wiring for the VPP pin of One Time PROM
ꢀ Installing oscillator away from signal lines where potential
levels change frequently
Electric Characteristic Differences Between
Mask ROM and One Time PROM Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between Mask ROM and
One Time PROM version MCUs due to the difference in the manufac-
turing processes.
CNTR
Do not cross
XIN
X
OUT
V
SS
When manufacturing an application system with the One TIme PROM
version and then switching to use of the Mask ROM version,
please perform sufficient evaluations for the commercial
samples of the Mask ROM version.
N.G.
Fig. 46 Wiring for a large current signal line/Wiring of signal
lines where potential levels change frequently
Rev.1.20 Dec 24, 2003 page 45 of 57
3822 Group (A ver.)
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ꢀ
1.Mask ROM Order Confirmation Form
ꢀ
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk
ꢀFor the mask ROM confirmation and the mark specifications, re-
fer to the “Renesas Technology” Homepage (http://
www.renesas.com/en/rom/).
Rev.1.20 Dec 24, 2003 page 46 of 57
3822 Group (A ver.)
Table 11 Absolute maximum ratings (A version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 6.5
All voltages are based on VSS.
Output transistors are cut off.
VI
Input voltage P00–P07, P10–P17, P20–P27,
P34–P37, P40–P47, P50–P57
P60–P67, P70, P71
–0.3 to VCC +0.3
V
V
V
V
V
V
V
V
–0.3 to VL2
VL1 to VL3
Input voltage VL1
VI
VI
VI
VI
VO
Input voltage VL2
VL2 to 6.5
Input voltage VL3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VL3
Input voltage RESET, XIN
Output voltage P00–P07, P10–P17
At output port
At segment output
At segment output
VO
VO
–0.3 to VL3
Output voltage P34–P37
Output voltage P20–P27, P41–P47,P50–P57,
P60–P67, P70, P71
–0.3 to VCC +0.3
V
VO
Output voltage SEG0–SEG11
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
–0.3 to VL3
–0.3 to VCC +0.3
300
V
V
VO
Pd
mW
°C
°C
Ta = 25°C
Topr
Tstg
–20 to 85
–40 to 150
Table 12 Recommended operating conditions (A version)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
High-speed mode
Unit
Min.
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
Max.
f(XIN) = 10 MHz
f(XIN) = 8 MHz
f(XIN) = 6 MHz
f(XIN) = 4 MHz
4.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
V
V
V
V
V
V
V
V
VCC
Power source voltage
(Note 1)
4.0
3.0
2.0
Middle-speed mode f(XIN) = 10 MHz
f(XIN) = 8 MHz
3.0
2.0
1.8
f(XIN) = 6 MHz
Low-speed mode
1.8
When oscillation starts (Note 2)
0.15 ✕ f + 1.3
VSS
Power source voltage
0
0
VREF
AVSS
VIA
A-D conversion reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
2.0
VCC
VCC
AVSS
Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D converter.
2: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator
will require some conditions of oscillation.
f : Means an oscillation frequency (MHz) of an oscillator. If it is 8, substitute 8 for “f”.
Rev.1.20 Dec 24, 2003 page 47 of 57
3822 Group (A ver.)
Table 13 Recommended operating conditions (A version)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
V
Min.
Max.
VCC
“H” input voltage
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47,
P52, P53,P56,P60–P67,P70,P71 (CM4= 0)
VIH
0.7VCC
“H” input voltage
“H” input voltage
“H” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIH
VIH
VIH
VIL
0.8VCC
0.8VCC
0.8VCC
0
VCC
VCC
V
V
V
V
RESET
XIN
VCC
P00–P07, P10–P17,P34–P37, P40, P41, P45, P47, P52, P53,
P56,P60–P67,P70,P71 (CM4= 0)
0.3 VCC
“L” input voltage
“L” input voltage
“L” input voltage
P20–P27, P42–P44,P46,P50, P51, P54, P55, P57
VIL
VIL
VIL
0
0
0
0.2 VCC
0.2 VCC
0.2 VCC
V
V
V
RESET
XIN
Rev.1.20 Dec 24, 2003 page 48 of 57
3822 Group (A ver.)
Table 14 Recommended operating conditions (A version)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
–40
–40
40
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
“H” total average output current
“H” total average output current
“L” total average output current
“L” total average output current
“H” peak output current
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17, P20–P27 (Note 1)
P41–P47, P50–P57, P60–P67, P70, P71 (Note 1)
P00–P07, P10–P17 (Note 2)
40
–20
–20
20
20
–2
“H” peak output current
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
–5
(Note 2)
IOL(peak)
IOL(peak)
“L” peak output current
“L” peak output current
mA
mA
P00–P07, P10–P17 (Note 2)
5
10
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 2)
–1.0
–2.5
mA
mA
IOH(avg)
IOH(avg)
“H” average output current
“H” average output current
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
mA
mA
“L” average output current
“L” average output current
2.5
5.0
IOL(avg)
IOL(avg)
P00–P07, P10–P17 (Note 3)
P20–P27, P41–P47, P50–P57, P60–P67, P70, P71
(Note 3)
f(CNTR0)
f(CNTR1)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC ≤ 4.5 V)
(2.0 V ≤ VCC ≤ 4.0 V)
(VCC ≤ 2.0 V)
5.0
MHz
Input frequency for timers X and Y
(duty cycle 50%)
2 ✕ VCC – 4 MHz
MHz
5 ✕ VCC – 8 MHz
10.0
MHz
VCC
High-speed mode
(4.5 V ≤ VCC ≤ 5.5 V)
f(XIN)
Main clock input oscillation frequency
(duty cycle 50%)
(Note 4)
High-speed mode
(4.0 V ≤ VCC ≤ 4.5 V)
4 ✕ VCC – 8 MHz
High-speed mode
(2.0 V ≤ VCC ≤ 4.0 V)
2 ✕ VCC
10.0
MHz
MHz
MHz
Middle-speed mode (Note 6)
(3.0 V ≤ VCC ≤ 5.5 V)
Middle-speed mode (Note 6)
(2.0 V ≤ VCC ≤ 5.5 V)
8.0
Middle-speed mode (Note 6)
6.0
50
MHz
kHz
f(XCIN)
Sub-clock input oscillation frequency
(duty cycle 50%)
32.768
(Notes 5, 6)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value
measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is an average value measured over 100 ms.
4: When the A-D converter is used, refer to the recommended operating condition for A-D converter.
5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
6: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially high-frequency oscillator
will require some conditions of oscillation.
Rev.1.20 Dec 24, 2003 page 49 of 57
3822 Group (A ver.)
Table 15 Electrical characteristics (A version)
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
IOH = –2.5 mA
Unit
Min.
Max.
VCC–2.0
V
V
“H” output voltage
P00–P07, P10–P17
VOH
IOH = –0.6 mA
VCC = 2.5 V
VCC–1.0
IOH = –5 mA
VCC–2.0
VCC–0.5
V
V
“H” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
IOH = –1.25 mA
VOH
VOL
IOH = –1.25 mA
VCC = 2.5 V
VCC–1.0
V
IOL = 5 mA
2.0
0.5
V
V
“L” output voltage
P00–P07, P10–P7
IOL = 1.25 mA
IOL = 1.25 mA
VCC = 2.5 V
1.0
V
2.0
0.5
V
V
IOL = 10 mA
IOL = 2.5 mA
“L” output voltage
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VOL
IOL = 2.5 mA
VCC = 2.5 V
1.0
V
V
VT+ – VT–
Hysteresis
0.5
INT0–INT3, ADT, CNTR0, CNTR1, P20–P27
VT+ – VT–
VT+ – VT–
Hysteresis
Hysteresis
SCLK, RXD
RESET
0.5
0.5
V
V
RESET : VCC = 2.2 V to 5.5 V
IIH
IIH
“H” input current
VI = VCC
Pull-downs “off”
5.0
140
45
µA
µA
µA
P00–P07, P10–P17, P34–P37
VCC = 5 V, VI = VCC
Pull-downs “on”
30
70
25
VCC = 3 V, VI = VCC
Pull-downs “on”
6.0
“H” input current
VI = VCC
P20–P27, P40–P47, P50–P57, P60–P67,
P70, P71 (Note)
5.0
5.0
µA
IIH
IIH
IIL
“H” input current RESET
“H” input current XIN
VI = VCC
VI = VCC
VI = VSS
µA
µA
4.0
“L” input current
P00–P07, P10–P17, P34–P37,P40
–5.0
–5.0
µA
µA
IIL
“L” input current
VI = VSS
Pull-ups “off”
P20–P27, P41–P47, P50–P57, P60–P67,
P70, P71 (Note)
VCC = 5 V, VI = VSS
Pull-ups “on”
–30
–70
–25
–140
µA
µA
VCC = 3 V, VI = VSS
Pull-ups “on”
–6.0
–45
IIL
IIL
“L” input current RESET
“L” input current XIN
VI = VSS
VI = VSS
–5.0
µA
µA
–4.0
Note: When “1” is set to the port XC switch bit (bit 4 at address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above
mentioned.
Rev.1.20 Dec 24, 2003 page 50 of 57
3822 Group (A ver.)
Table 16 Electrical characteristics (A version)
(VCC = 1.8 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
V
Min.
1.8
Max.
5.5
VRAM
RAM retention voltage
At clock stop mode
• High-speed mode, VCC = 5 V
f(XIN) = 10 MHz
5.0
3.0
0.8
10
6.0
1.6
mA
mA
mA
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter in operating
• High-speed mode, VCC = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “off”
A-D converter stopped
ICC
Power source current
• Low-speed mode, VCC = 5 V, Ta ≤ 55°C
f(XIN) = stopped
13
26
11
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 5 V, Ta = 25°C
f(XIN) = stopped
5.5
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta ≤ 55°C
f(XIN) = stopped
8.0
16
µA
µA
f(XCIN) = 32.768 kHz
Output transistors “off”
• Low-speed mode, VCC = 3 V, Ta = 25°C
f(XIN) = stopped
4.0
0.1
8.0
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “off”
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
1.0
10
µA
µA
Rev.1.20 Dec 24, 2003 page 51 of 57
3822 Group (A ver.)
Table 17 A-D converter characteristics (A version)
(VCC = 2.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, 4 MHz ≤ f(XIN) ≤ 10 MHz, in middle/high-speed mode unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
8
Bits
–
–
Resolution
±2
LSB
VCC = VREF = 2.2 V to 5.5 V
f(XIN) = 2 ✕ VCC MHz ≤ 10 MHz
Absolute accuracy
(excluding quantization error)
VCC = VREF < 2.2 V
f(XIN) ≤ 12 ✕ VCC – 22 MHz
±3
LSB
12.5
(Note)
tCONV
Conversion time
µs
f(XIN) = 8 MHz
VREF = 5 V
RLADDER
IVREF
IIA
Ladder resistor
kΩ
µA
µA
35
100
200
5.0
12
50
Reference power source input current
Analog port input current
150
Note: When an internal trigger is used in middle-speed mode, it is 14 µs.
Rev.1.20 Dec 24, 2003 page 52 of 57
3822 Group (A ver.)
Table 18 Timing requirements 1 (A version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
4.0 ≤ Vcc < 4.5 V
4.5 ≤ Vcc ≤ 5.5 V
1000/(4 ✕ VCC–8)
100
twH(XIN)
45
40
twL(XIN)
45
40
tc(CNTR)
twH(CNTR)
twL(CNTR)
1000/(2 ✕ VCC–4)
200
105
85
105
85
twH(INT)
twL(INT)
tc(SCLK)
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
80
80
800
370
370
220
100
twH(SCLK)
twL(SCLK)
t
su(RXD–SCLK)
th(SCLK–RXD) Serial I/O input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 19 Timing requirements 2 (A version)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
tw(RESET)
tc(XIN)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
125
1000/(10 ✕ VCC–12)
twH(XIN)
twL(XIN)
tc(CNTR)
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
50
70
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
50
70
1000/VCC
1000/(5 ✕ VCC–8)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
2.0 ≤ Vcc ≤ 4.0 V
Vcc < 2.0 V
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT3 input “H” pulse width
INT0 to INT3 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input set up time
230
tc(SCLK)
2000
twH(SCLK)
twL(SCLK)
950
950
t
su(RXD–SCLK)
400
th(SCLK–RXD) Serial I/O input hold time
200
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Rev.1.20 Dec 24, 2003 page 53 of 57
3822 Group (A ver.)
Table 20 Switching characteristics 1 (A version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
140
tC (SCLK)/2–30
tC (SCLK)/2–30
ns
ns
ns
ns
ns
ns
twH(SCLK)
twL(SCLK)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
td(SCLK–TXD) Serial I/O output delay time (Note)
tv(SCLK–TXD) Serial I/O output valid time (Note)
–30
Serial I/O clock output rising time
Serial I/O clock output falling time
30
30
tr(SCLK)
tf(SCLK)
Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Table 21 Switching characteristics 2 (A version)
(VCC = 1.8 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Serial I/O clock output “H” pulse width
Unit
Min.
Max.
350
ns
ns
ns
ns
ns
ns
tC (SCLK)/2–100
tC (SCLK)/2–100
twH(SCLK)
twL(SCLK)
td(SCLK–TXD)
tv(SCLK–TXD)
tr(SCLK)
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note)
Serial I/O output valid time (Note)
Serial I/O clock output rising time
Serial I/O clock output falling time
–30
100
100
tf(SCLK)
Notes : When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
Measurement output pin
1 kΩ
100 pF
Measurement output pin
100 pF
CMOS output
N-channel open-drain output (Note)
Note: When bit 4 of the UART control register
(address 001B16) is “1”. (N-channel open-
drain output mode)
Fig. 48 Circuit for measuring output switching characteristics
Rev.1.20 Dec 24, 2003 page 54 of 57
3822 Group (A ver.)
tC(CNTR)
tWH(CNTR)
0.8VCC
tWL(CNTR)
CNTR0, CNTR1
0.2VCC
tWH(INT)
0.8VCC
tWL(INT)
INT0–INT3
0.2VCC
tW(RESET)
0.8VCC
RESET
0.2VCC
tC(XIN)
tWL(XIN)
tWH(XIN)
0.8VCC
XIN
0.2VCC
tC(SCLK)
tf
tr
tWH(SCLK)
tWL(SCLK)
0.2VCC
SCLK
0.8VCC
tsu(RXD-SCLK)
th(SCLK-RXD)
RXD
TXD
0.8VCC
0.2VCC
td(SCLK-TXD)
tv(SCLK-TXD)
Fig. 49 Timing diagram
Rev.1.20 Dec 24, 2003 page 55 of 57
3822 Group (A ver.)
PACKAGE OUTLINE
MMP
80P6N-A
Plastic 80pin 14✕20mm body QFP
EIAJ Package Code
JEDEC Code
–
Weight(g)
1.58
Lead Material
Alloy 42
MD
QFP80-P-1420-0.80
HD
D
80
65
1
64
I
2
Recommended Mount Pad
Dimension in Millimeters
Symbol
Min
–
0
–
0.3
0.13
13.8
19.8
–
16.5
22.5
0.4
–
–
–
0°
–
1.3
–
Nom
–
Max
3.05
0.2
–
0.45
0.2
14.2
20.2
–
17.1
23.1
0.8
–
0.2
0.1
10°
–
A
A
A
1
2
0.1
2.8
0.35
0.15
14.0
20.0
0.8
16.8
22.8
0.6
1.4
–
–
–
0.5
–
14.6
20.6
b
c
D
E
e
24
41
25
40
A
HD
L1
HE
L
L1
x
y
F
e
b
L
b2
x
M
Detail F
I
2
–
–
–
y
M
M
D
E
–
Rev.1.20 Dec 24, 2003 page 56 of 57
3822 Group (A ver.)
MMP
80P6Q-A
Plastic 80pin 12✕12mm body LQFP
EIAJ Package Code
LQFP80-P-1212-0.5
JEDEC Code
Weight(g)
0.47
Lead Material
Cu Alloy
MD
–
HD
D
80
61
l
2
1
60
Recommended Mount Pad
Dimension in Millimeters
Symbol
A
Min
–
Nom
–
Max
1.7
0.2
–
A1
0
0.1
A
2
–
1.4
b
0.13
0.105
11.9
11.9
–
0.18
0.125
12.0
12.0
0.5
0.28
0.175
12.1
12.1
–
c
D
E
e
20
41
21
40
H
H
L
D
13.8
13.8
0.3
–
0.45
–
–
–
0°
–
14.0
14.0
0.5
1.0
0.6
0.25
–
–
14.2
14.2
0.7
–
0.75
–
0.08
0.1
10°
–
A
E
L
1
F
L1
e
Lp
A3
x
y
–
b
y
x
M
L
b2
0.225
–
12.4
12.4
I
2
0.9
–
–
–
–
–
Lp
Detail F
M
M
D
E
Rev.1.20 Dec 24, 2003 page 57 of 57
REVISION HISTORY
3822 GROUP (A ver.) DATA SHEET
Rev.
Date
Description
Summary
Page
1.0
1.1
09/26/02
10/10/02
First edition
1
[FEATURES] Power source voltage: f(XIN) = → f(XIN) ≤
4
6
Table 1 P0 and P1 Function: 8-bit output port → 8-bit I/O port
Fig. 4: M 6 A → M 6 A-
15
30
51
52
53
Table 6: [Notes] are revised.
Fig. 27: The explanation of VREF input switch bit is revised.
Table 16: VRAM Limits (Min.) is revised.
Table 17: Test conditions of Absolute accuracy are revised.
Tables 18, 19: Some parameters are added.
1.20 12/24/03
7
Fig. 5: “Under development” eliminated.
40
46
47
52
Fig. 39: a resistor is added to XOUT pin and Fig. title is revised.
DATA REQUIRED FOR MASK ORDERS: URL is revised.
Table 11: Input voltage VL3 is revised
Table 17: Test conditions of Absolute accuracy is revised.
(1/X)
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
imported into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
相关型号：
M38062M4DXXXFP
Microcontroller, 8-Bit, MROM, MELPS740 CPU, 8MHz, CMOS, PQFP80, 0.80 MM PITCH, PLASTIC, QFP-80
MITSUBISHI
©2020 ICPDF网 联系我们和版权申明