M38063ED-FP [RENESAS]
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER; 单片8位CMOS微机
| 型号： | M38063ED-FP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 文件： | 总58页 (文件大小：798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DESCRIPTION
The 3806 group is 8-bit microcomputer based on the 740 family
Clock generating circuit ....................... Internal feedback resistor
•
(connect to external ceramic resonator or quartz-crystal)
core technology.
Memory expansion possible
•
The 3806 group is designed for controlling systems that require
analog signal processing and include two serial I/O functions, A-D
converters, and D-A converters.
Specification
(unit)
Extended operating High-speed
Standard
0.5
temperature version
version
The various microcomputers in the 3806 group include variations
of internal memory size and packaging. For details, refer to the
section on part numbering.
Minimum instruction
0.5
0.4
execution time
(µs)
For details on availability of microcomputers in the 3806 group, re-
fer to the section on group expansion.
Oscillation frequency
(MHz)
8
8
10
Power source voltage
(V)
FEATURES
3.0 to 5.5
32
4.0 to 5.5
32
2.7 to 5.5
40
Basic machine-language instructions ....................................... 71
•
•
Memory size
Power dissipation
(mW)
ROM ................................................................ 12 K to 48 K bytes
RAM ................................................................. 384 to 1024 bytes
Operating temperature
–20 to 85
–40 to 85
–20 to 85
Programmable input/output ports ............................................. 72
•
range
(°C)
Interrupts .................................................. 16 sources, 16 vectors
•
Timers ............................................................................. 8 bit ✕ 4
•
Serial I/O1 .................... 8-bit ✕ 1 (UART or Clock-synchronized)
•
Serial I/O2 ....................................8-bit ✕ 1 (Clock-synchronized)
APPLICATIONS
Office automation, VCRs, tuners, musical instruments, cameras,
•
A-D converter .................................................. 8-bit ✕ 8 channels
•
D-A converter .................................................. 8-bit ✕ 2 channels
air conditioners, etc.
•
PIN CONFIGURATION (TOP VIEW)
65
66
67
68
69
70
71
72
73
74
75
76
77
78
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P8
P8
P8
P8
P8
P8
7
6
5
4
3
2
P2
P2
P2
P2
P2
P2
P2
P2
0
1
2
3
4
5
6
7
/DB
/DB
/DB
/DB
/DB
/DB
/DB
/DB
0
1
2
3
4
5
6
7
P8
P8
1
0
V
CC
V
X
X
SS
M38063M6-XXXFP
V
REF
OUT
IN
AVSS
/AN
/AN
/AN
/AN
/AN3
P6
7
7
P4
P4
RESET
CNVSS
P42/INT0
0
P66
6
1
P6
P6
P6
5
5
4
4
79
80
3
Package type : 80P6N-A
80-pin plastic-molded QFP
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
P31
P30
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
40
39
38
37
P16/AD14
P17/AD15
P20/DB0
P21/DB1
P22/DB2
P23/DB3
P24/DB4
P25/DB5
P26/DB6
P27/DB7
Vss
P87
P86
P85
P84
P83
P82
P81
36
35
34
33
32
31
30
29
28
27
26
25
24
P80
VCC
VREF
M38063M6-XXXGP
M38063M6AXXXHP
XOUT
XIN
P40
P41
AVSS
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/AN3
P62/AN2
RESET
CNVSS
P42/INT0
P43/INT1
23
22
21
78
79
80
P61/AN1
P44/RXD
Package type : 80P6S-A/80P6D-A
80-pin plastic-molded QFP
2
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
Pin
Name
Function
Function except a port function
VCC
VSS
Power source
• Apply voltage of 3.0 V to 5.5 V to VCC, and 0 V to VSS.
(Extended operating temperature version : 4.0 V to 5.5 V)
(High-speed version : 2.7 V to 5.5 V)
CNVSS
CNVSS
• This pin controls the operation mode of the chip.
• Normally connected to VSS.
• If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed.
VREF
AVSS
Analog reference • Reference voltage input pin for A-D and D-A converters
voltage
Analog power
source
• GND input pin for A-D and D-A converters
• Connect to VSS.
______
RESET
Reset input
Clock input
• Reset input pin for active “L”
XIN
• Input and output signals for the internal clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
oscillation frequency.
XOUT
Clock output
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00 – P07
P10 – P17
P20 – P27
P30 – P37
P40, P41
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
• 8 bit CMOS I/O port
• I/O direction register allows each pin to be individually programmed as either input or output.
• At reset this port is set to input mode.
• In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
• CMOS compatible input level
• CMOS 3-state output structure
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P42/INT0,
P43/INT1
• CMOS 3-state output structure
• External interrupt input pin
P44/RXD,
P45/TXD,
• Serial I/O1 I/O pins
P46/SCLK1,
_____
P47/SRDY1
P50
I/O port P5
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
P51/INT2 –
P53/INT4
• CMOS 3-state output structure
• External interrupt input pin
P54/CNTR0,
P55/CNTR1
• Timer X and Timer Y I/O pins
• D-A conversion output pins
• A-D conversion input pins
P56/DA1,
P57/DA2
P60/AN0 –
P67/AN7
I/O port P6
• 8-bit CMOS I/O port with the same function as
port P0
• CMOS compatible input level
• CMOS 3-state output structure
4
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION (Continued)
Pin
Name
Function
Function except a port function
• Serial I/O2 I/O pins
P70/SIN2,
P71/SOUT2,
I/O port P7
• 8-bit I/O port with the same function as port P0
• CMOS compatible input level
P72/SCLK2,
• N-channel open-drain output structure
_____
P73/SRDY2
P74 – P77
P80 – P87
I/O port P8
• 8-bit CMOS I/O port with the same function as port P0
• CMOS compatible input level
• CMOS 3-state output structure
PART NUMBERING
Product
M3806 3 M 6 - XXX FP
Package type
FP : 80P6N-A package
GP : 80P6S-A package
FS : 80D0 package
ROM number
Omitted in some types.
Normally, using hyphen
When electrical characteristic, or division of quality
identification code using alphanumeric character
– : standard
D : Extended operating temperature version
A : High-speed version
ROM/PROM size
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M : Mask ROM version
E : EPROM or One Time PROM version
RAM size
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
0
1
2
3
4
5
6
7
5
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
(2) Packages
Mitsubishi plans to expand the 3806 group as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
80P6N-A............................. 0.8 mm-pitch plastic molded QFP
80P6S-A ........................... 0.65 mm-pitch plastic molded QFP
80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
ROM/PROM capacity ................................ 12 K to 48 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
Mass product
ROM size (bytes)
48K
M38067MC/EC
Mass product
M38067M8
32K
28K
Mass product
24K
20K
16K
12K
8K
M38063M6/E6
Mass product
Mass product
M38062M4
M38062M3
4K
192 256
384
512
RAM size (bytes)
640
768
896
1024
Products under development : the development schedule and specification may be revised without notice.
Currently supported products are listed below
As of May 1996
(P) ROM size (bytes)
ROM size for User in ( )
Product name
RAM size (bytes)
Package
Remarks
M38062M3-XXXFP
M38062M3-XXXGP
M38062M4-XXXFP
M38062M4-XXXGP
M38063M6-XXXFP
M38063E6-XXXFP
M38063E6FP
80P6N-A Mask ROM version
80P6S-A Mask ROM version
80P6N-A Mask ROM version
80P6S-A Mask ROM version
Mask ROM version
12288
(12158)
384
384
16384
(16254)
80P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
24576
(24446)
M38063M6-XXXGP
M38063E6-XXXGP
M38063E6GP
512
80P6S-A One Time PROM version
One Time PROM version (blank)
M38063E6FS
80D0
EPROM version
M38067M8-XXXFP
M38067M8-XXXGP
M38067MC-XXXFP
M38067EC-XXXFP
M38067ECFP
80P6N-A Mask ROM version
80P6S-A Mask ROM version
Mask ROM version
32768
(32638)
1024
1024
80P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
49152
(49022)
M38067MC-XXXGP
M38067EC-XXXGP
M38067ECGP
80P6S-A One Time PROM version
One Time PROM version (blank)
6
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
(2) Packages
(EXTENDED OPERATING TEMPERATURE VERSION)
Mitsubishi plans to expand the 3806 group (extended operating
temperature version) as follows:
80P6N-A............................. 0.8 mm-pitch plastic molded QFP
(1) Support for mask ROM version
ROM/PROM capacity ................................ 12 K to 48 K bytes
RAM capacity .............................................. 384 to 1024 bytes
Memory Expansion Plan
New product
M38067ECD
Mass product
M38067MCD
ROM size (bytes)
48K
Mass product
M38067M8D
32K
28K
Mass product
M38063M6D
24K
20K
16K
12K
8K
Mass product
Mass product
M38062M4D
M38062M3D
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Currently supported products are listed below.
As of May 1996
(P) ROM size (bytes)
Product name
RAM size (bytes)
Package
Remarks
ROM size for User in (
12288(12158)
16384(16254)
24576(24446)
32768(32638)
)
M38062M3DXXXFP
M38062M4DXXXFP
M38063M6DXXXFP
M38067M8DXXXFP
M38067MCDXXXFP
M38067ECDXXXFP
M38067ECDFP
384
384
Mask ROM version
Mask ROM version
Mask ROM version
512
1024
80P6N-A Mask ROM version
Mask ROM version
49152(49022)
1024
One Time PROM version
One Time PROM version (blank)
7
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
GROUP EXPANSION
(2) Packages
(HIGH-SPEED VERSION)
80P6N-A............................. 0.8 mm-pitch plastic molded QFP
80P6S-A ........................... 0.65 mm-pitch plastic molded QFP
80P6D-A............................. 0.5 mm-pitch plastic molded QFP
80D0 ................ 0.8 mm-pitch ceramic LCC (EPROM version)
Mitsubishi plans to expand the 3806 group (high-speed version)
as follows:
(1) Support for mask ROM, One Time PROM, and EPROM
versions
ROM/PROM capacity ................................ 24 K to 48 K bytes
RAM capacity .............................................. 512 to 1024 bytes
Memory Expansion Plan
New product
ROM size (bytes)
48K
M38067MCA/ECA
New product
M38067M8A
32K
28K
New product
24K
20K
16K
12K
8K
M38063M6A
4K
192 256
384
512
640
768
896
1024
RAM size (bytes)
Products under development: the development schedule and specification may be revised without notice.
Currently supported products are listed below.
As of May 1996
(P) ROM size (bytes)
Product name
RAM size (bytes)
Package
Remarks
ROM size for User in (
)
M38063M6AXXXFP
M38063M6AXXXGP
M38063M6AXXXHP
M38067M8AXXXFP
M38067M8AXXXGP
M38067MCAXXXFP
M38067ECAXXXFP
M38067ECAFP
80P6N-A Mask ROM version
80P6S-A Mask ROM version
80P6D-A Mask ROM version
80P6N-A Mask ROM version
80P6S-A Mask ROM version
Mask ROM version
24576
(24446)
512
32768
(32638)
1024
80P6N-A One Time PROM version
One Time PROM version (blank)
Mask ROM version
49152
(49022)
M38067MCAXXXGP
M38067ECAXXXGP
M38067ECAGP
1024
80P6S-A One Time PROM version
One Time PROM version (blank)
M38067ECAFS
80D0
EPROM version
8
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 3806 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine in-
structions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
CPU mode register
The CPU mode register is allocated at address 003B16.
The CPU mode register contains the stack page selection bit.
b7
b0
CPU mode register
(
CPUM : address 003B16)
Processor mode bits
b1 b0
0
0
1
1
0
1
0
1
: Single-chip mode
: Memory expansion mode
: Microprocessor mode
: Not available
Stack page selection bit
0
1
: 0 page
: 1 page
Not used (return “0” when read)
Fig. 1 Structure of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Memory
Zero page
Special function register (SFR) area
The Special Function Register area in the zero page contains con-
trol registers such as I/O ports and timers.
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
RAM
RAM is used for data storage and for stack area of subroutine
calls and interrupts.
Special page
ROM
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
RAM area
RAM capacity
(bytes)
Address
XXXX16
000016
SFR area
192
256
384
512
640
768
896
1024
00FF16
013F16
01BF16
023F16
02BF16
033F16
03BF16
043F16
Zero page
004016
010016
RAM
XXXX16
Reserved area
Not used
044016
ROM area
ROM capacity
(bytes)
Address
YYYY16
Address
ZZZZ16
YYYY16
Reserved ROM area
(128 bytes)
4096
8192
F00016
E00016
D00016
C00016
B00016
A00016
900016
800016
700016
600016
500016
400016
300016
200016
100016
F08016
E08016
D08016
C08016
B08016
A08016
908016
808016
708016
608016
508016
408016
308016
208016
108016
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
ZZZZ16
ROM
FF0016
FFDC16
Special page
Interrupt vector area
Reserved ROM area
FFFE16
FFFF16
Fig. 2 Memory map diagram
10
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Port P0 (P0)
Prescaler 12 (PRE12)
Timer 1 (T1)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Port P0 direction register (P0D)
Port P1 (P1)
Timer 2 (T2)
Port P1 direction register (P1D)
Port P2 (P2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Port P2 direction register (P2D)
Port P3 (P3)
Prescaler Y (PREY)
Timer Y (TY)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
AD/DA control register (ADCON)
A-D conversion register (AD)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
Interrupt control register 2(ICON2)
Serial I/O2 control register (SIO2CON)
Serial I/O2 register (SIO2)
Fig. 3 Memory map of special function register (SFR)
11
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
I/O Ports
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Direction registers
The 3806 group has 72 programmable I/O pins arranged in nine
I/O ports (ports P0 to P8). The I/O ports have direction registers
which determine the input/output direction of each individual pin.
Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
Pin
Name
Input/Output
I/O Format
CMOS 3-state output
CMOS compatible
input level
Non-Port Function
Related SFRs
Ref.No.
Input/output,
individual bits
Address low-order byte
output
P00 – P07
Port P0
CPU mode register
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Address high-order
byte output
P10 – P17
P20 – P27
P30 – P37
Port P1
Port P2
Port P3
CPU mode register
CPU mode register
CPU mode register
(1)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Data bus I/O
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Control signal I/O
P40,P41
P42/INT0,
P43/INT1
P44/RXD,
P45/TXD,
Interrupt edge selection
register
External interrupt input
Serial I/O1 function I/O
(2)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Port P4
(3)
(4)
(5)
(6)
(1)
Serial I/O1 control
register
P46/SCLK1,
_____
UART control register
P47/SRDY1
P50
P51/INT2,
P52/INT3,
P53/INT4
P54/CNTR0,
P55/CNTR1
P56/DA1,
P57/DA2
Interrupt edge selection
register
External interrupt input
(2)
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
Port P5
Timer X and Timer Y
function I/O
Timer XY mode register
AD/DA control register
(7)
(8)
D-A conversion output
CMOS 3-state output
CMOS compatible
input level
P60/AN0 –
P67/AN7
Input/output,
individual bits
Port P6
Port P7
Port P8
A-D conversion input
(9)
P70/SIN2,
(10)
(11)
(12)
(13)
(14)
P71/SOUT2,
N-channel open-drain output
CMOS compatible
input level
Serial I/O2 control
register
Input/output,
individual bits
Serial I/O2 function I/O
P72/SCLK2,
_____
P73/SRDY2
P74 – P77
CMOS 3-state output
CMOS compatible
input level
Input/output,
individual bits
P80 – P87
(1)
Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func-
tion I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
12
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Ports P0, P1, P2, P3, P40, P41, P50, P8
(2) Ports P42, P43, P51, P52, P53
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Interrupt input
(3) Port P44
(4) Port P45
Serial I/O1 enable bit
Receive enable bit
P45/TXD P-channel output disable bit
Serial I/O1 enable bit
Transmit enable bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O1 input
Serial I/O1output
(5) Port P46
(6) Port P47
Serial I/O1
synchronous clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Serial I/O1
external
Serial I/O1 clock output
Serial I/O1 ready output
clock input
(7) Ports P54, P55
(8) Ports P56, P57
Direction register
Direction register
Port latch
Port latch
Data bus
Data bus
Pulse output mode
Timer output
D-A conversion output
DA1 output enable bit (P56)
DA2 output enable bit (P57)
Counter input
Interrupt input
Fig. 4 Port block diagram (single-chip mode) (1)
13
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P6
(10) Port P70
Direction register
Port latch
Direction register
Port latch
Data bus
Data bus
A-D conversion input
Analog input pin selection bit
Serial I/O2 input
(11) Port P71
(12) Port P72
Serial I/O2
transmit completion signal
Serial I/O2
synchronous clock selection bit
Serial I/O2 port selection bit
Serial I/O2 port selection bit
Direction register
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O2
external
clock input
Serial I/O2 clock output
Serial I/O2 output
(13) Port P73
(14) Ports P74 – Port P77
Direction register
SRDY2 output enable bit
Direction register
Port latch
Data bus
Port latch
Data bus
Serial I/O2 ready output
Fig. 5 Port block diagram (single-chip mode) (2)
14
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
INTERRUPTS
Interrupt operation
Interrupts occur by sixteen sources: seven external, eight internal,
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
and one software.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Notes on use
When the active edge of an external interrupt (INT0 to INT4,
CNTR0, or CNTR1) is changed, the corresponding interrupt re-
quest bit may also be set. Therefore, please take following se-
quence;
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Table 1. Interrupt vector addresses and priority
Interrupt Request
Remarks
Vector Addresses (Note 1)
Interrupt Source
Reset (Note 2)
INT0
Priority
High
Low
Generating Conditions
1
2
FFFD16
FFFC16
At reset
Non-maskable
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
External interrupt
FFFB16
FFF916
FFF716
FFFA16
FFF816
FFF616
(active edge selectable)
External interrupt
INT1
3
4
(active edge selectable)
Serial I/O1
reception
Valid when serial I/O1 is selected
At completion of serial I/O1
transfer shift or when
Serial I/O1
5
FFF516
FFF416
Valid when serial I/O1 is selected
transmission
transmission buffer is empty
At timer X underflow
Timer X
Timer Y
Timer 1
Timer 2
6
7
8
9
FFF316
FFF116
FFEF16
FFED16
FFF216
FFF016
FFEE16
FFEC16
At timer Y underflow
At timer 1 underflow
STP release timer underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
External interrupt
CNTR0
CNTR1
Serial I/O2
INT2
10
11
12
13
14
FFEB16
FFE916
FFE716
FFE516
FFE316
FFEA16
FFE816
FFE616
FFE416
FFE216
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion
External interrupt
(active edge selectable)
External interrupt
INT3
(active edge selectable)
External interrupt
INT4
15
16
17
FFE116
FFDF16
FFDD16
FFE016
FFDE16
FFDC16
(active edge selectable)
A-D converter
BRK instruction
At BRK instruction execution
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
15
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
Fig. 6 Interrupt control
b7
b0
Interrupt edge selection register
(INTEDGE : address 003A16
)
INT
INT
0
active edge selection bit
active edge selection bit
1
Not used (returns “0” when read)
INT
INT
INT
2
3
4
active edge selection bit
active edge selection bit
active edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
b7
b0
b7 b0
Interrupt request register 2
(IREQ2 : address 003D16
Interrupt request register 1
)
(IREQ1 : address 003C16
)
INT
INT
0
interrupt request bit
interrupt request bit
CNTR
0
interrupt request bit
interrupt request bit
1
CNTR
1
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Serial I/O2 interrupt request bit
INT
INT
INT
2
3
4
interrupt request bit
interrupt request bit
interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
Timer 2 interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7
b0 Interrupt control register 1
(ICON1 : address 003E16
b7
b0
Interrupt control register 2
(ICON2 : address 003F16
)
)
CNTR
0
1
interrupt enable bit
interrupt enable bit
INT
INT
0
1
interrupt enable bit
interrupt enable bit
CNTR
Serial I/O2 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
INT
INT
INT
2
3
4
interrupt enable bit
interrupt enable bit
interrupt enable bit
Timer Y interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 7 Structure of interrupt-related registers
16
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Timers
Timer 1 and Timer 2
The 3806 group has four timers: timer X, timer Y, timer 1, and
The count source of prescaler 12 is the oscillation frequency di-
vided by 16. The output of prescaler 12 is counted by timer 1 and
timer 2, and a timer underflow sets the interrupt request bit.
timer 2.
All timers are count down. When the timer reaches “0016”, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Timer X and Timer Y
Timer X and Timer Y can each be selected in one of four operating
modes by setting the timer XY mode register.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
Timer Mode
The timer counts f(XIN)/16 in timer mode.
Pulse Output Mode
Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of
the timer reach “0016”, the signal output from the CNTR0 (or
CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge
switch bit is “0”, output begins at “ H”.
b7
b0
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
If it is “1”, output starts at “L”. When using a timer in this mode, set
the corresponding port P54 ( or port P55) direction register to out-
put mode.
CNTR0 active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except the timer counts signals input through the CNTR0 or
CNTR1 pin.
Timer X count stop bit
0: Count start
1: Count stop
Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer
counts at the oscillation frequency divided by 16 while the CNTR0
(or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge
switch bit is “1”, the count continues during the time that the
CNTR0 (or CNTR1) pin is at “L”.
Timer Y operating mode bit
b5b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge switch bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
In all of these modes, the count can be stopped by setting the
timer X (timer Y) count stop bit to “1”. Every time a timer
underflows, the corresponding interrupt request bit is set.
Timer Y count stop bit
0: Count start
1: Count stop
Fig. 8 Structure of timer XY register
17
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Data bus
Oscillator
f(XIN
Divider
1/16
Prescaler X latch (8)
Timer X latch (8)
)
Timer mode
Pulse output
mode
Pulse width
measurement
mode
Prescaler X (8)
Timer X (8)
To timer X interrupt
request bit
CNTR0 active
edge switch bit
P54/CNTR0 pin
Event
counter
mode
Timer X count stop bit
“0”
To CNTR
0 interrupt
request bit
“1”
CNTR0 active
edge switch
bit
Q
Q
“1”
“0”
Toggle flip- flop
R
T
Port P5
latch
4
Port P5
direction register
4
Timer X latch write pulse
Pulse output mode
Pulse output
mode
Data bus
Prescaler Y latch (8)
Timer Y latch (8)
Timer Y (8)
Timer mode
Pulse output
mode
Pulse width
measurement
mode
Prescaler Y (8)
To timer Y interrupt
request bit
CNTR1 active
edge switch bit
P55/CNTR1 pin
Event
counter
mode
Timer Y count stop bit
“0”
To CNTR
1 interrupt
request bit
“1”
CNTR1 active
edge switch
bit
Q
Q
“1”
“0”
Toggle flip- flop
R
T
Port P5
latch
5
Port P5
direction register
5
Timer Y latch write pulse
Pulse output mode
Pulse output
mode
Data bus
Prescaler
12 latch (8)
Timer 1 latch (8)
Timer 2 latch (8)
To timer 2 interrupt
request bit
Prescaler 12 (8)
Timer 1 (8)
Timer 2 (8)
To timer 1 interrupt
request bit
Fig. 9 Block diagram of timer X, timer Y, timer 1, and timer 2
18
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock synchronous serial I/O mode
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
Clock synchronous serial I/O1 mode can be selected by setting
the mode selection bit of the serial I/O1 control register to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB (address 001816).
Data bus
Serial I/O1 control register
Address 001A16
Address 001816
Receive buffer
Receive buffer full flag (RBF)
Receive shift register
Receive interrupt request (RI)
P44/RXD
Shift clock
Clock control circuit
P46/SCLK1
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
1/4
Clock control circuit
P47/SRDY1
Falling-edge detector
F/F
Shift clock
Transmit shift register
Transmit buffer
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P45/TXD
Transmit interrupt request (TI)
Transmit buffer empty flag (TBE)
Serial I/O1 status register
Address 001916
Address 001816
Data bus
Fig. 10 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
Receive enable signal SRDY1
Write pulse to receive/transmit
buffer (address 001816
)
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Overrun error (OE)
detection
Notes
1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is
output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 11 Operation of clock synchronous serial I/O1 function
19
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Asynchronous serial I/O (UART) mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O mode selection bit of the serial I/O control
register to “0”.
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the re-
ceive buffer.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next charac-
ter is being received.
Data bus
Address 001816
Serial I/O1 control register Address 001A16
Receive buffer
Character length selection bit
Receive buffer full flag (RBF)
Receive interrupt request (RI)
OE
P44/RXD
STdetector
7 bits
8 bits
Receive shift register
1/16
UART control register
PE FE SP detector
Address 001B16
Clock control circuit
Serial I/O1 synchronous clock selection bit
P46/SCLK1
Frequency division ratio 1/(n+1)
BRG count source selection bit
1/4
f(XIN
)
Baud rate generator
Address 001C16
ST/SP/PA generator
1/16
Transmit shift completion flag (TSC)
Transmit interrupt source selection bit
P4
5
/TX
D
Transmit shift register
Transmit interrupt request (TI)
Character length selection bit
Transmit buffer empty flag (TBE)
Transmit buffer
Address 001816
Address 001916
Serial I/O1 status register
Data bus
Fig. 12 Block diagram of UART serial I/O
20
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock
Transmit buffer write
signal
TBE=0
TSC=0
TBE=1
TBE=0
TSC=1✽
SP
TBE=1
Serial output TXD
ST
D0
D1
D0
D1
ST
SP
✽Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read
signal
RBF=0
RBF=1
SP
RBF=1
SP
ST
Serial input R
X
D
D0
D1
D1
ST
D0
1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
Notes
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 13 Operation of UART serial I/O function
Serial I/O1 control register (SIO1CON) 001A16
The serial I/O control register consists of eight control bits for the
serial I/O function.
spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of
the Serial I/O Control Register) also clears all the status flags, in-
cluding the error flags.
All bits of the serial I/O1 status register are initialized to “0” at re-
set, but if the transmit enable bit (bit 4) of the serial I/O control reg-
ister has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
UART control register (UARTCON) 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer. One bit in this register (bit 4) is
always valid and sets the output structure of the P45/TXD pin.
Transmit buffer/Receive buffer register (TB/
RB) 001816
Serial I/O1 status register (SIO1STS) 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O
function and various errors.
The transmit buffer and the receive buffer are located at the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer is read.
Baud rate generator (BRG) 001C16
The baud rate generator determines the baud rate for serial trans-
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer, and
the receive buffer full flag is set. A write to the serial I/O status reg-
ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re-
fer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate genera-
tor.
21
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7
b0
b0
b7
Serial I/O1 status register
Serial I/O1 control register
(SIO1STS : address 0019 16
)
(SIO1CON : address 001A 16
BRG count source selection bit (CSS)
0: f(XIN
)
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
S
0: P4
1: P4
RDY1 output enable bit (SRDY)
Overrun error flag (OE)
0: No error
1: Overrun error
7
pin operates as ordinaly I/O pin
pin operates as SRDY1 output pin
7
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Parity error flag (PE)
0: No error
1: Parity error
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Framing error flag (FE)
0: No error
1: Framing error
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Not used (returns "1" when read)
b0
b7
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
UART control register
(UARTCON : address 001B 16
)
(pins P4
1: Serial I/O enabled
(pins P4 to P4 operate as serial I/O pins)
4 to P47 operate as ordinary I/O pins)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
4
7
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return "1" when read)
Fig. 14 Structure of serial I/O control registers
22
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O2
b7
b0
Serial I/O2 control register
(SIO2CON : address 001D16
The serial I/O2 function can be used only for clock synchronous
)
serial I/O.
Internal synchronous clock selection bits
For clock synchronous serial I/O the transmitter and the receiver
must use the same clock. If the internal clock is used, transfer is
started by a write signal to the serial I/O2 register.
b2 b1 b0
0 0 0: f(XIN)/8
0 0 1: f(XIN)/16
0 1 0: f(XIN)/32
0 1 1: f(XIN)/64
1 1 0: f(XIN)/128
1 1 1: f(XIN)/256
Serial I/O2 control register (SIO2CON) 001D16
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
Serial I/O2 port selection bit
0: I/O port
1: SOUT2,SCLK2 signal output
S
RDY2 output enable bit
0: I/O port
1: SRDY2 signal output
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
Not used (returns “0” when read)
Fig. 15 Structure of serial I/O2 control register
Internal synchronous
clock selection bits
1/8
1/16
Data bus
1/32
X
IN
1/64
1/128
1/256
P73 latch
"0"
Serial I/O2 synchronous
clock selection bit
"1"
P7
3
/SRDY2
SRDY2
Synchronization circuit
"1"
SRDY2 output enable bit
"0"
External clock
P72 latch
"0"
P7
P7
2
1
/SCLK2
/SOUT2
Serial I/O2
interrupt request
Serial I/O counter 2 (3)
"1"
Serial I/O2 port selection bit
P71 latch
"0"
"1"
Serial I/O2 port selection bit
Serial I/O shift register 2 (8)
P70/SIN2
Fig. 16 Block diagram of serial I/O2 function
23
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transfer clock (Note 1)
Serial I/O2 register
write signal
(Note 2)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
D2
D0
D1
D3
D4
D5
D6
D7
Receive enable signal SRDY2
Serial I/O2 interrupt request bit set
Notes 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial
I/O2 control register.
2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion.
Fig. 17 Timing of serial I/O2 function
24
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A-D Converter
[Comparator and Control circuit]
The functional blocks of the A-D converter are described below.
The comparator and control circuit compares an analog input volt-
age with the comparison voltage, then stores the result in the A-D
conversion register. When an A-D conversion is complete, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”.
[A-D conversion register]
The A-D conversion register is a read-only register that stores the
result of an A-D conversion. When reading this register during an
A-D conversion, the previous conversion result is read.
Note that the comparator is constructed linked to a capacitor, so
set f(XIN) to 500 kHz or more during an A-D conversion.
[AD/DA control register]
The AD/DA control register controls the A-D conversion process.
Bits 0 to 2 select a specific analog input pin. Bit 3 signals the
completion of an A-D conversion. The value of this bit remains at
“0” during an A-D conversion, and changes to “1” when an A-D
conversion ends. Writing “0” to this bit starts the A-D conversion.
Bits 6 and 7 are used to control the output of the D-A converter.
b7
b0
AD/DA control register
(ADCON : address 003416
)
Analog input pin selection bits
b2 b1 b0
0 0 0: P6
0 0 1: P6
0 1 0: P6
0 1 1: P6
1 0 0: P6
1 0 1: P6
1 1 0: P6
1 1 1: P6
0
1
2
3
4
5
6
7
/AN
/AN
/AN
/AN
/AN
/AN
/AN
/AN
0
1
2
3
4
5
6
7
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF into 256, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of the ports P60/AN0 to P67/AN7,
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
and inputs the voltage to the comparator.
Not used (return "0" When read)
DA1 output enable bit
0: DA
1: DA
1
output disabled
output enabled
1
DA2 output enable bit
0: DA
1: DA
2
output disabled
output enabled
2
Fig.18 Structure of AD/DA control register
Data bus
b7
3
b0
AD/DA control register
(Address 003416)
A-D control circuit
A-D interrupt request
P60/AN0
P61/AN1
P62/AN2
P63/AN3
P64/AN4
P65/AN5
P66/AN6
P67/AN7
Comparator
A-D conversion register (Address 003516)
8
Resistor ladder
VREF AVSS
Fig. 19 Block diagram of A-D converter
25
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A Converter
The 3806 group has two internal D-A converters (DA1 and DA2)
with 8-bit resolutions.
The D-A converter is performed by setting the value in the D-A
conversion register. The result of D-A converter is output from the
DA1 or DA2 pin by setting the DA output enable bit to “1”.
When using the D-A converter, the corresponding port direction
register bit (DA1/P56 or DA2/P57) should be set to “0” (input sta-
tus).
D-A1 conversion register (8)
DA1 output enable bit
The output analog voltage V is determined by the value n (base
10) in the D-A conversion register as follows:
R-2R resistor ladder
P56/DA1
V = VREF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
D-A2 conversion register (8)
At reset, the D-A conversion registers are cleared to “0016”, the DA
output enable bits are cleared to “0”, and the P56/DA1 and P57/
DA2 pins are set to input (high impedance).
DA2 output enable bit
P57/DA2
R-2R resistor ladder
The D-A output is not buffered, so connect an external buffer when
driving a low-impedance load.
Set VCC to 4.0 V or more when using the D-A converter.
Fig. 20 Block diagram of D-A converter
DA
1
output enable bit
R
"0"
R
R
2R
R
R
R
R
P5 /DA1
6
"1"
2R
2R
2R
2R
2R
2R
2R
2R
LSB
MSB
"0"
D-A1 conversion
register
"1"
AVSS
VREF
Fig. 21 Equivalent connection circuit of D-A converter
26
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Reset Circuit
______
To reset the microcomputer, the RESET pin should be held at an
Address
Register contents
0016
______
“L” level for 2 µs or more. Then the RESET pin is returned to an
“H” level (Note 1), reset is released. Internal operation does not
begin until after 8 to 13 XIN clock cycles are completed. After the
reset is completed, the program starts from the address contained
in address FFFD16 (high-order byte) and address FFFC16 (low-or-
der byte).
(000116) • • •
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
(000316) • • •
(000516) • • •
(000716) • • •
(000916) • • •
(000B16) • • •
(000D16) • • •
(000F16) • • •
(001116) • • •
(001916) • • •
(001A16) • • •
(001B16) • • •
(001D16) • • •
(002016) • • •
(002116) • • •
(002216) • • •
(002316) • • •
(002416) • • •
(002516) • • •
(002616) • • •
(002716) • • •
(003416) • • •
(003616) • • •
(003716) • • •
0016
0016
0016
0016
0016
0016
0016
0016
Make sure that the reset input voltage is less than 0.8 V for VCC of
4.0 V (Note 2).
Note 1. The power source voltage should be between the follow-
ing voltage.
(8) Port P7 direction register
• Between 3.0 V and 5.5 V for standard version
• Between 4.0 V and 5.5 V for extended operating tem-
perature version
(9)
Port P8 direction register
Serial I/O1 status register
Serial I/O1 control register
UART control register
(10)
(11)
(12)
(13)
1
1
0
1
0
1
0
0
0
0
0
0
0
0
• Between 2.7 V and 5.5 V for high-speed version
Note 2. Reset input voltage is less than the following voltage.
• 0.6 V for VCC = 3.0 V
0016
0
0
Serial I/O2 control register
• 0.8 V for VCC = 4.0 V
0016
FF16
0116
FF16
0016
FF16
FF16
FF16
FF16
• 0.54 V for VCC = 2.7 V
(14) Prescaler 12
(15)
(16)
(17)
(18)
(19)
Timer 1
Timer 2
Timer XY mode register
Prescaler X
Timer X
4.0V
Power source
0V
voltage
(20) Prescaler Y
(21)
(22)
Timer Y
0.8V
Reset input
voltage
0V
AD/DA control register
0
0
0
0
0
0
0
1
0
0
0
0
0
(23) D-A1 conversion register
0016
0016
0016
(24)
(25)
D-A2 conversion register
Interrupt edge selection register (003A16) • • •
VCC
1
5
4
(26) CPU mode register
Interrupt request register 1
(003B16) • • •
(003C16) • • •
(003D16) • • •
(003E16) • • •
(003F16) • • •
(PS)
0
0
✽
RESET
M51953AL
3
(27)
0016
0016
0016
0016
(28) Interrupt request register 2
(29) Interrupt control register 1
0.1 µ F
VSS
(30)
Interrupt control register 2
3806 group
(31)
Processor status register
✕
✕
✕
✕
✕
✕
✕
1
(32) Program counter
(PC
H
) Contents of address FFFD16
) Contents of address FFFC16
Fig. 22 Example of reset circuit
(PC
L
Note.
✕ : Undefined
✽ : The initial values of CM1 are determined by the level at the
CNVSS pin.
The contents of all other registers and RAM are undefined
after a reset, so they must be initialized by software.
Fig. 23 Internal status of microcomputer after reset
27
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
X
IN
φ
RESET
RESETOUT
(internal reset)
SYNC
Address
?
?
ADH, ADL
?
?
?
FFFC
FFFD
Reset address from the vector table
ADH
Data
?
?
?
?
ADL
?
Notes 1: f(XIN) and f(φ) are in the relationship: f(XIN)=2
• f(φ).
X
IN: 8 to 13 clock cycles
2: A question mark (?) indicates an undefined status that depends on the previous status.
Fig. 24 Timing of reset
28
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock Generating Circuit
When the STP status is released, prescaler 12 and timer 1 will
start counting and reset will not be released until timer 1
underflows, so set the timer 1 interrupt enable bit to “0” before the
STP instruction is executed.
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT. To supply a clock signal externally, input it to
the XIN pin and make the XOUT pin open.
Oscillation control
Stop Mode
If the STP instruction is executed, the internal clock φ stops at an
“H”. Timer 1 is set to “0116” and prescaler 12 is set to “FF16”.
Oscillator restarts when an external interrupt is received, but the
internal clock φ remains at an “H” until timer 1 underflow.
This allows time for the clock circuit oscillation to stabilize.
X
IN
XOUT
If oscillator is restarted by a reset, no wait time is generated, so
______
keep the RESET pin at an “L” level until oscillation has stabilized.
Wait Mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator itself does not stop. The internal clock
restarts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
C
IN
COUT
Fig. 25 Ceramic resonator circuit
To ensure that interrupts will be received to release the STP or
WIT state, interrupt enable bits must be set to “1” before the STP
or WIT instruction is executed.
X
IN
XOUT
Open
Vcc
Vss
External oscillation
circuit
Fig. 26 External clock input circuit
Interrupt request
Interrupt disable
Reset
S
R
Q
S
R
Q
Q
S
R
flag (I)
Reset
WIT
instruction
STP instruction
STP instruction
φ output
Internal clock φ
ONW pin
Single-chip mode
ONW
control
1/2
Rd
1/8
Prescaler 12
Timer 1
FF16
0116
Reset or STP instruction
Rf
X
IN
XOUT
Fig. 27 Block diagram of clock generating circuit
29
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Processor Modes
Single-chip mode, memory expansion mode, and microprocessor
mode can be selected by changing the contents of the processor
mode bits CM0 and CM1 (bits 0 and 1 of address 003B16). In
memory expansion mode and microprocessor mode, memory can
be expanded externally through ports P0 to P3. In these modes,
ports P0 to P3 lose their I/O port functions and become bus pins.
000016
000816
000016
000816
SFR area
SFR area
004016
004016
Internal RAM
reserved area
Internal RAM
reserved area
044016
044016
Table 2. Functions of ports in memory expansion mode and
microprocessor mode
✽
Port Name
Port P0
Function
YYYY16
Outputs low-order byte of address.
Outputs high-order byte of address.
Operates as I/O pins for data D7 to D0
(including instruction codes).
Internal ROM
Port P1
FFFF16
FFFF16
Memory expansion mode
Microprocessor mode
Port P2
P30 and P31 function only as output pins
The shaded areas are external memory areas.
YYYY16 is the start address of internal ROM.
✽
(except that the port latch cannot be read).
_____
:
P32 is the ONW input pin.
_________
P33 is the RESETOUT output pin. (Note)
Fig. 28 Memory maps in various processor modes
Port P3
P34 is the φ output pin.
P35 is the SYNC output pin.
___
P36 is the WR output pin, and P37 is the
___
RD output pin.
b7
b0
Note: If CNVSS is connected to VSS, the microcomputer goes to
CPU mode register
(CPUM : address 003B16
single-chip mode after a reset, so this pin cannot be used
as the RESETOUT output pin.
)
_________
Processor mode bits
b1 b0
Single-Chip Mode
0 0 : Single-chip mode
Select this mode by resetting the microcomputer with CNVSS con-
nected to VSS.
0 1 : Memory expansion mode
1 0 : Microprocessor mode
1 1 : Not available
Memory Expansion Mode
Stack page selection bit
0 : 0 page
1 : 1 page
Select this mode by setting the processor mode bits to “01” in soft-
ware with CNVSS connected to VSS. This mode enables external
memory expansion while maintaining the validity of the internal
ROM. Internal ROM will take precedence over external memory if
addresses conflict.
Not used (return “0” when read)
Fig. 29 Structure of CPU mode register
Microprocessor Mode
Select this mode by resetting the microcomputer with CNVSS con-
nected to VCC, or by setting the processor mode bits to “10” in
software with CNVSS connected to VSS. In microprocessor mode,
the internal ROM is no longer valid and external memory must be
used.
30
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Bus control with memory expansion
_____
The 3806 group has a built-in ONW function to facilitate access to
external memory and I/O devices in memory expansion mode or
microprocessor mode.
_____
If an “L” level signal is input to the ONW pin when the CPU is in a
read or write state, the corresponding read or write cycle is ex-
___
tended by one cycle of φ. During this extended period, the RD or
___
WR signal remains at “L”. This extension period is valid only for
writing to and reading from addresses 000016 to 000716 and
044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in
memory expansion mode, and only read and write cycles are ex-
tended.
Dummy cycle
Read cycle Dummy cycle
Read cycle
Write cycle
Write cycle
φ
AD15 to AD
0
RD
WR
ONW
✽
✽
✽
✽ :
Period during which ONW input signal is received
During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW
signal has no affect on operations.
The bus cycles is not extended for an address in the area 000816 to 043F16, regardless of whether the ONW signal
is received.
_____
Fig. 30 ONW function timing
31
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
NOTES ON PROGRAMMING
Serial I/O
Processor Status Register
In clock synchronous serial I/O, if the receive side is using an ex-
_____
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1”. Af-
ter a reset, initialize flags which affect program execution.
In particular, it is essential to initialize the index X mode (T) and
the decimal mode (D) flags because of their effect on calculations.
ternal clock and it is to output the SRDY1 signal, set the transmit
_____
enable bit, the receive enable bit, and the SRDY1 output enable bit
to “1”.
Serial I/O1 continues to output the final bit from the TXD pin after
transmission is completed. The SOUT2 pin from serial I/O2 goes to
high impedance after transmission is completed.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt re-
quest register, execute at least one instruction before executing a
BBC or BBS instruction.
A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is at least 500 kHz during an A-D conver-
____
sion. (If the ONW pin has been set to “L”, the A-D conversion will
take twice as long to match the longer bus cycle, and so f(XIN)
must be at least 1 MHz.)
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1”, then execute an ADC or SBC instruction. Only the ADC and
SBC instructions yield proper decimal results. After executing an
ADC or SBC instruction, execute at least one instruction before
executing a SEC, CLC, or CLD instruction.
Do not execute the STP or WIT instruction during an A-D conver-
sion.
D-A Converter
The accuracy of the D-A converter becomes poor rapidly under
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
the VCC = 4.0 V or less condition.
The carry flag can be used to indicate whether a carry or borrow
has occurred. Initialize the carry flag before each calculation.
Clear the carry flag before an ADC and set the flag before an
SBC.
Instruction Execution Time
The instruction execution time is obtained by multiplying the fre-
quency of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
The frequency of the internal clock φ is half of the XIN frequency.
_____
quency division ratio is 1/(n + 1).
When the ONW function is used in modes other than single-chip
mode, the frequency of the internal clock φ may be one fourth the
XIN frequency.
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
Memory Expansion Mode and Microproces-
sor Mode
Execute the LDM or STA instruction for writing to port P3 (address
000616) in memory expansion mode and microprocessor mode.
Set areas which can be read out and write to port P3 (address
000616) in a memory, using the read-modify-write instruction
(SEB, CLB).
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis-
ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a
direction register
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
32
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version and built-
in EPROM version can be read or programmed with a general-
purpose PROM programmer using a special programming
adapter. Set the address of PROM programmer in the user ROM
area.
1. Mask ROM Order Confirmation Form
2. Mark Specification Form
3. Data to be written to ROM, in EPROM form (three identical
copies)
Package
80P6N-A
80P6S-A
80D0
Name of Programming Adapter
PCA4738F-80A
PCA4738G-80A
PCA4738L-80A
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 40 is recommended to verify programming.
Programming with PROM
programmer
Screening (Caution)
(150°C for 40 hours)
Verification with
PROM programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution :
Fig. 31 Programming and testing of One Time PROM version
33
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Parameter
Power source voltage
Symbol
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VI
–0.3 to VCC +0.3
V
P60–P67, P70–P77, P80–P87,
VREF
______
All voltages are based on VSS.
Output transistors are cut off.
VI
VI
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to VCC +0.3
–0.3 to 13
V
V
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
XOUT
VO
–0.3 to VCC +0.3
V
Pd
Power dissipation
Ta = 25 °C
500
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
RECOMMENDED OPERATING CONDITIONS (Vcc=3.0 to 5.5v, Ta=-20 to 85°C,unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
3.0
Typ.
5.0
5.0
0
Max.
5.5
Power source voltage (f(XIN) < 2 MHz) (Note 1)
Power source voltage (f(XIN) = 8 MHz) (Note 1)
Power source voltage
VCC
V
V
V
4.0
5.5
VSS
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
2.0
3.0
VCC
VCC
VREF
AVSS
VIA
0
V
V
Analog input voltage
“H” input voltage
AN0–AN7
AVSS
0.8 VCC
0.8 VCC
0
VCC
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
VIH
VIH
VIL
V
V
P50–P57, P60–P67, P70–P77, P80–P87
______
“H” input voltage
“L” input voltage
RESET, XIN, CNVSS
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
0.2 VCC
V
P50–P57, P60–P67, P70–P77, P80–P87
______
VIL
“L” input voltage
RESET
XIN
0
0
0
0.2 VCC
0.16 VCC
0.2 VCC
–80
V
VIL
“L” input voltage
V
VIL
“L” input voltage
CNVSS
V
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47,P50–P57, P60–P67 (Note 2)
P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
–P8
7
7
(Note 2)
(Note 2)
mA
mA
mA
mA
mA
mA
mA
mA
–80
0
7
0
7
0
7
0
7
80
P40–P47,P50–P57, P60–P67, P70–P77 (Note 2)
80
“H” total average output current P0
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 2)
“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
7
7
(Note 2)
–40
–40
0
7
0
7
0
7
0
7
–P8
(Note 2)
40
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 2)
40
“H” peak output current
“L” peak output current
“H” average output current
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
–10
10
–5
5
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 4)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 4)
Internal clock oscillation frequency (VCC = 4.0 to 5.5 V)
Internal clock oscillation frequency (VCC = 3.0 to 4.0 V)
X+16
8
f(XIN)
MHz
6 VCC–16
Note 1: The minimum power source voltage is
[V] (f(XIN) = XMHz) on the condition of 2 MHz < f(XIN) < 8 MHz.
6
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
3: The peak output current is the peak current flowing in each port.
4: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
34
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
ELECTRICAL CHARACTERISTICS
Limits
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
V
Min.
Typ.
Max.
“H” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P8
0
0
0
–P1
–P4
–P8
7
7
7
, P2
, P5
(Note 1)
0
0
–P2
–P5
7
7
,
,
V
V
CC–2.0
P3
P6
VCC = 4.0 to 5.5 V
VOH
IOH = –1.0 mA
VCC = 3.0 to 5.5 V
CC–1.0
“L” output voltage P0
0–P0
0–P3
0–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7
7
7
, P2
0
–P2
–P5
–P8
7
,
IOL = 10 mA
VCC = 4.0 to 5.5 V
2.0
1.0
P3
P6
,P5
0
7
,
VOL
V
, P8
0
7
IOL = 1.0 mA
VCC = 3.0 to 5.5 V
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
0
, CNTR
1
, INT
0
–INT
4
0.4
0.5
0.5
V
V
V
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
RESET
Hysteresis
“H” input current
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIH
5.0
5.0
µA
VI = VCC
______
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
µA
µA
VI = VCC
VI = VCC
X
IN
4
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIL
–5.0
–5.0
µA
VI = VSS
______
IIL
“L” input current
“L” input current
RAM hold voltage
RESET, CNVSS
µA
µA
V
VI = VSS
IIL
X
IN
–4
VI = VSS
VRAM
2.0
5.5
13
8
When clock stopped
f(XIN) = 8 MHz, VCC = 5 V
f(XIN) = 5 MHz, VCC = 5 V
6.4
4
0.8
2.0
f(XIN) = 2 MHz, VCC = 3 V
When WIT instruction is executed with
f(Xin) = 8MHz,Vcc=5V
When WIT instruction is executed with
1.5
1
mA
ICC
Power source current
f(Xin) = 5MHz,Vcc=5V
When WIT instruction is executed
0.2
0.1
with f(Xin) = 2MHz,Vcc=3V
When STP instruction
Ta = 25 °C
1
is executed with clock (Note 2)
µA
stopped, output
transistors isolated.
(Note 2)
Ta = 85 °C
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
A-D CONVERTER CHARACTERISTICS
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, T
a
= –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
Max.
8
Typ.
—
—
Resolution
Bits
LSB
tC(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER Ladder resistor
35
VREF = 5.0 V
50
IVREF
II(AD)
Reference power source input current (Note)
A-D port input current
150
0.5
200
5.0
µA
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
35
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER CHARACTERISTICS
(VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Bits
%
Min.
Typ.
Max.
8
—
—
Resolution
V
CC = 4.0 to 5.5 V
CC = 3.0 to 4.0 V
1.0
2.5
3
Absolute accuracy
V
tsu
Setting time
µs
kΩ
mA
RO
Output resistor
1
2.5
4
IVREF
Reference power source input current (Note)
3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-
rents flowing through the A-D resistance ladder.
36
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
2
Max.
_____
tw(RESET)
Reset input “L” pulse width
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(XIN)
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
125
50
twH(XIN)
twL(XIN)
50
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
200
80
80
80
80
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
800
1000
370
400
370
400
220
200
100
200
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
TIMING REQUIREMENTS 2 (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Unit
Min.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
500/
(3 VCC–8)
tc(XIN)
External clock input cycle time
ns
200/
(3 VCC–8)
twH(XIN)
twL(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
ns
ns
200/
(3 VCC–8)
tc(CNTR)
twH(CNTR)
twH(INT)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twL(CNTR)
twL(INT)
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note : When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
37
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Typ.
Symbol
Parameter
Test conditions
Unit
Min.
Max.
140
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 32
X
D)
–30
tr(SCLK1)
tf(SCLK1)
30
30
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
)
)
/2–160
t
c(SCLK2
/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 33
Fig. 32
200
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
40
30
30
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
350
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 32
X
D)
–30
tr(SCLK1)
tf(SCLK1)
50
50
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
)
)
/2–240
t
c(SCLK2
/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 33
Fig. 32
400
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
50
50
50
20
20
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT and P70–P77 are excluded.
38
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
–20
–20
60
Typ.
Max.
_____
____
tsu(ONW–φ)
____
th(φ–ONW)
ns
ns
ns
ns
Before φ ONW input set up time
_____
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
0
After φ data bus hold time
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
tsu(ONW–WR)
__ ____
–20
–20
ns
ns
Before WR ONW input set up time
___ _____
th(RD–ONW)
After RD ONW input hold time
___ _____
___ ____
th(WR–ONW)
__
After WR ONW input hold time
___
tsu(DB–RD)
__
th(RD–DB)
65
0
ns
ns
Before RD data bus set up time
___
After RD data bus hold time
SWITCHING CHARACTERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
20
10
25
10
20
10
10
5
40
45
6
6
tv(φ–SYNC)
___
td(φ–WR)
___
SYNC valid time
___
___
RD and WR delay time
___ ___
20
10
70
tv(φ–WR)
RD and WR valid time
3
td(φ–DB)
tv(φ–DB)
__
After φ data bus delay time
After φ data bus valid time
20
15
___
___
Fig. 32
RD pulse width, WR pulse width
___ ___
tc(XIN)–10
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
td(AH–RD)
td(AH–WR)
__
td(AL–RD)
3tc(XIN)–10
ns
ns
ns
ns
ns
(When one-wait is valid)
___
After AD15–AD8 RD delay time
___
___
tc(XIN)–35
t
t
c(XIN
c(XIN
)
)
–15
–20
After AD15–AD8 WR delay time
___
After AD7–AD0 RD delay time
___
___
tc(XIN)–40
td(AL–WR)
__
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
0
0
5
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
5
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
After WR data bus delay time
___
15
65
ns
ns
ns
ns
___
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
200
200
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
__________
Note 1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
39
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Parameter
Unit
Symbol
____
Min.
–20
–20
180
0
Typ.
Max.
_____
ns
ns
ns
ns
tsu(ONW–φ)
Before φ ONW input set up time
_____
____
th(φ–ONW)
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
ns
ns
____ ___
tsu(ONW–WR)
__ ____
–20
–20
Before WR ONW input set up time
___ _____
th(RD–ONW)
After RD ONW input hold time
___ _____
___ ____
th(WR–ONW)
__
After WR ONW input hold time
___
ns
ns
tsu(DB–RD)
__
th(RD–DB)
Before RD data bus set up time
___
185
0
After RD data bus hold time
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Test conditions
Unit
Parameter
φ clock cycle time
Symbol
Typ.
Max.
Min.
tc(φ)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2tc(XIN)
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–20
tc(XIN)–20
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
150
150
10
10
15
15
40
20
15
7
tv(φ–SYNC)
___
td(φ–WR)
___
SYNC valid time
___
___
25
15
RD and WR delay time
___ ___
tv(φ–WR)
3
RD and WR valid time
td(φ–DB)
tv(φ–DB)
__
200
After φ data bus delay time
After φ data bus valid time
15
___
___
Fig. 32
tc(XIN)–20
RD pulse width, WR pulse width
___
___
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
3tc(XIN)–20
ns
ns
(when one-wait is valid)
___
td(AH–RD)
After AD15–AD8 _R_D_delay time
___
tc(XIN)–145
td(AH–WR)
__
After AD15–AD8 WR delay time
___
td(AL–RD)
td(AL–WR)
__
After AD7–AD0 _R_D_delay time
___
ns
ns
tc(XIN)–145
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
5
5
10
10
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
ns
ns
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
195
After WR data bus delay time
___
___
tv(WR–DB)
___ _____
10
0
After WR data bus valid time
_________
ns
ns
ns
td(RESET–RESETOUT)
RESETOUT output delay time (Note 1)
_________
300
300
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
__________
Note1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
40
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS (Extended operating temperature version)
Symbol
Parameter
Power source voltage
Conditions
Ratings
Unit
V
VCC
–0.3 to 7.0
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VI
–0.3 to VCC +0.3
V
P60–P67, P70–P77, P80–P87,
VREF
______
All voltage are based on VSS.
Output transistors are cut off.
VI
VI
Input voltage RESET, XIN
Input voltage CNVSS
–0.3 to VCC +0.3
–0.3 to 13
V
V
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
XOUT
VO
–0.3 to VCC +0.3
V
Pd
Power dissipation
Ta = 25 °C
500
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
–40 to 85
–65 to 150
°C
RECOMMENDED OPERATING CONDITIONS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
4.0
Typ.
5.0
0
Max.
5.5
VCC
Power source voltage
Power source voltage
V
V
VSS
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
2.0
4.0
VCC
VCC
V
VREF
AVSS
VIA
0
V
V
Analog input voltage
“H” input voltage
AN0–AN7
AVSS
0.8 VCC
0.8 VCC
0
VCC
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
VIH
VIH
VIL
V
V
V
P50–P57, P60–P67, P70–P77, P80–P87
______
“H” input voltage
“L” input voltage
RESET, XIN, CNVSS
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
0.2 VCC
P50–P57, P60–P67, P70–P77, P80–P87
______
VIL
“L” input voltage
RESET, CNVSS
XIN
0
0
0.2 VCC
0.16 VCC
–80
V
VIL
“L” input voltage
V
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
P0
P40–P47,P50–P57, P60–P67 (Note 1)
P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
–P8
7
7
(Note 1)
(Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
–80
0
7
0
7
0
7
0
7
80
P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
80
“H” total average output current P0
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
–P8
7
7
(Note 1)
(Note 1)
–40
–40
0
7
0
7
0
7
0
7
40
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
40
“H” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
IOH(peak)
IOL(peak)
IOH(avg)
–10
10
mA
mA
mA
“L” peak output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
“H” average output current
“L” average output current
Internal clock oscillation frequency
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
–5
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
IOL(avg)
f(XIN)
5
8
mA
MHz
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
S
p
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
41
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V,
VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
V
Min.
Typ.
Max.
“H” output voltage P0
0
0
0
–P0
–P3
–P6
7, P1
7, P4
7, P8
0
0
0
–P1
–P4
–P8
7
7
7
, P2
, P5
0
–P2
–P5
7
7
,
,
VOH
P3
P6
0
IOH = –10 mA
VCC–2.0
(Note 1)
, P2 –P2
–P5
–P8
“L” output voltage P0
0
0
0
–P0
–P3
–P6
7, P1
7, P4
7, P7
0–P1
0–P4
0–P7
7
7
7
0
7
,
VOL
P3
P6
,P5
0
7
,
7
IOL = 10 mA
2.0
V
, P8
0
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
0
, CNTR
1
, INT
0
–INT
4
0.4
0.5
0.5
V
V
V
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
RESET
Hysteresis
“H” input current
P0
P3
P6
0
0
0
–P0
–P3
–P6
7, P1
7, P4
7, P7
0–P1
0–P4
0–P7
7
7
7
, P2
, P5
, P8
0–P2
0–P5
0–P8
7
7
7
,
,
IIH
VI = VCC
5.0
5.0
µA
______
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
X
IN
4
P0
P3
P6
0
0
0
–P0
–P3
–P6
7, P1
7, P4
7, P7
0–P1
0–P4
0–P7
7
7
7
, P2
, P5
, P8
0–P2
0–P5
0–P8
7
7
7
,
,
IIL
VI = VSS
–5.0
–5.0
µA
______
IIL
“L” input current
“L” input current
RAM hold voltage
RESET, CNVSS
VI = VSS
µA
µA
V
IIL
X
IN
VI = VSS
–4
VRAM
When clock stopped
f(XIN) = 8 MHz
f(XIN) = 5 MHz
2.0
5.5
13
8
6.4
4
When WIT instruction is executed
with f(XIN) = 8 MHz
mA
1.5
1
When WIT instruction is executed
with f(XIN) = 5 MHz
ICC
Power source current
When STP instruction
is executed with clock (Note 2)
Ta = 25 °C
0.1
1
µA
stopped, output
transistors isolated.
(Note 2)
Ta = 85 °C
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
A-D CONVERTER CHARACTERISTICS(Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, T
a
= –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
LSB
tC(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER
IVREF
Ladder resistor
35
150
0.5
Reference power source input current (Note)
A-D port input current
VREF = 5.0 V
50
200
5.0
µA
II(AD)
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
42
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER CHARACTERISTICS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC, T
a
= –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
%
Absolute accuracy
Setting time
1.0
3
tsu
µs
RO
Output resistor
1
2.5
4
kΩ
mA
IVREF
Reference power source input current (Note)
3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-
rents flowing through the A-D resistance ladder.
43
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(XIN)
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
125
50
twH(XIN)
twL(XIN)
50
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
200
80
80
80
80
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
800
1000
370
400
370
400
220
200
100
200
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When bit 6 of address 001A16 is “1”. Divide this value by four when bit 6 of address 001A16 is “0”.
SWITCHING CHARACTERISTICS (Extended operating temperature version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
140
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rise time
Serial I/O1 clock output fall time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 32
X
D)
–30
tr(SCLK1)
tf(SCLK1)
30
30
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
)
)
/2–160
t
c(SCLK2
/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 33
Fig. 32
200
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output fall time
CMOS output rise time (Note 2)
CMOS output fall time (Note 2)
40
30
30
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: Pins XOUT pin and P70–P77 are excluded.
44
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
–20
–20
60
Typ.
Max.
_____
____
tsu(ONW–φ)
____
th(φ–ONW)
Before φ ONW input set up time
ns
ns
ns
ns
_____
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
0
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
Before RD data bus set up time
___
65
0
ns
ns
__
th(RD–DB)
After RD data bus hold time
SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
(Extended operating temperature version)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
20
10
25
10
20
10
10
5
40
45
6
6
tv(φ–SYNC)
___
td(φ–WR)
___
SYNC valid time
___
___
RD and WR delay time
___ ___
20
10
70
tv(φ–WR)
RD and WR valid time
3
td(φ–DB)
tv(φ–DB)
__
twL(RD)
twL(WR)
__
td(AH–RD)
td(AH–WR)
__
td(AL–RD)
td(AL–WR)
__
After φ data bus delay time
After φ data bus valid time
20
15
___
___
Fig. 32
RD pulse width, WR pulse width
___ ___
tc(XIN)–10
__
RD pulse width, WR pulse width
3tc(XIN)–10
ns
ns
ns
ns
ns
(When one-wait is valid)
___
After AD15–AD8 RD delay time
___
___
tc(XIN)–35
t
t
c(XIN
c(XIN
)
)
–15
–20
After AD15–AD8 WR delay time
___
After AD7–AD0 RD delay time
___
___
tc(XIN)–40
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
0
0
5
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
5
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
___
tv(WR–DB)
___ _____
After WR data bus delay time
___
15
65
ns
ns
ns
ns
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
200
200
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
_________
Note 1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
45
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS (High-speed version)
Symbol
Parameter
Conditions
Ratings
Unit
V
VCC
Power source voltage
–0.3 to 7.0
Input voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
VI
–0.3 to VCC +0.3
V
P60–P67, P70–P77, P80–P87,
VREF, XIN
______
VI
VI
Input voltage RESET
–0.3 to 7.0
–0.3 to 7.0
–0.3 to 13
V
V
All voltages are based on VSS.
Output transistors are cut off.
Mask ROM version
Input voltage CNVSS
PROM version
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P67, P70–P77, P80–P87,
XOUT
VO
–0.3 to VCC +0.3
V
Pd
Power dissipation
Ta = 25 °C
500
mW
°C
Topr
Tstg
Operating temperature
Storage temperature
–20 to 85
–40 to 125
°C
RECOMMENDED OPERATING CONDITIONS (High-speed version)
(VCC = 2.7 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Power source voltage (f(XIN) < 4.15 MHz)
Min.
2.7
Typ.
5.0
5.0
0
Max.
5.5
VCC
V
V
V
Power source voltage (f(XIN) = 10 MHz)
Power source voltage
4.0
5.5
VSS
Analog reference voltage (when A-D converter is used)
Analog reference voltage (when D-A converter is used)
Analog power source voltage
2.0
2.7
VCC
VCC
VREF
AVSS
VIA
0
V
V
Analog input voltage
“H” input voltage
AN0–AN7
AVSS
VCC
VCC
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
______
VIH
P50–P57, P60–P67, P70–P77, P80–P87, RESET, XIN, 0.8 VCC
CNVSS
V
“L” input voltage
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
______
0
VIL
0.2 VCC
V
P5
XIN
P0
P40–P47,P50–P57, P60–P67 (Note 1)
P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0–P57, P60–P67, P70–P77, P80–P87, RESET, CNVSS
VIL
“L” input voltage
0
0.16 VCC
–80
–80
80
V
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
“H” total peak output current
“H” total peak output current
“L” total peak output current
“L” total peak output current
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
7
7
(Note 1)
(Note 1)
mA
mA
mA
mA
mA
mA
mA
mA
0
7
0
7
0
7
0
7
–P8
P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
80
“H” total average output current P0
“H” total average output current P40–P47,P50–P57, P60–P67 (Note 1)
“L” total average output current P0 –P0 , P1 –P1 , P2 –P2 , P3 –P3 , P8
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P8
0
0
–P8
7
7
(Note 1)
–40
–40
40
0
7
0
7
0
7
0
7
–P8
(Note 1)
“L” total average output current P40–P47,P50–P57, P60–P67, P70–P77 (Note 1)
40
“H” peak output current
“L” peak output current
“H” average output current
“L” average output current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 2)
IOH(peak)
IOL(peak)
IOH(avg)
IOL(avg)
–10
10
–5
5
mA
mA
mA
mA
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 2)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P80–P87 (Note 3)
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P67, P70–P77, P80–P87 (Note 3)
Internal clock oscillation frequency (4.0 V < VCC < 5.5 V)
Internal clock oscillation frequency (2.7 V < VCC < 4.0 V)
10
f(XIN)
MHz
4.5VCC–8
Note 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms.
46
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
IOH = –10 mA
Unit
Min.
Typ.
Max.
“H” output voltage P0
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P8
0
0
0
–P1
–P4
–P8
7
7
7
, P2
, P5
(Note 1)
0
0
–P2
–P5
7
,
,
V
V
CC–2.0
P3
P6
7
VCC = 4.0 to 5.5 V
VOH
V
IOH = –1.0 mA
VCC = 2.7 to 5.5 V
CC–1.0
“L” output voltage P0
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0–P1
0–P4
0–P7
7
7
7
, P2
0
–P2
–P5
–P8
7
,
IOL = 10 mA
VCC = 4.0 to 5.5 V
2.0
1.0
P3
P6
,P5
0
7
,
VOL
V
, P8
0
7
IOL = 1.0 mA
VCC = 2.7 to 5.5 V
VT+ – VT–
VT+ – VT–
VT+ – VT–
Hysteresis
CNTR
0
, CNTR
1
, INT
0
–INT
4
0.4
0.5
0.5
V
V
V
Hysteresis
RXD, SCLK1, SIN2, SCLK2
______
RESET
Hysteresis
“H” input current
P0
P3
P6
0
0
0
–P0
–P3
–P6
7
7
7
, P1
, P4
, P7
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P8
7
7
7
,
,
IIH
VI = VCC
5.0
5.0
µA
______
IIH
IIH
“H” input current
“H” input current
“L” input current
RESET, CNVSS
VI = VCC
VI = VCC
µA
µA
X
IN
4
P0
P3
P6
0
0
0
–P0
–P3
7
7
, P1
, P4
0
0
0
–P1
–P4
–P7
7, P2
7, P5
7, P8
0
0
0
–P2
–P5
–P87,
7
,
,
7
IIL
VI = VSS
–5.0
µA
–P6 , P7
______7
RESET, CNVSS
IIL
“L” input current
X
IN
VI = VSS
–4
µA
VRAM
RAM hold voltage
With clock stopped
f(XIN) = 10 MHz, VCC = 5 V
f(XIN) = 4 MHz, VCC = 2.7 V
2.0
5.5
16
2
V
8
1.3
When WIT instruction is executed
with f(XIN) = 10 MHz, VCC = 5 V
mA
2
0.3
0.1
When WIT instruction is executed
with f(XIN) = 4 MHz, VCC = 2.7 V
ICC
Power source current
When STP instruction
Ta = 25 °C
1
is executed with clock (Note 2)
µA
stopped, output
transistors isolated.
(Note 2)
Ta = 85 °C
10
Note 1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin.
A-D CONVERTER CHARACTERISTICS (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC, T
a
= –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
LSB
tC(φ)
kΩ
Absolute accuracy (excluding quantization error)
Conversion time
±1
±2.5
50
tCONV
RLADDER
IVREF
Ladder resistor
35
150
0.5
Reference power source input current (Note)
A-D port input current
VREF = 5.0 V
50
200
5.0
µA
II(AD)
µA
Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”.
47
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
D-A CONVERTER CHARACTERISTICS (High-speed version)
(VCC = 2.7 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.7 V to VCC, T
a
= –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter Test conditions
Min.
Typ.
Max.
8
—
—
Resolution
Bits
%
V
V
CC = 4.0 to 5.5 V
CC = 2.7 to 5.5 V
1.0
2.5
3
Absolute accuracy
tsu
Setting time
µs
kΩ
mA
RO
Output resistor
1
2.5
4
IVREF
Reference power source input current (Note)
3.2
Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur-
rents flowing through the A-D resistance ladder.
48
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Unit
Symbol
Parameter
Min.
Typ.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tc(XIN)
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
100
40
twH(XIN)
twL(XIN)
40
tc(CNTR)
twH(CNTR)
twH(INT)
twL(CNTR)
twL(INT)
200
80
80
80
80
tc(SCLK1)
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
800
1000
370
400
370
400
220
200
100
200
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”.
TIMING REQUIREMENTS 2 (High-speed version)
VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Unit
Min.
Typ.
Max.
_____
tw(RESET)
Reset input “L” pulse width
2
µs
1000/
(4.5 VCC–8)
tc(XIN)
External clock input cycle time
ns
400/
(4.5 VCC–8)
twH(XIN)
twL(XIN)
External clock input “H” pulse width
External clock input “L” pulse width
ns
ns
400/
(4.5 VCC–8)
tc(CNTR)
twH(CNTR)
twH(INT)
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
INT0 to INT4 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “L” pulse width
500
230
230
230
230
2000
2000
950
950
950
950
400
400
200
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twL(CNTR)
twL(INT)
tc(SCLK1)
Serial I/O1 clock input cycle time (Note)
Serial I/O2 clock input cycle time
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O2 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O2 clock input “L” pulse width
Serial I/O1 input set up time
tc(SCLK2)
twH(SCLK1)
twH(SCLK2)
twL(SCLK1)
twL(SCLK2)
t
t
t
t
su(R
su(SIN2–SCLK2
D)
h(SCLK2–SIN2
X
D–SCLK1
)
)
Serial I/O2 input set up time
h(SCLK1–R
X
Serial I/O1 input hold time
)
Serial I/O2 input hold time
Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”.
49
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS 1 (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Test conditions
Unit
Parameter
Min.
Typ.
Max.
140
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
)
/2–30
/2–30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 32
X
D)
–30
tr(SCLK1)
tf(SCLK1)
30
30
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
)
)
/2–160
t
c(SCLK2
/2–160
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 33
Fig. 32
200
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
30
30
30
10
10
Note1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
SWITCHING CHARACTERISTICS 2 (High-speed version)
(VCC = 2.7 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
350
twH(SCLK1)
twL(SCLK1)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
t
t
c(SCLK1
)
)
/2–50
/2–50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
c(SCLK1
t
t
d(SCLK1–T
v(SCLK1–T
X
D)
Fig. 32
X
D)
–30
tr(SCLK1)
tf(SCLK1)
50
50
twH(SCLK2)
twL(SCLK2)
t
c(SCLK2
)
)
/2–240
t
c(SCLK2
/2–240
t
t
d(SCLK2–SOUT2
v(SCLK2–SOUT2
)
Fig. 33
Fig. 32
400
)
Serial I/O2 output valid time
0
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O2 clock output falling time
CMOS output rising time (Note 2)
CMOS output falling time (Note 2)
50
50
50
20
20
Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: XOUT pin is excluded.
50
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (High-speed version)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
–20
–20
50
Typ.
25
Max.
_____
____
tsu(ONW–φ)
____
th(φ–ONW)
Before φ ONW input set up time
ns
ns
ns
ns
_____
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
0
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
Before RD data bus set up time
___
50
0
25
ns
ns
__
th(RD–DB)
After RD data bus hold time
SWITCHING CHARACTERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
(High-speed version)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
After φ AD15–AD8 delay time
After φ AD15–AD8 valid time
After φ AD7–AD0 delay time
After φ AD7–AD0 valid time
SYNC delay time
tc(XIN)–10
tc(XIN)–10
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
__
16
5
35
40
2
2
20
5
16
5
SYNC valid time
After φ data bus delay time
After φ data bus valid time
15
30
10
___
___
RD pulse width, WR pulse width
___ ___
tc(XIN)–10
twL(RD)
___
Fig. 32
RD pulse width, WR pulse width
twL(WR)
__
td(AH–RD)
td(AH–WR)
__
td(AL–RD)
3tc(XIN)–10
ns
ns
ns
ns
ns
(when one-wait is valid)
___
After AD15–AD8 RD delay time
___
___
tc(XIN)–35
t
t
c(XIN
c(XIN
)
)
–16
–20
After AD15–AD8 WR delay time
___
After AD7–AD0 RD delay time
___
___
tc(XIN)–40
td(AL–WR)
__
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
2
2
5
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
5
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
After WR data bus delay time
___
15
30
ns
ns
ns
ns
___
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
200
100
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
_________
Note 1: The RESETOUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
51
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
(High-speed version)
Limits
Symbol
Parameter
Unit
Min.
–20
–20
120
0
Typ.
60
Max.
_____
____
tsu(ONW–φ)
____
Before φ ONW input set up time
ns
ns
ns
ns
_____
th(φ–ONW)
After φ ONW input hold time
Before φ data bus set up time
tsu(DB–φ)
th(φ–DB)
After φ data bus hold time
___ _____
____ __
tsu(ONW–RD)
Before RD ONW input set up time
___ _____
____ ___
–20
–20
ns
ns
tsu(ONW–WR) Before WR ONW input set up time
___ _____
__ ____
th(RD–ONW) After RD ONW input hold time
___ _____
___ ____
th(WR–ONW) After WR ONW input hold time
___
__
tsu(DB–RD)
Before RD data bus set up time
___
120
0
60
ns
ns
__
th(RD–DB)
After RD data bus hold time
SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE
(High-Speed Version)
(VCC = 2.7 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min.
Typ.
Max.
tc(φ)
φ clock cycle time
2tc(XIN)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
twH(φ)
φ clock “H” pulse width
φ clock “L” pulse width
AD15–AD8 delay time
AD15–AD8 valid time
AD7–AD0 delay time
AD7–AD0 valid time
SYNC delay time
tc(XIN)–20
tc(XIN)–20
twL(φ)
td(φ–AH)
tv(φ–AH)
td(φ–AL)
tv(φ–AL)
td(φ–SYNC)
tv(φ–SYNC)
td(φ–DB)
tv(φ–DB)
__
40
10
50
10
40
10
30
100
100
5
5
SYNC valid time
Data bus delay time
Data bus valid time
80
10
___
___
Fig. 32
RD pulse width, WR pulse width
___ ___
tc(XIN)–20
twL(RD)
___
RD pulse width, WR pulse width
twL(WR)
__
td(AH–RD)
td(AH–WR)
__
td(AL–RD)
3tc(XIN)–20
ns
ns
ns
ns
ns
(when one-wait is valid)
___
After AD15–AD8 RD delay time
___
___
tc(XIN)–100
t
t
c(XIN
c(XIN
)
)
–40
–50
After AD15–AD8 WR delay time
___
After AD7–AD0 RD delay time
___
___
tc(XIN)–100
td(AL–WR)
__
After AD7–AD0 WR delay time
___
tv(RD–AH)
After RD AD15–AD8 valid time
___
___
5
5
10
tv(WR–AH)
__
After WR AD15–AD8 valid time
___
tv(RD–AL)
After RD AD7–AD0 valid time
___
___
10
30
tv(WR–AL)
___
After WR AD7–AD0 valid time
___
td(WR–DB)
After WR data bus delay time
___
80
ns
ns
ns
ns
___
tv(WR–DB)
___ _____
After WR data bus valid time
_________
10
0
t
d
(RESET–RESETOUT
)
RESETOUT output delay time (Note 1)
_________
300
150
_____
tv(φ–RESET)
RESETOUT output valid time (Note 1)
_________
Note 1: The RESETOUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after
______
the RESET input goes “H”.
1kΩ
Measurement output pin
Measurement output pin
100pF
100pF
N-channel open-drain output
Circuit for measuring output switching
characteristics (2)
CMOS output
Fig. 33
Fig. 32
Circuit for measuring output switching
characteristics (1)
52
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING DIAGLAM
(1)Timing Diagram
tC(CNTR)
tWL(CNTR)
tWH(CNTR)
0.8 VCC
CNTR
0
, CNTR
1
0.2 VCC
t
WL(INT)
tWH(INT)
0.8 VCC
INT0–INT
RESET
4
0.2 VCC
tW(RESET)
0.8 VCC
0.2 VCC
tC(XIN)
tWL(XIN)
t
WH(XIN)
0.8 VCC
XIN
0.2 VCC
tC(SCLK1),
tC(SCLK2)
tWL(SCLK1),
tWL(SCLK2
)
tWH(SCLK1), tWH(SCLK2)
tr
tf
S
S
CLK1
CLK2
0.8 VCC
0.2 VCC
t
su(R
X
D
-
S
CLK1),
CLK2
th(SCLK1-
t
R
X
D),
tsu(SIN2-
S
)
h
(SCLK2-
SIN2
)
R
S
X
D
0.8 VCC
0.2 VCC
IN2
t
t
v(SCLK1-T
v(SCLK2-
X
D),
td(SCLK1-T
X
D),td(SCLK2-SOUT2)
S
OUT2
)
TXD
SOUT2
53
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2)Timing Diagram in Memory Expansion Mode and Microprocessor Mode (a)
tC(φ)
tWL(φ)
tWH(φ)
φ
0.5 VCC
tv(φ-AH)
td(φ-AH)
0.5 VCC
0.5 VCC
AD15–AD
8
td(φ-AL)
tv(φ-AL)
AD7
–AD
0
tv(φ-SYNC)
td(φ-SYNC)
0.5 VCC
SYNC
td(φ-WR)
0.5 VCC
tv(φ-WR)
RD,WR
th(φ-ONW)
tSU(ONW-φ)
0.8 VCC
0.2 VCC
ONW
th(φ-DB)
tv(φ-DB)
tSU(DB-φ)
0.8 VCC
0.2 VCC
DB
0
–DB
7
(At CPU reading)
td(φ-DB)
DB0–DB
7
0.5 VCC
(At CPU writing)
(3)Timing Diagram in Microprocessor Mode
0.8 VCC
RESET
0.2 VCC
φ
0.5 VCC
td(RESET- RESETOUT)
tv(φ- RESETOUT)
0.5 VCC
RESETOUT
54
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(4) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (b)
t
WL(RD)
tWL(WR)
RD,WR
0.5 VCC
t
d(AH-RD)
d(AH-WR)
t
t
v(RD-AH)
v(WR-AH)
t
0.5 VCC
AD15–AD
8
t
d(AL-RD)
d(AL-WR)
t
t
v(RD-AL)
v(WR-AL)
t
0.5 VCC
AD7
–AD
0
t
t
h(RD-ONW)
h(WR-ONW)
t
t
su(ONW-RD)
su(ONW-WR)
0.8 VCC
0.2 VCC
ONW
(At CPU reading)
RD
tWL(RD)
0.5 VCC
tSU(DB-RD)
th(RD-DB)
0.8 VCC
0.2 VCC
DB0–DB7
(At CPU writing)
WR
tWL(WR)
0.5 VCC
tv(WR-DB)
td(WR-DB)
0.5 VCC
DB0–DB7
55
MITSUBISHI MICROCOMPUTERS
3806 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
•
•
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
•
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
•
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the
approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
•
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
© 1996 MITSUBISHI ELECTRIC CORP.
H-DF047-C KI-9609
New publication, effective Sep. 1996.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
3806GROUP DATA SHEET
Rev.
Rev.
date
Revision Description
No.
1.0 First Edition
971128
(1/1)
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