M5M51008DVP [RENESAS]

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM; 1048576 - BIT （ 131072 -字×8位）的CMOS静态RAM


型号：	M5M51008DVP
厂家：	RENESAS TECHNOLOGY CORP
描述：	1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM 1048576 - BIT （ 131072 -字×8位）的CMOS静态RAM
文件：	总9页 (文件大小：119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi

Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi

Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names

have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.

Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been

made to the contents of the document, and these changes do not constitute any alteration to the

contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices

and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

DESCRIPTION

PIN CONFIGURATION (TOP VIEW)

The M5M51008DP,FP,VP,RV,KV are a 1048576-bit CMOS static

RAM organized as 131072 word by 8-bit which are fabricated using

high-performance quadruple-polysilicon and double metal CMOS

technology. The use of thin film transistor (TFT) load cells and

CMOS periphery result in a high density and low power static

RAM.

A16

A14

A12

VCC

ADDRESS

A15 INPUT

CHIP SELECT

INPUT

WRITE CONTROL

INPUT

They are low standby current and low operation current and ideal

for the battery back-up application.

28 A13

The M5M51008DVP,RV,KV are packaged in a 32-pin thin small

outline package which is a high reliability and high density surface

mount device(SMD). Two types of devices are available.

M5M51008DVP(normal lead bend type package),

ADDRESS

INPUTS

ADDRESS

INPUTS

26 A9

25 A11

24 OE

23 A10

M5M51008DRV(reverse lead bend type package).Using both types

of devices, it becomes very easy to design a printed circuit board.

OUTPUT ENABLE

INPUT

ADDRESS

INPUT

CHIP SELECT

INPUT

A2 10

A0 12

DQ1 13

DQ8

DQ7

DATA

INPUTS/

OUTPUTS

DATA

INPUTS/

OUTPUTS

DQ2

19 DQ6

FEATURES

DQ3 15

GND16

DQ5

Power supply current

Access

DQ4

Active

(1MHz)

(max)

Type name

time

stand-by

(max)

Outline 32P2M-A(FP)

M5M51008DFP,VP,RV,KV-55H

M5M51008DFP,VP,RV,KV-70H

55ns

70ns

20µA

15mA

(1MHz)

A11

A10

(Vcc=5.5V)

A13

29 DQ8

Directly TTL compatible : All inputs and outputs

Easy memory expansion and power down by S1,S2

Data hold on +2V power supply

Three-state outputs : OR - tie capability

OE prevents data contention in the I/O bus

Common data I/O

DQ7

DQ6

A15

VCC

DQ5

DQ4

GND

DQ3

DQ2

DQ1

M5M51008DVP,KV

Package

A16 10

M5M51008DFP

···········3· 2pin 525mil SOP

M5M51008DVP,RV ···········3· 2pin 8 X 20 mm²₂TSOP

A14

M5M51008DKV

···········3· 2pin 8 X 13.4 mm TSOP

A12

APPLICATION

Small capacity memory units

Outline 32P3H-E(VP), 32P3K-B(KV)

18 A2

19 A1

20 A0

21 DQ1

A12

A14

DQ2

A16

DQ3

GND

M5M51008DRV

VCC

DQ4

A15

DQ5

DQ6

DQ7

DQ8

A13

A10

A11

Outline 32P3H-F(RV)

NC : NO CONNECTION

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M51008D series are determined by

a combination of the device control inputs S1,S2,W and OE.

Each mode is summarized in the function table.

When setting S1 at a high level or S2 at a low level, the chip are in

a non-selectable mode in which both reading and writing are

disabled. In this mode, the output stage is in a high- impedance

state, allowing OR-tie with other chips and memory expansion by

S1 and S2. The power supply current is reduced as low as the

stand-by current which is specified as ICC3 or ICC4, and the memory

data can be held at +2V power supply, enabling battery back-up

operation during power failure or power-down operation in the non-

selected mode.

A write cycle is executed whenever the low level W overlaps with

the low level S1 and the high level S2. The address must be set up

before the write cycle and must be stable during the entire cycle.

The data is latched into a cell on the trailing edge of W,S1 or

S2,whichever occurs first,requiring the set-up and hold time relative

to these edge to be maintained. The output enable input OE

directly controls the output stage. Setting the OE at a high level,

the output stage is in a high-impedance state, and the data bus

contention problem in the write cycle is eliminated.

A read cycle is executed by setting W at a high level and OE at a

low level while S1 and S2 are in an active state(S1=L,S2=H).

FUNCTION TABLE

Mode

ICC

S1 S2

Stand-by

Non selection High-impedance

Non selection High-impedance Stand-by

Din

Dout

Active

Write

Read

High-impedance

Note 1: "H" and "L" in this table mean VIH and VIL, respectively.

2: "X" in this table should be "H" or "L".

BLOCK DIAGRAM

DQ1

DQ2

DQ3

A2 10

131072 WORDS

X 8 BITS

(512 ROWS

X128 COLUMNS

X 16BLOCKS)

DATA

INPUTS/

OUTPUTS

DQ4

DQ5

DQ6

A12

A14

A16

A15

20 DQ7

21 DQ8

ADDRESS

INPUTS

CLOCK

GENERATOR

A13

A11

WRITE

CONTROL

INPUT

CHIP

SELECT

INPUTS

A1 11

A10 23

OUTPUT

ENABLE

INPUT

24 OE

32 VCC

GND

(0V)

* Pin numbers inside dotted line show those of TSOP

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Ratings

Conditions

With respect to GND

Unit

Supply voltage

Input voltage

– 0.3*~7

– 0.3*~Vcc + 0.3

V_I

Output voltage

Power dissipation

V_O

P_d

0~Vcc

700

Ta=25°C

°C

T_opr

T_stg

Operating temperature

Storage temperature

0~70

– 65~150

°C

* –3.0V in case of AC ( Pulse width £ 50ns )

(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)

Test conditions

DC ELECTRICAL CHARACTERISTICS

Limits

Unit

Symbol

Parameter

Min

Typ

Max

2.2

–0.3*

2.4

VIH

VIL

High-level input voltage

Low-level input voltage

Vcc + 0.3

0.8

IOH= –1.0mA

IOH= –0.1mA

VOH

High-level output voltage

Vcc – 0.5

VOL

Low-level output voltage

Input current

IOL=2mA

VI=0~Vcc

0.4

±1

µA

S1=VIH or S2=VIL or OE=VIH

VI/O=0~VCC

±1

Output current in off-state

µA

55ns

70ns

S1 £ 0.2V, S2 ³ VCC–0.2V

other inputs £ 0.2V or ³ VCC–0.2V

Output-open(duty 100%)

Active supply current

(AC, MOS level)

ICC1

1MHz

55ns

S1=VIL,S2=VIH,

other inputs=VIH or VIL

Output-open(duty 100%)

Active supply current

(AC, TTL level)

ICC2

70ns

1MHz

1) S2 £ 0.2V,

~25°C

-H ~40°C

~70°C

other inputs=0~VCC

2) S1 ³ VCC–0.2V,

S2 ³ VCC–0.2V,

ICC3

ICC4

Stand-by current

µA

other inputs=0~VCC

S1=VIH or S2=VIL,

other inputs=0~VCC

* –3.0V in case of AC ( Pulse width £ 50ns )

(Ta=0~70°C, Vcc=5V±10% unless otherwise noted)

Parameter

CAPACITANCE

Limits

Typ

Symbol

Test conditions

Unit

Min

Max

Input capacitance

Output capacitance

FP,VP,RV,KV

VI=GND, VI=25mVrms, f=1MHz

VO=GND,VO=25mVrms, f=1MHz

Note 3: Direction for current flowing into an IC is positive (no mark).

4: Typical value is Vcc = 5V, Ta = 25°C

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

AC ELECTRICAL CHARACTERISTICS (Ta=0~70°C, 5V±10% unless otherwise noted )

(1) MEASUREMENT CONDITIONS

VCC

...............

Input pulse level

VIH=2.4V,VIL=0.6V (-70H)

VIH=3.0V,VIL=0.0V (-55H)

5ns

......

1.8kW

Input rise and fall time

................

Reference level

VOH=VOL=1.5V

.....................

Output loads

Fig.1, CL=100pF (-70H)

CL=30pF (-55H)

990W

CL ( Including scope

CL=5pF (for ten,tdis)

Transition is measured ± 500mV from steady

state voltage. (for ten,tdis)

and JIG )

Fig.1 Output load

(2) READ CYCLE

Limits

-70H

Symbol

Parameter

-55H

Unit

Min

Max

Min

Max

tCR

Read cycle time

Address access time

ta(A)

ta(S1)

ta(S2)

ta(OE)

tdis(S1)

tdis(S2)

tdis(OE)

ten(S1)

Chip select 1 access time

Chip select 2 access time

Output enable access time

Output disable time after S1 high

Output disable time after S2 low

Output disable time after OE high

Output enable time after S1 low

Output enable time after S2 high

Output enable time after OE low

Data valid time after address

ten(S2)

ten(OE)

tV(A)

(3) WRITE CYCLE

Limits

Symbol

Parameter

-55H

-70H

Unit

Min

Max

Min

Max

tCW

Write cycle time

Write pulse width

tw(W)

Address setup time

tsu(A)

tsu(A-WH)

tsu(S1)

tsu(S2)

tsu(D)

Address setup time with respect to W

Chip select 1 setup time

Chip select 2 setup time

Data setup time

th(D)

Data hold time

trec(W)

tdis(W)

tdis(OE)

ten(W)

ten(OE)

Write recovery time

Output disable time from W low

Output disable time from OE high

Output enable time from W high

Output enable time from OE low

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

(4) TIMING DIAGRAMS

Read cycle

tCR

A0~16

ta(A)

tv (A)

ta (S1)

(Note 5)

tdis (S1)

tdis (S2)

ta (S2)

ta (OE)

ten (OE)

(Note 5)

tdis (OE)

(Note 5)

ten (S1)

ten (S2)

DQ1~8

DATA VALID

W = "H" level

Write cycle (W control mode)

tCW

A0~16

tsu (S1)

(Note 5)

tsu (S2)

tsu (A-WH)

tsu (A)

tw (W)

trec (W)

tdis (W)

ten(OE)

ten (W)

tdis (OE)

DATA IN

STABLE

DQ1~8

tsu (D)

th (D)

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

Write cycle ( S1 control mode)

tCW

A0~16

tsu (A)

trec (W)

tsu (S1)

(Note 5)

(Note 7)

(Note 6)

(Note 5)

th (D)

tsu (D)

DATA IN

STABLE

DQ1~8

Write cycle (S2 control mode)

tCW

A0~16

(Note 5)

tsu (A)

tsu (S2)

trec (W)

(Note 7)

(Note 6)

(Note 5)

tsu (D)

th (D)

DATA IN

STABLE

DQ1~8

Note 5: Hatching indicates the state is "don't care".

6: Writing is executed while S2 high overlaps S1 and W low.

7: When the falling edge of W is simultaneously or prior to the falling edge of S1

or rising edge of S2, the outputs are maintained in the high impedance state.

8: Don't apply inverted phase signal externally when DQ pin is output mode.

Ver. 1.1

MITSUBISHI LSIs

M5M51008DFP,VP,RV,KV,KR -55H, -70H

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

POWER DOWN CHARACTERISTICS

(1) ELECTRICAL CHARACTERISTICS

(Ta=0~70°C, unless otherwise noted)

Test conditions

Limits

Typ

Symbol

VCC (PD)

VI (S1)

Parameter

Power down supply voltage

Chip select input S1

Unit

Min

2.0

2.2

Max

2.2V£Vcc(PD)

2V£Vcc(PD)£2.2V

4.5V£Vcc(PD)

Vcc(PD)<4.5V

VCC = 3V

Vcc(PD)

0.8

0.2

VI (S2)

Chip select input S2

~25°C

~40°C

~70°C

1) S2 £ 0.2V, other inputs = 0~3V

2) S1 ³ VCC–0.2V,S2 ³ VCC–0.2V

other inputs = 0~3V

-H

µA

ICC (PD)

Power down supply current

(2) TIMING REQUIREMENTS (Ta=0~70°C, unless otherwise noted )

Limits

Typ

Symbol

Parameter

Test conditions

Unit

Min

Max

tsu (PD)

trec (PD)

Power down set up time

Power down recovery time

(3) POWER DOWN CHARACTERISTICS

S1 control mode

VCC

4.5V

tsu (PD)

trec (PD)

2.2V

S1 ³ VCC – 0.2V

Note 9: On the power down mode by controlling S1,the input level of S2 must be S2 ³ Vcc - 0.2V or

S²£ 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state.

S2 control mode

VCC

4.5V

tsu (PD)

trec (PD)

0.2V

S2 £ 0.2V

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consideration to safety when making your circuit designs, with appropriate measures such as (i)

placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention

against any malfunction or mishap.

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M5M51008DVP [RENESAS]

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