M5M5256DFP-55XL [RENESAS]
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM; 262144 - BIT （ 32768 -字×8位）的CMOS静态RAM
| 型号： | M5M5256DFP-55XL |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M5M5256DFP,VP is 262,144-bit CMOS static RAMs
organized as 32,768-words by 8-bits which is f abricated using
high-perf ormance 3 poly silicon CMOS technology . The use of
resistiv e load NMOS cells and CMOS periphery results in a high
density and low power static RAM. Stand-by current is small
enough f or battery back-up application. It is ideal f or the memory
sy stems which require simple interf ace.
28
1
2
A14
A12
Vcc
/W
27
26
25
3
A13
A8
A7
A6
A5
A4
4
24
23
22
21
20
19
18
17
16
15
5
A9
A11
/OE
6
Especially the M5M5256DVP are packaged in a 28-pin thin small
outline package.
7
A3
A2
A1
A0
8
A10
/S
DQ8
DQ7
DQ6
DQ5
9
10
DQ1 11
DQ2
12
13
14
FEATURE
DQ3
GND
Power supply current
Access
Oprating
DQ4
Ty pe
time
(max)
Activ e Stand-by
Temperature
Outline 28P2W-C (FP)
(max)
(max)
M5M5256DFP,VP-55LL
M5M5256DFP,VP-70LL
55ns
70ns
20µA
22
21
A10
/S
DQ8
DQ7
DQ6
DQ5
0~70°C
/OE
A11
(Vcc=5.5V)
23
20
19
18
17
16
15
14
13
12
11
10
9
24 A9
25
A8
26
27
28
1
A13
/W
Vcc
A14
A12
A7
50mA
40µA
(Vcc=5.5V)
M5M5256DFP,VP-70LLI 70ns
-40~85°C
(Vcc=5.5V)
DQ4
GND
M5M5256DVP
2
5µA
DQ3
DQ2
DQ1
A0
A1
A2
(Vcc=5.5V)
M5M5256DFP,VP-55XL
M5M5256DFP,VP-70XL
55ns
70ns
3
0.05µA
(Vcc=3.0V,
Typical)
0~70°C
4
A6
A5
A4
A3
5
6
8
7
•Single +5V power supply
•No clocks, no ref resh
Outline 28P2C-A (VP)
•Data-Hold on +2.0V power supply
•Directly TTL compatible : all inputs and outputs
•Three-state outputs : OR-tie capability
•/OE prev ents data contention in the I/O bus
•Common Data I/O
•Battery backup capability
•Low stand-by current .......... 0.05µA(ty p.)
PACKAGE
M5M5256DFP
M5M5256DVP
: 28 pin 450 mil SOP
: 28pin 8 X 13.4 mm TSOP
2
APPLICATION
Small capacity memory units
1
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5256DFP,VP is
A read cy cle is executed by setting /W at a high lev el
determined by a combination of the dev ice control inputs
/S, /W and /OE. Each mode is summarized in the f unction
table.
and /OE at a low lev el while /S are in an activ e state.
When setting /S at a high lev el, the chip is in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips and
memory expansion by /S. The power supply current is
reduced as low as the stand-by current which is specif ied
as Icc3 or Icc4, and the memory data can be held at
+2V power supply , enabling battery back-up operation
during power f ailure or power-down operation in the non-
selected mode.
A write cy cle is executed whenev er the low lev el /W
ov erlaps with the low lev el /S. The address must be set
up bef ore the write cy cle and must be stable during the
entire cy cle. The data is latched into a cell on the trailing
edge of /W, /S, whichev er occurs f irst, requiring the set-
up and hold time relativ e to these edge to be maintained.
The output enable /OE directly controls the output stage.
Setting the /OE at a high lev el,the output stage is in a
high-impedance state, and the data bus contention
problem in the write cy cle is eliminated.
FUNCTION TABLE
DQ
/S
H
L
/OE
X
Mode
Icc
/W
High-impedance
Stand-by
Activ e
Activ e
Activ e
Non selection
Write
X
L
DIN
X
L
Read
DOUT
L
L
H
H
High-impedance
H
Note • "H" and "L" in this table mean VIH and VIL, respectiv ely .
• "X" in this table should be "H" or "L".
BLOCK DIAGRAM
A 8
25
26
1
11
DQ1
DQ2
DQ3
32768 WORD
X 8BIT
A 13
A 14
12
13
2
A 12
A 7
15
16
DQ4
DQ5
DQ6
DATA I/O
3
4
5
6
7
(512 ROWS X
A 6
17
18
A 5
A 4
512 COLUMNS)
DQ7
DQ8
19
ADDRESS
INPUT
A 3
A 2
A 1
A 0
A 10
A 11
A 9
8
9
10
21
23
24
CLOCK
GENERATOR
WRITE CONTROL
INPUT /W
27
20
22
VCC
(5V)
28
CHIP SELECT
INPUT
/S
14 GND
(0V)
OUTPUT ENABLE
INPUT
/OE
2
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Ratings
Unit
V
Symbol
Vcc
Parameter
Supply voltage
Conditions
-0.3*~7.0
-0.3*~Vcc+0.3
V
VI
Input voltage
With respect to GND
(Max 7.0)
0~Vcc
700
0~70
-40~85
-65~150
VO
Pd
Output voltage
Power dissipation
V
mW
Ta=25°C
-LL,-XL
-LLI
Topr
Operating temperature
°C
°C
Storage temperature
Tstg
_
* -3.0V in case of AC ( Pulse width < 30ns )
DC ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted)
Limits
Symbol
Parameter
Test conditions
Unit
Min Typ Max
Vcc
VIH
High-level input voltage
2.2
V
V
+0.3
0.8
Low-level input voltage
VIL
VOH1
VOH2
VOL
II
-0.3*
High-level output voltage 1 IOH=-1mA
High-level output voltage 2 IOH=-0.1mA
2.4
Vcc
-0.5
V
V
Low-level output voltage
Input current
IOL=2mA
0.4
±1
V
VI=0~Vcc
µA
µA
±1
IO
Output current in off-state
/S=VIH or or /OE=VIH, VI/O=0~Vcc
55ns
70ns
1MHz
55ns
70ns
1MHz
30
25
2
45
40
4
_
/S<0.2V,
Active supply current
(AC, MOS lev el )
Icc1
Icc2
Other inputs<0.2V or >Vcc-0.2V
Output-open
mA
mA
30
25
4
50
45
/S=VIL,
Active supply current
(AC, TTL lev el )
other inputs=VIH or VIL
Output-open
8
2
-LL,-LLI
-XL
~25°C
~40°C
0.1
0.4
6
-LL,-LLI
-XL
_
/S>Vcc-0.2V,
1.2
20
5
Icc3
Icc4
Stand-by current
Stand-by current
µA
other inputs=0~Vcc
-LL,-LLI
-XL
~70°C
~85°C
-LLI
40
3
/S=VIH,other inputs=0~Vcc
mA
_
* -3.0V in case of AC ( Pulse width < 30ns )
CAPACITANCE ( Vcc=5V±10%, unless otherwise noted)
Limits
Min Typ Max
Unit
Symbol
Parameter
Test conditions
Input capacitance
Output capacitance
pF
pF
CI
CO
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
6
8
Note 0: Direction f or current f lowing into an IC is positiv e (no mark).
1: Ty pical v alue is one at Ta = 25°C.
2: CI, CO are periodically sampled and are not 100% tested.
3
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted )
(1) READ CYCLE
Limits
-70LL,-70LLI,
-70 XL
Unit
Symbol
Parameter
-55LL, 55XL
Min
55
Max
Min
70
Max
ns
ns
ns
ns
ns
ns
ns
ns
tCR
Read cycle time
Address access time
Chip select access time
Output enable access time
ta(A)
ta(S)
ta(OE)
tdis(S)
55
55
30
20
20
70
70
35
25
25
Output disable time after /S high
tdis(OE) Output disable time after /OE high
ten(S)
Output enable time after /S low
ten(OE) Output enable time after /OE low
tV(A) Data valid time after address
5
5
10
5
5
10
ns
(2) WRITE CYCLE
Limits
-70LL,-70LLI,
-70 XL
-55LL, -55XL
Symbol
Parameter
Unit
Min
Max
Min
Max
tCW
tw(W)
tsu(A)
tsu(A-WH)
tsu(S)
tsu(D)
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
40
0
50
50
25
70
50
0
65
65
30
0
th(D)
0
0
trec(W)
tdis(W)
tdis(OE)
ten(W)
0
25
25
20
20
5
5
5
5
ten(OE)
4
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
(3) TIMING DIAGRAMS
Read cycle
tCR
A0~14
ta(A)
tv (A)
ta (S)
/S
(Note 3)
(Note 3)
ta (OE)
(Note 3)
(Note 3)
tdis (S)
ten (OE)
/OE
tdis (OE)
ten (S)
DATA VALID
DQ1~8
/W = "H" lev el
Write cycle (/W control mode)
tCW
A0~14
tsu (S)
/S
(Note 3)
(Note 3)
tsu (A-WH)
/OE
/W
tsu (A)
tw (W)
trec (W)
ten (W)
tdis (W)
ten(OE)
tdis (OE)
DATA IN
STABLE
DQ1~8
(Note 3)
(Note 3)
tsu (D)
th (D)
5
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle ( /S control mode)
tCW
A0~14
tsu (A)
tsu (S)
trec (W)
/S
(Note 5)
/W
(Note 4)
tsu (D)
(Note 3)
(Note 3)
th (D)
DATA IN
STABLE
DQ1~8
Note 3 : Hatching indicates the state is "don't care".
4 : Writing is executed in ov erlap of /S and /W low.
5 : If /W goes low simultaneously with or prior to /S, the outputs remain in the high impedance state.
6 : Don't apply inv erted phase signal externally when DQ pin is output mode.
7 : ten, tdis are periodically sampled and are not 100% tested.
(4) MEASUREMENT CONDITIONS
Input pulse level .............. VIH=2.4V,VIL=0.6V
Vcc
Input rise and fall time ..... 5ns
1.8kW
Reference level ................ VOH=VOL=1.5V
Output load ...................... Fig.1 CL=50pF (-55LL,-55XL )
DQ
L
C
990W
CL=100pF (-70LL,-70LLI,-70XL )
(Including
scope and JIG)
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Fig.1 Output load
6
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS ( Vcc=5V±10%, unless otherwise noted)
Limits
Min Typ Max
2
Symbol
Parameter
Test conditions
Unit
Vcc (PD)
Power down supply v oltage
V
V
V
_
2.2V < VCC(PD)
2.2
VI (/S)
Chip select input /S
_
_
2V< VCC(PD) < 2.2V
VCC(PD)
1
-LL,-LLI
-XL
~25°C
0.05 0.2
3
-LL,-LLI
-XL
_
Vcc = 3V,/S > Vcc-0.2V,
~40°C
Icc (PD)
Power down supply current
0.6
10
2
µA
Other inputs=0~Vcc
-LL,-LLI
-XL
~70°C
~85°C
-LLI
20
(2) TIMING REQUIREMENTS ( Vcc=5V±10%, unless otherwise noted )
Limits
Min Typ Max
Symbol
Unit
Parameter
Test conditions
tsu (PD)
trec (PD)
ns
ns
Power down set up time
0
tCR
Power down recov ery time
(3) POWER DOWN CHARACTERISTICS
/S control mode
Vcc
4.5V
4.5V
tsu (PD)
trec (PD)
2.2V
2.2V
_
/S
/S > Vcc-0.2V
7
RENESAS LSIs
M5M5256DFP,VP-55LL,-70LL,-70LLI,
-55XL,-70XL
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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REJ03C0055 © 2003 Renesas Technology Corp.
New publication, effective Feb 2004.
Specifications subject to change without notice
相关型号：
M5M5256DFP-55XLT
Standard SRAM, 32KX8, 55ns, MIXMOS, PDSO28, 0.450 INCH, 1.27 MM PITCH, PLASTIC, SOP-28
MITSUBISHI
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