M5M5408BFP-70E [RENESAS]
M5M5408BFP-70E;
| 型号： | M5M5408BFP-70E |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | M5M5408BFP-70E |
| 文件： | 总10页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statemenanges whatsoever have been
made to the contents of the document, and these changes do ny alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the busifrequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
DESCRIPTION
FEATURES
The M5M5408B is a f amily of 4-Mbit static RAMs organized
as 524,288-words by 8-bit, f abricated by Mitsubishi's high-
performance 0.25µm CMOS technology .
· Single +5V power supply
· Small stand-by current: 0.4µA(3V,ty p.)
· No clocks, No ref resh
The M5M5408B is suitable f or memory applications where a
simple interfacing , battery operating and battery backup are
the important design objectiv es.
· Data retention supply v oltage=2.0V to 5.5V
· All inputs and outputs are TTL compatible.
· Easy memory expansion by S#
· Common Data I/O
M5M5408B is packaged in 32-pin plastic SOP, 32-pin plastic
TSOP. Two ty pes of TSOPs are av ailable, M5M5408BTP
(normal-lead-bend TSOP) , M5M5408BRT (rev erse-lead-bend
TSOP). These two ty pes TSOPs are suitable f or a surf ace
mounting on double-sided printed circuit boards.
· Three-state outputs: OR-tie capability
· OE# prev ents data contention in the I/O bus
· Process technology: 0.25µm CMOS
· Package:
From the point of operating temperature, the f amily is
div ided into two v ersions; "Standard" and "I-v ersion". Those are
M5M540pin 525 mil SOP
M5Mpin 400 mil TSOP(ll)
PART NAME TABLE
Activ e
current
Icc1
D), Vcc=3.0V
s (max.)
Version,
Operating
Part name
Access
time
Power
(## stands f or
Supply
70°C
85°C
(5.0V, ty p.*)
"FP","TP",and "RT")
ma
temperature
Standard
0 ~ +70°C
M5M5408B## -55H
M5M5408B## -70H
M5M5408B## -55HI
M5M5408B## -70HI
50mA
(10MHz)
25mA
5.0V
5.
A
15µA
---
I-v ersion
1µA
15µA
30µA
(1MHz)
-40 ~ +85°C
pical v alues are sampled, and are not 100% tested.
PIN CONFIGURATION (TOP V
Pin
Function
1
2
3
4
5
1
1
30
A18
A18
A0 ~ A18 Address input
2
31
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A16
A14
DQ1 ~ DQ8 Data input / output
30
3
4
29
28
27
29
28
27
26
25
24
23
22
Chip select input
S# ( S )
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
#
A13
A8
W#
A13
A8
A9
A11
5
6
7
8
Write control input
Output inable input
Power supply
W# ( W )
6
7
8
OE# (OE)
Vcc
26
25
A9
A11
OE#
A10
Ground supply
GND
24
23
22
21
20
19
18
17
9
9
OE#
A10
S#
DQ8
DQ7
DQ6
DQ5
DQ4
10
10
11
11
12
13
S#
12
13
14
A0
21
20
19
18
17
DQ8
DQ7
DQ6
DQ5
DQ4
DQ1
DQ2
DQ3
GND
14
15
16
15
16
GND
Outline 32P2M-A (FP)
Outline
32P3Y-J (RT)
32P3Y-H (TP)
1
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
FUNCTION
When setting S# at a high lev el, the chips are in a non-
selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high-
impedance state, allowing OR-tie with other chips. Setting
the OE# at a high lev el,the output stage is in a high-
impedance state, and the data bus contention problem in
the write cycle is eliminated.
The power supply current is reduced as low as 0.4µA
(25°C, ty pical), and the memory data can be held at +2V
power supply, enabling battery back-up operation during
power f ailure or poer-down operation in the non-selected
mode.
The M5M5408BFP,TP,RT is organized as 524,288-words
by 8-bit. These dev ices operate on a single +5.0V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
ref resh, and makes it usef ul.
A write operation is executed during the S# low and W#
low ov erlap time. The address(A0~A18) must be set up
bef ore the write cycle
A read operation is executed by setting W# at a high
lev el and OE# at a low lev el while S# are in an activ e
state (S#=L).
FUNCTION TABLE
Function
DQ
S#
W#
OE#
Mode
Address input
Icc
High-impedance
Data input (D)
Data output (Q)
High-impedance
Stan
Data input / output
H
L
L
X
L
X
X
L
Non selection
Write
Chip select input
H
Write control input
Output inable input
Power supply
W )
Read
L
H
H
Read
E# (OE)
Vcc
note: "H" and "L" in this table mean VIH and VIL, respe
"X" in this table should be "H" or "L".
GND
Ground supply
BLOCK DIAGRAM
8
A4
A5
7
13
14
15
17
18
19
20
21
DQ1
DQ2
DQ3
6
A6
A7
5
ARRAY
A12
4
3
DQ4
DQ5
DQ6
DQ7
DQ8
A14
A16
4288 WORDS
x 8 BITS
2
30
1
A17
A18
A15
31
23
A10
A11
25
26
27
28
CLOCK
GENERATOR
A9
A8
W#
29
A13
22 S#
24
OE#
12
11
10
9
A0
A1
VCC
(5V)
32
16
A2
A3
GND
(0V)
2
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Conditions
With respect to GND
With respect to GND
With respect to GND
Ta=25°C
Ratings
Units
V
Supply v oltage
V
cc
VI
-0.3* ~ +7
-0.3* ~ Vcc + 0.3
0 ~ Vcc
Input v oltage
Output v oltage
Power dissipation
Operating
VO
Pd
700
mW
Standard
0 ~ +70
Ta
°C
°C
temperature
I-v ersion
-40 ~ +85
-65 ~ +150
Storage temperature
Tstg
_
* -3.0V in case of AC (Pulse width < 30ns)
DC ELECTRICAL CHARACTERISTICS
( V, unless otherwise noted)
mits
p.
Symbol
Parameter
Conditions
Units
Max
High-lev el input v oltage
Vcc+0.3V
0.8
*
.4
VIH
Low-lev el input v oltage
High-level output voltage 1
High-level output voltage 2
VIL
VOH1
VOH2
V
IOH= -1mA
IOH= -0.1mA
IOL=2mA
Vcc-0.5V
VOL
0.4
±1
Low-lev el output v oltage
II
VI =0 ~ Vcc
Input leakage current
Output leakage current
Activ e supply current
(CMOS-lev el input)
µA
±1
S# = VIH o
IO
f=10MHz
f=1MHz
f=10MHz
f=1MHz
Standard
I-v ersion
-
-
-
_
50
25
80
30
90
40
30
60
S# < 0
Icc1
Oth.2V
mA
Activ e supply current
(TTL-lev el input)
60
30
Icc2
Icc3
Icc4
-
-
-
Stand by supply cu
(CMOS-lev el inpu
1.0
1.0
µA
her inputs=0~Vcc
Stand by supply current
(TTL-lev el input)
her inputs= 0 ~ Vcc
-
mA
-
3
_
* -3.0V in case of AC (Pulse width <30ns)
Note 1: Direction f or current flowing intIC is indicated as positiv e (no mark).
Note 2: Ty pical v alues are sampled at Vcc=5.0V and Ta=25°C,
and are not 100% tested.
CAPACITANCE
(Vcc=5.0V±10%, unless otherwise noted)
Limits
Units
Parameter
Symbol
Conditions
Ty p.
Min
Max
8
CI
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
pF
CO
10
3
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(Vcc=5.0V±10%, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply v oltage
Input pulse
5.0V
VIH=2.4V,VIL=0.6V (-70H, -70HI)
VIH=3.0V,VIL=0V (-55H, -55HI )
1.8kW
DQ
990W
Input rise time and f all time
Reference lev el
5ns
CL
VOH=VOL=1.5V
Transition is measured ±500mV f rom
steady state voltage f or ten and tdis.
Fig.1, CL=100pF (-70H, -70HI)
CL=30pF (-55H, -55HI )
Output loads
L Includes scope and jig capacitance
CL=5pF (f or ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Units
-5
0HI
Parameter
Read cy cle time
Symbol
Max
tCR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
0
20
70
70
35
25
25
Address access time
Chip select access time
ta(S)
ta(OE)
tdis(S)
tdis(OE)
ten(S)
ten(OE)
tV(A)
Output enable access time
Output disable time after S
Output disable time aft
Output enable time
Output enable ti
Data v alid ti
10
5
10
5
10
(3) WRITE CYCLE
Limits
Symbol
-55H, -55HI
-70H, -70HI
Parameter
Units
Min
Max
Min
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write cy cle time
Write pulse width
tCW
55
40
0
70
50
0
tw(W)
tsu(A)
Address set up time
tsu(A-WH)
tsu(S)
Address set up time with respect to W# high
Chip select set up time
Data set up time
50
50
25
0
60
60
30
0
tsu(D)
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
Write recov ery time
0
0
Output disable time after W# low
Output disable time after OE# high
Output enable time af ter W# high
Output enable time af ter OE# low
20
20
25
25
ten(W)
5
5
5
5
ten(OE)
4
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~18
ta(A)
ta(S)
tv (A)
S#
(Note3)
(Note3)
s (S)
(Note3)
ta (OE)
OE#
ten (OE)
(Note3)
W# = "H" lev el
DQ1~8
ten (S)
DATA
Write cycle
( W# control mod
A0~18
tsu (S)
(Note4)
S#
(Note3)
(Note3)
tsu (A-WH)
OE#
W#
tw (W)
tsu (A)
trec (W)
(Note4)
ten(OE)
ten (W)
tdis (W)
tdis(OE)
DATA IN
STABLE
DQ1~8
(Note 6)
tsu (D) th (D)
5
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Write cycle (S# control mode)
tCW
A0~18
tsu (A)
S#
tsu (S)
trec (W)
(Note4)
(Note5)
W#
(Note4)
(Note3)
(Note3)
tsu (D)
(Note 6)
D
DQ1~8
Note 3: Hatching indicates the state is "don't
Note 4: A Write occurs during the ov erlap .
Note 5: If W goes low simultaneously ut remains in the high impedance state.
Note 6: Don't apply inv erted phase pin is in output mode.
6
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Units
Symbol
Vcc (PD)
VI (S#)
Parameter
Test conditions
Min
2
Ty pical
Max
-
-
Power down supply v oltage
Chip select input S#
_
-
-
Vcc(PD) > 2.2V
V
2.2
_
_
Vcc(PD)
-
2.2V > Vcc(PD) > 2.0V
-
30
-
-
-
85°C
70°C
40°C
I-version
Vcc=3.0V,
15
3
Standard,
I-version
-
1*
_
S# > Vcc-0.2V,
Icc (PD)
Power down supply current
µA
Other input
=0 ~ Vcc
1
0.4*
0.4*
Standard
I-version
0~ 25°C
-40~ 25
1
*Ty picand are not 100% tested.
(2) TIMING REQUIREMENTS
Limits
Ty p
Symbol
Parameter
Units
Min
Max
tsu (PD)
trec (PD)
Power down set up time
0
5
ns
ms
Power down recov ery time
(3) TIMING DIAGRAM
S# control mode
Vcc
4.5V
trec (PD)
2.2V
2.2V
_
S# > Vcc - 0.2V
S#
7
MITSUBISHI LSIs
revision-2.0e, Feb.12, 2002
M5M5408BFP/TP/RT
4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM
Revision History
Revision No.
K0.1e
History
Date
The first edition
1) Icc3 limit revised
2) Icc(PD) limit revised
Jul.30, '98 Preliminary
Jun. 3, '99 Preliminary
K0.2e
3) Icc1,Icc2 conditions revised
K0.3e
1) Vcc Level in the Block Diagram revised Jun.28, '99 Preliminary
2) Icc3 limit (typ) revised
K1.0e
K1.1e
The first product version
Product lineup revised
99 ---
---
2.0e
1) Product lineup revised
2 ---
2) Symbol notations revis
S -> S#, W-> W#, O
3) Icc(PD) conditio
8
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