M5M5V208AKV [RENESAS]
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM; 2097152 - BIT （ 262144 -字×8位）的CMOS静态RAM
| 型号： | M5M5V208AKV |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM |
| 文件： | 总8页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
DESCRIPTION
The M5M5V208AKV is low voltage 2-Mbit static RAMs organized
as 262,144-words by 8-bit, fabricated by high-performance 0.25µm
CMOS technology.
PIN CONFIGURATION (TOP VIEW)
The M5M5V208AKV is suitable for memory applications where a
simple interfacing , battery operating and battery backup are the
important design objectives.
The M5M5V208AKV is packaged in 32-pin 8mm x 13.4mm
sTSOP packages which is a high reliability and high density surface
mount device.
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
OE
A10
S1
3
A8
4
A13
W
DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1
A0
5
6
S2
7
A15
VCC
A17
A16
A14
A12
A7
8
M5M5V208AKV
9
10
11
12
13
14
15
16
FEATURES
Power supply current
Access
time
(max)
Type name
Active
(max)
stand-by
(max)
A6
A1
A5
A4
A2
30µA
A3
55ns
70ns
M5M5V208AKV-55HI
M5M5V208AKV-70HI
35mA
(Vcc=3.6V)
(10MHz)
0.3µA
7mA
Outline 32P3K-B(KV)
(Vcc=3.0V
TYPICAL)
(1MHz)
• Single 2.7 ~3.6V power supply
• No clock, No refresh
• Directly TTL compatible : All inputs and outputs
• Easy memory expansion and power down by S1,S2
• Data hold on +2V power supply
• Three-state outputs : OR - tie capability
• OE prevents data contention in the I/O bus
• Common data I/O
• Package
2
M5M5V208AKV ············· 32pin 8 X 13.4 mm sTSOP
1
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
FUNCTION
The operation mode of the M5M5V208AKV series are determined by a
combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
When setting S1 at a high level or S2 at a low level, the chip are in a
non-selectable mode in which both reading and writing are disabled. In
this mode, the output stage is in a high- impedance state, allowing OR-
tie with other chips and memory expansion by S1 and S2. The power
supply current is reduced as low as the stand-by current which is
specified as ICC3 or ICC4, and the memory data can be held at +2V power
supply, enabling battery back-up operation during power failure or
power-down operation in the non-selected mode.
A write cycle is executed whenever the low level W overlaps with the low
level S1 and the high level S2. The address must be set up before the
write cycle and must be stable during the entire cycle. The data is
latched into a cell on the trailing edge of W,S1 or S2,whichever occurs
first,requiring the set-up and hold time relative to these edge to be
maintained. The output enable input OE directly controls the output
stage. Setting the OE at a high level, the output stage is in a high-
impedance state, and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting W at a high level and OE at a low
level while S1 and S2 are in an active state(S1=L,S2=H).
FUNCTION TABLE
S1 S2
W
X
X
L
OE
X
Mode
DQ
ICC
X
H
L
L
Stand-by
Non selection High-impedance
X
H
X
Non selection High-impedance Stand-by
Din
Dout
Active
Active
Active
X
Write
Read
L
L
H
H
H
H
L
H
High-impedance
Note 1: "H" and "L" in this table mean VIH and VIL, respectively.
2: "X" in this table should be "H" or "L".
BLOCK DIAGRAM
DQ1
21
22
23
A2 18
A3 17
DQ2
DQ3
262144 WORDS
X 8 BITS
( 1024 ROWS
X256 COLUMNS
X 8 BLOCKS )
A4 16
DATA
INPUTS/
OUTPUTS
25
26
27
DQ4
DQ5
DQ6
A5 15
A6 14
13
12
A7
28
29
DQ7
DQ8
A12
11
10
9
A14
A16
A17
ADDRESS
INPUTS
CLOCK
GENERATOR
A15
A13
7
4
A8
3
2
1
A9
WRITE
A11
CONTROL
INPUT
5
W
30
6
S1
S2
A1
CHIP
SELECT
INPUTS
19
A0 20
31
A10
OUTPUT
ENABLE
INPUT
32 OE
8
VCC
GND
(0V)
24
2
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Ratings
Conditions
Unit
Supply voltage
Input voltage
V
VI
V
V
cc
- 0.5*~4.6
- 0.5*~Vcc + 0.3
0~Vcc
With respect to GND
V
VO
Output voltage
Ta=25°C
Pd
Power dissipation
Operating temperature
Storage temperature
700
mW
°C
°C
Topr
Tstg
- 40~85
- 65~150
* -3.0V in case of AC ( Pulse width £ 30ns )
(Ta= -40~85°C, Vcc=2.7~3.6V, unless otherwise noted)
Test conditions
DC ELECTRICAL CHARACTERISTICS
Limits
Symbol
VIH
Parameter
Unit
V
Min
Typ
Max
Vcc
+ 0.3
High-level input voltage
2.0
Low-level input voltage
V
V
VIL
-0.3*
2.4
0.6
VOH1
High-level output voltage 1
IOH= - 0.5mA
Vcc
- 0.5
VOH2
High-level output voltage 2
IOH= - 0.05mA
V
VOL
II
Low-level output voltage
Input current
IOL= 2mA
VI=0~Vcc
0.4
±1
V
µA
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
IO
Output current in off-state
µA
mA
±1
10MHz
1MHz
10MHz
1MHz
S1 £ 0.2V,S2 ³ Vcc-0.2V
other inputs £ 0.2V or ³ Vcc-0.2V, Output-open
28
5
30
7
Active supply current
(CMOS-level input)
ICC1
33
5
35
7
Active supply current
(TTL-level input)
S1=VIL,S2=VIH,
other inputs=VIH or VIL,Output-open
ICC2
ICC3
mA
µA
mA
0.3
2
~25°C
~40°C
~70°C
~85°C
1) S2 £ 0.2V, other inputs=0 ~ VCC
2) S1 ³ VCC - 0.2V, S2 ³ VCC - 0.2V
other inputs=0 ~ VCC
5
Stand-by current
10
30
1) S1=VIH, other inputs=VIL or VIH
2) S2=VIL, other inputs=VIL or VIH
ICC4
Stand-by current
0.33
* -3.0V in case of AC ( Pulse width£ 30ns )
(Ta=- 40~85°C, unless otherwise noted)
CAPACITANCE
Limits
Typ
Parameter
Symbol
Test conditions
Unit
Min
Max
8
pF
pF
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz
CI
10
CO
Note 3: Direction for current flowing into an IC is positive (no mark).
4: Typical value is Vcc = 3V, Ta = 25°C
3
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS (Ta=- 40~85°C, unless otherwise noted )
1TTL
(1) MEASUREMENT CONDITIONS
................................
............
VCC
2.7~3.6V
DQ
Input pulse level
VIH=2.2V,VIL=0.4V
5ns
CL
....
Input rise and fall time
including
scope and JIG
..............
Reference level
VOH=VOL=1.5V
Fig.1, CL=30pF
..................
Output loads
CL=5pF (for ten,tdis)
Transition is measured ± 500mV from steady
state voltage. (for ten,tdis)
Fig.1 Output load
(2) READ CYCLE
Limits
Symbol
Parameter
-55HI
-70HI
Min
70
Unit
Max
Max
Min
55
tCR
Read cycle time
Address access time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ta(A)
55
55
55
30
20
20
20
70
70
70
35
25
25
25
ta(S1)
ta(S2)
ta(OE)
tdis(S1)
tdis(S2)
tdis(OE)
ten(S1)
Chip select 1 access time
Chip select 2 access time
Output enable access time
Output disable time after S1 high
Output disable time after S2 low
Output disable time after OE high
Output enable time after S1 low
Output enable time after S2 high
Output enable time after OE low
Data valid time after address
10
10
ten(S2)
ten(OE)
tV(A)
10
5
10
5
10
10
(3) WRITE CYCLE
Limits
Symbol
Parameter
-55HI
Max
-70HI
Unit
Min
Min
70
55
0
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
Write cycle time
Write pulse width
55
45
0
tw(W)
Address setup time
tsu(A)
tsu(A-WH)
tsu(S1)
tsu(S2)
tsu(D)
Address setup time with respect to W
Chip select 1 setup time
Chip select 2 setup time
Data setup time
50
50
50
25
0
65
65
65
30
0
th(D)
Data hold time
trec(W)
tdis(W)
tdis(OE)
ten(W)
ten(OE)
Write recovery time
0
0
Output disable time from W low
Output disable time from OE high
Output enable time from W high
20
20
25
25
5
5
5
5
Output enable time from OE low
4
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS
Read cycle
tCR
A0~17
ta(A)
tv (A)
ta (S1)
S1
S2
(Note 5)
(Note 5)
(Note 5)
(Note 5)
tdis (S1)
tdis (S2)
ta (S2)
ta (OE)
ten (OE)
OE
(Note 5)
(Note 5)
tdis (OE)
ten (S1)
ten (S2)
DQ1~8
DATA VALID
W = "H" level
Write cycle (W control mode)
tCW
A0~17
tsu (S1)
S1
S2
(Note 5)
(Note 5)
(Note 5)
(Note 5)
tsu (S2)
tsu (A-WH)
OE
tsu (A)
tw (W)
trec (W)
W
tdis (W)
ten(OE)
ten (W)
tdis (OE)
DATA IN
STABLE
DQ1~8
tsu (D)
th (D)
5
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
Write cycle ( S1 control mode)
tCW
A0~17
tsu (A)
trec (W)
tsu (S1)
S1
S2
(Note 5)
(Note 5)
(Note 5)
(Note 7)
W
(Note 6)
(Note 5)
th (D)
tsu (D)
DATA IN
STABLE
DQ1~8
Write cycle (S2 control mode)
tCW
A0~17
S1
(Note 5)
(Note 5)
tsu (A)
tsu (S2)
trec (W)
S2
W
(Note 7)
(Note 6)
(Note 5)
(Note 5)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~8
Note 5: Hatching indicates the state is "don't care".
6: Writing is executed while S2 high overlaps S1 and W low.
7: When the falling edge of W is simultaneously or prior to the falling edge of S1
or rising edge of S2, the outputs are maintained in the high impedance state.
8: Don't apply inverted phase signal externally when DQ pin is output mode.
6
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS(Ta= -40~85°C, unless otherwise noted)
Limits
Typ
Symbol
Parameter
Power down supply voltage
Test conditions
Unit
Min
2.0
2.0
Max
0.2
VCC (PD)
VI (S1)
V
V
Chip select input S1
Chip select input S2
VI (S2)
V
~25°C
~40°C
~70°C
~85°C
0.3
1
3
VCC = 3.0V
1) S2 £ 0.2V, other inputs = 0~Vcc
2) S1 ³ VCC-0.2V, S2 ³ VCC-0.2V,
other inputs = 0~Vcc
µA
ICC (PD)
Power down supply current
8
24
(2) TIMING REQUIREMENTS (Ta=-40~85°C, unless otherwise noted )
Limits
Typ
Symbol
Parameter
Test conditions
Unit
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
Power down recovery time
ns
5
ms
(3) POWER DOWN CHARACTERISTICS
S1 control mode
VCC
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
S1
S1 ³ VCC - 0.2V
Note 9: On the power down mode by controlling S1,the input level of S2 must be S2 ³ Vcc - 0.2V or
S2 £ 0.2V. The other pins(Address,I/O,WE,OE) can be in high impedance state.
S2 control mode
VCC
2.7V
2.7V
S2
tsu (PD)
trec (PD)
0.2V
0.2V
S2 £ 0.2V
7
Revision-A0.5
RENESAS LSIs
M5M5V208AKV
2097152-BIT(262144-WORD BY 8-BIT)CMOS STATIC RAM
Nippon Bldg.,6-2,Otemachi 2-chome,Chiyoda-ku,Tokyo,100-0004 Japan
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8
REJ03C0104 © 2003 Renesas Technology Corp.
New publication, effective Aug 2003.
Specifications subject to change without notice
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