M5M5V216ATP-70HI [RENESAS]
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM; 2097152 - BIT （ 131072 - WORD 16位） CMOS静态RAM
| 型号： | M5M5V216ATP-70HI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| 文件： | 总9页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FEATURES
DESCRIPTION
The M5M5V216A is a f amily of low v oltage 2-Mbit static RAMs
organized as 131,072-words by 16-bit, f abricated by Mitsubishi's
high-perf ormance 0.25µm CMOS technology .
Single +2.7~+3.6V power supply
Small stand-by current: 0.3µA(3V,ty p.)
No clocks, No ref resh
The M5M5V216A is suitable f or memory applications where a
simple interf acing , battery operating and battery backup are the
important design objectiv es.
M5M5V216ATP, RT are packaged in a 44-pin 400mil thin small
outline package. M5M5V216ATP (normal lead bend ty pe package)
, M5M5V216ART (rev erse lead bend ty pe package) , both ty pes
are v ery easy to design a printed circuit board.
Data retention supply v oltage=2.0V to 3.6V
All inputs and outputs are TTL compatible.
Easy memory expansion by S , BC1 and BC2
Common Data I/O
Three-state outputs: OR-tie capability
OE prev ents data contention in the I/O bus
Process technology: 0.25µm CMOS
Package: 44 pin 400mil TSOP (II)
PART NAME TABLE
Activ e
current
Icc1
Stand-by current Icc(PD), Vcc=3.0V
ty pical *
25°C 40°C 25°C 40°C 70°C 85°C
Version,
Operating
Access
time
Power
Part name
Ratings (max.)
Supply
temperature
max.
(3.0V, ty p.)
45mA
(10MHz)
5mA
M5M5V216ATP,RT -55HI
M5M5V216ATP,RT -70HI
55ns
70ns
I-version
-40 ~ +85°C
8µA
24µA
2.7 ~ 3.6V
0.3µA 1µA 1µA 3µA
(1MHz)
* "ty pical" parameter is sampled, not 100% tested.
PIN CONFIGURATION
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
A5
A6
A7
OE
A5
A6
A7
OE
Pin
Function
A0 ~ A16
Address input
BC2
BC1
BC2
BC1
S
DQ1
DQ2
DQ3
DQ4
Vcc
S
DQ1 ~ DQ16 Data input / output
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ16
DQ15
DQ14
DQ13
GND
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
Chip select input
Write control input
Output inable input
Lower By te (DQ1 ~ 8)
Upper By te(DQ9 ~ 16)
Power supply
S
9
10
11
12
13
14
15
16
17
18
19
20
21
22
W
OE
BC1
GND
DQ5
DQ6
DQ7
DQ8
WE
GND
DQ5
DQ6
DQ7
DQ8
WE
A16
A15
A14
A13
A12
DQ12
DQ11
DQ10
DQ9
NC
DQ12
DQ11
DQ10
DQ9
NC
BC2
Vcc
A16
A8
A8
Ground supply
GND
A15
A9
A9
Outline: TP : 44P3W - H
A14
A10
A10
A13
A11
A11
RT : 44P3W - J
A12
NC
NC
NC: No Connection
1
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
FUNCTION
The M5M5V216ATP,RT is organized as 131,072-words by
16-bit. These dev ices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
ref resh, and makes it usef ul.
The operation mode are determined by a combination of
the dev ice control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenev er the low lev el W
ov erlaps with the low lev el BC1 and/or BC2 and the low
lev el S. The address(A0~A16) must be set up bef ore the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W at a high lev el
and OE at a low lev el while BC1 and/or BC2 and S are in
an activ e state(S=L).
When setting BC1 at the high lev el and other pins are in
an activ e stage , upper-by te are in a selesctable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high lev el and other pins are in an activ e stage, lower-
byte are in a selectable mode and upper-by te are in a
non-selectable mode.
When setting BC1 and BC2 at a high lev el or S at a high
lev el, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply current is reduced as low as 0.3µA(25 C,
ty pical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
FUNCTION TABLE
Mode
DQ1~8 DQ9~16
Icc
S BC1 BC2
W
X
X
L
OE
X
Non selection
Non selection
H
L
L
L
L
L
L
L
L
L
L
X
H
L
X
H
H
H
H
L
High-Z High-Z Standby
High-Z High-Z Standby
X
Write
Read
Din
High-Z Activ e
X
L
L
H
H
L
Dout High-Z Activ e
High-Z High-Z Activ e
L
H
X
L
H
H
H
L
Write
Read
High-Z Din
Activ e
Activ e
L
H
H
L
High-Z Dout
L
H
X
L
High-Z High-Z Activ e
L
Write
Read
Din
Din
Activ e
Activ e
Note : "H" and "L" in this table mean VIH or VIL.
"X" in this table should be "H" or "L".
BLOCK DIAGRAM
L
L
H
H
Dout
Dout
L
L
H
High-Z High-Z Activ e
A0
DQ
1
A1
MEMORY ARRAY
DQ
8
131072 WORDS
x 16 BITS
A15
A16
-
DQ
9
CLOCK
GENERATOR
DQ
16
S
BC1
BC2
W
Vcc
GND
OE
2
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Supply v oltage
Input v oltage
Conditions
Ratings
Units
V
With respect to GND
With respect to GND
With respect to GND
V
cc
VI
-0.5* ~ +4.6
-0.5* ~ Vcc + 0.5
0 ~ Vcc
Output v oltage
Power dissipation
VO
Pd
700
mW
ºC
Ta=25ºC
Operating
I-v ersion
(-HI)
Ta
- 40 ~ +85
temperature
Storage temperature
Tstg
- 65 ~ +150
ºC
<
* -3.0V in case of AC (Pulse width 30ns)
=
( Vcc=2.7 ~ 3.6V, unless otherwise noted)
Limits
DC ELECTRICAL CHARACTERISTICS
Parameter
Conditions
Units
V
Symbol
Min
Max
Ty p
High-lev el input v oltage
VIH
VIL
Vcc+0.3V
0.6
2.0
Low-lev el input v oltage
High-level output voltage 1
High-level output voltage 2
-0.3 *
VOH1
VOH2
VOL
II
IOH= -0.5mA
IOH= -0.05mA
IOL=2mA
2.4
Vcc-0.5V
0.4
±1
Low-lev el output v oltage
Input leakage current
Output leakage current
VI =0 ~ Vcc
µA
±1
BC1 and BC2=VIH or S=VIH or OE=VIH, VI/O=0 ~ Vcc
IO
<
<
0.2V
=
BC1 and BC2 0.2V ,
=
S
f= 10MHz
f= 1MHz
-
-
-
45
5
60
15
60
15
2
Activ e supply current
( AC,MOS lev el )
>
<
other inputs 0.2V or
Vcc-0.2V
Icc1
=
=
Output - open (duty 100%)
mA
BC1 and BC2=VIL , S=VIL
other pins =VIH or VIL
Output - open (duty 100%)
f= 10MHz
f= 1MHz
Activ e supply current
( AC,TTL lev el )
45
5
Icc2
Icc3
-
-
~ +25ºC
~ +40ºC
~ +70ºC
~ +85ºC
>
0.3
1
< 1 > S Vcc - 0.2V,other inputs = 0 ~ Vcc
=
Stand by supply current
( AC,MOS lev el )
-
5
>
< 2 >
BC1 and BC2 Vcc - 0.2V
=
µA
<
S
0.2V Other inputs=0~Vcc
10
30
-
-
-
-
=
Stand by supply current
( AC,TTL lev el )
BC1 and BC2=VIH , S=VIL or S=VIH
Other inputs= 0 ~ Vcc
Icc4
-
mA
-
0.5
<
Note 1: Direction for current flowing into IC is indicated as positive (no mark)
Note 2: Typical value is for Vcc=3.0V and Ta=25ºC
* -3.0V in case of AC (Pulse width 30ns)
=
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
CAPACITANCE
Limits
Units
Parameter
Symbol
Conditions
Ty p
Min
Max
8
CI
Input capacitance
Output capacitance
VI=GND, VI=25mVrms, f =1MHz
VO=GND,VO=25mVrms, f =1MHz
pF
CO
10
3
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
(Vcc=2.7 ~ 3.6V, unless otherwise noted)
AC ELECTRICAL CHARACTERISTICS
(1) TEST CONDITIONS
Supply v oltage
2.7V~3.6V
1TTL
Input pulse
VIH=2.4V,VIL=0.4V
5ns
DQ
Input rise time and f all time
CL
VOH=VOL=1.5V
Reference lev el
Output loads
Transition is measured ±500mV f rom
steady state voltage.(f or ten,tdis)
Fig.1,CL=30pF
Including scope and
jig capacitance
Fig.1 Output load
CL=5pF (for ten,tdis)
(2) READ CYCLE
Limits
55HI
70HI
Units
Parameter
Symbol
Min
55
Max
Min
70
Max
tCR
ta(A)
ta(S)
ta(BC1)
ta(BC2)
ta(OE)
Read cy cle time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
55
55
30
20
20
20
20
70
70
70
70
35
25
25
25
25
Address access time
Chip select access time
By te control 1 access time
By te control 2 access time
Output enable access time
tdis(S)
Output disable time after S high
Output disable time after BC1 high
Output disable time after BC2 high
Output disable time after OE high
Output enable time af ter S low
Output enable time af ter BC1 low
Output enable time af ter BC2 low
Output enable time af ter OE low
Data v alid time after address
tdis(BC1)
tdis(BC2)
tdis(OE)
ten(S)
ten(BC1)
ten(BC2)
ten(OE)
tV(A)
10
10
10
5
10
10
10
5
10
10
(3) WRITE CYCLE
Limits
55HI
70HI
Units
Parameter
Symbol
Min
55
45
0
50
50
50
50
25
0
Max
Min
70
55
0
65
65
65
65
30
0
Max
Write cy cle time
Write pulse width
Address setup time
Address setup time with respect to W
By te control 1 setup time
By te control 2 setup time
Chip select setup time
Data setup time
Data hold time
Write recov ery time
tCW
tw(W)
tsu(A)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(A-WH)
tsu(BC1)
tsu(BC2)
tsu(S)
tsu(D)
th(D)
trec(W)
tdis(W)
tdis(OE)
ten(W)
0
0
20
20
25
25
Output disable time from W low
Output disable time from OE high
Output enable time f rom W high
Output enable time f rom OE low
5
5
5
5
ten(OE)
4
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
(4)TIMING DIAGRAMS
Read cycle
tCR
A0~16
ta(A)
tv (A)
ta(BC1)
ta(BC2)
or
BC1
and / or
BC2
(Note3)
(Note3)
(Note3)
(Note3)
tdis (BC1) or tdis (BC1)
ta(S)
S
tdis (S)
(Note3)
ta (OE)
ten (OE)
OE
(Note3)
tdis (OE)
W = "H" lev el
DQ1~16
ten (BC1)
ten (BC2)
ten (S)
VALID DATA
Write cycle
( W control mode )
tCW
A0~16
tsu (BC1) or tsu(BC2)
BC1
and / or
BC2
(Note3)
(Note3)
tsu (A)
(Note3)
tsu (S)
S
tsu (A-WH)
(Note3)
OE
W
tw (W)
trec (W)
tdis (W)
ten(OE)
ten (W)
tdis(OE)
DATA IN
STABLE
DQ1~16
tsu (D) th (D)
5
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
Write cycle (BC control mode)
tCW
A0~16
trec (W)
tsu (BC1) or
tsu (BC2)
tsu (A)
BC1
and / or
BC2
S
(Note3)
(Note5)
(Note3)
(Note3)
W
(Note4)
tsu (D)
(Note3)
th (D)
DATA IN
STABLE
DQ1~16
Write cycle (S control mode)
tCW
A0~16
BC1
and / or
(Note4)
BC2
(Note3)
tsu (S)
(Note3)
trec (W)
tsu (A)
S
(Note5)
W
(Note4)
(Note3)
(Note3)
tsu (D)
th (D)
DATA IN
STABLE
DQ1~16
Note 3: Hatching indicates the state is "don't care".
Note 4: A Write occurs during S low , ov erlaps BC1 and/or BC2 low and W low.
Note 5: When the f alling edge of W is simultaneously or priorto the f alling edge of BC1 and/or BC2 or the falling edge of S,
the outputs are maintained in the high impedance state.
Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.
6
MITSUBISHI LSIs
revision-03, 14.Jan.'03
M5M5V216ATP,RT
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
POWER DOWN CHARACTERISTICS
(1) ELECTRICAL CHARACTERISTICS
Limits
Units
Symbol
Parameter
Test conditions
Ty p
Min
2.0
2.0
2.0
Max
Power down supply voltage
Byte control input BC1 & BC2
Chip select input S
Vcc (PD)
VI (BC)
VI (S)
V
V
V
µA
µA
µA
µA
Vcc=3.0V
~ +85ºC
-
-
24
8
-
-
>
1) S Vcc - 0.2V
=
~ +70ºC
~ +40ºC
Power down
supply current
Icc (PD)
other inputs=0~Vcc
-
-
3
>
1
0.3
2) BC1 and BC2 Vcc - 0.2V
=
<
S
0.2V, other inputs=0~Vcc
-40 ~ +25ºC
=
1
Note 7: Typical parameter of Icc(PD) indicates the value for the
center of distribution at 3.0V, and not 100% tested.
(2) TIMING REQUIREMINTS
Limits
Symbol
Parameter
Units
Test conditions
Ty p
Min
0
Max
tsu (PD)
trec (PD)
Power down set up time
ns
ms
5
Power down recov ery time
(3) TIMING DIAGRAM
Note8: On the BC# control mode, the lev el of S# must be f ixed at S# > Vcc-0.2V or S# < 0.2V.
BC control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
BC1
BC2
>
BC1 , BC2 Vcc - 0.2V
=
S control mode
Vcc
2.7V
2.7V
tsu (PD)
trec (PD)
2.2V
2.2V
>
S
S Vcc - 0.2V
=
7
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better
and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due
consideration to safety when making your circuit designs, with appropriate measures such as (i)
placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not convey any
license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric
Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any
third-party's rights, originating in the use of any product data, diagrams, charts, programs,
algorithms, or circuit application examples contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs
and algorithms represents information on products at the time of publication of these materials, and
are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or
an authorized Mitsubishi Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss
rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various
means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Mitsubishi
Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from
the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a
device or system that is used under circumstances in which human life is potentially at stake. Please
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor
when considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for further details on these materials or the products contained therein.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明