MC-2311100F9-B10-BQ1 [RENESAS]
MC-2311100F9-B10-BQ1;
| 型号： | MC-2311100F9-B10-BQ1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | MC-2311100F9-B10-BQ1 |
| 文件： | 总46页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-2311100
MCP (MULTI-CHIP PACKAGE) MOBILE SPECIFIED RAM AND SRAM
16M-BIT CMOS MOBILE SPECIFIED RAM AND 4M-BIT CMOS SRAM
Description
The MC-2311100 is a stacked type MCP (Multi-Chip Package) of 16,777,216 bits (1,048,576 words by 16 bits) Mobile
specified RAM and 4,194,304 bits (BYTE mode : 524,288 words by 8 bits, WORD mode : 262,144 words by 16 bits)
SRAM.
The MC-2311100 is packaged in a 61-pin TAPE FBGA.
General Features
• Supply voltage : VCCm / VCCs = 2.6 to 3.0 V
• Wide operating temperature : TA = −20 to +70 °C
• Output Enable input for easy application
• Byte data control : /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
Mobile specified RAM Features
• Memory organization : 1,048,576 words by 16 bits
• Fast access time : tAA = 80, 90, 100 ns (MAX.)
• Supply current : At operating : 35 mA (MAX.)
At Standby Mode 1 : 100 µA (MAX.) Normal standby (Memory cell data hold valid)
At Standby Mode 2 : 10 µA (MAX.) Memory cell data hold invalid
• Chip Enable inputs : /CEm
• Standby Mode input : MODE
SRAM Features
• Memory organization : 524,288 words × 8 bits (BYTE mode)
262,144 words × 16 bits (WORD mode)
• Fast access time : tAA = 70 ns (MAX.)
• Supply current :At operating : 40 mA (MAX.)
At Standby Mode : 7 µA (MAX.)
• Low VCC data retention: 1.0 V (MIN.)
• Two Chip Enable inputs: /CE1s, CE2s
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M15432EJ1V0DS00 (1st edition)
Date Published November 2001 NS CP (K)
Printed in Japan
The mark ★ shows major revised points.
2001
©
MC-2311100
Ordering Information
Part number
Access time ns (MAX.)
Mobile specified RAM
Package
SRAM
70
MC-2311100F9-B80-BQ1
MC-2311100F9-B90-BQ1Note
MC-2311100F9-B10-BQ1
80
90
61-pin TAPE FBGA (9 × 7)
70
100
70
Note Under development
Preliminary Data Sheet M15432EJ1V0DS
2
MC-2311100
Pin Configuration
/xxx indicates active low signal.
61-pin TAPE FBGA (9 × 7)
Top View
Bottom View
8
7
6
5
4
3
2
1
A B C D E F G H J K
K J H G F E D C B A
Top View
A
B
C
D
E
F
G
H
J
K
8
7
6
5
4
3
2
1
NC
A15
A12
NC
A13
V
SS
A16
SA
NC
V
SS
NC
A11
A8
A14
A10
I/O15 I/O7 I/O14
I/O13 I/O12 I/O5
A19
A9
I/O6
/WE MODE NC
I/O4
I/O3
V
CC
m
CIOs
I/O11
NC
/LB
CE2
/UB
NC
VCCs
A18
A17
I/O1
I/O9 I/O10 I/O2
A7
A6
A3
A5
A2
A4
A1
VSS
/OE
I/O0
I/O8
NC
NC
A0
/CE1s /CEm
NC
Common Pins
A0 - A19 : Address inputs
I/O0 - I/O15 : Data inputs / outputs
Mobile specified RAM Pins
/CEm : Chip Enable
MODE : Standby mode select
VCCm : Supply Voltage
/OE
: Output Enable
: Write Enable
: Byte data select
: Ground
/WE
SRAM Pins
/LB, /UB
VSS
NC Note
/CE1s
CE2s
SA
: Chip Enable
: No Connection
: Chip Enable
: Address input (A18)
CIOs
VCCs
: Selects 8-bit or 16-bit mode
: Supply Voltage
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to 5. Package Drawing for the index mark.
Preliminary Data Sheet M15432EJ1V0DS
3
MC-2311100
Block Diagram
V
CCs
V
SS
/CE1S
CE2S
CIO
S
4 M-bit SRAM
524,288 words by 8 bits
262,144 words by 16 bits
SA(A18)
A0 - A19
A0 - A17
V
CCm
V
SS
I/O0 - I/O15
/WE
/OE
/LB
16 M-bit Mobile Specified RAM
(1,048,576 words by 16 bits)
/UB
A0 - A19
/CEm
MODE
Preliminary Data Sheet M15432EJ1V0DS
4
MC-2311100
CONTENTS
1. Bus Operations ...................................................................................................................................................6
2. Mobile specified RAM.........................................................................................................................................7
2.1 Initialization.................................................................................................................................................7
2.2 Standby Mode.............................................................................................................................................8
2.2.1 Standby Mode State Machine ................................................................................................................8
3. Electrical Specifications.....................................................................................................................................9
4. Timing Charts....................................................................................................................................................19
5. Package Drawing ..............................................................................................................................................42
6. Recommended Soldering Conditions .............................................................................................................43
Preliminary Data Sheet M15432EJ1V0DS
5
MC-2311100
1. Bus Operations
Table 1-1. Bus Operations
Mobile specified
RAM
Operation
SRAM
Common
/CS MODE /CE1 CE2 CIOs
/OE
x
/WE
x
/LB
x
/UB
x
I/O0 to I/O7
Hi-Z
I/O8 to I/O15
Full standby
Standby Mode1
H
H
H
x
x
L
x
x
Hi-Z
Standby Mode2
L
H
x
L
H
Output disable
L
H
L
x
H
H
x
x
Mobile specified RAM
/CS MODE /CE1 CE2 CIOs
Note1
/OE
L
/WE
H
/LB
L
/UB
L
I/O0 to I/O7
DOUT
DOUT
Hi-Z
I/O8 to I/O15
DOUT
WORD Read
(1M x 16)
L
H
x
Lower byte read
Upper byte read
L
H
L
Hi-Z
H
H
L
DOUT
Hi-Z
Output disable
WORD Write
H
L
Hi-Z
(1M x 16)
x
L
DIN
DIN
Lower byte write
Upper byte write
L
H
L
DIN
Hi-Z
H
H
Hi-Z
DIN
Write impossible
H
Hi-Z
Hi-Z
SRAM
/CS MODE /CE1 CE2 CIOs
/OE
L
/WE
H
/LB
L
/UB
L
I/O0 to I/O7
DOUT
DOUT
DOUT
Hi-Z
I/O8 to I/O15
Hi-Z
BYTE Read
WORD Read
(512K x 8)
Note2
L
H
L
(256K x 16)
H
L
L
DOUT
Hi-Z
Lower byte read
Upper byte read
L
H
L
H
H
L
DOUT
Hi-Z
Output disable
BYTE Write
L
H
x
x
x
L
x
x
x
H
L
Hi-Z
(512K x 8)
Note2
L
H
L
DIN
Hi-Z
WORD Write
(256K x 16)
H
L
L
DIN
DIN
Lower byte write
Upper byte write
L
H
L
DIN
Hi-Z
H
Hi-Z
DIN
Caution Other operations except for indicated in this table are inhibited.
Notes 1. SRAM should be Standby.
2. Mobile specified RAM should be Standby.
Remarks 1. H : VIH, L : VIL, × : VIH or VIL
2. MODE pin must be fixed to H during active operation.
Preliminary Data Sheet M15432EJ1V0DS
6
MC-2311100
2. Mobile specified RAM
2.1 Initialization
The MC-2311100 is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any
signal toggling.
(2) After the wait time, read operation must be performed at least 8 times. After that, it can be normal operation.
Figure 2-1. Initialization Timing Chart
V
CCm (MIN.)
VCCm
Address (Input)
V
V
IH (MIN.)
IH (MIN.)
MODE (Input)
/CEm (Input)
t
RC
t
CP
Power On Wait Time
200
Read Operation 8 times
Normal
Operation
µ
s
Cautions 1. Following power application, make MODE and /CEm high level during the wait time interval.
2. Following power application, make MODE high level during the wait time and eight read
operations.
3. The read operation must satisfy the specs described on page 14 (Read Cycle (Mobile specified
RAM)).
4. The address is don’t care (VIH or VIL) during read operation.
5. Read operation must be executed with toggled the /CEm pin.
6. To prevent bus contention, it is recommended to set /OE to high level. However, do not input
data to the I/O pins if /OE is low level during a read operation.
Preliminary Data Sheet M15432EJ1V0DS
7
MC-2311100
2.2 Standby Mode
Standby Mode 1 and Standby Mode 2 differ as shown below.
Table 2-1. Standby Mode Characteristics
Memory Cell Data Hold Standby Supply Current (µA)
Standby Mode
Mode 1
Valid
100 (ISB1)
10 (ISB2)
Mode 2
Invalid
2.2.1 Standby Mode State Machine
(1) From Active
To shift from this state to Standby Mode 1, change /CEm from VIL to VIH.
To shift from this state to Standby Mode 2, change /CEm from VIL to VIH and change MODE from VIH to VIL.
(2) From Standby Mode 1
To shift from this state to Active, change /CEm from VIH to VIL.
To shift from this state to Standby Mode 2, change MODE from VIH to VIL.
(3) From Standby Mode 2
When shifting from this state to the Active state or to Standby Mode 1, it is necessary to set MODE to VIH and
perform a Dummy Read operation 8 times after waiting for 200 µs, in the same way as at power application.
Refer to Figure 4-16. Standby Mode 2 entry and recovery Timing Chart (Mobile specified RAM).
After shifting to Active state, change /CEm to VIL.
After shifting to Standby Mode 1, do not change either MODE or /CEm.
Figure 2-2. Standby Mode State Machine
Power On
/CEm = VIH
,
MODE = VIH
Wait 200
µ
s,
Dummy Read (8 times)
Initial State
/CEm = VIL
/CEm = VIH
MODE = VIH
,
MODE = VIH
Active
/CEm = VIH
,
/CEm = VIH
,
MODE = VIH
MODE = VIL
/CEm = VIL
,
MODE = VIH
/CEm = VIH, MODE = VIL
Standby Mode 1
Standby Mode 2
Preliminary Data Sheet M15432EJ1V0DS
8
MC-2311100
3. Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
Condition
Rating
–0.5Note to +4.0
Unit
VCCm with respect to VSS
V
VCCs
VT
with respect to VSS
with respect to VSS
–0.5 to +4.0
Input / Output voltage
–0.5 Note to VCCm, VCCs + 0.4 (4.0 V MAX.)
V
Ambient operation temperature
Storage temperature
TA
–20 to +70
°C
°C
Tstg
–55 to +125
Note –1.0 V (MIN.) (Pulse width ≤ 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Common
Parameter
Supply voltage
Symbol
VCCm, VCCs
TA
Condition
Condition
MIN.
2.6
TYP.
TYP.
MAX.
3.0
Unit
V
Ambient operation temperature
–20
+70
°C
Mobile specified RAM
Parameter
Symbol
VIH
MIN.
MAX.
Unit
V
High level input voltage
Low level input voltage
VCCm x 0.8
VCCm + 0.3
VCCm x 0.2
−0.3 Note
VIL
V
Note –0.5 V (MIN.) (Pulse width ≤ 30 ns)
SRAM
Parameter
High level input voltage
Low level input voltage
Symbol
VIH
Condition
MIN.
TYP.
MAX.
VCCs + 0.4
+0.5
Unit
V
2.4
−0.3 Note
VIL
V
Note –0.5 V (MIN.) (Pulse width ≤ 30 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Output capacitance
Symbol
CIN
Test condition
MIN.
TYP.
MAX.
TBD
TBD
Unit
pF
VIN = 0 V
COUT
VOUT = 0 V
pF
Remarks 1. VIN : Input voltage, VOUT : Output voltage
2. These parameters are not 100% tested.
Preliminary Data Sheet M15432EJ1V0DS
9
MC-2311100
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Mobile specified RAM
Parameter
Input leakage current
I/O leakage current
Symbol
Test condition
MIN.
–1.0
–1.0
TYP.
MAX.
+1.0
+1.0
Unit
µA
µA
I
LI
V
IN = 0 V to VCCm
I/O = 0 V to VCCm, /CEm = VIH or
I
LO
V
/WE = VIL or /OE = VIH
Operating supply current
ICCA
ISB1
ISB2
/CEm = VIL, Minimum cycle time, II/O = 0 mA
/CEm ≥ VCCm − 0.2 V, MODE ≥ VCCm − 0.2 V
/CEm ≥ VCCm − 0.2 V, MODE ≤ 0.2 V
35
100
10
mA
Standby supply Standby Mode 1
µA
current
Standby Mode 2
High level output voltage
Low level output voltage
VOH IOH = –0.5 mA
VCCm × 0.8
V
V
VOL
IOL = 1 mA
VCCm × 0.2
SRAM
Parameter
Symbol
ILI
Test condition
MIN.
–1.0
–1.0
TYP.
MAX.
+1.0
+1.0
Unit
µA
Input leakage current
I/O leakage current
VIN = 0 V to VCCs
ILO
VI/O = 0 V to VCCs, /CE1s = VIH or
CE2s = VIL or /WE = VIL or /OE = VIH
/CE1s = VIL, CE2s = VIH,
µA
Operating supply current
ICCA1
ICCA2
ICCA3
–
–
–
40
10
8
mA
II/O = 0 mA, Minimum cycle time
/CE1s = VIL, CE2s = VIH,
II/O = 0 mA, Cycle time = ∞
/CE1s ≤ 0.2 V, CE2s ≥ VCCs – 0.2 V,
II/O = 0 mA, Cycle time = 1 µs
VIH ≥ VCCs – 0.2 V, VIL ≤ 0.2 V
/CE1s = VIH or CE2s = VIL or /LB = /UB = VIH
/CE1s ≥ VCCs − 0.2 V, CE2s ≥ VCCs − 0.2 V
CE2s ≤ 0.2 V
Standby supply current
ISB
–
0.6
7
mA
ISB1
ISB2
ISB3
0.5
0.5
0.5
µA
7
/LB = /UB ≥ VCCs − 0.2 V, /CE1s ≤ 0.2 V,
CE2s ≥ VCCs − 0.2 V
7
High level output voltage
Low level output voltage
VOH
VOL
IOH = –0.5 mA
2.4
V
V
IOL = 1.0 mA
0.4
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless products classification.
Preliminary Data Sheet M15432EJ1V0DS
10
MC-2311100
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Mobile specified RAM
Input Waveform (Rise and Fall Time ≤ 5 ns)
V m
CCm x 0.8 V
CC
V
VCCm/2 V
Test points
VCCm/2 V
V
CCm x 0.2 V
V
SS
5 ns
Output Waveform
V
CCm/2 V
Test points
VCCm/2 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure.
CL: 50 pF
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW)
ZO =
50 Ω
I/O (Output)
CL
50 Ω
VCCm/2 V
Preliminary Data Sheet M15432EJ1V0DS
11
MC-2311100
SRAM
Input Waveform (Rise and Fall Time ≤ 5 ns)
V
CCs x 0.9 V
CCs x 0.1 V
VCCs/2 V
Test points
VCCs/2 V
V
Output Waveform
V
CCs/2 V
Test points
VCCs/2 V
Output Load
1 TTL + 50 pF
Preliminary Data Sheet M15432EJ1V0DS
12
MC-2311100
/CEm, /CEs Timing
Parameter
Symbol
tCCR
Test Condition
MIN.
0
TYP.
MAX.
Unit
ns
Note
/CEm, /CEs recover time
Preliminary Data Sheet M15432EJ1V0DS
13
MC-2311100
Read Cycle (Mobile specified RAM)
Parameter
Symbol MC-2311100-B80
MC-2311100-B90
MC-2311100-B10
Unit
Notes
MIN.
80
MAX.
10,000
10,000
10
MIN.
90
MAX.
10,000
10,000
15
MIN.
110
110
MAX.
10,000
10,000
20
Read cycle time
tRC
tRC1
tSKEW
tCP
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
Identical address read cycle time
Address skew time
80
90
/CEm pulse width
10
10
10
Address access time
tAA
80
80
35
35
90
90
40
40
100
100
50
4
5
/CEm access time
tACS
tOE
/OE to output valid
/LB, /UB to output valid
tBA
50
Output hold from address change
/CEm to output in low impedance
/OE to output in low impedance
/LB, /UB to output in low impedance
/CEm to output in high impedance
/OE to output in high impedance
/LB, /UB to output in high impedance
tOH
10
10
5
10
10
5
10
10
5
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
5
5
5
25
25
25
25
25
25
25
25
25
Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 µs). tRC
indicates the time from the /CEm low level input point or address determination point, whichever is later, to
the /CEm high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for tRC.
1) Time from address determination point to /CEm high level input point
2) Time from address determination point to next address change start point
3) Time from /CEm low level input point to next address change start point
4) Time from /CEm low level input point to /CEm high level input point
(address access)
(address access)
(/CEm access)
(/CEm access)
2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing
continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CEm low level. Perform
settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less.
3. tSKEW indicates the following three types of time depending on the condition.
1) When switching /CEm from high level to low level, tSKEW is the time from the /CEm low level input point
until the next address is determined.
2) When switching /CEm from low level to high level, tSKEW is the time from the address change start point to
the /CEm high level input point.
3) When /CEm is fixed to low level, tSKEW is the time from the address change start point until the next
address is determined.
Since specs are defined for tSKEW only when /CEm is active, tSKEW is not subject to limitations when /CEm is
switched from high level to low level following address determination, or when the address is changed after
/CEm is switched from low level to high level.
4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only
tACS is satisfied during /CEm access (refer to 3) of Note 1).
5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is
satisfied if /UB and /LB become active before /OE.
Preliminary Data Sheet M15432EJ1V0DS
14
MC-2311100
Write Cycle (Mobile specified RAM)
Parameter
Symbol MC-2311100-B80
MC-2311100-B90
MC-2311100-B10
Unit
Notes
MIN.
80
MAX.
10,000
10,000
10
MIN.
90
MAX.
10,000
10,000
15
MIN.
110
110
MAX.
10,000
10,000
20
Write cycle time
tWC
tWC1
tSKEW
tCW
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
4
Identical address write cycle time
Address skew time
80
90
/CEm to end of write
40
30
35
30
20
10
0
50
35
45
35
20
10
0
60
40
55
40
20
10
0
/LB, /UB to end of write
Address valid to end of write
Write pulse width
tBW
tAW
tWP
Write recovery time
tWR
tCP
5
/CEm pulse width
Address setup time
tAS
Byte write hold time
tBWH
tDW
20
20
0
20
25
0
20
30
0
Data valid to end of write
Data hold time
tDH
/OE to output in low impedance
/WE to output in high impedance
/OE to output in high impedance
Output active from end of write
tOLZ
tWHZ
tOHZ
tOW
5
5
5
25
25
25
25
25
25
5
5
5
Notes 1. One write cycle (tWC) must satisfy the minimum value (tWC(MIN.)) and the maximum value (tWC(MAX.) = 10 µs).
tWC indicates the time from the /CEm low level input point or address determination point, whichever is after,
to the /CEm high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for tWC.
1) Time from address determination point to /CEm high level input point
2) Time from address determination point to next address change start point
3) Time from /CEm low level input point to next address change start point
4) Time from /CEm low level input point to /CEm high level input point
2. The identical address read cycle time (tWC1) is the cycle time of one write cycle when performing continuous
write operations with the address fixed and /CEm low level, changing /LB and /UB at the same time, and
toggling /WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that
the sum (tWC) of the identical address write cycle times (tWC1) is 10 µs or less.
3. tSKEW indicates the following three types of time depending on the condition.
1) When switching /CEm from high level to low level, tSKEW is the time from the /CEm low level input point until
the next address is determined.
2) When switching /CEm from low level to high level, tSKEW is the time from the address change start point to
the /CEm high level input point.
3) When /CEm is fixed to low level, tSKEW is the time from the address change start point until the next
address is determined.
Since specs are defined for tSKEW only when /CEm is active, tSKEW is not subject to limitations when /CEm is
switched from high level to low level following address determination, or when the address is changed after
/CEm is switched from low level to high level.
Preliminary Data Sheet M15432EJ1V0DS
15
MC-2311100
4. Definition of write start and write end
/CEm
/WE
L
/LB, /UB
L
Status
Write start pattern 1
Write start pattern 2
Write start pattern 3
Write end pattern 1
Write end pattern 2
H to L
If /WE, /LB, /UB are low level, time when /CEm changes
from high level to low level
L
L
L
L
H to L
L
If /CEm, /LB, /UB are low level, time when /WE changes
from high level to low level
L
L to H
L
H to L
L
If /CEm, /WE are low level, time when /LB or /UB
changes from high level to low level
If /CEm, /WE, /LB, /UB are low level, time when /WE
changes from low level to high level
L to H
When /CEm, /WE, /LB, /UB are low level, time when
/LB or /UB changes from low level to high level
5. Definition of write end recovery time (tWR)
1) Time from write end to address change start point, or from write end to /CEm high level input point
2) When /CEm, /LB, /UB are low level and continuously written to the identical address, time from /WE high
level input point to /WE low level input point
3) When /CEm, /WE are low level and continuously written to the identical address, time from /LB or /UB
high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier.
4) When /CEm is low level and continuously written to the identical address, time from write end to point at
which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest.
Read Write Cycle (Mobile specified RAM)
Parameter
Symbol MC-2311100-B80
MC-2311100-B90
MC-2311100-B10
Unit
Notes
1, 2
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read write cycle time
Byte write setup time
Byte read setup time
tRWC
tBWS
tBRS
10,000
10,000
10,000
ns
ns
ns
20
20
20
20
20
20
Notes 1. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB
following a read using /LB with /CEm low level, or when a write is performed using /LB following a read
using /UB.
2. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1) is 10 µs or less when a read is performed at the identical address using /UB
following a write using /LB with /CEm low level, or when a read is performed using /LB following a write
using /UB.
Preliminary Data Sheet M15432EJ1V0DS
16
MC-2311100
Read Cycle (SRAM)
Parameter
Symbol
MC-2311100-B80, B90, B10
Unit
Notes
MIN.
70
MAX.
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
70
70
35
70
1
/CE1s access time
tCO1
tCO2
tOE
CE2s access time
/OE to output valid
/LB, /UB to output valid
tBA
Output hold from address change
/CE1s to output in low impedance
CE2s to output in low impedance
/OE to output in low impedance
/LB, /UB to output in low impedance
/CE1s to output in high impedance
CE2s to output in high impedance
/OE to output in high impedance
/LB, /UB to output in high impedance
tOH
10
10
10
0
tLZ1
tLZ2
tOLZ
tBLZ
tHZ1
tHZ2
tOHZ
tBHZ
2
10
25
25
25
25
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Write Cycle (SRAM)
Parameter
Symbol
MC-2311100-B80, B90, B10
Unit
Note
MIN.
70
55
55
55
55
0
MAX.
Write cycle time
tWC
tCW1
tCW2
tBW
tAW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CE1s to end of write
CE2s to end of write
/LB, /UB to end of write
Address valid to end of write
Address setup time
Write pulse width
tWP
tWR
tDW
tDH
50
0
Write recovery time
Data valid to end of write
Data hold time
30
0
/WE to output in high impedance
Output active from end of write
tWHZ
tOW
25
1
5
Note 1. The output load is 1TTL + 50 pF.
Preliminary Data Sheet M15432EJ1V0DS
17
MC-2311100
Low VCC Data Retention Characteristics (TA = –20 to +70°C)
Parameter
Symbol
Test Condition
Unit
V
MC-2311100-B80, B90, B10
MIN.
1.0
TYP.
MAX.
3.6
Data retention supply voltage
VCCDR1
VCCDR2
VCCDR3
/CE1s ≥ VCCs − 0.2 V,CE2s ≥ VCCs − 0.2 V
CE2s ≤ 0.2 V
1.0
3.6
/LB = /UB ≥ VCCs − 0.2 V,
1.0
3.6
/CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
VCCs = 1.5 V, /CE1s ≥ VCCs − 0.2 V,
CE2s ≥ VCCs − 0.2 V or CE2s ≤ 0.2 V
VCCs = 1.5 V, CE2s ≤ 0.2 V
Data retention supply current
ICCDR1
0.3
3.0
µA
ICCDR2
ICCDR3
0.3
0.3
3.0
3.0
VCCs = 1.5 V, /LB = /UB ≥ VCCs − 0.2 V,
/CE1s ≤ 0.2 V, CE2s ≥ VCCs − 0.2 V
tCDR
tR
0
ns
ns
Chip deselection to data retention mode
Operation recovery time
Note
tRC
Note
tRC : Read cycle time
Preliminary Data Sheet M15432EJ1V0DS
18
MC-2311100
4. Timing Charts
Figure 4-1. Alternating Mobile specified RAM to SRAM Timing Chart
/CEm (Input)
/CE1s (Input)
CE2s (Input)
t
CCR
t
CCR
Preliminary Data Sheet M15432EJ1V0DS
19
MC-2311100
Figure 4-2. Read Cycle Timing Chart 1 (Mobile specified RAM)
t
SKEW
t
SKEW
Address (Input)
/CEm (Input)
t
CP
t
RC
t
CP
t
ACS
t
CHZ
t
CLZ
/OE (Input)
t
OE
t
OHZ
t
OLZ
/LB, /UB (Input)
t
BA
t
BHZ
OH
t
BLZ
t
Hi-Z
I/O (Output)
Data out
t
SKEW
t
SKEW
t
RC
Address (Input)
/CEm (Input)
t
CP
t
CP
t
AA
t
CHZ
t
CLZ
/OE (Input)
t
OE
t
OHZ
t
OLZ
/LB, /UB (Input)
t
BA
t
BHZ
t
BLZ
Hi-Z
I/O (Output)
Data out
Caution If the address is changed using a value that is either lower than the minimum value or higher than
the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
Preliminary Data Sheet M15432EJ1V0DS
20
Figure 4-3 Read Cycle Timing Chart 2 (Mobile specified RAM)
t
SKEW
t
RC
t
SKEW
t
RC
t
SKEW
tSKEW
Address (Input)
/CEm (Input)
t
CP
t
RC
t
RC
t
CP
tRC
t
AA
tAA
t
AA
t
CLZ
t
CHZ
t
ACS
t
CHZ
t
ACS
tCHZ
t
CLZ
tCLZ
/OE (Input)
/LB, /UB (Input)
I/O (Output)
t
OE
t
OLZ
t
OHZ
t
BA
tBHZ
t
BHZ
t
OH
t
BA
t
BHZ
tBA
t
OH
t
BLZ
tOH
t
BLZ
tBLZ
Hi-Z
Data out
Data out
Data out
Data out
Data out
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle
time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
Figure 4-4. Read Cycle Timing Chart 3 (Mobile specified RAM)
t
SKEW
tRC
t
SKEW
t
RC
t
SKEW
t
RC
t
SKEW
tRC
t
SKEW
tRC
Address (Input)
t
AA
t
AA
t
AA
/CEm (Input)
/OE (Input)
t
CLZ
t
OE
t
OE
tOE
t
t
OHZ
t
t
OHZ
tOHZ
t
OLZ
t
OLZ
t
OLZ
t
BA
tBA
/LB (Input)
BHZ
BHZ
t
OH
t
OH
t
BLZ
tBLZ
Hi-Z
I/O0 - 7 (Output)
Data out
Data out
t
BA
tBA
/UB (Input)
t
BHZ
t
BHZ
t
OH
t
OH
t
BLZ
tBLZ
Hi-Z
I/O8 - 15 (Output)
Data out
Data out
Caution If the address is changed using a value that is either lower than the minimum value or higher than the maximum value for the read cycle
time (tRC), none of the data can be guaranteed.
Remark In read cycle, /WE should be fixed to High.
MC-2311100
Figure 4-5. Read Cycle Timing Chart 4 (Mobile specified RAM)
t
SKEW
t
SKEW
t
RC
Address (Input)
/CEm (Input)
Note
Note
RC1
t
RC1
t
t
AA
t
OE
t
OE
t
OLZ
t
OLZ
/OE (Input)
t
OHZ
t
OHZ
t
BA
t
BA
t
BLZ
t
BLZ
/LB, /UB (Input)
t
BHZ
t
BHZ
Hi-Z
Hi-Z
Data out
Data out
I/O (Output)
Caution If the address is changed using a value that is either lower than the minimum value or higher than
the maximum value for the read cycle time (tRC), none of the data can be guaranteed.
Note To perform a continuous read toggling /OE, /UB, and /LB with /CEm low level at an identical address, make
settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less.
Remark In read cycle, /WE should be fixed to High.
Preliminary Data Sheet M15432EJ1V0DS
23
MC-2311100
Figure 4-6. Write Cycle Timing Chart 1 (Mobile specified RAM)
t
WC
tWC
t
SKEW
t
SKEW
Address (Input)
/CEm (Input)
t
AW
t
AW
t
CP
t
WP
t
AS
tWP
t
WR
tWR
/WE (Input)
t
AS
t
BW
t
BW
/LB, /UB (Input)
t
DW
tDH
t
DW
tDH
Hi-Z
Hi-Z
I/O (Intput)
Data in
Data in
t
SKEW
t
WC
tWC
t
SKEW
tSKEW
Address (Input)
/CEm (Input)
t
CW
t
CW
t
CP
t
WP
tWP
t
WR
tWR
/WE (Input)
t
BW
t
BW
/LB, /UB (Input)
t
DW
tDH
t
DW
tDH
Hi-Z
Hi-Z
I/O (Intput)
Data in
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
24
MC-2311100
Figure 4-7. Write Cycle Timing Chart 2 (Mobile specified RAM)
t
SKEW
t
WC
t
SKEW
t
WC
t
SKEW
t
WC
t
SKEW
tSKEW
Address (Input)
t
AW
tCP
t
AW
/CEm (Input)
/WE (Input)
t
CW
t
WR
tWR
t
WP
t
WP
t
WP
t
WR
t
AS
t
AW
t
OW
t
t
WHZ
/OE (Input)
t
OLZ
OHZ
t
DW
t
DH
t
DW
t
DH
t
DW
tDH
Hi-Z
Hi-Z
Hi-Z
Indefinite
data out
I/O (Intput / Output)
Data in
Data in
Data in
Hi-Z
Hi-Z
t
SKEW
t
SKEW
t
WC
Address (Input)
/CEm (Input)
Note
Note
WC1
t
WC1
t
t
AS
t
WP
t
WR
t
WP
tWR
/WE (Input)
t
BW
/LB, /UB (Input)
t
DW
t
DH
t
DW
tDH
Hi-Z
Hi-Z
Hi-Z
I/O (Intput)
Data in
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CEm low level and a continuous write operation toggling
/WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs
or less.
Remarks 1. Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
2. When /WE is at Low, the I/O pins are always high impedance. When /WE is at High, read operation is
executed. Therefore /OE should be at High to make the I/O pins high impedance.
Preliminary Data Sheet M15432EJ1V0DS
25
MC-2311100
Figure 4-8. Write Cycle Timing Chart 3 (/CEm Controlled) (Mobile specified RAM)
Address (Input)
/CEm (Input)
t
WC
t
WC
t
AS
t
WR
t
WR
t
CW
t
AS
t
CW
/WE (Input)
/LB, /UB (Input)
I/O (Intput)
t
DW
t
DH
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Data in
Data in
Address (Input)
/CEm (Input)
t
WC
t
WC
t
AS
t
WR
t
WR
t
CW
t
AS
t
CW
/WE (Input)
/LB, /UB (Input)
I/O (Intput)
t
DW
t
DH
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Data in
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
26
MC-2311100
Figure 4-9. Write Cycle Timing Chart 4 (/LB, /UB Controlled 1) (Mobile specified RAM)
t
WC
t
WC
t
SKEW
t
SKEW
Address (Input)
/CEm (Input)
t
AW
t
AW
t
WP
/WE (Input)
t
AS
t
BW
t
AS
t
BW
t
WR
t
WR
/LB, /UB (Input)
t
DW
t
DH
t
DW
t
DH
Hi-Z
Hi-Z
I/O (Intput)
Data in
Data in
t
SKEW
t
WC
t
WC
t
SKEW
Address (Input)
/CEm (Input)
t
AW
t
CW
t
WP
/WE (Input)
t
AS
t
BW
t
WR
t
AS
t
BW
t
WR
/LB, /UB (Input)
t
DW
t
DH
t
DW
t
DH
Hi-Z
Hi-Z
I/O (Intput)
Data in
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
27
MC-2311100
Figure 4-10. Write Cycle Timing Chart 5 (/LB, /UB Controlled 2) (Mobile specified RAM)
t
SKEW
t
SKEW
t
WC
Address (Input)
Note
WC1
Note
WC1
t
t
/CEm (Input)
/WE (Input)
t
WP
t
AS
t
BW
t
WR
t
BW
t
WR
/LB, /UB (Input)
I/O (Intput)
t
DW
t
DH
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Data in
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CEm low level and a continuous write operation toggling
/WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs
or less.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
28
MC-2311100
Figure 4-11. Write Cycle Timing Chart 6 (/LB, /UB Independent Controlled 1) (Mobile specified RAM)
t
WC
Address (Input)
Note
Note
t
WC1
t
WC1
/CEm (Input)
/WE (Input)
/LB (Input)
/UB (Input)
t
CW
WP
t
t
AS
t
BW
t
WR
t
WR
t
BW
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data in
I/O0 - 7 (Intput)
I/O8 - 15 (Intput)
t
DW
t
DH
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Note If /LB and /UB are changed at the same time with /CEm low level and a continuous write operation toggling
/WE is performed, make settings so that the sum (tWC) of the identical address write cycle time (tWC1) is 10 µs
or less.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
29
MC-2311100
Figure 4-12. Write Cycle Timing Chart 7 (/LB, /UB Independent Controlled 2) (Mobile specified RAM)
Address (Input)
/CEm (Input)
t
WC
t
CW
t
CW
t
WP
t
WP
/WE (Input)
/LB (Input)
t
BW
t
WR
t
AS
t
BWH
t
WR
t
BW
/UB (Input)
t
AS
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O0 - 7 (Intput)
Data in
t
DW
t
DH
I/O8 - 15 (Intput)
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the write cycle time (tWC), none of the data can be guaranteed.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
30
MC-2311100
Figure 4-13. Read Write Cycle Timing Chart 1 (/LB, /UB Independent Controlled 1) (Mobile specified RAM)
t
RWC
Address (Input)
Note
Note
t
RC1
t
WC1
t
AA
/CEm (Input)
/WE (Input)
/LB (Input)
/UB (Input)
t
ACS
t
WP
t
BWS
t
WR
t
BW
t
CLZ
t
BLZ
t
BHZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O0 - 7 (Output)
I/O8 - 15 (Intput)
Data out
t
DW
t
DH
Data in
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a
read using /LB with /CEm low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
31
MC-2311100
Figure 4-14. Read Write Cycle Timing Chart 2 (/LB, /UB Independent Controlled 2) (Mobile specified RAM)
t
RWC
Address (Input)
Note
WC1
Note
t
t
RC1
t
CW
/CEm (Input)
/WE (Input)
/LB (Input)
/UB (Input)
t
WR
t
WP
t
BW
t
AS
t
BRS
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O0 - 7 (Input)
Data in
t
BA
t
BHZ
t
BLZ
I/O8 - 15 (Output)
Data out
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a
read using /LB with /CEm low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
32
MC-2311100
Figure 4-15. Read Write Cycle Timing Chart 3 (/LB, /UB Independent Controlled 3) (Mobile specified RAM)
t
RWC
Address (Input)
Note
WC1
Note
RC1
t
t
t
CW
/CEm (Input)
/WE (Input)
/LB (Input)
/UB (Input)
t
WR
t
WP
t
AS
t
BW
t
DW
t
DH
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I/O0 - 7 (Input)
Data in
t
BA
t
BHZ
t
BLZ
I/O8 - 15 (Output)
Data out
Cautions 1. During address transition, at least one of pins /CEm, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. If the address is changed using a value that is either lower than the minimum value or higher
than the maximum value for the identical address read cycle time (tRC1) and the identical
address write cycle time (tWC1), none of the data can be guaranteed.
Note Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following a
read using /LB with /CEm low level, or when a write is performed using /LB following a read using /UB.
Remark Write operation is done during the overlap time of a Low /CEm, /WE, /LB and/or /UB.
Preliminary Data Sheet M15432EJ1V0DS
33
MC-2311100
Figure 4-16. Standby Mode 2 entry and recovery Timing Chart (Mobile specified RAM)
Address (Input)
MODE (Input)
/CEm (Input)
t
RC
t
CP
t
CM
Standby
Mode 2
Wait Time 200 µs
Read Operation 8 times
Normal
Operation
Parameter
Symbol
tCM
MIN.
0
MAX.
Unit
ns
Note
/CEm High to MODE Low
Cautions 1. Make MODE and /CEm high level during the wait time.
2. Make MODE high level during the wait time and eight read operations.
3. The read operation must satisfy the specs described on page 34 (Read Cycle (Mobile specified
RAM)).
4. The read operation address can be either VIH or VIL.
5. Perform reading by toggling /CEm.
6. To prevent bus contention, it is recommended to set /OE to high level. However, do not input
data to the I/O pins if /OE is low level during a read operation.
Preliminary Data Sheet M15432EJ1V0DS
34
MC-2311100
Figure 4-17. Read Cycle Timing Chart (SRAM)
tRC
Address (Input)
/CE1s (Input)
tAA
tOH
tCO1
tLZ1
tHZ1
CE2s (Input)
/OE (Input)
tCO2
tLZ2
tHZ2
tOHZ
tOE
tOLZ
/LB, /UB (Input)
I/O (Output)
tBA
tBHZ
tBLZ
High impedance
Data out
Remark In read cycle, /WE should be fixed to high level.
Preliminary Data Sheet M15432EJ1V0DS
35
MC-2311100
Figure 4-18. Write Cycle Timing Chart 1 (/WE Controlled) (SRAM)
tWC
Address (Input)
tCW1
/CE1 (Input)
CE2 (Input)
tCW2
tAW
tAS
tWP
tWR
/WE (Input)
tBW
/LB, /UB (Input)
tOW
tWHZ
tDW
tDH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and
a high level CE2s.
2. If /CE1s changes to low level at the same time or after the change of /WE to low level, or if
CE2s changes to high level at the same time or after the change of /WE to low level, the I/O
pins will remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Preliminary Data Sheet M15432EJ1V0DS
36
MC-2311100
Figure 4-19. Write Cycle Timing Chart 2 (/CE1s Controlled) (SRAM)
t
WC
Address (Input)
t
AS
t
CW1
/CE1s (Input)
CE2s (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a high level
CE2s.
Preliminary Data Sheet M15432EJ1V0DS
37
MC-2311100
Figure 4-20. Write Cycle Timing Chart 3 (CE2s Controlled) (SRAM)
tWC
Address (Input)
/CE1s (Input)
CE2s (Input)
tCW1
tAS
tCW2
tAW
tWP
tBW
tWR
/WE (Input)
/LB, /UB (Input)
tDW
tDH
High impedance
High
Data in
I/O (Input)
impedance
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a high level
CE2s.
Preliminary Data Sheet M15432EJ1V0DS
38
MC-2311100
Figure 4-21. Write Cycle Timing Chart 4 (/LB, /UB Controlled) (SRAM)
t
WC
Address (Input)
t
t
CW1
CW2
/CE1s (Input)
CE2s (Input)
t
AW
t
WP
t
WR
/WE (Input)
t
AS
t
BW
/LB, /UB (Input)
I/O (Input)
t
DW
t
DH
High impedance
High
Data in
impedance
Cautions 1. During address transition, at least one of pins /CE1s, CE2s, /WE should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CE1s, /WE, /LB and/or /UB, and a high level
CE2s.
Preliminary Data Sheet M15432EJ1V0DS
39
MC-2311100
Figure 4-22. Data Retention Timing Chart 1 (/CE1s Controlled) (SRAM)
t
CDR
Data retention mode
t
R
VCCs
V
CC (MIN.)
/CE1
VIH (MIN.)
V
CCDR (MIN.)
/CE1 ≥ VCCs – 0.2 V
VIL (MAX.)
V
SS
Remark On the data retention mode by controlling /CE1s, the input level of CE2s must be ≥ VCC − 0.2 V or ≤ 0.2 V.
The other pins (Address, I/O, /WE, /OE, /LB, /UB) can be in high impedance state.
Figure 4-23. Data Retention Timing Chart 2 (CE2s Controlled) (SRAM)
t
CDR
Data retention mode
t
R
VCCs
V
CC (MIN.)
V
IH (MIN.)
V
CCDR (MIN.)
CE2
VIL (MAX.)
CE2 ≤ 0.2 V
V
SS
Remark On the data retention mode by controlling CE2s, The other pins (/CE1s, Address, I/O, /WE, /OE, /LB, /UB)
can be in high impedance state.
Preliminary Data Sheet M15432EJ1V0DS
40
MC-2311100
Figure 4-24. Data Retention Timing Chart 3 (/LB, /UB Controlled) (SRAM)
t
CDR
Data retention mode
t
R
VCCs
V
CC (MIN.)
/LB, /UB
VIH (MIN.)
V
CCDR (MIN.)
/LB, /UB ≥ VCCs – 0.2 V
VIL (MAX.)
V
SS
Remark On the data retention mode by controlling /LB and /UB, the input level of /CE1s and CE2s must be
≥ VCC − 0.2 V or ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
Preliminary Data Sheet M15432EJ1V0DS
41
MC-2311100
5. Package Drawing
61-PIN TAPE FBGA (9x7)
E
ZD
ZE
B
w
S B
8
7
6
5
4
3
2
1
A
D
K J H G F E D C B A
INDEX MARK
w
S A
A
A2
y1
S
S
e
A1
y
S
φ
b
φ x M S AB
ITEM MILLIMETERS
7.0±0.1
D
E
9.0±0.1
0.2
w
1.1±0.1
A
A1
A2
e
0.26±0.05
0.84
0.8
b
0.45±0.05
0.08
x
y
0.1
y1
ZD
ZE
0.1
0.7
0.8
Preliminary Data Sheet M15432EJ1V0DS
42
MC-2311100
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the MC-2311100.
Types of Surface Mount Device
MC-2311100F9-B80-BQ1 : 61-pin TAPE FBGA (9 × 7)
MC-2311100F9-B90-BQ1 : 61-pin TAPE FBGA (9 × 7)
MC-2311100F9-B10-BQ1 : 61-pin TAPE FBGA (9 × 7)
Preliminary Data Sheet M15432EJ1V0DS
43
MC-2311100
[MEMO]
Preliminary Data Sheet M15432EJ1V0DS
44
MC-2311100
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M15432EJ1V0DS
45
MC-2311100
•
The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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