NP48N055KLE [RENESAS]
48A, 55V, 0.024ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB, MP-25ZK, TO-263, 3 PIN;![NP48N055KLE](http://pdffile.icpdf.com/pdf2/p00256/img/icpdf/NP48N055KLE-_1546756_icpdf.jpg)
型号: | NP48N055KLE |
厂家: | ![]() |
描述: | 48A, 55V, 0.024ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB, MP-25ZK, TO-263, 3 PIN 开关 脉冲 晶体管 |
文件: | 总8页 (文件大小:79K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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DATA SHEET
MOS FIELD EFFECT TRANSISTOR
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
SWITCHING
N-CHANNEL POWER MOS FET
DESCRIPTION
ORDERING INFORMATION
These products are N-channel MOS Field Effect Transistor
designed for high current switching applications.
PART NUMBER
NP48N055CLE
NP48N055DLE
NP48N055ELE
NP48N055KLE
PACKAGE
TO-220AB
TO-262
FEATURES
TO-263 (MP-25ZJ)
TO-263 (MP-25ZK)
• Channel temperature 175 degree rated
• Super low on-state resistance
RDS(on)1 = 17 mΩ MAX. (VGS = 10 V, ID = 24 A)
RDS(on)2 = 21 mΩ MAX. (VGS = 5 V, ID = 24 A)
• Low Ciss: Ciss = 1970 pF TYP.
• Built-in gate protection diode
★
(TO-220AB)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC)
VDSS
VGSS
ID(DC)
ID(pulse)
PT
55
±20
±48
±140
1.8
V
V
A
Drain Current (pulse) Note1
A
Total Power Dissipation (TA = 25°C)
Total Power Dissipation (TC = 25°C)
Channel Temperature
W
W
°C
°C
A
(TO-262)
PT
85
Tch
175
Storage Temperature
Tstg
−55 to +175
46/27/10
Single Avalanche Current Note2
Single Avalanche Energy Note2
IAS
EAS
2.1/73/100
mJ
Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1%
(TO-263)
2. Starting Tch = 25°C, RG = 25 Ω , VGS = 20 → 0 V (see Figure 4.)
THERMAL RESISTANCE
Channel to Case Thermal Resistance
Channel to Ambient Thermal Resistance
Rth(ch-C)
Rth(ch-A)
1.76
83.3
°C/W
°C/W
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D14095EJ4V0DS00 (4th edition)
Date Published December 2002 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
1999, 2000
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
Zero Gate Voltage Drain Current
Gate Leakage Current
SYMBOL
IDSS
TEST CONDITIONS
VDS = 55 V, VGS = 0 V
MIN.
TYP.
MAX.
10
UNIT
µA
µA
V
IGSS
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 24 A
VGS = 10 V, ID = 24 A
VGS = 5 V, ID = 24 A
VGS = 4.5 V, ID = 24 A
±10
2.5
Gate to Source Threshold Voltage
Forward Transfer Admittance
Drain to Source On-state Resistance
VGS(th)
| yfs |
RDS(on)1
RDS(on)2
RDS(on)3
Ciss
1.5
13
2.0
25
S
13
17
21
mΩ
mΩ
mΩ
pF
pF
pF
ns
16
18
24
Input Capacitance
VDS = 25 V
VGS = 0 V
f = 1 MHz
1970
250
130
17
3000
380
240
38
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
td(on)
tr
td(off)
tf
VDD = 28 V, ID = 24 A
VGS = 10 V
11
27
ns
RG = 1 Ω
Turn-off Delay Time
Fall Time
54
110
23
ns
9.3
40
ns
Total Gate Charge 1
Total Gate Charge 2
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
QG1
VDD = 44 V, VGS = 10 V, ID = 48 A
60
nC
nC
nC
nC
V
QG2
VDD = 44 V
VGS = 5 V
ID = 48 A
21
32
QGS
7
QGD
VF(S-D)
trr
10
IF = 48 A, VGS = 0 V
1.0
40
IF = 48 A, VGS = 0 V
ns
di/dt = 100 A/µs
Qrr
55
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
V
GS
R
L
RG
= 25 Ω
90%
90%
V
GS
Wave Form
V
GS
10%
0
R
G
PG.
GS = 20 → 0 V
PG.
50 Ω
V
DD
V
DD
V
DS
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
τ
I
D
t
d(on)
t
r
t
d(off)
tf
V
DD
t
on
toff
τ = 1
µ
s
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
RL
PG.
50 Ω
V
DD
2
Data Sheet D14095EJ4V0DS
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
TYPICAL CHARACTERISTICS (TA = 25°C)
Figure2. TOTAL POWER DISSIPATION vs.
CASE TEMPERATURE
Figure1. DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
140
120
100
80
100
80
60
40
20
0
60
40
20
0
0
25 50 75 100 125 150 175 200
0
25 50 75 100 125 150 175 200
- Case Temperature - ˚C
T
C
TC - Case Temperature - ˚C
Figure3. FORWARD BIAS SAFE OPERATING AREA
Figure4. SINGLE AVALANCHE ENERGY
DERATING FACTOR
1000
100
10
120
100
80
60
40
20
0
100 mJ
73 mJ
I
D(pulse)
I
D(DC)
DC
I
AS = 10 A
27 A
46 A
1
Single pulse
= 25˚C
2.1 mJ
50
T
C
0.1
0.1
25
75
100
125
150
175
1
10
100
V
DS - Drain to Source Voltage - V
Starting Tch - Starting Channel Temperature - ˚C
Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
R
th(ch-A) = 83.3˚C/W
th(ch-C) = 1.76˚C/W
R
1
0.1
0.01
Single pulse
100 1000
10
µ
100
µ
1 m
10 m
100 m
1
10
PW - Pulse Width - s
3
Data Sheet D14095EJ4V0DS
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
Figure6. FORWARD TRANSFER CHARACTERISTICS
Figure7. DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
1000
140
120
100
80
Pulsed
Pulsed
V
GS = 10 V
100
5 V
T
A
= −40˚C
25˚C
10
1
60
4.5 V
75˚C
150˚C
175˚C
40
20
0
0.1
1.0
2.0
3.0
4.0
0
1
2
5
6
3
4
VDS - Drain to Source Voltage - V
V
GS - Gate to Source Voltage - V
Figure8. FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
100
40
V
DS = 10 V
Pulsed
Pulsed
35
10
30
25
T
A
= 175˚C
75˚C
25˚C
1
ID = 24 A
20
15
10
5
−40˚C
0.1
0.01
0
0.01
0.1
1
10
100
0
5
10
15
20
ID - Drain Current - A
VGS - Gate to Source Voltage - V
Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs.
CHANNEL TEMPERATURE
Figure10. DRAIN TO SOURCE ON-STATE
RESISTANCE vs. DRAIN CURRENT
3.0
40
30
20
10
0
V
DS = VGS
Pulsed
I
D
= 250 A
µ
2.5
2.0
1.5
1.0
V
GS = 4.5 V
5 V
10 V
0.5
0
−50
0
50
100
150
1
10
100
1000
T
ch - Channel Temperature - ˚C
I
D
- Drain Current - A
4
Data Sheet D14095EJ4V0DS
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
Figure13. SOURCE TO DRAIN DIODE
Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
FORWARD VOLTAGE
1000
100
Pulsed
45
40
35
30
25
20
15
10
5
Pulsed
V
GS = 4.5 V
5 V
VGS = 10 V
10 V
10
1
0 V
I
D
= 24 A
150
ch - Channel Temperature - ˚C
0.1
0
0
0.5
1.0
1.5
−50
0
50
100
V
SD - Source to Drain Voltage - V
T
Figure14. CAPACITANCE vs. DRAIN TO
SOURCE VOLTAGE
Figure15. SWITCHING CHARACTERISTICS
1000
100
10000
1000
100
V
GS = 0 V
f = 1 MHz
t
f
C
iss
t
d(off)
t
d(on)
C
oss
rss
t
r
10
1
C
0.1
1
10
100
10
0.1
1
10
100
ID - Drain Current - A
V
DS - Drain to Source Voltage - V
Figure16. REVERSE RECOVERY TIME vs.
DRAIN CURRENT
Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS
16
14
12
10
8
80
70
60
50
40
30
20
10
0
1000
100
di/dt = 100 A/
µ
s
V
GS = 0 V
V
DD = 44 V
28 V
11 V
V
GS
6
10
1
4
V
DS
2
I = 48 A
D
0
0.1
1
10
100
0
10
20
30
40
I
F
- Drain Current - A
Q
G
- Gate Charge - nC
5
Data Sheet D14095EJ4V0DS
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
PACKAGE DRAWINGS (Unit: mm)
1) TO-220AB (MP-25)
2) TO-262 (MP-25 Fin Cut)
4.8 MAX.
1.3±0.2
10.6 MAX.
10.0 TYP.
4.8 MAX.
1.3±0.2
φ
3.6±0.2
10 TYP.
4
1
2
3
4
1
2 3
1.3±0.2
1.3±0.2
2.8±0.2
0.5±0.2
0.75±0.3
2.54 TYP.
2.54 TYP.
0.75±0.1
2.54 TYP.
0.5±0.2
1. Gate
2. Drain
3. Source
4. Fin (Drain)
2.8±0.2
1. Gate
2. Drain
3. Source
2.54 TYP.
4. Fin (Drain)
3) TO-263 (MP-25ZJ)
★ 4) TO-263 (MP-25ZK)
4.8 MAX.
10.0±0.3
4.45±0.2
10 TYP.
4
1.3±0.2
No plating
7.88 MIN.
1.3±0.2
4
0.025 to
0.25
1
2
3
1.4±0.2
0.7±0.2
0.5±0.2
0.75±0.2
2.54 TYP.
2.54 TYP.
2.54
0.25
1
2
3
1. Gate
2. Drain
3. Source
1. Gate
2. Drain
4. Fin (Drain)
3. Source
4. Fin (Drain)
EQUIVALENT CIRCUIT
Remark The diode connected between the gate and source of the
transistor serves as a protector against ESD. When this device
actually used, an additional protection circuit is externally
required if a voltage exceeding the rated voltage may be
applied to this device.
Drain
Body
Diode
Gate
Gate
Protection
Diode
Source
6
Data Sheet D14095EJ4V0DS
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
[MEMO]
7
Data Sheet D14095EJ4V0DS
NP48N055CLE,NP48N055DLE,NP48N055ELE,NP48N055KLE
•
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
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purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
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customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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M8E 02. 11-1
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