PD70F3564 [RENESAS]
32-bit Single-Chip Microcontroller; 32位单芯片微控制器型号: | PD70F3564 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 32-bit Single-Chip Microcontroller |
文件: | 总80页 (文件大小:2415K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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Cover
V850E2/FL4-H
32-bit Single-Chip Microcontroller
µPD70F3564
32
R01DS0144ED0100
2013-05-24
Renesas Electronics
www.renesas.com
Notice
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Notes for CMOS Devices
(1) Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag
or conductive material. All text and measurement tools including work bench
and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
(2) Handling of unused input pins for CMOS
No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a resistor,
if it is considered to have a possibility of being an output pin. All handling
related to the unused pins must be judged device by device and related
specifications governing the devices.
(3) Status before initialization of MOS devices
Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
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Table of contents
Chapter 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1
Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1.1
1.1.2
Alternative function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
1.3
Pin Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
General measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1
AC characteristic measurement condition. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
2.3
2.4
2.5
Supply voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Port voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Port current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 3 Power supply specification. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
Requirements for external power supply connections . . . . . . . . . . . . . . . . . . . . . 16
Power area definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Supply voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.1
3.4.2
3.4.3
3.4.4
AWO Regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
POC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Power-up/-down sequence of external supply voltages . . . . . . . . . . . . . . . . . . . . 22
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
External FLMDn Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Condition 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Condition 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Condition 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Condition 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Condition 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Condition 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 4 Clock generators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1
4.2
4.3
CPU clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Peripheral clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.1
4.3.2
4.3.3
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sub-oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.4
PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Chapter 5 Supply current specification. . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1
5.2
5.3
Total supply current for µPDF70F3564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CVDD supply current for µPDF70F3564 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Voltage Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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Chapter 6 I/O specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1
Port Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Condition settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PgE0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PgE1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PgB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PgA0 and PgA1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Chapter 7 Peripherals specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
NMI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INTP timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
FLMD0 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
_DCUTRST timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timer timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Multiplexed bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.7.1
7.7.2
MEMC0CLK asynchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
MEMC0CLK synchronous timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.8
CSI timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.8.1
7.8.2
Master modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.9
UART timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FCN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
FlexRay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Ethernet timing (MII interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.12.1 Transmission interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.12.2 Reception interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
IIC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Frequency Output Function (FOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
VLVI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Voltage comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LVI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
A/D Converter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.18.1 12bit A/D (for ADC channels without S/H functionality) . . . . . . . . . . . . . . . . 69
7.18.2 12bit A/D (For channel ADCA0I0-5 when the S/H function is not used) . . . . 70
7.18.3 12bit A/D (When channel S/H function is used) . . . . . . . . . . . . . . . . . . . . . . 71
7.18.4 10bit A/D (for ADC channels without S/H functionality) . . . . . . . . . . . . . . . . 72
7.18.5 10bit A/D (For channel ADCA0I0-5 when the S/H function is not used) . . . . 73
7.18.6 10bit A/D (When channel S/H function is used) . . . . . . . . . . . . . . . . . . . . . . 74
7.18.7 Equivalent circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
7.18.8 ADTRG timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Key Return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
Chapter 8 Memory specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.1
8.2
8.3
Code flash specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Data flash specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Serial write operation specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Chapter 9 Pinning and package specification . . . . . . . . . . . . . . . . . . 78
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9.1
9.2
Pinning specification PBGA 272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Package specification PBGA 272. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Chapter 1
Overview
Chapter 1 Overview
1.1 Naming
1.1.1 Alternative function pins
Function
name
Peripheral
Prefix
Suffix
Peripheral
Macro pin
naming
Short-cut of
Consecutive number for
Consecutive number
for same pin namesa
macro name same peripheral modulea
a)
This is an option that can be omitted if meaning is obvious
Example:
– TAUB0I0, TAUB1I5
– URTE0TX, URTE0RX, URTE1TX, URTE1RX
– CSIG0SO, CSIG0SI, CSIG0SC, CSIG0RY
1.1.2 Power supply pins
Kind of
supply
Function
Prefix
Suffix
Consecutive number
for different pins with
same meaninga
Consecutive number for
different functionsa
Symbol
VDD or VSS
a)
This is an option that can be omitted if meaning is obvious
Example:
– E0VDDn, REG0VSS
Table 1-1 Selection for Functions
Function
Explanation
Core supply
C
REG
OSC
F
Internal regulator supply
Oscillator supply
Flash module supply
E
Standard buffer supply (mainly 5V or up to 40Mhz)
Standard buffer supply (mainly 3.3V or beyond 40Mhz)
Analog module supply (e.g. ADC)
B
A
If not mentioned otherwise this document neglects suffixes for power supply
pins with same functions that can be treated as equal.
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Chapter 1
Overview
1.2 Pin Groups
Symbol
PgE0
Pin group supplied by
E0VDD / E0VSS
Related pins / ports
JP0, P0, _RESET, FLMD0, WAKE, PWDG,
VCPC0IN, VCPC1IN
PgE1
PgB0
E1VDD / E1VSS
B0VDD / B0VSS
OSCVDD / OSCVSS
A0VDD / A0VSS
A1VDD / A1VSS
P1, P2, P3, P4
P21, P24, P25, P27
X1, X2, XT1, XT2
P10, P11, ADCA0Im
P12, P13
PgOSC
PgA0
PgA1
1.3 General measurement conditions
1.3.1 AC characteristic measurement condition
AC test input waveform
xVDD
7*)ꢀꢁNJOꢂ
7*)ꢀꢁNJOꢂ
7*-ꢀꢁNBYꢂ
.FBTVSFNFOU
7*-ꢀꢁNBYꢂ
xVSS
AC test output waveform
xVDD
70)ꢀꢁNJOꢂ
70)ꢀꢁNJOꢂ
70-ꢀꢁNBYꢂ
.FBTVSFNFOU
70-ꢀꢁNBYꢂ
xVSS
Standard AC test condition is 70%/30% of the applied IO supply voltage
(XmVDD) if not otherwise stated in the according AC timing specification of an
interface.
AC Test Condition: Ext. Capacitive Load
Load on test:
DUT
CL= 50pF
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Chapter 2
Absolute maximum ratings
Chapter 2 Absolute maximum ratings
2.1 Supply voltages
Table 2-1 VDD Data
Parameter
Symbol
CVDD
Condition
Ratings
-0.5 ~ 1.6
-0.5 ~ 6.0
-0.5 ~ 6.0
-0.5 ~ 6.0
-0.5 ~ 6.0
-
Unit
V
System
FVDD
V
OSCVDD
REG0VDD
REG1VDD
REG2VDD
REG3VDD
E0VDD
V
V
System
V
V
-
V
-0.5 ~ 6.0
-0.5 ~ 6.0
-0.5 ~ 6.0
V
Ports
E1VDD
V
Port
B0VDD
V
-0.3 ~ A0VDD+0.3
-0.3~6.0
ADCA0
ADCA0
A0VREFP
V
A0VDD
A1VDD
-0.5 ~ 6.0
-0.5 ~ 6.0
V
V
ADCA1
-0.3 ~ A1VDD+0.3
-0.3~6.0
A1VREFP
V
Table 2-2 VSS Data
Parameter
Symbol
CVSS
Condition
Ratings
-0.5 ~0.5
-0.5 ~0.5
-0.5 ~0.5
-0.5 ~0.5
-0.5 ~0.5
-
Unit
V
System
FVSS
V
OSCVSS
REG0VSS
REG1VSS
REG2VSS
REG3VSS
E0VSS
V
V
System
V
V
-
V
-0.5 ~0.5
-0.5 ~0.5
-0.5 ~0.5
-0.5 ~0.5
V
Ports
E1VSS
V
B0VSS
V
A0VSS
V
ADC0
ADC1
-0.3 ~ A0VDD+0.3
-0.3~6.0
A0VREFM
A1VSS
V
V
V
-0.5 ~0.5
-0.3 ~ A1VDD+0.3
-0.3~6.0
A1VREFM
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Chapter 2
Absolute maximum ratings
2.2 Port voltages
Table 2-3 Port Input voltage
Parameter
Pin Group
PgE0
Symbola
VI0
Condition
E0VDD≤5.5
Ratings
Unit
V
-0.5 ~ E0VDD+0.5
-0.5 ~ E1VDD+0.5
-0.5 ~ B0VDD+0.5
-0.5 ~ OSCVDD+0.5
A0VDD+0.3
PgE1
VI1
E1VDD≤5.5
B0VDD≤5.5
OSCVDD≤5.5
V
PgB0
VI2
V
Input voltageb
PgOSC
PgA0
VI5
V
VI3
V
PgA1
VI4
A1VDD+0.3
V
a)
b)
The symbols reflect all supplies within the device series. Therefore not every symbol is available for each
product.
The characteristics of the alternative-function pins are the same as those of the port pins unless otherwise
specified.
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Chapter 2
Absolute maximum ratings
2.3 Port current
Table 2-4 High level port output current
Parameter
Pin Groupa
Symbol
Condition
1 pin of PgE0
Max. spec
-10
Unit
PgE0
Power supply of PgE0
1 pin of PgE1
-50
PgE1
-10
High level output
current
IOH
mA
Power supply of PgE1
1 pin of PgA0
-150
-10
PgA0
PgA1
PgB0
Power supply of PgA0
1 pin of PgA1
-25
-10
High level output
current
IOH
IOH
mA
mA
Power supply of PgA1
1 pin of PgB0
-25
-10
High level output
current
Power supply of PgB0
-200
a)
The column reflects all supplies within the device series. Therefore not each pin group is available for each
product.
Table 2-5 Low level port output current
Parameter
Pin Groupa
Symbol
Condition
1 pin of PgE0
Max. spec
Unit
10
50
PgE0
Power supply of PgE0
1 pin of PgE1
PgE1
10
Low level output
current
IOL
mA
Power supply of PgE1
1 pin of PgA0
150
10
PgA0
PgA1
PgB0
Power supply of PgA0
1 pin of PgA1
25
10
Low level output
current
IOL
IOL
mA
mA
Power supply of PgA1
1 pin of PgB0
25
10
Low level output
current
Power supply of PgB0
150
a)
The column reflects all supplies within the device series. Therefore not each pin group is available for each
product.
2.4 Capacitance
Parameter
Symbol
CI
Condition
Max. spec
Unit
pF
Input capacitance
15
15
15
f = 1 MHz
0V for non measurement pins
Input/Output capacitance
Output capacitance
CIO
pF
CO
pF
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Chapter 2
Absolute maximum ratings
2.5 Thermal characteristics
Table 2-6 Thermal characteristics
Parameter
Symbol
Condition
Ratings
-65 ~150
-40 ~85
Unit
Storage temperature
TSTG
(A) grade products
(A1) grade products
Operating ambient
temperature
Junction temperature
Ta
Tj
-40 ~110
-40 ~150
°C
This section specifies the absolute maximum limitation of operating and
storage temperature.
The device’s functions are not guaranteed outside of the specified maximum
temperature ratings.
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Chapter 3
Power supply specification
Chapter 3 Power supply specification
3.1 Requirements for external power supply
connections
The user has to ensure a low resistive connection of all VSS pins on the PCB.
This specification denotes ground supply pins as:
• VSS = OSCVSS = REGnVSS = EnVSS = BnVSS = AnVSS = AnVREM =
CVSS = 0V
in the further text.
With
• EnVSS = E0VSS = E1VSS
• BnVSS = B0VSS
• REGnVSS = REG0VSS = REG1VSS
• AnVSS = A0VSS = A1VSSAnVREFM = A0VREFM = A1VREFM
The user has to ensure a low resistive connection of all VDD pins to the related
power supply. This specification denotes power supply pins as:
• EnVDD, BnVDD, FVDD, REGnVDD, OSCVDDCVDD, AnVDD and
AnVREFP.
in the further text.
With
• EnVDD = E0VDD = E1VDD
• BnVDD = B0VDD
• REGnVDD = REG0VDD = REG1VDD.
• AnVDD = A0VDD = A1VDD
• AnVREFP = A0VREFP = A1VREFP
• I/OVDD = AnVDD, EnVDD, B0VDD, FVDD, OSCVDD
3.2 Power area definitions
The device consists of the following power areas:
• AWO (Always On area)
• ISO0 (Isolated area 0)
• ISO1 (Isolated area 1)
The table below lists the related core and port voltage supply of each power
area:
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Chapter 3
Power supply specification
Table 3-1 Power areas supply voltages
Supply voltage
Core supply
Power
Area
Related pins
REG0VDD, REG0VSS, REG0C
E0VDD, E0VSS
Port Supply
Other
AWO
ISO0
OSCVDD, OSCVSS
FVDD0
REG1VDD, REG1VSS
CVDD, CVSS
Core supply
Port Supply
Other
E1VDD, E1VSS
A0VREFP, A0VREFM
A0VDD, A0VSS
REG1VDD, REG1VSS
CVDD, CVSS
Core supply
Port Supply
Other
ISO1
B0VDD, B0VSS
A1VDD, A1VSS
A1VREFP, A1VREFM
3.3 Power supply groups
For each of the following power supply groups the same voltage must by
supplied:
Table 3-2 Power supply groups
Power supply
Related pins
group
#1
#2
#3
#4
#5
#6
#7
REG0VDD, REG1VDD, FVDD, OSCVDD, E0VDD, E1VDD
B0VDD
-
CVDD
A0VDD, A0VREFP
A1VDD, A1VREFP
All VSS
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Chapter 3
Power supply specification
3.4 Supply voltages
Table 3-3 VDD Data
Ratings
Unit
Parameter
Symbol
Condition
Min
VPOC
VPOC
VPOC
VPOC
-
Typ
Max
5.5
5.5
5.5
5.5
-
System supply voltage
System supply voltage
System supply voltage
System supply voltage
System supply voltage
System supply voltage
System supply voltage
FVDD
-
-
-
-
-
-
-
V
V
V
V
V
V
V
OSCVDD
REG0VDD
REG1VDD
REG2VDD
REG3VDD
CVDD
REG0VDD = REG1VDD
REG1VDD = 3.0V to 5.5V
-
-
1.1
1.3
System supply voltage
slopes
AIVS
-
-
5.6
V/ms
Port supply voltages
Port supply voltages
Port supply voltages
E0VDD
E1VDD
VPOC
VPOC
-
-
5.5
5.5
V
V
B0VDD
B0VDD ≤ power supply group #1 voltages VPOC
-
5.5
V
ADC supply voltages
ADC supply voltages
ADC supply voltages
ADC supply voltages
ADC supply voltages
ADC supply voltages
A0VDD
A0VDD
12bit resolution
10bit resolution
4.5
-
-
-
-
-
-
5.5
5.5
V
V
V
V
V
V
VPOC
A0VDD
4.5
A0VREFP
A0VDD
5.5
12bit resolution
10bit resolution
A1VDD
VPOC
A1VDD
5.5
A1VREFP A1VREFP-A1VREFM > A1VDD/2
A1VDD
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Chapter 3
Power supply specification
3.4.1 AWO Regulator characteristics
Table 3-4 AWO Regulator characteristics
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
Regulator Output
voltage
VRO
1.1
1.2
1.3
V
System supply voltage
slope
RAVS 0V to 3.0V
REG0C
-
-
1800
6.11
V/ms
µF
Capacitance on
REG0C
3.29
4.7
After REG0VDD reaches 3.0V
After DeepStop mode
-
-
-
-
1
ms
ms
Output voltage
stabilization time
TRAA
0.5
During power-up sequence
REG0VDD
VPOC
RAVS
VRO
VROMIN
TRAA
After DeepStop mode
VPOC to 5.5V
REG0VDD
VRO
VROMIN
TRAA
DeepStop
Release timing
3.4.2 Amplifier characteristics
Ratings
Typ
Parameter
Symbol
Condition
Unit
Min
Max
5.5
System supply voltage REG1VDD
VPOC
3.29
-
V
Capacitance on CVDD
Voltage slope
CVDDC
AIVS
For each CVDDa
3.0V to 5.5V
4.7
-
6.11
5.6
µF
V/ms
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Chapter 3
Power supply specification
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
After REG1VDD reaches 3.0V
After DeepStop mode
-
-
-
-
-
-
1
ms
ms
mA
PTCTL1 stabilization
time
TRAI
0.5
1.55
PTCTL1 output current
IPTCTL
a)
Required when using an external power transistor such as 2SD1584 (base connected to PTCTL1)
During power-up sequence
REG1VDD
3.0V
AIVS
PTCTL1
TRAI
After DeepStop mode
VPOC to 5.5V
REG1VDD
PTCTL1
TRAI
DeepStop
Release timing
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Chapter 3
Power supply specification
3.4.3 POC characteristics
Table 3-5 POC characteristics
Ratings
Unit
Parameter
Detection voltage
Symbol
Condition
Min
2.8
Typ
Max
VPOC
PVS1
PVS2
2.9
3.0
V
Voltage slope 1
Voltage slope 2
0.18
-
-
1800
1800
V/ms
V/ms
0.0018
From detect voltage to release of reset
signal.
Response time 1
tPTHD
-
-
2
ms
Voltage slope = PVS1, PVS2
From detect voltage to occurence of
reset signal
Voltage slope = PVS2
Response time 2
tPD
-
-
-
2
-
ms
ms
VDD minimum width
tPW
0.2
VDD
Pvs2
Detect voltage(MAX.)
Detect voltage(TYP.)
Detect voltage(MIN.)
Pvs1
tPW
tPTHD
tPD
tPTHD
3.4.4 Voltage Comparator characteristics
Table 3-6 VCMP characteristics
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
REG0VDD
Input voltage range of VCPCnIN
VICMP
REG0VSS
-
V
Note VDD: REG0VDD
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Chapter 3
Power supply specification
3.5 Power-up/-down sequence of external supply
voltages
3.5.1 External FLMDn Resistors
Valid for all conditions described in the following
Ratings
Parameter
Symbol
Condition
Unit
Min
82
-
Typ
-
Max
FLMD0 external pull-down resistor
FLMD1 external pull-down resistor
R1
R2
-
-
kΩ
kΩ
10
3.5.2 Condition 1
RESET, WAKE and PTCTL1 are not used
Normal operating mode
Ratings
Typ
Parameter
Symbol
Condition
Unit
Min
Max
REG0VDD, REG1VDD, IOVDD (rise) to
CVDD (rise)
tR0CON
tR0MDH
1
-
-
10
ms
ms
REG0VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
2
-
FLMD0,1 (≤VIL) to REG0VDD, IOVDD
(fall)
tMDR0OF
tCR0OF
0
0
-
-
-
-
ms
ms
CVDD (0V) to REG0VDD, IOVDD (fall)
REGnVDD
3.0V
3.0V
IOVDD
1.1V
CVDD
tROCON
tROCOF
FLMD0
P0_1/FLMD1
VIL
VIL
tROMDH
tMDR0OF
Note IOVDD: AnVDD, B0VDD, EnVDD, FVDD, OSCVDD
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Chapter 3
Power supply specification
3.5.3 Condition 2
RESET is used; WAKE and PTCTL1 are not used
Normal operating mode / Serial programming mode
Ratings
Typ
Parameter
Symbol
Condition
Unit
Min
Max
REGnVDD, IOVDD (rise) to CVDD (0V)
hold time
tR0CH
1
-
-
ms
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
tR0MDH
tCRR
1
0
1
-
-
-
-
-
-
ms
ms
ms
CVDD (rise) to _RESET (rise)
FLMD0,1 (≥VIH or VIL1) a to
_RESET(≤VIL) (rise)
tMDRR
_RESET (rise) to FLMD0,1(≥VIH or ≤VIL)
hold time
tRMDH
tMDRF
1
0
-
-
-
-
ms
ms
FLMD0,1,MODE0,1(≤VIL) to _RESET
(≥VIH) (fall) setup time
_RESET (fall) to CVDD (fall)
tRCF
0
0
-
-
-
-
ms
ms
CVDD (0V) to REGnVDD, IOVDD (fall)
tCR0OF
_RESET (≤VIL) (fall) to REGnVDD,
IOVDD (fall) hold time
tRR0OF
0
-
-
ms
a)
In case of BSCAN mode set also the MODE0,1 pins.
REGnVDD
3.0V
IOVDD
3.0V
CVDD
1.1V
tCRR
VIH
1.1V
tR0CH
tRCF tCROOF
FLMD0
P0_1/FLMD1
VIL
VIL
tROMDH
tMDRR tRMDH
VIH
_RESET
VIL
tMDRF
tRR0OF
Note There is no specification for _RESET rise and fall times.
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Chapter 3
Power supply specification
3.5.4 Condition 3
RESET is not used; WAKE/PWGD is used
Normal operating mode
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
REG0VDD, REG1VDD, IOVDD (rise) to
WAKE (rise) output delay time
tR0WRD
-
-
2
ms
WAKE (rise) to CVDD (rise)
CVDD (rise) to PWGD (rise)
tWCON
0
0
-
-
8
-
ms
ms
tCPWDH
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
tR0MDH
2
-
-
ms
FLMD0,1 (≤VIL) to REG0VDD, IOVDD
(fall)
tMDR0OF
tWCOF
0
0
-
-
-
ms
ms
WAKE (fall) to CVDD (0V)
8
REG0VDD
3.0V
3.0V
REG1VDD
IOVDD
CVDD
1.1V
tWCOF
tWCON
PWGD
VIL
tCPWDH
FLMD0
P0_1/FLMD1
VIL
VIL
tROMDH
tR0WRD
tMDR0OF
VIH
WAKE
VIL
The WAKE signal falls at the same time as the fall of the IOVDD voltage due to
the lack of output voltage.
Even if REG0VDD keeps some voltage, the WAKE signal falls at least 2ms
after the POC detection.
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Chapter 3
Power supply specification
3.5.5 Condition 4
RESET and WAKE/PWGD are used.
Normal operating mode / Serial programming mode / BSCAN mode
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1 (≤VIL) hold time
tR0MDH
1
-
-
ms
FLMD0,1 (VIH or VIL) a to _RESET (rise)
_RESET (rise) to CVDD (rise)
WAKE (rise) to CVDD (rise)
tMDRR
tRCON
1
0
0
0
-
-
-
-
-
10
-
ms
ms
ms
ms
tWCON
tCPWDH
CVDD (rise) to PWGD (rise)
-
_RESET (rise) to FLMD0,1(VIH or VIL) a
hold time
tRMDH
1
-
-
ms
FLMD0,1 (≤VIL) to _RESET (fall)
_RESET (fall) to CVDD (fall)
WAKE (fall) to CVDD (fall)
tMDRF
tRCF
0
0
0
0
0
-
-
-
-
-
-
10
-
ms
ms
ms
ms
ms
tWCF
PWGD (VIH) to CVDD (fall)
tPCS
-
CVDD (0V) to REG0VDD, IOVDD (fall)
tCR0OF
-
a)
In case of BSCAN mode set also the MODE0,1 pins.
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
CVDD
1.1V
1.1V
tRCON
tWCON
tRCF
tCR0OF
tWCF
VIH
PWGD
FLMD0
VIL
tWPF
tPR0OF
tCPWDH
VIH
P0_1/FLMD1
VIL
VIL
tR0MDH
VIH
tMDRR
tRMDH
VIH
VIL
tMDRF
_RESET
WAKE
VIL
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Electrical Target Specification
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Chapter 3
Power supply specification
3.5.6 Condition 5
PTCTL1 is used
Normal operating mode
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
REG0VDD, REG1VDD, IOVDD (rise) to
PTCTL1 (rise) setup time
tR1PTON
tR0CON
tR0MDH
tMDR0OF
-
-
1
ms
ms
ms
ms
REG0VDD, REG1VDD, IOVDD (rise) to
CVDD (rise) byPTCTL1 (rise)
1
2
0
-
-
-
10
-
REG0VDD, REG1VDD, IOVDD (rise) to
FLMD0,1(≤VIL) hold time
FLMD0,1 (≤VIL) to REG0VDD,
REG1VDD, IOVDD (fall)
-
REG0VDD, REG1VDD, IOVDD (fall) to
PTCTL1 (fall)
tR1PTOF
tPTCOF
-
-
-
1
8
ms
ms
PTCTL1 (fall) to CVDD (fall)
0
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
1.1V
CVDD
tR0CON
VIL
tPTCOF
FLMD0
P0_1/FLMD1
VIL
tR0MDH
tMDR0OF
PTCTL1
tR1PTON
tR1PTOF
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Electrical Target Specification
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Chapter 3
Power supply specification
3.5.7 Condition 6
RESET is used; PTCTL1 is used
Normal operating mode / Serial programming mode / BSCAN mode
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
REG0VDD, REG1VDD, IOVDD (rise) to
CVDD (0V) hold time
tR0CH
tR1PTON
tR0MDH
-
-
1
ms
ms
ms
REG1VDD (rise) to PTCTL1 (rise) setup
time
-
-
-
1
-
REG0VDD, IOVDD (rise) to FLMD0,1
(≤VIL) hold time
1
CVDD (rise) to _RESET (rise)
tCRR
0
1
-
-
-
-
ms
ms
FLMD0,1 (VIH or VIL) a to _RESET (rise)
tMDRR
_RESET (rise) to FLMD0,1 (VIH or VIL)
hold time
tRMDH
tMDRF
1
0
-
-
-
-
ms
ms
FLMD0,1,MODE0,1 (≤VIL) a to _RESET
(fall)
_RESET (fall) to REG0VDD, IOVDD (fall)
REG1VDD (fall) to PTCTL1 (fall)
PTCTL1 (fall) to CVDD (fall)
tRR0OF
tR1PTOF
tPTCOF
0
-
-
-
-
-
ms
ms
ms
1
8
0
a)
In case of BSCAN mode set also the MODE0,1 pins.
REG0VDD
REG1VDD
IOVDD
3.0V
3.0V
CVDD
1.1V
tCRR
tR0CH
tPTCOF
VIH
FLMD0
P0_1/FLMD1
VIL
VIL
tRMDH
VIH
tMDRR
tR0MDH
_RESET
tMDRF
tRR0OF
PTCTL1
tR1PTOF
tR1PTON
Note There is no specification for _RESET rise and fall times.
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Electrical Target Specification
27
Chapter 4
Clockgenerators
Chapter 4 Clock generators
4.1 CPU clock
Table 4-1 CPU clock frequency
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
PLL based
SSCG based
-
-
-
-
160
MHz
CPU clock frequency
fCPU
176.64 MHz
4.2 Peripheral clock
Table 4-2 Peripheral clock frequency
Ratings
Typ
Parameter
Symbol
Condition
Unit
Max
Min
Peripheral clock
frequency
fPERI
-
-
80
MHz
4.3 Oscillator characteristics
4.3.1 Main oscillator
A ceramic or crystal resonator can be connected to the main clock input pins
as shown in figure 4-1 “Recommended Main Oscillator Circuit”
.
X1
X2
internal
external
R
d
C1
C2
Figure 4-1 Recommended Main Oscillator Circuit
Caution Values of C , C and R and the best setting for MOSCC.AMPSEL[1:0]
1
2
d
register depend on the used ceramic or crystal resonator and must be
specified in cooperation with ceramic or crystal resonator manufacturer.
The main oscillator amplifier gain for the external resonator can be selected by
MOSCC.MOSCCAMPSEL[1:0]. Thereby it can be adjusted to support a wide
R01DS0144ED0100
Electrical Target Specification
28
Chapter 4
Clockgenerators
range of frequencies to cope with different external resonators and their
external circuitry.
As an example a typical setting for quartz crystals is shown in Table 4-3
“Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals
frequencies”.
Note For details to the setting of MOSCC.MOSCCAMPSEL[1:0] please refer to the
user manual.
Table 4-3 Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals
frequencies
MOSCC.AMPSEL[
1:0]
Amplification
gain
Typical condition for quartz
crystals
00
01
10
11
high
medium
low
16 < fMOSC ≤ 20 MHz
8 < fMOSC ≤ 16 MHz
4 < fMOSC≤ 8 MHz
4 MHz
very low
(1) Main oscillator charactrisitics
Table 4-4 Main oscillator characteristics
Ratings
Parameter
MainOSC frequency
Symbol
Condition
Unit
Min
Typ
Max
fMOSC
4
-
20
MHz
Cautions 1. External clock input is prohibited.
2. General guidance for PCB layout:
• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route this circuit close to a signal line with high fluctuating current
flow.
• Always make the ground point of the oscillator capacitor the same
potential as REG0VSS and OSCVSS.
• Do not ground the capacitor to a ground pattern with high current flow.
• Do not tap signals from the oscillator.
4.3.2 Sub-oscillator
A crystal resonator can be connected to the sub clock input pins as shown in
figure 4-2 “Recommended Sub Oscillator Circuit”
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Electrical Target Specification
29
Chapter 4
Clockgenerators
.
XT1
XT2
internal
external
R
ds
C1s
C2s
Figure 4-2 Recommended Sub Oscillator Circuit
Caution Values of C , C and R depend on the used crystal and must be specified
1s
2s
ds
in cooperation with crystal manufacturer.
(1) Sub-oscillator characteristics
Table 4-5 Sub-oscillator characteristics
Ratings
Typ
Parameter
MainOSC frequency
Symbol
Condition
Unit
Min
Max
fSOSC
-
32.768
-
kHz
4.3.3 Internal oscillator
Table 4-6 Internal oscillator characteristics
Ratings
Typ
Parameter
Symbol
Condition
Unit
Min
Max
•
•
Other than DeepStop mode
fRL
fRLLP
fRH
220.8
240
240
8.0
259.2
kHz
kHz
MHz
DeepStop mode with
PSC0.REGSTP = 0
Lowspeed OSC frequency
•
DeepStop mode with
PSC0.REGSTP = 1
216
7.2
264
8.8
•
•
Other than DeepStop mode
DeepStop mode with
PSC0.REGSTP = 0
Highspeed OSC frequency
•
DeepStop mode with
PSC0.REGSTP = 1
fRHLP
6.64
-
8.0
-
8.8
19
MHz
µs
Highspeed OSC
stabilization time
TRHSTB
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Electrical Target Specification
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Chapter 4
Clockgenerators
4.4 PLL Characteristics
Table 4-7 PLL characteristics
Ratings
Parameter
Symbol
fxn
Condition
Unit
Min
Typ
Max
20
Input frequency
PLL mode and SSCG mode
PLL mode
4
-
-
-
-
-
MHz
MHz
25
160
Output frequency
fxxn
SSCG mode
22.40
176.6 MHz
TLCKPn
TLCKSn
PLL mode
-
-
650
µs
µs
Lock time
SSCG mode
1300
Peak to peak,
fixed frequency mode,
Pr=2
Period jittera
tPJn
-150
-
-
150
ps
ns
PLL mode, Peak to peak,
term=1µs
Long term jittera
tLTJn
-1.275
1.275
fVCOOUT=160MHz (Pr=2)
a)
Not tested in production. Specified by design.
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Electrical Target Specification
31
Chapter 5
Supply current specification
Chapter 5 Supply current specification
5.1 Total supply current for µPDF70F3564
Table 5-1 Total supply current
a
b
Power
Condition
Specification
Item
Unit
8MHz
Main
Sub
CPU
Freq
ISO0
ISO1
PLL
Peripherals Min. Typ.
(A)
(A1)
intOSC OSC OSC
RUN
mode
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
160
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
STOPPED
STOPPED
STOPPED
STOPPED
STOPPED
247
153
30
394
-
416
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
160
ON
OFF
OFF
ON
OFF
OFF
ON
8
60
-
62
-
ON
8
22
OFF
OFF
OFF
OFF
ON
160
176
140
24
285
-
300
-
ON
ON
160
OFF
OFF
ON
OFF
OFF
ON
8
50
-
52
-
8
21
HALT
mode
160
236
150
29
305
-
311
-
ON
ON
ON
160
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
8
8
-
50
-
51
-
ON
21
STOP
mode
ON
2.5
2.2
0.06
0.60
0.60
57
49
3.4
8.0
8.1
67
57
3.6
9.2
9.2
OFF
OFF
OFF
OFF
-
DEEPSTOP
mode
-
-
-
a)
b)
The AWO is always ON.
The 240kHz IntOSC is always ON.
Notes 1. The above currents do not include port buffer currents or ADC currents.
2. The currents in run mode include currents for self-programming and
EEPROM emulation.
3. The current of FlexRay is not included in case of CPU frequency = 8MHz.
4. The ‘typical’ specification is for reference only and not a guaranteed value.
The ‘typical’ specification is applicable under the following conditions:
•
•
Ta = 25°C
REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V
(n=0-3, m=0-1).
•
•
CVDD = 1.2V
REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V
(n=0-3, m=0-1)
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Electrical Target Specification
32
Chapter 5
Supply current specification
5.2 CVDD supply current for µPDF70F3564
Table 5-2 CVDD supply current
a
b
Power
Condition
Specification
Item
Unit
8MHz
Main
Sub
CPU
Freq
ISO0
ISO1
PLL
Peripherals Min. Typ.
(A)
(A1)
intOSC OSC OSC
RUN
mode
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
ON
160
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
WORKING
STOPPED
STOPPED
STOPPED
STOPPED
STOPPED
STOPPED
216
129
18
347
-
365
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
160
ON
OFF
OFF
ON
OFF
OFF
ON
8
41
-
43
-
ON
8
11
OFF
OFF
OFF
OFF
ON
160
145
116
12
237
-
250
-
ON
ON
160
OFF
OFF
ON
OFF
OFF
ON
8
32
-
33
-
8
9
HALT
mode
160
205
126
17
267
-
272
-
ON
ON
ON
160
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
8
8
-
35
-
36
-
ON
10
STOP
mode
ON
1.7
1.3
0.0
0.0
0.0
37
28
0.0
0.0
0.0
43
33
0.0
0.0
0.0
OFF
OFF
OFF
OFF
-
DEEPSTOP
mode
-
-
-
a)
The AWO is always ON.
The 240kHz IntOSC is always ON.
b)
Notes 1. The above currents do not include port buffer currents or ADC currents.
2. The currents in run mode include currents for self-programming and
EEPROM emulation.
3. The current of FlexRay is not included in case of CPU frequency = 8MHz.
4. The ‘typical’ specification is for reference only and not a guaranteed value.
The ‘typical’ specification is applicable under the following conditions:
•
•
Ta = 25°C
REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V
(n=0-3, m=0-1).
•
CVDD = 1.2V
REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V
(n=0-3, m=0-1)
5.3 Voltage Comparator characteristics
Table 5-3 VCMP characteristics
Ratings
Typ
Parameter
Symbol
Condition
Unit
Min
Max
VCMP current
IVCMP
200
300
µA
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Electrical Target Specification
33
Chapter 6
I/Ospecification
Chapter 6 I/O specification
6.1 Port Characteristics
6.1.1 Condition settings
Some of the conditions mentioned in this chapter can be selected by software.
The related register settings are described below:
(1) Input characteristic
The input characteristics can be selected by the registers PIS and PISE with
the following coding:
Table 6-1 Input characteristic selection
Reference in
UserManual
Electrical
characteristic
PISE
PIS
0
0
1
1
0
1
0
1
Type 1
Type 2
Type 3
Type 4
CMOSa
Schmitt2
Schmitt1
Schmitt4
a)
Default setting after reset
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Electrical Target Specification
34
Chapter 6
I/Ospecification
6.1.2 PgE0
Table 6-2 PgE0 characteristics
Ratings
Parameter
Symbol
Condition
Unit
Max
Min
Typ
CMOS
0.7·E0VDD
-
-
E0VDD+0.3
E0VDD+0.3
Schmitt1
0.7·E0VDD
High level input voltage
VIH
Schmitt2
0.8·E0VDD
-
E0VDD+0.3
E0VDD+0.3
E0VDD+0.3
0.3·E0VDD
0.3·E0VDD
0.2·E0VDD
0.4·E0VDD
0.5·E0VDD
V
V
Schmitt4 (E0VDD=VPOC~3.0)
Schmitt4 (E0VDD=3.0~5.5)
CMOS
0.84·E0VDD
-
0.8·E0VDD
-
-0.5
-
Schmitt1
-0.5
-
Low level input voltage
VIL
Schmitt2
-0.5
-
Schmitt4 (E0VDD=VPOC~3.0)
Schmitt4 (E0VDD=3.0~5.5)
IOH = -5mA
-0.5
-
-0.5
-
E0VDD-1.0
-
High level output voltage
Low level output voltage
VOH
VOL
V
V
IOH = -100µA
IOL = 5mA
E0VDD-0.5
-
-
-
0.4
0.4
IOL = 100µA
-
-
Schmitt1
0.3
0.3
0.1
20
20
-
Input hysteresis of Schmit
VH
Schmitt2
-
V
Schmitt4
-
Internal pull-up resistor
RU
RD
40
40
100
100
kꢀ
kꢀ
Internal pull-down resistor
High level port output
current
IOH
IOL
ILIH
ILIL
Power supply of PgE0
Power supply of PgE0
VI = E0VDD
-
-
-
-
-
-
-
-
-
-
-
-
-20
20
mA
mA
µA
µA
µA
µA
Low level port output
current
High level input leakage
current
0.5
-0.5
0.5
-0.5
Low level input leakage
current
VI = 0V
High level output leakage
current
ILOH VO = E0VDD
ILOL VO = 0V
Low level output leakage
current
Slow mode
fO
-
-
-
-
-
-
-
-
-
-
-
-
25
40
15
8
Output frequency
Rise time (output)
Fall time (output)
MHz
Fast mode
Slow mode
tKRP
ns
ns
ns
ns
Fast mode
Slow mode
tKFP
15
8
Fast mode
R01DS0144ED0100
Electrical Target Specification
35
Chapter 6
I/Ospecification
6.1.3 PgE1
Table 6-3 PgE1 characteristics
Ratings
Parameter
Symbol
Condition
Unit
Max
Min
Typ
CMOS
0.7·E1VDD
-
-
E1VDD+0.3
E1VDD+0.3
Schmitt1
0.7·E1VDD
High level input voltage
Low level input voltage
VIH
Schmitt2
0.8·E1VDD
-
E1VDD+0.3
E1VDD+0.3
E1VDD+0.3
0.3·E1VDD
0.3·E1VDD
0.2·E1VDD
0.4·E1VDD
0.5·E1VDD
V
V
Schmitt4 (E1VDD=VPOC~3.0)
Schmitt4 (E1VDD=3.0~5.5)
CMOS
0.84·E1VDD
-
0.8·E1VDD
-
-0.5
-
Schmitt1
-0.5
-
VIL
Schmitt2
-0.5
-
Schmitt4 (E1VDD=VPOC~3.0)
Schmitt4 (E1VDD=3.0~5.5)
IOH = -5mAa
IOH = -100µA
IOL = 5mAa
-0.5
-
-0.5
-
E1VDD-1.0
-
High level output voltage
Low level output voltage
VOH
VOL
V
V
E1VDD-0.5
-
-
-
0.4
0.4
IOL = 100µA
-
-
Schmitt1
0.3
0.3
0.1
20
20
-
Input hysteresis of Schmit
VH
Schmitt2
-
V
Schmitt4
-
Internal pull-up resistor
RU
RD
40
40
100
100
kꢀ
kꢀ
Internal pull-down resistor
High level port output
current
IOH
IOL
ILIH
ILIL
Power supply of PgE1
Power supply of PgE1
VI = E1VDD
-
-
-
-
-
-
-
-
-
-
-
-
-150
150
0.5
mA
mA
µA
µA
µA
µA
Low level port output
current
High level input leakage
current
Low level input leakage
current
VI = 0V
-0.5
0.5
High level output leakage
current
ILOH VO = E1VDD
ILOL VO = 0V
Low level output leakage
current
-0.5
Slow mode
fO
-
-
-
-
-
-
-
-
-
-
-
-
25
40
15
8
Output frequency
Rise time (output)
MHz
Fast mode
Slow mode
tKRP
ns
ns
ns
ns
Fast mode
Slow mode
tKFP
15
8
Fall time (output)
Fast mode
a)
The maximum number of PgE1 pins with ‘ON’ signal at the same time is 5 in ‘Slow mode’.
The maximum number of PgE1 pins with ‘ON’ signal at the same time is 8 in ‘Fast mode’.
See the UM for the related description of the Port drive strength control.
R01DS0144ED0100
Electrical Target Specification
36
Chapter 6
I/Ospecification
6.1.4 PgB0
Table 6-4 PgB0 characteristics
Ratings
Parameter
Symbol
Condition
Unit
Max
Min
Typ
CMOS
0.7·B0VDD
-
-
B0VDD+0.3
B0VDD+0.3
Schmitt1
0.7·B0VDD
High level input voltage
Low level input voltage
VIH
Schmitt2
0.8·B0VDD
-
B0VDD+0.3
V
V
Schmitt4 (B0VDD=VPOC~3.0)
Schmitt4 (B0VDD=3.0~5.5)
CMOS
0.84·B0VDD
-
B0VDD+0.3
0.8·B0VDD
-
B0VDD+0.3
-0.5
-
0.3·B0VDD
Schmitt1
-0.5
-
0.3·B0VDD
VIL
Schmitt2
-0.5
-
0.2·B0VDD
Schmitt4 (B0VDD=VPOC~3.0)
Schmitt4 (B0VDD=3.0~5.5)
IOH = -5mAa
IOH = -100µA
IOL = 5mAa
-0.5
-
0.4·B0VDD
-0.5
-
0.5·B0VDD
B0VDD-1.0
-
-
-
High level output voltage
Low level output voltage
VOH
VOL
V
V
B0VDD-0.5
-
-
-
0.4
0.4
-
IOL = 100µA
-
-
Schmitt1
0.3
0.3
0.1
20
20
-
Input hysteresis of Schmit
VH
Schmitt2
-
-
V
Schmitt4
-
-
Internal pull-up resistor
RU
RD
40
40
100
100
kꢀ
kꢀ
Internal pull-down resistor
High level port output
current
IOH
IOL
ILIH
ILIL
Power supply of PgB0
Power supply of PgB0
VI =B0VDD
-
-
-
-
-
-
-
-
-
-
-
-
-150
150
mA
mA
µA
µA
µA
µA
Low level port output
current
High level input leakage
current
0.5
-0.5
0.5
Low level input leakage
current
VI = 0V
High level output leakage
current
ILOH VO = B0VDD
ILOL VO = 0V
Low level output leakage
current
-0.5
Slow mode
fO
-
-
-
-
-
-
-
-
-
-
-
-
25
40
15
8
Output frequency
Rise time (output)
MHz
Fast mode
Slow mode
tKRP
ns
ns
ns
ns
Fast mode
Slow mode
tKFP
15
8
Fall time (output)
Fast mode
a)
The maximum number of PgB0 pins with ‘ON’ signal at the same time is 5 in ‘Slow mode’ (Except the pins
related to the external memory interface (MEMC)).
The maximum number of PgB0 pins with ‘ON’ signal at the same time is 8 in ‘Fast mode’.
See the UM for the related description of the Port drive strength control.
R01DS0144ED0100
Electrical Target Specification
37
Chapter 6
I/Ospecification
6.1.5 PgA0 and PgA1
Table 6-5 PgA0 and PGA1 characteristics
Ratings
Parameter
Symbol
Condition
Unit
Max
Min
Typ
High level input voltage
Low level input voltage
VIH
VIL
CMOS
CMOS
0.7·AnVDD
-
-
-
-
-
-
AnVDD+0.3
V
V
-0.5
0.3·AnVDD
IOH = -1mA
IOH = -100µA
IOL = 1mA
AnVDD-1.0
-
High level output voltage
Low level output voltage
VOH
VOL
V
V
AnVDD-0.5
-
-
-
0.4
0.4
IOL = 100µA
High level port output
current
Power supply of PgA0 and
PgA1
IOH
IOL
ILIH
ILIL
-
-
-
-
-
-
-
-
-
-
-
-
-20
20
mA
mA
µA
µA
µA
µA
Low level port output
current
Power supply of PgA0 and
PgA1
High level input leakage
current
VI = AnVDD
VI = 0V
0.2
-0.2
0.2
-0.2
Low level input leakage
current
High level output leakage
current
ILOH VO = AnVDD
ILOL VO = 0V
Low level output leakage
current
Output frequency
Rise time (output)
Fall time (output)
fO
-
-
-
-
-
-
25
15
15
MHz
ns
tKRP
tKFP
ns
R01DS0144ED0100
Electrical Target Specification
38
Chapter 7
Peripheralsspecification
Chapter 7 Peripherals specification
7.1 Reset timing
Ratings
Unit
Parameter
Symbol
tWRSH
tWRSL
Condition
Min
450
4.7
Typ
Max
Highspeed OSC is operating
Highspeed OSC is stopped
Highspeed OSC is operating
Highspeed OSC is stopped
-
-
-
-
-
-
-
-
ns
µs
ns
µs
RESET input High level width
RESET input Low level width
450
4.7
tWRSL
tWRSH
_RESET
7.2 NMI timing
Ratings
Parameter
Symbol
Condition
Unit
Min
300
300
Typ
Max
NMI input High level width
NMI input Low level width
tWNIH
tWNIL
-
-
-
-
ns
ns
tWKRH
tWKRL
KRn
R01DS0144ED0100
Electrical Target Specification
39
Chapter 7
Peripheralsspecification
7.3 INTP timing
Ratings
Unit
Parameter
Symbol
Condition
Min
300
300
Typ
Max
INTPn input High level width
INTPn input Low level width
tWITH
tWITL
-
-
-
-
ns
ns
tWITH
tWITL
INTPn
7.4 FLMD0 timing
Ratings
Parameter
Symbol
Condition
Unit
Min
300
300
82
Typ
Max
FLMD0 input High level width
FLMD0 input Low level width
FLMD0 external pull down resistor
tWMDH
tWMDL
RFLMD0
-
-
-
-
-
-
ns
ns
kꢀ
tWMDL
tWMDH
FLMD0
7.5 _DCUTRST timing
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
_DCUTRST input High level width
_DCUTRST input Low level width
tWRH
450
450
-
-
-
-
ns
ns
tWTRL
tWTRL
tWTRH
_TRST
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Chapter 7
Peripheralsspecification
7.6 Timer timing
Table 7-1 Timer timing
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
TAUAnI input High level
width
a,b
tTAIH
tTAIL
tTBIH
tTBIL
tTJIH
tTJIH
tTJIH
tTJIL
tTJIL
tTJIL
n=0
-
-
ns
ns
ns
ns
ns
µs
ns
ns
µs
ns
TAUAnI input Low level
width
a,b
n=0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
TAUBnI input High level
width
a b
n=1
,
TAUBnI input Low level
width
a,b
n=-1
n=0,1
TAUJnI input High level
width
300
4.7
b
TAUJnI input High level
width
TAUJnI input High level
width
TAUJnI input Low level
width
n=0,1
300
TAUJnI input Low level
width
4.7
TAUJnI input Low level
width
b
TAUAnO output cycle
TAUBnO output cycle
TAUCnO output cycle
TAUJnO output cycle
tTACYK
tTBCYK
tTCCYK
tTJCYK
n=0
-
-
-
-
-
-
-
-
20
20
20
20
MHz
MHz
MHz
MHz
n=1
n=2-7
n=0,1
TAPAnESO input High level
width
tWESH
tWESL
n=0
n=0
300
300
-
-
-
-
ns
ns
TAPAnESO input Low level
width
ENCAnTmIN high level
width
a,b
a,b
a,b
a,b
tWENmH n=0, m=A,B,Z
tWENmL n=0, m=A,B,Z
tWENmH n=0, m=0-1
tWENmL n=0, m=0-1
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ENCAnTmIN low level width
ENCAnTINm high level
width
ENCAnTINm low level width
a)
With digital noise filter enabled: 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in Noise
filter macro. More than 1 PCLK width of Timer macro must be kept regarding DNF pass through pulse width.
With digital noise filter disabled: 1xtSYNC+20 ( tSYNC: 1 PCLK of Timer macro)
b)
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Peripheralsspecification
tTAIH
tTBIH
tTJIH
tTAIL
TBIL
t
tTJIL
TAUAnI
TAUBnI
TAUJnI
tTACYK
tTBCYK
tTCC YK
tTJCYK
TAUAnO
TAUBnO
TAUCnO
TAUJnO
WESH
t
tWESL
TAPAnESO
tWENmH
tWENmL
ENCAnTmIN
ENCAnTINm
7.7 Multiplexed bus timing
Table 7-2 MEMC0CLK timing
Ratings
Typ Max
Parameter
Symbol
Condition
Unit
Min
MEMC0CLK output cycle
MEMC0CLK high level width
MEMC0CLK low level width
MEMC0CLK rise time
tMEMC
tWKHMEM
tWKLMEM
tKRMEM
tKFMEM
25
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
tMEMC / 2 - 10
tMEMC / 2 - 10
-
-
-
10
10
MEMC0CLK fall time
tMBMC
tWKHMBM
tWKLMBM
MEMC0CLK
tKRMBM
tKF MB M
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Chapter 7
Peripheralsspecification
7.7.1 MEMC0CLK asynchronous timing
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
Bus operational period
T
-
25
-
-
ns
ns
Address setup time to
MEMC0ASTBZ (f)
tSAST
<1>
<2>
<3>
<4>
(1+ASW)·T-15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Address hold time from
MEMC0ASTBZ (f)
tHSTA
tFRDA
tHRDA
(1+AHW)·T-15
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address float delay time from
MEMC0RDZ (f)
-
6
Address hold time from
MEMC0RDZ (r)
0
-
Data input delay time from
MEMC0RDZ (f)
tDRDID <5>
tHRDID <6>
tDSTRD <7>
tDSTWR <8>
tWRDST <9>
tDWROD <10>
6
(1+w)·T-35
Data input hold time from
MEMC0RDZ (r)
0
-
-
Delay time from ASTB(f) to
MEMC0RDZ (f)
(1+AHW)·T-15
Delay time from ASTB(f) to
MEMC0WRZ (f)
(1+AHW)·T-15
-
MEMC0RDZ, MEMC0WRZ
low level width
(1+w)·T-10
-
Data output delay time from
MEMC0WRZ (f)
-
10
-
Address hold time from
MEMC0WRZ (r)
tHWRA
<11>
T-15
Data output setup time to
MEMC0WRZ (r)
tSODWR <12>
(1+w)·T-15
-
Data output hold time from
MEMC0WRZ (r)
tHWROD <13>
T-15
-
MEMC0WAITZ setting delay
from MEMC0ASTBZ (f)
(1+AHW)·T -
(2·HEAPCLK+35)
tSSTWT1 <14>
-
-
MEMC0WAITZ hold time from
MEMC0ASTBZ (f)
(1+w+AHW)·T -
(2·HEAPCLK+35)
tSSTWT2 <15> w≥1
tHSTWT1 <16> w≥1
tHSTWT2 <17> w≥1
MEMC0WAITZ setting delay
from Address
(w+AHW)·T-
(2*HEAPCLK+20)
-
-
MEMC0WAITZ hold time from
Address
(1+w+AHW)·T-
2*HEAPCLK+20)
Notes 1. ASW: Number of Address Setup Wait for multiplex bus
2. AHW: Number of Address Hold Wait for multiplex bus
3. w: Number of data wait
4. In case the bus operational period (T) is shorter then 41ns, tDRDID
requires at least 1 data wait (w=1).
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Peripheralsspecification
(1) Multiplex write cycle (Asynchronous; 1 data wait)
T1
TA
TDEW
T2
TDHW
MEMC0CLK
(output)
MEMC0CSZ4-2
(output)
MEMC0A18-16
(output)
Address
MEMC0AD15-0
(I/O)
Address
Data
<1>
<2>
<8>
MEMC0ASTBZ
(output)
<12>
<11>
<13>
<10>
MEMC0WRZ
(output)
<9>
<14>
<16>
<15>
<17>
MEMC0WAITZ
(input)
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Chapter 7
Peripheralsspecification
(2) Multiplex read cycle (Asynchronous; 1 data wait)
T1
TA
TDEW
T2
MEMC0CLK
(output)
MEMC0CSZ4-2
(output)
MEMC0A18-16
output)
Address
MEMC0AD15-0
(I/O)
Data
Address
<1>
<2>
<7>
MEMC0ASTBZ
(output)
<3>
<4>
<6>
<5>
MEMC0RDZ
(output)
<9>
<14>
<16>
<15>
<17>
MEMC0WAITZ
(input)
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Chapter 7
Peripheralsspecification
7.7.2 MEMC0CLK synchronous timing
Ratings
Unit
Min Typ Max
Parameter
Symbol
Condition
Bus operational period
T
25
0
-
-
-
ns
ns
Delay time from MEMC0CLK (r) to
address
tDKA
<18>
<19>
<20>
12
Delay time from MEMC0CLK (r) to
address float
tFKA
0
0
-
-
-
-
-
-
12
11
6
ns
ns
ns
ns
ns
ns
Delay time from MEMC0CLK (r) to
ASTB (f)
tDKST
Delay time from MEMC0CLK (r) to
MEMC0RDZ and MEMC0WRZ
tDKRDWR <21>
-2.5
10
2.5
-
Data input setup time
(from MEMC0CLK (r))
tSIDK
tHKID
tDKOD
<22>
<23>
<24>
-
Data input hold time
(from MEMC0CLK (r))
-
Data output delay time
(from MEMC0CLK (r))
11
<25> B0VDD≥3.5V
23
27
-
-
-
-
ns
ns
MEMC0WAITZ setup time
(to MEMC0CLK (r))
tSWTK
tHKWT
<25> B0VDD<3.5V
MEMC0WAITZ hold time
(from MEMC0CLK (r))
<26>
2.5
-
-
ns
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Chapter 7
Peripheralsspecification
(1) Multiplex write cycle (Synchronous; 1 data wait)
T1
TA
TDEW
TDEW
T2
TDHW
MEMC0CLK
(output)
<18>
MEMC0CSZ4-2
(output)
<24>
MEMC0A18-16
(output)
Address
MEMC0AD15-0
(I/O)
Address
Data
<20>
MEMC0ASTBZ
(output)
<21>
<21>
MEMC0WRZ
(output)
<25>
<26>
<25>
<26>
MEMC0WAITZ
(input)
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Chapter 7
Peripheralsspecification
(2) Multiplex read cycle (Synchronous; 1 data wait)
T1
TA
TDEW
TDEW
T2
MEMC0CLK
(output)
<18>
<19>
MEMC0CSZ4-2
(output)
MEMC0A18-16
output)
Address
<22>
<23>
MEMC0AD15-0
(I/O)
Data
Address
<20>
MEMC0ASTBZ
(output)
<21>
<21>
MEMC0RDZ
(output)
<25>
<26>
<25>
<26>
MEMC0WAITZ
(input)
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Chapter 7
Peripheralsspecification
7.8 CSI timing
7.8.1 Master modes
(1) CSIG timing
Table 7-3 CSIG timing (Master mode)
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ Max
Macro Operation clock cycle
time
tKCYGn
12.5
-
-
ns
CSIGnSC cycle time
tKCYMGn
tKWHMGn
tKWLMGn
100
-
-
-
-
-
-
ns
ns
ns
CSIGnSC high level width
CSIGnSC low level width
0.5 · tKCYMGn-10
0.5 · tKCYMGn-10
CSIGnSI setup time
(vs. CSIGnSC )
tSSIMGn CSIGnSC@PDSC=1
tSSIMGn CSIGnSC@PDSC=0
tHSIMGn
30
38
0
-
-
-
-
-
-
ns
ns
ns
ns
CSIGnSI setup time
(vs. CSIGnSC )
CSIGnSI hold time
(vs. CSIGnSC)
-
CSIGnSO output delay
(vs. CSIGnSC)
tDSOMGn
-
7
CSIGnRYI setup time
(vs. CSIGnSC)
CSIGnCTL1.CSIGnSIT=x
tSRYIGn
2 · tKCYGn+25
tKCYGn- 5.0
-
-
-
-
ns
ns
CSIGnCTL1.CSIGnHSE=1
CSIGnRYI High level width
tWRYIGn CSIGnCTL1.CSIGnHSE=1
Note n: Number of macro instances. Refer to the User Manual for the detailed
specification.
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Peripheralsspecification
(2) CSIH timing master mode
Table 7-4 CSIH timing (Master mode)
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ Max
Macro Operation clock cycle
time
tKCYHn
12.5
-
-
ns
CSIHnSC cycle time
tKCYMHn
tKWHMHn
tKWLMHn
100
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
CSIHnSC high level width
CSIHnSC low level width
0.5 · tKCYMHn-10
0.5 · tKCYMHn-10
CSIHnSC@PDSC=1
CSIHnSC@PDSC=0
30
38
CSIHnSI setup time
(vs. CSIHnSC )
tSSIMHn
CSIHnSI hold time
(vs. CSIHnSC)
tHSIMHn
tDSOMHn
tSRYIHn
0
-
-
-
-
ns
ns
CSIHnSO output delay
(vs. CSIHnSC)
7
CSIHnRYI setup time
(vs. CSIHnSC)
CSIHnCTL1.CSIHnSIT=x
CSIHnCTL1.CSIHnHSE=1
2 · tKCYHn+25
tKCYHn- 5.0
-
-
-
-
-
-
ns
ns
ns
CSIHnRYI High level width
tWRYIHn CSIHnCTL1.CSIHnHSE=1
tWSCSBHn
CSIHnCSS0-7 inactive
width
CSIDLE ×
tKCYMHn - 5.0
CSSETUP ×
tKCYMHn-5.0
tSSCSBHn0 CSIHnCTL1.CSIHnDAP=0
tSSCSBHn1 CSIHnCTL1.CSIHnDAP=1
tHSCSBHn0 CSIHnCTL1.CSIHnSIT=0
tHSCSBHn1 CSIHnCTL1.CSIHnSIT=1
-
-
-
-
-
-
-
-
ns
ns
ns
ns
CSIHnCSS0-7 setup time
( vs. CSIHnSC )
(CSSETUP + 0.5 ) ×
tKCYMHn-5.0
CSHOLD ×
tKCYMHn-10.0
CSIHnCSS0-7 hold time
( vs. CSIHnSC )
(CSSHOLD + 0.5) ×
tKCYMHn-5.0
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. CSSETUP: Value of CSIHnCFG0-7.CSIHnSP0-7[3:0]
3. CSHOLD: Value of CSIHnCFG0-7.CSIHnHD0-7[3:0]
4. CSIDLE: Value of CSIHnCFG0-7.CSIHnID0-7[2:0]
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Peripheralsspecification
(3) Timing diagrams
SCKO / SI / SO
CSIG ( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0 / 0 or 1 / 1 )
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0 /0 or 1/1 )
KCYGn
t
tKCYHn
Clock
KCYMGn
t
tKCYMHn
tKWLMGn
tKWLMHn
tKW HMGn
tKW HMHn
CSIGnSC
CSIHnSC
tDSOMGn
tDSOMHn
CSIGnSO
CSIHnSO
tSSIMGn
tSSIMHn
tHSIMGn
tHSIMHn
CSIGnSI
CSIHnSI
CSIG( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1 / 0 or 0 / 1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/ 0 or 0/ 1 )
KCYGn
t
tKCYHn
Clock
KCYMGn
t
tKCYMHn
tKWHMGn
tKWHMHn
tKW LMGn
tKW LMHn
CSIGnSC
CSIHnSC
tDSOMGn
tDSOMHn
CSIGnSO
CSIHnSO
tSSIMGn
tSSIMHn
tHSIMGn
tHSIMHn
CSIGnSI
CSIHnSI
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Peripheralsspecification
RYI
CSIGnCTL1 : CSIGnHSE=1, CSIGnCTL1 : CSIGnSIT = 0 )
CSIHnCTL1 : CSIHnHSE=1, CSIHnCTL1 : CSIHnSIT = 0 )
CSIG (CSIGnCTL1 :CSIGnCKR= 0)
CSIH (CSIHnCFGm:CSIHnCKPm= 0)
KCYGn
t
tKCYHn
Clock
tSRYIGn
tSRYIHn
CSIGnSC
CSIHnSC
tWRYIGn
tWRYIHn
CSIGnRYI
CSIHnRYI
CSIG (CSIGnCTL1 :CSIGnCKR= 1)
CSIH (CSIHnCFGm:CSIHnCKPm= 1)
t
tKKCCYYGHnn
Clock
t
tSSRRYYIIGHnn
CSIGnSC
CSIHnSC
t
tWWRRYYIIGHnn
CSIGnRYI
CSIHnRYI
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Chapter 7
Peripheralsspecification
CSSn
CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 0
tKCYHn
Clock
CSIHnSC
tSSCSBHn0
CSIHnCSS0-7
CSIHnSO
CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 1
tKCYHn
Clock
CSIHnSC
tSSCSBHn1
CSSETUP
x
tKCYMHn
0.5x tKCYMHn
CSIHnCSS0-7
CSIHnSO
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Peripheralsspecification
CSIHnCTL1 : CSIHnSIT=0, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm:
CHIHnDAPm= 0
tKCYHn
Clock
CSIHnSC
tHSCSBHn0
CSHnCSS0-7
CSIHnCTL1 : CSIHnSIT=1, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm:
CHIHnDAPm= 0
tKCYHn
Clock
CSIHnSC
tHSCSBHn1
0.5
x
tKCYMHn
CSHOLD
x
tKCYMHn
CSHnCSS0-7
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Peripheralsspecification
7.8.2 Slave mode
(1) CSIG timing slave mode
Table 7-5 CSIG timing (Slave mode)
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ Max
Macro Operation clock cycle
time
tKCYGn
12.5
-
-
ns
CSIGnSC cycle time
tKCYSGn
tKWHSGn
tKWLSGn
200
-
-
-
-
-
-
ns
ns
ns
CSIGnSC high level width
CSIGnSC low level width
0.5 · tKCYSGn-10
0.5 · tKCYSGn-10
CSIGnSI setup time
(vs. CSIGnSC )
tSSISGn
tHSISGn
20
-
-
-
-
ns
ns
CSIGnSI hold time
(vs. CSIGnSC)
tKCYGn+5.0
SO output delay (vs SCKI)
CSIGnRYO output delay
tDSOSGn
tSRYOGn
-
-
-
-
35
35
ns
ns
_CSIGnSSI setup time (vs
CSIGnSC)
tSSSISGn
tHSSISGn
0.5 · tKCYSn-5.0
tKCY+5.0
-
-
-
-
ns
ns
_CSIGnSSI hold time (vs
CSIGnSC)
Note n: Number of macro instances. Refer to the User Manual for the detailed
specification.
(2) CSIH timing slave mode
Table 7-6 CSIH timing (Slave mode)
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ Max
Macro Operation clock cycle
time
tKCYHn
12.5
-
-
ns
CSIHnSC cycle time
tKCYSHn
tKWHSHn
tKWLSHn
200
-
-
-
-
-
-
ns
ns
ns
CSIHnSC high level width
CSIHnSC low level width
0.5 · tKCYSHn-10
0.5 · tKCYSHn-10
CSIHnSI setup time
(vs. CSIHnSC )
tSSISHn
tHSISHn
20
-
-
-
-
ns
ns
CSIHnSI hold time
(vs. CSIHnSC)
tKCYHn+5.0
SO output delay (vs SCKI)
CSIHnRYO output delay
tDSOSHn
tSRYOHn
-
-
-
-
35
35
ns
ns
CSIHnSSI setup time
(vs. CSIHnSC)
tSSSISHn
tHSSISHn
0.5 · tKCYSn-5:0
tKCYn* 5.0
-
-
-
-
ns
ns
CSIHnSSI hold time
(vs. CSIHnSC)
Note n: Number of macro instances. Refer to the User Manual for the detailed
specification.
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Chapter 7
Peripheralsspecification
(3) Timing diagrams
SCKO / SI / SO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0 or 1/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0 or 1/1)
KCYGn
t
tKCYHn
Clock
KCYSGn
t
tKCYSHn
tKWLSGn
tKWLSHn
tKWHSGn
tKWHSHn
CSIGnSC
CSIHnSC
tDSOSGn
tDSOSHn
CSIGnSO
CSIHnSO
tSSISGn
tSSISHn
tHSISGn
tHSISHn
CSIGnSI
CSIHnSI
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0 or 0/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0 or 0/1)
KCYGn
t
tKCYHn
Clock
KCYSGn
t
tKCYSHn
tKWHSGn
tKWHSHn
tKWLSGn
tKWLSHn
CSIGnSC
CSIHnSC
tDSO SGn
tDSO SHn
CSIGnSO
CSIHnSO
tSSISGn
tSSISHn
tHSISGn
tHSISHn
CSIGnSI
CSIHnSI
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Chapter 7
Peripheralsspecification
RYO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0)
CSIGnSC
CSIHnSC
t
tSSRRYYOOGHnn
CSIGnRYO
CSIHnRYO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/1)
CSIGnSC
CSIHnSC
t
tSSRRYYOOGHnn
CSIGnRYO
CSIHnRYO
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0)
CSIGnSC
CSIHnSC
t
tSSRRYYOOGHnn
CSIGnRYO
CSIHnRYO
CSIHnTIC
CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/1)
CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/1)
CSIGnSC
CSIHnSC
t
tSSRRYYOOGHnn
CSIGnRYO
CSIHnRYO
R01DS0144ED0100
Electrical Target Specification
57
Chapter 7
Peripheralsspecification
SSI:
CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 :
CHIGnDAP0 = 0/0 or 1/1)
CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm /
CSIHnCFGm : CHIHnDAPm = 0/0 or 1/1)
CSIGnSC
CSIHnSC
tSSSISGn
HSSISGn
t
tSSSISHn
tHSSISHn
_CSIGnSSI
_CSIHnSSI
Hi-Z
CSIGnSO
CSIHnSO
CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 :
CHIGnDAP0 = 1/0 or 0/1 ) n=0, 4
CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm /
CSIHnCFGm : CHIHnDAPm = 1/0 or 0/1)
CSIGnSC
CSIHnSC
tSSSISGn
tSSSISHn
tHSSISGn
tHSSISHn
_CSIGnSSI
_CSIHnSSI
Hi-Z
CSIGnSO
CSIHnSO
7.9 UART timing
Ratings
Parameter
Transfer rate
Symbol
Condition
Unit
Min
Typ
Max
1.5
-
-
Mbps
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Electrical Target Specification
58
Chapter 7
Peripheralsspecification
7.10 FCN timing
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
Transfer rate
-
-
-
-
-
-
1
Mbps
ns
Internal delay time
CAN Node delay time
tINTDEL
tNODE
37.5
100
tCYCLE = 62.5ns
ns
CAN macro clock
toutput
FCnTX pin
( Transfer data )
tGATE
tCYCLE
FCnRX pin
( Receive data )
tINPUT = tGATE + tCYCLE
CAN node delay time (tNODE) = INPUT delay time (tinput) + Output delay time (toutput)
Internal delay time (tINTDEL) = Internal gate delay time (tGATE) + Output delay time (toutput)
FCnTX pin
Output delay time
V850E2/Fx4
CAN
macro
(tOUTPUT
)
Input delay time
(tINPUT
)
Input gate delay time
FCnRX pin
(tGATE
)
Image of Internal delay time
R01DS0144ED0100
Electrical Target Specification
59
Chapter 7
Peripheralsspecification
7.11 FlexRay timing
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
Transfer rate
-
-
-
-
-
-
-
-
10
Mbps
ns
FLX0TXDA, FLX0TXDB,
FLX0TXENA, FLX0TXENB
FLX0RXDA, FLX0RXDB
Node Output Delay
Node Input Delay
tOUTPUT
tINPUT
25
10
ns
uCOM device with
FlexRay macro
Node Output Delay
FlexRay macro
(internal system clock)
eray_sclk
FRTXDx
FRRXDx
I/O Port
I/O Port
I/O Buf
Pxx/TXDx
D Q
Q D
Pxx/RXDx
Node Input Delay
FRSCLK
(internal clock)
touput
FRTXDx
(macro output)
TXDx*
(chip output)
RXDx*
(chip input)
tinput
FRRXDx
(macro input)
R01DS0144ED0100
Electrical Target Specification
60
Chapter 7
Port
Peripheralsspecification
Ratings
Unit
Name
Condition
Min
Typ
Max
dTxENRISE-FALL
dCCTxEN01
dCCTxEN10
dCCTxAsym
Cload=25pF, measured at 20-80% E1VDD
-
-
-
-
-
-
-
-
-
-
9
ns
ns
ns
ns
ns
FLX0TXENA
FLX0TXENB
25
25
2.45
9
measured at 50% E1VDD
Cload=25pF, measured at 20-80% E1VDD
dCCTxDRISE25 +
dCCTxDFALL25
FLX0TXDA
FLX0TXDB
Cload=10pF, measured at 20-80% E1VDD
at the end of a 50ohm, 1ns microstripline
-
-
9
ns
dCCTxD01
dCCTxD10
-
-
-
-
-
-
25
25
ns
ns
measured at 50% of E1VDD
Input signal: Cload=25pF, 6.5ns (20-80%
E1VDD)
dCCRxAsmAccept
-
-
5.5
ns
-
-
-
-
-
C_CCRxD
uLogic_1
-
35
30
-
-
-
-
-
-
10
70
65
10
10
pf
%
%
ns
ns
FLX0RXDA
FLX0RXDB
uLogic_0
dCCRxD01
dCCRxD10
-
R01DS0144ED0100
Electrical Target Specification
61
Chapter 7
Peripheralsspecification
7.12 Ethernet timing (MII interface)
7.12.1 Transmission interface
(CL = 30pF)
Ratings
Unit
Item
Symbol Condition
Min
Typ
Max
ETH0TXD[3:0] delay vs ETH0TXCLK(r)
tDTKTD
tDTKTE
0
-
25
ns
ns
ETH0TXEN, ETH0TXER delay vs
ETH0TXCLK(r)
0
-
25
ETH0TXCLK clock period
ETH0TXCLK high level width
ETH0TXCLK low level width
tCYTK
tTKH
tTKL
40
-
-
-
-
ns
ns
ns
0.4·tCYTK
0.4·tCYTK
0.6·tCYTK
0.6·tCYTK
tCYTK
tTKH
tTKL
ETH0TXCLK
tDTKTD
ETH0TXD[3:0]
ETH0TXEN
ETH0TXER
tDTKTE
tDTKTE
R01DS0144ED0100
Electrical Target Specification
62
Chapter 7
Peripheralsspecification
7.12.2 Reception interface
(CL=30pF)
Ratings
Unit
Item
Symbol Condition
Min
Typ
Max
ETH0RXD[3:0] hold time vs
ETH0RXCLK(r)
tHRKRD
tSRDRK
tHRKRV
tSRVRK
5
-
-
ns
ns
ns
ns
ETH0RXD[3:0] setup time vs
ETH0RXCLK(r)
5
5
5
-
-
-
-
-
-
ETH0RXER, ETH0RXDV hold time vs
ETH0RXCLK(r)
ETH0RXER, ETH0RXDV setup time vs
ETH0RXCLK(r)
ETH0RXCLK clock period
ETH0RXCLK high level width
ETH0RXCLK low level width
tCYRK
tRKH
tRKL
40
-
-
-
-
ns
ns
ns
0.4·tCYRK
0.4·tCYRK
0.6·tCYRK
0.6·tCYRK
tRKL
tRKH
ETH0RXCLK
tHRKRD
tSRDRK
tCYRK
ETH0RXD[3:0]
ETH0RXDV
ETH0RXER
tHRKRV
tSRVRK
Management Interface
(CL = 30pF)
Ratings
Item
Symbol Condition
Unit
Min
Typ
Max
ETH0MDC clock period
tCYMDC
tDMCMD
tSMDMC
tHMCMD
400
0
-
-
-
-
-
ns
ns
ns
ns
ETH0MDO delay vs ETH0MDC(r)
ETH0MDI setup time vs ETH0MDC(r)
ETH0MDI hold time vs ETH0MDC(r)
300
50
50
-
-
R01DS0144ED0100
Electrical Target Specification
63
Chapter 7
Peripheralsspecification
7.13 IIC timing
Table 7-7 Normal mode
Parameter
Ratings
Unit
Symbol
Condition
Min
Typ Max
SCL clock period
fCLK
tBUF
0
100 kHz
Bus free time (between stop condition
and start condition)
4.7
4
-
-
-
-
µs
Start/Restart Hold time (New clock
pulse
is generated after this hold time as a
master.)
tHD:STA
µs
SCL clock low state hold time
SCL clock high state hold time
Setup time for start/restart condition
tLOW
tHIGH
4.7
4
-
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
ns
ns
ns
µs
pF
-
tSU:STA
4.7
5
-
CBUS compatible
IIC bus
-
-
Data hold time
tHD:DAT
0
Data setup time
tSU:DAT
tR
250
-
-
Rising transition time of SDA or SCL
Falling transition time of SDA or SCL
Setup time of stop condition
Bus capacitance
1000
300
-
tF
-
tSU:STO
Cb
4
-
400
R01DS0144ED0100
Electrical Target Specification
64
Chapter 7
Peripheralsspecification
Table 7-8 Fast mode
Parameter
Ratings
Unit
Symbol
Condition
Min
Typ Max
SCL clock period
fCLK
tBUF
0
-
-
400 kHz
Bus free time (between stop condition
and start condition)
1.3
0.6
-
-
µs
Start/Restart Hold time (New clock
pulse
is generated after this hold time as a
master.)
tHD:STA
-
µs
SCL clock low state hold time
SCL clock high state hold time
Setup time for start/restart condition
Data hold time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
-
-
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
ns
ns
ns
µs
ns
pF
0.6
0.6
-
IIC bus
0
0.9
-
Data setup time
100
Rising transition time of SDA or SCL
Falling transition time of SDA or SCL
Setup time of stop condition
Noise elimination width
20+0.1Cb
300
300
-
tF
20+0.1Cb
tSU:STO
tSP
0.6
0
50
400
Bus capacitance
Cb
-
tLOW
tR
tHI GH
tF
SCL0
tHD: STA
tHD: DAT
tSU:DAT
SDA0
tBUF
P
S
tSU:STO
tSU:STA
tSP
tHD: STA
Sr
P
Notes 1. P: Stop condition
Notes 1. S: Start condition
Notes 1. Sr: Restart condition
R01DS0144ED0100
Electrical Target Specification
65
Chapter 7
Peripheralsspecification
7.14 Frequency Output Function (FOUT)
Table 7-9 Frequency Output Function (FOUT)
Ratings
Typ Max
Parameter
Symbol
Condition
Unit
Min
CSCXFOUTP output cycle
CSCXFOUTP high level width
CSCXFOUTP low level width
CSCXFOUTP rise time
tFO
50
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
tWKHFO
tWKLFO
tKRFO
tKFFO
tFOUT / 2 - 10
tFOUT / 2 - 10
-
-
-
10
10
CSCXFOUTP fall time
tFO
tWKHFO
tWKLFO
CSCXFOUT
tKRFO
tKFFO
7.15 VLVI characteristics
Table 7-10 VLVI characteristics
Ratings
Parameter
Symbol
Condition
Unit
Min
1.8
Typ
Max
Detection voltage
Voltage slope1
Voltage slope2
Response timea
VRAMHF
Rvs1
1.9
2.0
1800
1800
2
V
0.18
0.0018
-
-
-
-
V/ms
V/ms
ms
Rvs2
tRAMHD
a)
From detection voltage to setting of VLVF bit (VLVF.bit0)
VDD
Rvs2
Rvs1
Detectvoltage(MAX.)
Detectvoltage(TYP.)
Detectvoltage(MIN.)
tRAMHD
tRAMHD
tRAMHD
Note VDD: REG0VDD
R01DS0144ED0100
Electrical Target Specification
66
Chapter 7
Peripheralsspecification
7.16 Voltage comparator characteristics
Ratings
Unit
Parameter
Symbol
Condition
Min
Typ
Max
VCMP current
IVCMP
VCMPR
VCMPF
VCVS
-
200
300
µA
V
Threshould voltage (rise)
Threshould voltage (fall)
Voltage slope
1.745 1.780 1.815
1.645 1.680 1.715
V
-
-
-
-
50
2
mV/µs
µs
Detection time
tVCMPD
VCMP operation readyness after
VCPC0OEn is set to 1
Stabilization time
tVCMPST
-
-
2
ms
VCPCnIN
VCMPR(MAX.)
VCMPR(TYP.)
VCMPR(MIN.)
VCMPF(MAX.)
VCMPF(TYP.)
VCMPF(MIN.)
tVCMPD
tVCMPD
VCPCnOUT
n=0,1
R01DS0144ED0100
Electrical Target Specification
67
Chapter 7
Peripheralsspecification
7.17 LVI characteristics
Table 7-11 LVI characteristics
Ratings
Unit
Parameter
Symbol
Condition
Min
3.9
Typ
4.0
3.7
3.5
-
Max
VLVI0
VLVI1
VLVI2
LVS1
LVS2
tLD
LVICNT.LVICNT[2:0]=001B
LVICNT.LVICNT[2:0]=010B
LVICNT.LVICNT[2:0]=011B
4.1
V
V
Detection voltage
3.6
3.8
3.4
3.6
V
Voltage slope1
Voltage slope2
Response time
VDD minimum width
0.18
0.0018
-
1800
1800
2.0
V/ms
V/ms
ms
ms
-
-
tLW
2
-
-
LVICNT0,1 is set to 1, then LVI is
ready to operate
Stabilization time
tLVIST
-
-
350
µs
VDD
LVS2
Detect voltage(MAX.)
Detect voltage(TYP.)
Detect voltage(MIN.)
LVS1
tLW
tLD
tLD
R01DS0144ED0100
Electrical Target Specification
68
Chapter 7
Peripheralsspecification
7.18 A/D Converter characteristics
7.18.1 12bit A/D (for ADC channels without S/H functionality)
Table 7-12 12bit A/D
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
12
Resolution
RESn
TCONn
TOEn
ILEn
12
12
-
bit
µs
Total conversion time
Overall errora
1.5
10
-
-
±6.0
±2.5
±1.5
±5.0
±5.0
AnVREFP
1
LSB
LSB
LSB
LSB
LSB
V
Non-liniarity errora
Differencial liniarity errora
Zero scale errora
-
-
DLEn
ZSEn
FSEn
VAIN
-
-
-
-
Full scale errora
-
-
Analog input voltagea
Power on stabilization timeb
AnVREFM
-
-
µs
ADAnBPC=0, withDiagnosis
function
-
-
-
-
4.0
6.3
8.1
7.4
9.2
mA
mA
mA
mA
ADAnBPC=0, w/o Diagnosis
function
5.2
4.6
6.2
AIDDn
AnVDD current
ADAnBPC=1, with Diagnosis
function
ADAnBPC=1, w/o Diagnosis
function
AIDDnPD Power down
-
1
650
-
-
µA
AnVREFP current
AIREFn
-
-
µA
TESHn AnVDD was converted
TESHLn3 2/3 AnVDD was converted
TESHLn2 1/2 AnVDD was converted
TESHLn1 1/3 AnVDD was converted
TESLn AGND was converted
4015
2691
2018
1325
0
4095
2771
2078
1405
80
LSB
LSB
LSB
LSB
LSB
2731
2048
1365
-
Conversion result by
Diagnosis functionc
a)
The specification does not include the quantization error.
‘Power on’ refers to
b)
- setting ADCAnGPS = 1
The values given do not include influence of injected current
c)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
R01DS0144ED0100
Electrical Target Specification
69
Chapter 7
Peripheralsspecification
7.18.2 12bit A/D (For channel ADCA0I0-5 when the S/H function is
not used)
Table 7-13 12bit A/D (When channel Sample & Hold function is not used)
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
12
Resolution
RES0SN
TCON0SN
TOE0SN
ILE0SN
12
12
-
bit
µs
Total conversion time
Overall errora
1.5
10
-
-
±6.0
±2.5
±1.5
±5.0
±5.0
A0VREFP
1
LSB
LSB
LSB
LSB
LSB
V
Non-liniarity errora
Differencial liniarity errora
Zero scale errora
-
-
DLE0SN
ZSE0SN
FSE0SN
VAIN0SN
-
-
-
-
Full scale errora
-
-
Analog input voltagea
Power on stabilization timeb
A0VREFM
-
-
-
µs
ADA0BPC=0, withDiagnosis
function
-
-
-
-
4.0
5.2
4.6
6.2
6.3
8.1
7.4
9.2
mA
mA
mA
mA
ADA0BPC=0, w/o Diagnosis
function
AIDD0SN
A0VDD current
ADA0BPC=1, with Diagnosis
function
ADA0BPC=1, w/o Diagnosis
function
AIDD0SNPD Power down
-
1
650
-
-
µA
A0VREFP current
AIREF0SN
-
-
µA
TESH0SN A0VDD was converted
TESHL0SN3 2/3 A0VDD was converted
TESHL0SN2 1/2 A0VDD was converted
TESHL0SN1 1/3 A0VDD was converted
TESL0SN AGND was converted
4015
2691
2018
1325
0
4095
2771
2078
1405
80
LSB
LSB
LSB
LSB
LSB
2731
2048
1365
-
Conversion result by
Diagnosis functionc
a)
The specification does not include the quantization error.
‘Power on’ refers to
b)
- setting ADCAnGPS = 1
The values given do not include influence of injected current
c)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
R01DS0144ED0100
Electrical Target Specification
70
Chapter 7
Peripheralsspecification
7.18.3 12bit A/D (When channel S/H function is used)
Table 7-14 12bit A/D (When channel Sample & Hold function is used [ADCA0I0 to
ADCA0I5])
Ratings
Parameter
Symbol
Condition
Unit
Min
12
1.8
50
-
Typ
Max
Resolution
RES0S
12
-
12
bit
µs
Total conversion time
Sample & Hold time
Overall errora
TCON0SN
12
-
-
±8.0
µs
TOE0S
ILE0S
-
LSB
LSB
LSB
LSB
LSB
V
Non-liniarity errora
Differencial liniarity errora
Zero scale errora
Full scale errora
-
-
±4.0
DLE0S
ZSE0S
FSE0S
VAIN0S
-
-
±2.5
-
-
±6.0
-
-
±6.0
Analog input voltage
0.2
-
A0VREFP-0.2
Power on stabilization
timeb
-
-
1
µs
withDiagnosis function
w/o Diagnosis function
-
Note3
Note3
1
22.1
24.0
-
mA
mA
µA
AIDD0S
A0VDD current
-
AIDD0SPD Power down
-
A0VREFP current
AIREF0S
-
650
-
µA
TESHLS3 2/3 A0VDD was converted
TESHLS2 1/2 A0VDD was converted
TESHLS1 1/3 A0VDD was converted
2689
2016
1323
2731
2048
1365
2773
2080
1407
LSB
LSB
LSB
Conversion result by
Diagnosis functionc
a)
The specification does not include the quantization error.
‘Power on’ refers to
b)
- setting ADCAnGPS = 1
The values given do not include influence of injected current
c)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
3. AIDDn + 1.72mA x (number of channels used with S/H)
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Electrical Target Specification
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Chapter 7
Peripheralsspecification
7.18.4 10bit A/D (for ADC channels without S/H functionality)
Table 7-15 10 bit A/D
Ratings
Typ
Parameter
Symbol
Condition
Unit
Min
Max
10
Resolution
RESn
TCONn
TOEn
ILEn
10
10
bit
µs
Total conversion time
Overall errora
1.5
10
Excluding quantization error
-
-
-
-
-
-
±2.0
±1.5
±1.0
±1.5
±1.5
AnVREFP
1
LSB
LSB
LSB
LSB
LSB
V
Non-liniarity errora
Differencial liniarity errora
Zero scale errora
-
DLEn
ZSEn
FSEn
VAIN
-
-
Full scale errora
-
Analog input voltagea
Power on stabilization timeb
AnVREFM
-
µs
ADAnBPC=0, withDiagnosis
function
-
-
-
-
4.0
5.2
4.6
6.2
6.3
8.1
7.4
9.2
mA
mA
mA
mA
ADAnBPC=0, w/o Diagnosis
function
AIDDn
AnVDD current
ADAnBPC=1, with Diagnosis
function
ADAnBPC=1, w/o Diagnosis
function
AIDDnPD Power down
-
-
1
-
µA
AnVREFP current
AIREFn
500
-
µA
TESHn AnVDD was converted
TESHLn3 2/3 AnVDD was converted
TESHLn2 1/2 AnVDD was converted
TESHLn1 1/3 AnVDD was converted
TESLn AGND was converted
1003
673
504
331
0
1023
693
520
351
20
LSB
LSB
LSB
LSB
LSB
683
512
341
Conversion result by
Diagnosis functionc
a)
The specification does not include the quantization error.
‘Power on’ refers to
b)
- setting ADCAnGPS = 1
The values given do not include influence of injected current
c)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
R01DS0144ED0100
Electrical Target Specification
72
Chapter 7
Peripheralsspecification
7.18.5 10bit A/D (For channel ADCA0I0-5 when the S/H function is
not used)
Table 7-16 10 bit A/D
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
10
Resolution
RES0SN
TCON0SN
TOE0SN
ILE0SN
10
10
bit
µs
Total conversion time
Overall errora
1.5
10
-
-
-
-
-
-
±2.0
±1.5
±1.0
±1.5
±1.5
AnVREFP
1
LSB
LSB
LSB
LSB
LSB
V
Non-liniarity errora
Differencial liniarity errora
Zero scale errora
-
DLE0SN
ZSE0SN
FSE0SN
VAIN0SN
-
-
Full scale errora
-
Analog input voltagea
Power on stabilization timeb
AnVREFM
-
-
µs
ADAnBPC=0, withDiagnosis
function
-
-
-
-
4.0
6.3
8.1
7.4
9.2
mA
mA
mA
mA
ADAnBPC=0, w/o Diagnosis
function
5.2
4.6
6.2
AIDD0SN
AnVDD current
ADAnBPC=1, with Diagnosis
function
ADAnBPC=1, w/o Diagnosis
function
AIDD0SNPD Power down
-
-
1
500
-
-
µA
AnVREFP current
AIREF0SN
-
µA
TESH0SN AnVDD was converted
TESHL0SN3 2/3 AnVDD was converted
TESHL0SN2 1/2 AnVDD was converted
TESHL0SN1 1/3 AnVDD was converted
TESL0SN AGND was converted
1003
673
504
331
0
1023
693
520
351
20
LSB
LSB
LSB
LSB
LSB
683
512
341
-
Conversion result by
Diagnosis functionc
a)
The specification does not include the quantization error.
‘Power on’ refers to
b)
- setting ADCAnGPS = 1
The values given do not include influence of injected current
c)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
3. AIDDn + 1.72mA x (number of channels used with S/H)
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Chapter 7
Peripheralsspecification
7.18.6 10bit A/D (When channel S/H function is used)
Table 7-17 10 bit A/D
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
10
Resolution
RES0S
10
10
-
bit
Total conversion time
Sample & Hold time
Overall errora
TCON0S
1.84
12.2
-
µs
50
-
-
µs
TOE0S
ILE0S
-
±2.5
±2.0
±1.5
±2.0
±2.0
LSB
LSB
LSB
LSB
LSB
Non-liniarity errora
Differencial liniarity errora
Zero scale errora
Full scale errora
-
-
DLE0S
ZSE0S
FSE0S
-
-
-
-
-
-
A0VREFP-
0.2
Analog input voltagea
VAIN0S
0.2
-
V
Power on stabilization timeb
-
-
-
1
µs
ADAnBPC=1, with Diagnosis
function
c
22.1
mA
AIDD0S
AnVDD current
ADAnBPC=1, w/o Diagnosis
function
c
-
24.0
mA
AIDD0SPD Power down
-
1
-
µA
µA
AnVREFP current
AIREF0S
-
500
683
512
341
-
TESHL0S3 2/3 AnVDD was converted
TESHL0S2 1/2 AnVDD was converted
TESHL0S1 1/3 AnVDD was converted
672
503
330
694
521
352
LSB
LSB
LSB
Conversion result by
Diagnosis functiond
a)
The specification does not include the quantization error.
‘Power on’ refers to
b)
- setting ADCAnGPS = 1
AIDDn x 1.72 x the number of used channels with Sample & Hold
The values given do not include influence of injected current
c)
d)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
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Electrical Target Specification
74
Chapter 7
Peripheralsspecification
7.18.7 Equivalent circuit
ADCAnIm
(n=0, m=0-23)
(n=1, m=0-23)
RIN
CIN
Terminals
Condition
RIN[kꢀ]
0.7
CIN[pF]
3.6
When S&H is used
ADCA0I0-ADCA0I5
ADA0BPC=0
ADA0BPC=1
1.6
12.6
7.1
When S&H is not
used
1.5
ADA0BPC=0
ADA0BPC=1
ADA0BPC=0
ADA0BPC=1
1.2
11.9
7.1
ADCA0I6-ADCA0I23
ADCA1I0-ADCA1I23
1.1
1.2
11.9
7.1
1.1
Caution These specifications are not tested in outgoing inspection. Therefore R and
IN
C
values are not guaranteed and are reference values only.
IN
Additionally these values are specified as maximum values.
7.18.8 ADTRG timing
Ratings
Parameter
Symbol
tWADH
tWADL
Condition
Unit
Min
Typ
Max
a
with digital noise filter
without digital noise filter
with digital noise filter
without digital noise filter
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ADCAnTRGm input High level width
ADCAnTRGm input Low level width
b
a
b
a)
b)
2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in noise filter).
More than 1 PCLK width of ADC macro must be kept regarding DNF pass through pulse width.
1 × tSYNC+20 ( tSYNC: 1 PCLK of ADC macro)
Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2. m: Number of channels. Refer to the User Manual for the detailed
specification.
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Chapter 7
Peripheralsspecification
tWADH
tWADL
ADCAn
7.19 Key Return
Table 7-18
Parameter
Ratings
Symbol
Condition
Unit
Min
300
300
Typ
Max
KRn input High level width
KRn input Low level width
tWKRH
tWKRL
-
-
-
-
ns
ns
Note n: Number of instances. Refer to the User Manual for the detailed specification.
tWNIH
tWNIL
NMI
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Electrical Target Specification
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Chapter 8
Memoryspecification
Chapter 8 Memory specification
8.1 Code flash specification
Table 8-1 Code flash
Ratings
Unit
Parameter
Symbol
Condition
Min
-
Typ
Max
100
85
Number of Re-Writesa
CWRT
Data retention 20 years
(A) grade products
-
-
-
times
°C
-40
-40
Programming
Temperature
tPRG
(A1) grade products
110
°C
a)
Please contact RENESAS sales office regarding specification other than the above.
8.2 Data flash specification
Table 8-2 Data flash
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
DWRT1
DWRT2
DWRT3
Data retention 20 years
Data retention 15 years
Data retention 5 years
(A) grade products
-
-
-
-
-
-
-
1000 times
5000 times
15000 times
Number of Re-Writesa
-
-40
-40
85
°C
°C
Programming
Temperature
tPRG
(A1) grade products
110
a)
Please contact RENESAS sales office regarding specification other than the above.
8.3 Serial write operation specification
Serial write operation
Ratings
Parameter
Symbol
Condition
Unit
Min
Typ
Max
-
FLMD0 setup time
RESET release
tDR
tPR
tRP
tPW
tR
1
2
-
-
ms
ms
ms
µs
-
-
FLMD0 pulse input start
FLMD0 low/high level width
FLMD0 raise time
FLMD0 fall time
100
-
10
-
-
-
-
-
-
100
20
20
50
54
ns
tF
-
ns
Programming time
Erase time
per 128 bit
per 4KB
-
µs
-
ms
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Electrical Target Specification
77
Chapter 9
Pinning and package specification
Chapter 9 Pinning and package specification
9.1 Pinning specification PBGA 272
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
E1VSS
FLMD0
P0_15
P0_10
P0_7
P0_4
P0_1
XT1
XT2
X1
JP0_5
JP0_2 VCPC0IN REG0VSS _RESET P24_3
P24_0
P21_3
P27_5
B0VSS
A
B
C
D
E
F
A
B
C
D
E
F
P4_10
P4_8
P4_5
P4_2
P3_12
P3_9
P3_6
P3_3
P2_3
P2_2
P1_13
P1_10
P1_7
P1_4
P1_1
P11_5
P11_2
P11_0
P4_11
P4_9
P4_6
P4_3
P4_0
P3_10
P3_7
P3_4
P3_1
P1_15
P1_12
P1_9
P1_6
P1_3
P11_7
P11_4
P11_1
P0_14
FVDD
P4_7
P4_4
P4_1
P3_11
P3_8
P3_5
P3_2
P3_0
P1_14
P1_11
P1_8
P1_5
P1_2
P11_6
P11_3
P0_11
P0_13
P0_8
P0_12
E0VSS
P0_5
P0_9
P0_2
P0_6
P0_0
P0_3
OSCVSS
X2
JP0_4
JP0_3
E0VSS
JP0_1 VCPC1IN REG0C
PWGD
P24_2
P24_1
P24_5
P21_2
CVDD
P21_4
B0VSS
P27_1
P27_2
P27_0
OSCVDD E0VSS
JP0_0
WAKE REG0VDD P24_4
B0VSS
E0VSS
E1VSS
E1VSS
E1VDD
E1VSS
E1VSS
E1VDD
E1VSS
E1VDD
E1VSS
E1VSS
E1VSS
E1VSS
E1VSS
A0VSS
E0VSS
E0VDD
E0VSS
E0VSS
E0VSS
E0VDD
E0VSS
E0VSS
CVSS
B0VSS
B0VSS
B0VDD
B0VSS
B0VSS
B0VDD
B0VSS
B0VSS
B0VDD
B0VSS
B0VSS
B0VSS
B0VSS
B0VSS
P12_0
P13_7
P25_15 P25_14 P25_13
P25_12 P25_11 P25_10
P25_9
P25_6
P25_3
P25_0
P21_1
P21_10
P13_2
P12_15
P25_8
P25_5
P25_2
P24_7
P21_0
P21_9
P13_3
P13_0
P25_7
P25_4
P25_1
P24_6
P21_11
P21_8
P21_7
P13_1
V850E2/FL4-H
G
H
J
G
H
J
E1VSS
E1VSS
E1VSS
E1VSS
B0VSS
E1VSS
E1VSS
E1VSS
B0VSS
B0VSS
B0VSS
E1VSS
B0VSS
B0VSS
B0VSS
B0VSS
K
L
K
L
M
N
P
R
T
M
N
P
R
T
P12_12 P12_13 P12_14
P12_9
P12_6
A1VSS
P12_10 P12_11
P12_7
P12_4
P12_8
P12_5
E1VSS
E1VSS
E1VSS
E1VSS
E1VSS
CVSS
E1VSS
CVDD
E1VDD
B0VSS
B0VDD
B0VSS
P21_6
P21_5
B0VSS
P24_14
P24_13
B0VSS
P13_5
P13_4
U
V
W
Y
U
V
W
Y
ADCA0I1
(P10_1)
P10_8
P10_11 P10_14
P10_12 P10_15
CVDD REG1VDD P24_10
B0VSS AVREFP1 AVREFM1
ADCA0I2 ADCA0I4
(P10_2) (P10_4)
E1VSS AVREFP0 P10_6
A0VDD AVREFM0 P10_7
P10_9
N.C. REG1VSS P27_4
P24_9
P12_2
B0VSS
A1VDD
ADCA0I0 ADCA0I3 ADCA0I5
(P10_0) (P10_3) (P10_5)
E1VSS
P10_10 P10_13
P2_0
P2_1
PTCTL1
P24_8
P24_11 P24_12 P24_15
P13_6
P12_1
P12_3
B0VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
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Electrical Target Specification
78
Chapter 9
Pinning and package specification
9.2 Package specification PBGA 272
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Electrical Target Specification
79
Revision History
Version
Date
Document number
Description
Initial release
Document was EASE-DS-0032-1.2
Changes:
- Added FLMD0 / FLMD1 resistor values
- Corrected timing diagram for wake-signal (chapter 3.5.5
Condition 4)
1.0
2013-05-24
R01DS0144ED0100
- Updated Power Supply Currents (chapter 5.1)
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Electrical Target Specification
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