R1EX24016ATA00I#S0 [RENESAS]

R1EX24016ATA00I#S0;
R1EX24016ATA00I#S0
型号: R1EX24016ATA00I#S0
厂家: RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述:

R1EX24016ATA00I#S0

可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路
文件: 总24页 (文件大小:288K)
中文:  中文翻译
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R1EX24016ASA00I  
R1EX24016ATA00I  
Two-wire serial interface  
16k EEPROM (2-kword × 8-bit)  
REJ03C0359-0002  
Preliminary  
Rev.0.02  
Jan.14, 2009  
Description  
R1EX24xxx series are two-wire serial interface EEPROM ogrammable  
ROM). They realize high speed, low power consumptility by employing  
advanced MNOS memory technology and CMOS prry technology. They  
also have a 16-byte page programming function tfaster.  
Features  
Single supply: 1.8 V to 5.5
Two-wire serial interfac
Clock frequency: 4
Power dissipatio
Standby:
Active (Read
Active (Write): 
Automatic page write: e/page  
Write cycle time: 5 ms  
Endurance: 1,000k Cycles @25°C  
Data retention: 100 Years @25°C  
Preliminary: The specifications of this device are subject to change without notice. Please contact your  
nearest Renesas Technology’s Sales Dept. regarding specifications.  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 1 of 20  
R1EX24016Axx00I  
Small size packages: SOP-8pin, TSSOP-8pin  
Shipping tape and reel  
TSSOP 8-pin: 3,000 IC/reel  
SOP 8-pin: 2,500 IC/reel  
Temperature range: 40 to +85°C  
Lead free products.  
Ordering Information  
Type No.  
Internal  
Operating voltage Frequency Package  
organization  
R1EX24016ASA00I  
16k bit  
(2048× 8-bit)  
1.8 V to 5.5 V  
400
0 mil 8-pin plastic SOP  
0008DF-B  
V)  
R1EX24016ATA00I  
16k bit  
(2048× 8-bit)  
1.8 V to 5.5 V  
astic TSSOP  
P0008JC-B  
TP-8DAV)  
Lead free  
Pin Arrangement  
SSOP  
3
4
8
7
6
5
VCC  
WP  
SCL  
SDA  
(Top view)  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 2 of 20  
R1EX24016Axx00I  
Pin Description  
Pin name  
A0 to A2  
SCL  
Function  
Device address  
Serial clock input  
Serial data input/output  
Write protect  
SDA  
WP  
VCC  
Power supply  
Ground  
VSS  
NC  
No connection  
Block Diagram  
e generator  
VCC  
VSS  
Memory array  
WP  
A0, A1, A2  
SCL  
Contr
lo
Y-select & Sense amp.  
Serial-parallel converter  
SDA  
Absolute Maximum Ratngs  
Parameter  
Symbol  
VCC  
Value  
Unit  
Supply voltage relative to VSS  
Input voltage relative to VSS  
Operating temperature range*1  
Storage temperature range  
0.6 to +7.0  
0.5*2 to +7.0*3  
40 to +85  
V
Vin  
V
Topr  
Tstg  
°C  
°C  
55 to +125  
Notes: 1. Including electrical characteristics and data retention.  
2. Vin (min): 3.0 V for pulse width 50 ns.  
3. Should not exceed VCC + 1.0 V.  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 3 of 20  
R1EX24016Axx00I  
DC Operating Conditions  
Parameter  
Symbol  
VCC  
Min  
1.8  
0
Typ  
Max  
5.5  
Unit  
V
Supply voltage  
VSS  
0
0
V
Input high voltage  
Input low voltage  
VIH  
V
CC × 0.7  
VCC + 0.5  
V
VIL  
0.3*1  
VCC × 0.3  
V
Operating temperature  
Topr  
40  
+85  
°C  
Notes: 1. VIL (min): 1.0 V for pulse width 50 ns.  
DC Characteristics (Ta = 40 to +85°C, VCC = 1.8 V to 5.5 V)  
Parameter  
Symbol Min  
Typ  
Max  
2.0  
2.0  
Un
ns  
Input leakage current  
Output leakage current  
Standby VCC current  
Read VCC current  
Write VCC current  
Output low voltage  
ILI  
0 to 5.5 V  
t = 0 to 5.5 V  
VCC  
ILO  
ISB  
1.0  
ICC1  
ICC2  
VOL2  
VOL1  
V, Read at 400 kHz  
= 5.5 V, Write at 400 kHz  
VCC = 2.7 to 5.5 V, IOL = 3.0 mA  
VCC = 1.8 to 2.7 V, IOL = 1.5 mA  
Capacitance (Ta = +25°C
Test  
Parameter  
Min  
Typ  
Max  
6.0  
Unit  
pF  
conditions  
Input capacitance
Vin = 0 V  
Output capacitance
I/O*1  
6.0  
pF  
Vout = 0 V  
Note: 1. Not 100% te
Memory cell charactercs (VCC = 1.8 V to 5.5 V)  
Ta=25°C  
Ta=85°C  
Notes  
Endurance  
1,000k Cycles min. 100k Cycles min  
100 Years min. 10 Years min.  
1
1
Data retention  
Notes: 1. Not 100% tested.  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 4 of 20  
R1EX24016Axx00I  
AC Characteristics (Ta = 40 to +85°C, VCC = 1.8 to 5.5 V)  
Test Conditions  
Input pules levels:  
VIL = 0.2 × VCC  
VIH = 0.8 × VCC  
Input rise and fall time: 20 ns  
Input and output timing reference levels: 0.5 × VCC  
Output load: TTL Gate + 100 pF  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
kHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ms  
Notes  
Clock frequency  
fSCL  
0  
Clock pulse width low  
Clock pulse width high  
Noise suppression time  
Access time  
tLOW  
tHIGH  
tI  
1200  
600  
1
tAA  
1
Bus free time for next mode  
Start hold time  
tBUF  
tHD.
Start setup time  
Data in hold time  
Data in setup time  
Input rise time  
300  
300  
1
1
Input fall time  
Stop setup time  
600  
50  
Data out hold time  
Write protect hold ti
Write protect setu
Write cycle time  
.WP  
tSU.WP  
tWC  
1200  
0
5
2
Notes: 1. Not 100% tes
2. tWC is the time froop condition to the end of internally controlled write cycle.  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 5 of 20  
R1EX24016Axx00I  
Timing Waveforms  
Bus Timing  
1/fSCL  
tLOW  
tR  
tF  
tHIGH  
SCL  
tSU.STA  
tHD.DAT  
tSU.DAT  
tHD.STA  
tSU.STO  
SDA  
(in)  
tBUF  
tAA  
tDH  
SDA  
(out)  
tSU.WP  
tHD.WP  
WP  
Write Cycle Timing  
dition  
Start condition  
SCL  
SDA  
tWC  
(Internally controlled)  
Write
(Address
ACK  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 6 of 20  
R1EX24016Axx00I  
Pin Function  
Serial Clock (SCL)  
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge  
clock data into EEPROM device and negative edge clock data out of each device. Maximum clock rate is  
400 kHz.  
Serial Input/Output Data (SDA)  
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that  
pin is open-drain driven structure. Use proper resistor value for your sysy considering VOL, IOL and  
the SDA pin capacitance. Except for a start condition and a stop condwill be discussed later,  
the SDA transition needs to be completed during the SCL low perio
Data Validity (SDA data change timing waveform)  
SCL  
SDA  
Data  
change  
Note:  
High-to-low and lould be done during the SCL low period.  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 7 of 20  
R1EX24016Axx00I  
Device Address (A0, A1, A2)  
One device can be wired for one common data bus line as maximum. All device address are used for  
memory address, corresponding device address pins must not be fixed.  
Pin Connections for A0 to A2  
Pin connection  
Max connect  
Memory size number  
A2  
A1  
A0  
Note  
16k bit  
1
×*1  
×*1  
×*1  
Use A0,A1,A2 for memory address a8,a9  
and a10  
Note: 1. Floating state can be possible.  
Write Protect (WP)  
When the Write Protect pin (WP) is high, the write prooperates as shown in  
the following table. When the WP is low, write ops are allowed. The read  
operation is always activated irrespective of the
Write Protect Area  
Wr
WP pin status  
VIH  
VIL  
eration  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 8 of 20  
R1EX24016Axx00I  
Functional Description  
Start Condition  
A high-to-low transition of the SDA with the SCL high is needed in order to start read, write operation  
(See start condition and stop condition).  
Stop Condition  
A low-to-high transition of the SDA with the SCL high is a stop condition. The stand-by operation starts  
after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the  
write data inputs and place the device in a internally-timed write cycle to temories. After the  
internally-timed write cycle which is specified as tWC, the device enters ode (See write cycle  
timing).  
Start Condition and Stop Condition  
SCL  
SDA  
(in)  
Start con
Stop condition  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 9 of 20  
R1EX24016Axx00I  
Acknowledge  
All addresses and data words are serially transmitted to and from in 8-bit words. The receiver sends a  
zero to acknowledge that it has received each word. This happens during ninth clock cycle. The  
transmitter keeps bus open to receive acknowledgment from the receiver at the ninth clock. In the write  
operation, EEPROM sends a zero to acknowledge after receiving every 8-bit words. In the read operation,  
EEPROM sends a zero to acknowledge after receiving the device address word. After sending read data,  
the EEPROM waits acknowledgment by keeping bus open. If the EEPROM receives zero as an  
acknowledge, it sends read data of next address. If the EEPROM receives acknowledgment "1" (no  
acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode.  
If the EEPROM receives neither acknowledgment "0" nor a stop condition, the EEPROM keeps bus open  
without sending read data.  
Acknowledge Timing Waveform  
1
2
9
SCL  
SDA IN  
Acknowledge  
out  
SDA OUT  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 10 of 20  
R1EX24016Axx00I  
Device Addressing  
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip  
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device  
address code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are  
used to distinguish device type and this EEPROM uses “1010” fixed code. The device address word is  
followed by the 3-bit device address code in the order of A2, A1, A0. The device address code selects one  
device out of all devices which are connected to the bus. This means that the device is selected if the  
inputted 3-bit device address code is equal to the corresponding hard-wired A2-A0 pin status. The  
eighth bit of the device address word is the read/write(R/W) bit. A write operation is initiated if this bit is  
low and a read operation is initiated if this bit is high. Upon a compare of the device address word, the  
EEPROM enters the read or write operation after outputting the zero as an aknowledge. The EEPROM  
turns to a stand-by state if the device code is not “1010” or device addreoesn’t coincide with  
status of the correspond hard-wired device address pins A0 to A2.  
Device Address Word  
Device address word (8-bit)  
Device code (fixed)  
R/W code*1  
16k  
1
0
1
0
a8  
R/W  
Note: 1. R/W=“1” is read and R/W = “0” is
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 11 of 20  
R1EX24016Axx00I  
Write Operations  
Byte Write:  
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends  
acknowledgment "0" at the ninth clock cycle. After these, the 64kbit EEPROM receives 2 sequence 8-bit  
memory address words. Upon receipt of this memory address, the EEPROM outputs acknowledgment "0"  
and receives a following 8-bit write data. After receipt of write data, the EEPROM outputs  
acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters an internally-timed  
write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The EEPROM  
returns to a standby mode after completion of the write cycle.  
Byte Write Operation  
Device  
Memory  
address  
address (n)  
W
1 0 1 0  
16k  
ACK  
R/W  
Stop  
Start  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 12 of 20  
R1EX24016Axx00I  
Page Write:  
The EEPROM is capable of the page write operation which allows any number of bytes up to 32 bytes to  
be written in a single write cycle. The page write is the same sequence as the byte write except for  
inputting the more write data. The page write is initiated by a start condition, device address word,  
memory address(n) and write data (Dn) with every ninth bit acknowledgment. The EEPROM enters the  
page write operation if the EEPROM receives more write data (Dn+1) instead of receiving a stop  
condition. The a0 to a4 address bits are automatically incremented upon receiving write data (Dn+1).  
The EEPROM can continue to receive write data up to 32 bytes. If the a0 to a4 address bits reaches the  
last address of the page, the a0 to a4 address bits will roll over to the first address of the same page and  
previous write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving  
write data and enters internally-timed write cycle.  
Page Write Operation  
Device  
Memory  
address  
address (n)  
Wr
m)  
16k  
Start  
W
1 0 1 0  
ACK  
R/W  
ACK  
Stop  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 13 of 20  
R1EX24016Axx00I  
Acknowledge Polling:  
Acknowledge polling feature is used to show if the EEPROM is in a internally-timed write cycle or not.  
This feature is initiated by the stop condition after inputting write data. This requires the 8-bit device  
address word following the start condition during a internally-timed write cycle. Acknowledge polling  
will operate when the R/W code = “0”. Acknowledgment “1” (no acknowledgment) shows the EEPROM  
is in a internally-timed write cycle and acknowledgment “0” shows that the internally-timed write cycle has  
completed. See Write Cycle Polling using ACK.  
Write Cycle Polling Using ACK  
Send  
write command  
Send  
stop condition  
to initiate write cycle  
Send  
start condition  
Send  
device addres
with R/
No  
ory  
s  
Send  
Send  
Send  
mory address  
start condition  
stop condition  
Send  
stop condition  
Proceed random address  
read operation  
Proceed write operation  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 14 of 20  
R1EX24016Axx00I  
Read Operation  
There are three read operations: current address read, random read, and sequential read. Read operations  
are initiated the same way as write operations with the exception of R/W = “1”.  
Current Address Read:  
The internal address counter maintains the last address accessed during the last read or write operation,  
with incremented by one. Current address read accesses the address kept by the internal address counter.  
After receiving a start condition and the device address word (R/W is “1”), the EEPROM outputs the 8-bit  
current address data from the most significant bit following acknowledgment “0”. If the EEPROM  
receives acknowledgment “1” (no acknowledgment) and a following stop condition, the EEPROM stops  
the read operation and is turned to a standby state. In case the EEPROM ccessed the last address of  
the last page at previous read operation, the current address will roll ovns to zero address. In  
case the EEPROM has accessed the last address of the page at prevn, the current address  
will roll over within page addressing and returns to the first addrhe current address  
is valid while power is on. The current address after power ndom read  
operation described below is necessary to define the mem
Current Address Read Operation  
Devic
add
1)  
No ACK  
16k  
Stop  
Sta
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 15 of 20  
R1EX24016Axx00I  
Random Read:  
This is a read operation with defined read address. A random read requires a dummy write to set read  
address. The EEPROM receives a start condition, device address word (R/W=0) and memory address 2 ×  
8-bit sequentially. The EEPROM outputs acknowledgment “0” after receiving memory address then  
enters a current address read with receiving a start condition. The EEPROM outputs the read data of the  
address which was defined in the dummy write operation. After receiving acknowledgment “1”(no  
acknowledgment) and a following stop condition, the EEPROM stops the random read operation and  
returns to a standby state.  
Random Read Operation  
Memory  
Device  
Device  
address (n)  
address  
address  
ad data (n)  
16k  
W
1 0 10  
1 0 1 0  
ACK  
R/W  
K  
Stop  
S
A
Start  
Dummy write  
ad  
Notes: 1. Don't care bit  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 16 of 20  
R1EX24016Axx00I  
Sequential Read:  
Sequential reads are initiated by either a current address read or a random read. If the EEPROM receives  
acknowledgment “0” after 8-bit read data, the read address is incremented and the next 8-bit read data are  
coming out. This operation can be continued as long as the EEPROM receives acknowledgment “0”.  
The address will roll over and returns address zero if it reaches the last address of the last page. The  
sequential read can be continued after roll over. The sequential read is terminated if the EEPROM  
receives acknowledgment “1” (no acknowledgment) and a following stop condition.  
Sequential Read Operation  
Device  
address  
Read data (n) Read data (n+1) Read dn+2) Read data (n+m)  
R
1 0 1 0  
*1  
*1 *1  
16k  
Start  
ACK  
R/W  
ACK  
No ACK  
Stop  
*1: Don't care bit  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 17 of 20  
R1EX24016Axx00I  
Notes  
Data Protection at VCC On/Off  
When VCC is turned on or off, noise on the SCL and SDA inputs generated by external circuits (CPU, etc)  
may act as a trigger and turn the EEPROM to unintentional program mode. To prevent this unintentional  
programming, this EEPROM has a power on reset function. Be careful of the notices described below in  
order for the power on reset function to operate correctly.  
SCL and SDA should be fixed to VCC or VSS during VCC on/off. Low to high or high to low transition  
during VCC on/off may cause the trigger for the unintentional programming.  
VCC should be turned off after the EEPROM is placed in a standby state
V
CC should be turned on from the ground level(VSS) in order for the not to enter the  
unintentional programming mode.  
VCC turn on speed should be longer than 10 µs.  
Noise Suppression Time  
This EEPROM have a noise suppression function cut noise of width less than  
50 ns. Be careful not to allow noise of width
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 18 of 20  
R1EX24016Axx00I  
Package Dimensions  
R1EX24016ASA00I (PRSP0008DF-B / Previous Code: FP-8DBV)  
JEITA Package Code  
P-SOP8-3.9x4.89-1.27  
RENESAS Code  
PRSP0008DF-B  
Previous Code  
FP-8DBV  
MASS[Typ.]  
0.08g  
*1  
D
F
NOTE)  
8
5
1. DIMENSIONS"*1 (Nom)"AND"*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION"*3"DOES NOT  
INCLUDE TRIM OFFSET.  
Index mark  
Dimension in Millimeters  
Reference  
Symbol  
1
4
Min Nom Max  
*3  
bp  
x
e
Z
D
M
4.89 5.15  
3.90  
E
A2  
A1  
A
bp  
b1  
c
0.102 0.14 0.254  
1.73  
0.35 0.40 0.45  
0.15 0.20 0.25  
L
c1  
θ
HE  
e
0° 8°  
5.84 6.02 6.20  
1.27  
Detail F  
x
0.25  
y
Z
0.10  
0.69  
L
L1  
0.406 0.60 0.889  
1.06  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 19 of 20  
R1EX24016Axx00I  
R1EX24016ATA00I (PTSP0008JC-B / Previous Code: TTP-8DAV)  
JEITA Package Code  
P-TSSOP8-4.4x3-0.65  
RENESAS Code  
PTSP0008JC-B  
Previous Code  
TTP-8DAV  
MASS[Typ.]  
0.034g  
*1  
D
F
8
5
NOTE)  
1. DIMENSIONS"*1 (Nom)"AND"*2"  
DO NOT INCLUDE MOLD FLASH.  
2. DIMENSION"*3"DOES NOT  
INCLUDE TRIM OFFSET.  
bp  
Dimension in Millimeters  
Reference  
Symbol  
Min Nom Max  
Index mark  
D
E
3.00 3.30  
4.40  
A2  
A1  
A
bp  
b1  
c
0.03 0.07 0.10  
1.10  
0.15 0.20 0.25  
1
4
*3  
e
bp  
Z
x
M
0.10 0.15 0.20  
c1  
θ
HE  
e
x
y
0° 8°  
6.20 6.40 6.60  
L
0.65  
0.13  
0.10  
il F  
Z
L
L1  
0.805  
0.40 0.50 0.60  
1.00  
REJ03C0359-0002 Rev.0.02 Jan.14, 2009  
Page 20 of 20  
Revision History  
R1EX24016Axx00I Data Sheet  
Rev. Date  
Contents of Modification  
Page Description  
0.01 Dec. 28, 2007  
0.02 Jan. 14, 2009  
Initial issue  
P1 Features  
Endurance cycles change 106 cycles to 1,000k cycles @25°C.  
Data retentions years change 10 years to 100 years @25°C.  
P4 Memory cell characteristics new is described.  
P5 AC characteristics  
Erase/Write endurance is deleted.  
Notes1. change Not 100% tested.  
Notes3 deleted.  
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan  
Notes:  
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes  
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property  
rights or any other rights of Renesas or any third party with respect to the information in this document.  
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,  
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.  
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass  
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws  
and regulations, and procedures required by such laws and regulations.  
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this  
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,  
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be  
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )  
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a  
result of errors or omissions in the information included in this document.  
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability  
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular  
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.  
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications  
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk uman injury or which require especially high quality  
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combntrol, aerospace and aeronautics, nuclear power, or  
undersea communication transmission. If you are considering the use of our products for such purposes, pleRenesas sales office beforehand. Renesas shall  
have no liability for damages arising out of the uses set forth above.  
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed
(1) artificial life support devices or systems  
(2) surgical implantations  
(3) healthcare intervention (e.g., excision, administration of medication, etc.)  
(4) any other purposes that pose a direct threat to human life  
Renesas shall have no liability for damages arising out of the uses set forth in the above and cts in any of the foregoing  
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated coployees against any and all  
damages arising out of such applications.  
9. You should use the products described herein within the range specified by Renesas, g, operating supply voltage range,  
movement power voltage range, heat radiation characteristics, installation and other no liability for malfunctions or damages  
arising out of the use of Renesas products beyond such specified ranges.  
10. Although Renesas endeavors to improve the quality and reliability of its productuch as the occurrence of failure at a certain  
rate and malfunctions under certain use conditions. Please be sure to implemssibility of physical injury, and injury or damage  
caused by fire in the event of the failure of a Renesas product, such as safeg but not limited to redundancy, fire control and  
malfunction prevention, appropriate treatment for aging degradation or an, since the evaluation of microcomputer software  
alone is very difficult, please evaluate the safety of the final products or
11. In case Renesas products listed in this document are detached from are attached or affixed, the risk of accident such as  
swallowing by infants and small children is very high. You should iproducts may not be easily detached from your products.  
Renesas shall have no liability for damages arising out of such d
12. This document may not be reproduced or duplicated, in any foapproval from Renesas.  
13. Please contact a Renesas sales office if you have any queshis document, Renesas semiconductor products, or if you have  
any other inquiries.  
RENESAS SALES OFFICE
http://www.renesas.com  
Refer to "http://www.renesas.coiled information.  
Renesas Technology Amer
450 Holger Way, San Jos
Tel: <1> (408) 382-7500,
Renesas Technology Europ
Dukes Meadow, Millboard Roadamshire, SL8 5FH, U.K.  
Tel: <44> (1628) 585-100, Fax: <40  
Renesas Technology (Shanghai) Co.
Unit 204, 205, AZIACenter, No.1233 Lujiaing Rd, Pudong District, Shanghai, China 200120  
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898  
Renesas Technology Hong Kong Ltd.  
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong  
Tel: <852> 2265-6688, Fax: <852> 2377-3473  
Renesas Technology Taiwan Co., Ltd.  
10th Floor, No.99, Fushing North Road, Taipei, Taiwan  
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399  
Renesas Technology Singapore Pte. Ltd.  
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632  
Tel: <65> 6213-0200, Fax: <65> 6278-8001  
Renesas Technology Korea Co., Ltd.  
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea  
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145  
Renesas Technology Malaysia Sdn. Bhd  
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia  
Tel: <603> 7955-9390, Fax: <603> 7955-9510  
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.  
Colophon .7.2  

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