R1LV0108ESF-7SIB0 [RENESAS]
1Mb Advanced LPSRAM (128k word x 8bit); 1MB先进LPSRAM （ 128K字X 8位）
| 型号： | R1LV0108ESF-7SIB0 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1Mb Advanced LPSRAM (128k word x 8bit) |
| 文件： | 总17页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1LV0108E Series
1Mb Advanced LPSRAM (128k word x 8bit)
R10DS0049EJ0200
Rev.2.00
2011.01.14
Description
The R1LV0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated
by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LV0108E Series has realized higher
density, higher performance and low power consumption. The R1LV0108E Series is suitable for memory applications
where a simple interfacing, battery operating and battery backup are the important design objectives. It has been
packaged in 32-pin SOP,32-pin TSOP and 32-pin sTSOP.
Features
•
•
•
•
•
•
•
•
Single 2.7~3.6V power supply
Small stand-by current: 1µA (3.0V, typical)
No clocks, No refresh
All inputs and outputs are TTL compatible.
Easy memory expansion by CS1# and CS2
Common Data I/O
Three-state outputs: OR-tie Capability
OE# prevents data contention on the I/O bus
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Ordering Information
Access Temperature
Shipping
Container
Orderable Part Name
Package
Quantity
time
Range
R1LV0108ESP-5SR#B0
R1LV0108ESP-5SI#B0
R1LV0108ESP-7SR#B0
R1LV0108ESP-7SI#B0
R1LV0108ESP-5SR#S0
R1LV0108ESP-5SI#S0
R1LV0108ESP-7SR#S0
R1LV0108ESP-7SI#S0
R1LV0108ESA-5SR#B0
R1LV0108ESA-5SI#B0
R1LV0108ESA-7SR#B0
R1LV0108ESA-7SI#B0
R1LV0108ESA-5SR#S0
R1LV0108ESA-5SI#S0
R1LV0108ESA-7SR#S0
R1LV0108ESA-7SI#S0
R1LV0108ESF-5SR#B0
R1LV0108ESF-5SI#B0
R1LV0108ESF-7SR#B0
R1LV0108ESF-7SI#B0
R1LV0108ESF-5SR#S0
R1LV0108ESF-5SI#S0
R1LV0108ESF-7SR#S0
R1LV0108ESF-7SI#S0
0 ~ +70°C
55 ns
Max. 25pcs/Tube
Max. 225pcs/Inner Bag
Max. 900pcs/Inner Box
-40 ~ +85°C
0 ~ +70°C
Tube
525-mil 32-pin
plastic SOP
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
55 ns
70 ns
-40 ~ +85°C
0 ~ +70°C
PRSP0032DA-A
(32P2M-A)
-40 ~ +85°C
0 ~ +70°C
Embossed
tape
1000pcs/Reel
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
Max. 234pcs/Tray
Tray
8mm×13.4mm 32-pin
plastic sTSOP
Max. 1872pcs/Inner Box
-40 ~ +85°C
0 ~ +70°C
(normal-bend type)
PTSA0032KB-A
(32P3K-B)
-40 ~ +85°C
0 ~ +70°C
Embossed
tape
1000pcs/Reel
-40 ~ +85°C
0 ~ +70°C
-40 ~ +85°C
0 ~ +70°C
Max. 156pcs/Tray
Tray
8mm×20mm 32-pin
plastic TSOP
Max. 1248pcs/Inner Box
-40 ~ +85°C
0 ~ +70°C
(normal-bend type)
PTSA0032KA-A
(32P3H-E)
-40 ~ +85°C
0 ~ +70°C
Embossed
tape
1000pcs/Reel
-40 ~ +85°C
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Pin Arrangement
NC
A16
A14
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CS2
WE#
A13
A8
1
2
3
4
5
A6
6
A5
A9
7
A4
A11
OE#
A10
CS1#
DQ7
DQ6
DQ5
DQ4
DQ3
8
32-pin SOP
A3
9
A2
10
11
12
13
14
15
16
A1
A0
DQ0
DQ1
DQ2
GND
A11
A9
32
OE#
A10
CS1#
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
1
2
3
4
5
6
7
8
9
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A8
A13
WE#
CS2
A15
Vcc
NC
32-pin sTSOP
A16
A14
A12
A7
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
A11
A9
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CS1#
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
1
2
A8
3
A13
WE#
CS2
A15
Vcc
NC
4
5
6
7
8
32-pin TSOP
9
(normal-bend)
A16
A14
A12
A7
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Pin Description
Pin name
Vcc
Function
Power supply
Ground
Vss
A0 to A16
DQ0 to DQ7
CS1#
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
Non connection
CS2
WE#
OE#
NC
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R1LV0108E Series
Block Diagram
A0
A1
MEMORY ARRAY
128k-word x8-bit
ROW
ADDRESS
BUFFER
DECODER
A16
DQ0
DQ1
DQ
BUFFER
SENSE / WRITE AMPLIFIER
COLUMN DECODER
DQ7
CLOCK
GENERATOR
Vcc
Vss
WE#
CS1#
CS2
OE#
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R1LV0108E Series
Operation Table
CS1#
CS2
L
WE#
X
OE#
X
DQ0~7
High-Z
High-Z
Din
Operation
Stand-by
Stand-by
Write
X
H
L
X
X
X
H
L
X
L
H
H
L
Dout
Read
L
H
H
H
High-Z
Output disable
Note 1. H: VIH L:VIL
X: VIH or VIL
Absolute Maximum
Parameter
Symbol
Value
unit
V
Power supply voltage relative to Vss
Terminal voltage on any pin relative to Vss
Power dissipation
Vcc
VT
-0.3 to +4.6
-0.3*1 to Vcc+0.3*2
0.7
V
PT
W
R Ver.
0 to +70
Operation temperature
Topr*3
Tstg
°C
°C
°C
I Ver.
-40 to +85
Storage temperature range
Storage temperature range under bias
-65 to 150
R Ver.
I Ver.
0 to +70
Tbias*3
-40 to +85
Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum)
2. Maximum voltage is +4.6V.
3. Ambient temperature range depends on R/I-version. Please see table on page 1.
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
DC Operating Conditions
Parameter
Symbol
Vcc
Min.
2.7
0
Typ.
Max.
3.6
Unit
V
Note
Supply voltage
3.0
Vss
0
-
0
V
Input high voltage
Input low voltage
VIH
2.0
-0.3
0
Vcc+0.3
0.6
V
VIL
-
V
1
2
2
R Ver.
I Ver.
-
+70
°C
°C
Ambient temperature range
Ta
-40
-
+85
Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum)
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
DC Characteristics
Parameter
Symbol
| ILI |
Min.
-
Typ.
-
Max.
1
Unit
Test conditions
Input leakage current
Output leakage current
μA
Vin = Vss to Vcc
CS1# =VIH or CS2 =VIL or
OE# =VIH,
| ILO
ICC1
ICC2
|
-
-
-
-
1
25
5
μA
VI/O =Vss to Vcc
Average operating current
Min. cycle, duty =100%, II/O = 0mA
CS1# =VIL, CS2 =VIH, Others = VIH/VIL
Cycle =1μs, duty =100%, II/O = 0mA
15
2
mA
mA CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V,
VIH ≥ Vcc-0.2V, VIL ≤ 0.2V
“CS2 =VIL“ or
Standby current
Standby current
ISB
-
-
0.33
mA “CS2 = VIH and CS1# =VIH”,
Others = Vss to Vcc
Vin = Vss to Vcc
-
-
-
1*1
2
3
μA
μA
μA
μA
~+25°C
~+40°C
~+70°C
-
-
-
(1) CS2 ≤ 0.2 or
ISB1
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
8
-
10
~+85°C
Output high voltage
Output low voltage
VOH
2.4
-
-
-
-
-
V
V
V
IOH = -0.5mA
Vcc
VOH2
IOH = -0.05mA
- 0.5
VOL
-
0.4
IOL = 2mA
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Capacitance
(Vcc = 2.7V ~ 3.6V, f = 1MHz, Ta = 0 ~ +70°C / -40 ~ +85°C*2)
Parameter
Input capacitance
Symbol
C in
Min.
Typ.
Max.
8
Unit
pF
Test conditions
Vin =0V
Note
-
-
-
-
1
1
Input / output capacitance
C I/O
10
pF
VI/O =0V
Note 1. This parameter is sampled and not 100% tested.
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
•
•
•
•
Input pulse levels: VIL = 0.4V, VIH = 2.2V
Input rise and fall time: 5ns
Input and output timing reference level: 1.5V
Output load: See figures (Including scope and jig)
1.5V
RL = 500 ohm
DQ
CL = 30 pF
Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1.
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Read Cycle
R1LV0108E**-5S*
R1LV0108E**-7S*
Parameter
Symbol
Unit
Note
Min.
Max.
-
Min.
70
-
Max.
-
Read cycle time
tRC
tAA
55
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
55
55
55
30
-
70
70
70
35
-
tACS1
tACS2
tOE
-
-
Chip select access time
-
-
Output enable to output valid
-
-
Output hold from address change
tOH
5
5
5
5
0
0
0
10
10
10
5
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
-
-
2,3
2,3
Chip select to output in low-Z
Output enable to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
-
-
-
-
2,3
20
20
20
0
25
25
25
1,2,3
1,2,3
1,2,3
0
0
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Write Cycle
R1LV0108E**-5S*
R1LV0108E**-7S*
Parameter
Symbol
Unit
Note
Min.
55
50
50
45
0
Max.
Min.
70
55
55
50
0
Max.
Write cycle time
tWC
tAW
tCW
tWP
tAS
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip select to end of write
Write pulse width
-
-
5
4
6
7
-
-
Address setup time
-
-
Write recovery time
tWR
tDW
tDH
0
-
0
-
Data to write time overlap
Data hold from write time
Output enable from end of write
Output disable to output in high-Z
Write to output in high-Z
25
0
-
30
0
-
-
-
tOW
tOHZ
tWHZ
5
-
5
-
2
0
20
20
0
25
25
1,2
1,2
0
0
Note 1. tCHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not
referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#.
A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low.
A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high.
tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
8. Don’t apply inverted phase signal externally when DQ pin is output mode.
R10DS0049EJ0200 Rev.2.00
2011.01.14
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R1LV0108E Series
Timing Waveforms
Read Cycle
tRC
A0~16
tOH
tAA
tACS1
CS1#
CS2
tCLZ1
tCHZ1
tACS2
tCLZ2
tCHZ2
VIH
WE#
WE# = “H” level
tOE
OE#
tOLZ
tOHZ
High impedance
DQ0~7
Valid Data
R10DS0049EJ0200 Rev.2.00
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R1LV0108E Series
Write Cycle (1) (WE# CLOCK)
tWC
A0~16
tCW
CS1#
tCW
CS2
tAW
tWP
tAS
tWR
WE#
OE#
tWHZ
tOLZ
tOHZ
tOW
DQ0~7
Valid Data
tDW tDH
R10DS0049EJ0200 Rev.2.00
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R1LV0108E Series
Write Cycle (2) (CS1#, CS2 CLOCK)
tWC
A0~16
tAW
tAS
tCW
tWR
CS1#
CS2
tAS
tCW
tWR
tWP
WE#
VIH
OE#
OE# = “H” level
tDW
tDH
DQ0~7
Valid Data
R10DS0049EJ0200 Rev.2.00
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R1LV0108E Series
Low Vcc Data Retention Characteristics
Parameter
Symbol
Min.
Typ. Max.
Unit
V
Test conditions*2
Vin ≥ 0V
(1) 0V ≤ CS2 ≤ 0.2V or
VCC for data retention
VDR
2.0
-
3.6
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
-
-
-
-
1*1
2
3
μA
μA
μA
μA
~+25°C
Vcc=3.0V, Vin ≥ 0V
-
-
-
~+40°C
~+70°C
~+85°C
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ Vcc-0.2V,
CS2 ≥ Vcc-0.2V
Data retention current
ICCDR
8
10
Chip deselect to data retention time
Operation recovery time
tCDR
tR
0
5
-
-
-
-
ns
See retention waveform.
ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer and Din buffer. If CS2 controls data
retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state.
If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input
levels (address, WE# ,OE#, DQ) can be in the high impedance state.
R10DS0049EJ0200 Rev.2.00
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R1LV0108E Series
Low Vcc Data Retention Timing Waveforms
(1) CS1# Controlled
Vcc
2.7V
2.7V
tCDR
tR
VDR
2.2V
2.2V
CS1# ≥ Vcc - 0.2V
CS1#
(2) CS2 Controlled
Vcc
2.7V
2.7V
CS2
tCDR
tR
VDR
0.2V
0.2V
0V ≤ CS2 ≤ 0.2V
R10DS0049EJ0200 Rev.2.00
2011.01.14
Page 15 of
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Revision History
R1LV0108E Series Data Sheet
Description
Summary
Rev.
1.00
2.00
Date
Page
2010.12.27
2011.01.14
-
First Edition issued
Ordering Information is revised
2
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Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2011 Renesas Electronics Corporation. All rights reserved.
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