R1LV1616HSA-5SI#B0 [RENESAS]
Wide Temperature Range Version 16 M SRAM (1-Mword x 16-bit / 2-Mword x 8-bit);
| 型号： | R1LV1616HSA-5SI#B0 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Wide Temperature Range Version 16 M SRAM (1-Mword x 16-bit / 2-Mword x 8-bit) 静态存储器 |
| 文件： | 总21页 (文件大小：394K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1LV1616HSA-I Series
Wide Temperature Range Version
16 M SRAM (1-Mword 16-bit / 2-Mword 8-bit)
REJ03C0195-0103
Rev. 1.03
Feb.20.2020
Description
The R1LV1616HSA-I Series is 16-Mbit static RAM organized 1-Mword 16-bit / 2-Mword 8-bit with
embedded ECC. R1LV1616HSA-I Series has realized higher density, higher performance and low power
consumption by employing CMOS process technology (6-transistor memory cell). It offers low power
standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48-pin
plastic TSOPI for high density surface mounting.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Fast access time: 45/55 ns (max)
Power dissipation:
Active: 9 mW/MHz (typ)
Standby: 1.5 W (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Battery backup operation.
2 chip selection for battery backup
Temperature range: 40 to +85C
Byte function (x8 mode) available by BYTE# & A-1
Embedded ECC (error checking and correction) for single-bit error correction
Rev.1.03, Feb.20.2020, page 1 of 19
R1LV1616HSA-I Series
Ordering Information
Type No.
R1LV1616HSA-4SI
R1LV1616HSA-5SI
Access time
45 ns
Package
48-pin plastic TSOPI
55 ns
Rev.1.03, Feb.20.2020, page 2 of 19
R1LV1616HSA-I Series
Pin Arrangement
48-pin TSOP
A15
A14
A13
A12
A11
A10
A9
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
Vss
3
4
I/O15/A-1
I/O7
5
6
I/O14
I/O6
7
A8
8
I/O13
I/O5
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I/O12
I/O4
WE#
CS2
NU
Vcc
I/O11
I/O3
UB#
LB#
A18
A17
A7
I/O10
I/O2
I/O9
I/O1
A6
I/O8
A5
I/O0
A4
OE#
Vss
A3
A2
CS1#
A0
A1
(Top view)
Rev.1.03, Feb.20.2020, page 3 of 19
R1LV1616HSA-I Series
Pin Description (TSOP)
Pin name
Function
Address input (word mode)
A0 to A19
A-1 to A19
I/O0 to I/O15
CS1# (CS1)
CS2
Address input (byte mode)
Data input/output
Chip select 1
Chip select 2
WE# (WE)
OE# (OE)
LB# (LB)
UB# (UB)
BYTE# (BYTE)
VCC
Write enable
Output enable
Lower byte select
Upper byte select
Byte enable
Power supply
VSS
Ground
NC
No connection
Not used (test mode pin)
NU*1
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
Rev.1.03, Feb.20.2020, page 4 of 19
R1LV1616HSA-I Series
Block Diagram (TSOP)
LSB
VCC
VSS
A15
A14
A13
A12
A11
A10
Memory matrix
・
・
・
・
・
Row
A9
8,192 x 128 x 16
decoder
A8
A18
A16
A19
A4
8,192 x 256 x 8
A5
MSB
ECC
I/O0
ECC
Column I/O
・
・
・
・
・
・
・
・
decoder
encoder
Input
data
Column decoder
control
I/O15
LSB
MSB
A17 A7 A6 A3 A2 A1 A0 A-1
・
・
BYTE#
CS2
CS1#
LB#
Control logic
UB#
WE#
OE#
Rev.1.03, Feb.20.2020, page 5 of 19
R1LV1616HSA-I Series
Operation Table (TSOP)
Byte mode
CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 I/O8 to I/O14
I/O15
High-Z
High-Z
A-1
Operation
Standby
Standby
Read
H
L
L
L
L
L
L
L
L
L
High-Z
High-Z
Dout
High-Z
High-Z
High-Z
High-Z
High-Z
H
H
H
H
L
L
Din
A-1
Write
H
H
High-Z
High-Z
Output disable
Note: H: VIH, L: VIL, : VIH or VIL
Word mode
CS1# CS2 WE# OE# UB# LB# BYTE# I/O0 to I/O7 I/O8 to I/O14
I/O15
High-Z
High-Z
High-Z
Dout
Operation
Standby
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
High-Z
High-Z
High-Z
Dout
High-Z
High-Z
High-Z
Dout
Standby
H
L
H
L
H
L
L
Standby
H
H
H
H
H
H
H
H
H
H
L
Read
Dout
High-Z
Dout
High-Z
Dout
Lower byte read
Upper byte read
Write
H
L
High-Z
Din
L
Din
Din
L
H
L
L
Din
High-Z
Din
High-Z
Din
Lower byte write
Upper byte write
Output disable
L
H
High-Z
High-Z
H
High-Z
High-Z
Note: H: VIH, L: VIL, : VIH or VIL
Rev.1.03, Feb.20.2020, page 6 of 19
R1LV1616HSA-I Series
Absolute Maximum Ratings
Parameter
Power supply voltage relative to VSS
Terminal voltage on any pin relative to VSS
Power dissipation
Symbol
VCC
Value
0.5 to +4.6
0.5*1 to VCC + 0.3*2
1.0
Unit
V
VT
V
PT
W
Storage temperature range
Tstg
Tbias
55 to +125
40 to +85
C
C
Storage temperature range under bias
Notes: 1. VT min: 2.0 V for pulse half-width 10 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter
Symbol
VCC
VSS
VIH
Min
2.7
0
Typ
Max
3.6
Unit
V
Note
Supply voltage
3.0
0
0
V
Input high voltage
2.2
0.3
40
VCC + 0.3
0.6
V
Input low voltage
VIL
V
1
Ambient temperature range
Ta
+85
C
Note: 1. VIL min: 2.0 V for pulse half-width 10 ns.
Rev.1.03, Feb.20.2020, page 7 of 19
R1LV1616HSA-I Series
DC Characteristics
Parameter
Input leakage current
Output leakage current
Symbol
|ILI|
Min
Typ Max Unit Test conditions*2
1
1
A Vin = VSS to VCC
|ILO
|
A CS1# = VIH or CS2 = VIL or
OE# = VIH or WE# = VIL or
LB# = UB# = VIH, VI/O = VSS to VCC
Operating current
ICC
20
35
mA CS1# = VIL, CS2 = VIH,
Others = VIH/ VIL, II/O = 0 mA
Average operating current
ICC1
(READ)
22*1
mA Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
WE# = VIH, Others = VIH/VIL
ICC1
30*1
3*1
50
8
mA Min. cycle, duty = 100%,
I
I/O = 0 mA, CS1# = VIL, CS2 = VIH,
Others = VIH/VIL
3
ICC2*
mA Cycle time = 70 ns, duty = 100%,
(READ)
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
WE# = VIH, Others = VIH/VIL
Address increment scan or
decrement scan
3
ICC2
*
20*1
30
8
mA Cycle time = 70 ns, duty = 100%,
I
I/O = 0 mA, CS1# = VIL, CS2 = VIH,
Others = VIH/VIL
Address increment scan or
decrement scan
ICC3
3*1
mA Cycle time = 1 s, duty = 100%,
I
I/O = 0 mA, CS1# 0.2 V,
CS2 VCC 0.2 V
VIH VCC 0.2 V, VIL 0.2 V
Standby current
Standby current
ISB
0.1*1 0.5
mA CS2 = VIL
A 0 V Vin
(1) 0 V CS2 0.2 V or
ISB1
0.5*1
8
(2) CS1# VCC 0.2 V,
CS2 VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Average value
Output high voltage
Output low voltage
VOH
VOH
2.4
VCC
0.2
V
V
IOH = 1 mA
IOH = 100 A
VOL
VOL
0.4
0.2
V
V
IOL = 2 mA
IOL = 100 A
Rev.1.03, Feb.20.2020, page 8 of 19
R1LV1616HSA-I Series
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed.
2. BYTE# VCC 0.2 V or BYTE# 0.2 V
3. ICC2 is the value measured while the valid address is increasing or decreasing by one bit.
Word mode: LSB (least significant bit) is A0.
Byte mode: LSB (least significant bit) is A-1.
Capacitance
(Ta = +25C, f = 1.0 MHz)
Parameter
Input capacitance
Symbol
Cin
Min
Typ
Max
8
Unit
pF
Test conditions
Vin = 0 V
Note
1
1
Input/output capacitance
CI/O
10
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
Rev.1.03, Feb.20.2020, page 9 of 19
R1LV1616HSA-I Series
AC Characteristics
(Ta = 40 to +85C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
Input rise and fall time: 5 ns
Input and output timing reference levels: 1.4 V
Output load: See figures (Including scope and jig)
1.4V
RL = 500Ω
Dout
50 pF
Rev.1.03, Feb.20.2020, page 10 of 19
R1LV1616HSA-I Series
Read Cycle
R1LV1616HSA-I
-4SI -5SI
Parameter
Read cycle time
Symbol
tRC
Min
45
10
10
10
5
Max
45
45
45
30
45
20
20
15
15
Min
55
10
10
10
5
Max
55
55
55
35
55
20
20
20
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Address access time
Chip select access time
tAA
tACS1
tACS2
tOE
Output enable to output valid
Output hold from address change
LB#, UB# access time
tOH
tBA
Chip select to output in low-Z
tCLZ1
tCLZ2
tBLZ
2, 3
2, 3
LB#, UB# enable to low-Z
2, 3
Output enable to output in low-Z
Chip deselect to output in high-Z
tOLZ
5
5
2, 3
tCHZ1
tCHZ2
tBHZ
tOHZ
0
0
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
0
0
LB#, UB# disable to high-Z
0
0
Output disable to output in high-Z
0
0
Write Cycle
R1LV1616HSA-I
-4SI -5SI
Parameter
Write cycle time
Symbol
tWC
Min
45
45
45
35
45
0
Max
15
Min
55
50
50
40
50
0
Max
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Address valid to end of write
Chip selection to end of write
Write pulse width
tAW
tCW
5
4
tWP
LB#, UB# valid to end of write
Address setup time
tBW
tAS
6
7
Write recovery time
tWR
0
0
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in high-Z
Write to output in high-Z
tDW
25
0
25
0
tDH
tOW
tOHZ
tWHZ
5
5
2
0
0
1, 2
1, 2
0
15
0
20
Rev.1.03, Feb.20.2020, page 11 of 19
R1LV1616HSA-I Series
Byte Control
R1LV1616HSA-I
-4SI -5SI
Parameter
BYTE# setup time
Symbol
tBS
Min
5
Max
Min
5
Max
Unit
ms
Notes
BYTE# recovery time
tBR
5
5
ms
Notes: 1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit
conditions and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given
device and from device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low
UB#. A write begins at the latest transition among CS1# going low, CS2 going high, WE# going
low and LB# going low or UB# going low. A write ends at the earliest transition among CS1#
going high, CS2 going low, WE# going high and LB# going high or UB# going high. tWP is
measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of
write cycle.
Rev.1.03, Feb.20.2020, page 12 of 19
R1LV1616HSA-I Series
Timing Waveform
Read Cycle*1
tRC
Address*2
Valid address
tAA
tACS1
CS1#
tCLZ1
tCHZ1
CS2
tACS2
tCLZ2
tCHZ2
tBHZ
tBA
LB#, UB#
OE#
tBLZ
tOHZ
tOE
tOLZ
tOH
High impedance
Dout*3
Valid data
Notes: 1. BYTE# > VCC – 0.2 V or
BYTE# < 0.2 V
2. Word mode: A0 to A19
Byte mode: A-1 to A19
3. Word mode: I/O0 to I/O15
Byte mode: I/O0 to I/O7
Rev.1.03, Feb.20.2020, page 13 of 19
R1LV1616HSA-I Series
Write Cycle (1)*1 (WE# Clock)
tWC
Valid address
Address*2
tWR
tCW
CS1#
tCW
CS2
tBW
LB#, UB#
tAW
tWP
WE#
tAS
tDW
Valid data
tDH
Din*3
tWHZ
tOW
High impedance
Dout*3
Notes: 1. BYTE# > VCC – 0.2 V or
BYTE# < 0.2 V
2. Word mode: A0 to A19
Byte mode: A-1 to A19
3. Word mode: I/O0 to I/O15
Byte mode: I/O0 to I/O7
Rev.1.03, Feb.20.2020, page 14 of 19
R1LV1616HSA-I Series
Write Cycle (2)*1 (CS1#, CS2 Clock, OE# = VIH)
tWC
Valid address
tAW
Address*2
tAS
tWR
tCW
CS1#
tAS
tCW
CS2
tBW
LB#, UB#
tWP
WE#
tDW
Valid data
tDH
Din*3
High impedance
Dout*3
Notes: 1. BYTE# > VCC – 0.2 V or
BYTE# < 0.2 V
2. Word mode: A0 to A19
Byte mode: A-1 to A19
3. Word mode: I/O0 to I/O15
Byte mode: I/O0 to I/O7
Rev.1.03, Feb.20.2020, page 15 of 19
R1LV1616HSA-I Series
Write Cycle (3)*1 (LB#, UB# Clock, OE# = VIH)
tWC
Valid address
Address
CS1#
tAW
tCW
tWR
tCW
CS2
tBW
tAS
UB# (LB#)
LB# (UB#)
tBW
tWP
WE#
tDW
tDH
Din-UB
(Din-LB)
Valid data
tDW
tDH
Din-LB
(Din-UB)
Valid data
High impedance
Dout
Note: 1. BYTE# > VCC – 0.2 V
Rev.1.03, Feb.20.2020, page 16 of 19
R1LV1616HSA-I Series
Byte Control (TSOP)
CS2
CS1#
tBS
tBR
BYTE#
Rev.1.03, Feb.20.2020, page 17 of 19
R1LV1616HSA-I Series
Low VCC Data Retention Characteristics
(Ta = 40 to +85C)
Test conditions*2, 3
Parameter
Symbol
VDR
Min
1.5
Typ
Max
3.6
Unit
V
VCC for data retention
Vin 0 V
(1) 0 V CS2 0.2 V or
(2) CS2 VCC 0.2 V,
CS1# VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Data retention current
ICCDR
0.5*1
8
A
VCC = 3.0 V, Vin 0 V
(1) 0 V CS2 0.2 V or
(2) CS2 VCC 0.2 V,
CS1# VCC 0.2 V or
(3) LB# = UB# VCC 0.2 V,
CS2 VCC 0.2 V,
CS1# 0.2 V
Average value
Chip deselect to data
retention time
tCDR
tR
0
5
ns
See retention waveforms
Operation recovery time
ms
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed.
2. BYTE# VCC 0.2 V or BYTE# 0.2 V
3. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din
buffer. If CS2 controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#,
I/O) can be in the high impedance state. If CS1# controls data retention mode, CS2 must be
CS2 VCC 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE#, OE#, LB#, UB#,
I/O) can be in the high impedance state.
Rev.1.03, Feb.20.2020, page 18 of 19
R1LV1616HSA-I Series
Low VCC Data Retention Timing Waveform (1) (CS1# Controlled)
Data retention mode
tCDR
tR
VCC
2.7 V
2.2 V
VDR
CS1#
0 V
CS1#
V
CC
– 0.2 V
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
tCDR
Data retention mode
tR
VCC
2.7 V
CS2
VDR
0.6 V
0 V
<
<
0 V CS2 0.2 V
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled)
Data retention mode
tCDR
tR
VCC
2.7 V
2.2 V
VDR
LB#, UB#
0 V
LB#, UB# VCC – 0.2 V
Rev.1.03, Feb.20.2020, page 19 of 19
Revision History
R1LV1616HSA-I Series Data Sheet
Rev.
Date
Contents of Modification
Description
Page
―
1.00
1.01
1.02
Apr.22.2004
Nov.18.2004
Feb.23.2017
Initial issue
Addition of 2-Mword x 8-bit function
p.1,p.5 Disclosed embedded ECC features
p.2 Deleted previous package code (48P3R-B)
Last page Updated the Notice to the latest version
1.03
Feb.20.2020
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