R1QKA7236ABB-25RA [RENESAS]
QDR SRAM;
| 型号： | R1QKA7236ABB-25RA |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | QDR SRAM 静态存储器 内存集成电路 |
| 文件： | 总39页 (文件大小：873K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
hinT=00000.0000.0000.1100.1100---
00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
QDRII+_RL20
R1GAA72 / R1QKA72 Series
R1QGA7236ABB / R1QGA7218ABB
R1QKA7236ABB / R1QKA7218ABB
72-Mbit QDR™II+ SRAM
4-word Burst
R10DS0172EJ0011
Rev. 0.11
2013.01.15
Description
The R1Q#A7236 is a 2,097,152-word by 36-bit and the R1Q#A7218 is a 4,194,304-word by 18-bit synchronous
quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory
cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled
by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable
for applications which require synchronous operation, high speed, low voltage, high density and wide bit
configuration. These products are packaged in 165-pin plastic FBGA package.
# = A: Read Latency =2.5, w/o ODT
# = D: Read Latency =2.5, w/ ODT
# = G: Read Latency =2.0, w/o ODT
# = K: Read Latency =2.0, w/ ODT
Features
႑ Power Supply
• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ
႑ Clock
)
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with μs restart
႑ I/O
• Separate independent read and write data ports with concurrent transactions
• 100% bus utilization DDR read and write operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
႑ Function
• Four-tick burst for reduced address frequency
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
႑ Package
• 165 FBGA package (13 x 15 x 1.4 mm)
Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
Part Number Definition
Part Number Definition Table
Column No.
0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16
R 1 Q G A 7 2 1 8 A B B - 2 5 R B 0
The above part number is just example for 72M QDRII+ B4 x18 400MHz, 13x15mm PKG, Pb-free part.
Example
No.
0-1
-
Comments
No.
4
-
A
Comments
Vdd = 1.8 V
No.
-
Comments
R1
Q2
Q3
Q4
Q5
Q6
QA
QB
QC
QD
QE
QF
QG
QH
QJ
Renesas Memory Prefix
60
50
40
36
33
30
27
25
22
20
19
18
Frequency = 167MHz
Frequency = 200MHz
Frequency = 250MHz
Frequency = 275MHz
Frequency = 300MHz
Frequency = 333MHz
QDR II B2[*1]
QDR II B4
DDR II B2
DDR II B4
(L15)[*2]
(L15)
36
72
44
88
09
18
36
R
Density = 36Mb
Density = 72Mb
Density = 144Mb
Density = 288Mb
Data width = 9bit
Data width = 18bit
Data width = 36bit
1st Generation
5-6
7-8
(L15)
(L15)
DDR IIB2 SIO[*3] (L15)
12-13
QDR II+ B4 L25[*2]
DDR II+ B2 L25
DDR II+ B4 L25
Frequency = 375MHz
Frequency = 400MHz
Frequency = 450MHz
Frequency = 500MHz
Frequency = 533MHz
Frequency = 550MHz
Commercial temp.
QDR II+ B4 L25 w/ODT[*4]
DDR II+ B2 L25 w/ODT
DDR II+ B4 L25 w/ODT
QDR II+ B4 L20
A
2nd Generation
3rd Generation
B
9
C
4th Generation
2-3
D
5th Generation
R
DDR II+ B2 L20
DDR II+ B4 L20
E
6th Generation
Ta range = 0 to 70
é
é
14
F
7th Generation
Industrial temp.
I
QK
QL
QM
QN
QP
QDR II+ B4 L20 w/ODT
DDR II+ B2 L20 w/ODT
DDR II+ B4 L20 w/ODT
QDR II+ B2 L20
BG
BB
PKG= BGA 15x17 mm
PKG= BGA 13x15 mm
Ta range = -40 to 85
é
é
10-11
-
A
Pb-and Tray
Pb-free and Tray
Pb-and Tape&Reel
B
T
15
16
QDR II+ B2 L20 w/ODT
S
Pb-free and Tape&Reel
-
-
0 to 9,
-
-
A to Z Renesas internal use
or None
Note1:
Note2:
[*1] B=Burst length (B2: Burst length=2, B4: Burst length=4)
[*2] L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)
[*3] SIO=Separate I/O
[*4] ODT=On die termination
Package Marking Name
Pb-parts: Marking Name = Part Number(0-14)
Pb-free parts: Marking Name = Part Number(0-14) + "PB-F"
(Example) R1QAA4436RBG-20R Pb-F ----- Pb-parts
(Example) R1QAA4436RBG-20R PB-F ----- Pb-free parts
Note3:
Note4:
Pb-free: RoHS Compliance Level = 5/6
Pb-free: RoHS Compliance Level = 6/6
R1Q*A series support both "Commercial" and "Industrial" temperatures
by "Industrial" temperature parts.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---072M
R1GAA72 / R1QKA72 Series
72M QDR/DDR SRAM (R1Q*A72 Series) Lineup
- Renesas supports or plans to support the parts listed below.
QDR II+ / DDR II+
QDR II / DDR II
Frequency (max)
(MHz)
533 500 450 400 375 333 333 300 250 200
No
Cycle Time (min)
1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00
(ns)
Part Number
yy
-19
ă
-20
-22
-25
-27
-30
-30
-33
-40
-40
-50
-50
Ą
1
2
x 9 R1Q 2 A72 09ABv- yy
x18 R1Q 2 A72 18ABv- yy
x36 R1Q 2 A72 36ABv- yy
x18 R1Q 3 A72 18ABv- yy
x36 R1Q 3 A72 36ABv- yy
x18 R1Q 4 A72 18ABv- yy
x36 R1Q 4 A72 36ABv- yy
x18 R1Q 5 A72 18ABv- yy
x36 R1Q 5 A72 36ABv- yy
x18 R1Q 6 A72 18ABv- yy
x36 R1Q 6 A72 36ABv- yy
x18 R1Q A A72 18ABv- yy
x36 R1Q A A72 36ABv- yy
x18 R1Q B A72 18ABv- yy
x36 R1Q B A72 36ABv- yy
x18 R1Q C A72 18ABv- yy
x36 R1Q C A72 36ABv- yy
x18 R1Q D A72 18ABv- yy
x36 R1Q D A72 36ABv- yy
x18 R1Q E A72 18ABv- yy
x36 R1Q E A72 36ABv- yy
x18 R1Q F A72 18ABv- yy
x36 R1Q F A72 36ABv- yy
x18 R1Q GA72 18ABv- yy
x36 R1Q GA72 36ABv- yy
x18 R1Q H A72 18ABv- yy
x36 R1Q H A72 36ABv- yy
x18 R1Q J A72 18ABv- yy
x36 R1Q J A72 36ABv- yy
x18 R1Q K A72 18ABv- yy
x36 R1Q K A72 36ABv- yy
x18 R1Q L A72 18ABv- yy
x36 R1Q L A72 36ABv- yy
x18 R1QM A72 18ABv- yy
x36 R1QM A72 36ABv- yy
B2
-40
-40
-40
-40
-40
-50
QDRII
DDRII
3
5
B4
B2
B4
B2
-30
-30
-30
-30
-33
-33
-33
-33
6
8
9
11
12
14 DDRII
15 SIO
17
QDRII+ B4
-19
-19
-19
-19
-19
-19
-20
-20
-20
-20
-20
-20
-22
-22
-22
-22
-22
-22
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
QDRII+ B4
-25
-25
-25
-25
-25
-25
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Notes:
1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example.
3. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
72---
R1GAA72 / R1QKA72 Series
Pin Arrangement
R1Q3A7236 (Top) / R1QA(G)A7236 (Mid) / R1QD(K)A7236 (Bottom)
1
2
NC
3
SA
4
/W
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
5
6
/K
K
7
8
/R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
9
SA
10
NC
Q17
Q7
D15
D6
Q14
D13
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
Q27
D27
D28
Q29
Q30
D30
/BW2
/BW3
SA
/BW1
/BW0
SA
Q18
Q28
D20
D29
Q21
D22
D18
D19
Q19
Q20
D21
Q22
D17
D16
Q16
Q15
D14
Q13
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
/DOFF VREF VDDQ VDDQ
VDDQ VDDQ VREF
D31
Q32
Q33
D33
D34
Q31
D32
Q24
Q34
D26
D23
Q23
D24
D25
Q25
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VSS
D12
Q12
D11
D10
Q10
Q4
D3
Q11
Q1
D9
VSS
VSS
C
QVLD
QVLD
P
R
Q35
D35
Q26
SA
SA
SA
SA
SA
SA
SA
SA
SA
Q9
SA
D0
Q0
/C
NC
TDO TCK
TMS
TDI
ODT
(Top View)
Top
Mid
ĸR1Q3A7236
ĸR1QA(G)A7236
Bottom ĸR1QD(K)A7236
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ
.
R1Q3A7218 (Top) / R1QA(G)A7218 (Mid) / R1QD(K)A7218 (Bottom)
1
2
NC
Q9
NC
D11
NC
Q12
D13
3
SA
D9
D10
Q10
Q11
D12
Q13
4
/W
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
5
/BW1
NC
6
/K
K
7
NC
/BW0
SA
8
/R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
9
10
SA
NC
Q7
NC
D6
NC
NC
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
NC
NC
NC
SA
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
/DOFF VREF VDDQ VDDQ
VDDQ VDDQ VREF
NC
NC
NC
NC
NC
NC
NC
Q15
NC
D14
Q14
D15
D16
Q16
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
Q4
D3
NC
Q1
NC
D17
VSS
VSS
C
QVLD
QVLD
P
R
NC
NC
Q17
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
SA
D0
Q0
/C
NC
TDO TCK
TMS
TDI
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ
.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
72---
R1GAA72 / R1QKA72 Series
Pin Arrangement
Just Reference
R1Q3A7209 (Top) / R1QA(G)A7209 (Mid) / R1QD(K)A7209 (Bottom)
1
2
3
4
/W
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
5
6
/K
K
7
8
/R
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
9
10
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
D5
NC
NC
D6
SA
NC
NC
NC
Q5
NC
Q6
NC
NC
SA
NC
/BW
SA
SA
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
D3
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
NC
NC
/DOFF VREF VDDQ VDDQ
VDDQ VDDQ VREF
NC
NC
NC
NC
NC
NC
NC
Q7
NC
D8
NC
NC
D7
NC
NC
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
Q2
NC
NC
NC
NC
VSS
VSS
C
QVLD
QVLD
P
R
NC
NC
Q8
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
SA
D0
Q0
/C
NC
TDO TCK
TMS
TDI
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ
.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11000.1100.1100.1100.1100
---11000.1100.1100.1100.1100---
11000.1100.1100.1100.1100---
QDR
R1GAA72 / R1QKA72 Series
Pin Descriptions
Name I/O type
Descriptions
Notes
Synchronous address inputs: These inputs are registered and must meet
the setup and hold times around the rising edge of K. All transactions
operate on a burst-of-four words (two clock periods of bus activity).
These inputs are ignored when device is deselected.
Synchronous read: When low, this input causes the address inputs to be
registered and a READ cycle to be initiated. This input must meet setup
and hold times around the rising edge of K, and is ignored on the
subsequent rising edge of K.
Synchronous write: When low, this input causes the address inputs to be
registered and a WRITE cycle to be initiated. This input must meet setup
and hold times around the rising edge of K, and is ignored on the
subsequent rising edge of K.
SA
Input
Input
Input
/R
/W
Synchronous byte writes: When low, these inputs cause their respective
byte to be registered and written during WRITE cycles. These signals
are sampled on the same edge as the corresponding data and must meet
setup and hold times around the rising edges of K and /K for each of the
two rising edges comprising the WRITE cycle. See Byte Write Truth
Table for signal to data relationship.
/BWx
K, /K
Input
Input clock: This input clock pair registers address and control inputs on
the rising edge of K, and registers data on the rising edge of K and the
Input rising edge of /K. /K is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock
rising edges. These balls cannot remain VREF level.
Output clock: This clock pair provides a user-controlled means of tuning
device output data. The rising edge of /C is used as the output timing
reference for the first and third output data. The rising edge of C is used
as the output timing reference for second and fourth output data. Ideally,
Input /C is 180 degrees out of phase with C. C and /C may be tied high to
force the use of K and /K as the output reference clocks instead of having
to provide C and /C clocks. If tied high, C and /C must remain high and
not to be toggled during device operation. These balls cannot remain
VREF level.
C, /C
(II only)
1
DLL/PLL disable: When low, this input causes the DLL/PLL to be
bypassed for stable, low frequency operation.
/DOFF
Input
TMS
TDI
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if
the JTAG function is not used in the circuit.
TCK
Input
Notes:
1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD,
R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C,
/C pins. In the series, K and /K are used as the output reference clocks instead of C and /C.
Therefore, hereafter, C and /C represent K and /K in this document.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
---
R1GAA72 / R1QKA72 Series
Name I/O type
Descriptions
Notes
Output impedance matching input: This input is used to tune the device
outputs to the system data bus impedance. Q and CQ output
impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to
ground. This ball can be connected directly to VDDQ, which enables the
Input minimum impedance mode. This ball cannot be connected directly to
VSS or left unconnected.
ZQ
In ODT (On Die Termination) enable devices, the ODT termination
values tracks the value of RQ. The ODT range is selected by ODT
control input.
ODT control: When low;
[Option 1] Low range mode is selected. The impedance range is
between 52 Ω and 105 Ω (Thevenin equivalent), which follows 0.3 ×
RQ for 175 Ω RQ 350 Ω.
ODT
(II+ only)
[Option 2] ODT is disabled.
Input
1
When high; High range mode is selected. The impedance range is
between 105 Ω and 150 Ω (Thevenin equivalent), which follows 0.6
× RQ for 175 Ω RQ 250 Ω.
When floating; [Option 1] High range mode is selected.
[Option 2] ODT is disabled.
Synchronous data inputs: Input data must meet setup and hold times
around the rising edges of K and /K during WRITE operations. See Pin
Arrangement figures for ball site location of individual signals.
D0 to Dn
Input
The ×9 device uses D0~D8. D9~D35 should be treated as NC pin.
The ×18 device uses D0~D17. D18~D35 should be treated as NC pin.
The ×36 device uses D0~D35.
Synchronous echo clock outputs: The edges of these outputs are tightly
matched to the synchronous data outputs and can be used as a data
valid indication. These signals run freely and do not stop when Q tri-
states.
CQ, /CQ Output
TDO
Output IEEE 1149.1 test output: 1.8 V I/O level.
Synchronous data outputs: Output data is synchronized to the
respective C and /C, or to the respective K and /K if C and /C are tied
high. This bus operates in response to /R commands. See Pin
Q0 to Qn Output Arrangement figures for ball site location of individual signals.
The ×9 device uses Q0~Q8. Q9~Q35 should be treated as NC pin.
The ×18 device uses Q0~Q17. Q18~Q35 should be treated as NC pin.
The ×36 device uses Q0~Q35.
QVLD
(II+ only)
Valid output indicator: The Q Valid indicates valid output data. QVLD is
edge aligned with CQ and /CQ.
Output
Supply
Supply
Power supply: 1.8 V nominal. See DC Characteristics and Operating
Conditions for range.
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC
Characteristics and Operating Conditions for range.
VDD
2
VDDQ
VSS
2
2
Supply Power supply: Ground.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to
VREF
⎯
⎯
improve system noise margin. Provides a reference voltage for the
HSTL input buffers.
NC
No connect: These pins can be left floating or connected to 0V ᨺ VDDQ.
Notes:
1. Renesas status: Option 1 = Available, Option 2 = Possible.
2. All power supply and ground balls must be connected for proper operation of the device.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
7 2 - - -
R1GAA72 / R1QKA72 Series
Block Diagram (R1QxA7236 / R1QxA7218 / R1QxA7209, x=3,A,D,G,K)
19/20/21
Address
Address
/R
/W
K
19/20/21
Registry
and
Logic
ZQ
/K
72
/36
/18
72
/36
/18
/W
144
/72
/36
Q
(Data out)
4/2/1
/BWx
36/18/9
72
/36
/18
72
/36
/18
Memory
Array
Data
Registry
and
36/18/9
(Data in)
D
2
Logic
CQ
/R
/CQ
K
/K
C,/C
or
K
C
or
K
K,/K
Notes
1. C and /C pins do not exist in II+ series parts.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
11111.1111.1111.1111.1111---00000.0000.0000.0000.0000---
72M_36M
R1GAA72 / R1QKA72 Series
General Description
Power-up and Initialization Sequence
- VDD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : VSS ĺ VDD ĺ VDDQ & VREF ĺ VIN. (0 V to VDD, VDDQ < 200 ms)
- Apply VREF after VDDQ or at the same time as VDDQ
.
- Then execute either one of the following three sequences.
1. Single Clock Mode (C and /C tied high)
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series).
These meet the QDR common specification of 20 us.
When the operating frequency is less than 180 MHz, 2048 cycles are required (II series).
1. Single clock mode (C and /C pins fixed High)
Power Up &
NOP &
Normal
Status
Unstable Stage
Set-up Stage
Operation
VDD
VDDQ
VREF
Fix High (=Vddq)
SET-UP Cycle
/DOFF
K, /K
2. Double Clock Mode (C and /C control outputs) (II series only)
- Drive /DOFF high (/DOFF can be tied high from the start)
- Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series).
This meets the QDR common specification of 20 us.
When the operating frequency is less than 180 MHz, 2048 cycles are required (II series).
2. Double clock mode
Power Up &
NOP &
Normal
Status
Unstable Stage
Set-up Stage
Operation
VDD
VDDQ
VREF
Fix High (=Vddq)
SET-UP Cycle
/DOFF
K, /K
C, /C
3. DLL/PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+
series). These meet the QDR common specification of 20 us.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
DLL/PLL Constraints
1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is
specified as tKC var.
2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz.
(Please refer to AC Characteristics table for detail.)
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor
(RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to
guarantee impedance matching with a tolerance of 15% is 250 Ω typical. The total external capacitance of
ZQ ball must be less than 7.5 pF.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
IIP
R1GAA72 / R1QKA72 Series
QVLD (Valid data indicator)
(R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM
R1QN, R1QP series)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q
Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be
ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop
capturing the data. QVLD is edge aligned with CQ and /CQ.
ODT (On Die Termination)
(R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated,
especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of
devices. (See the ODT pin table)
2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input. (See the ODT range table)
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data
and disabled when the device outputs data.
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without
ODT.
5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current
consumption from the I/O voltage supply) with ODT.
ODT range
Thevenin equivalent resistance (RTHEV
)
Unit
-
Notes
6
1, 4
2, 5
3
ODT control pin
Option 1
0.3 × RQ
0.6 × RQ
0.6 × RQ
Option 2
(ODT disable)
0.6 × RQ
Ω
Low
High
Floating
Ω
Ω
(ODT disable)
Notes:
1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of 20 % is
175 Ω RQ 350 Ω.
2. Allowable range of RQ to guarantee impedance matching a tolerance of 20 % is
175 Ω RQ 250 Ω.
3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of 20 % is
175 Ω RQ 250 Ω.
4. At option 1, ODT control pin is connected to VDDQ through 3.5 kΩ. Therefore it is recommended
to connect it to VSS through less than 100 Ω to make it low.
5. At option 2, ODT control pin is connected to VSS through 3.5 kΩ. Therefore it is recommended to
connect it to VDDQ through less than 100 Ω to make it high.
6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
IIP
R1GAA72 / R1QKA72 Series
Thevenin termination
Other LSI
SRAM with ODT
VDDQ
ZQ
2 × RTHEV
RQ
Input
Buffer
Output
Buffer
2 × RTHEV
VSS
VSS
ODT pin (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
ODT On/Off timing
Option 2
Notes
Pin name
Option 1
3
1
ODT pin = Low
or Floating
ODT pin = High
D0 ~ Dn in separate I/O devices
Always On
Always Off
Off: First Read Command
+ Read Latency
- 0.5 cycle
DQ0 ~ DQn
in common I/O devices
On: Last Read Command
+ Read Latency
Always Off
2
+ BL/2 cycle + 0.5 cycle
(See below timing chart)
/BWx
K, /K
Always On
Always On
Always Off
Always Off
Notes: 1. Separate I/O devices are R1QD, R1QK, R1QP series.
2. Common I/O devices are R1QE, R1QF, R1QL, R1QM series.
3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with
option 2, please contact Renesas sales office.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
IIP
R1GAA72 / R1QKA72 Series
ODT on/off Timing Chart for R1QE series (DDR II+, Burst Length=2, Read Latency=2.5 cycle)
Read Read Read Read
(B2) (B2) (B2) (B2)
Write Write Write Write Read Read
(B2) (B2) (B2) (B2) (B2) (B2)
NOP
NOP NOP NOP
Status
K, /K
Command
DQ
Ra
Rb
Rc
Rd
We
Wf
Wg
Wh
Ri
Rj
Qa Qa Qb Qb Qc Qc Qd Qd
Disabled
De De Df Df Dg Dg Dh Dh
Enabled
Qi Qi Qj
Disabled
Enabled
DQ ODT
ODT on/off Timing Chart for R1QF series (DDR II+, Burst Length=4, Read Latency=2.5 cycle)
Read
(B4)
Read
(B4)
Write
(B4)
Write
(B4)
Read
(B4)
NOP
-
-
NOP NOP NOP
-
-
-
Status
K, /K
Command
DQ
Ra
Rc
We
Wg
Ri
Qa Qa Qa Qa Qc Qc Qc Qc
Disabled
De De De De Dg Dg Dg Dg
Enabled
Qi Qi Qi
Disabled
Enabled
DQ ODT
ODT on/off Timing Chart for R1QL series (DDR II+, Burst Length=2, Read Latency=2.0 cycle)
Read Read Read Read
(B2) (B2) (B2) (B2)
Write Write Write Write Read Read Read
(B2) (B2) (B2) (B2) (B2) (B2) (B2)
NOP
NOP NOP
Status
K, /K
Command
DQ
Ra
Rb
Rc
Rd
We
Wf
Wg
Wh
Ri
Rj
Rk
Qa Qa Qb Qb Qc Qc Qd Qd
Disabled
De De Df Df Dg Dg Dh Dh
Enabled
Qi Qi Qj Qj Qk Qk
Disabled
Enabled
DQ ODT
ODT on/off Timing Chart for R1QM series (DDR II+, Burst Length=4, Read Latency=2.0 cycle)
Read
(B4)
Read
(B4)
Write
(B4)
Write
(B4)
Read
(B4)
Read
(B4)
NOP
-
-
NOP NOP
-
-
-
Status
K, /K
Command
DQ
Ra
Rc
We
Wg
Ri
Rk
Qa Qa Qa Qa Qc Qc Qc Qc
Disabled
De De De De Dg Dg Dg Dg
Enabled
Qi Qi Qi Qi Qk Qk
Disabled
Enabled
DQ ODT
Notes
1. ODT on/off switching timings are edge aligned with CQ or /CQ.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
- - -
R1GAA72 / R1QKA72 Series
K Truth Table
Operation
K
/R /W
D or Q
Data in
Write Cycle:
Input
data
Input
clock
Load address, input write
data on two consecutive
K and /K rising edges
D(A+0) D(A+1) D(A+2) D(A+3)
Ĺ
H*7 L*8
K(t+1)Ĺ /K(t+1)Ĺ K(t+2)Ĺ /K(t+2)Ĺ
Data out
Read Cycle:
Output
data
Q(A+0) Q(A+1) Q(A+2) Q(A+3)
Load address, output
read data on two
consecutive C and /C
rising edges
Ĺ
Ĺ
L*8
×
RL*9=1.5 /C(t+1)Ĺ C(t+2)Ĺ /C(t+2)Ĺ C(t+3)Ĺ
Input
clock RL=2.0 C(t+2)Ĺ /C(t+2)Ĺ C(t+3)Ĺ /C(t+3)Ĺ
for Q
RL=2.5 /C(t+2)Ĺ C(t+3)Ĺ /C(t+3)Ĺ C(t+4)Ĺ
NOP (No operation)
Standby (Clock stopped) Stopped
Notes:
H
×
H D = × or Q = High-Z
Previous state
×
1. H: high level, L: low level, ×: don’t care, Ĺ: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C
rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising
edges.
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are
registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K =
high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This
condition is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
7. If this signal was low to initiate the previous cycle, this signal becomes a “don’t care” for this
operation; however, it is strongly recommended that this signal be brought high, as shown in
the truth table.
8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE
operations on consecutive K clock rising edges is not permitted. The device will ignore the
second request.
9. RL = Read Latency (unit = cycle).
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
Byte Write Truth Table ( x 36 )
Operation
K
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
/K
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
/BW0
L
L
L
L
H
H
H
H
H
H
H
H
/BW1
L
L
H
H
L
L
H
H
H
H
H
/BW2
L
L
H
H
H
H
L
L
H
H
H
/BW3
L
L
H
H
H
H
H
H
L
L
H
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
Ĺ
H
H
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 18 )
Operation
K
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
/K
-
Ĺ
-
Ĺ
-
Ĺ
-
/BW0
/BW1
L
L
L
L
L
H
H
L
L
H
H
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
L
H
H
H
H
Ĺ
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 9 )
Just Reference except R1Q2A**09 series
Operation
K
Ĺ
-
Ĺ
-
/K
-
Ĺ
-
/BW
L
L
H
H
Write D0 to D8
Write nothing
Ĺ
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
---
R1GAA72 / R1QKA72 Series
Bus Cycle State Diagram
/R = H & RCount = 4
/R = H
RCount
= 2
Load New
Increment
Read Address
by Two*1
Always
Read Double
RCount
/R = L
Read Port NOP
Read Address
R
Init = 0
RCount = 0
= RCount + 2
R
Init = 1
RInit = 0
/R = L
&
Always
R
Count = 4
Supply voltage
provided
Power Up
Supply voltage
provided
WCount
= 2
Always
Load New
Write Double
WCount
Increment
Write Address
by Two*1
Write Port NOP
Write Address
WCount = 0
= WCount + 2
/W = L
Init = 0
/W = L
&
Always
R
WCount = 4
/W = H
/W = H & WCount = 4
Notes:
1. The address is concatenated with two additional internal LSBs to facilitate burst operation. The
address order is always fixed as: xxx…xxx+0, xxx…xxx+1, xxx…xxx+2, xxx…xxx+3.
Bus cycle is terminated at the end of this sequence (burst count = 4).
2. Read and write state machines can be active simultaneously. Read and write cannot be
simultaneously initiated. Read takes precedence.
3. State machine control timing sequence is controlled by K.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
−0.5 to VDD + 0.5
Input voltage on any ball
VIN
V
1, 4
(2.5 V max.)
−0.5 to VDDQ + 0.5
Input/output voltage
VI/O
V
1, 4
(2.5 V max.)
Core supply voltage
Output supply voltage
Junction temperature
Storage temperature
Notes:
VDD
VDDQ
Tj
−0.5 to 2.5
−0.5 to VDD
+125 (max)
−55 to +125
V
V
1, 4
1, 4
5
°C
°C
TSTG
1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted the Operation Conditions. Exposure to higher than
recommended voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications
shown in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF
then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to
exceed 2.5 V, whatever the instantaneous value of VDDQ
.
5. Some method of cooling or airflow should be considered in the system. (Especially for high
frequency or ODT parts)
Recommended DC Operating Conditions
Parameter
Symbol
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
Min
1.7
1.4
Typ
1.8
1.5
0.75
⎯
Max
1.9
VDD
Unit
V
V
V
V
Notes
1
1, 2
Power supply voltage -- core
Power supply voltage -- I/O
Input reference voltage -- I/O
Input high voltage
0.68
VREF + 0.1
−0.3
0.95
3
VDDQ + 0.3
REF − 0.1
1, 4, 5
1, 4, 5
Input low voltage
⎯
V
V
Notes:
1. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ
.
During normal operation, VDDQ must not exceed VDD.
2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum
ratings table due to current from VDDQ
3. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
.
.
4. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing
parameters.
5. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---072M
R1GAA72 / R1QKA72 Series
DC Characteristics
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series, Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V 0.1V, VDDQ = 1.5V, VREF = 0.75V)
Operating Supply Current (Write / Read)
Symbol = IDD. Unit = mA. See Notes 1, 2 and 3 in the page after next.
QDR II+ / DDR II+
QDR II / DDR II
Frequency (max)
(MHz)
Cycle Time (min)
533 500 450 400 375 333 333 300 250 200
1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00
No
(ns)
Part Number
Ą
yy
-19
-20
-22
-25
-27
-30
-30
-33
-40
-50
ă
1
2
x 9 R1Q 2 A72 09ABv- yy
x18 R1Q 2 A72 18ABv- yy
x36 R1Q 2 A72 36ABv- yy
x18 R1Q 3 A72 18ABv- yy
x36 R1Q 3 A72 36ABv- yy
x18 R1Q 4 A72 18ABv- yy
x36 R1Q 4 A72 36ABv- yy
x18 R1Q 5 A72 18ABv- yy
x36 R1Q 5 A72 36ABv- yy
x18 R1Q 6 A72 18ABv- yy
x36 R1Q 6 A72 36ABv- yy
x18 R1Q A A72 18ABv- yy
x36 R1Q A A72 36ABv- yy
x18 R1Q B A72 18ABv- yy
x36 R1Q B A72 36ABv- yy
x18 R1Q C A72 18ABv- yy
x36 R1Q C A72 36ABv- yy
x18 R1Q D A72 18ABv- yy
x36 R1Q D A72 36ABv- yy
x18 R1Q E A72 18ABv- yy
x36 R1Q E A72 36ABv- yy
x18 R1Q F A72 18ABv- yy
x36 R1Q F A72 36ABv- yy
x18 R1Q GA72 18ABv- yy
x36 R1Q GA72 36ABv- yy
x18 R1Q H A72 18ABv- yy
x36 R1Q H A72 36ABv- yy
x18 R1Q J A72 18ABv- yy
x36 R1Q J A72 36ABv- yy
x18 R1Q K A72 18ABv- yy
x36 R1Q K A72 36ABv- yy
x18 R1Q L A72 18ABv- yy
x36 R1Q L A72 36ABv- yy
x18 R1QM A72 18ABv- yy
x36 R1QM A72 36ABv- yy
760 670
890 780
950 830
B2
QDRII
DDRII
3
5
880 820 730
910 850 750
750 700 630
810 760 680
660 630 590
700 670 630
750 700 630
810 760 680
B4
B2
B4
B2
6
8
9
11
12
14 DDRII
15 SIO
17
1220 1160 1070
1280 1220 1130
1030 990 920
1110 1060 990
820 790 750
880 850 800
1220 1160 1070
1280 1220 1130
1030 990 920
1110 1060 990
820 790 750
880 850 800
QDRII+ B4
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
1070 980
1150 1060
920 850
990 910
750 710
800 760
1070 980
1150 1060
920 850
990 910
750 710
800 760
QDRII+ B4
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Notes:
1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---072M
R1GAA72 / R1QKA72 Series
Standby Supply Current (NOP)
Symbol = ISB1. Unit = mA. See Notes 2, 4 and 5 in the next page.
QDR II+ / DDR II+
Frequency (max)
QDR II / DDR II
533 500 450 400 375 333 333 300 250 200
1.875 2.00 2.22 2.50 2.66 3.00 3.00 3.30 4.00 5.00
(MHz)
Cycle Time (min)
(ns)
No
Part Number
Ą
yy
-19
-20
-22
-25
-27
-30
-30
-33
-40
-50
ă
1
2
x 9 R1Q 2 A72 09ABv- yy
x18 R1Q 2 A72 18ABv- yy
x36 R1Q 2 A72 36ABv- yy
x18 R1Q 3 A72 18ABv- yy
x36 R1Q 3 A72 36ABv- yy
x18 R1Q 4 A72 18ABv- yy
x36 R1Q 4 A72 36ABv- yy
x18 R1Q 5 A72 18ABv- yy
x36 R1Q 5 A72 36ABv- yy
x18 R1Q 6 A72 18ABv- yy
x36 R1Q 6 A72 36ABv- yy
x18 R1Q A A72 18ABv- yy
x36 R1Q A A72 36ABv- yy
x18 R1Q B A72 18ABv- yy
x36 R1Q B A72 36ABv- yy
x18 R1Q C A72 18ABv- yy
x36 R1Q C A72 36ABv- yy
x18 R1Q D A72 18ABv- yy
x36 R1Q D A72 36ABv- yy
x18 R1Q E A72 18ABv- yy
x36 R1Q E A72 36ABv- yy
x18 R1Q F A72 18ABv- yy
x36 R1Q F A72 36ABv- yy
x18 R1Q GA72 18ABv- yy
x36 R1Q GA72 36ABv- yy
x18 R1Q H A72 18ABv- yy
x36 R1Q H A72 36ABv- yy
x18 R1Q J A72 18ABv- yy
x36 R1Q J A72 36ABv- yy
x18 R1Q K A72 18ABv- yy
x36 R1Q K A72 36ABv- yy
x18 R1Q L A72 18ABv- yy
x36 R1Q L A72 36ABv- yy
x18 R1QM A72 18ABv- yy
x36 R1QM A72 36ABv- yy
570 510
670 600
710 630
B2
QDRII
DDRII
3
5
630 590 520
650 610 540
650 610 560
710 670 610
540 510 480
570 540 500
650 610 560
710 670 610
B4
B2
B4
B2
6
8
9
11
12
14 DDRII
15 SIO
17
870 830 780
910 870 810
870 840 780
960 920 860
690 660 630
730 710 670
870 830 780
910 870 810
870 840 780
960 920 860
690 660 630
730 710 670
QDRII+ B4
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41
42
44
45
47
48
50
51
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
780 720
830 770
780 720
860 790
630 590
670 630
780 720
830 770
780 720
860 790
630 590
670 630
QDRII+ B4
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
Notes:
1. "v" represents the package size. If "v" = "G" then size is 15 x 17 mm, and if "v" = "B" then 13 x 15 mm.
2. "yy" represents the speed bin. "R1QAA7236ABB-20" can operate at 500 MHz(max) of frequency, for example.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
Leakage Currents & Output Voltage
Parameter
Input leakage current
Output leakage current
Symbol
ILI
Min
−2
−5
Max
2
5
Unit
μA
μA
Test condition Notes
10
11
ILO
VOH
V
DDQ − 0.2
VDDQ
V
V
V
V
|IOH| ≤ 0.1 mA
8, 9
8, 9
8, 9
8, 9
(Low)
Output high voltage
VDDQ/2
− 0.12
VDDQ/2
+ 0.12
VOH
Note 6
VOL
(Low)
VSS
0.2
IOL ≤ 0.1 mA
Output low voltage
Notes:
VDDQ/2
− 0.12
VDDQ/2
+ 0.12
VOL
Note 7
1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
I
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of
device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100% write
cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)).
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and
WRITE cycles are completed. )
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω ≤ RQ ≤ 350 Ω.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
10. 0 ≤ VIN ≤ VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec.
11. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---72M_36M
R1GAA72 / R1QKA72 Series
Thermal Resistance
Parameter
Junction to Ambient
Junction to Case
Notes:
Symbol Airflow
Typ
11.0
4.4
Unit
Test condition
Notes
șJA
șJC
1 m/s
-
°C/W
EIA/JEDEC JESD51
1
1. These parameters are calculated under the condition. These are reference values.
2. Tj = Ta + șJA Pd
Tj = Tc + șJC Pd
where
Tj : junction temperature when the device has achieved a steady-state
after application of Pd (rC)
Ta : ambient temperature (rC)
Tc : temperature of external surface of the package or case (rC)
șJA : thermal resistance from junction-to-ambient (rC/W)
șJC : thermal resistance from junction-to-case (package) (rC/W)
Pd : power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)
Capacitance
(Ta = +25°C, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V)
Parameter
Input capacitance
(SA, /R, /W, /BW, D(separate))
Clock input capacitance (K, /K, C, /C)
Output capacitance
Symbol Min Typ Max Unit Test condition Notes
CIN
CCLK
CI/O
⎯
⎯
⎯
4
4
5
5
5
6
pF
pF
pF
VIN = 0 V
VCLK = 0 V
VI/O = 0 V
1, 2
1, 2
1, 2
(Q(separate), DQ(common), CQ, /CQ)
Notes:
1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
Input waveform (Rise/fall time ≤ 0.3 ns)
1.25V
0.75V
Test points
0.75V
0.25V
Output waveform
VDDQ/2
Test points
VDDQ/2
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
Output load conditions Output load and voltage conditions
VDDQ / 2
= 0.75V
1.8V 0.1V
1.5V
VDDQ / 2
= 0.75V
50Ω
Z0 = 50Ω
250Ω
AC Operating Conditions
Parameter
Input high voltage
Input low voltage
Symbol
VIH (AC)
VIL (AC)
Min
VREF + 0.2
Typ
⎯
⎯
Max
⎯
VREF – 0.2
Unit
V
V
Notes
1, 2, 3, 4
1, 2, 3, 4
⎯
Notes:
1. All voltages referenced to VSS (GND).
During normal operation, VDDQ must not exceed VDD.
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates
less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level,
VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level,
VIL (DC) or VIH (DC).
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=00000.0000.0000.0111.0111---
00000.0000.0000.0111.0111---
00000.0000.0000.0000.0000---RL=2.0
R1GAA72 / R1QKA72 Series
AC Characteristics (Read Latency = 2.0 cycle)
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V 0.1V, VDDQ = 1.5V, VREF = 0.75V)
-19
-20
-22
-25
-27
-30
Unit Notes
Parameter
Symbol
Min Max Min Max Min Max Min Max Min Max Min Max
Clock
Average clock
cycle time
(K, /K)
tKHKH 1.875 4.00 2.00 4.00 2.22 4.00 2.50 4.00 2.66 4.00 3.00 4.00 ns
Clock high time
(K, /K)
Cy-
tKHKL
0.40
0.40
⎯
⎯
⎯
0.40
0.40
⎯
⎯
⎯
0.40
0.40
⎯
⎯
⎯
0.40
0.40
⎯
⎯
⎯
0.40
0.40
⎯
⎯
⎯
0.40
0.40
⎯
⎯
⎯
cle
Clock low time
(K, /K)
Cy-
cle
tKLKH
Clock to /clock
(K to /K)
Cy-
cle
tKH/KH 0.425
t/KHKH 0.425
0.425
0.425
0.425
0.425
0.425
/Clock to clock
(/K to K)
Cy-
cle
⎯
⎯
0.425
⎯
⎯
0.425
⎯
⎯
0.425
⎯
⎯
0.425
⎯
⎯
0.425
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DLL/PLL Timing
Clock phase
jitter
tKC var
⎯
0.15
⎯
0.15
⎯
0.15
⎯
0.20
⎯
0.20
⎯
0.20 ns
3
(K, /K)
Lock time
(K)
t
KC lock 20
⎯
⎯
20
30
⎯
⎯
20
30
⎯
⎯
20
30
⎯
⎯
20
30
⎯
⎯
20
30
⎯
⎯
us
ns
2
7
K static to
DLL/PLL reset
t
KC reset 30
Output Times
K, /K high to
output valid
tCHQV
⎯
0.55
⎯
⎯
−0.35
⎯
0.55
⎯
⎯
−0.35
⎯
0.55
⎯
⎯
−0.35
⎯
0.55
⎯
⎯
−0.35
⎯
0.55
⎯
⎯
−0.35
⎯
0.55 ns
K, /K high to
output hold
tCHQX −0.35
⎯
ns
K, /K high to
echo clock valid
tCHCQV
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55 ns
K, /K high to
echo clock hold
tCHCQX −0.35
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
−0.35
⎯
⎯
ns
CQ, /CQ high to
output valid
tCQHQV
⎯
0.15
⎯
0.15
⎯
0.15
⎯
0.20
⎯
0.20
⎯
0.20 ns 4, 7
CQ, /CQ high to
output hold
tCQHQX −0.15
−0.15
⎯
−0.15
⎯
−0.20
⎯
−0.20
⎯
−0.20
⎯
⎯
ns 4, 7
K, /K high to
output high-Z
tCHQZ
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55
⎯
0.55 ns 5, 6
K, /K high to
output low-Z
tCHQX1 −0.35
−0.35
−0.35
−0.35
−0.35
−0.35
⎯
ns
5
7
/CQ high to
QVLD valid
tQVLD −0.15 0.15 −0.15 0.15 −0.15 0.15 −0.20 0.20 −0.20 0.20 −0.20 0.20 ns
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=00000.0000.0000.0111.0111---
00000.0000.0000.0111.0111---
00000.0000.0000.0000.0000---RL=2.0
R1GAA72 / R1QKA72 Series
-19
-20
-22
-25
-27
-30
Parameter
Symbol
Unit Notes
Min Max Min Max Min Max Min Max Min Max Min Max
Setup Times
tAVKH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Address valid to
K rising edge
(QDRII+ B2)
ns
1, 8
tAVKH
0.30
0.33
0.40
0.40
0.40
0.40
(QDRII+ B4 & DDRII+)
tIVKH
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Control inputs
valid to
(QDRII+ B2)
ns
ns
1, 8
1, 9
K rising edge
tIVKH
0.30
0.20
0.33
0.22
0.40
0.25
0.40
0.28
0.40
0.28
0.40
0.28
(QDRII+ B4 & DDRII+)
Data-in valid to
K, /K rising edge
tDVKH
Hold Times
tKHAX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
K rising edge
to address hold
(QDRII+ B2)
ns
1, 8
tKHAX
0.30
0.33
0.40
0.40
0.40
0.40
(QDRII+ B4 & DDRII+)
tKHIX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
K rising edge
to control inputs
hold
(QDRII+ B2)
ns
ns
1, 8
1, 9
tKHIX
0.30
0.20
0.33
0.22
0.40
0.25
0.40
0.28
0.40
0.28
0.40
0.28
(QDRII+ B4 & DDRII+)
K, /K rising edge
to data-in hold
tKHDX
Notes:
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and
hold times for all latching clock edges.
2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock
time begins once VDD , VDDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
This specification meets the QDR common spec. of 20 us.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from
echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured 100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQV
.
7. These parameters are sampled.
8. tAVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number (Marking
Name). The following is the spec for the actual frequency.
0.30 ns for 533MHz & >500MHz
0.33 ns for 500MHz & >450MHz
0.40 ns for 450MHz & 250MHz
9. tDVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The
following is the spec for the actual frequency.
0.20 ns for 533MHz & >500MHz
0.22 ns for 500MHz & >450MHz
0.25 ns for 450MHz & >400MHz
0.28 ns for 400MHz & 250MHz
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. VDDQ is +1.5 V DC. VREF is +0.75 V DC.
4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=00000.0000.0000.0100.0100---
00000.0000.0000.0100.0100---00000.0000.0000.0100.0100---
R1QA_RL=2.0
R
R1GAA72 / R1QKA72 Series
Timing Waveforms
Read and Write Timing (QDRII+, B4, Read Latency = 2.0 cycle)
1
2
3
4
5
6
7
8
9
NOP
READ
WRITE
READ
WRITE
NOP
NOP
NOP
K
/K
tKHKL
tKLKH
tKH/KH
t/KHKH
tKHKH
/R
tIVKH
tKHIX
/W
tIVKH
tKHIX
A0
A1
tKHAX
A2
A3
Address
Data in
tAVKH
D10 D11 D12 D13 D30 D31 D32 D33
tDVKH
tDVKH
tKHDX
tKHDX
Data out
CQ
/CQ
QVLD
Notes:
1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address
following A0, i.e., A0+1.
2. Outputs are disabled (high-Z) N clock cycle after the last read cycle. Here, N = Read Latency + Burst
Length × 0.5.
3. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded
immediately as read results.
4. To control read and write operations, /BW signals must operate at the same timing as Data-in signals.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up
resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O Pin assignments Description
Notes
Test clock input. All inputs are captured on the rising edge of
TCK and all outputs propagate from the falling edge of TCK.
Test mode select. This is the command input for the TAP
controller state machine.
TCK
TMS
2R
10R
Test data input. This is the input side of the serial registers
placed between TDI and TDO. The register placed between
TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in
the TAP instruction.
Test data output. Output changes in response to the falling
edge of TCK. This is the output side of the serial registers
placed between TDI and TDO.
TDI
11R
1R
TDO
Notes:
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while
TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM
POWER-UP.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
TAP DC Operating Characteristics
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V 0.1V)
Parameter
Symbol
VIH
Min
+1.3
−0.3
−5.0
Typ
⎯
⎯
Max
VDD + 0.3
+0.5
Unit
V
V
Notes
Input high voltage
Input low voltage
Input leakage current
VIL
ILI
⎯
+5.0
μA
0 V ≤ VIN ≤ VDD
0 V ≤ VIN ≤ VDD,
Output leakage current
Output low voltage
Output high voltage
ILO
−5.0
⎯
+5.0
μA
output disabled
VOL1
VOL2
VOH1
VOH2
⎯
⎯
1.6
1.4
⎯
⎯
⎯
⎯
0.2
0.4
⎯
V
V
V
V
IOLC = 100 μA
IOLT = 2 mA
|IOHC| = 100 μA
|IOHT| = 2 mA
⎯
Notes:
1. All voltages referenced to VSS (GND).
2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ
.
During normal operation, VDDQ must not exceed VDD.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
TAPAC Test Conditions
Parameter
Input timing measurement reference levels
Input pulse levels
Symbol
VREF
VIL, VIH
tr, tf
Conditions
0.9
0 to 1.8
≤ 1.0
0.9
0.9
See figures
Unit Notes
V
V
ns
V
V
Input rise/fall time
Output timing measurement reference levels
Test load termination supply voltage (VTT)
Output load
Input waveform
1.8V
0.9V
0V
Test points
0.9V
Output waveform
0.9V
Test points
0.9V
Output load condition
VTT = 0.9V
DUT
TDO
50Ω
Z0 = 50Ω
20pF
External Load at Test
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
TAPAC Operating Characteristics
(Ta = 0 ~ +70°C @ R1Q*A*****BB-**R** series)
(Ta = -40 ~ +85°C @ R1Q*A*****BB-**I** series)
(VDD = 1.8V 0.1V)
Parameter
Test clock (TCK) cycle time
TCK high pulse width
TCK low pulse width
Test mode select (TMS) setup
TMS hold
Symbol
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
Min
50
20
20
5
5
5
5
5
Typ
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Capture setup
Capture hold
1
1
tCH
TDI valid to TCK high
TCK high to TDI invalid
TCK low to TDO unknown
TCK low to TDO valid
Notes:
tDVTH
tTHDX
tTLQX
tTLQV
5
0
⎯
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
TMS
TDI
tMVTH
tTHMX
tDVTH
tTHDX
tTLQV
TDO
tTLQX
tCS
tCH
PI
(SRAM
Test Access Port Registers
Register name
Instruction register
Bypass register
Length
3 bits
1 bit
Symbol
IR [2:0]
BP
Notes
ID register
Boundary scan register
32 bits
109 bits
ID [31:0]
BS [109:1]
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
TAP Controller Instruction Set
IR2 IR1 IR0 Instruction
Description
Notes
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register cells
at output balls are used to apply test vectors, while those at
input balls capture test results. Typically, the first test vector to
be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output driver is
turned on and the PRELOAD data is driven onto the output balls.
0
0
0
0
0 EXTEST
1 IDCODE
1, 2, 3, 5
The IDCODE instruction causes the ID ROM to be loaded into
the ID register when the controller is in capture-DR mode and
places the ID register between the TDI and TDO balls in shift-
DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in
the Test-Logic-Reset state.
If the SAMPLE-Z instruction is loaded in the instruction register,
all RAM outputs are forced to an inactive drive state (high-Z),
moving the TAP controller into the capture-DR state loads the
data in the RAMs input into the boundary scan register, and the
boundary scan register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
0
0
1
1
0 SAMPLE-Z
1 RESERVED
3, 4, 5
The RESERVED instructions are not implemented but are
reserved for future use. Do not use these instructions.
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR state
loads the data in the RAMs input and I/O buffers into the
boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the TAP
to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although
allowing the TAP to SAMPLE metastable input will not harm the
device, repeatable results cannot be expected. Moving the
controller to shift-DR state then places the boundary scan
register between the TDI and TDO balls.
SAMPLE
0
1
0
3, 5
(/PRELOAD)
1
1
0
1
1 RESERVED
0 RESERVED
-
-
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the shift-DR state.
This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
1
1
1 BYPASS
Notes:
1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal
operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture
setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required after boundary scan.
5. For R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, ODT is disabled in EXTEST,
SAMPLE-Z or SAMPLE mode.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
72---
R1GAA72 / R1QKA72 Series
Boundary Scan Order
Signal names
x18
/C or NC /C or NC /C or NC
Signal names
Bit # Ball ID
Bit # Ball ID
x9
x36
x9
x18
x36
D6
1
2
6R
6P
36
37
10E
10D
D3
D6
or ODT
or ODT
or ODT
C
C
C
NC
NC
D15
or QVLD or QVLD or QVLD
3
4
5
6
7
8
9
6N
7P
7N
7R
8R
SA
SA
SA
SA
SA
SA
SA
Q0
D0
NC
NC
NC
NC
NC
NC
Q1
D1
NC
NC
NC
NC
NC
NC
Q2
D2
ZQ
NC
NC
NC
NC
NC
NC
Q3
SA
SA
SA
SA
SA
SA
SA
Q0
D0
NC
NC
Q1
D1
NC
NC
Q2
D2
NC
NC
Q3
D3
NC
NC
Q4
D4
ZQ
NC
NC
Q5
D5
NC
NC
Q6
SA
SA
SA
SA
SA
SA
SA
Q0
D0
D9
Q9
Q1
D1
D10
Q10
Q2
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
NC
NC
NC
NC
NC
Q4
D4
NC
NC
CQ
SA
SA
SA
SA
NC
/R
NC
Q7
D7
NC
NC
Q8
D8
NC
NC
CQ
SA
SA
SA
SA
NC
/R
Q15
Q7
D7
D16
Q16
Q8
8P
9R
D8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
D17
Q17
CQ
NC
SA
SA
SA
NC
/R
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
D2
NC
/BW
K
NC
/BW0
K
/BW1
/BW0
K
D11
Q11
Q3
/K
/K
/K
D3
NC
NC
/W
NC
/BW1
/W
SA
SA
SA
NC
/CQ
Q9
D9
/BW3
/BW2
/W
SA
SA
D12
Q12
Q4
9K
10J
11J
11H
10G
9G
11F
11G
9F
SA
SA
SA
SA
/CQ
NC
NC
NC
NC
NC
D4
ZQ
D13
Q13
Q5
SA
NC
/CQ
Q18
D18
D27
Q27
Q19
D5
D14
Q14
Q6
NC
NC
Q10
10F
11E
3D
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
---
R1GAA72 / R1QKA72 Series
Boundary Scan Order
Signal names
Signal names
x18
Bit # Ball ID
Bit # Ball ID
x9
NC
NC
NC
Q5
x18
D10
NC
x36
D19
D28
Q28
Q20
D20
D29
Q29
Q21
D21
D30
Q30
Q22
D22
/DOFF
D31
Q31
Q23
D23
x9
Q7
D7
NC
NC
NC
NC
NC
NC
Q8
D8
NC
NC
SA
SA
SA
SA
SA
SA
x36
Q24
D24
D33
Q33
Q25
D25
D34
Q34
Q26
D26
D35
Q35
SA
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
91
92
2L
3L
Q15
D15
NC
NC
93
94
1M
1L
Q11
D11
NC
NC
D5
95
96
97
98
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
Q16
D16
NC
NC
NC
NC
NC
NC
NC
Q6
NC
Q12
D12
NC
NC
99
Q17
D17
NC
NC
SA
SA
SA
SA
SA
100
101
102
103
104
105
106
107
108
NC
Q13
D13
/DOFF
NC
NC
Q14
D14
D6
/DOFF
NC
NC
NC
NC
SA
SA
SA
SA
2J
3K
3J
SA
SA
INTER-
NAL
INTER-
NAL
INTER-
NAL
89
90
2K
1K
NC
NC
NC
NC
D32
Q32
109
⎯
⎯
⎯
⎯
⎯
⎯
Notes:
In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for
reliable operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K
(except EXTEST, SAMPLE-Z).
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
R1GAA72 / R1QKA72 Series
ID Register
Revision
Type number
(28 : 12)
Start bit (0) ăŇ
-
Vendor JEDEC code
(11 : 1)
number
䊼
䊼
0
(31 :29)
#
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
1
1
1
Symbol
R
R
R
0
C
M M M A W W
0
1
Q
Q
Q
B
O
S
0
0
1
1
R
0
0
0
0
R
0
0
1
1
:
R
0
1
0
1
Q
0
1
Revison 0
Revison 1
Revison 2
Revison 3
:
II (QDR-II, DDR-II)
II+ (QDR-II+, DDR-II+)
Q
0
1
DDR
QDR
Q
C
36M&72M w/o ODT, 144M,288M
36M&72M w/ ODT
M M M
Latency=1.5 (@II), Latency=2.0 (@II+)
Latency=2.5 (@II+)
0
1
0
1
B
0
1
Density = 36Mb
Density = 72Mb
Density = 144Mb
Density = 288Mb
Burst Length = 2 word burst
Burst Length = 4 word burst
O
0
0
1
1
1
1
0
1
0
1
1
0
without ODT
with ODT
0
1
A
0
1
144M&288M w/o ODT, 36M,72M
144M&288M w/ ODT
W W
S
0
1
Common I/O
Separate I/O
x9
x18
x36
0
1
1
0
0
1
TAP Controller State Diagram
1
Test Logic Reset
0
1
1
1
Run Test/Idle
Select DR Scan
Select IR Scan
0
0
0
1
1
Capture DR
Capture IR
0
0
0
Shift IR
1
0
Shift DR
1
Exit1 DR
0
1
1
Exit1 IR
0
0
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
Update DR
Update IR
1
0
1
0
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---72M_36M
R1GAA72 / R1QKA72 Series
Package Dimensions and Marking Information
Both Pb parts and Pb-free parts are available.
JEITA Package Code
P-LBGA165-13x15-1.00
Renesas Code
PLBG0165FE-A
Previous Code
165FHG
Mass (typ.)
0.5g
D
B
A
Top View
Index Mark
Marking Information
(Laser Mark)
1st row : Vender name (RENESAS)
2nd row: Part number
3rd row : Y
WW
: Year code
: Week code
E
XXXX : Renesas
internal use
This part
number or
mark is just
one example.
4th row : Country name (JAPAN)
+ "None" --- Pb-free parts
+ "PB-F" --- Pb-free parts
S
Side View
A
A1
- y S
Z
D
[e]
Bottom View
[e]
Dimension in mm
Reference
Symbol
Min Nom Max
12.9 13.0 13.1
14.9 15.0 15.1
D
E
A
-
-
1.4
0.31 0.36 0.41
1.0
0.45 0.5 0.6
A1
[e]
b
Z
E
-
-
1
2
3
4
5
6
7
8
9
10 11
x
y
-
-
-
-
-
0.2
0.15
-
Øb
-
Øx(M) S AB
2.5
Z
D
E
Index Mark
-
1.5
-
Z
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=00000.0100.0100.0100.0100---
00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---72M_QDRII+_B4
R1GAA72 / R1QKA72 Series
Appendix
Example of DC/AC characteristics data
Parts Number : R1QAA7236RBG-19R
IDD (Operating supply current) - tKHKH (Ta=70 degC)
ᵏᵒᵎᵎ
ᵱᵮᵣᵡ
ᵏᵐᵎᵎ
ᵫᶃᵿᶑᶓᶐᶃᶂᴾᶂᵿᶒᵿ
ᵏᵎᵎᵎ
ᵴᶂᶂᵛᵏᵌᵕᵴ
ᵴᶂᶂᵛᵏᵌᵖᵴ
ᵴᶂᶂᵛᵏᵌᵗᵴ
ᵖᵎᵎ
ᵔᵎᵎ
ᵏᵌᵓ
ᵐᵌᵎ
ᵐᵌᵓ
ᵑᵌᵎ
ᶒᵩᵦᵩᵦᴾᵆᶌᶑᵇ
tKHKH (Clock cycle time) Shmoo (Ta=70 degC)
6+/'
ꢀ05
ꢁ05
ꢂ05
ꢃ05
ꢄ05
ꢅ05
8QNVCIG ꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆ
ꢁꢈꢉꢉ8
ꢀꢈꢋꢄ8
ꢀꢈꢋꢉ8
ꢀꢈꢍꢄ8
ꢀꢈꢍꢉ8
ꢀꢈꢎꢄ8
ꢀꢈꢎꢉ8
ꢀꢈꢅꢄ8
ꢀꢈꢅꢉ8
ꢈꢈꢈꢈꢈꢈ222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ2222222222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ2222222222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ2222222222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ2222222222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ2222222222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ222222222222222222222222222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈ222222222222222222222222222222222222222222222ꢊ
ꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆ
2
ꢌꢊ2CUU
ꢌꢊ52'%
Vdd
ꢀ05
ꢁ05
ꢂ05
ꢃ05
ꢄ05
ꢅ05
tKHKH
tCHQV (K, /K high to output valid) Shmoo (Ta=70 degC)
6+/'
ꢉ25
ꢀꢉꢉ25
ꢁꢉꢉ25
ꢂꢉꢉ25
ꢃꢉꢉ25
ꢄꢉꢉ25
8QNVCIG ꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆ
ꢁꢈꢉꢉ8
ꢀꢈꢋꢄ8
ꢀꢈꢋꢉ8
ꢀꢈꢍꢄ8
ꢀꢈꢍꢉ8
ꢀꢈꢎꢄ8
ꢀꢈꢎꢉ8
ꢀꢈꢅꢄ8
ꢀꢈꢅꢉ8
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ2222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ2222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ222222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ2222222222222222222ꢊ
ꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈꢈ2222222222222222222ꢊ
ꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆꢇꢇꢇꢇꢆ
2
ꢌꢊ2CUU
ꢌꢊ52'%
Vdd
ꢉ25
ꢀꢉꢉ25
ꢁꢉꢉ25
ꢂꢉꢉ25
ꢃꢉꢉ25
ꢄꢉꢉ25
tCHQV
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---72M_36M
R1GAA72 / R1QKA72 Series
Revision History (1)
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Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
hinS=11111.1111.1111.1111.1111---
11111.1111.1111.1111.1111---
00000.0000.0000.0000.0000---72M_36M
R1GAA72 / R1QKA72 Series
Revision History (2)
Rev. 0.11 : 2013.01.15
R10DS0172EJ0011
Common
Renesas Electronics Corporation Headquarters: Nippon Bldg., 2-6-2, Ote-machi, Chiyoda-ku, Tokyo 100-0004, Japan
NOTES:
1.
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither
makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document.
Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document,
including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
2.
3.
You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4.
All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date
this document is issued. Such information, however,is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different
information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5.
6.
Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred
as a result of errors or omissions in the information included in this document.
When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the
applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products
for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
The products described in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring
equipment, industrial robotics, domestic appliances, etc.). The products are not designed, manufactured, tested or warranted for applications or otherwise in
systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and
reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power,
or undersea communication transmission. Unintended usage of the products shall be made at the customer’s own risk. Renesas shall have no liability for
damages arising out of the uses set forth above.
7.
8.
Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Electronics Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9.
You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions
or damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a
certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such
as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you
have any other inquiries.
Renesas Sales Offices
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
Renesas Electronics Hong Kong Limited
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Unit 1601-1613, 16/F., Tower 2, Grand Century Place,
193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Taiwan Co., Ltd.
7F, No. 363 Fu Shing North Road Taipei, Taiwan, R.O.C.
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire,
SL8 5FH, U.K
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Renesas Electronics Malaysia Sdn.Bhd.
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-6503-0, Fax: +49-211-6503-1327
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18,
Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District,
Beijing 100083, P.R.China
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku,
Seoul 135-080, Korea
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Tel: +82-2-558-3737, Fax: +82-2-558-5141
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District,
Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
---
© 2013 Renesas Electronics Corporation. All rights reserved.
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