首页 |元器件品牌

R1QLA4436RBG-25IB0 [RENESAS]

144-Mbit DDR™II SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT;
R1QLA4436RBG-25IB0
型号： R1QLA4436RBG-25IB0
厂家： RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述：

144-Mbit DDR™II SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT

双倍数据速率 静态存储器
文件： 总31页 (文件大小：955K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Datasheet  
R1QLA4436RBG, R1QLA4418RBG  
144-Mbit DDR™II+ SRAM 2-word Burst  
R10DS0144EJ0200  
Rev.2.00  
Architecture (2.0 Cycle Read latency) with ODT  
Aug 01, 2014  
Description  
The R1QLA4436RBG is a 4,194,304-word by 36-bit and the R1QLA4418RBG is a 8,388,608-word by 18-bit  
synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor  
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are  
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are  
suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit  
configuration. These products are packaged in 165-pin plastic FBGA package.  
Features  
„ Power Supply  
z
1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)  
„ Clock  
z
z
z
z
Fast clock cycle time for high bandwidth  
Two input clocks (K and /K) for precise DDR timing at clock rising edges only  
Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems  
Clock-stop capability with μs restart  
„ I/O  
z
z
z
z
z
z
Common data input/output bus  
Pipelined double data rate operation  
HSTL I/O  
User programmable output impedance  
PLL circuitry for wide output data valid window and future frequency scaling  
Data valid pin (QVLD) to indicate valid data on the output  
„ Function  
z
z
z
z
Two-tick burst for low DDR transaction size  
Internally self-timed write control  
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
„ Package  
z
165 FBGA package (15 x 17 x 1.4 mm)  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 1 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Part Number Definition  
0
1
2
3
4
5
6
7
8
9
10  
11  
-
12  
13  
14  
15  
16  
Column No.  
Example  
R
1
Q
L
A
4
4
3
6
R
B G  
-
2
5
I
B
0
The above part number is just example for 144M DDRII+ B2 x36 400MHz, 15x17mm PKG, Pb-free part.  
No.  
0-1  
-
Comments  
Renesas Memory Prefix  
No.  
4
-
A
Comments  
Vdd = 1.8 V  
No.  
-
Comments  
R1  
Q2  
Q3  
Q4  
Q5  
Q6  
60  
50  
40  
36  
33  
30  
Frequency = 167MHz  
Frequency = 200MHz  
Frequency = 250MHz  
Frequency = 275MHz  
Frequency = 300MHz  
Frequency = 333MHz  
QDR II B2[*1]  
QDR II B4  
DDR II B2  
DDR II B4  
(L15)[*2]  
(L15)  
(L15)  
(L15)  
36  
72  
44  
88  
09  
Density = 36Mb  
Density = 72Mb  
Density = 144Mb  
Density = 288Mb  
Data width = 9bit  
5-6  
7-8  
DDR II B2 SIO[*3] (L15)  
12-13  
QDR II+ B4 L25[*2]  
DDR II+ B2 L25  
DDR II+ B4 L25  
QA  
QB  
QC  
QD  
QE  
QF  
QG  
QH  
QJ  
QK  
QL  
QM  
QN  
QP  
18  
36  
R
Data width = 18bit  
Data width = 36bit  
1st Generation  
27  
25  
22  
20  
19  
18  
Frequency = 375MHz  
Frequency = 400MHz  
Frequency = 450MHz  
Frequency = 500MHz  
Frequency = 533MHz  
Frequency = 550MHz  
Commercial temp.  
Ta range = 0℃ to 70℃  
Industrial temp.  
Ta range = -40 to 85  
Pb-and Tray  
QDR II+ B4 L25 w/ODT[*4]  
DDR II+ B2 L25 w/ODT  
DDR II+ B4 L25 w/ODT  
QDR II+ B4 L20  
DDR II+ B2 L20  
DDR II+ B4 L20  
QDR II+ B4 L20 w/ODT  
DDR II+ B2 L20 w/ODT  
DDR II+ B4 L20 w/ODT  
QDR II+ B2 L20  
A
2nd Generation  
3rd Generation  
4th Generation  
5th Generation  
6th Generation  
7th Generation  
PKG= BGA 15x17 mm  
PKG= BGA 13x15 mm  
B
C
D
E
F
BG  
BB  
9
2-3  
R
I
14  
℃
℃
10-11  
-
A
B
T
Pb-free and Tray  
Pb-and Tape&Reel  
Pb-free and Tape&Reel  
15  
16  
QDR II+ B2 L20 w/ODT  
S
-
-
0 to 9,  
-
-
A to Z Renesas internal use  
or None  
Note1:  
Note2:  
[*1] B=Burst length (B2: Burst length=2, B4: Burst length=4)  
[*2] L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)  
[*3] SIO=Separate I/O  
[*4] ODT=On die termination  
Package Marking Name  
Pb-parts: Marking Name = Part Number(0-14)  
Pb-free parts: Marking Name = Part Number(0-14) + "PB-F"  
(Example) R1QAA4436RBG-20R Pb-F ----- Pb-parts  
(Example) R1QAA4436RBG-20R PB-F ----- Pb-free parts  
Note3:  
Note4:  
Pb-free: RoHS Compliance Level = 5/6  
Pb-free: RoHS Compliance Level = 6/6  
R1Q*A series support both "Commercial" and "Industrial" temperatures  
by "Industrial" temperature parts.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 2 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Part Number Information  
Datasheet  
Core  
Supply  
Voltage  
(V)  
Operating  
Ambient  
Organization  
Ordering part number  
(word x bit)  
Clock  
frequency  
Cycle time  
Package  
Temperature  
R1QLA4436RBG-25IA0  
R1QLA4418RBG-25IA0  
R1QLA4436RBG-25IB0  
R1QLA4418RBG-25IB0  
4M x 36  
8M x 18  
4M x 36  
8M x 18  
2.50ns  
2.50ns  
2.50ns  
2.50ns  
400MHz  
400MHz  
400MHz  
400MHz  
TA = −40 to 85°C 1.8 ± ±0.1  
165-pin  
PLASTIC BGA  
(15 x 17)  
Pb  
TA = −40 to 85°C 1.8 ± ±0.1  
165-pin  
PLASTIC BGA  
(15 x 17)  
Pb-Free  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 3 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Pin Arrangement  
[R1QLA4436RBG]  
4M x 36  
(Top View)  
1
2
3
4
5
6
/K  
7
8
9
10  
SA  
11  
CQ  
/CQ  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
SA  
R-/W  
SA  
/BW2  
/BW3  
SA  
/BW1  
/BW0  
SA  
/LD  
SA  
NC  
NC  
NC  
NC  
NC  
NC  
A
B
C
D
E
F
DQ27  
NC  
DQ18  
DQ28  
DQ19  
DQ20  
DQ21  
DQ22  
K
SA  
NC  
DQ8  
DQ7  
DQ16  
DQ6  
DQ5  
DQ14  
ZQ  
VSS  
NC  
VSS  
VSS  
VDDQ  
VDDQ  
VDDQ  
DQ17  
NC  
DQ29  
NC  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SA  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VDDQ  
VDDQ  
VDDQ  
DQ15  
NC  
DQ30  
DQ31  
NC  
G
H
J
/DOFF VREF  
VDDQ VDDQ  
VDDQ VDDQ  
VREF  
DQ13  
DQ12  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
TDO  
NC  
NC  
DQ32  
DQ23  
DQ24  
DQ34  
DQ25  
DQ26  
SA  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDDQ  
VDDQ  
VDDQ  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
DQ4  
DQ3  
DQ2  
DQ1  
DQ10  
DQ0  
TDI  
K
L
DQ33  
NC  
DQ11  
NC  
M
N
P
R
DQ35  
NC  
VSS  
VSS  
SA  
SA  
QVLD  
ODT  
SA  
SA  
DQ9  
TMS  
TCK  
SA  
SA  
SA  
SA  
Notes: 1.  
2.  
Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.  
NC pins can be left floating or connected to 0V to VDDQ  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 4 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
[R1QLA4418RBG]  
8M x 18  
(Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
/CQ  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
DQ9  
NC  
SA  
NC  
R-/W  
SA  
/BW1  
NC  
/K  
K
SA  
/BW0  
SA  
/LD  
SA  
SA  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
NC  
CQ  
DQ8  
NC  
NC  
VSS  
SA  
NC  
VSS  
DQ7  
NC  
NC  
DQ10  
DQ11  
NC  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SA  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
NC  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
NC  
DQ6  
DQ5  
NC  
DQ12  
NC  
NC  
G
H
J
DQ13  
NC  
/DOFF VREF  
VDDQ VDDQ  
VDDQ VDDQ  
VREF  
DQ4  
NC  
ZQ  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
NC  
DQ14  
NC  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDDQ  
VDDQ  
VDDQ  
VSS  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
NC  
K
L
DQ3  
DQ2  
NC  
DQ15  
NC  
NC  
M
N
P
R
NC  
DQ1  
NC  
NC  
DQ16  
DQ17  
SA  
VSS  
VSS  
NC  
NC  
SA  
SA  
QVLD  
ODT  
SA  
SA  
NC  
DQ0  
TDI  
TDO  
TCK  
SA  
SA  
SA  
SA  
TMS  
Notes: 1.  
2.  
Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.  
NC pins can be left floating or connected to 0V to VDDQ  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 5 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Pin Descriptions  
Name I/O type  
Descriptions  
Note  
SA  
Input  
Synchronous address inputs: These inputs are registered and must meet the setup  
and hold times around the rising edge of K. These inputs are ignored when device is  
deselected.  
/LD  
Input  
Input  
Synchronous load: This input is brought low when a bus cycle sequence is to be  
defined. This definition includes address and READ/WRITE direction.  
R-/W  
Synchronous read / write Input: When /LD is low, this input designates the access  
type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R-  
/W must meet the setup and hold times around the rising edge of K.  
/BWx  
Input  
Input  
Synchronous byte writes: When low, these inputs cause their respective byte to be  
registered and written during WRITE cycles. These signals are sampled on the same  
edge as the corresponding data and must meet setup and hold times around the  
rising edges of K and /K for each of the rising edge comprising the WRITE cycle. See  
Byte Write Truth Table for signal to data relationship.  
K, /K  
Input clock: This input clock pair registers address and control inputs on the rising  
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is  
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and  
hold times around the clock rising edges. These balls cannot remain VREF level.  
/DOFF  
Input  
Input  
Input  
Input  
PLL disable: When low, this input causes the PLL to be bypassed for stable, low  
frequency operation.  
TMS  
TDI  
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left unconnected if the  
JTAG function is not used in the circuit.  
TCK  
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG  
function is not used in the circuit.  
ZQ  
Output impedance matching input: This input is used to tune the device outputs to  
the system data bus impedance. DQ and CQ output impedance are set to 0.2 × RQ,  
where RQ is a resistor from this ball to ground. This ball can be connected directly to  
VDDQ, which enables the minimum impedance mode. This ball cannot be connected  
directly to VSS or left unconnected.  
ODT  
Input  
ODT control: When low;  
Low range mode is selected. The impedance range is between 52 Ω and 105 Ω  
(Thevenin equivalent), which follows 0.3 × RQ for 175 Ω ≤ RQ ≤ 350 Ω.  
ODT control:When high;  
High range mode is selected. The impedance range is between 105 Ω and 150 Ω  
(Thevenin equivalent), which follows 0.6 × RQ for 175 Ω ≤ RQ ≤ 250 Ω.  
ODT control:When floating;  
High range mode is selected.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 6 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Name  
I/O type  
Input  
Descriptions  
Note  
DQ0 to DQn  
Synchronous data I/Os: Input data must meet setup and hold times around the  
rising edges of K and /K. Output data is synchronized to the K clock.  
Output  
The ×18 device uses DQ0 to DQ17. DQ18 to DQ35 should be treated as NC pin.  
The ×36 device uses DQ0 to DQ35.  
CQ, /CQ  
Output  
Synchronous echo clock outputs: The edges of these outputs are tightly matched  
to the synchronous data outputs and can be used as a data valid indication.  
These signals run freely and do not stop when DQ tri-states.  
TDO  
Output  
Output  
IEEE 1149.1 test output: 1.8 V I/O level.  
QVLD  
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge  
aligned with CQ and /CQ.  
VDD  
Supply  
Supply  
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions  
for range.  
1
1
1
VDDQ  
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC  
Characteristics and Operating Conditions for range.  
VSS  
Supply  
-
Power supply: Ground.  
VREF  
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve  
system noise margin. Provides a reference voltage for the HSTL input buffers.  
NC  
-
No connect: These pins can be left floating or connected to 0V to VDDQ.  
Notes:  
1. All power supply and ground balls must be connected for proper operation of the device.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 7 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Block Diagram  
[R1QLA4436RBG]  
21  
21  
SA  
Address  
ZQ  
/LD  
Registry  
R-/W  
and  
Logic  
K
/K  
CQ, /CQ  
2
DQ  
36  
R-/W  
72  
72  
72  
/LD  
Memory  
Array  
4
Data  
Registry  
and  
/BWx  
K
/K  
Logic  
36  
K
K,/K  
K
[R1QLA4418RBG]  
22  
22  
SA  
Address  
Registry  
and  
ZQ  
/LD  
R-/W  
K
CQ, /CQ  
2
Logic  
/K  
DQ  
18  
R-/W  
/LD  
36  
K
36  
36  
Memory  
Array  
2
Data  
Registry  
and  
/BWx  
K
/K  
Logic  
18  
K
K,/K  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 8 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Power-up and Initialization Sequence  
VDD must be stable before K, /K clocks are applied.  
- Recommended voltage application sequence : VSS → VDD → VDDQ & VREF → VIN. (0 V to VDD, VDDQ < 200 ms)  
- Apply VREF after VDDQ or at the same time as VDDQ  
.
- Then execute either one of the following sequences.  
1. Single Clock Mode  
- Drive /DOFF high (/DOFF can be tied high from the start).  
- Then provide stable clocks (K, /K) for at least 20 us.  
Power Up &  
NOP &  
Normal  
Status  
Unstable Stage  
Set-up Stage  
Operation  
VDD  
VDDQ  
VREF  
Fix High (=Vddq)  
SET-UP Cycle  
/DOFF  
K, /K  
2. PLL Off Mode (/DOFF tied low)  
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us.  
PLL Constraints  
1. These chips use the PLL. The clock input should have low phase jitter which is specified as tKC var.  
2. The lower end of the frequency at which the PLL can operate is 250 MHz.  
(Please refer to AC Characteristics table for detail.)  
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 9 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Programmable Output Impedance  
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).  
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance  
matching with a tolerance of 15% is between 175 Ω and 350 Ω. The total external capacitance of ZQ ball must be  
less than 7.5 pF.  
QVLD (Valid data indicator)  
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q Valid  
indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for  
capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop capturing the data.  
QVLD is edge aligned with CQ and /CQ.  
ODT (On Die Termination)  
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated, especially  
at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of devices.  
2. The ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input.  
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data and  
disabled when the device outputs data.  
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without ODT.  
5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current  
consumption from the I/O voltage supply) with ODT.  
ODT range  
ODT control pin  
Low  
Thevenin equivalent resistance (RTHEV  
)
Unit  
Ω±  
Notes  
0.3 x RQ  
0.6 x RQ  
0.6 x RQ  
1,3  
2
High  
Ω±  
Floating  
Ω±  
2
Notes:  
1. Allowable range of RQ to guarantee impedance matching a tolerance of ± 20 % is 175 Ω ≤ RQ ≤ 350Ω.  
2. Allowable range of RQ to guarantee impedance matching a tolerance of ± 20 % is 175 Ω ≤ RQ ≤ 250 Ω.  
3. ODT control pin is connected to VDDQ through 3.5 kΩ. Therefore it is recommended to connect it to  
VSS through less than 100 Ω to make it low.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 10 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Thevenin termination  
Other LSI  
SRAM with ODT  
VDDQ  
ZQ  
2 × RTHEV  
RQ  
Input  
Buffer  
Output  
Buffer  
2 × RTHEV  
VSS  
VSS  
ODT pin  
Pin name  
ODT On/Off  
Off: First Read Command  
+ Read Latency  
- 0.5 cycle  
On: Last Read Command  
+ Read Latency  
DQ0 to DQn  
+ BL/2 cycle + 0.5 cycle  
(See below timing chart)  
Always On  
/BWx  
K, /K  
Always On  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 11 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
K Truth Table  
Operation  
K
/LD  
R-/W  
DQ  
Data in  
Input  
Write Cycle:  
D(A+0)  
D(A+1)  
Load address, input write  
data on two consecutive  
data  
Input  
clock  
↑
L
L
K and /K rising edges  
K(t+1) ↑  
/K(t+1) ↑  
Data out  
Output  
Read Cycle:  
Q(A+0)  
Q(A+1)  
Load address, output read  
data on two consecutive  
data  
Input  
clock  
↑
L
H
K and /K rising edges  
K(t+2) ↑  
/K(t+2) ↑  
NOP (No operation)  
↑
H
×
×
High-Z  
Standby (Clock stopped)  
Stopped  
×
Previous state  
Notes:  
1. H: high level, L: low level, ×: don’t care, ↑: rising edge.  
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at K clock edges.  
3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at  
the rising edge of K.  
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.  
5. Refer to state diagram and timing diagrams for clarification.  
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, or the  
case of K = high, /K = low. This condition is not essential, but permits most rapid restart by overcoming  
transmission line charging symmetrically.  
7. A+0 refers to the address input during a WRITE or READ cycle. A+1 refers to the next internal burst  
address in accordance with the linear burst sequence.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 12 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Byte Write Truth Table ( x 36 )  
Operation  
K
↑
-
/K  
-
/BW0  
L
/BW1  
L
/BW2  
L
/BW3  
L
Write D0 to D35  
↑
-
L
L
L
L
Write D0 to D8  
Write D9 to D17  
Write D18 to D26  
Write D27 to D35  
Write nothing  
Notes:  
↑
-
L
H
H
H
↑
-
L
H
H
H
↑
-
H
L
H
H
↑
-
H
L
H
H
↑
-
H
H
L
H
↑
-
H
H
L
H
↑
-
H
H
H
L
↑
-
H
H
H
L
↑
-
H
H
H
H
↑
H
H
H
H
1. H: high level, L: low level, ↑: rising edge.  
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation  
provided that the setup and hold requirements are satisfied.  
Byte Write Truth Table ( x 18 )  
Operation  
K
↑
-
/K  
-
/BW0  
/BW1  
Write D0 to D17  
L
L
L
L
↑
-
Write D0 to D8  
Write D9 to D17  
Write nothing  
Notes:  
↑
-
L
H
H
L
↑
-
L
↑
-
H
H
H
H
↑
-
L
↑
-
H
H
↑
1. H: high level, L: low level, ↑: rising edge.  
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation  
provided that the setup and hold requirements are satisfied.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 13 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Bus Cycle State Diagram  
/LD = H & Count = 2  
R-/W = L  
Write Double  
Count  
= Count + 2  
/LD = L  
&
/LD = H  
Count = 2  
/LD = L  
Load New  
Address  
NOP  
Count = 0  
Supply  
voltage  
R-/W = H  
Read Double  
Count  
provided  
= Count + 2  
/LD = L  
&
Power  
Up  
Count = 2  
/LD = H & Count = 2  
Notes:  
1. Bus cycle is terminated at the end of this sequence (burst count = 2).  
2. State machine control timing sequence is controlled by K.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 14 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Electrical Characteristics  
Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
Unit  
Notes  
−0.5 to VDD + 0.5  
(2.5 V max.)  
Input voltage on any ball  
VIN  
V
1,4  
−0.5 to VDDQ + 0.5  
Input/output voltage  
VI/O  
V
1,4  
(2.5 V max.)  
Core supply voltage  
Output supply voltage  
Junction temperature  
Storage temperature  
VDD  
VDDQ  
Tj  
−0.5 to 2.5  
−0.5 to VDD  
+125 (max)  
−55 to +125  
V
V
1,4  
1,4  
5
°C  
°C  
TSTG  
Notes:  
1. All voltage is referenced to VSS.  
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation  
should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended  
periods of time could affect device reliability.  
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables  
after thermal equilibrium has been established.  
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.  
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the  
instantaneous value of VDDQ  
.
5. Some method of cooling or airflow should be considered in the system.  
Recommended DC Operating Conditions  
Parameter  
Symbol  
VDD  
Min  
1.7  
Typ  
1.8  
1.5  
0.75  
-
Max  
1.9  
Unit  
V
Notes  
1
Power supply voltage -- core  
Power supply voltage -- I/O  
Input reference voltage -- I/O  
Input high voltage  
VDDQ  
1.4  
VDD  
V
1,2  
VREF  
0.68  
0.95  
V
3
VIH (DC)  
VIL (DC)  
VREF + 0.1  
-0.3  
VDDQ + 0.3  
VREF - 0.1  
V
1,4,5  
1,4,5  
Input low voltage  
-
V
Notes:  
1.  
At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this  
time, VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD  
.
2.  
3.  
4.  
5.  
Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings table due to current from VDDQ  
.
Peak to peak AC component superimposed on VREF may not exceed 5% of VREF  
.
These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.  
Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2  
Undershoot: VIL (AC) ≥±−0.5 V for t ≤ tKHKH/  
2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 15 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
DC Characteristics  
(TA = -40 to +85°C, VDD = 1.8V ± 0.1V, VDDQ = 1.5V, VREF = 0.75V)  
Parameter  
Symbol  
Test condition  
MIN.  
Unit Notes  
MAX.  
-25  
Operating Supply  
Current  
(x36)  
mA  
mA  
IDD  
1070  
910  
(x18)  
1,2,3  
2,4,5  
(Write / Read)  
Standby Supply  
Current  
(x36)  
(x18)  
ISB1  
880  
770  
(NOP)  
Input leakage current  
Output leakage current  
Output high voltage  
ILI  
μA  
μA  
9
-2  
-5  
2
5
ILO  
10  
VOH  
(Low)  
|IOH| ≤ 0.1 mA  
V
V
V
V
8
8
8
8
VDDQ − 0.2  
DDQ/2 − 0.12  
VSS  
VDDQ  
DDQ/2 + 0.12  
0.2  
Note 6  
IOL ≤ 0.1 mA  
Note 7  
VOH  
V
V
Output low voltage  
VOL  
(Low)  
VOL  
VDDQ/2− 0.12  
V
DDQ/2+ 0.12  
Notes:  
1. All inputs (except ZQ, VREF) are held at either VIH or VIL.  
2. OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.  
I
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of DDR family is current of  
device with 100% write cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) <  
I
DD(Read)).  
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.  
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and  
WRITE cycles are completed. )  
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175±Ω±≤ RQ ≤ 350 Ω.  
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω±≤ RQ ≤ 350±Ω.  
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.  
9. 0 ≤ VIN ≤±VDDQ for all input balls (except VREF, DQn, /BWx, K, /K, ZQ, ODT, TCK, TMS, TDI ball).  
10. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 16 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Thermal Resistance  
Datasheet  
Parameter  
Junction to Ambient  
Junction to Case  
Symbol  
θJA  
Airflow  
1 m/s  
-
Typ  
9.7  
Unit  
Test condition  
Notes  
°C/W  
EIA/JEDEC JESD51  
1
θJC  
4.4  
Notes:  
1. These parameters are calculated under the condition. These are reference values.  
2. Tj = Ta + θJA × Pd  
Tj = Tc + θJC × Pd  
where  
Tj : junction temperature when the device has achieved a steady-state after application of Pd (°C)  
Ta :ambient temperature (°C)  
Tc :temperature of external surface of the package or case (°C)  
θ
JA :thermal resistance from junction-to-ambient (°C/W)  
θJC :thermal resistance from junction-to-case (package) (°C/W)  
Pd :power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)  
Capacitance  
(TA = +25°C, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V)  
Parameter  
Symbol  
CIN  
Min  
Typ  
Max  
Unit  
pF  
Test condition  
VIN = 0 V  
Note  
1,2  
Input capacitance (SA, /R, /W, /BW)  
Clock input capacitance (K, /K)  
Output capacitance (DQ, CQ, /CQ)  
-
-
-
4
4
5
5
5
6
CCLK  
pF  
VCLK = 0 V  
1,2  
CI/O  
pF  
VI/O = 0 V  
1,2  
Notes:  
1. Except JTAG (TCK, TMS, TDI, TDO) pins.  
AC Test Conditions  
Input waveform (Rise/fall time ≤ 0.3 ns)  
1.25V  
0.75V  
Test points  
0.75V  
0.25V  
Output waveform  
VDDQ/2  
Test points  
VDDQ/2  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 17 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Output load conditions  
V
1.8V 0.1V  
1.5V  
= 0.75V  
V
DDQ / 2  
50Ω  
Z0 = 50Ω  
250Ω  
AC Operating Conditions  
Parameter  
Symbol  
VIH (AC)  
VIL (AC)  
Min  
Typ  
Max  
-
Unit  
V
Notes  
1,2,3,4  
1,2,3,4  
Input high voltage  
Input low voltage  
VREF + 0.2  
-
-
-
VREF – 0.2  
V
Notes:  
1. All voltages referenced to VSS (GND). During normal operation, VDDQ must not exceed VDD  
2. These conditions are for AC functions only, not for AC parameter test.  
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2  
.
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2  
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH  
(min).  
4. To maintain a valid level, the transitioning edge of the input must:  
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)  
b. Reach at least the target AC level.  
.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)  
.
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 18 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
AC Characteristics  
(TA = -40 to +85°C, VDD = 1.8V ± 0.1V, VDDQ = 1.5V, VREF = 0.75V)  
Parameter  
Symbol  
Unit  
Notes  
-25  
Min  
Max  
4.00  
Clock  
Average clock cycle time  
(K, /K)  
tKHKH  
tKHKL  
tKLKH  
tKH/KH  
t/KHKH  
2.50  
ns  
Cycle  
Cycle  
Cycle  
Cycle  
Clock high time (K, /K)  
Clock low time (K, /K)  
Clock to /clock (K to /K)  
0.40  
0.40  
-
-
-
-
0.425  
0.425  
/Clock to clock (/K to K)  
PLL Timing  
tKC var  
tKC lock  
tKC reset  
ns  
us  
ns  
3
2
5
Clock phase jitter (K, /K)  
Lock time (K)  
-
0.20  
20  
30  
-
-
K static to PLL reset  
Output Times  
tCHQV  
tCHQX  
ns  
ns  
K, /K high to output valid  
K, /K high to output hold  
-
0.45  
-
-0.45  
K, /K high to  
echo clock valid  
K, /K high to  
echo clock hold  
CQ, /CQ high to  
output valid  
tCHCQV  
tCHCQX  
tCQHQV  
tCQHQX  
ns  
ns  
ns  
ns  
-
0.45  
-0.45  
-
-
0.20  
-
5
5
CQ, /CQ high to  
output hold  
-0.20  
tCHQZ  
tCHQX1  
tQVLD  
ns  
ns  
ns  
4
4
5
K, /K high to output high-Z  
K, /K high to output low-Z  
CQ high to QVLD valid  
-
0.45  
-
-0.45  
-0.20  
0.20  
Setup Times  
Address valid to  
K rising edge  
tAVKH  
tIVKH  
ns  
ns  
ns  
1
1
1
0.40  
0.40  
0.28  
-
-
-
Control inputs valid to  
K rising edge  
Data-in valid to  
K, /K rising edge  
Hold Times  
tDVKH  
K rising edge to  
address hold  
tKHAX  
tKHIX  
ns  
ns  
ns  
1
1
1
0.40  
0.40  
0.28  
-
-
-
K rising edge to  
control inputs hold  
K, /K rising edge to  
data-in hold  
tKHDX  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 19 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Notes:  
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold  
times for all latching clock edges.  
2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time  
begins once VDD , VDDQ and input clock are stable.  
It is recommended that the device is kept inactive during these cycles.  
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.  
4. Transitions are measured ± 100 mV from steady-state voltage.  
5. These parameters are sampled.  
Remarks:  
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.  
2. Control input signals may not be operated with pulse widths less than tKHKL (min).  
3. VDDQ is +1.5 V DC. VREF is +0.75 V DC.  
4. Control signals are /LD and R-/W.  
Setup and hold times of /BWx signals must be the same as those of Data-in signals.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 20 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Read and Write Timing  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
READ  
READ  
READ  
READ  
WRITE  
WRITE  
WRITE  
WRITE  
READ  
READ  
NOP  
NOP  
NOP  
(burst of 2) (burst of 2) (burst of 2) (burst of 2)  
(burst of 2) (burst of 2) (burst of 2) (burst of 2) (burst of 2) (burst of 2)  
K
K, /K  
/LD:R-/W  
SA  
/K  
t
KHKH  
t
KH/KH  
t
/KHKH  
t
KHKL  
tKLKH  
01  
A0  
01  
01  
A2  
01  
1x  
1x  
00  
A4  
00  
A5  
00  
A6  
00  
A7  
01  
A8  
01  
A9  
t
IVKH  
tKHIX  
A1  
A3  
t
AVKH  
t
KHAX  
CHQZ  
DQ  
Q00 Q01 Q10 Q11 Q20 Q21 Q30 Q31  
D40 D41 D50 D51 D60 D61 D70 D71  
Qx0 Qx1  
t
-tCHQX1  
t
-tCCQQHHQQVX  
t
tDKVHKDHX  
t
KHDX  
DVKH  
t
CHQV  
t
-tCCHHQQXV  
-tCHQX  
t
CQ  
/CQ  
t
-tCCHHCCQQXV  
t
-tCCHHCCQQXV  
QVLD  
t
QVLD  
t
-tQQVVLLDD  
-tQVLD  
DQ-ODT  
Enabled  
Disabled  
Disabled  
Enabled  
Disabled  
1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e.,  
A0+1.  
2. In this example, if address A8 = A7, then data Q80 = D70, Q81 = D71, etc. Write data is forwarded immediately as  
read results.  
3. To control read and write operations, /BW signals must operate at the same timing as Data-in signals.  
4. It recommends two NOP cycles during transition from READ to WRITE cycle for correct device operation.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 21 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
JTAG Specification  
These products support a limited set of JTAG functions as in IEEE standard 1149.1.  
Disabling the Test Access Port  
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with  
normal operation of the device, TCK must be tied to VSS to preclude middle level inputs.  
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up resistor.  
TDO should be left unconnected.  
Test Access Port (TAP) Pins  
Symbol I/O Pin assignments  
Description  
Notes  
Test clock input. All inputs are captured on the rising edge of TCK  
and all outputs propagate from the falling edge of TCK.  
TCK  
TMS  
2R  
Test mode select. This is the command input for the TAP controller  
state machine.  
10R  
Test data input. This is the input side of the serial registers placed  
between TDI and TDO. The register placed between TDI and TDO is  
determined by the state of the TAP controller state machine and the  
instruction that is currently loaded in the TAP instruction.  
TDI  
11R  
1R  
Test data output. Output changes in response to the falling edge of  
TCK. This is the output side of the serial registers placed between  
TDI and TDO.  
TDO  
Notes:  
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for  
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.  
TAP DC Operating Characteristics  
(TA = -40 to +85°C , VDD = 1.8V ±0.1V)  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Notes  
Input high voltage  
Input low voltage  
Input leakage current  
VIH  
VIL  
ILI  
+1.3  
-0.3  
-5.0  
-
-
-
VDD + 0.3  
+0.5  
V
V
μA  
+5.0  
0 V ≤ VIN ≤ VDD  
0 V ≤ VIN ≤ VDD,  
output disabled  
IOLC = 100 μA  
IOLT = 2 mA  
|IOHC| = 100 μA  
|IOHT| = 2 mA  
Output leakage current  
ILO  
-5.0  
-
+5.0  
μA  
VOL1  
VOL2  
VOH1  
VOH2  
-
-
-
-
-
0.2  
0.4  
-
V
V
V
V
Output low voltage  
-
1.6  
1.4  
Output high voltage  
-
Notes:  
1. All voltages referenced to VSS (GND).  
2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within  
200ms. During this time, VDDQ < VDD and VIH < VDDQ  
.
During normal operation, VDDQ must not exceed VDD  
.
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 22 of 30  
R1QLA4436RBG, R1QLA4418RBG  
TAP AC Test Conditions  
Datasheet  
Parameter  
Input timing measurement reference levels  
Input pulse levels  
Symbol  
VREF  
Conditions  
0.9  
Unit Notes  
V
V
VIL, VIH  
tr, tf  
0 to 1.8  
Input rise/fall time  
ns  
V
≤ 1.0  
0.9  
Output timing measurement reference levels  
Test load termination supply voltage (VTT)  
Output load  
0.9  
V
See figures  
Input waveform  
1.8V  
0.9V  
0V  
Test points  
0.9V  
Output waveform  
0.9V  
Test points  
0.9V  
Output load condition  
VTT = 0.9V  
DUT  
TDO  
50Ω  
Z0 = 50ΩΩ  
20pF  
External Load at Test  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 23 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Notes  
TAP AC Operating Characteristics  
(TA = -40 to +85°C , VDD = 1.8V ±0.1V)  
Parameter  
Test clock (TCK) cycle time  
TCK high pulse width  
TCK low pulse width  
Test mode select (TMS) setup  
TMS hold  
Symbol  
Min  
50  
20  
20  
5
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tTHTH  
tTHTL  
tTLTH  
tMVTH  
tTHMX  
tCS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
Capture setup  
5
-
Capture hold  
tCH  
5
-
TDI valid to TCK high  
TCK high to TDI invalid  
TCK low to TDO unknown  
TCK low to TDO valid  
tDVTH  
tTHDX  
tTLQX  
tTLQV  
5
-
5
-
0
-
-
10  
Notes:  
1.  
tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 24 of 30  
R1QLA4436RBG, R1QLA4418RBG  
TAP Controller Timing Diagram  
Datasheet  
THTH  
THTL  
TLTH  
t
t
t
TCK  
TMS  
TDI  
MVTH  
t
t
THMX  
DVTH  
t
THDX  
t
t
TLQV  
TDO  
t
CS  
t
CH  
t
TLQX  
PI  
(SRAM)  
Test Access Port Registers  
Register name  
Instruction register  
Bypass register  
Length  
3 bits  
Symbol  
Notes  
IR [2:0]  
BP  
1 bits  
ID register  
32 bits  
109 bit  
ID [31:0]  
BS [109:1]  
Boundary scan register  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 25 of 30  
R1QLA4436RBG, R1QLA4418RBG  
TAP Controller Instruction Set  
Datasheet  
IR2 IR1 IR0 Instruction  
Description  
Notes  
The EXTEST instruction allows circuitry external to the component  
package to be tested. Boundary scan register cells at output balls  
are used to apply test vectors, while those at input balls capture test  
results. Typically, the first test vector to be applied using the  
EXTEST instruction will be shifted into the boundary scan register  
using the PRELOAD instruction. Thus, during the Update-IR state  
of EXTEST, the output driver is turned on and the PRELOAD data is  
driven onto the output balls.  
The IDCODE instruction causes the ID ROM to be loaded into the  
ID register when the controller is in capture-DR mode and places  
the ID register between the TDI and TDO balls in shift-DR mode.  
The IDCODE instruction is the default instruction loaded in at power  
up and any time the controller is placed in the Test-Logic-Reset  
state.  
0
0
0
0
0
1
EXTEST  
IDCODE  
1,2,3,4  
If the SAMPLE-Z instruction is loaded in the instruction register, all  
RAM outputs are forced to an inactive drive state (high-Z), moving  
the TAP controller into the capture-DR state loads the data in the  
RAMs input into the boundary scan register, and the boundary scan  
register is connected between TDI and TDO when the TAP  
controller is moved to the shift-DR state.  
0
0
1
1
0
1
SAMPLE-Z  
RESERVED  
3,4  
The RESERVED instruction is not implemented but is reserved for  
future use. Do not use this instruction.  
When the SAMPLE instruction is loaded in the instruction register,  
moving the TAP controller into the capture-DR state loads the data  
in the RAMs input and I/O buffers into the boundary scan register.  
Because the RAM clock(s) are independent from the TAP clock  
(TCK) it is possible for the TAP to attempt to capture the I/O ring  
SAMPLE  
1
0
0
3,4  
(/PRELOAD) contents while the input buffers are in transition (i.e., in a metastable  
state). Although allowing the TAP to SAMPLE metastable input will  
not harm the device, repeatable results cannot be expected.  
Moving the controller to shift-DR state then places the boundary  
scan register between the TDI and TDO balls.  
The RESERVED instruction is not implemented but is reserved for  
future use. Do not use this instruction.  
The RESERVED instruction is not implemented but is reserved for  
future use. Do not use this instruction.  
1
1
0
1
1
0
RESERVED  
RESERVED  
The BYPASS instruction is loaded in the instruction register when  
the bypass register is placed between TDI and TDO. This occurs  
1
1
1
BYPASS  
when the TAP controller is moved to the shift-DR state. This allows  
the board level scan path to be shortened to facilitate testing of  
other devices in the scan path.  
Notes:  
1. Data in output register is not guaranteed if EXTEST instruction is loaded.  
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.  
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus  
hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except  
capturing the I/O ring contents into the boundary scan register.  
4. Clock recovery initialization cycles are required after boundary scan.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 26 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Boundary Scan Order  
Signal names  
Ball  
Signal names  
Signal names  
Ball  
ID  
Ball  
ID  
Bit#  
ID  
Bit#  
Bit#  
x18  
x36  
x18  
x36  
x18  
x36  
1
2
3
4
5
6
7
8
6R  
6P  
6N  
7P  
7N  
7R  
8R  
8P  
9R  
11P  
10P  
10N  
9P  
10M  
11N  
9M  
ODT  
QVLD  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
DQ0  
NC  
NC  
NC  
DQ1  
NC  
NC  
NC  
DQ2  
NC  
NC  
NC  
DQ3  
NC  
NC  
NC  
DQ4  
NC  
ZQ  
NC  
NC  
DQ5  
NC  
NC  
NC  
DQ6  
NC  
ODT  
QVLD  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
9E  
10C  
11D  
9C  
9D  
11B  
11C  
9B  
10B  
11A  
10A  
9A  
NC  
DQ7  
NC  
NC  
NC  
DQ8  
NC  
NC  
NC  
CQ  
SA  
SA  
SA  
SA  
NC  
/LD  
SA  
/BW0  
K
/K  
NC  
NC  
DQ17  
DQ16  
NC  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
2D  
2E  
1E  
2F  
3F  
1G  
1F  
3G  
2G  
1H  
1J  
NC  
NC  
NC  
DQ12  
NC  
NC  
NC  
DQ13  
NC  
/DOFF  
NC  
NC  
DQ14  
NC  
NC  
NC  
DQ15  
NC  
NC  
NC  
DQ16  
NC  
NC  
DQ29  
NC  
NC  
DQ30  
DQ21  
NC  
NC  
DQ8  
DQ7  
NC  
NC  
CQ  
SA  
SA  
SA  
SA  
NC  
/LD  
/BW1  
/BW0  
K
NC  
DQ22  
DQ31  
/DOFF  
NC  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
DQ0  
DQ9  
NC  
2J  
3K  
3J  
NC  
NC  
8B  
DQ23  
DQ32  
NC  
DQ11  
DQ10  
NC  
7C  
6C  
8A  
7A  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
2A  
1A  
2B  
3B  
1C  
1B  
2K  
1K  
2L  
3L  
1M  
1L  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
-
NC  
9N  
NC  
DQ33  
DQ24  
NC  
11L  
11M  
9L  
10L  
11K  
10K  
9J  
DQ2  
DQ1  
NC  
/K  
NC  
NC  
/BW3  
/BW2  
R-/W  
SA  
SA  
SA  
DQ25  
DQ34  
NC  
DQ3  
DQ12  
NC  
/BW1  
R-/W  
SA  
SA  
SA  
NC  
DQ17  
NC  
NC  
NC  
SA  
SA  
SA  
SA  
NC  
9K  
NC  
DQ26  
DQ35  
NC  
NC  
SA  
SA  
SA  
SA  
SA  
10J  
11J  
11H  
10G  
9G  
11F  
11G  
9F  
10F  
11E  
10E  
10D  
DQ13  
DQ4  
ZQ  
NC  
NC  
DQ5  
DQ14  
NC  
SA  
SA  
/CQ  
DQ9  
NC  
NC  
NC  
DQ10  
NC  
NC  
NC  
DQ11  
/CQ  
DQ27  
DQ18  
NC  
NC  
3D  
3C  
1D  
2C  
3E  
DQ19  
DQ28  
NC  
NC  
DQ20  
SA  
SA  
NC  
SA  
DQ6  
DQ15  
NC  
Internal Internal  
NC  
Notes:  
In boundary scan mode,  
1. Clock balls (K, /K) are referenced to each other and must be at opposite logic levels for reliable operation.  
2. CQ and /CQ data are synchronized to the K clock (except EXTEST, SAMPLE-Z).  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 27 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
ID Register  
Revision  
number  
(31:29)  
Start bit(0)→  
￢
↓
Type number  
(28:12)  
Vendor JEDEC code  
(11:1)  
#
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
1
1
1
0
1
Symbol  
R
R
R
0
C
M
M
M
A
W
W
0
1
Q
Q
Q
B
O
S
0
0
1
R
0
0
0
0
R
0
0
1
1
:
R
0
1
0
1
Q
0
Revision0  
Revision1  
Revision2  
Revision3  
:
II(QDR-II,DDR-II)  
II+(QDR-II+,DDR-II+)  
Q
1
0
1
DDR  
QDR  
C
Q
0
0
1
36M&72M w/o ODT,144M,288M  
36M&72M w/ ODT  
Latency = 1.5(@II).Latency = 2.0(@II+)  
Latency = 2.5(@II+)  
B
1
M
0
0
1
1
M
1
1
0
1
M
0
1
1
0
Density = 36Mb  
Density = 72Mb  
Density = 144Mb  
Density = 288Mb  
A
0
1
Burst Latency = 2 word burst  
Burst Latency = 4 word burst  
O
without ODT  
with ODT  
S
0
1
144M&288M w/o ODT,36M,72M  
144M&288M w/ ODT  
0
1
Common I/O  
0
1
Separate I/O  
W
0
W
0
x9  
1
0
x18  
x36  
1
1
TAP Controller State Diagram  
1
Test Logic Reset  
0
1
1
1
Select IR Scan  
Run Test/Idle  
Select DR Scan  
0
0
0
1
1
Capture DR  
Capture IR  
0
0
0
Shift IR  
1
0
Shift DR  
1
Exit1 DR  
0
1
1
0
Exit1 IR  
0
0
Pause DR  
1
Pause IR  
1
0
0
Exit2 DR  
1
Exit2 IR  
1
Update DR  
Update IR  
1
0
0
1
Notes:  
The value adjacent to each state transition in this figure represents the signal present at TMS at  
the time of a rising edge at TCK.  
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held  
high for at least five rising edges of TCK.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 28 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Package Dimensions and Marking Information  
Both Pb parts and Pb-free parts are available.  
JEITA Package Code  
P-LBGA165-15x17-1.00  
Renesas Code  
PLBG0165FD-B  
Previous Code  
Mass (typ.)  
165FHE-B
ࠉࠉࠉ
0.6g
ࠉ
 
D
B
A
Top View  
Index Mark  
Marking Information  
(Laser Mark)  
1st row : Vender name (RENESAS  
2nd row: Part number  
)
3rd row : Y  
WW  
: Year code  
: Week code  
E
XXXX : Renesas  
internal use  
This part  
number or  
mark is just  
one example.  
4th row : Country name (JAPAN)  
+ "None" --- Pb -free parts  
+ "PB-F" --- Pb-free parts  
S
Side View  
A
A1  
- y S  
Z
[e]  
D
Bottom View  
[e]  
Dimension in mm  
Reference  
Symbol  
Min Nom Max  
14.9 15.0 15.1  
16.9 17.0 17.1  
D
E
A
-
-
1.4  
0.31 0.36 0.41  
1.0  
0.45 0.5 0.6  
A1  
[e]  
b
Z
E
-
-
1
2
3
4
5
6
7
8
9
10 11  
x
y
-
-
-
-
-
0.2  
0.15  
-
Øb  
-
Øx(M) S AB  
2.5  
Z
D
E
Index Mark  
-
1.5  
-
Z
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 29 of 30  
R1QLA4436RBG, R1QLA4418RBG  
Datasheet  
Revision History  
R1QLA4436RBG,R1QLA4418RBG  
Description  
Summary  
Rev.  
Date  
Page  
-
Rev.1.00  
Rev.2.00  
’13.11.01  
’14.08.01  
New Datasheet.  
Modification : DC Characteristics ,Spec of IDD and ISB1.  
P16  
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, and Renesas Electronics Corporation.  
http://www.qdrconsortium.org/  
The information contained herein is subject to change without notice.  
R10DS0144EJ0200 Rev.2.00  
Aug 01, 2014  
Page 30 of 30  
Notice  
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for  
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the  
use of these circuits, software, or information.  
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics  
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.  
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or  
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or  
others.  
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or  
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.  
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on  
the product's quality grade, as indicated below.  
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic  
equipment; and industrial robots etc.  
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.  
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical  
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it  
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses  
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.  
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage  
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the  
use of Renesas Electronics products beyond such specified ranges.  
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and  
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the  
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to  
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,  
please evaluate the safety of the final products or systems manufactured by you.  
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics  
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes  
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.  
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or  
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the  
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and  
regulations and follow the procedures required by such laws and regulations.  
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the  
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics  
products.  
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.  
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.  
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.  
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.  
SALES OFFICES  
http://www.renesas.com  
Refer to "http://www.renesas.com/" for the latest and detailed information.  
Renesas Electronics America Inc.  
2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.  
Tel: +1-408-588-6000, Fax: +1-408-588-6130  
Renesas Electronics Canada Limited  
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada  
Tel: +1-905-898-5441, Fax: +1-905-898-3220  
Renesas Electronics Europe Limited  
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K  
Tel: +44-1628-585-100, Fax: +44-1628-585-900  
Renesas Electronics Europe GmbH  
Arcadiastrasse 10, 40472 Düsseldorf, Germany  
Tel: +49-211-6503-0, Fax: +49-211-6503-1327  
Renesas Electronics (China) Co., Ltd.  
Room 1709, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100191, P.R.China  
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679  
Renesas Electronics (Shanghai) Co., Ltd.  
Unit 301, Tower A, Central Towers, 555 Langao Road, Putuo District, Shanghai, P. R. China 200333  
Tel: +86-21-2226-0888, Fax: +86-21-2226-0999  
Renesas Electronics Hong Kong Limited  
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong  
Tel: +852-2265-6688, Fax: +852 2886-9022/9044  
Renesas Electronics Taiwan Co., Ltd.  
13F, No. 363, Fu Shing North Road, Taipei 10543, Taiwan  
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670  
Renesas Electronics Singapore Pte. Ltd.  
80 Bendemeer Road, Unit #06-02 Hyflux Innovation Centre, Singapore 339949  
Tel: +65-6213-0200, Fax: +65-6213-0300  
Renesas Electronics Malaysia Sdn.Bhd.  
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia  
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510  
Renesas Electronics Korea Co., Ltd.  
12F., 234 Teheran-ro, Gangnam-Ku, Seoul, 135-920, Korea  
Tel: +82-2-558-3737, Fax: +82-2-558-5141  
© 2014 Renesas Electronics Corporation. All rights reserved.  
Colophon 4.0  

相关型号：

SI9130DB

 5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

 SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

 Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明