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R1QPA4436RBG-30IB0 [RENESAS]

144-Mbit QDR™II SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT;
R1QPA4436RBG-30IB0
型号： R1QPA4436RBG-30IB0
厂家： RENESAS TECHNOLOGY CORP    RENESAS TECHNOLOGY CORP
描述：

144-Mbit QDR™II SRAM 2-word Burst Architecture (2.0 Cycle Read latency) with ODT

静态存储器
文件： 总31页 (文件大小：936K)
中文：  中文翻译
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Datasheet  
R1QPA4436RBG,R1QPA4418RBG  
144-Mbit QDR™II+ SRAM 2-word Burst  
R10DS0147EJ0200  
Rev.2.00  
Architecture (2.0 Cycle Read latency) with ODT  
Aug 01, 2014  
Description  
The R1QPA4436RBG is a 4,194,304-word by 36-bit and the R1QPA4418RBG is a 8,388,608-word by 18-bit  
synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor  
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are  
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are  
suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit  
configuration. These products are packaged in 165-pin plastic FBGA package.  
Features  
„ Power Supply  
z
1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ  
)
„ Clock  
z
Fast clock cycle time for high bandwidth  
z
z
z
Two input clocks (K and /K) for precise DDR timing at clock rising edges only  
Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems  
Clock-stop capability with μs restart  
„ I/O  
z
z
z
Separate independent read and write data ports with concurrent transactions  
100% bus utilization DDR read and write operation  
HSTL I/O  
z
User programmable output impedance  
z
z
PLL circuitry for wide output data valid window and future frequency scaling  
Data valid pin (QVLD) to indicate valid data on the output  
„ Function  
z
z
Two-tick burst for low DDR transaction size  
Internally self-timed write control  
z
Simple control logic for easy depth expansion  
JTAG 1149.1 compatible test access port  
z
„ Package  
z
165 FBGA package (15 x 17 x 1.4 mm)  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 1 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Part Number Definition  
0
1
2
3
4
5
6
7
8
9
10  
11  
-
12  
13  
14  
15  
16  
Column No.  
Example  
R
1
Q P  
A
4
4
3
6
R
B G  
-
3
0
I
B
0
The above part number is just example for 144M QDRII+ B2 x36 333MHz, 15x17mm PKG, Pb-free part.  
No.  
0-1  
-
Comments  
Renesas Memory Prefix  
No.  
4
-
A
Comments  
Vdd = 1.8 V  
No.  
-
Comments  
R1  
Q2  
Q3  
Q4  
Q5  
Q6  
60  
50  
40  
36  
33  
30  
Frequency = 167MHz  
Frequency = 200MHz  
Frequency = 250MHz  
Frequency = 275MHz  
Frequency = 300MHz  
Frequency = 333MHz  
QDR II B2[*1]  
QDR II B4  
DDR II B2  
DDR II B4  
(L15)[*2]  
(L15)  
(L15)  
(L15)  
36  
72  
44  
88  
09  
Density = 36Mb  
Density = 72Mb  
Density = 144Mb  
Density = 288Mb  
Data width = 9bit  
5-6  
7-8  
DDR II B2 SIO[*3] (L15)  
12-13  
QDR II+ B4 L25[*2]  
DDR II+ B2 L25  
DDR II+ B4 L25  
QA  
QB  
QC  
QD  
QE  
QF  
QG  
QH  
QJ  
QK  
QL  
QM  
QN  
QP  
18  
36  
R
Data width = 18bit  
Data width = 36bit  
1st Generation  
27  
25  
22  
20  
19  
18  
Frequency = 375MHz  
Frequency = 400MHz  
Frequency = 450MHz  
Frequency = 500MHz  
Frequency = 533MHz  
Frequency = 550MHz  
Commercial temp.  
Ta range = 0℃ to 70℃  
Industrial temp.  
Ta range = -40 to 85  
Pb-and Tray  
QDR II+ B4 L25 w/ODT[*4]  
DDR II+ B2 L25 w/ODT  
DDR II+ B4 L25 w/ODT  
QDR II+ B4 L20  
DDR II+ B2 L20  
DDR II+ B4 L20  
QDR II+ B4 L20 w/ODT  
DDR II+ B2 L20 w/ODT  
DDR II+ B4 L20 w/ODT  
QDR II+ B2 L20  
A
2nd Generation  
3rd Generation  
4th Generation  
5th Generation  
6th Generation  
7th Generation  
PKG= BGA 15x17 mm  
PKG= BGA 13x15 mm  
B
C
D
E
F
BG  
BB  
9
2-3  
R
I
14  
℃
℃
10-11  
-
A
B
T
Pb-free and Tray  
Pb-and Tape&Reel  
Pb-free and Tape&Reel  
15  
16  
QDR II+ B2 L20 w/ODT  
S
-
-
0 to 9,  
-
-
A to Z Renesas internal use  
or None  
Note1:  
Note2:  
[*1] B=Burst length (B2: Burst length=2, B4: Burst length=4)  
[*2] L=Read Latency (L15: Read Latency = 1.5 cycle, L20: 2.0 cycle, L25: 2.5 cycle)  
[*3] SIO=Separate I/O  
[*4] ODT=On die termination  
Package Marking Name  
Pb-parts: Marking Name = Part Number(0-14)  
Pb-free parts: Marking Name = Part Number(0-14) + "PB-F"  
(Example) R1QAA4436RBG-20R Pb-F ----- Pb-parts  
(Example) R1QAA4436RBG-20R PB-F ----- Pb-free parts  
Note3:  
Note4:  
Pb-free: RoHS Compliance Level = 5/6  
Pb-free: RoHS Compliance Level = 6/6  
R1Q*A series support both "Commercial" and "Industrial" temperatures  
by "Industrial" temperature parts.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 2 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Part Number Information  
Core  
Supply  
Voltage  
(V)  
Operating  
Ambient  
Organization  
Ordering part number  
(word x bit)  
Clock  
frequency  
Cycle time  
Package  
Temperature  
R1QPA4436RBG-30IA0  
R1QPA4436RBG-33IA0  
R1QPA4418RBG-30IA0  
R1QPA4418RBG-33IA0  
R1QPA4436RBG-30IB0  
R1QPA4436RBG-33IB0  
R1QPA4418RBG-30IB0  
R1QPA4418RBG-33IB0  
4M x 36  
8M x 18  
4M x 36  
8M x 18  
3.00ns  
3.30ns  
3.00ns  
3.30ns  
3.00ns  
3.30ns  
3.00ns  
3.30ns  
333MHz  
300MHz  
333MHz  
300MHz  
333MHz  
300MHz  
333MHz  
300MHz  
TA = −40 to 85°C  
1.8 ± ±0.1  
165-pin  
PLASTIC BGA  
(15 x 17)  
Pb  
1.8 ± ±0.1  
TA = −40 to 85°C  
165-pin  
PLASTIC BGA  
(15 x 17)  
Pb-free  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 3 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Pin Arrangement  
[R1QPA4436RBG]  
4M x 36  
(Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
/CQ  
Q27  
D27  
D28  
Q29  
Q30  
D30  
/DOFF  
D31  
Q32  
Q33  
D33  
D34  
Q35  
TDO  
SA  
D18  
D19  
Q19  
Q20  
D21  
Q22  
VDDQ  
D23  
Q23  
D24  
D25  
Q25  
Q26  
SA  
/W  
SA  
/BW2  
/BW3  
SA  
/K  
K
/BW1  
/BW0  
SA  
/R  
SA  
D17  
D16  
Q16  
Q15  
D14  
Q13  
VDDQ  
D12  
Q12  
D11  
D10  
Q10  
Q9  
SA  
Q17  
Q7  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
NC  
Q18  
Q28  
D20  
D29  
Q21  
D22  
VREF  
Q31  
D32  
Q24  
Q34  
D26  
D35  
TCK  
SA  
VSS  
SA  
VSS  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SA  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
D15  
D6  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
Q14  
D13  
VREF  
Q4  
G
H
J
K
L
D3  
Q11  
Q1  
M
N
P
R
VSS  
VSS  
D9  
SA  
SA  
QVLD  
ODT  
SA  
SA  
D0  
SA  
SA  
SA  
SA  
SA  
TMS  
Notes: 1.  
2.  
Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.  
NC pins can be left floating or connected to 0V to VDDQ  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 4 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
[R1QPA4418RBG]  
8M x 18  
(Top View)  
1
2
3
4
5
6
7
8
9
10  
11  
A
B
C
D
E
F
/CQ  
NC  
SA  
Q9  
SA  
D9  
/W  
SA  
/BW1  
NC  
/K  
K
/R  
SA  
NC  
NC  
NC  
NC  
NC  
NC  
VDDQ  
NC  
NC  
NC  
NC  
NC  
NC  
SA  
SA  
NC  
Q7  
CQ  
Q8  
D8  
D7  
Q6  
Q5  
D5  
ZQ  
D4  
Q3  
Q2  
D2  
D1  
Q0  
TDI  
NC  
/BW0  
SA  
SA  
NC  
NC  
D10  
Q10  
Q11  
D12  
Q13  
VDDQ  
D14  
Q14  
D15  
D16  
Q16  
Q17  
SA  
VSS  
SA  
SA  
VSS  
NC  
D11  
NC  
VSS  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
VSS  
SA  
VSS  
VSS  
VDD  
VDD  
VDD  
VDD  
VDD  
VSS  
VSS  
SA  
VSS  
NC  
D6  
NC  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VDDQ  
VSS  
NC  
Q12  
D13  
VREF  
NC  
NC  
NC  
VREF  
Q4  
G
H
J
NC  
/DOFF  
NC  
K
L
NC  
NC  
D3  
NC  
Q15  
NC  
NC  
Q1  
M
N
P
R
NC  
NC  
D17  
NC  
VSS  
VSS  
NC  
D0  
NC  
SA  
SA  
QVLD  
ODT  
SA  
SA  
TDO  
TCK  
SA  
SA  
SA  
SA  
TMS  
Notes: 1.  
2.  
Address expansion order for future higher density SRAMs: 10A → 2A → 7A → 5B.  
NC pins can be left floating or connected to 0V to VDDQ  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 5 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Pin Descriptions  
Name I/O type  
Descriptions  
Note  
SA  
Input  
Input  
Input  
Input  
Synchronous address inputs: These inputs are registered and must meet the setup  
and hold times around the rising edge of K (read address) and /K (write address).  
These inputs are ignored when device is deselected.  
/R  
Synchronous read: When low, this input causes the address inputs to be registered  
and a READ cycle to be initiated. This input must meet setup and hold times around  
the rising edge of K.  
/W  
Synchronous write: When low, this input causes the address inputs to be registered  
and a WRITE cycle to be initiated. This input must meet setup and hold times around  
the rising edge of K.  
/BWx  
Synchronous byte writes: When low, these inputs cause their respective byte to be  
registered and written during WRITE cycles. These signals are sampled on the same  
edge as the corresponding data and must meet setup and hold times around the  
rising edges of K and /K for each of the two rising edges comprising the WRITE cycle.  
See Byte Write Truth Table for signal to data relationship.  
K, /K  
Input  
Input clock: This input clock pair registers address and control inputs on the rising  
edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is  
ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and  
hold times around the clock rising edges. These balls cannot remain VREF level.  
/DOFF  
Input  
Input  
PLL disable: When low, this input causes the PLL to be bypassed for stable, low  
frequency operation.  
TMS  
TDI  
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left unconnected if the  
JTAG function is not used in the circuit.  
TCK  
Input  
Input  
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG  
function is not used in the circuit.  
ZQ  
Output impedance matching input: This input is used to tune the device outputs to  
the system data bus impedance. Q and CQ output impedance are set to 0.2 × RQ,  
where RQ is a resistor from this ball to ground. This ball can be connected directly to  
VDDQ, which enables the minimum impedance mode. This ball cannot be connected  
directly to VSS or left unconnected.  
The ODT termination values tracks the value of RQ. The ODT range is selected by  
ODT control input.  
ODT  
Input  
ODT control: When low;  
Low range mode is selected. The impedance range is between 52 Ω and 105 Ω  
(Thevenin equivalent), which follows 0.3 × RQ for 175 Ω ≤ RQ ≤ 350 Ω.  
ODT control:When high;  
High range mode is selected. The impedance range is between 105 Ω and 150 Ω  
(Thevenin equivalent), which follows 0.6 × RQ for 175 Ω ≤ RQ ≤ 250 Ω.  
ODT control:When floating;  
High range mode is selected.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 6 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Name  
I/O type  
Input  
Descriptions  
Note  
D0 to Dn  
Synchronous data inputs: Input data must meet setup and hold times around the  
rising edges of K and /K during WRITE operations. See Pin Arrangement figures  
for ball site location of individual signals.  
The ×18 device uses D0 to D17. D18 to D35 should be treated as NC pin.  
The ×36 device uses D0 to D35.  
CQ, /CQ  
Output  
Synchronous echo clock outputs: The edges of these outputs are tightly matched  
to the synchronous data outputs and can be used as a data valid indication.  
These signals run freely and do not stop when Q tri-states.  
TDO  
Output  
Output  
IEEE 1149.1 test output: 1.8 V I/O level.  
Q0 to Qn  
Synchronous data outputs: Output data is synchronized to the K clock. This bus  
operates in response to /R commands. See Pin Arrangement figures for ball site  
location of individual signals.  
The ×18 device uses Q0 to Q17. Q18 to Q35 should be treated as NC pin.  
The ×36 device uses Q0 to Q35.  
QVLD  
VDD  
Output  
Supply  
Supply  
Valid output indicator: The Q Valid indicates valid output data. QVLD is edge  
aligned with CQ and /CQ.  
Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions  
for range.  
1
1
1
VDDQ  
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC  
Characteristics and Operating Conditions for range.  
VSS  
Supply  
-
Power supply: Ground.  
VREF  
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve  
system noise margin. Provides a reference voltage for the HSTL input buffers.  
NC  
-
No connect: These pins can be left floating or connected to 0V to VDDQ.  
Notes:  
1. All power supply and ground balls must be connected for proper operation of the device.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 7 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Block Diagram  
[R1QPA4436RBG]  
21  
Address  
Address  
/R  
21  
Registry  
/W  
and  
Logic  
K
/K  
ZQ  
/W  
72  
72  
Q
(Data out)  
36  
4
/BWx  
72  
Memory  
Array  
Data  
36  
Registry  
and  
D
2
(Data in)  
Logic  
CQ  
/R  
/CQ  
K
/K  
K
K
K,/K  
[R1QPA4418RBG]  
22  
Address  
Address  
/R  
/W  
K
22  
Registry  
and  
Logic  
ZQ  
/K  
/W  
36  
36  
Q
(Data out)  
18  
2
/BWx  
/36  
Memory  
Array  
Data  
Registry  
and  
18  
D
2
(Data in)  
Logic  
CQ  
/R  
/CQ  
K
/K  
K
K
K,/K  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 8 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Power-up and Initialization Sequence  
VDD must be stable before K, /K clocks are applied.  
- Recommended voltage application sequence : VSS → VDD → VDDQ & VREF → VIN. (0 V to VDD, VDDQ < 200 ms)  
- Apply VREF after VDDQ or at the same time as VDDQ  
.
- Then execute either one of the following sequences.  
1. Single Clock Mode  
- Drive /DOFF high (/DOFF can be tied high from the start).  
- Then provide stable clocks (K, /K) for at least 20 us.  
Power Up &  
NOP &  
Normal  
Status  
Unstable Stage  
Set-up Stage  
Operation  
VDD  
VDDQ  
VREF  
Fix High (=Vddq)  
SET-UP Cycle  
/DOFF  
K, /K  
2. PLL Off Mode (/DOFF tied low)  
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us.  
PLL Constraints  
1. These chips use the PLL. The clock input should have low phase jitter which is specified as tKC var.  
2. The lower end of the frequency at which the PLL can operate is 250 MHz.  
(Please refer to AC Characteristics table for detail.)  
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 9 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Programmable Output Impedance  
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).  
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance  
matching with a tolerance of 15% is between 175 Ω and 350 Ω. The total external capacitance of ZQ ball must be  
less than 7.5 pF.  
QVLD (Valid data indicator)  
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q Valid  
indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for  
capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop capturing the data.  
QVLD is edge aligned with CQ and /CQ.  
ODT (On Die Termination)  
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated, especially  
at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of devices.  
2. The ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input.  
3. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without ODT.  
4. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current  
consumption from the I/O voltage supply) with ODT.  
ODT range  
ODT control pin  
Low  
Thevenin equivalent resistance (RTHEV  
)
Unit  
Ω±  
Notes  
0.3 x RQ  
0.6 x RQ  
0.6 x RQ  
1,3  
2
High  
Ω±  
Floating  
Ω±  
2
Notes:  
1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of ± 20 % is 175 Ω ≤ RQ ≤ 350  
Ω.  
2. Allowable range of RQ to guarantee impedance matching a tolerance of ± 20 % is 175 Ω ≤ RQ ≤ 250 Ω.  
3. ODT control pin is connected to VDDQ through 3.5 kΩ. Therefore it is recommended to connect it to  
VSS through less than 100 Ω to make it low.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 10 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Thevenin termination  
Other LSI  
SRAM with ODT  
VDDQ  
ZQ  
2 × RTHEV  
RQ  
Input  
Buffer  
Output  
Buffer  
2 × RTHEV  
VSS  
VSS  
ODT pin  
Pin name  
ODT On/Off  
Always On  
Always On  
Always On  
D0 to Dn  
/BWx  
K, /K  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 11 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
K Truth Table  
Operation  
K
/R  
/W  
D or Q  
Data in  
Input  
data  
Write Cycle:  
D(A+0)  
D(A+1)  
Load address, input write data on  
two consecutive  
↑
×
L
Input  
clock  
K and /K rising edges  
K(t) ↑  
K(t) ↑  
Data out  
Output  
data  
Read Cycle:  
Q(A+0)  
Q(A+1)  
Load address, output read data on  
consecutive  
↑
L
×
Input  
K and /K rising edges  
/C(t+2) ↑  
/C(t+2) ↑  
clock  
NOP (No operation)  
↑
H
x
H
x
D = x or Q = High-Z  
Previous state  
Standby (Clock stopped)  
Stopped  
Notes:  
1. H: high level, L: low level, ×: don’t care, ↑: rising edge.  
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at K clock edges.  
3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are registered at the  
rising edge of K.  
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.  
5. Refer to state diagram and timing diagrams for clarification.  
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, or the  
case of K = high, /K = low. This condition is not essential, but permits most rapid restart by overcoming  
transmission line charging symmetrically.  
7. If this signal was low to initiate the previous cycle, this signal becomes a “don’t care” for this operation;  
however, it is strongly recommended that this signal be brought high, as shown in the truth table.  
8. This signal was high on previous K clock rising edge. Initiating consecutive READ or WRITE operations  
on consecutive K clock rising edges is not permitted. The device will ignore the second request.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 12 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Byte Write Truth Table ( x 36 )  
Operation  
K
↑
-
/K  
-
/BW0  
L
/BW1  
L
/BW2  
L
/BW3  
L
Write D0 to D35  
↑
-
L
L
L
L
Write D0 to D8  
Write D9 to D17  
Write D18 to D26  
Write D27 to D35  
Write nothing  
Notes:  
↑
-
L
H
H
H
↑
-
L
H
H
H
↑
-
H
L
H
H
↑
-
H
L
H
H
↑
-
H
H
L
H
↑
-
H
H
L
H
↑
-
H
H
H
L
↑
-
H
H
H
L
↑
-
H
H
H
H
↑
H
H
H
H
1. H: high level, L: low level, ↑: rising edge.  
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation  
provided that the setup and hold requirements are satisfied.  
Byte Write Truth Table ( x 18 )  
Operation  
K
↑
-
/K  
-
/BW0  
/BW1  
Write D0 to D17  
L
L
L
L
↑
-
Write D0 to D8  
Write D9 to D17  
Write nothing  
Notes:  
↑
-
L
H
H
L
↑
-
L
↑
-
H
H
H
H
↑
-
L
↑
-
H
H
↑
1. H: high level, L: low level, ↑: rising edge.  
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation  
provided that the setup and hold requirements are satisfied.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 13 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Bus Cycle State Diagram  
/R = H  
/R = H  
Always  
/R = L  
/R = L  
Read Port NOP  
Load New  
Read Double  
R
Init = 0  
Read Address  
Supply voltage  
provided  
Power Up  
Supply voltage  
provided  
Always  
/W = L  
Load New  
Write Address  
at /K↑  
Write Double  
at /K↑  
Write Port NOP  
/W = L  
/W = H  
/W = H  
Notes:  
1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is  
always fixed as: xxx…xxx+0, xxx…xxx+1.  
Bus cycle is terminated at the end of this sequence (burst count = 2).  
2. Read and write state machines can be active simultaneously.  
3. State machine control timing sequence is controlled by K.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 14 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Electrical Characteristics  
Absolute Maximum Ratings  
Parameter  
Symbol  
Rating  
Unit  
Notes  
−0.5 to VDD + 0.5  
(2.5 V max.)  
Input voltage on any ball  
VIN  
V
1,4  
−0.5 to VDDQ+ 0.5  
Input/output voltage  
VI/O  
V
1,4  
(2.5 V max.)  
Core supply voltage  
Output supply voltage  
Junction temperature  
Storage temperature  
Notes:  
VDD  
VDDQ  
Tj  
−0.5 to 2.5  
−0.5 to VDD  
+125 (max)  
−55 to +125  
V
V
1,4  
1,4  
5
°C  
°C  
TSTG  
1. All voltage is referenced to VSS.  
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation  
should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended  
periods of time could affect device reliability.  
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables  
after thermal equilibrium has been established.  
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.  
Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.5 V, whatever the  
instantaneous value of VDDQ  
.
5. Some method of cooling or airflow should be considered in the system.  
Recommended DC Operating Conditions  
Parameter  
Symbol  
VDD  
Min  
1.7  
Typ  
1.8  
1.5  
0.75  
-
Max  
1.9  
Unit  
V
Notes  
1
Power supply voltage -- core  
Power supply voltage -- I/O  
Input reference voltage -- I/O  
Input high voltage  
VDDQ  
1.4  
VDD  
V
1,2  
VREF  
0.68  
0.95  
V
3
VIH (DC)  
VIL (DC)  
VREF + 0.1  
-0.3  
VDDQ + 0.3  
VREF - 0.1  
V
1,4,5  
1,4,5  
Input low voltage  
-
V
Notes:  
1.  
At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within 200ms. During this  
time, VDDQ < VDD and VIH < VDDQ. During normal operation, VDDQ must not exceed VDD  
.
2.  
3.  
4.  
5.  
Please pay attention to Tj not to exceed the temperature shown in the absolute maximum ratings table due to current from VDDQ  
.
Peak to peak AC component superimposed on VREF may not exceed 5% of VREF  
.
These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing parameters.  
Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2  
Undershoot: VIL (AC) ≥±−0.5 V for t ≤ tKHKH/  
2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 15 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
DC Characteristics  
(TA = -40 to +85°C, VDD = 1.8V ± 0.1V, VDDQ = 1.5V, VREF = 0.75V)  
Parameter  
Symbol  
Test condition  
MIN.  
MAX.  
Unit Notes  
-30  
1230  
980  
-33  
1150  
920  
Operating Supply  
Current  
(x36)  
mA  
mA  
IDD  
(x18)  
1,2,3  
2,4,5  
(Write / Read)  
Standby Supply  
Current  
(x36)  
(x18)  
ISB1  
920  
800  
870  
750  
(NOP)  
Input leakage current  
Output leakage current  
Output high voltage  
μA  
μA  
V
ILI  
9
-2  
-5  
2
5
ILO  
10  
VOH  
(Low)  
|IOH| ≤ 0.1 mA  
VDDQ − 0.2  
8
8
8
8
VDDQ  
Note 6  
IOL ≤ 0.1 mA  
Note 7  
V
V
VOH  
V
DDQ/2 − 0.12  
VDDQ/2 + 0.12  
0.2  
Output low voltage  
VOL  
(Low)  
VSS  
V
VOL  
VDDQ/2− 0.12  
VDDQ/2+ 0.12  
Notes:  
1. All inputs (except ZQ, VREF) are held at either VIH or VIL.  
2. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.  
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of  
device with 100% write and 100% read cycle.  
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.  
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and  
WRITE cycles are completed. )  
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175±Ω±≤ RQ ≤ 350 Ω.  
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 Ω±≤ RQ ≤ 350±Ω.  
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.  
9. 0 ≤ VIN ≤±VDDQ for all input balls (except VREF, Dn, /BWx, K, /K, ZQ, ODT, TCK, TMS, TDI ball).  
10. 0 ≤ VOUT ≤ VDDQ (except TDO ball), output disabled.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 16 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Thermal Resistance  
Datasheet  
Parameter  
Junction to Ambient  
Junction to Case  
Symbol  
θJA  
Airflow  
1 m/s  
-
Typ  
9.7  
Unit  
Test condition  
Notes  
°C/W  
EIA/JEDEC JESD51  
1
θJC  
4.4  
Notes:  
1. These parameters are calculated under the condition. These are reference values.  
2. Tj = Ta + θJA × Pd  
Tj = Tc + θJC × Pd  
where  
Tj : junction temperature when the device has achieved a steady-state after application of Pd (°C)  
Ta :ambient temperature (°C)  
Tc :temperature of external surface of the package or case (°C)  
θJA  
:
thermal resistance from junction-to-ambient (°C/W)  
θJC :  
thermal resistance from junction-to-case (package) (°C/W)  
Pd :power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)  
Capacitance  
(TA = +25°C, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V)  
Parameter  
Symbol  
CIN  
Min  
Typ  
Max  
Unit  
pF  
Test condition  
VIN = 0 V  
Note  
1,2  
Input capacitance (SA, /R, /W, /BW)  
Clock input capacitance (K, /K)  
Output capacitance (DQ, CQ, /CQ)  
-
-
-
4
4
5
5
5
6
CCLK  
pF  
VCLK = 0 V  
1,2  
CI/O  
pF  
VI/O = 0 V  
1,2  
Notes:  
1. These parameters are sampled and not 100% tested.  
2. Except JTAG (TCK, TMS, TDI, TDO) pins.  
AC Test Conditions  
Input waveform (Rise/fall time ≤ 0.3 ns)  
1.25V  
0.75V  
Test points  
0.75V  
0.25V  
Output waveform  
VDDQ/2  
Test points  
V DDQ/2  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 17 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Output load conditions  
V
DDQ / 2  
1.8V 0.1V  
1.5V  
= 0.75V  
VDDQ / 2  
= 0.75V  
50Ω  
Z0 = 50Ω  
250Ω  
AC Operating Conditions  
Parameter  
Symbol  
VIH (AC)  
VIL (AC)  
Min  
Typ  
Max  
-
Unit  
V
Notes  
1,2,3,4  
1,2,3,4  
Input high voltage  
Input low voltage  
VREF + 0.2  
-
-
-
VREF – 0.2  
V
Notes:  
1. All voltages referenced to VSS (GND). During normal operation, VDDQ must not exceed VDD  
2. These conditions are for AC functions only, not for AC parameter test.  
3. Overshoot: VIH (AC) ≤ VDDQ + 0.5 V for t ≤ tKHKH/2  
.
Undershoot: VIL (AC) ≥ −0.5 V for t ≤ tKHKH/2  
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH  
(min).  
4. To maintain a valid level, the transitioning edge of the input must:  
a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC)  
b. Reach at least the target AC level.  
.
c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)  
.
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 18 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
AC Characteristics  
(TA = -40 to +85°C, VDD = 1.8V ± 0.1V, VDDQ = 1.5V, VREF = 0.75V)  
Parameter  
Symbol  
-30  
-33  
Unit  
Notes  
Min  
Max  
Min  
Max  
Clock  
Average clock cycle time(K, /K)  
Clock high time (K, /K)  
tKHKH  
tKHKL  
3.00  
0.40  
4.00  
-
3.30  
0.40  
4.00  
-
ns  
Cycle  
Clock low time (K, /K)  
Clock to /clock (K to /K)  
/Clock to clock (/K to K)  
tKLKH  
tKH/KH  
t/KHKH  
0.40  
0.45  
0.45  
-
-
-
0.40  
0.45  
0.45  
-
-
-
Cycle  
Cycle  
Cycle  
PLL Timing  
Clock phase jitter (K, /K)  
tKC var  
tKC lock  
tKC reset  
-
0.20  
-
0.20  
ns  
us  
ns  
3
2
5
Lock time (K)  
20  
30  
-
-
20  
30  
-
-
K static to PLL reset  
Output Times  
K, /K high to output valid  
tCHQV  
tCHQX  
-
0.45  
-
-
0.45  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
K, /K high to output hold  
K, /K high to echo clock valid  
K, /K high to echo clock hold  
CQ, /CQ high to output valid  
CQ, /CQ high to output hold  
K, /K high to output high-Z  
K, /K high to output low-Z  
CQ high to QVLD valid  
-0.45  
-
-0.45  
-
tCHCQV  
tCHCQX  
tCQHQV  
tCQHQX  
tCHQZ  
0.45  
0.45  
-0.45  
-
-0.45  
-
0.20  
-
0.20  
-
5
5
4
4
5
-0.20  
-
-0.20  
-
0.45  
-
0.45  
-
tCHQX1  
tQVLD  
-0.45  
-0.20  
-0.45  
-0.20  
0.20  
0.20  
Setup Times  
Address valid to K rising edge  
tAVKH  
tIVKH  
0.28  
0.28  
0.28  
-
-
-
0.30  
0.30  
0.30  
-
-
-
ns  
ns  
ns  
1
1
1
Control inputs valid to K rising edge  
Data-in valid to K, /K rising edge  
tDVKH  
Hold Times  
K rising edge to address hold  
tKHAX  
tKHIX  
0.28  
0.28  
0.28  
-
-
-
0.30  
0.30  
0.30  
-
-
-
ns  
ns  
ns  
1
1
1
K rising edge to control inputs hold  
K, /K rising edge to data-in hold  
tDVKH  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 19 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Notes:  
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold  
times for all latching clock edges.  
2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for PLL lock retention. PLL lock time  
begins once VDD , VDDQ and input clock are stable.  
It is recommended that the device is kept inactive during these cycles.  
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.  
4. Transitions are measured ± 100 mV from steady-state voltage.  
5. These parameters are sampled.  
Remarks:  
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted.  
2. Control input signals may not be operated with pulse widths less than tKHKL (min).  
3. VDDQ is +1.5 V DC. VREF is +0.75 V DC.  
4. Control signals are /R and /W.  
Setup and hold times of /BWx signals must be the same as those of Data-in signals.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 20 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Read and Write Timing  
1
NOP  
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
NOP  
NOP  
NOP  
READ  
READ  
WRITE  
READ  
WRITE  
READ  
WRITE  
NOP  
WRITE  
NOP  
NOP  
WRITE  
K
/K  
tKHKL  
tKH/KH  
tKHKH  
tKLKH  
t/KHKH  
/R  
t
IVKH  
t
KHIX  
KHIX  
/W  
t
IVKH  
t
A0  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
Address  
Data in  
tAVKH  
t
KHAX  
D10 D11 D30 D31 D50 D51 D70 D71 D80 D81  
tDVKH  
tDVKH  
tKHDX  
tKHDX  
Q00 Q01 Q20 Q21 Q40 Q41 Q60 Q61  
Data out  
CQ  
t
CHQZ  
-tCHQX1  
t
CHQV  
t
CHQV  
t
CQHQV  
-tCHQX  
-tCHQX  
-tCQHQX  
t
CHCQV  
-tCHCQX  
/CQ  
t
CHCQV  
-tCHCQX  
QVLD  
t
QVLD  
t
QVLD  
-tQVLD  
-tQVLD  
Notes:  
1. Q00 refers to output from address A0+0. Q01 refers to output from the next internal burst address following  
A0, i.e., A0+1.  
2. In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11. Write data is forwarded immediately  
as read results.  
3. To control read and write operations, /BW signals must operate at the same timing as Data-in signals.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 21 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
JTAG Specification  
These products support a limited set of JTAG functions as in IEEE standard 1149.1.  
Disabling the Test Access Port  
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with  
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.  
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up resistor.  
TDO should be left unconnected.  
Test Access Port (TAP) Pins  
Symbol I/O Pin assignments  
Description  
Notes  
Test clock input. All inputs are captured on the rising edge of TCK  
and all outputs propagate from the falling edge of TCK.  
TCK  
TMS  
2R  
Test mode select. This is the command input for the TAP controller  
state machine.  
10R  
Test data input. This is the input side of the serial registers placed  
between TDI and TDO. The register placed between TDI and TDO is  
determined by the state of the TAP controller state machine and the  
instruction that is currently loaded in the TAP instruction.  
TDI  
11R  
1R  
Test data output. Output changes in response to the falling edge of  
TCK. This is the output side of the serial registers placed between  
TDI and TDO.  
TDO  
Notes:  
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for  
five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP.  
TAP DC Operating Characteristics  
( TA = -40 to +85°C, VDD = 1.8V ± 0.1V )  
Parameter  
Symbol  
Min  
Typ  
Max  
Unit  
Notes  
Input high voltage  
Input low voltage  
Input leakage current  
VIH  
VIL  
ILI  
+1.3  
-0.3  
-5.0  
-
-
-
VDD + 0.3  
+0.5  
V
V
μA  
+5.0  
0 V ≤ VIN ≤ VDD  
0 V ≤ VIN ≤ VDD,  
output disabled  
IOLC = 100 μA  
IOLT = 2 mA  
|IOHC| = 100 μA  
|IOHT| = 2 mA  
Output leakage current  
ILO  
-5.0  
-
+5.0  
μA  
VOL1  
VOL2  
VOH1  
VOH2  
-
-
-
-
-
0.2  
0.4  
-
V
V
V
V
Output low voltage  
-
1.6  
1.4  
Output high voltage  
-
Notes:  
1. All voltages referenced to VSS (GND).  
2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or VDDQ(min.) within  
200ms. During this time, VDDQ < VDD and VIH < VDDQ  
.
During normal operation, VDDQ must not exceed VDD  
.
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 22 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
TAP AC Test Conditions  
Parameter  
Input timing measurement reference levels  
Input pulse levels  
Symbol  
VREF  
Conditions  
0.9  
Unit Notes  
V
V
VIL, VIH  
tr, tf  
0 to 1.8  
Input rise/fall time  
ns  
≤ 1.0  
0.9  
Output timing measurement reference levels  
Test load termination supply voltage (VTT)  
Output load  
V
V
0.9  
See figures  
Input waveform  
1.8V  
0.9V  
0V  
Test points  
0.9V  
Output waveform  
0.9V  
Test points  
0.9V  
Output load condition  
VTT = 0.9V  
DUT  
TDO  
50Ω  
Z0 = 50ΩΩ  
20pF  
External Load at Test  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 23 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Notes  
TAP AC Operating Characteristics  
( TA = -40 to +85°C, VDD = 1.8V ± 0.1V )  
Parameter  
Test clock (TCK) cycle time  
TCK high pulse width  
TCK low pulse width  
Test mode select (TMS) setup  
TMS hold  
Symbol  
Min  
50  
20  
20  
5
Typ  
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tTHTH  
tTHTL  
tTLTH  
tMVTH  
tTHMX  
tCS  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
-
Capture setup  
5
-
Capture hold  
tCH  
5
-
TDI valid to TCK high  
TCK high to TDI invalid  
TCK low to TDO unknown  
TCK low to TDO valid  
tDVTH  
tTHDX  
tTLQX  
tTLQV  
5
-
5
-
0
-
-
10  
Notes:  
1.  
tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 24 of 30  
R1QPA4436RBG,R1QPA4418RBG  
TAP Controller Timing Diagram  
Datasheet  
THTH  
THTL  
TLTH  
t
t
t
TCK  
TMS  
TDI  
MVTH  
t
t
THMX  
DVTH  
t
THDX  
t
t
TLQV  
TDO  
t
CS  
t
CH  
t
TLQX  
PI  
(SRAM)  
Test Access Port Registers  
Register name  
Instruction register  
Bypass register  
Length  
3 bits  
Symbol  
Notes  
IR [2:0]  
BP  
1 bits  
ID register  
32 bits  
109 bit  
ID [31:0]  
BS [109:1]  
Boundary scan register  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 25 of 30  
R1QPA4436RBG,R1QPA4418RBG  
TAP Controller Instruction Set  
Datasheet  
IR2 IR1 IR0 Instruction  
Description  
Notes  
The EXTEST instruction allows circuitry external to the component  
package to be tested. Boundary scan register cells at output balls  
are used to apply test vectors, while those at input balls capture test  
results. Typically, the first test vector to be applied using the  
EXTEST instruction will be shifted into the boundary scan register  
using the PRELOAD instruction. Thus, during the Update-IR state  
of EXTEST, the output driver is turned on and the PRELOAD data is  
driven onto the output balls.  
The IDCODE instruction causes the ID ROM to be loaded into the  
ID register when the controller is in capture-DR mode and places  
the ID register between the TDI and TDO balls in shift-DR mode.  
The IDCODE instruction is the default instruction loaded in at power  
up and any time the controller is placed in the Test-Logic-Reset  
state.  
0
0
0
0
0
1
EXTEST  
IDCODE  
1,2,3,4,5  
If the SAMPLE-Z instruction is loaded in the instruction register, all  
RAM outputs are forced to an inactive drive state (high-Z), moving  
the TAP controller into the capture-DR state loads the data in the  
RAMs input into the boundary scan register, and the boundary scan  
register is connected between TDI and TDO when the TAP  
controller is moved to the shift-DR state.  
0
0
1
1
0
1
SAMPLE-Z  
RESERVED  
3,4,5  
The RESERVED instruction is not implemented but is reserved for  
future use. Do not use this instruction.  
When the SAMPLE instruction is loaded in the instruction register,  
moving the TAP controller into the capture-DR state loads the data  
in the RAMs input and I/O buffers into the boundary scan register.  
Because the RAM clock(s) are independent from the TAP clock  
(TCK) it is possible for the TAP to attempt to capture the I/O ring  
SAMPLE  
1
0
0
3,4,5  
(/PRELOAD) contents while the input buffers are in transition (i.e., in a metastable  
state). Although allowing the TAP to SAMPLE metastable input will  
not harm the device, repeatable results cannot be expected.  
Moving the controller to shift-DR state then places the boundary  
scan register between the TDI and TDO balls.  
The RESERVED instruction is not implemented but is reserved for  
future use. Do not use this instruction.  
The RESERVED instruction is not implemented but is reserved for  
future use. Do not use this instruction.  
1
1
0
1
1
0
RESERVED  
RESERVED  
The BYPASS instruction is loaded in the instruction register when  
the bypass register is placed between TDI and TDO. This occurs  
1
1
1
BYPASS  
when the TAP controller is moved to the shift-DR state. This allows  
the board level scan path to be shortened to facilitate testing of  
other devices in the scan path.  
Notes:  
1. Data in output register is not guaranteed if EXTEST instruction is loaded.  
2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.  
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus  
hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except  
capturing the I/O ring contents into the boundary scan register.  
4. Clock recovery initialization cycles are required after boundary scan.  
5. ODT is disabled in EXTEST, SAMPLE-Z or SAMPLE mode.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 26 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Boundary Scan Order  
Signal names  
Ball  
Signal names  
Signal names  
Ball  
ID  
Ball  
ID  
Bit#  
ID  
Bit#  
Bit#  
x18  
x36  
x18  
x36  
x18  
x36  
1
2
3
4
5
6
7
8
6R  
6P  
6N  
7P  
7N  
7R  
8R  
8P  
9R  
11P  
10P  
10N  
9P  
10M  
11N  
9M  
ODT  
QVLD  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
Q0  
D0  
NC  
NC  
Q1  
D1  
NC  
NC  
Q2  
D2  
NC  
NC  
Q3  
D3  
NC  
NC  
Q4  
D4  
ZQ  
NC  
NC  
Q5  
D5  
NC  
NC  
Q6  
D6  
ODT  
QVLD  
SA  
SA  
SA  
SA  
SA  
SA  
SA  
Q0  
D0  
D9  
Q9  
Q1  
D1  
D10  
Q10  
Q2  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
9E  
10C  
11D  
9C  
9D  
11B  
11C  
9B  
10B  
11A  
10A  
9A  
NC  
Q7  
D7  
NC  
NC  
Q8  
D8  
NC  
NC  
CQ  
SA  
SA  
SA  
SA  
SA  
/R  
Q15  
Q7  
D7  
D16  
Q16  
Q8  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
2D  
2E  
1E  
2F  
3F  
1G  
1F  
3G  
2G  
1H  
1J  
D11  
NC  
NC  
Q12  
D12  
NC  
D20  
D29  
Q29  
Q21  
D21  
D30  
Q30  
Q22  
D22  
/DOFF  
D31  
Q31  
Q23  
D23  
D32  
Q32  
Q24  
D24  
D33  
Q33  
Q25  
D25  
D34  
Q34  
Q26  
D26  
D35  
Q35  
SA  
D8  
NC  
D17  
Q17  
CQ  
SA  
SA  
SA  
SA  
SA  
/R  
Q13  
D13  
/DOFF  
NC  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
2J  
3K  
3J  
NC  
8B  
Q14  
D14  
NC  
7C  
6C  
8A  
7A  
7B  
6B  
6A  
5B  
5A  
4A  
5C  
4B  
3A  
2A  
1A  
2B  
3B  
1C  
1B  
2K  
1K  
2L  
3L  
1M  
1L  
3N  
3M  
1N  
2M  
3P  
2N  
2P  
1P  
3R  
4R  
4P  
5P  
5N  
5R  
-
NC  
9N  
NC  
/BW0  
K
/BW1  
/BW0  
K
Q15  
D15  
NC  
11L  
11M  
9L  
10L  
11K  
10K  
9J  
D2  
D11  
Q11  
Q3  
/K  
/K  
NC  
NC  
/BW1  
/W  
SA  
SA  
SA  
SA  
/CQ  
Q9  
D9  
NC  
NC  
Q10  
D10  
NC  
NC  
Q11  
/BW3  
/BW2  
/W  
SA  
SA  
Q16  
D16  
NC  
D3  
D12  
Q12  
Q4  
D4  
ZQ  
D13  
Q13  
Q5  
NC  
9K  
Q17  
D17  
NC  
NC  
SA  
SA  
SA  
SA  
SA  
10J  
11J  
11H  
10G  
9G  
11F  
11G  
9F  
10F  
11E  
10E  
10D  
SA  
NC  
/CQ  
Q18  
D18  
D27  
Q27  
Q19  
D19  
D28  
Q28  
Q20  
SA  
SA  
SA  
SA  
D5  
D14  
Q14  
Q6  
D6  
D15  
3D  
3C  
1D  
2C  
3E  
SA  
SA  
Internal Internal  
NC  
Notes:  
In boundary scan mode,  
1. Clock balls (K, /K) are referenced to each other and must be at opposite logic levels for reliable operation.  
2. CQ and /CQ data are synchronized to the K clock (except EXTEST, SAMPLE-Z).  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 27 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
ID Register  
Revision  
number  
(31:29)  
Start bit(0)→  
￢
↓
Type number  
(28:12)  
Vendor JEDEC code  
(11:1)  
#
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
1
1
1
0
1
Symbol  
R
R
R
0
C
M
M
M
A
W
W
0
1
Q
Q
Q
B
O
S
0
0
1
R
0
0
0
0
R
0
0
1
1
:
R
0
1
0
1
Q
0
Revision0  
Revision1  
Revision2  
Revision3  
:
II(QDR-II,DDR-II)  
II+(QDR-II+,DDR-II+)  
Q
1
0
1
DDR  
QDR  
C
Q
0
0
1
36M&72M w/o ODT,144M,288M  
36M&72M w/ ODT  
Latency = 1.5(@II).Latency = 2.0(@II+)  
Latency = 2.5(@II+)  
B
1
M
0
0
1
1
M
1
1
0
1
M
0
1
1
0
Density = 36Mb  
Density = 72Mb  
Density = 144Mb  
Density = 288Mb  
A
0
1
Burst Latency = 2 word burst  
Burst Latency = 4 word burst  
O
without ODT  
with ODT  
S
0
1
144M&288M w/o ODT,36M,72M  
144M&288M w/ ODT  
0
1
Common I/O  
0
1
Separate I/O  
W
0
W
0
x9  
1
0
x18  
x36  
1
1
TAP Controller State Diagram  
1
Test Logic Reset  
0
1
1
1
Select IR Scan  
Run Test/Idle  
Select DR Scan  
0
0
0
1
1
Capture DR  
Capture IR  
0
0
0
Shift IR  
1
0
Shift DR  
1
Exit1 DR  
0
1
1
0
Exit1 IR  
0
0
Pause DR  
1
Pause IR  
1
0
0
Exit2 DR  
1
Exit2 IR  
1
Update DR  
Update IR  
1
0
0
1
Notes:  
The value adjacent to each state transition in this figure represents the signal present at TMS at  
the time of a rising edge at TCK.  
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held  
high for at least five rising edges of TCK.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 28 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Package Dimensions and Marking Information  
Both Pb parts and Pb-free parts are available.  
JEITA Package Code  
P-LBGA165-15x17-1.00  
Renesas Code  
PLBG0165FD-Bꢀ  
Previous Code  
165FHE-B  
Mass (typ.)  
0.6 g  
D
B
A
Top View  
Index Mark  
Marking Information  
(Laser Mark)  
1st row : Vender name (RENESAS  
2nd row: Part number  
)
3rd row : Y  
WW  
: Year code  
: Week code  
E
XXXX : Renesas  
internal use  
4th row : Country name (JAPAN)  
This part  
number or  
mark is just  
one example.  
+ "None" --- Pb -free parts  
+ "PB-F" --- Pb-free parts  
S
Side View  
A
A1  
- y S  
Z
[e]  
D
Bottom View  
[e]  
Dimension in mm  
Reference  
Symbol  
Min Nom Max  
14.9 15.0 15.1  
16.9 17.0 17.1  
D
E
A
-
-
1.4  
0.31 0.36 0.41  
1.0  
0.45 0.5 0.6  
A1  
[e]  
b
Z
E
-
-
1
2
3
4
5
6
7
8
9
10 11  
x
y
-
-
-
-
-
0.2  
0.15  
-
Øb  
-
Øx(M) S AB  
2.5  
Z
D
E
Index Mark  
-
1.5  
-
Z
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 29 of 30  
R1QPA4436RBG,R1QPA4418RBG  
Datasheet  
Revision History  
R1QPA4436RBG,R1QPA4418RBG  
Description  
Summary  
Rev.  
Date  
Page  
-
Rev.1.00  
Rev.2.00  
’13.09.02  
’14.08.01  
New Datasheet.  
Modification : DC Characteristics ,Spec of IDD and ISB1.  
P15  
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, and Renesas Electronics Corporation.  
http://www.qdrconsortium.org/  
The information contained herein is subject to change without notice.  
R10DS0147EJ0200 Rev.2.00  
Aug 01, 2014  
Page 30 of 30  
Notice  
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for  
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the  
use of these circuits, software, or information.  
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics  
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.  
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or  
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or  
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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.  
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Refer to "http://www.renesas.com/" for the latest and detailed information.  
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© 2014 Renesas Electronics Corporation. All rights reserved.  
Colophon 4.0  

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SI9135_11

 SMBus Multi-Output Power-Supply Controller

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SI9136_11

 Multi-Output Power-Supply Controller

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SI9130CG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130LG-T1-E3

 Pin-Programmable Dual Controller - Portable PCs

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SI9130_11

 Pin-Programmable Dual Controller - Portable PCs

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SI9137

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137DB

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9137LG

 Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

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SI9122E

 500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

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