R1QPA4436RBG [RENESAS]
144-Mbit DDRII SRAM 2-word Burst; 144兆位的SRAM DDRII 2字突发
| 型号： | R1QPA4436RBG |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 144-Mbit DDRII SRAM 2-word Burst |
| 文件： | 总37页 (文件大小：503K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
R1QBA4436RBG / R1QBA4418RBG / R1QBA4409RBG
R1QEA4436RBG / R1QEA4418RBG / R1QEA4409RBG
R1QHA4436RBG / R1QHA4418RBG / R1QHA4409RBG
R1QLA4436RBG / R1QLA4418RBG / R1QLA4409RBG
R10DS0189EJ0011
Preliminary
Rev. 0.11b
2012.06.05
144-Mbit DDRII+ SRAM
2-word Burst
Description
The R1Q#A4436 is a 4,194,304-word by 36-bit and the R1Q#A4418 is a 8,388,608-word by 18-bit synchronous
double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor
memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are
controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products
are suitable for applications which require synchronous operation, high speed, low voltage, high density and
wide bit configuration. These products are packaged in 165-pin plastic FBGA package.
# = B: Latency =2.5, w/o ODT
# = E: Latency =2.5, w/ ODT
# = H: Latency =2.0, w/o ODT
# = L: Latency =2.0, w/ ODT
Features
႑ Power Supply
• 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ
႑ Clock
)
• Fast clock cycle time for high bandwidth
• Two input clocks (K and /K) for precise DDR timing at clock rising edges only
• Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
• Clock-stop capability with Ps restart
႑ I/O
• Common data input/output bus
• Pipelined double data rate operation
• HSTL I/O
• User programmable output impedance
• DLL/PLL circuitry for wide output data valid window and future frequency scaling
• Data valid pin (QVLD) to indicate valid data on the output
႑ Function
• Two-tick burst for low DDR transaction size
• Internally self-timed write control
• Simple control logic for easy depth expansion
• JTAG 1149.1 compatible test access port
႑ Package
• 165 FBGA package (15 x 17 x 1.4 mm)
Notes: 1. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, IDT, Samsung, and Renesas Electronics Corp. (QDR Co-Development Team)
2. The specifications of this device are subject to change without notice. Please contact your nearest
Renesas Electronics Sales Office regarding specifications.
3. Refer to
"http://www.renesas.com/products/memory/fast_sram/qdr_sram/index.jsp"
for the latest and detailed information.
4. Descriptions about x9 parts in this datasheet are just for reference.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Part Number Definition
Part Number Definition Table
Column No.
0 1 2 3 4 5 6 7 8 9 10 11 - 12 13 14 15 16
R 1 Q 2 A 4 4 1 8 R B G - 4 0 R B 0
The above part number is just example for 144M QDRII B2 x18 250MHz, 15x17mm PKG, Pb-free part.
Example
0Qꢀ
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%QOOGPVU
0Qꢀ
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8FFꢄꢆꢄꢃꢀꢇꢄ8
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Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
144M QDR/DDR SRAM Lineup
- Renesas plans to support the parts listed below.
Frequency (max)
(MHz)
Cycle Time (min)
(ns)
533 500 450 400 375 333 300 250 200
1.875 2.00 2.22 2.50 2.66 3.00 3.30 4.00 5.00
No
Status
Part Number
yy
-19
ă
-20
-22
-25
-27
-30
-33
-40
-40
-50
-50
Ą
2
3
x18 R1Q 2 A44 18 RBG-yy
x36 R1Q 2 A44 36 RBG-yy
x18 R1Q 3 A44 18 RBG-yy
x36 R1Q 3 A44 36 RBG-yy
x18 R1Q 4 A44 18 RBG-yy
x36 R1Q 4 A44 36 RBG-yy
x18 R1Q 5 A44 18RBG-yy
x36 R1Q 5 A44 36RBG-yy
x18 R1Q 6 A44 18RBG-yy
x36 R1Q 6 A44 36RBG-yy
x18 R1Q A A44 18RBG-yy
x36 R1Q A A44 36RBG-yy
x18 R1Q B A44 18RBG-yy
x36 R1Q B A44 36RBG-yy
x18 R1Q C A44 18RBG-yy
x36 R1Q C A44 36RBG-yy
x18 R1Q D A44 18RBG-yy
x36 R1Q D A44 36RBG-yy
x18 R1Q E A44 18RBG-yy
x36 R1Q E A44 36RBG-yy
x18 R1Q F A44 18RBG-yy
x36 R1Q F A44 36RBG-yy
x18 R1Q N A44 18RBG-yy
x36 R1Q N A44 36RBG-yy
x18 R1Q GA44 18RBG-yy
x36 R1Q GA44 36RBG-yy
x18 R1Q H A44 18RBG-yy
x36 R1Q H A44 36RBG-yy
x18 R1Q J A44 18RBG-yy
x36 R1Q J A44 36RBG-yy
x18 R1Q P A44 18RBG-yy
x36 R1Q P A44 36RBG-yy
x18 R1Q K A44 18RBG-yy
x36 R1Q K A44 36RBG-yy
x18 R1Q L A44 18RBG-yy
x36 R1Q L A44 36RBG-yy
x18 R1QM A44 18RBG-yy
x36 R1QM A44 36RBG-yy
B2
B4
B2
B4
B2
QDRII
DDRII
Under
Development
5
-33
-33
-33
-33
-40
-40
-40
-40
6
8
9
11
12
-
14 DDRII
15 SIO
20
QDRII+ B4
-19
-19
-19
-20
-20
-20
-22
-22
-22
Under
Development
21
23
24
26
27
32
33
35
36
38
39
41
42
44
45
47
48
50
51
53
54
56
57
59
60
62
63
B2
DDRII+
B4
-
QDRII+ B4
-19
-19
-19
-20
-20
-20
-22
-22
-22
Under
Development
B2
DDRII+
B4
-
B2
QDRII+
B4
-33
-33
Under
Development
-25
-25
-25
B2
DDRII+
B4
-
B2
QDRII+
B4
Under
Development
-25
-25
-25
B2
DDRII+
B4
-
: No Plan
-
Notes:
1. "yy" represents the speed bin. "R1QAA4436RBG-20" can operate at 500 MHz(max) of frequency, for example.
2. The part which is not listed above is not supported, as of the day when this datasheet was issued,
in spite of the existence of the part number or datasheet.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Pin Arrangement
R1Q4A4436 (Top) / R1QB(H)A4436 (Mid) / R1QE(L)A4436 (Bottom)
1
/CQ
NC
2
SA
3
SA
4
5
6
/K
K
7
8
/LD
SA
9
SA
NC
10
SA
NC
11
CQ
DQ8
A
B
R-/W /BW2
SA
/BW1
/BW0
DQ27 DQ18
NC DQ28 VSS
DQ29 DQ19 VSS
NC DQ20 VDDQ
/BW3
SA0
NC
SA
C
NC
SA
VSS
NC
DQ17 DQ7
NC DQ16
DQ15 DQ6
NC
NC
NC
D
E
F
G
H
J
K
L
M
N
NC
NC
NC
NC
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
DQ30 DQ21 VDDQ
DQ31 DQ22 VDDQ
DQ5
DQ14
ZQ
/DOFF VREF VDDQ VDDQ
VDDQ VDDQ VREF
NC
NC
NC
NC
NC
NC
NC
DQ32 VDDQ
DQ23 VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
DQ13 DQ4
DQ12 DQ3
NC
DQ11 DQ1
NC DQ10
DQ33 DQ24 VDDQ
NC DQ34 VSS
DQ35 DQ25 VSS
DQ2
VSS
C
QVLD
QVLD
P
R
NC
NC
DQ26
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
SA
DQ9 DQ0
TMS TDI
/C
NC
TDO TCK
ODT
(Top View)
Top
Mid
ĸR1Q4A4436
ĸR1QB(H)A4436
Bottom ĸR1QE(L)A4436
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ
.
R1Q4A4418 (Top) / R1QB(H)A4418 (Mid) / R1QE(L)A4418 (Bottom)
1
/CQ
NC
2
SA
DQ9
3
SA
NC
4
5
6
/K
K
7
SA
/BW0
8
/LD
SA
9
SA
NC
10
SA
NC
11
CQ
DQ8
A
B
R-/W /BW1
SA
NC
SA0
NC
SA
C
NC
NC
NC
VSS
SA
VSS
NC
DQ7
NC
NC
D
E
F
G
H
J
K
L
M
N
NC
NC
NC
NC
NC
NC
DQ12
NC
DQ10 VSS
DQ11 VDDQ
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
VDDQ
VDDQ
VDDQ
NC
VDDQ
DQ13 VDDQ
/DOFF VREF VDDQ VDDQ
VDDQ VDDQ VREF
NC
NC
NC
NC
NC
NC
NC
DQ15
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
DQ4
NC
NC
DQ1
NC
DQ14 VDDQ
NC
NC
VDDQ
VSS
NC
DQ16 VSS
VSS
NC
C
QVLD
QVLD
P
R
NC
NC
DQ17
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
SA
NC
DQ0
TDI
/C
NC
TDO TCK
TMS
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ
.
Rev. 0.11b : 2012.06.05
R10DS0189EJ0011
PAGE : ‹#›
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Pin Arrangement
Just Reference
R1Q4A4409 (Top) / R1QB(H)A4409 (Mid) / R1QE(L)A4409 (Bottom)
1
2
3
4
5
6
/K
K
7
SA
/BW
SA
8
/LD
SA
VSS
9
10
11
CQ
DQ4
NC
NC
DQ3
NC
NC
ZQ
NC
NC
DQ1
NC
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
/CQ
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
DQ5 VDDQ
NC VDDQ
DQ6 VDDQ
R-/W
SA
VSS
VSS
NC
NC
SA
SA
NC
NC
NC
NC
NC
NC
SA
NC
NC
NC
NC
NC
NC
SA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
VSS
VDDQ
VDDQ
VDDQ
/DOFF VREF VDDQ VDDQ
VDDQ VDDQ VREF
NC
NC
NC
NC
NC
NC
NC
DQ7
NC
NC
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
VDDQ
VSS
NC
NC
NC
NC
NC
DQ2
NC
NC
NC
NC
NC
VSS
VSS
C
QVLD
QVLD
P
R
NC
NC
DQ8
SA
SA
SA
SA
SA
SA
SA
SA
SA
NC
SA
NC
DQ0
TDI
/C
NC
TDO TCK
TMS
ODT
(Top View)
Notes: 1. Address expansion order for future higher density SRAMs: 10A ĺ 2A ĺ 7A ĺ 5B.
2. NC pins can be left floating or connected to 0V ᨺ VDDQ
.
3. Note that 6C is not SA0 and 7C is not SA1 in x9 product. Thus u9 product does not
permit random start address on the two least significant address bits. SA0, SA1 = 0
at the start of each address.
Rev. 0.11b : 2012.06.05
R10DS0189EJ0011
PAGE : ‹#›
hinS=00111.0011.0011.0011.0011
---00111.0011.0011.0011.0011---
00111.0011.0011.0011.0011---DDR
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Pin Descriptions
Name I/O type
Descriptions
Notes
Synchronous address inputs: These inputs are registered and must meet
the setup and hold times around the rising edge of K. All transactions
operate on a burst-of-four words (two clock periods of bus activity). SA0
SAx
Input and SA1 are used as the lowest two address bits for burst READ and
burst WRITE operations permitting a random burst start address on u18
and u36 of DDR II (not II+) devices. These inputs are ignored when
device is deselected or once burst operation is in progress.
Synchronous load: This input is brought low when a bus cycle sequence
is to be defined. This definition includes address and READ / WRITE
/LD
Input
direction. All transactions operate on a burst-of-four data (two clock
periods of bus activity).
Synchronous read / write Input: When /LD is low, this input designates
the access type (READ when R-/W is high, WRITE when R-/W is low) for
R-/W
Input
the loaded address. R-/W must meet the setup and hold times around
the rising edge of K.
Synchronous byte writes: When low, these inputs cause their respective
byte to be registered and written during WRITE cycles. These signals
are sampled on the same edge as the corresponding data and must meet
/BWx
K, /K
Input
setup and hold times around the rising edges of K and /K for each of the
two rising edges comprising the WRITE cycle. See Byte Write Truth
Table for signal to data relationship.
Input clock: This input clock pair registers address and control inputs on
the rising edge of K, and registers data on the rising edge of K and the
Input rising edge of /K. /K is ideally 180 degrees out of phase with K. All
synchronous inputs must meet setup and hold times around the clock
rising edges. These balls cannot remain VREF level.
Output clock: This clock pair provides a user-controlled means of tuning
device output data. The rising edge of /C is used as the output timing
reference for the first and third output data. The rising edge of C is used
as the output timing reference for second and fourth output data. Ideally,
Input /C is 180 degrees out of phase with C. C and /C may be tied high to
force the use of K and /K as the output reference clocks instead of having
to provide C and /C clocks. If tied high, C and /C must remain high and
not to be toggled during device operation. These balls cannot remain
VREF level.
C, /C
(II only)
1
DLL/PLL disable: When low, this input causes the DLL/PLL to be
bypassed for stable, low frequency operation.
/DOFF
Input
TMS
TDI
IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.
Input
IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if
the JTAG function is not used in the circuit.
TCK
Input
Notes:
1. R1Q2, R1Q3, R1Q4, R1Q5, R1Q6 series have C and /C pins. R1QA, R1QB, R1QC, R1QD,
R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM, R1QN, R1QP series do not have C,
/C pins. In the series, K and /K are used as the output reference clocks instead of C and /C.
Therefore, hereafter, C and /C represent K and /K in this document.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Name I/O type
Descriptions
Notes
Output impedance matching input: This input is used to tune the device
outputs to the system data bus impedance. DQ and CQ output
impedance are set to 0.2 u RQ, where RQ is a resistor from this ball to
ground. This ball can be connected directly to VDDQ, which enables the
ZQ
Input minimum impedance mode. This ball cannot be connected directly to
VSS or left unconnected.
In ODT (On Die Termination) enable devices, the ODT termination
values tracks the value of RQ. The ODT range is selected by ODT
control input.
ODT control: When low;
[Option 1] Low range mode is selected. The impedance range is
between 52 : and 105 : (Thevenin equivalent), which follows 0.3 u RQ
for 175 : RQ 350 :.
ODT
(II+ only)
[Option 2] ODT is disabled.
Input
1
When high; High range mode is selected. The impedance range is
between 105 : and 150 : (Thevenin equivalent), which follows 0.6 u RQ
for 175 : RQ 250 :.
When floating; [Option 1] High range mode is selected.
[Option 2] ODT is disabled.
Synchronous data I/Os: Input data must meet setup and hold times
around the rising edges of K and /K. Output data is synchronized to the
respective C and /C, or to the respective K and /K if C and /C are tied
Input high.
DQ0 to
DQn
The u9 device uses DQ0~DQ8.
/
output
DQ9~DQ35 should be treated as NC pin.
The u18 device uses DQ0~DQ17.
DQ18~DQ35 should be treated as NC pin.
The u36 device uses DQ0~DQ35.
Synchronous echo clock outputs: The edges of these outputs are tightly
matched to the synchronous data outputs and can be used as a data
valid indication. These signals run freely and do not stop when DQ tri-
states.
CQ, /CQ Output
TDO
QVLD
(II+ only)
Output IEEE 1149.1 test output: 1.8 V I/O level.
Valid output indicator: The Q Valid indicates valid output data. QVLD is
Output
edge aligned with CQ and /CQ.
Power supply: 1.8 V nominal. See DC Characteristics and Operating
Conditions for range.
VDD
Supply
2
Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC
VDDQ
VSS
Supply
2
2
Characteristics and Operating Conditions for range.
Supply Power supply: Ground.
HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to
VREF
improve system noise margin. Provides a reference voltage for the
HSTL input buffers.
NC
No connect: These pins can be left floating or connected to 0V ᨺ VDDQ.
Notes:
1. Renesas status: Option 1 = Available, Option 2 = Possible.
2. All power supply and ground balls must be connected for proper operation of the device.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Block Diagram (R1QxA4436 / R1QxA4418 series, x=4 )
SA0
SA0'
Burst
Logic
Output
Control
Logic
22/23
22/23
SA0''
SA0'''
SA
Address
Registry
and
ZQ
/LD
R-/W
K
CQ, /CQ
2
Logic
/K
72
/36
72
/36
72
/36
DQ
R-/W
/LD
36/18
Memory
Array
4/2
Data
Registry
and
/BWx
K
/K
Logic
36/18
C
C,/C
or
K
or
K
K,/K
Notes
1. C and /C pins do not exist in II+ series parts.
Block Diagram
(R1QxA4436 / R1QxA4418 / R1QyA4409 series, x=B,E,H,L, y=4,B,E,H,L)
21/22/23
SA
21/22/23
Address
Registry
and
ZQ
/LD
R-/W
K
CQ, /CQ
2
Logic
/K
72
/36
/18
72
/36
/18
72
/36
/18
DQ
R-/W
/LD
36/18/9
Memory
Array
4/2/1
Data
Registry
and
/BWx
K
/K
Logic
36/18/9
C
or
K
C,/C
or
K
K,/K
Notes
1. C and /C pins do not exist in II+ series parts.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---11111.1111.1111.1111.1111---
144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
General Description
Power-up and Initialization Sequence
- VDD must be stable before K, /K clocks are applied.
- Recommended voltage application sequence : VSS ĺ VDD ĺ VDDQ & VREF ĺ VIN. (0 V to VDD, VDDQ < 200 ms)
- Apply VREF after VDDQ or at the same time as VDDQ
.
- Then execute either one of the following three sequences.
1. Single Clock Mode (C and /C tied high)
- Drive /DOFF high (/DOFF can be tied high from the start).
- Then provide stable clocks (K, /K) for at least 20 us.
1. Single clock mode (C and /C pins fixed High)
Power Up &
NOP &
Normal
Status
Unstable Stage
Set-up Stage
Operation
VDD
VDDQ
VREF
Fix High (=Vddq)
SET-UP Cycle
/DOFF
K, /K
2. Double Clock Mode (C and /C control outputs) (II series only)
- Drive /DOFF high (/DOFF can be tied high from the start)
- Then provide stable clocks (K, /K , C, /C) for at least 20 us.
2. Double clock mode
Power Up &
NOP &
Normal
Status
Unstable Stage
Set-up Stage
Operation
VDD
VDDQ
VREF
Fix High (=Vddq)
SET-UP Cycle
/DOFF
K, /K
C, /C
3. DLL/PLL Off Mode (/DOFF tied low)
- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
DLL/PLL Constraints
1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is
specified as tKC var.
2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz.
(Please refer to AC Characteristics table for detail.)
3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor
(RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to
guarantee impedance matching with a tolerance of 15% is 250 : typical. The total external capacitance of
ZQ ball must be less than 7.5 pF.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
IIP
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
QVLD (Valid data indicator)
(R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM
R1QN, R1QP series)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q
Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be
ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop
capturing the data. QVLD is edge aligned with CQ and /CQ.
ODT (On Die Termination)
(R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated,
especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of
devices. (See the ODT pin table)
2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input. (See the ODT range table)
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data
and disabled when the device outputs data.
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without
ODT.
5. There is no increase in the IDD of SRAMs with ODT, however, there is an increase in the IDDQ (current
consumption from the I/O voltage supply) with ODT.
ODT range
Thevenin equivalent resistance (RTHEV
)
Unit
-
Notes
6
1, 4
2, 5
3
ODT control pin
Option 1
0.3 u RQ
0.6 u RQ
0.6 u RQ
Option 2
(ODT disable)
0.6 u RQ
:
Low
High
Floating
:
:
(ODT disable)
Notes:
1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of r 20 % is
175 : RQ 350 :.
2. Allowable range of RQ to guarantee impedance matching a tolerance of r 20 % is
175 : RQ 250 :.
3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of r 20 % is
175 : RQ 250 :.
4. At option 1, ODT control pin is connected to VDDQ through 3.5 k:. Therefore it is recommended
to connect it to VSS through less than 100 : to make it low.
5. At option 2, ODT control pin is connected to VSS through 3.5 k:. Therefore it is recommended to
connect it to VDDQ through less than 100 : to make it high.
6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
Rev. 0.11b : 2012.06.05
R10DS0189EJ0011
PAGE : ‹#›
IIP
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Thevenin termination
Other LSI
SRAM with ODT
VDDQ
ZQ
2 u RTHEV
RQ
Input
Buffer
Output
Buffer
2 u RTHEV
VSS
VSS
ODT pin (R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
ODT On/Off timing
Option 2
Notes
Pin name
Option 1
3
1
ODT pin = Low
or Floating
ODT pin = High
D0 ~ Dn in separate I/O devices
Always On
Always Off
Off: First Read Command
+ Read Latency
- 0.5 cycle
DQ0 ~ DQn
in common I/O devices
On: Last Read Command
+ Read Latency
Always Off
2
+ BL/2 cycle + 0.5 cycle
(See below timing chart)
/BWx
K, /K
Always On
Always On
Always Off
Always Off
Notes: 1. Separate I/O devices are R1QD, R1QK, R1QP series.
2. Common I/O devices are R1QE, R1QF, R1QL, R1QM series.
3. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with
option 2, please contact Renesas sales office.
Rev. 0.11b : 2012.06.05
R10DS0189EJ0011
PAGE : ‹#›
IIP
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
ODT on/off Timing Chart for R1QE series (DDR II+, Burst Length=2, Read Latency=2.5 cycle)
Read Read Read Read
(B2) (B2) (B2) (B2)
Write Write Write Write Read Read
(B2) (B2) (B2) (B2) (B2) (B2)
NOP
NOP NOP NOP
Status
K, /K
Command
DQ
Ra
Rb
Rc
Rd
We
Wf
Wg
Wh
Ri
Rj
Qa Qa Qb Qb Qc Qc Qd Qd
Disabled
De De Df Df Dg Dg Dh Dh
Enabled
Qi Qi Qj
Disabled
Enabled
DQ ODT
ODT on/off Timing Chart for R1QF series (DDR II+, Burst Length=4, Read Latency=2.5 cycle)
Read
(B4)
Read
(B4)
Write
(B4)
Write
(B4)
Read
(B4)
NOP
-
-
NOP NOP NOP
-
-
-
Status
K, /K
Command
DQ
Ra
Rc
We
Wg
Ri
Qa Qa Qa Qa Qc Qc Qc Qc
Disabled
De De De De Dg Dg Dg Dg
Enabled
Qi Qi Qi
Disabled
Enabled
DQ ODT
ODT on/off Timing Chart for R1QL series (DDR II+, Burst Length=2, Read Latency=2.0 cycle)
Read Read Read Read
(B2) (B2) (B2) (B2)
Write Write Write Write Read Read Read
(B2) (B2) (B2) (B2) (B2) (B2) (B2)
NOP
NOP NOP
Status
K, /K
Command
DQ
Ra
Rb
Rc
Rd
We
Wf
Wg
Wh
Ri
Rj
Rk
Qa Qa Qb Qb Qc Qc Qd Qd
Disabled
De De Df Df Dg Dg Dh Dh
Enabled
Qi Qi Qj Qj Qk Qk
Disabled
Enabled
DQ ODT
ODT on/off Timing Chart for R1QM series (DDR II+, Burst Length=4, Read Latency=2.0 cycle)
Read
(B4)
Read
(B4)
Write
(B4)
Write
(B4)
Read
(B4)
Read
(B4)
NOP
-
-
NOP NOP
-
-
-
Status
K, /K
Command
DQ
Ra
Rc
We
Wg
Ri
Rk
Qa Qa Qa Qa Qc Qc Qc Qc
Disabled
De De De De Dg Dg Dg Dg
Enabled
Qi Qi Qi Qi Qk Qk
Disabled
Enabled
DQ ODT
Notes
1. ODT on/off switching timings are edge aligned with CQ or /CQ.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
K Truth Table
Operation
K
/LD R-/W
DQ
Data in
Write Cycle:
Input
data
Input
clock
Load address, input write
data on consecutive K
and /K rising edges
D(A1)
D(A2)
Ĺ
L
L
K(t+1)Ĺ
/K(t+1)Ĺ
Data out
Output
data
Read Cycle:
Q(A1)
Q(A2)
Load address, output
read data on consecutive
C and /C rising edges
Ĺ
Ĺ
L
H
RL*8=1.5
/C(t+1)Ĺ
C(t+2)Ĺ
/C(t+2)Ĺ
C(t+2)Ĺ
/C(t+2)Ĺ
C(t+3)Ĺ
Input
clock RL=2.0
for Q
RL=2.5
NOP (No operation)
Standby (Clock stopped) Stopped
Notes:
H
u
u
u
High-Z
Previous state
1. H: high level, L: low level, u: don’t care, Ĺ: rising edge.
2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C
rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising
edges.
3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are
registered at the rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. When clocks are stopped, the following cases are recommended; the case of K = low, /K =
high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This
condition is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
7. A1 refers to the address input during a WRITE or READ cycle. A2 refers to the next internal
burst address in accordance with the linear burst sequence.
8. RL = Read Latency (unit = cycle).
Burst Sequence
Linear Burst Sequence Table (R1Q4Aww36 / R1Q4Aww18 series )
SA0
SA0
Notes
External address
0
1
1st internal burst address
1
0
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Byte Write Truth Table ( x 36 )
Operation
K
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
/K
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
/BW0
L
L
L
L
H
H
H
H
H
H
H
H
/BW1
L
L
H
H
L
L
H
H
H
H
H
/BW2
L
L
H
H
H
H
L
L
H
H
H
/BW3
L
L
H
H
H
H
H
H
L
L
H
Write D0 to D35
Write D0 to D8
Write D9 to D17
Write D18 to D26
Write D27 to D35
Write nothing
Ĺ
H
H
H
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 18 )
Operation
K
Ĺ
-
Ĺ
-
Ĺ
-
Ĺ
-
/K
-
Ĺ
-
Ĺ
-
Ĺ
-
/BW0
/BW1
L
L
L
L
L
H
H
L
L
H
H
Write D0 to D17
Write D0 to D8
Write D9 to D17
Write nothing
L
H
H
H
H
Ĺ
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Byte Write Truth Table ( x 9 )
Just Reference except R1Q2A**09 series
Operation
K
Ĺ
-
Ĺ
-
/K
-
Ĺ
-
/BW
L
L
H
H
Write D0 to D8
Write nothing
Ĺ
Notes:
1. H: high level, L: low level, Ĺ: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Bus Cycle State Diagram
/LD = H & Count = 2
R-/W = L
Write Double
Count
= Count + 2
/LD = L
&
/LD = H
Count = 2
/LD = L
Load New
Address
NOP
Count = 0
Supply
voltage
R-/W = H
Read Double
Count
provided
= Count + 2
/LD = L
&
Power
Up
Count = 2
/LD = H & Count = 2
Notes:
1. SA0 is internally advanced in accordance with the burst order table. Bus cycle is terminated at
the end of this sequence (burst count = 2).
2. State machine control timing sequence is controlled by K.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Notes
ꢀ0.5 to VDD + 0.5
Input voltage on any ball
VIN
V
1, 4
(2.5 V max.)
ꢀ0.5 to VDDQ + 0.5
Input/output voltage
VI/O
V
1, 4
(2.5 V max.)
Core supply voltage
Output supply voltage
Junction temperature
Storage temperature
Notes:
VDD
VDDQ
Tj
ꢀ0.5 to 2.5
ꢀ0.5 to VDD
+125 (max)
ꢀ55 to +125
V
V
1, 4
1, 4
5
qC
qC
TSTG
1. All voltage is referenced to VSS.
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted the Operation Conditions. Exposure to higher than
recommended voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications
shown in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF
then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to
exceed 2.5 V, whatever the instantaneous value of VDDQ
.
5. Some method of cooling or airflow should be considered in the system. (Especially for high
frequency or ODT parts)
Recommended DC Operating Conditions
Parameter
Symbol
VDD
VDDQ
VREF
VIH (DC)
VIL (DC)
Min
1.7
1.4
Typ
1.8
1.5
0.75
Max
1.9
VDD
Unit
V
V
V
V
Notes
1
1, 2
Power supply voltage -- core
Power supply voltage -- I/O
Input reference voltage -- I/O
Input high voltage
0.68
VREF + 0.1
ꢀ0.3
0.95
3
VDDQ + 0.3
REF ꢀ 0.1
1, 4, 5
1, 4, 5
Input low voltage
V
V
Notes:
1. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ
.
During normal operation, VDDQ must not exceed VDD.
2. Please pay attention to Tj not to exceed the temperature shown in the absolute maximum
ratings table due to current from VDDQ
3. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF
.
.
4. These are DC test criteria. The AC VIH / VIL levels are defined separately to measure timing
parameters.
5. Overshoot: VIH (AC) d VDDQ + 0.5 V for t d tKHKH/2
Undershoot: VIL (AC) t ꢀ0.5 V for t d tKHKH/2
During normal operation, VIH(DC) must not exceed VDDQ and VIL(DC) must not be lower than VSS.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
DC Characteristics
(Ta = 0 ~ +70qC @ R1Q*A*****BG-**R** series, Ta = -40 ~ +85qC @ R1Q*A*****BG-**I** series)
(VDD = 1.8V r0.1V, VDDQ = 1.5V, VREF = 0.75V)
Operating Supply Current (Write / Read)
Symbol = IDD. Unit = mA. See Notes 1, 2 and 3 in the page after next.
Frequency (max)
533 500 450 400 375 333 300 250 200
(MHz)
No
Cycle Time (min)
1.875 2.00 2.22 2.50 2.66 3.00 3.30 4.00 5.00
(ns)
Part Number
yy
-19
-20
-22
-25
-27
-30
-33
-40
TBD TBD
TBD TBD
-50
Ą
ă
2
3
x18 R1Q 2 A44 18 RBG-yy
x36 R1Q 2 A44 36 RBG-yy
x18 R1Q 3 A44 18 RBG-yy
x36 R1Q 3 A44 36 RBG-yy
x18 R1Q 4 A44 18 RBG-yy
x36 R1Q 4 A44 36 RBG-yy
x18 R1Q 5 A44 18RBG-yy
x36 R1Q 5 A44 36RBG-yy
x18 R1Q 6 A44 18RBG-yy
x36 R1Q 6 A44 36RBG-yy
x18 R1Q A A44 18RBG-yy
x36 R1Q A A44 36RBG-yy
x18 R1Q B A44 18RBG-yy
x36 R1Q B A44 36RBG-yy
x18 R1Q C A44 18RBG-yy
x36 R1Q C A44 36RBG-yy
x18 R1Q D A44 18RBG-yy
x36 R1Q D A44 36RBG-yy
x18 R1Q E A44 18RBG-yy
x36 R1Q E A44 36RBG-yy
x18 R1Q F A44 18RBG-yy
x36 R1Q F A44 36RBG-yy
x18 R1Q N A44 18RBG-yy
x36 R1Q N A44 36RBG-yy
x18 R1Q G A44 18RBG-yy
x36 R1Q G A44 36RBG-yy
x18 R1Q H A44 18RBG-yy
x36 R1Q H A44 36RBG-yy
x18 R1Q J A44 18RBG-yy
x36 R1Q J A44 36RBG-yy
x18 R1Q P A44 18RBG-yy
x36 R1Q P A44 36RBG-yy
x18 R1Q K A44 18RBG-yy
x36 R1Q K A44 36RBG-yy
x18 R1Q L A44 18RBG-yy
x36 R1Q L A44 36RBG-yy
x18 R1Q M A44 18RBG-yy
x36 R1Q M A44 36RBG-yy
B2
B4
B2
B4
B2
QDRII
DDRII
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
5
6
8
9
11
12
14 DDRII
15 SIO
20
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
QDRII+ B4
21
23
24
26
27
32
33
35
36
38
39
41
42
44
45
47
48
50
51
53
54
56
57
59
60
62
63
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
TBD
TBD
B2
QDRII+
B4
TBD
TBD
TBD
TBD
TBD
TBD
B2
DDRII+
B4
TBD
TBD
B2
QDRII+
B4
TBD
TBD
TBD
TBD
TBD
TBD
B2
DDRII+
B4
Notes:
1. "yy" represents the speed bin. "R1QAA4436RBG-20" can operate at 500 MHz(max) of frequency, for example.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Standby Supply Current (NOP)
Symbol = ISB1. Unit = mA. See Notes 2, 4 and 5 in the next page.
Frequency (max)
533 500 450 400 375 333 300 250 200
1.875 2.00 2.22 2.50 2.66 3.00 3.30 4.00 5.00
(MHz)
Cycle Time (min)
(ns)
No
Part Number
yy
-19
-20
-22
-25
-27
-30
-33
-40
TBD TBD
TBD TBD
-50
Ą
ă
2
3
x18 R1Q 2 A44 18 RBG-yy
x36 R1Q 2 A44 36 RBG-yy
x18 R1Q 3 A44 18 RBG-yy
x36 R1Q 3 A44 36 RBG-yy
x18 R1Q 4 A44 18 RBG-yy
x36 R1Q 4 A44 36 RBG-yy
x18 R1Q 5 A44 18RBG-yy
x36 R1Q 5 A44 36RBG-yy
x18 R1Q 6 A44 18RBG-yy
x36 R1Q 6 A44 36RBG-yy
x18 R1Q A A44 18RBG-yy
x36 R1Q A A44 36RBG-yy
x18 R1Q B A44 18RBG-yy
x36 R1Q B A44 36RBG-yy
x18 R1Q C A44 18RBG-yy
x36 R1Q C A44 36RBG-yy
x18 R1Q D A44 18RBG-yy
x36 R1Q D A44 36RBG-yy
x18 R1Q E A44 18RBG-yy
x36 R1Q E A44 36RBG-yy
x18 R1Q F A44 18RBG-yy
x36 R1Q F A44 36RBG-yy
x18 R1Q N A44 18RBG-yy
x36 R1Q N A44 36RBG-yy
x18 R1Q G A44 18RBG-yy
x36 R1Q G A44 36RBG-yy
x18 R1Q H A44 18RBG-yy
x36 R1Q H A44 36RBG-yy
x18 R1Q J A44 18RBG-yy
x36 R1Q J A44 36RBG-yy
x18 R1Q P A44 18RBG-yy
x36 R1Q P A44 36RBG-yy
x18 R1Q K A44 18RBG-yy
x36 R1Q K A44 36RBG-yy
x18 R1Q L A44 18RBG-yy
x36 R1Q L A44 36RBG-yy
x18 R1Q M A44 18RBG-yy
x36 R1Q M A44 36RBG-yy
B2
B4
B2
B4
B2
QDRII
DDRII
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
TBD TBD
5
6
8
9
11
12
14 DDRII
15 SIO
20
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
TBD TBD TBD
QDRII+ B4
21
23
24
26
27
32
33
35
36
38
39
41
42
44
45
47
48
50
51
53
54
56
57
59
60
62
63
B2
DDRII+
B4
QDRII+ B4
B2
DDRII+
B4
TBD
TBD
B2
QDRII+
B4
TBD
TBD
TBD
TBD
TBD
TBD
B2
DDRII+
B4
TBD
TBD
B2
QDRII+
B4
TBD
TBD
TBD
TBD
TBD
TBD
B2
DDRII+
B4
Notes:
1. "yy" represents the speed bin. "R1QAA4436RBG-20" can operate at 500 MHz(max) of frequency, for example.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Leakage Currents & Output Voltage
Parameter
Input leakage current
Output leakage current
Symbol
ILI
Min
ꢀ2
ꢀ5
Max
2
5
Unit
PA
PA
Test condition Notes
10
11
ILO
VOH
V
DDQ ꢀ 0.2
VDDQ
V
V
V
V
|IOH| d 0.1 mA
8, 9
8, 9
8, 9
8, 9
(Low)
Output high voltage
VDDQ/2
ꢀ 0.12
VDDQ/2
ꢁ 0.12
VOH
Note 6
VOL
(Low)
VSS
0.2
IOL d 0.1 mA
Output low voltage
Notes:
VDDQ/2
ꢀ 0.12
VDDQ/2
ꢁ 0.12
VOL
Note 7
1. All inputs (except ZQ, VREF) are held at either VIH or VIL.
2. OUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min.
I
3. Operating supply currents (IDD) are measured at 100% bus utilization. IDD of QDR family is current of
device with 100% write and 100% read cycle. IDD of DDR family is current of device with 100% write
cycle (if IDD(Write) > IDD(Read)) or 100% read cycle (if IDD(Write) < IDD(Read)).
4. All address / data inputs are static at either VIN > VIH or VIN < VIL.
5. Reference value. (Condition = NOP currents are valid when entering NOP after all pending READ and
WRITE cycles are completed. )
6. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 : d RQ d 350 :.
7. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 : d RQ d 350 :.
8. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
9. HSTL outputs meet JEDEC HSTL Class I and Class II standards.
10. 0 d VIN d VDDQ for all input balls (except VREF, ZQ, TCK, TMS, TDI ball).
If R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, balls with ODT do not follow this spec.
11. 0 d VOUT d VDDQ (except TDO ball), output disabled.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Thermal Resistance
Parameter
Junction to Ambient
Junction to Case
Notes:
Symbol Airflow
Typ
9.7
4.4
Unit
Test condition
Notes
șJA
șJC
1 m/s
-
qC/W
EIA/JEDEC JESD51
1
1. These parameters are calculated under the condition. These are reference values.
2. Tj = Ta + șJA Pd
Tj = Tc + șJC Pd
where
Tj : junction temperature when the device has achieved a steady-state
after application of Pd (rC)
Ta : ambient temperature (rC)
Tc : temperature of external surface of the package or case (rC)
șJA : thermal resistance from junction-to-ambient (rC/W)
șJC : thermal resistance from junction-to-case (package) (rC/W)
Pd : power dissipation that produced change in junction temperature (W) (cf.JESD51-2A)
Capacitance
(Ta = +25qC, Frequency = 1.0MHz, VDD = 1.8V, VDDQ = 1.5V)
Parameter
Input capacitance
(SA, /R, /W, /BW, D(separate))
Clock input capacitance (K, /K, C, /C)
Output capacitance
Symbol Min Typ Max Unit Test condition Notes
CIN
CCLK
CI/O
4
4
5
5
5
6
pF
pF
pF
VIN = 0 V
VCLK = 0 V
VI/O = 0 V
1, 2
1, 2
1, 2
(Q(separate), DQ(common), CQ, /CQ)
Notes:
1. These parameters are sampled and not 100% tested.
2. Except JTAG (TCK, TMS, TDI, TDO) pins.
AC Test Conditions
Input waveform (Rise/fall time d 0.3 ns)
1.25V
0.75V
Test points
0.75V
0.25V
Output waveform
VDDQ/2
Test points
VDDQ/2
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Output load conditions Output load and voltage conditions
VDDQ / 2
= 0.75V
1.8Vr0.1V
1.5V
VDDQ / 2
= 0.75V
50:
Z0 = 50:
250:
AC Operating Conditions
Parameter
Input high voltage
Input low voltage
Symbol
VIH (AC)
VIL (AC)
Min
VREF + 0.2
Typ
Max
Unit
V
V
Notes
1, 2, 3, 4
1, 2, 3, 4
VREF – 0.2
Notes:
1. All voltages referenced to VSS (GND).
During normal operation, VDDQ must not exceed VDD.
2. These conditions are for AC functions only, not for AC parameter test.
3. Overshoot: VIH (AC) d VDDQ + 0.5 V for t d tKHKH/2
Undershoot: VIL (AC) t ꢀ0.5 V for t d tKHKH/2
Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates
less than tKHKH (min).
4. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through the target AC level,
VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC level,
VIL (DC) or VIH (DC).
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
00000.0111.0111.0000.0000---RL=2.5
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
AC Characteristics (Read Latency = 2.5 cycle)
(Ta = 0 ~ +70qC @ R1Q*A*****BG-**R** series)
(Ta = -40 ~ +85qC @ R1Q*A*****BG-**I** series)
(VDD = 1.8V r0.1V, VDDQ = 1.5V, VREF = 0.75V)
-19
-20
-22
-25
-27
-30
Unit Notes
Parameter
Symbol
Min Max Min Max Min Max Min Max Min Max Min Max
Clock
Average clock
cycle time
(K, /K)
tKHKH 1.875 4.00 2.00 4.00 2.22 4.00 2.50 4.00 2.66 4.00 3.00 4.00 ns
Clock high time
(K, /K)
Cy-
tKHKL
0.40
0.40
0.40
0.40
0.40
0.40
0.40
0.40
0.40
0.40
0.40
0.40
cle
Clock low time
(K, /K)
Cy-
cle
tKLKH
Clock to /clock
(K to /K)
Cy-
cle
tKH/KH 0.425
t/KHKH 0.425
0.425
0.425
0.425
0.425
0.425
/Clock to clock
(/K to K)
Cy-
cle
0.425
0.425
0.425
0.425
0.425
DLL/PLL Timing
Clock phase
jitter
tKC var
0.15
0.15
0.15
0.20
0.20
0.20 ns
3
(K, /K)
Lock time
(K)
t
KC lock 20
20
30
20
30
20
30
20
30
20
30
us
ns
2
7
K static to
DLL/PLL reset
t
KC reset 30
Output Times
K, /K high to
output valid
tCHQV
0.45
ꢀ0.45
0.45
ꢀ0.45
0.45
ꢀ0.45
0.45
ꢀ0.45
0.45
ꢀ0.45
0.45 ns
K, /K high to
output hold
tCHQX ꢀ0.45
ns
K, /K high to
echo clock valid
tCHCQV
0.45
0.45
0.45
0.45
0.45
0.45 ns
K, /K high to
echo clock hold
tCHCQX ꢀ0.45
ꢀ0.45
ꢀ0.45
ꢀ0.45
ꢀ0.45
ꢀ0.45
ns
CQ, /CQ high to
output valid
tCQHQV
0.15
0.15
0.15
0.20
0.20
0.20 ns 4, 7
CQ, /CQ high to
output hold
tCQHQX ꢀ0.15
ꢀ0.15
ꢀ0.15
ꢀ0.20
ꢀ0.20
ꢀ0.20
ns 4, 7
K, /K high to
output high-Z
tCHQZ
0.45
0.45
0.45
0.45
0.45
0.45 ns 5, 6
K, /K high to
output low-Z
tCHQX1 ꢀ0.45
ꢀ0.45
ꢀ0.45
ꢀ0.45
ꢀ0.45
ꢀ0.45
ns
5
7
CQ high to
QVLD valid
tQVLD ꢀ0.15 0.15 ꢀ0.15 0.15 ꢀ0.15 0.15 ꢀ0.20 0.20 ꢀ0.20 0.20 ꢀ0.20 0.20 ns
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
00000.0111.0111.0000.0000---RL=2.5
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
-19
-20
-22
-25
-27
-30
Parameter
Symbol
Unit Notes
Min Max Min Max Min Max Min Max Min Max Min Max
Setup Times
tAVKH
Address valid to
K rising edge
(QDRII+ B2)
ns
1, 8
tAVKH
0.30
0.33
0.40
0.40
0.40
0.40
(QDRII+ B4 & DDRII+)
tIVKH
Control inputs
valid to
(QDRII+ B2)
ns
ns
1, 8
1, 9
K rising edge
tIVKH
0.30
0.20
0.33
0.22
0.40
0.25
0.40
0.28
0.40
0.28
0.40
0.28
(QDRII+ B4 & DDRII+)
Data-in valid to
K, /K rising edge
tDVKH
Hold Times
tKHAX
K rising edge
to address hold
(QDRII+ B2)
ns
1, 8
tKHAX
0.30
0.33
0.40
0.40
0.40
0.40
(QDRII+ B4 & DDRII+)
tKHIX
K rising edge
to control inputs
hold
(QDRII+ B2)
ns
ns
1, 8
1, 9
tKHIX
0.30
0.20
0.33
0.22
0.40
0.25
0.40
0.28
0.40
0.28
0.40
0.28
(QDRII+ B4 & DDRII+)
K, /K rising edge
to data-in hold
tKHDX
Notes:
1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and
hold times for all latching clock edges.
2. VDD and VDDQ slew rate must be less than 0.1 V DC per 50 ns for DLL/PLL lock retention. DLL/PLL lock
time begins once VDD , VDDQ and input clock are stable.
It is recommended that the device is kept inactive during these cycles.
3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a r0.1 ns variation from
echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations.
5. Transitions are measured r100 mV from steady-state voltage.
6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQV
.
7. These parameters are sampled.
8. tAVKH, tIVKH, tKHAX, tKHIX spec is determined by the actual frequency regardless of Part Number (Marking
Name). The following is the spec for the actual frequency.
0.30 ns for 533MHz & >500MHz
0.33 ns for 500MHz & >450MHz
0.40 ns for 450MHz & 250MHz
9. tDVKH, tKHDX spec is determined by the actual frequency regardless of Part Number (Marking Name). The
following is the spec for the actual frequency.
0.20 ns for 533MHz & >500MHz
0.22 ns for 500MHz & >450MHz
0.25 ns for 450MHz & >400MHz
0.28 ns for 400MHz & 250MHz
Remarks:
1. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise
noted.
2. Control input signals may not be operated with pulse widths less than tKHKL (min).
3. VDDQ is +1.5 V DC. VREF is +0.75 V DC.
4. Control signals are /R, /W (QDR series), /LD, R-/W (DDR series), /BW, /BW0, /BW1, /BW2 and /BW3.
Setup and hold times of /BWx signals must be the same as those of Data-in signals.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0010.0010.0000.0000---
00000.0010.0010.0000.0000---00000.0010.0010.0000.0000---
R1QB_RL=2.5
R
R1QBA44**RBG / R1QEA44**RBG Series (Pr
Timing Waveforms (DDRII+, B2, Read Latency = 2.5 cycle)
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
JTAG Specification
These products support a limited set of JTAG functions as in IEEE standard 1149.1.
Disabling the Test Access Port
It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with
normal operation of the device, TCK must be tied to VSS to preclude mid level inputs.
TDI and TMS are internally pulled up and may be unconnected, or may be connected to VDD through a pull up
resistor.
TDO should be left unconnected.
Test Access Port (TAP) Pins
Symbol I/O Pin assignments Description
Notes
Test clock input. All inputs are captured on the rising edge of
TCK and all outputs propagate from the falling edge of TCK.
Test mode select. This is the command input for the TAP
controller state machine.
TCK
TMS
2R
10R
Test data input. This is the input side of the serial registers
placed between TDI and TDO. The register placed between
TDI and TDO is determined by the state of the TAP controller
state machine and the instruction that is currently loaded in
the TAP instruction.
Test data output. Output changes in response to the falling
edge of TCK. This is the output side of the serial registers
placed between TDI and TDO.
TDI
11R
1R
TDO
Notes:
The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while
TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM
POWER-UP.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
TAP DC Operating Characteristics
(Ta = 0 ~ +70qC @ R1Q*A*****BG-**R** series)
(Ta = -40 ~ +85qC @ R1Q*A*****BG-**I** series)
(VDD = 1.8V r0.1V)
Parameter
Symbol
VIH
Min
+1.3
ꢀ0.3
ꢀ5.0
Typ
Max
VDD + 0.3
ꢁ0.5
Unit
V
V
Notes
Input high voltage
Input low voltage
Input leakage current
VIL
ILI
ꢁ5.0
PA
0 V d VIN d VDD
0 V d VIN d VDD,
Output leakage current
Output low voltage
Output high voltage
ILO
ꢀ5.0
ꢁ5.0
PA
output disabled
VOL1
VOL2
VOH1
VOH2
0.2
0.4
V
V
V
V
IOLC = 100 PA
IOLT = 2 mA
|IOHC| = 100 PA
|IOHT| = 2 mA
1.6
1.4
Notes:
1. All voltages referenced to VSS (GND).
2. At power-up, VDD and VDDQ are assumed to be a linear ramp from 0V to VDD(min.) or
VDDQ(min.) within 200ms. During this time VDDQ < VDD and VIH < VDDQ
.
During normal operation, VDDQ must not exceed VDD.
Rev. 0.11b : 2012.06.05
R10DS0189EJ0011
PAGE : ‹#›
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
TAPAC Test Conditions
Parameter
Input timing measurement reference levels
Input pulse levels
Symbol
VREF
VIL, VIH
tr, tf
Conditions
0.9
0 to 1.8
d 1.0
0.9
0.9
See figures
Unit Notes
V
V
ns
V
V
Input rise/fall time
Output timing measurement reference levels
Test load termination supply voltage (VTT)
Output load
Input waveform
1.8V
0.9V
0V
Test points
0.9V
Output waveform
0.9V
Test points
0.9V
Output load condition
VTT = 0.9V
DUT
TDO
50:
Z0 = 50:
20pF
External Load at Test
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
TAPAC Operating Characteristics
(Ta = 0 ~ +70qC @ R1Q*A*****BG-**R** series)
(Ta = -40 ~ +85qC @ R1Q*A*****BG-**I** series)
(VDD = 1.8V r0.1V)
Parameter
Test clock (TCK) cycle time
TCK high pulse width
TCK low pulse width
Test mode select (TMS) setup
TMS hold
Symbol
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tCS
Min
50
20
20
5
5
5
5
5
Typ
Max
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Capture setup
Capture hold
1
1
tCH
TDI valid to TCK high
TCK high to TDI invalid
TCK low to TDO unknown
TCK low to TDO valid
Notes:
tDVTH
tTHDX
tTLQX
tTLQV
5
0
1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
TMS
TDI
tMVTH
tTHMX
tDVTH
tTHDX
tTLQV
TDO
tTLQX
tCS
tCH
PI
(SRAM
Test Access Port Registers
Register name
Instruction register
Bypass register
Length
3 bits
1 bit
Symbol
IR [2:0]
BP
Notes
ID register
Boundary scan register
32 bits
109 bits
ID [31:0]
BS [109:1]
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
TAP Controller Instruction Set
IR2 IR1 IR0 Instruction
Description
Notes
The EXTEST instruction allows circuitry external to the
component package to be tested. Boundary scan register cells
at output balls are used to apply test vectors, while those at
input balls capture test results. Typically, the first test vector to
be applied using the EXTEST instruction will be shifted into the
boundary scan register using the PRELOAD instruction. Thus,
during the Update-IR state of EXTEST, the output driver is
turned on and the PRELOAD data is driven onto the output balls.
0
0
0
0
0 EXTEST
1 IDCODE
1, 2, 3, 5
The IDCODE instruction causes the ID ROM to be loaded into
the ID register when the controller is in capture-DR mode and
places the ID register between the TDI and TDO balls in shift-
DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in
the Test-Logic-Reset state.
If the SAMPLE-Z instruction is loaded in the instruction register,
all RAM outputs are forced to an inactive drive state (high-Z),
moving the TAP controller into the capture-DR state loads the
data in the RAMs input into the boundary scan register, and the
boundary scan register is connected between TDI and TDO
when the TAP controller is moved to the shift-DR state.
0
0
1
1
0 SAMPLE-Z
1 RESERVED
3, 4, 5
The RESERVED instructions are not implemented but are
reserved for future use. Do not use these instructions.
When the SAMPLE instruction is loaded in the instruction
register, moving the TAP controller into the capture-DR state
loads the data in the RAMs input and I/O buffers into the
boundary scan register. Because the RAM clock(s) are
independent from the TAP clock (TCK) it is possible for the TAP
to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although
allowing the TAP to SAMPLE metastable input will not harm the
device, repeatable results cannot be expected. Moving the
controller to shift-DR state then places the boundary scan
register between the TDI and TDO balls.
SAMPLE
0
1
0
3, 5
(/PRELOAD)
1
1
0
1
1 RESERVED
0 RESERVED
-
-
The BYPASS instruction is loaded in the instruction register
when the bypass register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the shift-DR state.
This allows the board level scan path to be shortened to
facilitate testing of other devices in the scan path.
1
1
1 BYPASS
Notes:
1. Data in output register is not guaranteed if EXTEST instruction is loaded.
2. After performing EXTEST, power-up conditions are required in order to return part to normal
operation.
3. RAM input signals must be stabilized for long enough to meet the TAPs input data capture
setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other
TAP operation except capturing the I/O ring contents into the boundary scan register.
4. Clock recovery initialization cycles are required after boundary scan.
5. For R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series, ODT is disabled in EXTEST,
SAMPLE-Z or SAMPLE mode.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Boundary Scan Order
Signal names
Signal names
Bit # Ball ID
Bit # Ball ID
x9
x18
x36
x9
x18
x36
/C or NC /C or NC /C or NC
1
2
6R
6P
36
37
10E
10D
NC
NC
NC
DQ15
or ODT
C
or ODT
C
or ODT
C
NC
NC
or QVLD or QVLD or QVLD
3
4
5
6
7
8
9
6N
7P
7N
7R
8R
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
DQ0
DQ9
NC
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
NC
NC
NC
NC
NC
DQ4
NC
NC
NC
CQ
SA
SA
SA
SA
SA
/LD
SA
/BW
K
NC
DQ7
NC
NC
NC
DQ8
NC
NC
NC
CQ
SA
NC
DQ17
DQ16
NC
NC
8P
9R
SA
SA
SA
SA
DQ8
DQ7
NC
NC
CQ
SA
SA
SA
SA
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
DQ0
NC
NC
NC
NC
NC
NC
NC
DQ1
NC
NC
NC
NC
NC
NC
NC
DQ2
NC
ZQ
NC
NC
NC
NC
NC
NC
DQ3
DQ0
NC
NC
NC
DQ1
NC
NC
NC
DQ2
NC
NC
NC
DQ3
NC
NC
NC
DQ4
NC
ZQ
NC
DQ11
DQ10
NC
SA
SA
SA
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
NC
SA0 or NC SA0 or NC
DQ2
DQ1
NC
/LD
SA
/BW0
K
/K
NC
/BW1
R-/W
SA
SA
SA
/LD
/BW1
/BW0
K
NC
DQ3
DQ12
NC
/K
/K
NC
NC
R-/W
SA
SA
SA
SA
/CQ
NC
NC
NC
NC
NC
/BW3
/BW2
R-/W
SA
SA
SA
9K
NC
10J
11J
11H
10G
9G
11F
11G
9F
DQ13
DQ4
ZQ
NC
NC
DQ5
DQ14
NC
NC
DQ6
NC
NC
DQ5
NC
NC
NC
DQ6
SA
SA
/CQ
DQ9
NC
NC
NC
/CQ
DQ27
DQ18
NC
NC
DQ19
10F
11E
3D
DQ10
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Boundary Scan Order
Signal names
Signal names
x18
Bit # Ball ID
Bit # Ball ID
x9
NC
NC
NC
DQ5
NC
NC
NC
NC
NC
NC
NC
DQ6
NC
/DOFF
NC
NC
NC
NC
x18
NC
NC
NC
DQ11
NC
NC
NC
DQ12
NC
NC
NC
DQ13
NC
/DOFF
NC
NC
x36
DQ28
NC
x9
DQ7
NC
NC
NC
NC
NC
NC
NC
DQ8
NC
NC
NC
SA
x36
DQ33
DQ24
NC
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
3C
1D
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1H
1J
91
92
2L
3L
DQ15
NC
NC
NC
DQ16
NC
NC
NC
DQ17
NC
NC
NC
SA
SA
SA
SA
SA
SA
NC
93
94
1M
1L
DQ20
DQ29
NC
NC
95
96
97
98
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
DQ25
DQ34
NC
NC
DQ30
DQ21
NC
NC
99
DQ26
DQ35
NC
NC
SA
SA
SA
SA
SA
100
101
102
103
104
105
106
107
108
NC
DQ22
DQ31
/DOFF
NC
NC
DQ23
DQ32
SA
SA
SA
SA
2J
3K
3J
DQ14
NC
SA
SA
INTER-
NAL
INTER-
NAL
INTER-
NAL
89
90
2K
1K
NC
NC
NC
NC
NC
NC
109
Notes:
In boundary scan mode,
1. Clock balls (K, /K, C, /C) are referenced to each other and must be at opposite logic levels for
reliable operation.
2. CQ and /CQ data are synchronized to the respective C and /C (except EXTEST, SAMPLE-Z).
3. If C and /C tied high, CQ is generated with respect to K and /CQ is generated with respect to /K
(except EXTEST, SAMPLE-Z).
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
ID Register
Revision
Type number
(28 : 12)
Start bit (0) ăŇ
-
Vendor JEDEC code
(11 : 1)
number
䊼
䊼
0
(31 :29)
#
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
0
8
0
7
0
6
1
5
0
4
0
3
0
2
1
1
1
Symbol
R
R
R
0
C
M M M A W W
0
1
Q
Q
Q
B
O
S
0
0
1
1
R
0
0
0
0
R
0
0
1
1
:
R
0
1
0
1
Q
0
1
Revison 0
Revison 1
Revison 2
Revison 3
:
II (QDR-II, DDR-II)
II+ (QDR-II+, DDR-II+)
Q
0
1
DDR
QDR
Q
C
36M&72M w/o ODT, 144M,288M
36M&72M w/ ODT
M M M
Latency=1.5 (@II), Latency=2.0 (@II+)
Latency=2.5 (@II+)
0
1
0
1
B
0
1
Density = 36Mb
Density = 72Mb
Density = 144Mb
Density = 288Mb
Burst Length = 2 word burst
Burst Length = 4 word burst
O
0
0
1
1
1
1
0
1
0
1
1
0
without ODT
with ODT
0
1
A
0
1
144M&288M w/o ODT, 36M,72M
144M&288M w/ ODT
W W
S
0
1
Common I/O
Separate I/O
x9
x18
x36
0
1
1
0
0
1
TAP Controller State Diagram
1
Test Logic Reset
0
1
1
1
Run Test/Idle
Select DR Scan
Select IR Scan
0
0
0
1
1
Capture DR
Capture IR
0
0
0
Shift IR
1
0
Shift DR
1
Exit1 DR
0
1
1
Exit1 IR
0
0
0
Pause DR
1
Pause IR
1
0
0
Exit2 DR
1
Exit2 IR
1
Update DR
Update IR
1
0
1
0
Notes:
The value adjacent to each state transition in this figure represents the signal present at TMS at
the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held
high for at least five rising edges of TCK.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Package Dimensions and Marking Information
Both Pb parts and Pb-free parts are available.
JEITA Package Code
P-LBGA165-15x17-1.00
Renesas Code
PLBG0165FD-A
Previous Code
165FHE
Mass (typ.)
0.6 g
D
B
A
Top View
Index Mark
Marking Information
(Laser Mark)
1st row : Vender name (RENESAS)
2nd row: Part number
3rd row : Y
WW
: Year code
: Week code
E
XXXX : Renesas
internal use
This part
number or
mark is just
one example.
4th row : Country name (JAPAN)
+ "None" --- Pb-free parts
+ "PB-F" --- Pb-free parts
S
Side View
A
A1
- y S
Z
D
[e]
Bottom View
[e]
Dimension in mm
Reference
Symbol
Min Nom Max
14.9 15.0 15.1
16.9 17.0 17.1
D
E
A
-
-
1.4
0.31 0.36 0.41
1.0
0.45 0.5 0.6
A1
[e]
b
Z
E
-
-
1
2
3
4
5
6
7
8
9
10 11
x
y
-
-
-
-
-
0.2
0.15
-
Øb
-
Øx(M) S AB
2.5
Z
D
E
Index Mark
-
1.5
-
Z
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
hinS=00000.0000.0000.0000.0000---
00000.0000.0000.0000.0000---
11111.1111.1111.1111.1111---144M
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Revision History (1)
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Rev. 0.11b : 2012.06.05
PAGE : ‹#›
R10DS0189EJ0011
Common
R1QBA44**RBG / R1QEA44**RBG Series (Preliminary)
Renesas Electronics Corporation Headquarters: Nippon Bldg., 2-6-2, Ote-machi, Chiyoda-ku, Tokyo 100-0004, Japan
NOTES:
1.
This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.
Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document
nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this
document.
2.
3.
Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this
document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
You should not use the products or the technology described in this document for the purpose of military applications such as the development of
weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should
follow the applicable export control laws and regulations, and procedures required by such laws and regulations.
All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current
as of the date this document is issued. Such information, however,is subject to change without any prior notice. Before purchasing or using any
Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and
careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website.
(http://www.renesas.com )
4.
5.
6.
Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any
damages incurred as a result of errors or omissions in the information included in this document.
When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding
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suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information
in this document or Renesas products.
7. The products described in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment,
measuring equipment, industrial robotics, domestic appliances, etc.). The products are not designed, manufactured, tested or warranted for
applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or
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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any
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9.
You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating
supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall
have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges.
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13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor
products, or if you have any other inquiries.
Renesas Sales Offices
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
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Tel: +82-2-558-3737, Fax: +82-2-558-5141
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District,
Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
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© 2012 Renesas Electronics Corporation. All rights reserved.
Rev. 0.11b : 2012.06.05
PAGE : ‹#›
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