R1RW0416DSB-0PI [RENESAS]
Wide Temperature Range Version 4M High Speed SRAM (256-kword × 16-bit); 宽温度范围版本4M高速SRAM （ 256千字× 16位）
| 型号： | R1RW0416DSB-0PI |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Wide Temperature Range Version 4M High Speed SRAM (256-kword × 16-bit) |
| 文件： | 总13页 (文件大小：467K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
R1RW0416DI Series
Wide Temperature Range Version
4M High Speed SRAM (256-kword × 16-bit)
REJ03C0109-0201
Rev.2.01
Jun 16, 2010
Description
The R1RW0416DI is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access
time by employing CMOS process (6-transistor memory cell) and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. The R1RW0416DI is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin
plastic TSOPII for high density surface mounting.
Features
•
•
•
Single 3.3 V supply: 3.3 V 0.3 V
Access time: 10ns/12 ns (max)
Completely static memory
No clock or timing strobe required
Equal access and cycle times
•
•
Directly TTL compatible
All inputs and outputs
•
•
•
•
•
Operating current: 145/130 mA (max)
TTL standby current: 40 mA (max)
CMOS standby current: 5 mA (max)
Center VCC and VSS type pin out
Temperature range: −40 to +85°C
Ordering Information
Type No.
R1RW0416DGE-0PI
R1RW0416DGE-2PI
R1RW0416DSB-0PI
R1RW0416DSB-2PI
Access time
Package
10ns
12 ns
10 ns
12 ns
400-mil 44-pin plastic SOJ (44P0K)
400-mil 44-pin plastic TSOPII (44P3W-H)
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 1 of 11
R1RW0416DI Series
Pin Arrangement
Pin Description
Pin name
Function
A0 to A17
I/O1 to I/O16
CS#
Address input
Data input/output
Chip select
OE#
Output enable
Write enable
WE#
UB#
Upper byte select
Lower byte select
Power supply
Ground
LB#
VCC
VSS
NC
No connection
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 2 of
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R1RW0416DI Series
Block Diagram
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 3 of
11
R1RW0416DI Series
Operation Table
CS# OE# WE# LB# UB#
Mode
Standby
VCC current
I/O1−I/O8
High-Z
I/O9−I/O16
High-Z
High-Z
Output
High-Z
Output
High-Z
Input
Ref. Cycle
H
L
L
L
L
L
L
L
L
L
×
H
L
L
L
L
×
×
×
×
×
×
×
ISB, ISB1
ICC
H
H
H
H
H
L
×
×
Output disable
Read
High-Z
Output
Output
High-Z
High-Z
Input
L
L
ICC
Read cycle
Read cycle
Read cycle
L
H
L
Lower byte read ICC
Upper byte read ICC
H
H
L
H
L
ICC
ICC
Write
Write cycle
Write cycle
Write cycle
L
L
H
L
Lower byte write ICC
Upper byte write ICC
Input
High-Z
Input
L
H
H
High-Z
High-Z
L
H
ICC
High-Z
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter
Supply voltage relative to VSS
Voltage on any pin relative to VSS
Power dissipation
Symbol
Value
−0.5 to +4.6
−0.5*1 to VCC + 0.5*2
Unit
VCC
VT
V
V
PT
1.0
W
°C
°C
°C
Operating temperature
Topr
Tstg
−40 to +85
−55 to +125
−40 to +85
Storage temperature
Storage temperature under bias
Tbias
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 4 of
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R1RW0416DI Series
Recommended DC Operating Conditions
(Ta = −40 to +85°C)
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
3
VCC
*
3.0
0
3.3
0
3.6
0
V
V
V
V
4
VSS
VIH
VIL
*
Input voltage
2.0
−0.5*1
VCC + 0.5*2
0.8
Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
3. The supply voltage with all VCC pins must be on the same level.
4. The supply voltage with all VSS pins must be on the same level.
DC Characteristics
(Ta = −40 to +85°C, VCC = 3.3 V 0.3 V, VSS = 0 V)
Max Unit Test conditions
VIN = VSS to VCC
Parameter
Input leakage current
Symbol
|ILI|
Min
2
2
µA
µA
Output leakage current
Operating power supply current
|ILO
ICC
|
VIN = VSS to VCC
130
mA
Min cycle
CS# = VIL, IOUT = 0 mA
Other inputs = VIH/VIL
Standby power supply current
ISB
40
5
mA
mA
Min cycle, CS# = VIH,
Other inputs = VIH/VIL
ISB1
f = 0 MHz
V
CC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Output voltage
VOL
VOH
0.4
V
V
IOL = 8 mA
2.4
IOH = −4 mA
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Test conditions
Parameter
Input capacitance*1
Input/output capacitance*1
Symbol
Min
Max
Unit
CIN
CI/O
6
8
pF
pF
VIN = 0 V
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 5 of
11
R1RW0416DI Series
AC Characteristics
(Ta = −40 to +85°C, VCC = 3.3 V 0.3 V, unless otherwise noted.)
Test Conditions
•
•
•
•
Input pulse levels: 3.0 V/0.0 V
Input rise and fall time: 3 ns
Input and output timing reference levels: 1.5 V
Output load: See figures (Including scope and jig)
Read Cycle
R1RW0416DI
10ns Version
Min Max
12ns Version
Min Max
Parameter
Symbol
tRC
Unit Notes
ns
Read cycle time
10
3
10
10
5
12
3
12
12
6
Address access time
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip select access time
tACS
tOE
Output enable to output valid
Byte select to output valid
Output hold from address change
Chip select to output in low-Z
Output enable to output in low-Z
Byte select to output in low-Z
Chip deselect to output in high-Z
Output disable to output in high-Z
Byte deselect to output in high-Z
tBA
5
6
tOH
5
6
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
3
3
1
1
1
1
1
1
0
0
0
0
5
6
5
6
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 6 of
11
R1RW0416DI Series
Write Cycle
R1RW0416DI
10ns Version 12ns Version
Min Max Min Max
Parameter
Write cycle time
Symbol
tWC
Unit
ns
Notes
10
7
5
12
8
6
Address valid to end of write
Chip select to end of write
Write pulse width
tAW
tCW
tWP
tBW
tAS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
8
8
7
8
7
Byte select to end of write
Address setup time
7
8
0
0
5
6
Write recovery time
tWR
tDW
tDH
0
0
Data to write time overlap
Data hold from write time
Write disable to output in low-Z
Output disable to output in high-Z
Write enable to output in high-Z
5
6
0
0
tOW
tOHZ
tWHZ
3
3
1
1
1
5
6
Notes: 1. Transition is measured 200 mV from steady voltage with output load (B). This parameter is sampled and
not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going low.
6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A write begins
at the latest transition among CS# going low, WE# going low and LB# going low or UB# going low. A write
ends at the earliest transition among CS# going high, WE# going high and LB# going high or UB# going high.
8. tCW is measured from the later of CS# going low to the end of write.
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 7 of
11
R1RW0416DI Series
Timing Waveforms
Read Timing Waveform (1) (WE# = VIH)
Read Timing Waveform (2) (WE# = VIH, LB# = VIL, UB# = VIL)
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 8 of
11
R1RW0416DI Series
Write Timing Waveform (1) (WE# Controlled)
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 9 of
11
R1RW0416DI Series
Write Timing Waveform (2) (CS# Controlled)
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 10 of
11
R1RW0416DI Series
Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH)
REJ03C0109-0201 Rev.2.01
Jun 16, 2010
Page 11 of
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Revision History
R1RW0416DI Series data sheet
Description
Summary
Rev.
Date
Page
−
0.01
1.00
2.00
Sep. 30, 2003
Mar. 12, 2004
May. 01, 2009
Initial issue
−-
Deletion of Preliminary
Addition of access grade 10ns version.
−
The product lineup :R1RW0416DSB-0PI/DGE-0PI is added.
Operating power supply current of 10ns cycle version is described to the
DC characteristic.
P1
P5
The timing standard of 10ns version is described at the read cycle
The timing standard of 10ns version is described at the write cycle
P6/P7
2.01
Jun. 16, 2010
−
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