R1WV6416RSA-5SR [RENESAS]
64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit); 64MB先进LPSRAM （ 4M字X 16位/ 800万字X 8位）
| 型号： | R1WV6416RSA-5SR |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit) |
| 文件： | 总18页 (文件大小：197K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
R1WV6416R Series
64Mb Advanced LPSRAM (4M word x 16bit / 8M word x 8bit)
REJ03C0368-0001
Preliminary
Rev.0.01
2008.03.24
Description
The R1WV6416R Series is a family of low voltage 64-Mbit static RAMs organized as 4,194,304-word by
16-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies.
The R1WV6416R Series is suitable for memory applications where a simple interfacing, battery operating
and battery backup are the important design objectives.
The R1WV6416R Series is provided in 48-pin thin small outline package [TSOP (I): 12mm x 20mm with
pin pitch of 0.5mm], 52-pin micro thin small outline package [µTSOP (II): 10.79mm x 10.49mm with pin pitch
of 0.4mm] and 48-ball fine pitch ball grid array [f-BGA] package. It gives the best solution for compaction of
mounting area as well as flexibility of wiring pattern of printed circuit boards.
Features
•
•
•
•
•
•
•
•
Single 2.7~3.6V power supply
Small stand-by current: 8 µA (3.0V, typical)
No clocks, No refresh
All inputs and outputs are TTL compatible.
Easy memory expansion by CS1#, CS2, LB# and UB#
Common Data I/O
Three-state outputs: OR-tie Capability
OE# prevents data contention on the I/O bus
Ordering Information
Type No.
Access time
55 ns*1
70 ns
Package
R1WV6416RSA-5S%
R1WV6416RSA-7S%
R1WV6416RSD-5S%
R1WV6416RSD-7S%
R1WV6416RBG-5S%
R1WV6416RBG-7S%
12mm x 20mm 48-pin plastic TSOP (I)
(normal-bend type) (48P3R)
350 mil 52-pin plastic μ-TSOP (II)
(normal-bend type) (52PTG)
55 ns*1
70 ns
55 ns*1
70 ns
f-BGA 0.75mm pitch 48-ball
Note1. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on customer’s
system. Please contact our sales office in your region, in case of the inquiry for 55ns parts.
% - Temperature version; see table below
%
R
I
Temperature Range
0 ~ +70 °C
-40 ~ +85 °C
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 1 of 16
R1WV6416R Series
Preliminary
Pin Arrangement
A15
A14
A13
A12
A11
A10
A9
1
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
A16
2
BYTE#
UB#
Vss
3
4
5
LB#
1
2
3
4
5
6
6
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
NC
7
LB#
OE#
A0
A1
A4
A6
A7
A2
A
B
C
D
CS2
DQ0
DQ2
Vcc
A8
8
A19
CS1#
WE#
NC
9
DQ15 UB#
A3
CS1#
DQ1
DQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DQ13 DQ14 A5
Vss DQ12 A17
NC
52-pin μTSOP (II)
Vcc
CS2
A21
A20
A18
A17
A7
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
Vcc DQ11
A21
A16 DQ4
A15 DQ6
A13 WE#
Vss
E
F
DQ10 DQ9
A14
DQ5
DQ7
A20
DQ8
A18
A19
A8
A12
A9
G
H
A6
A10
A11
A5
A4
A3
A2
NC
48-pin f-BGA (TOP VIEW)
A1
A0
A15
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
A14
A13
A12
A11
A10
A9
BYTE#
Vss
3
4
DQ15/A-1
DQ7
5
6
DQ14
DQ6
7
A8
8
DQ13
DQ5
A19
A20
WE#
CS2
A21
UB#
LB#
A18
A17
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
48-pin TSOP (I)
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
A6
DQ8
A5
DQ0
A4
OE#
A3
Vss
A2
CS1#
A0
A1
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 2 of 16
R1WV6416R Series
Preliminary
Pin Description
Pin name
Vcc
Function
Power supply
Vss
Ground
A0 to A21
A-1 to A21
DQ0 to DQ15
CS1#
Address input (word mode)
Address input (byte mode)
Data input/output
Chip select 1
CS2
Chip select 2
WE#
Write enable
OE#
Output enable
LB#
Lower byte enable
Upper byte enable
Byte control mode enable
Non connection
UB#
BYTE#
NC
Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 3 of 16
R1WV6416R Series
Preliminary
Block Diagram
A0
A1
MEMORY ARRAY
2M-word x16-bit
or
ROW
ADDRESS
BUFFER
DECODER
4M-word x 8-bit
DQ0
DQ1
DQ
BUFFER
A21
DQ7
DATA
SENSE / WRITE AMPLIFIER
COLUMN DECODER
SELECTOR
DQ8
DQ9
DQ
BUFFER
CLOCK
DQ15
/ A -1
GENERATOR
CS2
CS1#
LB#
Vcc
Vss
X8 / x16
UB#
CONTROL
BYTE#
WE#
OE#
32Mb SRAM #1
32Mb SRAM #2
Note: BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 4 of 16
R1WV6416R Series
Preliminary
Operation Table
CS1#
CS2
X
BYTE#
LB#
UB#
X
X
H
H
H
L
WE#
X
OE#
X
DQ0~7
High-Z
High-Z
High-Z
Din
DQ8~14
High-Z
High-Z
High-Z
High-Z
High-Z
Din
DQ15
High-Z
High-Z
High-Z
High-Z
High-Z
Din
Operation
H
X
X
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
H
H
H
H
L
X
Stand-by
Stand-by
L
X
X
X
X
H
X
X
Stand-by
H
H
H
H
H
H
H
H
H
H
L
L
X
Write in lower byte
Read in lower byte
Write in upper byte
Read in upper byte
Word write
L
H
L
L
Dout
H
X
High-Z
High-Z
Din
H
L
H
L
L
Dout
Dout
L
L
X
Din
Din
L
L
H
H
L
L
Dout
Dout
Dout
Word read
L
L
H
X
High-Z
Din
High-Z
High-Z
High-Z
High-Z
High-Z
A-1
Output disable
Byte write
L
L
L
L
L
L
H
H
L
Dout
A-1
Byte read
L
L
H
High-Z
A-1
Output disable
Note1. H: VIH L:VIL
X: VIH or VIL
2. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
3. When apply BYTE# =“L”, please assign LB#=UB#=“L”.
Absolute Maximum Ratings
Parameter
Power supply voltage relative to Vss
Terminal voltage on any pin relative to Vss
Power dissipation
Symbol
Vcc
VT
Value
unit
V
-0.5 to +4.6
-0.5*1 to Vcc+0.3*2
0.7
V
PT
W
R ver.
I ver.
0 to +70
°C
°C
°C
°C
°C
Operation temperature
Topr*3
Tstg
-40 to +85
-65 to 150
0 to +70
Storage temperature range
Storage temperature range under bias
R ver.
I ver.
Tbias*3
-40 to +85
Note 1. –2.0V in case of AC (Pulse width ≤30ns)
2. Maximum voltage is +4.6V.
3. Ambient temperature range depends on R/I-version. Please see table on page 1.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 5 of 16
R1WV6416R Series
Preliminary
Recommended Operating Conditions
Parameter
Symbol
Min.
2.7
0
Typ.
Max.
3.6
Unit
V
Note
Supply voltage
Vcc
Vss
VIH
3.0
0
-
0
V
Input high voltage
Input low voltage
2.4
-0.2
0
V
Vcc+0.2
0.4
VIL
-
V
1
2
2
R ver.
I ver.
-
+70
+85
°C
°C
Ambient temperature range
Ta
-40
-
Note 1. –2.0V in case of AC (Pulse width ≤ 30ns)
2. Ambient temperature range depends on R/I-version. Please see table on page 1.
DC Characteristics
Parameter
Input leakage current
Output leakage current
Symbol
| ILI |
Min.
-
Typ.
-
Max.
1
Unit
Test conditions*3
Vin = Vss to Vcc
μA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS1# =VIH or CS2 =VIL or
| ILO
|
-
-
-
-
1
μA
mA
mA
OE# =VIH or WE# =VIL or
LB# = UB# =VIH, VI/O =Vss to Vcc
Min. cycle, duty =100%, II/O = 0mA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS1# =VIL, CS2 =VIH, Others = VIH/VIL
Cycle =1μs, duty =100%, II/O = 0mA
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS1# ≤ 0.2V, CS2 ≥ VCC-0.2V,
VIH ≥ VCC-0.2V, VIL ≤ 0.2V
Average operating current
ICC1
45*1
60
10
ICC2
5*1
Standby current
Standby current
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
CS2 =VIH
ISB
-
-
0.1*1
8*1
0.3
24
mA
Vin ≥ 0V
μA
~+25°C
BYTE# ≥ Vcc -0.2V or
BYTE# ≤ 0.2V
-
-
-
14*2
48
μA
μA
μA
~+40°C
(1) 0V ≤ CS2 ≤ 0.2V or
ISB1
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
-
-
100
160
~+70°C
~+85°C
CS2 ≥ VCC-0.2V
Output high voltage
Output low voltage
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
IOH = -0.5mA
VOH
VOL
2.4
-
-
-
-
V
V
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
IOL = 2mA
0.4
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested.
3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 6 of 16
R1WV6416R Series
Preliminary
Capacitance
(Ta =25°C, f =1MHz)
Parameter
Input capacitance
Symbol
C in
Min.
Typ.
Max.
20
Unit
pF
Test conditions
Note
-
-
-
-
Vin =0V
1
1
Input / output capacitance
C I/O
20
pF
V I/O =0V
Note1.This parameter is sampled and not 100% tested.
AC Characteristics
Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
•
•
•
•
Input pulse levels: VIL = 0.4V, VIH = 2.4V
Input rise and fall time: 5ns
Input and output timing reference level: 1.4V
Output load: See figures (Including scope and jig)
1.4V
RL = 500 ohm
DQ
CL = 30 pF
Note1. Ambient temperature range depends on R/I-version. Please see table on page 1.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 7 of 16
R1WV6416R Series
Read Cycle
Preliminary
Note
R1WV6416R**-5S
(Note 0)
R1WV6416R**-7S
Parameter
Symbol
Unit
Min.
55
-
Max.
-
Min.
70
-
Max.
-
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
55
55
25
-
70
70
70
35
-
tACS1
tACS2
tOE
-
-
Chip select access time
-
-
Output enable to output valid
Output hold from address change
LB#, UB# access time
-
-
tOH
10
-
10
-
tBA
55
-
70
-
tCLZ1
tCLZ2
tBLZ
tOLZ
tCHZ1
tCHZ2
tBHZ
tOHZ
10
10
5
10
10
5
2,3
2,3
Chip select to output in low-Z
-
-
LB#, UB# enable to low-Z
-
-
2,3
Output enable to output in low-Z
5
-
5
-
2,3
0
20
20
20
20
0
25
25
25
25
1,2,3
1,2,3
1,2,3
1,2,3
Chip deselect to output in high-Z
0
0
LB#, UB# disable to high-Z
0
0
Output disable to output in high-Z
0
0
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 8 of 16
R1WV6416R Series
Write Cycle
Preliminary
Note
R1WV6416R**-5S
(Note 0)
R1WV6416R**-7S
Parameter
Symbol
Unit
Min.
55
50
50
40
50
0
Max.
Min.
70
65
65
55
65
0
Max.
Write cycle time
tWC
tAW
tCW
tWP
tBW
tAS
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to end of write
Chip select to end of write
Write pulse width
-
-
5
4
-
-
LB#, UB# valid to end of write
Address setup time
-
-
-
-
6
7
Write recovery time
tWR
tDW
tDH
0
-
0
-
Data to write time overlap
Data hold from write time
Output enable from end of write
Output disable to output in high-Z
Write to output in high-Z
25
0
-
35
0
-
-
-
tOW
tOHZ
tWHZ
5
-
5
-
2
0
20
20
0
25
25
1,2
1,2
0
0
Note0. 55ns parts can be supported under the condition of the input timing limitation toward SRAM on
customer’s system. Please contact our sales office in your region, in case of the inquiry for 55ns parts.
In case of tAA =70ns, tRC =70ns.
1. tCHZ, tOHZ, tWHZ and tBHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and
from device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#.
A write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going
low or UB# going low .
A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going high and LB#
going high or UB# going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to end of write.
6. tAS is measured the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 9 of 16
R1WV6416R Series
Preliminary
Note
BYTE# Timing Conditions
R1WV6416R**-5S R1WV6416R**-7S
Parameter
Symbol
Unit
Min.
5
Max.
Min.
5
Max.
Byte setup time
tBS
tBR
-
-
-
-
ms
ms
Byte recovery time
5
5
BYTE# Timing Waveforms
CS1#
CS2
tBS
tBR
BYTE#
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 10 of 16
R1WV6416R Series
Preliminary
Timing Waveforms
Read Cycle*1
tRC
A0~21
(Word Mode)
A -1~21
(Byte Mode)
tOH
tAA
tBA
LB#,UB#
tBLZ
tCLZ1
tCLZ2
tBHZ
tACS1
CS1#
CS2
tCHZ1
tACS2
tCHZ2
VIH
WE#
WE# = “H” level
VIL
tOE
OE#
tOLZ
tOHZ
DQ0~15
(Word Mode)
DQ0~7
High impedance
Valid Data
(Byte Mode)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 11 of 16
R1WV6416R Series
Preliminary
Write Cycle (1)*1 (WE# CLOCK)
tWC
A0~21
(Word Mode)
A -1~21
(Byte Mode)
tOH
tBW
LB#,UB#
tCW
CS1#
CS2
tCW
tAW
tWP
tAS
tWR
WE#
OE#
tWHZ
tOLZ
tOHZ
tOW
DQ0~15
(Word Mode)
DQ0~7
Valid Data
tDW tDH
(Byte Mode)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 12 of 16
R1WV6416R Series
Preliminary
Write Cycle (2)*1 (CS1#, CS2 CLOCK)
tWC
A0~21
(Word Mode)
A -1~21
(Byte Mode)
tAW
tBW
LB#,UB#
tAS
tCW
tWR
CS1#
CS2
tAS
tCW
tWR
tWP
WE#
VIH
OE#
OE# = “H” level
VIL
tDW
tDH
DQ0~15
(Word Mode)
DQ0~7
Valid Data
(Byte Mode)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 13 of 16
R1WV6416R Series
Preliminary
Write Cycle (3)*1 (LB#, UB# CLOCK)
tWC
A0~21
(Word Mode)
A -1~21
(Byte Mode)
tAW
tAS
tBW
tWR
LB#,UB#
tCW
CS1#
CS2
tCW
tWP
WE#
VIH
OE#
OE# = “H” level
VIL
tDW
tDH
DQ0~15
(Word Mode)
DQ0~7
Valid Data
(Byte Mode)
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 14 of 16
R1WV6416R Series
Preliminary
Low Vcc Data Retention Characteristics
Parameter
Symbol Min.
Typ Max.
Unit
V
Test conditions*3,4
Vin ≥ 0V
BYTE# ≥ Vcc -0.2V or BYTE# ≤ 0.2V
(1) 0V ≤ CS2 ≤ 0.2V or
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
VCC for data retention
VDR
2.0
-
3.6
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
CS2 ≥ VCC-0.2V
Vin ≥ 0V
-
-
-
-
8*1
24
48
μA
μA
μA
μA
~+25°C
BYTE# ≥ Vcc -0.2V or
BYTE# ≤0.2V
14*2
~+40°C
(1) 0V ≤ CS2 ≤ 0.2V or
Data retention current
ICCDR
(2) CS1# ≥ VCC-0.2V,
CS2 ≥ VCC-0.2V or
(3) LB# = UB# ≥ VCC-0.2V,
CS1# ≤ 0.2V,
-
-
100
160
~+70°C
~+85°C
CS2 ≥ VCC-0.2V
Chip select to data retention
time
tCDR
tR
0
5
-
-
-
-
ns
See retention waveform.
Operation recovery time
ms
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 40ºC), and not 100% tested.
3. BYTE# pin is supported for 48-pin TSOP (I) and 52-pin µTSOP (II) packages.
4. CS2 also controls address buffer, WE# buffer ,CS1# buffer ,OE# buffer ,LB# ,UB# buffer and Din buffer. If
CS2 controls data retention mode, Vin levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ Vcc-0.2V or0V ≤ CS2 ≤ 0.2V.
The other input levels (address, WE# ,OE#,CS1#,LB#,UB#,I/O) can be in the high impedance state.
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 15 of 16
R1WV6416R Series
Preliminary
Low Vcc Data Retention Timing Waveforms*1
(1) CS1# Controlled
Vcc
2.7V
2.7V
tCDR
tR
VDR
2.2V
2.2V
CS1# ≥ Vcc - 0.2V
CS1#
(2) CS2 Controlled
Vcc
2.7V
2.7V
CS2
tCDR
tR
VDR
0.6V
0.6V
0V ≤ CS2 ≤ 0.2V
(3) LB#, UB# Controlled
Vcc
2.7V
2.7V
tCDR
tR
VDR
2.2V
2.2V
LB#, UB#
LB#, UB# ≥ Vcc - 0.2V
Note1. BYTE# ≥ Vcc – 0.2V or BYTE# ≤ 0.2V
REJ03C0368-0001, Rev.0.01, 2008.03.24
Page 16 of 16
Revision History
R1WV6416R Data Sheet
Contents pf Revision
Description
Initial issue: Preliminary Data Sheet
Rev.
0.01
Date
Mar.24, 2008
Page
-
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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