R2A20150NP [RENESAS]

8-bit I/O Expander for I2C BUS (Corresponds to Fast mode); 8位I / O扩展为I2C总线（与快速模式）


型号：	R2A20150NP
厂家：	RENESAS TECHNOLOGY CORP
描述：	8-bit I/O Expander for I2C BUS (Corresponds to Fast mode) 8位I / O扩展为I2C总线（与快速模式）
文件：	总11页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

New Product

R2A20150NP/SA

8-bit I/O Expander for I²C BUS (Corresponds to Fast mode)

R03DS0012EJ0100

Rev.1.00

2011.09.05

Description

The R2A20150NP/SA is a CMOS 8-bit I/O expander, which has serial to parallel and parallel to serial

data converting functions.

It can communicate with a microcontroller via few wiring thanks to the adoption of the 2-wire I²C BUS.

Maximum 8 ICs can be connected to a bus by using 3-chip select pins, so that it is possible to handle up

to 64 bits data.

Features

 Simple 2-wire (SCL and SDA) communication with a microcontroller.

 8-bit data conversion between serial and parallel by I²C BUS.

 Corresponds to Fast mode (400kHz) of I²C BUS specification.

 Possible to set input and output each bit separately.

 By using three chip select pins (CS0,CS1,CS2), R2A20150 can connect with the same BUS line

to maximum 8 pieces.

 Very small package line-up QFN-16 and TSSOP-16.

Application

I/O port expansion of Microcomputer.

Data conversion from serial to parallel and from parallel to serial in peripheral of Microcomputer.

Block Diagram

CS0 CS1 CS2

Number for TSSOP package

Number for QFN package

I²C BUS

TRANSCIEVER

SCL

SDA

SHIFT

RESISTOR

Output Data

Input/Output

INPUT

I/O SETTING

OUTPUT

DATA LATCH

Reset

Input Data

VDD

POWER ON

RESET

I/O PORT

GND

D7 D6 D5 D4 D3 D2 D1 D0

R03DS0012EJ0100 Rev.1.00

2011.09.05

Page 1 of 10

New Product

R2A20150NP/SA

Pin Arrangement

R2A20150NP (Top view)

R2A20150SA (Top view)

CS0

CS1

CS2

V^DD

SCL

SDA

CS2

VDD

D3 7

GND

Package: PTSP0016JB-A [SA]

Package: PWQN0016KB-A [NP]

EXPLANATION OF TERMINALS The pin No. of ( ) are for QFN package

Pin No.

Symbol

I/O

Function

TSSOP

QFN

SCL

SDA

Output

Input

Serial data output terminal

Serial clock input terminal

Input/Output Serial data input/output terminal

Parallel data input/output terminal

Input/Output

( Initial state after power on is input mode. )

CS2

CS1

CS0

V^DD

GND

Chip select data input terminal

This IC accessed only when the lower 3bits data from

Slave address coincide with the data of CS0 to CS2.

Input

Power supply terminal

GND terminal

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

Absolute Maximum Ratings

(Ta= 25 deg unless otherwise noted)

Symbol

VDD

Item

Conditions

Ratings

Unit

Supply voltage

-0.3 to +6.5

Input voltage

-0.3 to V^DD+0.3 (<6.5)

Output voltage

IOH

Output current “High”

D0 ~ D7

-5 to 0

0 to +4

0 to +30

Continuous

Peak

IOL

Output current “Low” *1

Power dissipation

Ta= +85deg

Ta> +25deg

290(NP) / 150(SA)

7.25(NP) / 3.75(SA)

-30 to +85

K theta Thermal derating factor

mW/deg

deg

Topr

Tstg

Operating temperature range

Storage temperature

-40 to +125

deg

*1 : The maximum ratings of Output current “Low” is 4mA when using continuously for each port, but peak current is

30mA (13% duty) when considering duty cycle including power off period.

Recommended Operating conditions

Limits

Symbol

Item

Conditions

Unit

Min

2.7

Typ

Max

5.5

VDD

VIH

V^IL

Supply voltage

5.0

Input high voltage

Input low voltage

0.8VDD

VDD

0.2V^DD

(VDD = +5V +/-10%, GND=0V, Ta= -30 to +85deg unless otherwise noted)

Limits

Electrical Characteristics

Symbol

Item

Conditions

Unit

Min

Typ

0.05

0.1

Max

0.5

V^IH=VDD, VIL=GND, fSCL=400kHz

VIH=VDD, VIL=GND, fSCL=STOP

µA

I^DD

Circuit current

IILK

V^OL

VIH

Input leak current

-10

Output low voltage (SDA)

Input high voltage

Isink=3mA

0.8VDD

0.4

VDD

VIL

Input low voltage

0.2VDD

Vhys

Hysteresis of Schmitt trigger input (SDA, SCL)

0.5

0.8

IOH=-1mA, VDD=5V

IOH=-500µA, VDD=3V

I^OL=5mA, VDD=5V

IOL=2.5mA, VDD=3V

V^OL=0.4V, VDD=5V

VDD – 0.4

V^DD

VDD

0.4

Output high voltage

(D0 ~ D7)

V^OH

V^OL

VDD – 0.4

Output low voltage

(D0 ~ D7)

VOL=0.4V, VDD=3V

V^OL=1.0V, VDD=5V

V^OL=1.0V, VDD=3V

VDD=0 to 2.7V

2.5

Output current “Low” *2

(D0 ~ D7)

I^OL

trVDD

Supply voltage rise-up time *3

100

µs

Operating voltage of internal reset *3

VDDPOR

VDD=0 to 2.7V

1.5

1.9

Time period of re-power on

(Power supply OFF  ON) *3

tPOR

VDD < 0.1V

*2 : Output low current should be set; average current of summary of D0 to D3 or D4 to D7 < 16mA.

Average current is calculate by below equation;

Average current = I^OLX duty duty : The period of flow IOL (Include power off period)

*3 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on

quickly, initialize is not operate. So, keep the time period of re-powered on (t^POR).

trVDD

(equivalent to trVDD)

tPOR

VDDPOR

VDD

GND

< 0.1V

Internal

Reset signal

GND

Resetting period

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

I²C BUS Characteristics

Normal mode

Fast mode

Item

Symbol

Unit

kHz

µs

Min.

Max.

Min.

Max.

SCL clock frequency

fSCL

tBUF

100

400

Free time: the bus must be free before a new

transmission can start

4.7

4.0

1.3

0.6

Hold time START condition after this period, the first

Clock pulse is generated

tHD:STA

µs

Low period of the clock

High period of the clock

tLOW

tHIGH

4.7

4.0

1.3

0.6

µs

Set-up time for START condition.

Only relevant for a repeated START condition.

tSU:STA

4.7

0.6

µs

Data Hold time

tHD:DAT

tSU:DAT

250

3.45

100

0.9

µs

Data Set-up time

Rise time of SDA and SCL signals

Fall time of SDA and SCL signals

Set-up time for STOP condition

Capacitive load of bus line

1000

300

tSU:STO

4.0

0.6

400

All of above value are corresponds to VIHmin and VILmax.

Timing Chart

tR, tF

tBUF

VIH

SDA

VIL

tHD:STA

tSU:DAT

tHD:DAT

tsu:STA

tSU:ST0

VIH

VIL

SCL

tLOW

tHIGH

Start

Stop

Start

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

Functional Blocks

 I²C BUS Interface

The I²C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection

by receiving SDA,SCL,CS0,CS1 and CS2 signals and then the latch pulse, dedicated to each data latch

are generated.

 Data Latch

This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch

and each latch is controlled by the I²C BUS interface.

 I/O setting data latch

These latches set input-state or output-state of each parallel data terminals (D0 to D7). They are

set at the next byte after receiving the slave address byte in the write mode from the master.

In case this latch is set to high, the data is transferred from the I²C BUS interface to the parallel

data terminals. In the opposite transmission: from the parallel data terminals to the I²C BUS,

it is set to low.

 Output data latch

In the write mode, the data from the I²C BUS to the parallel data terminals is latched.

When the master transmits output data after a setting in write mode, the output data is taken into

the latch.

 Input data latch

In the read mode, the data of parallel data terminals is latched in the input data latches. The input

data is taken into the latches from the parallel data terminals on every 8th negative edge of SCL clock.

The latched data is output to the master through the sift resistor. On the output terminal assigned by

the I/O setting latch, the input data latch takes the state of the output terminal.

 Parallel Input/Output Port

In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance

and is able to accept an input. In another case I/O setting latch is set to high (output mode), each parallel

terminal output a data according to the state of the output data latch.

 Serial Output Port

The parallel data from each parallel terminal are conversion to 8bit serial data and output to SO terminal.

Without serial output mode, SO terminal goes to low output.

 Power on Reset

When the power is turned on, each latch is reset (initialize) and then the parallel data I/O terminals

become hi-impedance (input mode).

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

Digital Data Format

1.Write mode: I²C BUS data input to parallel data output

(The data transmits continuously each 8bits after setting slave address and I/O.)

FIRST

LAST

Slave address

I/O setting

8bit data

2.Read mode: Parallel data input to I²C BUS data output)

(The data transmits continuously each 8bits after setting slave address. When final data transmitted,

do not return the acknowledge, then input the stop condition.)

FIRST

LAST

Slave address

8bit data

R A

Transmission from Master (MCU etc.) to Slave (R2A20150)

Transmission from Slave (R2A20150) to Master (MCU etc.)

 S: Start condition

While SCL level is high, SDA line level should be changed from high to low.

Chip select data

 Slave address

MSB

LSB

CS2

CS1

CS0

FIRST

MSB

LAST

LSB

1 1

A2 A1 A0

Note: Lower three bits (A0, A1, A2) are a programmable address.

This IC is accessed only when the lower 3 bits data of slave

address coincide with the data of CSO to CS2. (refer to the right table)

 W: Write (SDA = Low), R: Read (SDA = High)

 A: Acknowledge bit

(L=Low,H=High)

(Slave side confirm the data receive, change to Low in the SDA line)

*A: IN a read mode; after final data transmitted, do not return acknowledge. Change to High.)

 I/O setting data (I/O setting of parallel data I/O terminals.)

FIRST

LAST

MSB

LSB

P7 P6 P5 P4 P3 P2 P1 P0

Note: DATA INPUT from parallel data terminals = Low

DATA OUTPUT to parallel data terminals = High

Each bit data corresponds to the I/O state of the parallel data terminals.

 8-bit data

LAST

FIRST

LSB

MSB

D7 D6 D5 D4 D3 D2 D1 D0

 P: Stop condition

While SCL level is high, SDA level should be changed from low to high.

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

FUNCTIONAL DESCRIPTION

All parallel data I/O terminals are set to the input-state after power-on. In case any terminals need to be

set to the output state, the corresponding terminals should be set during the write mode.

This setting is hold until a next setting.

In the write mode, 8 bits data can be transmitted from the I²C BUS interface to the parallel ports continually

After the slave address and I/O setting.

In the read mode, 8 bits data can be transmitted from the parallel ports to the I2C BUS interface continually

After the slave address setting. This 8 bits serial data is output from the SO terminal. SO terminal sets

to “L” state without read mode.

In the case of a changing between the write- and read-mode, the data must be transmitted again from the

Starting condition.

Transmission from a master (MCU etc.)

In a case of a data conversion from serial to parallel

Transmission from a slave (R2A20150)

Start

Stop

condition

Slave address

I/O setting byte

condition

DATA

A2 A1 A0

P7 P6 P5 P4 P3 P2 P1 P0

D₁7 D₁6 D₁5 D₁4 D₁3 D₁2 D₁1 D₁0 A D₂7 D₂6 D₂5 D₂4 D₂3 D₂2 D₂1 D₂0 A

SDA

SCL

Data output

Hi-Z

D X

In a case of a data conversion from parallel to serial

All I/O setting resistors are set to low (input) in the write mode, before a parallel data is read.

(All I/O setting resistors are set to the input mode after power-on.)

Start

condition

Transmission from a master (MCU etc.)

Transmission from a slave (R2A20150)

Slave address

I/O setting byte

A2 A1 A0

P7 P6 P5 P4 P3 P2 P1 P0

SDA

SCL

D0 to D7

output

Hi-Z

Stop

condition

DATA

Start

condition

DATA

Slave address

DATA

A2 A1 A0

D₁7 D₁6 D₁5 D₁4 D₁3 D₁2 D₁1 D₁0

D₃7 D₃6 D₃5 D₃4 D₃3 D₃2 D₃1 D₃0 A D₄7 D₄6 D₄5 D₄4 D₄3 D₄2 D₄1 D₄0 A

SDA

SCL

D₁7 D₁6 D₁5 D₁4 D₁3 D₁2 D₁1 D₁0

D₃7 D₃6 D₃5 D₃4 D₃3 D₃2 D₃1 D₃0

D₄7 D₄6 D₄5 D₄4 D₄3 D₄2 D₄1 D₄0

D0 to D7

Input

D X

(example)

Data latch

D0 to D7

output

Hi-Z

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

In case the I/O setting is different between each terminals.

An example : the parallel port terminals of D0 to D3 and D4 to D7 are assigned as output and

input terminals, respectively.

Stop

condition

Start

condition

Slave address

I/O setting byte

DATA

A2 A1 A0

P7 P6 P5 P4 P3 P2 P1 P0

D₁7 D₁6 D₁5 D₁4 D₁3 D₁2 D₁1 D₁0 A D₂7 D₂6 D₂5 D₂4 D₂3 D₂2 D₂1 D₂0 A

SDA

SCL

Data output

D0 to

Hi-Z

D X

D4 to

Hi-Z

Start

condition

Stop

condition

Slave address

DATA

SDA

A2 A1 A0

D₁7 D₁6 D₁5 D₁4 D₁3 D₁2 D₁1 D₁0

D₃7 D₃6 D₃5 D₃4 D₃3 D₃2 D₃1 D₃0 A D₄7 D₄6 D₄5 D₄4 D₄3 D₄2 D₄1 D₄0 A

SCL

D₁7 D₁6 D₁5 D₁4 D₁3 D₁2 D₁1 D₁0

D₃7 D₃6 D₃5 D₃4 D₃3 D₃2 D₃1 D₃0

D₄7 D₄6 D₄5 D₄4 D₄3 D₄2 D₄1 D₄0

D0 to D3

D4 to D7

(instance)

D X

Data latch

D4 to D7

output

Hi-Z

* Write mode

The terminal assigned as an output provides the data written in the output data latch.

After power-on, all terminals are reset to the input-state. Then an initial data low of the output latch are

output after the I/O setting has been done. Finally the assigned output are provided after the 8-bit data

transmission.

Then terminal assigned as an input keeps the input condition (High-impedance) regardless of 8-bit data

setting.

* Read mode

The input data is taken into input latch on every 8th negative-going edge of the SCL clock through the

terminal assigned as an input, and then the latched data is output via the SDA line.

The data of the output assigned terminal is also handled in the same procedures as above.

R03DS0012EJ0100 Rev.1.00

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New Product

R2A20150NP/SA

TYPICAL APPLICATION

10F

V^DD

2 4

3 5

4 6

5 7

7 9

8 10

9 11

10 12

14 12

CS2

CS1

CS0

Chip select data

15 13

16 14

Parallel input/

Output terminal

SCL

2 16

MCU

3 1 SDA

Serial data output

15 1

GND

Number for TSSOP package

Number for QFN package

Ordering Information

Order part No. Package Name

Package Code Package type No.

Packing/Quantity

R2A20150SA

R2A20150NP

TSSOP-16

QFN-16

PTSP0016JB-A

PWQN0016KB-A

Embossed Taping/2,000 pcs.

Embossed Taping/3,000 pcs.

R03DS0012EJ0100 Rev.1.00

2011.09.05

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New Product

R2A20150NP/SA

Package outline

SA: PTSP0016JB-A

NP: PWQN0016KB-A

R03DS0012EJ0100 Rev.1.00

2011.09.05

Page 10 of 10

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Colophon 1.1

R2A20150NP [RENESAS]

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