R2A20162SA [RENESAS]
8-bit 2ch D/A Converter with Buffer; 8位双声道D / A转换器与缓冲器型号: | R2A20162SA |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 8-bit 2ch D/A Converter with Buffer |
文件: | 总8页 (文件大小:400K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
New Product
R2A20162NS/SA/SP
8-bit 2ch D/A Converter with Buffer
R03DS0016EJ0100
Rev.1.00
2011.09.05
Description
The R2A20162 is an integrated circuit semiconductor of CMOS structure with 2 channels of built in D/A
converters with output buffer op-amps. It is the electrical characteristic improvement version of the M62342.
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and
can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements
unnecessary and enabling configuration of a system with few component parts.
Very small SON package is added to lineup. It is suitable for a small mounting and reduces the mounting area.
Features
Guarantee Differential Nonlinearity error : +/- 0.7LSB, Nonlinearity error : +/- 1.0LSB,
Data transfer format: 10-bit serial data input type by 3 wire ( DI, SCK, LD )
Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V )
High output current capacity: +/- 1mA or Higher
Very mall size package line-up: SON-8 (pin pitch: 0.5mm), TSSOP-8 (pin pitch 0.65mm)
Application
Conversion from digital data to analog control data for home-use and industrial equipment.
Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor.
Blurring correction control or various control of the interchangeable lens of digital camera for self
adjustment by combination with microcomputer and EEPROM. (substitution of half fixed resistance)
Block Diagram
Vcc
4
GND
5
LD
8
CLK
7
DI
6
10-bit shift register
Power on
reset
Channel
decoder
8
8-bit latch
8-bit latch
8-bit upper
8-bit upper
segment R-2R
Segment R-2R
1
2
3
Ao1
Ao2
N.C.
Page 1 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
New Product
R2A20162NS/SA/SP
Pin Arrangement
R2A20162NS (Top view)
R2A20162SA/SP (Top view)
1
2
3
4
8
7
6
5
Ao1
Ao2
N.C.
Vcc
LD
1
2
3
4
8
7
6
5
Ao1
Ao2
N.C.
Vcc
LD
CLK
DI
CLK
DI
GND
GND
N.C.: Not connected
N.C.: Not connected
Outline: PRSP0008DE-C [SP]
PTSP-0008JC-B [SA]
Outline: PWSN0008KA-A [NS]
Pin Description
Pin No. Pin Name
Function
Serial data input terminal.
6
DI
(Input serial data with a 10-bit data length.)
Serial clock input terminal
7
CLK
(Input signal from DI terminal is input to 10-bit shift register at rise of serial
clock.)
Load terminal
8
LD
(When High level is input to LD terminal, value in 10-bit shift register is
loaded into decoder and 8-bit latch.)
1
2
3
4
5
Ao1
A02
N.C.
Vcc
8-bit resolution D/A converter output terminals
(After power-on, all channels are reset and DAC data 00h is output.)
Not connected
Power supply terminal
GND terminal
GND
Page 2 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
New Product
R2A20162NS/SA/SP
Absolute Maximum Ratings
(Ta= +25deg unless otherwise noted)
Item
Supply voltage
Symbol
Vcc
Conditions
Ratings
-0.3 to +6.5
Unit
V
Input voltage
Vin
-0.3 to Vcc+0.3 <6.5
-0.3 to Vcc+0.3 <6.5
-2.0 to +2.0
V
Output voltage
Vo
V
IAO
Continuous
Ta=85deg
Ta>25deg
mA
Buffer amplifier output current
Power dissipation
Pd
mW
mW/deg
deg
deg
270(NS) / 200(SA) / 272(SP)
6.75(NS) / 5.0(SA) / 6.8(SP)
-30 to +85
Thermal derating factor
Operating temperature
Storage temperature
K theta
Topr
Tstg
-40 to +125
Electrical Characteristics
( Vcc= +5V +/-10%, GND=0V, Ta= -30 to +85deg unless otherwise noted)
Limits
Item
Supply voltage
Symbol
Test Conditions
Unit
Min.
Typ.
Max.
2.7
5.0
5.5
V
Vcc
Icc
CLK = 1MHz operation, IAO=0µA,
DATA: 6Ah (at maximum current)
0
0.7
2.5
mA
Supply current
SDA = SCL = GND, IAO=0µA
Vcc=0 to 2.7V
0
0.5
—
1.6
—
mA
µs
Supply voltage rise-up time *1
Operating voltage of
100
trVcc
Vcc=0 to 2.7V
—
1.5
1.9
V
VccPOR
Internal resetting
*1
Time period of re-power on
(Power supply OFF ON) *1
Vcc < 0.1V
1
—
—
—
ms
µA
tPOR
VIN= 0 to Vcc
Input leak current
-10
10
IILK
VIL
Input low voltage
0
—
—
—
—
—
0.2Vcc
Vcc
V
V
V
4.0V < Vcc
Vcc < 4.0V
IAO= +/-100µA
IAO= +/-500µA
0.5Vcc
0.8Vcc
0.1
Input high voltage
VIH
VAO
IAO
Vcc
Vcc-0.1
Vcc-0.2
Buffer amplifier output voltage
range
V
0.2
Buffer amplifier output drive
range
Upper side saturation voltage = 0.3V
Lower side saturation voltage = 0.2V
-1.0
—
1.0
mA
Differential nonlinearity
Nonlinearity
-0.7
-1.0
-2.0
-2.0
—
—
—
—
—
—
0.7
1.0
2.0
2.0
0.1
LSB
LSB
LSB
LSB
µF
SDL
SL
Vcc=5.12V (20mV/ LSB),
without load (IAO= 0µA)
Zero code error
SZERO
SFULL
Co
Full scale error
Output capacitate load
Buffer amplifier output
impedance
—
5.0
—
ohm
Ro
*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered on quickly,
initialize is not operate. So, keep the time period of re-powered on (tPOR).
(equivalent to trVcc)
trVcc
tPOR
VccPOR
GND
Vcc
Internal
< 0.1V
Reset signal
GND
Resetting period
Resetting period
Page 3 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
New Product
R2A20162NS/SA/SP
AC Characteristics
( Vcc = +5V +/-10deg, GND = 0V, Ta = -30 to +85deg unless otherwise noted )
Limits
Item
Symbol
Test Conditions
Unit
Min.
-
Typ.
Max.
Clock frequency
Clock high pulse width
Clock low pulse width
Clock rise time
1.0
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
fCLK
tCKH
tCKL
tCR
40
40
-
-
-
-
-
-
-
-
-
-
-
-
200
Clock fall time
-
200
tCF
Data setup time
Data hold time
5
-
-
-
-
-
tDCH
tCHD
tCHL
tLDC
tLDH
30
40
40
40
Load setup time
Load hold time
Load high pulse width
Ta=25deg, CL<100pF, VAO: 0.54.5V,
D/A output settling time
-
-
150
µs
tLDD
The time until the output becomes the final
value of 1/2 LSB.
Timing Chart
tCR
tCKH
tCF
CLK
DI
tCKL
tDCH
tCHD
tLDH
tLDD
tLDC
tCHL
LD
D/A
output
(Note) Timing chart above is a schematic representation of the timing of each signal type.
CLK signal input is High or Low regardless, LD signal High input is enabled.
Page 4 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
New Product
R2A20162NS/SA/SP
Digital Data Format
Last
LSB
First
MSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DAC data
Channel
Select data
Channel select data
D8
0
D9
0
Channel selection
Ao1 selected
1
0
Ao2 selected
Don’t care
Don’t care
0
1
1
1
DAC data
D0
0
D1
0
D2
0
D3
D4
0
D5
D6
0
D7
0
DAC output
0
0
0
0
0
0
0
0
Vcc/256 x 1
Vcc/256 x 2
Vcc/256 x 3
Vcc/256 x 4
1
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Vcc/256 x 255
Vcc
Data timing chart ( Model )
D9
D8
D7
D6
D5
D2
D1
D0
DI
CLK
Whether CLK input is “H” or “L”,
High level input of LD signal is recognized.
LD
D/A
output
Page 5 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
New Product
R2A20162NS/SA/SP
Precaution For use
Supply voltage terminal (Vcc) is also used for D/A converter upper reference voltage setting. If ripple or
spike is input this terminal, accuracy of D/A converter is down, So, when use this device, please connect
capacitor among Vcc to GND for stable D/A conversion.
This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when
connect capacitor ( 0.1 µF Max ) among output to GND for every noise elimination.
Application Example
Ao1
Ao2
1
2
LD
CLK
DI
8
7
6
Analog output
terminals
MCU
N.C.
Vcc
3
4
GND
5
+
5V
10µF
Ordering Information
Order part No. Package Name
Package Code Package type No.
Packing/Quantity
R2A20162SP
R2A20162SA
R2A20162NS
SOP-8
TSSOP-8
SON-8
PRSP0008DE-C
RTSP0008JC-B
PWSN0008KA-A
SP
SA
NS
Embossed Taping/2,500 pcs.
Embossed Taping/3,000 pcs.
Embossed Taping/5,000 pcs.
Package Dimensions
PWSN0008KA-A [NS]
Page 6 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
New Product
R2A20162NS/SA/SP
PRSP0008DE-C [SP]
PTSP0008JC-B [SA]
Page 7 of 7
R03DS0016EJ0100 Rev.1.00
2011.09.05
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