R2A20168SA#W5 [RENESAS]
8-bit 8ch D/A Converter with Buffer Amplifiers;
| 型号： | R2A20168SA#W5 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-bit 8ch D/A Converter with Buffer Amplifiers 光电二极管 转换器 |
| 文件： | 总10页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
R2A20168NP/SA/SP
8-bit 8ch D/A Converter with Buffer Amplifiers
R03DS0019EJ0200
Rev.2.00
Jul 03, 2013
Description
The R2A20168 is an integrated circuit semiconductor of CMOS structure with 8 channels of built in D/A
unnecessary and enabling configuration of a system with few component parts.
Serial data transfer type input can easily be used through a combination of three lines: DI, CLK, and LD.
Outputs incorporate buffer op-amps that have a drive capacity of 1 mA or above for both sink source, and
can operate over the entire voltage range from almost ground to Vcc ( 0 to 5V ), making peripheral elements
unnecessary and enabling configuration of a system with few component parts.
Very small QFN package is added to lineup. It is suitable for a small mounting and reduces the mounting area.
Features
· Guarantee Nonlinearity error : +/-1.0LSB, Differential nonlinearity error : +/-0.7LSB
· Data transfer format: 12-bit serial data input type by 3 wire ( DI, SCK, LD )
· Output buffer op-amps: Operable over entire voltage range from almost ground to Vcc ( 0 to 5V )
· Very small size package line-up: QFN-16(pin pitch: 0.5mm), TSSOP-16(pin pitch 0.65mm)
Application
· Conversion from digital data to analog control data for home-use and industrial equipment.
· Signal gain control or automatic adjustment of LCD-TV, PDP-TV or LCD display-monitor.
· Blurring correction control or various control of the interchangeable lens of digital still camera.
· Automatic adjustment by combination with microcomputer and EEPROM.
(substitution of half fixed resistance)
Block Diagram
Number for SOP/TSSOP package
Number for QFN package
14 12
13 11
DI
12-bit shift register
D0 D1 D2 D3 D4 D5 D6 D7
DO
LD
9
11
D8 D9 D10 D11
CLK
Channel decoder
10 12
9
7
Vcc
1
2
3 4 5 6 7 8
8
Power on
reset
8
1
8
8-bit latch
8–bit latch
8-bit upper
8-bit upper
segment R-2R
segment R-2R
16
GND
14
8
3
5
4
6
5
7
2
6
8
13
15
16
2
1
3
15
1
4
10
Ao5
Ao6 Ao7
Ao8
VrefL
VrefU
Ao2 Ao3 Ao4
Ao1
Page 1 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
Pin Arrangement
R2A20168NP (Top view)
R2A20168SA/SP (Top view)
VrefL
Ao2
Ao3
Ao4
Ao5
Ao6
GND
Ao1
DI
1
2
3
4
5
6
7
8
16
15
14
1
2
3
4
12
11
10
9
DI
Ao3
Ao4
Ao5
Ao6
CLK
LD
CLK
LD
13
12
11
10
9
DO
Ao8
Vcc
DO
Ao7
VrefU
Outline: PTSP0016JB-A [SA]
PRSP0016DH-B [SP]
Outline: PWQN0016KB-A [NP]
Pin Description
Pin No.
[TSSO
Symbol
Function
P
[QFN]
/SOP]
Serial data input terminal.
( Input serial data with a 12-bit data length )
Serial clock input terminal
(Input signal from DI terminal is input to 12-bit shift register at rise of
serial clock.)
12
11
14
DI
13
CLK
Load terminal
(When High level is input to LD terminal, value in 12-bit shift register
is loaded into decoder and 8-bit latch.)
Serial data output terminal
10
9
12
11
LD
Do
(Data is sequentially output from the MSB bit.)
13
16
1
15
2
Ao1
Ao2
Ao3
Ao4
Ao5
Ao6
Ao7
Ao8
Vcc
3
2
4
8-bit resolution D/A converter output terminals
(After power on, all channels are reset and DAC data 00h is output.)
3
5
4
6
5
7
8
10
9
7
Power supply terminal
GND terminal
14
6
16
8
GND
VrefU
VrefL
D/A converter upper reference voltage input terminal
D/A converter lower reference voltage input terminal
15
1
Page 2 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
(Ta= +25deg unless otherwise noted)
Absolute Maximum Ratings
Item
Symbol
Conditions
Ratings
Unit
Supply voltage
Vcc
VrefU
VrefL
IAO
-0.3 to +6.5
-0.3 to +6.5
V
V
D/A converter upper reference voltage
D/A converter lower reference voltage
Buffer amplifier output current
Input voltage
-0.3 to +6.5
V
Continuous
-2.0 to +2.0
mA
V
Vin
-0.3 to Vcc+0.3 <+6.5
-0.3 to Vcc+0.3 <+6.5
290(NP) / 150(SA) / 300(SP)
7.25(NP) / 3.75(SA) / 7.5(SP)
-30 to +85
Output voltage
Vo
V
Power dissipation
Pd
Ta= +85deg
Ta> +25deg
mW
mW/deg
deg
deg
Thermal derating factor
Operating temperature
Storage temperature
K theta
Topr
Tstg
-40 to +125
Electrical Characteristics
« Digital Part »
( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted )
Limits
Item
Symbol
Test conditions
Unit
Min
Typ
Max
5.5
1.2
10
Supply voltage
Supply current
Input leak current
Input low voltage
Vcc
Icc
IILK
VIL
2.7
5.0
V
mA
µA
V
CLK =1MHz, Vcc =5V, IAO =0µA
VIN = 0 to Vcc
-
0.4
-10
-
-
-
-
-
-
-
0.2Vcc
-
4.0V < Vcc
Vcc £ 4.0V
0.55Vcc
V
Input high voltage
VIH
0.8Vcc
-
V
4.0V < Vcc, IOL = 2.0mA
Vcc < 4.0V, IOL = 1.5mA
-
-
0.4
0.4
V
Output low voltage
Output high voltage
VOL
V
Vcc –
0.4
VOH
trVcc
IOH = -400µA
Vcc = 0 to 2.7V
Vcc = 0 to 2.7V
-
-
-
-
V
µs
V
Supply voltage
rise time *1
100
-
Internal reset
operating voltage *1
VccPOR
1.5
1.9
Power supply restart
interval (Power supply
t
POR
Vcc < 0.1V
1
-
-
ms
OFF à ON)
*1
*1 : When power supply is turned on, internal circuit is initialized by power on reset circuit. But, if re-powered
on quickly, initialize is not operate. So, keep the time period of re-powered on (tPOR).
(equivalent to trVcc)
tPOR
trVcc
VccPOR
GND
Vcc
Internal
< 0.1V
Reset signal
GND
Resetting period
Resetting period
Page 3 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
« Analog Part »
Item
( Vcc, VrefU = +5V +/-10%, Vcc>VrefU, GND,VrefL =0V, Ta= -30 to +85deg, Unless otherwise noted )
Limits
Symbol
Test conditions
Unit
Min
Typ
Max
VrefU=5V, VrefL=0V, IAO=0µA,
Data condition: at maximum current
Current dissipation
IrefU
-
1.0
2.0
mA
Vcc 4.5V
Vcc < 4.5V
Vcc 4.5V
Vcc<4.5V
3.5
0.7Vcc
GND
GND
-
-
-
-
Vcc
Vcc
D/A converter upper
reference voltage range *2
VrefU
V
V
Vcc-3.5
0.3Vcc
D/A converter lower
reference voltage range *2
VrefL
IAO = +/- 100 µA
IAO = +/- 500 µA
0.1
0.2
-
-
Vcc – 0.1
Vcc – 0.2
V
V
Buffer amplifier output
voltage range
VAO
Upper side saturation voltage = 0.3V,
Lower side saturation voltage = 0.2V
Buffer amplifier output
drive range
IAO
-1.0
-
1.0
mA
Differential nonlinearity
Nonlinearity
SDL
SL
-0.7
-1.0
-2.0
-2.0
-
-
-
-
-
-
0.7
1.0
2.0
2.0
0.1
LSB
LSB
LSB
LSB
µF
VrefU = 4.79V,
VrefL = 0.95V,
Vcc = 5.5V (15mV/LSB),
Without load (IAO =0µA)
Zero code error
SZERO
SFULL
Co
Full scale error
Output capacitive load
Buffer amplifier output
impedance
Ro
-
5.0
-
ohm
*2 : The output does not necessary be the value with the reference voltage setting range.
The output value is determined by the buffer amplifier output voltage range (VAO).
Page 4 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
AC Characteristics
( Vcc,VrefU = +5V +/-10%, Vcc VrefU, GND=VrefL = 0V, Ta = -30 to +85deg, unless otherwise noted )
Limits
Test conditions
Unit
Item
Symbol
Min
Typ
Max
Clock frequency
Clock low pulse width
Clock high pulse width
Clock rise time
fCLK
tCKL
tCKH
tCR
-
40
40
-
1.0
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
-
-
200
Clock fall time
tCF
-
200
Data setup time
Data hold time
tDCH
tCHD
tCHL
tLDC
tLDH
tDO
4
-
-
30
40
40
40
-10
LD setup time
-
LD hold time
-
LD high pulse width
Data output delay time
-
CL < 100 pF
50
Ta=25deg, CL<100pF, VAO: 0.5¬ ® 4.5V,
D/A output settling time
tLDD
-
-
150
µs
The time until the output becomes the final
value of 1/2 LSB.
Timing Chart
tCR
tCKH
tCF
CLK
DI
tCKL
tDCH
tCHD
tLDH
tLDC
tCHL
LD
tLDD
D/A
output
tDo
Do
output
(Note) Timing chart above is a schematic representation of the timing of each signal type.
CLK signal input is High or Low regardless, LD signal High input is enabled.
Page 5 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
Digital Data Format
Last
LSB
First
MSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
DAC data
Channel
select data
Channel select data
D8
0
D9
0
D10
D11
0
Chanel Selection
Don’t care
Ao1 select
Ao2 select
Ao3 select
Ao4 select
Ao5 select
Ao6 select
Ao7 select
Ao8 select
Don’t care
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
1
:
:
:
:
:
1
1
1
1
1
1
0
1
Don’t care
Don’t care
DAC data
D0
0
D1
0
D2
0
D3
0
D4
0
D5
0
D6
0
D7
D/A Output
0
0
0
0
(VrefU – VrefL) / 256 x 1 + VrefL
(VrefU – VrefL) / 256 x 2 + VrefL
(VrefU – VrefL) / 256 x 3 + VrefL
(VrefU – VrefL) / 256 x 4 + VrefL
1
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
:
:
:
:
:
:
:
:
:
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(VrefU – VrefL) / 256 x 255 + VrefL
VrefU
Page 6 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
Data Timing Chart ( Model )
MSB
LSB
D0
D11
D10
D9
D8
D7
D2
D1
DI
CLK
Whether CLK input is “H” or “L”, high
level input of LD signal is recognized.
LD
D/A
output
Precaution For Use
· There are three terminals (Vcc, VrefU, VrefL) that should be impressed a constant voltage. When ripple
or spike noise is input to this terminal, there is fear that the accuracy of D/A conversion becomes lower and
this IC malfunction. So, when use this IC, please connect capacitor between these terminals (Vcc, VrefU, VrefL)
and GND for stable D/A conversion.
· This IC’s output amplifier has an advantage to capacitive load, So, it’s no problem at device action when
connect capacitor ( 0.1µF Max ) among output to GND for every noise elimination.
Standard Application Circuit
Vcc
+
Ao1
Ao2
10µF
10µF
VrefU
+
Analog voltage
output
LD
CLK
DI
MCU
Ao7
Ao8
VrefL
+
10µF
GND
Page 7 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
Package Dimensions
PRSP0016DH-B [SP]
PTSP0016JB-A [SA]
Page 8 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
Datasheet
R2A20168NP/SA/SP
PWQN0016KB-A [NP]
Ordering Information
Order part No. Package Name
Package Code Package type No.
Packing/Quantity
R2A20168SP
R2A20168SA
R2A20168NP
SOP-16
TSSOP-16
QFN-16
PRSP0016DH-B
RTSP0016JB-A
PWQN0016KB-A
SP
SA
NP
Embossed Taping/2,000 pcs.
Embossed Taping/2,000 pcs.
Embossed Taping/3,000 pcs.
Page 9 of 9
R03DS0019EJ0200 Rev.2.00
Jul 03, 2013
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