R2J20655NP [RENESAS]
Integrated Driver - MOS FET (DrMOS); 集成的驱动程序 - MOS场效应管(的DrMOS )型号: | R2J20655NP |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | Integrated Driver - MOS FET (DrMOS) |
文件: | 总18页 (文件大小:169K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Preliminary Datasheet
R2J20655NP
Integrated Driver - MOS FET (DrMOS)
R07DS0200EJ0100
Rev.1.00
Jan 25, 2011
Description
The R2J20655NP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in
a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.
Features
Based on Intel 6 6 DrMOS Specification.
Built-in power MOS FET suitable for Desktop, Server application.
Low-side MOS FET with built-in SBD for lower loss and reduced ringing.
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
High-frequency operation (above 1 MHz) possible
VIN operating-voltage range: 27 Vmax
Large average output current (Max.35 A)
Achieve low power dissipation
Controllable driver: Remote on/off
Low side MOS FET disabled function for DCM operation
Double thermal protection: Thermal Warning & Thermal Shutdown
Built-in bootstrapping Switch
Small package: QFN40 (6 mm 6 mm 0.95 mm)
Pb-free/Halogen-Free
Outline
Integrated Driver-MOS FET (DrMOS)
QFN40 package 6 mm × 6 mm
VCIN Reg5V BOOT GH
VIN
1
10
40
11
THWN
DISBL#
LSDBL#
PWM
Driver
Pad
High-side
MOS Pad
VSWH
MOS FET Driver
Low-side MOS Pad
31
20
30
21
CGND
GL PGND
(Bottom view)
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 1 of 17
R2J20655NP
Preliminary
Block Diagram
Driver Chip
VCIN
Reg5V
BOOT
GH
UVL
THWN
THDN
Boot
SW
THWN
VIN
Reg5V
DISBL#
High Side
MOS FET
2 μA
Supervisor
CGND
Level Shifter
20 k
Reg5V
CGND
160 k
LSDBL#
VSWH
Overlap
Protection.
& Logic
Low Side
MOS FET
Reg5V
Reg5V
Input Logic
(TTL Level)
(3 state in)
PWM
35 k
PGND
CGND
GL
Notes: 1. Truth table for the DISBL# pin
DISBL# Input Driver Chip Status
"L" Shutdown (GL, GH = "L")
2. Truth table for the LSDBL# pin
LSDBL# Input
GL Status
"L"
"L"
"Open"
"H"
Shutdown (GL, GH = "L")
Enable (GL, GH = "Active")
"Open"
"H"
"Active"
"Active"
3. Output signal from the UVL block
4. Output signal from the THWN block
For active
"H"
"H"
Thermal
Warning
UVL output
Logic Level
Normal
operating
For shutdown
Thermal Warning
Logic Level
"L"
VCIN
"L"
T
IC(°C)
VL
VH
TwarnL TwarnH
5. Truth table for the THDN block
Driver IC Temp.
< 150°C
Driver Chip Status
Enable (GL, GH = "Active")
> 150°C
Shutdown (GL, GH = "L")
(latch-off)
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 2 of 17
R2J20655NP
Preliminary
Pin Arrangement
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
VIN
VIN
PWM
DISBL#
THWN
CGND
GL
VIN
CGND
VIN
VIN
VSWH
PGND
PGND
PGND
PGND
PGND
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
21 22 23 24 25 26 27 28 29 30
(Top view)
Note: All die-pads (three pads in total) should be soldered to PCB.
Pin Description
Pin Name
LSDBL#
Reg5V
VCIN
Pin No.
Description
Low-side gate disable
+5 V logic power supply output
Control input voltage
Bootstrap voltage pin
Control signal ground
High-side gate signal
Input voltage
Remarks
1
2
3
4
When asserted "L" signal, Low-side gate disable
Driver Vcc input
BOOT
CGND
GH
To be supplied +5 V through internal switch
Should be connected to PGND externally
Pin for monitor
5, 37, Pad
6
VIN
8 to 14, Pad
VSWH
PGND
GL
7, 15, 29 to 35, Pad Phase output/Switch output
16 to 28
36
Power ground
Low-side gate signal
Thermal warning
Signal disable
Pin for monitor
THWN
DISBL#
38
Thermal warning when over 115°C
39
Disabled when DISBL# is "L".
This Pin is pulled low when internal IC over the
thermal shutdown level, 150°C.
PWM
40
PWM drive logic input
Capable of both 3.3 V and 5 V logic input
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 3 of 17
R2J20655NP
Preliminary
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Pt(25)
Rating
Units
Note
Power dissipation
25
W
1
Pt(110)
8
Average output current
Input voltage
Iout
35
A
V
VIN(DC)
VIN(AC)
VSWH(DC)
VSWH(AC)
VBOOT(DC)
VBOOT(AC)
VCIN
–0.3 to +27
2
2, 4, 6
2
30
Switch node voltage
BOOT voltage
27
V
V
30
32
2, 4, 6
2
36
2, 4, 6
2
Supply voltage
PWM voltage
–0.3 to +27
V
V
Vpwm
–0.3 to +5.5 @UVL OFF
–0.3 to +0.3 @UVL ON
–0.3 to Reg5V + 0.3
2, 4
2, 5
2, 7, 8
Other I/O voltage
Vdisbl, Vlsdbl
Vreg5V
–0.3 to VCIN + 0.3
–0.3 to +6
V
V
2
2, 7
3
Reg5V voltage
Reg5V current
Ireg5V
–20 to +0.1
0 to 1.0
mA
mA
°C
°C
THWN/THDN current
Operating junction temperature
Storage temperature
Ithwn, Idisbl
Tj-opr
3
–40 to +150
–55 to +150
Tstg
Notes: 1. Pt(25) represents a PCB temperature of 25°C, and Pt(110) represents 110C.
2. Rated voltages are relative to voltages on the CGND and PGND pins.
3. For rated current, (+) indicates inflow to the chip and (–) indicates outflow.
4. This rating is when UVL (Under Voltage Lock out) is ineffective (normal operation mode).
5. This rating is when UVL (Under Voltage Lock out) is effective (lock out mode).
6. The specification values indicated "AC" are limited within 10 ns.
7. This rating is when the external power-source is applied to Reg5V pin.
8. Reg5V + 0.3 V < 6 V
Safe Operating Area
45
40
35
30
25
20
VOUT = 1.3 V
15
VIN = 12 V
10
5
VCIN = 5 V
L = 0.45 μH
Fsw = 1 MHz
0
0
25
50
75
100
125
150
175
PCB Temperature (°C)
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 4 of 17
R2J20655NP
Preliminary
Recommended Operating Condition
Item
Symbol
VIN
VCIN
Rating
Units
Note
Input voltage
4.5 to 22
V
V
When the usage of VCIN = 4.5 V to 5.5 V,
VCIN should be connected to Reg5V
(Refer to "Pin Connection")
Supply voltage &
Drive voltage
4.5 to 5.5
or
8 to 22
Electrical Characteristics
(Ta = 25°C, VCIN = 12 V, VSWH = 0 V, unless otherwise specified)
Item
Symbol
VH
Min
7.0
6.6
—
Typ
7.4
7.0
0.4
49
Max
7.8
7.4
—
Units
V
Test Conditions
Supply
VCIN start threshold
VCIN shutdown threshold
UVLO hysteresis
VL
V
dUVL
ICIN
V
VH – VL
VCIN operating current
—
—
mA
fPWM = 1 MHz,
Ton_pwm = 120 ns
VCIN disable current
ICIN-DISBL
—
—
800
A
DISBL# = 0 V,
PWM = LSDBL# = Open
PWM
input
PWM input high level
PWM input low level
PWM input resistance
PWM input tri-state range
Shutdown hold-off time
Enable level
VH-PWM
VL-PWM
RIN-PWM
VIN-tri
2.6
—
—
—
—
0.8
25
V
V
3.3 V/5.0 V PWM interface
6.5
1.4
—
12.5
—
k
V
PWM = 1 V
2.0
—
3.3 V/5.0 V PWM interface
1
tHOLD-OFF
VENBL
*
150
—
ns
V
DISBL#
input
2.0
—
—
Disable level
VDISBL
—
0.8
5.0
1.0
—
V
Input current
IDISBL
—
2.0
0.5
—
A
k
V
DISBL# = 1 V
1
THDN on resistance
Low-side activation level
Low-side disable level
Input current
RTHDN
*
0.2
2.0
—
DISBL# = 0.2 V
LSDBL#
input
VLSDBLH
VLSDBLL
ILSDBL
—
0.8
–12
130
—
V
–52
100
—
–26
115
15
A
°C
°C
k
A
°C
LSDBL# = 1 V
1
Thermal
warning
Warning temperature
Temperature hysteresis
THWN on resistance
THWN leakage current
Shutdown temperature
TTHWN
*
Driver IC temperature
1
THYS
RTHWN
ILEAK
*
1
*
0.2
—
0.5
—
1.0
1.0
—
THWN = 0.2 V
THWN = 5 V
Thermal
Tstdn *1
130
150
Driver IC temperature
shutdown
5 V
regulator
Output voltage
Line regulation
Load regulation
Vreg
4.95
–10
–10
5.2
0
5.45
10
V
Vreg-line
Vreg-load
mV
mV
VCIN = 12 V to 16 V
Ireg = 0 to 10 mA
0
10
Note: 1. Reference values for design. Not 100% tested in production.
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 5 of 17
R2J20655NP
Preliminary
Typical Application
(1) Desktop/Server Application
+12 V
VCIN
BOOT
THWN
DISBL#
Reg5V
VIN
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
VCIN
BOOT
+5 V
THWN
DISBL#
Reg5V
VIN
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
PWM1
PWM2
+1.3 V
PWM
Control
PWM3
Circuit
PWM4
VCIN
BOOT
THWN
DISBL#
Reg5V
VIN
Power GND
Signal GND
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
VCIN
BOOT
THWN
DISBL#
Reg5V
VIN
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 6 of 17
R2J20655NP
Preliminary
Typical Application (cont.)
(2) Notebook Application
+19 V
+5 V
VCIN
BOOT
THWN
DISBL#
Reg5V
VIN
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
VCIN
BOOT
THWN
DISBL#
Reg5V
VIN
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
PWM1
PWM2
+1.1 V
PWM
Control
PWM3
Circuit
VCIN
BOOT
THWN
DISBL#
Reg5V
VIN
Power GND
Signal GND
R2J20655NP VSWH
PWM
PGND
CGND LSDBL# GH
GL
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 7 of 17
R2J20655NP
Preliminary
Pin Connection
(1) Single 12 V Application
0.1 μF
1.0 μF
CGND
VIN
1.0 μF
12 V
Low Side Disable Signal INPUT
CGND
10
9
8
7
6
5
4
3
2
1
10 μF × 4
11
PWM 40
DISBL# 39
THWN 38
CGND 37
GL 36
VSWH 35
34
PWM INPUT
12
Thermal Shutdown
VIN
PAD
CGND
PAD
13
PGND
14 VIN
10 kΩ
10 kΩ
15 VSWH
VCIN
VCIN
R2J20655NP
16 PGND
17
18
19
20
VSWH
PAD
33
Thermal Warning
32
31
21 22 23 24 25 26 27 28 29 30
0.45 μH
Power GND Signal GND
PGND
Vout
PGND
(2) VCIN 5 V Application
0.1 μF
1.0 μF
VIN
Low Side Disable Signal INPUT
12 V
5.0 V
External
Power Supply
CGND
10
9
8
7
6
5
4
3
2
1
10 μF × 4
11
PWM 40
PWM INPUT
12
DISBL# 39
THWN 38
CGND 37
GL 36
VSWH 35
34
Thermal Shutdown
VIN
PAD
CGND
PAD
13
PGND
14 VIN
10 kΩ
10 kΩ
15 VSWH
5 V
5 V
R2J20655NP
16 PGND
17
18
19
20
VSWH
PAD
33
Thermal Warning
32
31
21 22 23 24 25 26 27 28 29 30
0.45 μH
Power GND Signal GND
PGND
Vout
PGND
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 8 of 17
R2J20655NP
Preliminary
Test Circuit
IIN
A
A
Vinput
Vcont
VIN
V
ICIN
VCIN
V
VCIN
BOOT
VIN
DISBL#
R2J20655NP
Reg5V
VSWH
PGND
LSDBL#
Electric
load
PWM
5 V pulse
IO
CGND
GH
GL
Note: PIN = IIN × VIN + ICIN × VCIN
POUT = IO × VO
Average Output Voltage
VO
Averaging
circuit
V
Efficiency = POUT / PIN
PLOSS(DrMOS) = PIN – POUT
Ta = 27°C
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 9 of 17
R2J20655NP
Preliminary
Typical Data
Power Loss vs. Output Current
VIN = 12 V
VCIN = Reg5V = 5 V
VOUT = 1.3 V
Power Loss vs. Input Voltage
9
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VCIN = Reg5V = 5 V
VOUT = 1.3 V
PWM = 600 kHz
L = 0.45 μH
IOUT = 25 A
8
7
6
5
4
3
2
1
0
f
f
PWM = 600 kHz
L = 0.45 μH
0
5
10
15
20
25
30
35
4
6
8
10 12 14 16 18 20 22
Input Voltage (V)
Output Current (A)
Power Loss vs. Output Voltage
Power Loss vs. Switching Frequency
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VIN = 12 V
VCIN = Reg5V = 5 V
PWM = 600 kHz
L = 0.45 μH
IOUT = 25 A
VIN = 12 V
VCIN = Reg5V = 5 V
VOUT = 1.3 V
L = 0.45 μH
f
IOUT = 25 A
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
250
500
750
1000
1250
Output Voltage (V)
Switching Frequency (kHz)
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 10 of 17
R2J20655NP
Preliminary
Typical Data (cont.)
Power Loss vs. Output Inductance
Power Loss vs. VCIN
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
VIN = 12 V
VCIN = Reg5V = 5 V
VOUT = 1.3 V
VIN = 12 V
VOUT = 1.3 V
PWM = 600 kHz
L = 0.45 μH
IOUT = 25 A
f
f
PWM = 600 kHz
IOUT = 25 A
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
4.5
5.0
5.5
6.0
Output Inductance (μH)
VCIN = Reg5V (V)
Average ICIN vs. Switching Frequency
70
VIN = 12 V
VCIN = Reg5V = 5 V
VOUT = 1.3 V
L = 0.45 μH
60
50
40
30
20
10
IOUT = 0 A
250
500
750
1000
1250
Switching Frequency (kHz)
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 11 of 17
R2J20655NP
Preliminary
Description of Operation
The DrMOS multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a
single QFN package. Since the parasitic inductance between each chip is extremely small, the module is highly suitable
for use in buck converters to be operated at high frequencies. The control timing between the high-side MOS FET, low-
side MOS FET, and driver is optimized so that high efficiency can be obtained at low output-voltage.
VCIN & DISBL#
The VCIN pin is connected to the UVL (under-voltage lockout) module, so that the built-in 5 V regulator is disabled as
long as VCIN is 7.4 V or less. On cancellation of UVL, the built-in 5 V regulator remains enabled until the UVL input
is driven to 7.0 V or less.
The built-in 5 V regulator is a series regulator with temperature compensation. A ceramic capacitor with a value of 0.1
F or more must be connected between the CGND plane and the Reg5V pin.
The output of 5 V regulator is monitored by the internal Supervisor circuits. When the Supervisor detects this output is
more than 4.3 V (typ.), the driver state becomes active (figure 1.1). Supervisor circuit has hysteresis and its shutdown
level of Supervisor is 3.8 V (typ.).
Figure 1.2 shows the application when the external 5 V regulator is used. When the Reg5V pin is applied into external 5
V, the Supervisor can activate the driver. In this application usage, VCIN should be connected to Reg5V.
The signal on pin DISBL# also enables or disables the circuit. When UVL disables the circuit , the built-in 5 V
regulator does not operate, but when the signal on DISBL# disables the circuit, only output-pulse generation is
terminated, and the 5 V regulator is not disabled.
Voltages from –0.3 V to VCIN+0.3 V can be applied to the DISBL# pin, so on/off control by a logic IC or the use of a
resistor, etc., to pull the DISBL# line up to VCIN are both possible.
VCIN
DISBL#
REG5V
0
Driver State
Disable (GL, GH = L)
Disable (GL, GH = L)
Active
L
L
H
H
H
Active
Active
Active
H
Open
Disable (GL, GH = L)
12 V
VCIN
VCIN > 7.4 V
Reg5V
VCIN
5 V
IN
IN
Reg5V
UVL &
5 V Regulator
UVL &
5 V Regulator
External 5 V
To Internal
Logic
To Internal
Logic
Supervisor
Supervisor
Figure 1.1 Typical 12 V Input Application
(Activate Built-in 5 V Regulator)
Figure 1.2 External 5 V Application
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 12 of 17
R2J20655NP
Preliminary
PWM & LSDBL#
The PWM pin is the signal input pin for the driver chip. When the PWM input is high, the gate of the high-side MOS
FET (GH) is high and the gate of the low-side MOS FET (GL) is low.
PWM
GH
L
GL
H
L
H
H
L
The LSDBL# pin is the Low Side Gate Disable pin for "Discontinuous Conduction Mode (DCM)" when LSDBL# is
low.
Figure 2 shows the Typical high side and low side gate switching and Inductor current (IL) during "Continuous
Conduction Mode (CCM)" and low side gate disabled when asserting LSDBL# signal.
This pin is internally pulled up to Reg5V with 160 k resistor.
When low side disable function is not used, keep this pin open or pulled up to VCIN.
CCM Operation (LSDBL# = "H" or Open mode)
IL
GH
GL
Figure 2.1 Typical Signals during CCM
DCM Operation (LSDBL# = "L")
IL
0 A
GH
GL
Figure 2.2 Typical Signals during DCM
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 13 of 17
R2J20655NP
Preliminary
The PWM input is TTL level and has hysteresis. When the signal route from the control IC is high impedance, the tri-
state function turns off the high- and low-side MOS FETs. This function operates when the PWM input signal stays in
the input hysteresis window for 150ns (typ.). After the tri-state mode has been entered and GH and GL have become
low, a PWM input voltage of 2.6 V or more is required to make the circuit return to normal operation.
150 ns (tHOLD-OFF
)
150 ns (tHOLD-OFF)
2.0 V
1.4 V
PWM
GH
GL
150 ns (tHOLD-OFF
)
150 ns (tHOLD-OFF)
2.0 V
1.4 V
PWM
GH
GL
Figure 3 PWM Shutdown-Hold Time Signal
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 14 of 17
R2J20655NP
Preliminary
The equivalent circuit for the PWM-pin input is shown in the next figure. M1 is in the ON state during normal
operation; after the PWM input signal has stayed in the hysteresis window for 150 ns (typ.) and the tri-state detection
signal has been driven high, the transistor M1 is turned off.
When VCIN is powered up, M1 is started in the OFF state regardless of PWM Low or Open state. After PWM is
asserted high signal, M1 becomes ON and shifts to normal operation.
Reg5V
M1
25 k
Tri-state
PWM Pin
detection signal
Input
Logic
To internal control
12.5 k
Figure 4 Equivalent Circuit for the PWM-pin Input
THWN & THDN
This device has two level thermal detection, one is thermal warning and the other is thermal shutdown function.
This Thermal Warning feature is the indication of the high temperature status.
THWN is an open drain logic output signal and need to connect a pull-up resistor (ex.51 k) to THWN for Systems
with the thermal warning implementation.
When the chip temperature of the internal driver IC becomes over 115°C, Thermal warning function operates.
This signal is only indication for the system controller and does not disable DrMOS operation.
When thermal warning function is not used, keep this pin open.
Thermal
warning
"H"
Normal
THWN output
Logic Level
operating
"L"
TIC (°C)
100 115
Figure 5 THWN Trigger Temperature
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 15 of 17
R2J20655NP
Preliminary
THDN is an internal thermal shutdown signal when driver IC becomes over 150°C.
This function makes High Side MOS FET and Low Side MOS FET turn off for the device protection from abnormal
high temperature situation and at the same time DISBL# pin is pulled low internally to give notice to the system
controller. Once thermal shutdown function operates, driver IC keeps DISBL# pin pulled low until VCIN becomes
under UVL level (or under supervisor shutdown level).
Figure 6 shows the example of two types of DISBL# connection with the system controller signal.
Driver IC Temp.
< 150°C
> 150°C
Driver Chip Status
Enable (GL, GH = "Active")
Shutdown (GL, GH = "L")
5 V
10 k
To Internal
Logic
To Internal
Logic
DISBL#
DISBL#
10 k
2 μA
2 μA
To shutdown signal
ON/OFF signal
Thermal
Shutdown
Detection
Thermal
Shutdown
Detection
Figure 6.1 THDN Signal to the System Controller
Figure 6.2 ON/OFF Signal from the System Controller
MOS FET
The MOS FETs incorporated in R2J20655NP are highly suitable for synchronous-rectification buck conversion. For the
high-side MOS FET, the drain is connected to the VIN pin and the source is connected to the VSWH pin. For the low-
side MOS FET, the drain is connected to the VSWH pin and the source is connected to the PGND pin.
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 16 of 17
R2J20655NP
Preliminary
Package Dimensions
JEITA Package Code
RENESAS Code
Previous Code
—
MASS[Typ.]
—
P-HVQFN40-p-0606-0.50
PVQN0040KE-A
HD
D
HD/2
D /2
4-C0.50
B
B
1pin
1pin
INDEX
40
40
2.2
C0.3
A
0.7
0.2
1.95
Dimension in Millimeters
Min Nom Max
5.95 6.00 6.05
5.95 6.00 6.05
Reference
Symbol
2-A section
CAV No.
Die No.
D
E
2.05
1.95
A2 0.87 0.89 0.91
f
—
—
0.20
ZD
A
0.865 0.91 0.95
X 4
e
X 4
t
S AB
A1 0.005 0.02 0.04
0.17 0.22 0.27
b1 0.16 0.20 0.24
0.50
Lp 0.40 0.50 0.60
f
S AB
b
b
x
S AB
y1
S
e
—
—
L1
x
y
y1
t
—
—
—
—
—
—
—
—
0.05
0.05
0.20
0.20
S
HD 6.15 6.20 6.25
HE 6.15 6.20 6.25
y
S
Lp
ZD
ZE
—
—
0.75
0.75
—
—
L1 0.06 0.10 0.14
c1 0.17 0.20 0.23
c2 0.17 0.22 0.27
Ordering Information
Part Name
Quantity
Shipping Container
Taping Reel
R2J20655NP#G0
2500 pcs
R07DS0200EJ0100 Rev.1.00
Jan 25, 2011
Page 17 of 17
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