R5F10RF8 [RENESAS]
PG-FP5;型号: | R5F10RF8 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | PG-FP5 |
文件: | 总202页 (文件大小:1740K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Datasheet
R01DS0131EJ0330
Rev.3.30
RL78/G13
RENESAS MCU
Mar 31, 2016
True Low Power Platform (as low as 66 µA/MHz, and 0.57 µA for RTC + LVD), 1.6 V to 5.5 V
operation, 16 to 512 Kbyte Flash, 41 DMIPS at 32 MHz, for General Purpose Applications
1. OUTLINE
1.1 Features
Ultra-low power consumption technology
VDD = single power supply voltage of 1.6 to 5.5 V
HALT mode
DMA (Direct Memory Access) controller
2/4 channels
Number of clocks during transfer between 8/16-bit
SFR and internal RAM: 2 clocks
STOP mode
SNOOZE mode
Multiplier and divider/multiply-accumulator
16 bits × 16 bits = 32 bits (Unsigned or signed)
32 bits ÷ 32 bits = 32 bits (Unsigned)
16 bits × 16 bits + 32 bits = 32 bits (Unsigned or
signed)
RL78 CPU core
CISC architecture with 3-stage pipeline
Minimum instruction execution time: Can be changed
from high speed (0.03125 μs: @ 32 MHz operation
with high-speed on-chip oscillator) to ultra-low speed
(30.5 μs: @ 32.768 kHz operation with subsystem
clock)
Address space: 1 MB
General-purpose registers: (8-bit register × 8) × 4
banks
Serial interface
CSI: 2 to 8 channels
UART/UART (LIN-bus supported):2 to 4 channels
I2C/Simplified I2C communication: 2 to 8 channels
Timer
On-chip RAM: 2 to 32 KB
16-bit timer: 8 to 16 channels
12-bit interval timer: 1 channel
Code flash memory
Code flash memory: 16 to 512 KB
Block size: 1 KB
Prohibition of block erase and rewriting (security
function)
On-chip debug function
Self-programming (with boot swap function/flash
shield window function)
Real-time clock:
1 channel (calendar for 99
years, alarm function, and
clock correction function)
1 channel (operable with the
dedicated low-speed on-chip
oscillator)
Watchdog timer:
A/D converter
8/10-bit resolution A/D converter (VDD = 1.6 to 5.5 V)
Analog input: 6 to 26 channels
Data Flash Memory
Data flash memory: 4 KB to 8 KB
Back ground operation (BGO): Instructions can be
executed from the program memory while rewriting
the data flash memory.
Number of rewrites: 1,000,000 times (TYP.)
Voltage of rewrites: VDD = 1.8 to 5.5 V
Internal reference voltage (1.45 V) and temperature
sensor Note 1
I/O port
I/O port: 16 to 120 (N-ch open drain I/O [withstand
voltage of 6 V]: 0 to 4, N-ch open drain I/O
[VDD withstand voltage Note 2/EVDD withstand
voltage Note 3]: 5 to 25)
Can be set to N-ch open drain, TTL input buffer, and
on-chip pull-up resistor
High-speed on-chip oscillator
Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8
MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz
High accuracy: +/- 1.0 % (VDD = 1.8 to 5.5 V, TA = -20
to +85°C)
Different potential interface: Can connect to a
1.8/2.5/3 V device
On-chip key interrupt function
On-chip clock output/buzzer output controller
Operating ambient temperature
TA = -40 to +85°C (A: Consumer applications, D:
Industrial applications )
Others
TA = -40 to +105°C (G: Industrial applications)
On-chip BCD (binary-coded decimal) correction
circuit
Power management and reset function
On-chip power-on-reset (POR) circuit
On-chip voltage detector (LVD) (Select interrupt and
reset from 14 levels)
Notes 1. Can be selected only in HS (high-speed
main) mode
2. Products with 20 to 52 pins
3. Products with 64 to 128 pins
Remark The functions mounted depend on the
product. See 1.6 Outline of Functions.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 1 of 196
RL78/G13
1. OUTLINE
ROM, RAM capacities
Flash
ROM
Data
RAM
RL78/G13
flash
8 KB
20 pins
24 pins
25 pins
30 pins
32 pins
36 pins
128
KB
12
R5F100AG
R5F101AG
R5F100BG
R5F101BG
R5F100CG
R5F101CG
KB
96
8 KB
8 KB
R5F100AF
R5F101AF
R5F100BF
R5F101BF
R5F100CF
R5F101CF
KB
64
4 KB
4 KB
Note
R5F1006E
R5F1016E
R5F1007E
R5F1017E
R5F1008E
R5F1018E
R5F100AE
R5F101AE
R5F100BE
R5F101BE
R5F100CE
R5F101CE
KB
48
4 KB
3 KB
Note
R5F1006D
R5F1016D
R5F1007D
R5F1017D
R5F1008D
R5F1018D
R5F100AD
R5F101AD
R5F100BD
R5F101BD
R5F100CD
R5F101CD
KB
32
4 KB
2 KB
2 KB
R5F1006C
R5F1016C
R5F1007C
R5F1017C
R5F1008C
R5F1018C
R5F100AC
R5F101AC
R5F100BC
R5F101BC
R5F100CC
R5F101CC
KB
16
4 KB
R5F1006A
R5F1016A
R5F1007A
R5F1017A
R5F1008A
R5F1018A
R5F100AA
R5F101AA
R5F100BA
R5F101BA
R5F100CA
R5F101CA
KB
Flash
ROM
Data
flash
RAM
RL78/G13
40 pins
44 pins
48 pins
52 pins
64 pins
80 pins
100 pins
128 pins
512
KB
8 KB 32 KB
R5F100FL R5F100GL R5F100JL R5F100LL R5F100ML R5F100PL R5F100SL
Note
R5F101FL R5F101GL R5F101JL R5F101LL R5F101ML R5F101PL R5F101SL
384
KB
8 KB 24 KB
R5F100FK R5F100GK R5F100JK R5F100LK R5F100MK R5F100PK R5F100SK
R5F101FK R5F101GK R5F101JK R5F101LK R5F101MK R5F101PK R5F101SK
256
KB
8 KB 20 KB
R5F100FJ R5F100GJ R5F100JJ R5F100LJ R5F100MJ R5F100PJ R5F100SJ
Note
R5F101FJ R5F101GJ R5F101JJ R5F101LJ R5F101MJ R5F101PJ R5F101SJ
192
KB
8 KB 16 KB R5F100EH R5F100FH R5F100GH R5F100JH R5F100LH R5F100MH R5F100PH R5F100SH
R5F101EH R5F101FH R5F101GH R5F101JH R5F101LH R5F101MH R5F101PH R5F101SH
128
KB
8 KB 12 KB R5F100EG R5F100FG R5F100GG R5F100JG R5F100LG R5F100MG R5F100PG
R5F101EG R5F101FG R5F101GG R5F101JG R5F101LG R5F101MG R5F101PG
R5F100EF R5F100FF R5F100GF R5F100JF R5F100LF R5F100MF R5F100PF
R5F101EF R5F101FF R5F101GF R5F101JF R5F101LF R5F101MF R5F101PF
96
8 KB
8 KB
KB
64
4 KB
4 KB R5F100EE R5F100FE R5F100GE R5F100JE R5F100LE
Note
KB
R5F101EE R5F101FE R5F101GE R5F101JE R5F101LE
R5F100ED R5F100FD R5F100GD R5F100JD R5F100LD
3 KB Note
48
4 KB
KB
R5F101ED R5F101FD R5F101GD R5F101JD R5F101LD
32
4 KB
2 KB R5F100EC R5F100FC R5F100GC R5F100JC R5F100LC
KB
R5F101EC R5F101FC R5F101GC R5F101JC R5F101LC
16
4 KB
2 KB R5F100EA R5F100FA R5F100GA
R5F101EA R5F101FA R5F101GA
KB
Note
The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F100xD, R5F101xD (x = 6 to 8, A to C, E to G, J, L): Start address FF300H
R5F100xE, R5F101xE (x = 6 to 8, A to C, E to G, J, L): Start address FEF00H
R5F100xJ, R5F101xJ (x = F, G, J, L, M, P):
R5F100xL, R5F101xL (x = F, G, J, L, M, P, S):
Start address FAF00H
Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library for
RL78 Family (R20UT2944).
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 2 of 196
RL78/G13
1.2 List of Part Numbers
1. OUTLINE
Figure 1-1. Part Number, Memory Size, and Package of RL78/G13
Part No. R 5 F 1 0 0 L E A x x x F B #V0
Packaging specification
#U0 : Tray (HWQFN,VFBGA,WFLGA)
#V0 : Tray (LFQFP,LQFP,LSSOP)
#W0 : Embossed Tape (HWQFN,VFBGA,WFLGA)
#X0 : Embossed Tape (LFQFP, LQFP, LSSOP)
Package type:
SP: LSSOP, 0.65 mm pitch
FP : LFQFP, 0.80 mm pitch
FA : LFQFP, 0.65 mm pitch
FB : LFQFP, 0.50 mm pitch
NA : HWQFN, 0.50 mm pitch
LA : WFLGA, 0.50 mm pitchNote 1
BG : VFBGA, 0.40 mm pitchNote 1
ROM number (Omitted with blank products)
Fields of application:
A : Consumer applications, operating ambient temperature : -40˚C to +85˚C
D : Industrial applications, operating ambient temperature : -40˚C to +85˚C
G : Industrial applications, operating ambient temperature : -40˚C to +105˚C
ROM capacity:
A : 16 KB
C: 32 KB
D : 48 KB
E: 64 KB
F : 96 KB
G : 128 KB
H : 192 KB
J : 256 KB
K : 384 KBNote 2
L : 512 KBNote 2
Pin count:
6 : 20-pin
7 : 24-pin
8 : 25-pinNote 1
A : 30-pin
B : 32-pin
C : 36-pinNote 1
E: 40-pin
F : 44-pin
G : 48-pin
J : 52-pin
L : 64-pin
M : 80-pin
P : 100-pin
S : 128-pinNote 2
RL78/G13 group
Note 2
Memory type:
F : Flash memory
Renesas MCU
Renesas semiconductor product
Notes 1. Products only for “A: Consumer applications (TA = 40 to +85°C)”, and "G: Industrial applications
(TA = 40 to +105°C)"
2. Products only for “A: Consumer applications (TA = 40 to +85°C)”, and "D: Industrial applications (TA
= 40 to +85°C)"
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 3 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(1/12)
Pin
Package
Data
flash
Fields of
Application Note
Ordering Part Number
count
20 pins
20-pin plastic LSSOP Mounted
(7.62 mm (300), 0.65
mm pitch)
A
R5F1006AASP#V0, R5F1006CASP#V0, R5F1006DASP#V0,
R5F1006EASP#V0
R5F1006AASP#X0, R5F1006CASP#X0, R5F1006DASP#X0,
R5F1006EASP#X0
D
G
A
D
A
D
G
A
D
R5F1006ADSP#V0, R5F1006CDSP#V0, R5F1006DDSP#V0,
R5F1006EDSP#V0
R5F1006ADSP#X0, R5F1006CDSP#X0, R5F1006DDSP#X0,
R5F1006EDSP#X0
R5F1006AGSP#V0, R5F1006CGSP#V0, R5F1006DGSP#V0,
R5F1006EGSP#V0
R5F1006AGSP#X0, R5F1006CGSP#X0, R5F1006DGSP#X0,
R5F1006EGSP#X0
Not
R5F1016AASP#V0, R5F1016CASP#V0, R5F1016DASP#V0,
R5F1016EASP#V0
mounted
R5F1016AASP#X0, R5F1016CASP#X0, R5F1016DASP#X0,
R5F1016EASP#X0
R5F1016ADSP#V0, R5F1016CDSP#V0, R5F1016DDSP#V0,
R5F1016EDSP#V0
R5F1016ADSP#X0, R5F1016CDSP#X0, R5F1016DDSP#X0,
R5F1016EDSP#X0
24 pins
24-pin plastic
Mounted
R5F1007AANA#U0, R5F1007CANA#U0, R5F1007DANA#U0,
R5F1007EANA#U0
HWQFN (4 4mm,
0.5 mm pitch)
R5F1007AANA#W0, R5F1007CANA#W0, R5F1007DANA#W0,
R5F1007EANA#W0
R5F1007ADNA#U0, R5F1007CDNA#U0, R5F1007DDNA#U0,
R5F1007EDNA#U0
R5F1007ADNA#W0, R5F1007CDNA#W0, R5F1007DDNA#W0,
R5F1007EDNA#W0
R5F1007AGNA#U0, R5F1007CGNA#U0, R5F1007DGNA#U0,
R5F1007EGNA#U0
R5F1007AGNA#W0, R5F1007CGNA#W0, R5F1007DGNA#W0,
R5F1007EGNA#W0
Not
R5F1017AANA#U0, R5F1017CANA#U0, R5F1017DANA#U0,
R5F1017EANA#U0
mounted
R5F1017AANA#W0, R5F1017CANA#W0, R5F1017DANA#W0,
R5F1017EANA#W0
R5F1017ADNA#U0, R5F1017CDNA#U0, R5F1017DDNA#U0,
R5F1017EDNA#U0
R5F1017ADNA#W0, R5F1017CDNA#W0, R5F1017DDNA#W0,
R5F1017EDNA#W0
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 4 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(2/12)
Pin
Package
Data
Fields of
Ordering Part Number
count
flash
Application
Note
A
R5F1008AALA#U0, R5F1008CALA#U0, R5F1008DALA#U0,
R5F1008EALA#U0
R5F1008AALA#W0, R5F1008CALA#W0, R5F1008DALA#W0,
R5F1008EALA#W0
25 pins
25-pin plastic
Mounted
WFLGA (3 3 mm,
0.5 mm pitch)
G
A
A
D
G
R5F1008AGLA#U0, R5F1008CGLA#U0, R5F1008DGLA#U0,
R5F1008EGLA#U0
R5F1008AGLA#W0, R5F1008CGLA#W0, R5F1008DGLA#W0,
R5F1008EGLA#W0
R5F1018AALA#U0, R5F1018CALA#U0, R5F1018DALA#U0,
R5F1018EALA#U0
R5F1018AALA#W0, R5F1018CALA#W0, R5F1018DALA#W0,
R5F1018EALA#W0
Not
mounted
R5F100AAASP#V0, R5F100ACASP#V0, R5F100ADASP#V0,
R5F100AEASP#V0, R5F100AFASP#V0, R5F100AGASP#V0
R5F100AAASP#X0, R5F100ACASP#X0, R5F100ADASP#X0
R5F100AEASP#X0, R5F100AFASP#X0, R5F100AGASP#X0
R5F100AADSP#V0, R5F100ACDSP#V0, R5F100ADDSP#V0,
R5F100AEDSP#V0, R5F100AFDSP#V0, R5F100AGDSP#V0
R5F100AADSP#X0, R5F100ACDSP#X0, R5F100ADDSP#X0,
R5F100AEDSP#X0, R5F100AFDSP#X0, R5F100AGDSP#X0
R5F100AAGSP#V0, R5F100ACGSP#V0,
30 pins
30-pin plastic LSSOP Mounted
(7.62 mm (300), 0.65
mm pitch)
R5F100ADGSP#V0,R5F100AEGSP#V0,
R5F100AFGSP#V0, R5F100AGGSP#V0
R5F100AAGSP#X0, R5F100ACGSP#X0,
R5F100ADGSP#X0,R5F100AEGSP#X0,
R5F100AFGSP#X0, R5F100AGGSP#X0
A
D
A
D
G
A
D
R5F101AAASP#V0, R5F101ACASP#V0, R5F101ADASP#V0,
R5F101AEASP#V0, R5F101AFASP#V0, R5F101AGASP#V0
R5F101AAASP#X0, R5F101ACASP#X0, R5F101ADASP#X0,
R5F101AEASP#X0, R5F101AFASP#X0, R5F101AGASP#X0
R5F101AADSP#V0, R5F101ACDSP#V0, R5F101ADDSP#V0,
R5F101AEDSP#V0, R5F101AFDSP#V0, R5F101AGDSP#V0
R5F101AADSP#X0, R5F101ACDSP#X0, R5F101ADDSP#X0,
R5F101AEDSP#X0, R5F101AFDSP#X0, R5F101AGDSP#X0
R5F100BAANA#U0, R5F100BCANA#U0, R5F100BDANA#U0,
R5F100BEANA#U0, R5F100BFANA#U0, R5F100BGANA#U0
R5F100BAANA#W0, R5F100BCANA#W0, R5F100BDANA#W0,
R5F100BEANA#W0, R5F100BFANA#W0, R5F100BGANA#W0
R5F100BADNA#U0, R5F100BCDNA#U0, R5F100BDDNA#U0,
R5F100BEDNA#U0, R5F100BFDNA#U0, R5F100BGDNA#U0
R5F100BADNA#W0, R5F100BCDNA#W0, R5F100BDDNA#W0,
R5F100BEDNA#W0, R5F100BFDNA#W0, R5F100BGDNA#W0
R5F100BAGNA#U0, R5F100BCGNA#U0, R5F100BDGNA#U0,
R5F100BEGNA#U0, R5F100BFGNA#U0, R5F100BGGNA#U0
R5F100BAGNA#W0, R5F100BCGNA#W0, R5F100BDGNA#W0,
R5F100BEGNA#W0, R5F100BFGNA#W0, R5F100BGGNA#W0
R5F101BAANA#U0, R5F101BCANA#U0, R5F101BDANA#U0,
R5F101BEANA#U0, R5F101BFANA#U0, R5F101BGANA#U0
R5F101BAANA#W0, R5F101BCANA#W0, R5F101BDANA#W0,
R5F101BEANA#W0, R5F101BFANA#W0, R5F101BGANA#W0
R5F101BADNA#U0, R5F101BCDNA#U0, R5F101BDDNA#U0,
R5F101BEDNA#U0, R5F101BFDNA#U0, R5F101BGDNA#U0
R5F101BADNA#W0, R5F101BCDNA#W0, R5F101BDDNA#W0,
R5F101BEDNA#W0, R5F101BFDNA#W0, R5F101BGDNA#W0
Not
mounted
32 pins
32-pin plastic
Mounted
HWQFN (5 5 mm,
0.5 mm pitch)
Not
mounted
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 5 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(3/12)
Pin
Package
Data flash
Fields of
Ordering Part Number
count
Application
Note
36 pins
36-pin plastic WFLGA
(4 4 mm, 0.5 mm
pitch)
Mounted
A
R5F100CAALA#U0, R5F100CCALA#U0, R5F100CDALA#U0,
R5F100CEALA#U0, R5F100CFALA#U0, R5F100CGALA#U0
R5F100CAALA#W0, R5F100CCALA#W0, R5F100CDALA#W0,
R5F100CEALA#W0, R5F100CFALA#W0, R5F100CGALA#W0
R5F100CAGLA#U0, R5F100CCGLA#U0, R5F100CDGLA#U0,
R5F100CEGLA#U0, R5F100CFGLA#U0, R5F100CGGLA#U0
R5F100CAGLA#W0, R5F100CCGLA#W0, R5F100CDGLA#W0,
R5F100CEGLA#W0, R5F100CFGLA#W0, R5F100CGGLA#W0
R5F101CAALA#U0, R5F101CCALA#U0, R5F101CDALA#U0,
R5F101CEALA#U0, R5F101CFALA#U0, R5F101CGALA#U0
R5F101CAALA#W0, R5F101CCALA#W0, R5F101CDALA#W0,
R5F101CEALA#W0, R5F101CFALA#W0, R5F101CGALA#W0
G
A
A
Not
mounted
40 pins
40-pin plastic HWQFN
(6 6 mm, 0.5 mm
pitch)
Mounted
R5F100EAANA#U0, R5F100ECANA#U0, R5F100EDANA#U0,
R5F100EEANA#U0, R5F100EFANA#U0, R5F100EGANA#U0,
R5F100EHANA#U0
R5F100EAANA#W0, R5F100ECANA#W0, R5F100EDANA#W0,
R5F100EEANA#W0, R5F100EFANA#W0, R5F100EGANA#W0,
R5F100EHANA#W0
D
G
A
D
R5F100EADNA#U0, R5F100ECDNA#U0, R5F100EDDNA#U0,
R5F100EEDNA#U0, R5F100EFDNA#U0, R5F100EGDNA#U0,
R5F100EHDNA#U0
R5F100EADNA#W0, R5F100ECDNA#W0,
R5F100EDDNA#W0, R5F100EEDNA#W0, R5F100EFDNA#W0,
R5F100EGDNA#W0, R5F100EHDNA#W0
R5F100EAGNA#U0, R5F100ECGNA#U0, R5F100EDGNA#U0,
R5F100EEGNA#U0, R5F100EFGNA#U0, R5F100EGGNA#U0,
R5F100EHGNA#U0
R5F100EAGNA#W0, R5F100ECGNA#W0,
R5F100EDGNA#W0, R5F100EEGNA#W0,
R5F100EFGNA#W0, R5F100EGGNA#W0, R5F100EHGNA#W0
R5F101EAANA#U0, R5F101ECANA#U0, R5F101EDANA#U0,
R5F101EEANA#U0, R5F101EFANA#U0, R5F101EGANA#U0,
R5F101EHANA#U0
Not
mounted
R5F101EAANA#W0, R5F101ECANA#W0, R5F101EDANA#W0,
R5F101EEANA#W0, R5F101EFANA#W0, R5F101EGANA#W0,
R5F101EHANA#W0
R5F101EADNA#U0, R5F101ECDNA#U0, R5F101EDDNA#U0,
R5F101EEDNA#U0, R5F101EFDNA#U0, R5F101EGDNA#U0,
R5F101EHDNA#U0
R5F101EADNA#W0, R5F101ECDNA#W0,
R5F101EDDNA#W0, R5F101EEDNA#W0, R5F101EFDNA#W0,
R5F101EGDNA#W0, R5F101EHDNA#W0
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 6 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(4/12)
Pin
Package
Data flash
Fields of
Ordering Part Number
count
Application
Note
44 pins
44-pin plastic LQFP
(10 10 mm, 0.8 mm
pitch)
Mounted
A
R5F100FAAFP#V0, R5F100FCAFP#V0, R5F100FDAFP#V0,
R5F100FEAFP#V0, R5F100FFAFP#V0, R5F100FGAFP#V0,
R5F100FHAFP#V0, R5F100FJAFP#V0, R5F100FKAFP#V0,
R5F100FLAFP#V0
R5F100FAAFP#X0, R5F100FCAFP#X0, R5F100FDAFP#X0,
R5F100FEAFP#X0, R5F100FFAFP#X0, R5F100FGAFP#X0,
R5F100FHAFP#X0, R5F100FJAFP#X0, R5F100FKAFP#X0,
R5F100FLAFP#X0
D
R5F100FADFP#V0, R5F100FCDFP#V0, R5F100FDDFP#V0,
R5F100FEDFP#V0, R5F100FFDFP#V0, R5F100FGDFP#V0,
R5F100FHDFP#V0, R5F100FJDFP#V0, R5F100FKDFP#V0,
R5F100FLDFP#V0
R5F100FADFP#X0, R5F100FCDFP#X0, R5F100FDDFP#X0,
R5F100FEDFP#X0, R5F100FFDFP#X0, R5F100FGDFP#X0,
R5F100FHDFP#X0, R5F100FJDFP#X0, R5F100FKDFP#X0,
R5F100FLDFP#X0
G
R5F100FAGFP#V0, R5F100FCGFP#V0, R5F100FDGFP#V0,
R5F100FEGFP#V0, R5F100FFGFP#V0, R5F100FGGFP#V0,
R5F100FHGFP#V0, R5F100FJGFP#V0
R5F100FAGFP#X0, R5F100FCGFP#X0, R5F100FDGFP#X0,
R5F100FEGFP#X0, R5F100FFGFP#X0, R5F100FGGFP#X0,
R5F100FHGFP#X0, R5F100FJGFP#X0
Not
A
R5F101FAAFP#V0, R5F101FCAFP#V0, R5F101FDAFP#V0,
R5F101FEAFP#V0, R5F101FFAFP#V0, R5F101FGAFP#V0,
R5F101FHAFP#V0, R5F101FJAFP#V0, R5F101FKAFP#V0,
R5F101FLAFP#V0
mounted
R5F101FAAFP#X0, R5F101FCAFP#X0, R5F101FDAFP#X0,
R5F101FEAFP#X0, R5F101FFAFP#X0, R5F101FGAFP#X0,
R5F101FHAFP#X0, R5F101FJAFP#X0, R5F101FKAFP#X0,
R5F101FLAFP#X0
D
R5F101FADFP#V0, R5F101FCDFP#V0, R5F101FDDFP#V0,
R5F101FEDFP#V0, R5F101FFDFP#V0, R5F101FGDFP#V0,
R5F101FHDFP#V0, R5F101FJDFP#V0, R5F101FKDFP#V0,
R5F101FLDFP#V0
R5F101FADFP#X0, R5F101FCDFP#X0, R5F101FDDFP#X0,
R5F101FEDFP#X0, R5F101FFDFP#X0, R5F101FGDFP#X0,
R5F101FHDFP#X0, R5F101FJDFP#X0, R5F101FKDFP#X0,
R5F101FLDFP#X0
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 7 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(5/12)
Pin
Package
Data
Fields of
Ordering Part Number
count
flash
Application
Note
48 pins
48-pin plastic
Mounted
A
R5F100GAAFB#V0, R5F100GCAFB#V0, R5F100GDAFB#V0,
LFQFP (7 7 mm,
0.5 mm pitch)
R5F100GEAFB#V0, R5F100GFAFB#V0, R5F100GGAFB#V0,
R5F100GHAFB#V0, R5F100GJAFB#V0, R5F100GKAFB#V0,
R5F100GLAFB#V0
R5F100GAAFB#X0, R5F100GCAFB#X0, R5F100GDAFB#X0,
R5F100GEAFB#X0, R5F100GFAFB#X0, R5F100GGAFB#X0,
R5F100GHAFB#X0, R5F100GJAFB#X0, R5F100GKAFB#X0,
R5F100GLAFB#X0
D
R5F100GADFB#V0, R5F100GCDFB#V0, R5F100GDDFB#V0,
R5F100GEDFB#V0, R5F100GFDFB#V0, R5F100GGDFB#V0,
R5F100GHDFB#V0, R5F100GJDFB#V0, R5F100GKDFB#V0,
R5F100GLDFB#V0
R5F100GADFB#X0, R5F100GCDFB#X0, R5F100GDDFB#X0,
R5F100GEDFB#X0, R5F100GFDFB#X0, R5F100GGDFB#X0,
R5F100GHDFB#X0, R5F100GJDFB#X0, R5F100GKDFB#X0,
R5F100GLDFB#X0
G
R5F100GAGFB#V0, R5F100GCGFB#V0, R5F100GDGFB#V0,
R5F100GEGFB#V0, R5F100GFGFB#V0, R5F100GGGFB#V0,
R5F100GHGFB#V0, R5F100GJGFB#V0
R5F100GAGFB#X0, R5F100GCGFB#X0, R5F100GDGFB#X0,
R5F100GEGFB#X0, R5F100GFGFB#X0, R5F100GGGFB#X0,
R5F100GHGFB#X0, R5F100GJGFB#X0
Not
A
R5F101GAAFB#V0, R5F101GCAFB#V0, R5F101GDAFB#V0,
R5F101GEAFB#V0, R5F101GFAFB#V0, R5F101GGAFB#V0,
R5F101GHAFB#V0, R5F101GJAFB#V0, R5F101GKAFB#V0,
R5F101GLAFB#V0
mounted
R5F101GAAFB#X0, R5F101GCAFB#X0, R5F101GDAFB#X0,
R5F101GEAFB#X0, R5F101GFAFB#X0, R5F101GGAFB#X0,
R5F101GHAFB#X0, R5F101GJAFB#X0, R5F101GKAFB#X0,
R5F101GLAFB#X0
D
R5F101GADFB#V0, R5F101GCDFB#V0, R5F101GDDFB#V0,
R5F101GEDFB#V0, R5F101GFDFB#V0, R5F101GGDFB#V0,
R5F101GHDFB#V0, R5F101GJDFB#V0, R5F101GKDFB#V0,
R5F101GLDFB#V0
R5F101GADFB#X0, R5F101GCDFB#X0, R5F101GDDFB#X0,
R5F101GEDFB#X0, R5F101GFDFB#X0, R5F101GGDFB#X0,
R5F101GHDFB#X0, R5F101GJDFB#X0, R5F101GKDFB#X0,
R5F101GLDFB#X0
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 8 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(6/12)
Pin count
Package
Data flash
Fields of
Ordering Part Number
Application
Note
48 pins
48-pin plastic
Mounted
A
R5F100GAANA#U0, R5F100GCANA#U0, R5F100GDANA#U0,
HWQFN (7 7 mm,
0.5 mm pitch)
R5F100GEANA#U0, R5F100GFANA#U0, R5F100GGANA#U0,
R5F100GHANA#U0, R5F100GJANA#U0, R5F100GKANA#U0,
R5F100GLANA#U0
R5F100GAANA#W0, R5F100GCANA#W0,
R5F100GDANA#W0, R5F100GEANA#W0,
R5F100GFANA#W0, R5F100GGANA#W0,
R5F100GHANA#W0, R5F100GJANA#W0,
R5F100GKANA#W0, R5F100GLANA#W0
D
R5F100GADNA#U0, R5F100GCDNA#U0, R5F100GDDNA#U0,
R5F100GEDNA#U0, R5F100GFDNA#U0, R5F100GGDNA#U0,
R5F100GHDNA#U0, R5F100GJDNA#U0, R5F100GKDNA#U0,
R5F100GLDNA#U0
R5F100GADNA#W0, R5F100GCDNA#W0,
R5F100GDDNA#W0, R5F100GEDNA#W0,
R5F100GFDNA#W0, R5F100GGDNA#W0,
R5F100GHDNA#W0, R5F100GJDNA#W0,
R5F100GKDNA#W0, R5F100GLDNA#W0
G
R5F100GAGNA#U0, R5F100GCGNA#U0, R5F100GDGNA#U0,
R5F100GEGNA#U0, R5F100GFGNA#U0, R5F100GGGNA#U0,
R5F100GHGNA#U0, R5F100GJGNA#U0
R5F100GAGNA#W0, R5F100GCGNA#W0,
R5F100GDGNA#W0, R5F100GEGNA#W0,
R5F100GFGNA#W0, R5F100GGGNA#W0,
R5F100GHGNA#W0, R5F100GJGNA#W0
Not
A
R5F101GAANA#U0, R5F101GCANA#U0, R5F101GDANA#U0,
R5F101GEANA#U0, R5F101GFANA#U0, R5F101GGANA#U0,
R5F101GHANA#U0, R5F101GJANA#U0, R5F101GKANA#U0,
R5F101GLANA#U0
mounted
R5F101GAANA#W0, R5F101GCANA#W0,
R5F101GDANA#W0, R5F101GEANA#W0,
R5F101GFANA#W0, R5F101GGANA#W0,
R5F101GHANA#W0, R5F101GJANA#W0,
R5F101GKANA#W0, R5F101GLANA#W0
D
R5F101GADNA#U0, R5F101GCDNA#U0, R5F101GDDNA#U0,
R5F101GEDNA#U0, R5F101GFDNA#U0, R5F101GGDNA#U0,
R5F101GHDNA#U0, R5F101GJDNA#U0, R5F101GKDNA#U0,
R5F101GLDNA#U0
R5F101GADNA#W0, R5F101GCDNA#W0,
R5F101GDDNA#W0, R5F101GEDNA#W0,
R5F101GFDNA#W0, R5F101GGDNA#W0,
R5F101GHDNA#W0, R5F101GJDNA#W0,
R5F101GKDNA#W0, R5F101GLDNA#W0
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 9 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(7/12)
Pin
Package
Data
flash
Fields of
Ordering Part Number
count
Application
Note
52 pins
52-pin plastic
LQFP (10 10
mm, 0.65 mm
pitch)
Mounted
A
D
G
A
D
R5F100JCAFA#V0, R5F100JDAFA#V0, R5F100JEAFA#V0,
R5F100JFAFA#V0, R5F100JGAFA#V0, R5F100JHAFA#V0,
R5F100JJAFA#V0, R5F100JKAFA#V0, R5F100JLAFA#V0
R5F100JCAFA#X0, R5F100JDAFA#X0, R5F100JEAFA#X0,
R5F100JFAFA#X0, R5F100JGAFA#X0, R5F100JHAFA#X0,
R5F100JJAFA#X0, R5F100JKAFA#X0, R5F100JLAFA#X0
R5F100JCDFA#V0, R5F100JDDFA#V0, R5F100JEDFA#V0,
R5F100JFDFA#V0, R5F100JGDFA#V0, R5F100JHDFA#V0,
R5F100JJDFA#V0, R5F100JKDFA#V0, R5F100JLDFA#V0
R5F100JCDFA#X0, R5F100JDDFA#X0, R5F100JEDFA#X0,
R5F100JFDFA#X0, R5F100JGDFA#X0, R5F100JHDFA#X0,
R5F100JJDFA#X0, R5F100JKDFA#X0, R5F100JLDFA#X0
R5F100JCGFA#V0, R5F100JDGFA#V0, R5F100JEGFA#V0,
R5F100JFGFA#V0,R5F100JGGFA#V0, R5F100JHGFA#V0,
R5F100JJGFA#V0
R5F100JCGFA#X0, R5F100JDGFA#X0, R5F100JEGFA#X0,
R5F100JFGFA#X0,R5F100JGGFA#X0, R5F100JHGFA#X0,
R5F100JJGFA#X0
Not
R5F101JCAFA#V0, R5F101JDAFA#V0, R5F101JEAFA#V0,
R5F101JFAFA#V0, R5F101JGAFA#V0, R5F101JHAFA#V0,
R5F101JJAFA#V0, R5F101JKAFA#V0, R5F101JLAFA#V0
R5F101JCAFA#X0, R5F101JDAFA#X0, R5F101JEAFA#X0,
R5F101JFAFA#X0, R5F101JGAFA#X0, R5F101JHAFA#X0,
R5F101JJAFA#X0, R5F101JKAFA#X0, R5F101JLAFA#X0
R5F101JCDFA#V0, R5F101JDDFA#V0, R5F101JEDFA#V0,
R5F101JFDFA#V0, R5F101JGDFA#V0, R5F101JHDFA#V0,
R5F101JJDFA#V0, R5F101JKDFA#V0, R5F101JLDFA#V0
R5F101JCDFA#X0, R5F101JDDFA#X0, R5F101JEDFA#X0,
R5F101JFDFA#X0, R5F101JGDFA#X0, R5F101JHDFA#X0,
R5F101JJDFA#X0, R5F101JKDFA#X0, R5F101JLDFA#X0
mounted
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 10 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(8/12)
Pin count
Package
Data flash
Fields of
Application Note
Ordering Part Number
64 pins
64-pin plastic LQFP
(12 12 mm, 0.65
mm pitch)
Mounted
A
D
G
R5F100LCAFA#V0, R5F100LDAFA#V0,
R5F100LEAFA#V0, R5F100LFAFA#V0,
R5F100LGAFA#V0, R5F100LHAFA#V0,
R5F100LJAFA#V0, R5F100LKAFA#V0, R5F100LLAFA#V0
R5F100LCAFA#X0, R5F100LDAFA#X0,
R5F100LEAFA#X0, R5F100LFAFA#X0,
R5F100LGAFA#X0, R5F100LHAFA#X0,
R5F100LJAFA#X0, R5F100LKAFA#X0, R5F100LLAFA#X0
R5F100LCDFA#V0, R5F100LDDFA#V0,
R5F100LEDFA#V0, R5F100LFDFA#V0,
R5F100LGDFA#V0, R5F100LHDFA#V0,
R5F100LJDFA#V0, R5F100LKDFA#V0, R5F100LLDFA#V0
R5F100LCDFA#X0, R5F100LDDFA#X0,
R5F100LEDFA#X0, R5F100LFDFA#X0,
R5F100LGDFA#X0, R5F100LHDFA#X0,
R5F100LJDFA#X0, R5F100LKDFA#X0, R5F100LLDFA#X0
R5F100LCGFA#V0, R5F100LDGFA#V0,
R5F100LEGFA#V0, R5F100LFGFA#V0
R5F100LCGFA#X0, R5F100LDGFA#X0,
R5F100LEGFA#X0, R5F100LFGFA#X0
R5F100LGGFA#V0, R5F100LHGFA#V0,
R5F100LJGFA#V0
R5F100LGGFA#X0, R5F100LHGFA#X0,
R5F100LJGFA#X0
Not
A
R5F101LCAFA#V0, R5F101LDAFA#V0,
R5F101LEAFA#V0, R5F101LFAFA#V0,
R5F101LGAFA#V0, R5F101LHAFA#V0,
R5F101LJAFA#V0, R5F101LKAFA#V0, R5F101LLAFA#V0
R5F101LCAFA#X0, R5F101LDAFA#X0,
R5F101LEAFA#X0, R5F101LFAFA#X0,
R5F101LGAFA#X0, R5F101LHAFA#X0,
R5F101LJAFA#X0, R5F101LKAFA#X0, R5F101LLAFA#X0
R5F101LCDFA#V0, R5F101LDDFA#V0,
R5F101LEDFA#V0, R5F101LFDFA#V0,
R5F101LGDFA#V0, R5F101LHDFA#V0,
R5F101LJDFA#V0, R5F101LKDFA#V0, R5F101LLDFA#V0
R5F101LCDFA#X0, R5F101LDDFA#X0,
R5F101LEDFA#X0, R5F101LFDFA#X0,
R5F101LGDFA#X0, R5F101LHDFA#X0,
R5F101LJDFA#X0, R5F101LKDFA#X0, R5F101LLDFA#X0
mounted
D
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 11 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(9/12)
Pin count
Package
Data flash
Fields of
Ordering Part Number
Application
Note
A
R5F100LCAFB#V0, R5F100LDAFB#V0, R5F100LEAFB#V0,
64 pins
64-pin plastic
Mounted
R5F100LFAFB#V0, R5F100LGAFB#V0, R5F100LHAFB#V0,
R5F100LJAFB#V0, R5F100LKAFB#V0, R5F100LLAFB#V0
R5F100LCAFB#X0, R5F100LDAFB#X0, R5F100LEAFB#X0,
R5F100LFAFB#X0, R5F100LGAFB#X0, R5F100LHAFB#X0,
R5F100LJAFB#X0, R5F100LKAFB#X0, R5F100LLAFB#X0
R5F100LCDFB#V0, R5F100LDDFB#V0, R5F100LEDFB#V0,
R5F100LFDFB#V0, R5F100LGDFB#V0, R5F100LHDFB#V0,
R5F100LJDFB#V0, R5F100LKDFB#V0, R5F100LLDFB#V0
R5F100LCDFB#X0, R5F100LDDFB#X0, R5F100LEDFB#X0,
R5F100LFDFB#X0, R5F100LGDFB#X0, R5F100LHDFB#X0,
R5F100LJDFB#X0, R5F100LKDFB#X0, R5F100LLDFB#X0
R5F100LCGFB#V0, R5F100LDGFB#V0, R5F100LEGFB#V0,
R5F100LFGFB#V0
LFQFP (10 10
mm, 0.5 mm pitch)
D
G
A
D
A
G
A
R5F100LCGFB#X0, R5F100LDGFB#X0, R5F100LEGFB#X0,
R5F100LFGFB#X0
R5F100LGGFB#V0, R5F100LHGFB#V0, R5F100LJGFB#V0
R5F100LGGFB#X0, R5F100LHGFB#X0, R5F100LJGFB#X0
R5F101LCAFB#V0, R5F101LDAFB#V0, R5F101LEAFB#V0,
R5F101LFAFB#V0, R5F101LGAFB#V0, R5F101LHAFB#V0,
R5F101LJAFB#V0, R5F101LKAFB#V0, R5F101LLAFB#V0
R5F101LCAFB#X0, R5F101LDAFB#X0, R5F101LEAFB#X0,
R5F101LFAFB#X0, R5F101LGAFB#X0, R5F101LHAFB#X0,
R5F101LJAFB#X0, R5F101LKAFB#X0, R5F101LLAFB#X0
R5F101LCDFB#V0, R5F101LDDFB#V0, R5F101LEDFB#V0,
R5F101LFDFB#V0, R5F101LGDFB#V0, R5F101LHDFB#V0,
R5F101LJDFB#V0, R5F101LKDFB#V0, R5F101LLDFB#V0
R5F101LCDFB#X0, R5F101LDDFB#X0, R5F101LEDFB#X0,
R5F101LFDFB#X0, R5F101LGDFB#X0, R5F101LHDFB#X0,
R5F101LJDFB#X0, R5F101LKDFB#X0, R5F101LLDFB#X0
R5F100LCABG#U0, R5F100LDABG#U0, R5F100LEABG#U0,
R5F100LFABG#U0, R5F100LGABG#U0, R5F100LHABG#U0,
R5F100LJABG#U0
Not
mounted
64-pin plastic
VFBGA
Mounted
(4 4 mm, 0.4 mm
pitch)
R5F100LCABG#W0, R5F100LDABG#W0, R5F100LEABG#W0,
R5F100LFABG#W0, R5F100LGABG#W0, R5F100LHABG#W0,
R5F100LJABG#W0
R5F100LCGBG#U0, R5F100LDGBG#U0, R5F100LEGBG#U0,
R5F100LFGBG#U0, R5F100LGGBG#U0, R5F100LHGBG#U0,
R5F100LJGBG#U0
R5F100LCGBG#W0, R5F100LDGBG#W0, R5F100LEGBG#W0,
R5F100LFGBG#W0, R5F100LGGBG#W0, R5F100LHGBG#W0,
R5F100LJGBG#W0
R5F101LCABG#U0, R5F101LDABG#U0, R5F101LEABG#U0,
R5F101LFABG#U0, R5F101LGABG#U0, R5F101LHABG#U0,
R5F101LJABG#U0
Not
mounted
R5F101LCABG#W0, R5F101LDABG#W0, R5F101LEABG#W0,
R5F101LFABG#W0, R5F101LGABG#W0, R5F101LHABG#W0,
R5F101LJABG#W0
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 12 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(10/12)
Pin count
Package
Data flash
Fields of
Ordering Part Number
Application
Note
80 pins
80-pin plastic LQFP
(14 14 mm, 0.65
mm pitch)
Mounted
A
R5F100MFAFA#V0, R5F100MGAFA#V0, R5F100MHAFA#V0,
R5F100MJAFA#V0, R5F100MKAFA#V0, R5F100MLAFA#V0
R5F100MFAFA#X0, R5F100MGAFA#X0, R5F100MHAFA#X0,
R5F100MJAFA#X0, R5F100MKAFA#X0, R5F100MLAFA#X0
R5F100MFDFA#V0, R5F100MGDFA#V0, R5F100MHDFA#V0,
R5F100MJDFA#V0, R5F100MKDFA#V0, R5F100MLDFA#V0
R5F100MFDFA#X0, R5F100MGDFA#X0, R5F100MHDFA#X0,
R5F100MJDFA#X0, R5F100MKDFA#X0, R5F100MLDFA#X0
R5F100MFGFA#V0, R5F100MGGFA#V0, R5F100MHGFA#V0,
R5F100MJGFA#V0
D
G
R5F100MFGFA#X0, R5F100MGGFA#X0, R5F100MHGFA#X0,
R5F100MJGFA#X0
Not
A
D
A
D
G
A
D
R5F101MFAFA#V0, R5F101MGAFA#V0, R5F101MHAFA#V0,
R5F101MJAFA#V0, R5F101MKAFA#V0, R5F101MLAFA#V0
R5F101MFAFA#X0, R5F101MGAFA#X0, R5F101MHAFA#X0,
R5F101MJAFA#X0, R5F101MKAFA#X0, R5F101MLAFA#X0
R5F101MFDFA#V0, R5F101MGDFA#V0, R5F101MHDFA#V0,
R5F101MJDFA#V0, R5F101MKDFA#V0, R5F101MLDFA#V0
R5F101MFDFA#X0, R5F101MGDFA#X0, R5F101MHDFA#X0,
R5F101MJDFA#X0, R5F101MKDFA#X0, R5F101MLDFA#X0
R5F100MFAFB#V0, R5F100MGAFB#V0, R5F100MHAFB#V0,
R5F100MJAFB#V0, R5F100MKAFB#V0, R5F100MLAFB#V0
R5F100MFAFB#X0, R5F100MGAFB#X0, R5F100MHAFB#X0,
R5F100MJAFB#X0, R5F100MKAFB#X0, R5F100MLAFB#X0
R5F100MFDFB#V0, R5F100MGDFB#V0, R5F100MHDFB#V0,
R5F100MJDFB#V0, R5F100MKDFB#V0, R5F100MLDFB#V0
R5F100MFDFB#X0, R5F100MGDFB#X0, R5F100MHDFB#X0,
R5F100MJDFB#X0, R5F100MKDFB#X0, R5F100MLDFB#X0
R5F100MFGFB#V0, R5F100MGGFB#V0, R5F100MHGFB#V0,
R5F100MJGFB#V0
mounted
80-pin plastic
Mounted
LFQFP (12 12
mm, 0.5 mm pitch)
R5F100MFGFB#X0, R5F100MGGFB#X0, R5F100MHGFB#X0,
R5F100MJGFB#X0
Not
R5F101MFAFB#V0, R5F101MGAFB#V0, R5F101MHAFB#V0,
R5F101MJAFB#V0, R5F101MKAFB#V0, R5F101MLAFB#V0
R5F101MFAFB#X0, R5F101MGAFB#X0, R5F101MHAFB#X0,
R5F101MJAFB#X0, R5F101MKAFB#X0, R5F101MLAFB#X0
R5F101MFDFB#V0, R5F101MGDFB#V0, R5F101MHDFB#V0,
R5F101MJDFB#V0, R5F101MKDFB#V0, R5F101MLDFB#V0
R5F101MFDFB#X0, R5F101MGDFB#X0, R5F101MHDFB#X0,
R5F101MJDFB#X0, R5F101MKDFB#X0, R5F101MLDFB#X0
mounted
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 13 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(11/12)
Pin count
Package
Data flash
Fields of
Ordering Part Number
Application
Note
100 pins
100-pin plastic
Mounted
A
R5F100PFAFB#V0, R5F100PGAFB#V0, R5F100PHAFB#V0,
LFQFP (14 14
mm, 0.5 mm pitch)
R5F100PJAFB#V0, R5F100PKAFB#V0, R5F100PLAFB#V0
R5F100PFAFB#X0, R5F100PGAFB#X0, R5F100PHAFB#X0,
R5F100PJAFB#X0, R5F100PKAFB#X0, R5F100PLAFB#X0
R5F100PFDFB#V0, R5F100PGDFB#V0, R5F100PHDFB#V0,
R5F100PJDFB#V0, R5F100PKDFB#V0, R5F100PLDFB#V0
R5F100PFDFB#X0, R5F100PGDFB#X0, R5F100PHDFB#X0,
R5F100PJDFB#X0, R5F100PKDFB#X0, R5F100PLDFB#X0
R5F100PFGFB#V0, R5F100PGGFB#V0, R5F100PHGFB#V0,
R5F100PJGFB#V0
D
G
A
D
A
D
G
A
D
R5F100PFGFB#X0, R5F100PGGFB#X0, R5F100PHGFB#X0,
R5F100PJGFB#X0
Not
R5F101PFAFB#V0, R5F101PGAFB#V0, R5F101PHAFB#V0,
R5F101PJAFB#V0, R5F101PKAFB#V0, R5F101PLAFB#V0
R5F101PFAFB#X0, R5F101PGAFB#X0, R5F101PHAFB#X0,
R5F101PJAFB#X0, R5F101PKAFB#X0, R5F101PLAFB#X0
R5F101PFDFB#V0, R5F101PGDFB#V0, R5F101PHDFB#V0,
R5F101PJDFB#V0, R5F101PKDFB#V0, R5F101PLDFB#V0
R5F101PFDFB#X0, R5F101PGDFB#X0, R5F101PHDFB#X0,
R5F101PJDFB#X0, R5F101PKDFB#X0, R5F101PLDFB#X0
R5F100PFAFA#V0, R5F100PGAFA#V0, R5F100PHAFA#V0,
R5F100PJAFA#V0, R5F100PKAFA#V0, R5F100PLAFA#V0
R5F100PFAFA#X0, R5F100PGAFA#X0, R5F100PHAFA#X0,
R5F100PJAFA#X0, R5F100PKAFA#X0, R5F100PLAFA#X0
R5F100PFDFA#V0, R5F100PGDFA#V0, R5F100PHDFA#V0,
R5F100PJDFA#V0, R5F100PKDFA#V0, R5F100PLDFA#V0
R5F100PFDFA#X0, R5F100PGDFA#X0, R5F100PHDFA#X0,
R5F100PJDFA#X0, R5F100PKDFA#X0, R5F100PLDFA#X0
R5F100PFGFA#V0, R5F100PGGFA#V0, R5F100PHGFA#V0,
R5F100PJGFA#V0
mounted
100-pin plastic
Mounted
LQFP (14 20 mm,
0.65 mm pitch)
R5F100PFGFA#X0, R5F100PGGFA#X0, R5F100PHGFA#X0,
R5F100PJGFA#X0
Not
R5F101PFAFA#V0, R5F101PGAFA#V0, R5F101PHAFA#V0,
R5F101PJAFA#V0, R5F101PKAFA#V0, R5F101PLAFA#V0
R5F101PFAFA#X0, R5F101PGAFA#X0, R5F101PHAFA#X0,
R5F101PJAFA#X0, R5F101PKAFA#X0, R5F101PLAFA#X0
R5F101PFDFA#V0, R5F101PGDFA#V0, R5F101PHDFA#V0,
R5F101PJDFA#V0, R5F101PKDFA#V0, R5F101PLDFA#V0
R5F101PFDFA#X0, R5F101PGDFA#X0, R5F101PHDFA#X0,
R5F101PJDFA#X0, R5F101PKDFA#X0, R5F101PLDFA#X0
mounted
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 14 of 196
RL78/G13
1. OUTLINE
Table 1-1. List of Ordering Part Numbers
(12/12)
Pin count
Package
Data flash
Fields of
Application Note
Ordering Part Number
128 pins
128-pin plastic LFQFP Mounted
(14 20 mm, 0.5 mm
pitch)
A
D
A
D
R5F100SHAFB#V0, R5F100SJAFB#V0,
R5F100SKAFB#V0, R5F100SLAFB#V0
R5F100SHAFB#X0, R5F100SJAFB#X0,
R5F100SKAFB#X0, R5F100SLAFB#X0
R5F100SHDFB#V0, R5F100SJDFB#V0,
R5F100SKDFB#V0, R5F100SLDFB#V0
R5F100SHDFB#X0, R5F100SJDFB#X0,
R5F100SKDFB#X0, R5F100SLDFB#X0
R5F101SHAFB#V0, R5F101SJAFB#V0,
R5F101SKAFB#V0, R5F101SLAFB#V0
R5F101SHAFB#X0, R5F101SJAFB#X0,
R5F101SKAFB#X0, R5F101SLAFB#X0
R5F101SHDFB#V0, R5F101SJDFB#V0,
R5F101SKDFB#V0, R5F101SLDFB#V0
R5F101SHDFB#X0, R5F101SJDFB#X0,
R5F101SKDFB#X0, R5F101SLDFB#X0
Not
mounted
Note
For the fields of application, refer to Figure 1-1 Part Number, Memory Size, and Package of RL78/G13.
Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering
part numbers, refer to the target product page of the Renesas Electronics website.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 15 of 196
RL78/G13
1.3 Pin Configuration (Top View)
1. OUTLINE
1.3.1 20-pin products
20-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch)
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P40/TOOL0
1
2
3
4
5
6
7
8
9
10
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P147/ANI18
P10/SCK00/SCL00
P11/SI00/RxD0/TOOLRxD/SDA00
P12/SO00/TxD0/TOOLTxD
P16/TI01/TO01/INTP5/SO11
P17/TI02/TO02/SI11/SDA11
P30/INTP3/SCK11/SCL11
20
19
18
17
16
15
14
13
12
11
RESET
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
V
SS
V
DD
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remark For pin identification, see 1.4 Pin Identification.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 16 of 196
RL78/G13
1.3.2 24-pin products
1. OUTLINE
24-pin plastic HWQFN (4 × 4 mm, 0.5 mm pitch)
exposed die pad
P17/TI02/TO02/SO11
18 17 16 15 14 13
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P40/TOOL0
19
20
21
22
23
24
12
11
10
9
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
P31/TI03/TO03/INTP4/PCLBUZ0
P61/SDAA0
RL78/G13
(Top View)
8
7
P60/SCLA0
RESET
1 2 3 4
5 6
INDEX MARK
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. It is recommended to connect an exposed die pad to Vss.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 17 of 196
RL78/G13
1.3.3 25-pin products
1. OUTLINE
25-pin plastic WFLGA (3 × 3 mm, 0.50 mm pitch)
Bottom View
Top View
<R>
5
4
RL78/G13
3
(Top View)
2
1
A
B
C
D
E
E
D
C
B
A
INDEX MARK
INDEX MARK
A
B
C
D
E
P40/TOOL0
RESET
P01/ANI16/
TO00/RxD1
P22/ANI2
P147/ANI18
5
4
5
4
P122/X2/
EXCLK
P137/INTP0
VDD
P00/ANI17/
TI00/TxD1
P21/ANI1/
AVREFM
P10/SCK00/
SCL00
P121/X1
P20/ANI0/
AVREFP
P12/SO00/
TxD0/
TOOLTxD
P11/SI00/
RxD0/
TOOLRxD/
SDA00
3
2
1
3
2
1
REGC
VSS
P30/INTP3/
SCK11/SCL11
P17/TI02/
TO02/SO11
P50/INTP1/
SI11/SDA11
P60/SCLA0
P61/SDAA0
P31/TI03/
TO03/INTP4/
PCLBUZ0
P16/TI01/
TO01/INTP5
P130
A
B
C
D
E
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remark For pin identification, see 1.4 Pin Identification.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 18 of 196
RL78/G13
1.3.4 30-pin products
1. OUTLINE
30-pin plastic LSSOP (7.62 mm (300), 0.65 mm pitch)
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P120/ANI19
1
2
3
4
5
6
7
8
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
P147/ANI18
P40/TOOL0
RESET
P137/INTP0
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
P122/X2/EXCLK
P121/X1
9
10
11
12
13
14
15
REGC
V
SS
VDD
P60/SCLA0
P61/SDAA0
P31/TI03/TO03/INTP4/PCLBUZ0
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
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Mar 31, 2016
Page 19 of 196
RL78/G13
1.3.5 32-pin products
1. OUTLINE
32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch)
exposed die pad
24 23 22 21 20 19 18 17
P147/ANI18
P23/ANI3
P22/ANI2
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
P70
P31/TI03/TO03/INTP4/PCLBUZ0
P62
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
RL78/G13
(Top View)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P120/ANI19
P61/SDAA0
P60/SCLA0
1 2 3 4 5 6 7 8
INDEX MARK
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
3. It is recommended to connect an exposed die pad to Vss.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 20 of 196
RL78/G13
1.3.6 36-pin products
1. OUTLINE
36-pin plastic WFLGA (4 × 4 mm, 0.5 mm pitch)
Top View
Bottom View
6
5
4
3
2
1
RL78/G13
(Top View)
A
B
C
D
E
F
F
E
D
C
B
A
INDEX MARK
A
B
C
D
E
F
P60/SCLA0
VDD
P121/X1
P122/X2/EXCLK P137/INTP0
P40/TOOL0
6
5
4
3
6
5
4
3
P62
P61/SDAA0
VSS
REGC
RESET
P120/ANI19
P72/SO21
P50/INTP1/
P71/SI21/
SDA21
P14/RxD2/SI20/
SDA20/(SCLA0)
/(TI03)/(TO03)
P31/TI03/TO03/
INTP4/
PCLBUZ0
P00/TI00/TxD1
P01/TO00/RxD1
P70/SCK21/
SCL21
P15/PCLBUZ1/
SCK20/SCL20/
(TI02)/(TO02)
P22/ANI2
P20/ANI0/
AVREFP
P21/ANI1/
AVREFM
SI11/SDA11
P30/INTP3/
SCK11/SCL11
P16/TI01/TO01/
INTP5/(RxD0)
P12/SO00/
TxD0/TOOLTxD
/(TI05)/(TO05)
P11/SI00/RxD0/
TOOLRxD/
SDA00/(TI06)/
(TO06)
P24/ANI4
P23/ANI3
2
1
2
1
P51/INTP2/
SO11
P17/TI02/TO02/
(TxD0)
P13/TxD2/
SO20/(SDAA0)/
(TI04)/(TO04)
P10/SCK00/
SCL00/(TI07)/
(TO07)
P147/ANI18
E
P25/ANI5
F
A
B
C
D
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 21 of 196
RL78/G13
1.3.7 40-pin products
1. OUTLINE
40-pin plastic HWQFN (6 × 6 mm, 0.5 mm pitch)
30 29 28 27 26 25 242322 21
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
31
32
33
34
35
36
37
38
39
40
20
19
18
17
16
15
14
13
12
11
P50/INTP1/SI11/SDA11
exposed die pad
P30/INTP3/RTC1HZ/SCK11/SCL11
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0
P62
RL78/G13
(Top View)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1
P00/TI00/TxD1
P120/ANI19
P61/SDAA0
P60/SCLA0
1 2 3 4 5 6 7 8 9 10
INDEX MARK
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
3. It is recommended to connect an exposed die pad to Vss.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 22 of 196
RL78/G13
1.3.8 44-pin products
1. OUTLINE
44-pin plastic LQFP (10 × 10 mm, 0.8 mm pitch)
33 32 31 30 29 28 27 26 25 24 23
P50/INTP1/SI11/SDA11
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
22
21
20
19
18
17
16
15
14
13
12
34
35
36
37
38
39
40
41
42
43
44
P30/INTP3/RTC1HZ/SCK11/SCL11
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P31/TI03/TO03/INTP4/PCLBUZ0
P63
P62
P61/SDAA0
P60/SCLA0
RL78/G13
(Top View)
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P01/TO00/RxD1
P00/TI00/TxD1
P120/ANI19
1 2 3 4
5 6 7 8 9 10 11
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 23 of 196
RL78/G13
1.3.9 48-pin products
1. OUTLINE
48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch)
36 35 34 33 32 31 30 29 28 27 26 25
24
P120/ANI19
P41/TI07/TO07
P40/TOOL0
RESET
37
38
39
40
41
42
43
44
45
46
47
48
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
23
22
21
20
19
18
17
16
15
14
13
P124/XT2/EXCLKS
P123/XT1
RL78/G13
(Top View)
P137/INTP0
P122/X2/EXCLK
P121/X1
REGC
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
V
SS
V
DD
1 2 3 4
5 6 7 8 9 10 11 12
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 24 of 196
RL78/G13
1. OUTLINE
48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch)
36 35 34 33 32 31 30 29 28 27 26 25
37
P147/ANI18
P146
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(RXD0)
P120/ANI19
P41/TI07/TO07
P40/TOOL0
RESET
24
23
22
21
20
19
18
17
16
15
14
13
38
39
40
41
42
43
44
45
46
47
48
exposed die pad
P124/XT2/EXCLKS
P123/XT1
RL78/G13
(Top View)
P137/INTP0
P122/X2/EXCLK
P121/X1
P17/TI02/TO02/(TXD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
REGC
V
SS
VDD
1 2 3 4 5
6 7 8 9 10 11 12
INDEX MARK
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
3. It is recommended to connect an exposed die pad to Vss.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 25 of 196
RL78/G13
1.3.10 52-pin products
1. OUTLINE
52-pin plastic LQFP (10 × 10 mm, 0.65 mm pitch)
39 38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
P70/KR0/SCK21/SCL21
P27/ANI7
P26/ANI6
P71/KR1/SI21/SDA21
P72/KR2/SO21
P25/ANI5
P73/KR3/SO01
P24/ANI4
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63
P23/ANI3
P22/ANI2
RL78/G13
(Top View)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P03/ANI16/RxD1
P02/ANI17/TxD1
P01/TO00
P62
P61/SDAA0
P60/SCLA0
P00/TI00
1
2
3
4
5
6
7
8 9 10 11 12 13
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 26 of 196
RL78/G13
1.3.11 64-pin products
1. OUTLINE
64-pin plastic LQFP (12 × 12 mm, 0.65 mm pitch)
64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P27/ANI7
P26/ANI6
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P30/INTP3/RTC1HZ/SCK11/SCL11
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P05/TI05/TO05
P25/ANI5
P06/TI06/TO06
P24/ANI4
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P23/ANI3
P22/ANI2
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P73/KR3/SO01
RL78/G13
(Top View)
P74/KR4/INTP8/SI01/SDA01
P75/KR5/INTP9/SCK01/SCL01
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P62
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P61/SDAA0
P60/SCLA0
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 27 of 196
RL78/G13
1. OUTLINE
64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch)
Top View
Bottom View
8
7
6
5
RL78/G13
(Top View)
4
3
2
1
A
B
C
D
E
F
G H
H
G
F
E
D
C
B A
Index mark
Pin No.
A1
Name
Pin No.
C1
Name
Pin No.
E1
Name
P13/TxD2/SO20/
(SDAA0)/(TI04)/(TO04)
Pin No.
G1 P146
Name
P05/TI05/TO05
P51/INTP2/SO11
A2
A3
A4
A5
P30/INTP3/RTC1HZ
/SCK11/SCL11
C2
C3
C4
C5
P71/KR1/SI21/SDA21 E2
P14/RxD2/SI20/SDA20 G2
/(SCLA0)/(TI03)/(TO03)
P25/ANI5
P24/ANI4
P22/ANI2
P130
P70/KR0/SCK21
/SCL21
P74/KR4/INTP8/SI01 E3
/SDA01
P15/SCK20/SCL20/
(TI02)/(TO02)
G3
P75/KR5/INTP9
/SCK01/SCL01
P52/(INTP10)
E4
P16/TI01/TO01/INTP5 G4
/(SI00)/(RxD0)
P77/KR7/INTP11/
(TxD2)
P53/(INTP11)
E5
P03/ANI16/SI10/RxD1 G5
/SDA10
A6
A7
A8
B1
P61/SDAA0
P60/SCLA0
EVDD0
C6
C7
C8
D1
P63
E6
E7
E8
F1
P41/TI07/TO07
RESET
G6
G7
G8
H1
P02/ANI17/SO10/TxD1
P00/TI00
VSS
P121/X1
P137/INTP0
P124/XT2/EXCLKS
P147/ANI18
P50/INTP1/SI11
/SDA11
P55/(PCLBUZ1)/
(SCK00)
P10/SCK00/SCL00/
(TI07)/(TO07)
B2
B3
P72/KR2/SO21
D2
D3
P06/TI06/TO06
F2
F3
P11/SI00/RxD0
/TOOLRxD/SDA00/
(TI06)/(TO06)
H2
H3
P27/ANI7
P26/ANI6
P73/KR3/SO01
P17/TI02/TO02/
(SO00)/(TxD0)
P12/SO00/TxD0
/TOOLTxD/(INTP5)/
(TI05)/(TO05)
B4
B5
P76/KR6/INTP10/
(RxD2)
D4
D5
P54
F4
F5
P21/ANI1/AVREFM
H4
H5
P23/ANI3
P31/TI03/TO03
P42/TI04/TO04
P04/SCK10/SCL10
P20/ANI0/AVREFP
/INTP4/(PCLBUZ0)
B6
B7
B8
P62
VDD
D6
D7
D8
P40/TOOL0
REGC
F6
F7
F8
P43
H6
H7
H8
P141/PCLBUZ1/INTP7
P140/PCLBUZ0/INTP6
P120/ANI19
P01/TO00
P123/XT1
EVSS0
P122/X2/EXCLK
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
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Mar 31, 2016
Page 28 of 196
RL78/G13
1.3.12 80-pin products
1. OUTLINE
80-pin plastic LQFP (14 × 14 mm, 0.65 mm pitch)
80-pin plastic LFQFP (12 × 12 mm, 0.5 mm pitch)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
P30/INTP3/RTC1HZ/SCK11/SCL11
P05/TI05/TO05
P06/TI06/TO06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
RL78/G13
(Top View)
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P62/SCLA1
P61/SDAA0
P60/SCLA0
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P142/SCK30/SCL30
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Cautions 1. Make EVSS0 pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0 pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 29 of 196
RL78/G13
1.3.13 100-pin products
1. OUTLINE
100-pin plastic LQFP (14 × 14 mm, 0.5 mm pitch)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TXD1)
P81/(SI10)/(RXD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVSS1
P05
P06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
RL78/G13
(Top View)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102/TI06/TO06
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P145/TI07/TO07
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P62/SCLA1
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0
and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 30 of 196
RL78/G13
1. OUTLINE
100-pin plastic LQFP (14 × 20 mm, 0.65 mm pitch)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P146/(INTP4)
P111/(INTP11)
P110/(INTP10)
P101
P10/SCK00/SCL00/(TI07)/(TO07)
P11/SI00/RxD0/TOOLRxD/SDA00/(TI06)/(TO06)
P12/SO00/TxD0/TOOLTxD/(INTP5)/(TI05)/(TO05)
P13/TxD2/SO20/(SDAA0)/(TI04)/(TO04)
P14/RxD2/SI20/SDA20/(SCLA0)/(TI03)/(TO03)
P15/SCK20/SCL20/(TI02)/(TO02)
P16/TI01/TO01/INTP5/(SI00)/(RXD0)
P17/TI02/TO02/(SO00)/(TXD0)
P57/(INTP3)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P120/ANI19
P47/INTP2
P46/INTP1/TI05/TO05
P45/SO01
P44/SI01/SDA01
P43/SCK01/SCL01
P42/TI04/TO04
P41
P40/TOOL0
RL78/G13
(Top View)
RESET
P124/XT2/EXCLKS
P123/XT1
P137/INTP0
P122/X2/EXCLK
P121/X1
P56/(INTP1)
P55/(PCLBUZ1)/(SCK00)
P54/SCK31/SCL31
P53/SI31/SDA31
P52/SO31
REGC
V
SS
EVSS0
DD
EVDD0
P51/SO11
P50/SI11/SDA11
V
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0
and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 31 of 196
RL78/G13
1.3.14 128-pin products
1. OUTLINE
128-pin plastic LFQFP (14 × 20 mm, 0.5 mm pitch)
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P86/(INTP8)
P85/(INTP7)
P84/(INTP6)
P83
P82/(SO10)/(TXD1)
P81/(SI10)/(RXD1)/(SDA10)
P80/(SCK10)/(SCL10)
EVDD1
EVSS1
P05
P156/ANI14
P155/ANI13
P154/ANI12
P153/ANI11
P152/ANI10
P151/ANI9
P150/ANI8
P27/ANI7
P26/ANI6
P25/ANI5
P24/ANI4
P23/ANI3
P22/ANI2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
P06
P70/KR0/SCK21/SCL21
P71/KR1/SI21/SDA21
P72/KR2/SO21
P73/KR3
RL78/G13
(Top View)
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P130
P102/TI06/TO06
P07
P74/KR4/INTP8
P75/KR5/INTP9
P76/KR6/INTP10/(RXD2)
P77/KR7/INTP11/(TXD2)
P67/TI13/TO13
P66/TI12/TO12
P65/TI11/TO11
P64/TI10/TO10
P31/TI03/TO03/INTP4/(PCLBUZ0)
P63/SDAA1
P04/SCK10/SCL10
P03/ANI16/SI10/RxD1/SDA10
P02/ANI17/SO10/TxD1
P01/TO00
P00/TI00
P145/TI07/TO07
P144/SO30/TxD3
P143/SI30/RxD3/SDA30
P62/SCLA1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Cautions 1. Make EVSS0, EVSS1 pins the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD0, EVDD1 pins (EVDD0 = EVDD1).
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD, EVDD0
and EVDD1 pins and connect the VSS, EVSS0 and EVSS1 pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 32 of 196
RL78/G13
1. OUTLINE
1.4 Pin Identification
ANI0 to ANI14,
ANI16 to ANI26:
AVREFM:
REGC:
Regulator capacitance
Reset
Analog input
RESET:
RTC1HZ:
A/D converter reference
potential ( side) input
A/D converter reference
potential (+ side) input
Power supply for port
Ground for port
Real-time clock correction clock
(1 Hz) output
AVREFP:
RxD0 to RxD3:
Receive data
SCK00, SCK01, SCK10,
SCK11, SCK20, SCK21,
SCLA0, SCLA1:
EVDD0, EVDD1:
EVSS0, EVSS1:
EXCLK:
Serial clock input/output
Serial clock output
External clock input (Main SCLA0, SCLA1, SCL00,
system clock)
External clock input
(Subsystem clock)
Interrupt request from
peripheral
Key return
Port 0
SCL01, SCL10, SCL11,
SCL20,SCL21, SCL30,
SCL31:
EXCLKS:
INTP0 to INTP11:
SDAA0, SDAA1, SDA00,
SDA01,SDA10, SDA11,
SDA20,SDA21, SDA30,
SDA31:
KR0 to KR7:
P00 to P07:
P10 to P17:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P67:
P70 to P77:
P80 to P87:
P90 to P97:
P100 to P106:
P110 to P117:
P120 to P127:
P130, P137:
P140 to P147:
P150 to P156:
Serial data input/output
Port 1
SI00, SI01, SI10, SI11,
Port 2
SI20, SI21, SI30, SI31: Serial data input
SO00, SO01, SO10,
Port 3
Port 4
SO11, SO20, SO21,
Port 5
SO30, SO31:
TI00 to TI07,
TI10 to TI17:
TO00 to TO07,
TO10 to TO17:
TOOL0:
Serial data output
Timer input
Port 6
Port 7
Port 8
Port 9
Timer output
Port 10
Data input/output for tool
Data input/output for external device
Transmit data
Port 11
TOOLRxD, TOOLTxD:
TxD0 to TxD3:
VDD:
Port 12
Port 13
Power supply
Port 14
VSS:
Ground
Port 15
X1, X2:
Crystal oscillator (main system clock)
Crystal oscillator (subsystem clock)
PCLBUZ0, PCLBUZ1: Programmable clock
output/buzzer output
XT1, XT2:
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 33 of 196
RL78/G13
1. OUTLINE
1.5 Block Diagram
1.5.1 20-pin products
TIMER ARRAY
UNIT (8ch)
2
5
3
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 12
P00, P01
TI00/P00
ch0
P10 to P12, P16, P17
P20 to P22
P30
TO00/P01
TI01/TO01/P16
TI02/TO02/P17
ch1
ch2
ch3
P40
ch4
ch5
ch6
ch7
P121, P122
2
PORT 13
PORT 14
P137
P147
CODE FLASH MEMORY
DATA FLASH MEMORY
ANI0/P20 to
ANI2/P22
RL78
CPU
CORE
3
3
WINDOW
WATCHDOG
TIMER
ANI16/P01, ANI17/P00,
ANI18/P147
A/D CONVERTER
AVREFP/P20
AVREFM/P21
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
REAL-TIME
CLOCK
DETECTOR
RAM
SERIAL ARRAY
UNIT0 (4ch)
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
RxD0/P11
TxD0/P12
UART0
UART1
VDD
V
SS TOOLRxD/P11,
TOOLTxD/P12
SYSTEM
CONTROL
RxD1/P01
TxD1/P00
RESET
X1/P121
HIGH-SPEED
ON-CHIP
OSCILLATOR
X2/EXCLK/P122
SCK00/P10
SI00/P11
MULTIPLIER&
DIVIDER,
MULITIPLY-
CRC
CSI00
CSI11
SO00/P12
ACCUMULATOR
VOLTAGE
REGULATOR
REGC
SCK11/P30
SI11/P17
DIRECT MEMORY
ACCESS CONTROL
SO11/P16
INTP0/P137
SCL00/P10
SDA00/P11
INTERRUPT
CONTROL
IIC00
IIC11
INTP3/P30
INTP5/P16
BCD
ADJUSTMENT
SCL11/P30
SDA11/P17
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 34 of 196
RL78/G13
1.5.2 24-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
5
3
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
P00, P01
TI00/P00
TO00/P01
ch0
P10 to P12, P16, P17
P20 to P22
P30, P31
P40
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
TI03/TO03/P31
ch4
ch5
ch6
ch7
P50
2
2
P60, P61
PORT 12
P121, P122
PORT 13
PORT 14
P137
P147
WINDOW
WATCHDOG
TIMER
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
LOW-SPEED
ON-CHIP
OSCILLATOR
ANI0/P20 to
ANI2/P22
12-BIT INTERVAL
TIMER
3
3
ANI16/P01, ANI17/P00,
ANI18/P147
A/D CONVERTER
REAL-TIME
CLOCK
AVREFP/P20
AVREFM/P21
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
SERIAL ARRAY
UNIT0 (4ch)
DETECTOR
RAM
RxD0/P11
TxD0/P12
UART0
UART1
RESET CONTROL
ON-CHIP DEBUG
RxD1/P01
TxD1/P00
TOOL0/P40
V
DD
V
SS TOOLRxD/P11,
TOOLTxD/P12
SCK00/P10
SI00/P11
CSI00
CSI11
SO00/P12
SYSTEM
CONTROL
RESET
SCK11/P30
SI11/P50
SDAA0/P61
SCLA0/P60
SERIAL
X1/P121
HIGH-SPEED
ON-CHIP
SO11/P17
INTERFACE IICA0
X2/EXCLK/P122
OSCILLATOR
SCL00/P10
SDA00/P11
IIC00
IIC11
BUZZER OUTPUT
VOLTAGE
REGULATOR
SCL11/P30
SDA11/P50
PCLBUZ0/P31
CRC
REGC
CLOCK OUTPUT
CONTROL
DIRECT MEMORY
ACCESS CONTROL
INTP0/P137
MULTIPLIER&
DIVIDER,
MULITIPLY-
INTP1/P50
INTP3/P30,
INTERRUPT
CONTROL
ACCUMULATOR
BCD
ADJUSTMENT
2
INTP4/P31
INTP5/P16
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 35 of 196
RL78/G13
1.5.3 25-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
P00, P01
TI00/P00
TO00/P01
ch0
5
P10 to P12, P16, P17
TI01/TO01/P16
ch1
ch2
ch3
3
2
P20 to P22
TI02/TO02/P17
TI03/TO03/P31
P30, P31
P40
ch4
ch5
ch6
ch7
P50
2
2
P60, P61
PORT 12
P121, P122
P130
P137
PORT 13
PORT 14
WINDOW
WATCHDOG
TIMER
P147
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
LOW-SPEED
ON-CHIP
OSCILLATOR
ANI0/P20 to
ANI2/P22
12-BIT INTERVAL
TIMER
3
3
ANI16/P01, ANI17/P00,
ANI18/P147
A/D CONVERTER
AVREFP/P20
AVREFM/P21
REAL-TIME
CLOCK
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
SERIAL ARRAY
UNIT0 (4ch)
DETECTOR
RAM
RxD0/P11
TxD0/P12
UART0
UART1
RESET CONTROL
ON-CHIP DEBUG
RxD1/P01
TxD1/P00
TOOL0/P40
V
DD
V
SS TOOLRxD/P11,
TOOLTxD/P12
SCK00/P10
SI00/P11
CSI00
CSI11
SO00/P12
SYSTEM
CONTROL
SCK11/P30
SI11/P50
RESET
SDAA0/P61
SCLA0/P60
SERIAL
X1/P121
HIGH-SPEED
ON-CHIP
SO11/P17
INTERFACE IICA0
X2/EXCLK/P122
OSCILLATOR
SCL00/P10
SDA00/P11
IIC00
IIC11
BUZZER OUTPUT
SCL11/P30
SDA11/P50
VOLTAGE
REGULATOR
PCLBUZ0/P31
CRC
REGC
CLOCK OUTPUT
CONTROL
DIRECT MEMORY
ACCESS CONTROL
INTP0/P137
MULTIPLIER&
DIVIDER,
MULITIPLY-
INTP1/P50
INTP3/P30,
INTERRUPT
CONTROL
BCD
ADJUSTMENT
ACCUMULATOR
2
INTP4/P31
INTP5/P16
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 36 of 196
RL78/G13
1.5.4 30-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
8
4
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
P00, P01
P10 to P17
P20 to P23
P30, P31
P40
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
(TI04/TO04/P13)
(TI05/TO05/P12)
(TI06/TO06/P11)
ch4
ch5
ch6
ch7
2
2
P50, P51
P60, P61
(TI07/TO07/P10)
RxD2/P14
P120
PORT 12
P121, P122
2
PORT 13
PORT 14
P137
P147
WINDOW
WATCHDOG
TIMER
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
REAL-TIME
CLOCK
ANI0/P20 to
ANI3/P23
4
4
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
ANI16/P01, ANI17/P00,
ANI18/P147, ANI19/P120
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
UART0
UART1
TxD0/P12(TxD0/P17)
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
RxD1/P01
TxD1/P00
DETECTOR
RAM
SCK00/P10
SI00/P11
CSI00
CSI11
RESET CONTROL
ON-CHIP DEBUG
SO00/P12
SCK11/P30
SI11/P50
TOOL0/P40
VDD
V
SS TOOLRxD/P11,
TOOLTxD/P12
SO11/P51
SCL00/P10
SDA00/P11
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
IIC00
IIC11
SERIAL
INTERFACE IICA0
SYSTEM
CONTROL
RESET
X1/P121
SCL11/P30
SDA11/P50
HIGH-SPEED
ON-CHIP
OSCILLATOR
X2/EXCLK/P122
BUZZER OUTPUT
PCLBUZ0/P31,
PCLBUZ1/P15
2
CLOCK OUTPUT
CONTROL
VOLTAGE
REGULATOR
SERIAL ARRAY
UNIT1 (2ch)
REGC
MULTIPLIER&
DIVIDER,
MULITIPLY-
RxD2/P14
TxD2/P13
CRC
UART2
LINSEL
RxD2/P14
INTP0/P137
ACCUMULATOR
INTP1/P50,
INTP2/P51
SCK20/P15
SI20/P14
2
INTERRUPT
CONTROL
DIRECT MEMORY
ACCESS CONTROL
CSI20
IIC20
INTP3/P30,
INTP4/P31
SO20/P13
2
INTP5/P16
SCL20/P15
SDA20/P14
BCD
ADJUSTMENT
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 37 of 196
RL78/G13
1.5.5 32-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
8
4
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00, P01
P10 to P17
P20 to P23
P30, P31
P40
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
(TI04/TO04/P13)
ch4
ch5
ch6
ch7
2
3
P50, P51
(TI05/TO05/P12)
(TI06/TO06/P11)
P60 to P62
P70
(TI07/TO07/P10)
RxD2/P14
P120
PORT 12
WINDOW
WATCHDOG
TIMER
P121, P122
2
PORT 13
PORT 14
P137
P147
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
REAL-TIME
CLOCK
ANI0/P20 to
ANI3/P23
4
4
ANI16/P01, ANI17/P00,
ANI18/P147, ANI19/P120
A/D CONVERTER
SERIAL ARRAY
UNIT0 (4ch)
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
UART0
UART1
TxD0/P12(TxD0/P17)
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
RxD1/P01
TxD1/P00
RAM
DETECTOR
SCK00/P10
SI00/P11
CSI00
CSI11
RESET CONTROL
ON-CHIP DEBUG
SO00/P12
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
SCK11/P30
SI11/P50
TOOL0/P40
SO11/P51
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SCL00/P10
SDA00/P11
SERIAL
INTERFACE IICA0
IIC00
IIC11
SYSTEM
CONTROL
RESET
SCL11/P30
SDA11/P50
X1/P121
HIGH-SPEED
ON-CHIP
OSCILLATOR
BUZZER OUTPUT
X2/EXCLK/P122
PCLBUZ0/P31,
PCLBUZ1/P15
2
CLOCK OUTPUT
CONTROL
SERIAL ARRAY
UNIT1 (2ch)
VOLTAGE
REGULATOR
REGC
MULTIPLIER&
DIVIDER,
MULITIPLY-
CRC
RxD2/P14
TxD2/P13
UART2
LINSEL
RxD2/P14
INTP0/P137
ACCUMULATOR
INTP1/P50,
INTP2/P51
SCK20/P15
SI20/P14
DIRECT MEMORY
ACCESS CONTROL
2
CSI20
IIC20
INTERRUPT
CONTROL
INTP3/P30,
INTP4/P31
SO20/P13
2
SCL20/P15
SDA20/P14
BCD
ADJUSTMENT
INTP5/P16
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 38 of 196
RL78/G13
1.5.6 36-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
8
6
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00, P01
P10 to P17
P20 to P25
P30, P31
P40
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
(TI04/TO04/P13)
(TI05/TO05/P12)
(TI06/TO06/P11)
ch4
ch5
ch6
ch7
2
3
3
P50, P51
P60 to P62
P70 to P72
(TI07/TO07/P10)
RxD2/P14
P120
WINDOW
WATCHDOG
TIMER
PORT 12
P121, P122
2
PORT 13
PORT 14
P137
P147
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
REAL-TIME
CLOCK
ANI0/P20 to
ANI5/P25
6
2
SERIAL ARRAY
UNIT0 (4ch)
A/D CONVERTER
ANI18/P147, ANI19/P120
RxD0/P11(RxD0/P16)
AVREFP/P20
AVREFM/P21
UART0
UART1
CSI00
TxD0/P12(TxD0/P17)
RxD1/P01
TxD1/P00
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
SCK00/P10
SI00/P11
DETECTOR
RAM
SO00/P12
SCK11/P30
SI11/P50
RESET CONTROL
ON-CHIP DEBUG
CSI11
SO11/P51
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
SCL00/P10
SDA00/P11
TOOL0/P40
IIC00
IIC11
SCL11/P30
SDA11/P50
SYSTEM
CONTROL
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
RESET
X1/P121
SERIAL
INTERFACE IICA0
HIGH-SPEED
ON-CHIP
X2/EXCLK/P122
SERIAL ARRAY
UNIT1 (2ch)
OSCILLATOR
BUZZER OUTPUT
RxD2/P14
TxD2/P13
PCLBUZ0/P31,
PCLBUZ1/P15
UART2
LINSEL
VOLTAGE
REGULATOR
2
REGC
CLOCK OUTPUT
CONTROL
RxD2/P14
INTP0/P137
SCK20/P15
SI20/P14
MULTIPLIER&
DIVIDER,
MULITIPLY-
CSI20
CSI21
CRC
INTP1/P50,
INTP2/P51
SO20/P13
SCK21/P70
SI21/P71
2
INTERRUPT
CONTROL
ACCUMULATOR
INTP3/P30,
INTP4/P31
2
SO21/P72
DIRECT MEMORY
ACCESS CONTROL
INTP5/P16
SCL20/P15
SDA20/P14
IIC20
IIC21
SCL21/P70
SDA21/P71
BCD
ADJUSTMENT
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 39 of 196
RL78/G13
1.5.7 40-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
8
7
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00, P01
P10 to P17
P20 to P26
P30, P31
P40
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
(TI04/TO04/P13)
(TI05/TO05/P12)
(TI06/TO06/P11)
ch4
ch5
ch6
ch7
2
3
4
P50, P51
P60 to P62
P70 to P73
(TI07/TO07/P10)
RxD2/P14
P120
WINDOW
WATCHDOG
TIMER
PORT 12
P121 to P124
4
PORT 13
PORT 14
P137
P147
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
REAL-TIME
CLOCK
RTC1HZ/P30
ANI0/P20 to
ANI6/P26
7
2
SERIAL ARRAY
UNIT0 (4ch)
A/D CONVERTER
KEY RETURN
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
UART1
CSI00
RxD1/P01
TxD1/P00
KR0/P70 to
KR3/P73
4
SCK00/P10
SI00/P11
RAM
SO00/P12
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
SCK11/P30
SI11/P50
DETECTOR
CSI11
SO11/P51
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
SCL00/P10
SDA00/P11
IIC00
IIC11
RESET CONTROL
ON-CHIP DEBUG
SCL11/P30
SDA11/P50
TOOL0/P40
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SERIAL
INTERFACE IICA0
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
SERIAL ARRAY
UNIT1 (2ch)
BUZZER OUTPUT
RxD2/P14
TxD2/P13
HIGH-SPEED
ON-CHIP
OSCILLATOR
PCLBUZ0/P31,
PCLBUZ1/P15
UART2
LINSEL
2
XT1/P123
CLOCK OUTPUT
CONTROL
XT2/EXCLKS/P124
SCK20/P15
SI20/P14
VOLTAGE
REGULATOR
MULTIPLIER&
DIVIDER,
MULITIPLY-
CSI20
CSI21
REGC
CRC
SO20/P13
SCK21/P70
SI21/P71
ACCUMULATOR
RxD2/P14
INTP0/P137
SO21/P72
DIRECT MEMORY
ACCESS CONTROL
INTP1/P50,
INTP2/P51
2
SCL20/P15
SDA20/P14
INTERRUPT
CONTROL
IIC20
IIC21
INTP3/P30,
INTP4/P31
2
SCL21/P70
SDA21/P71
BCD
ADJUSTMENT
INTP5/P16
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 40 of 196
RL78/G13
1.5.8 44-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
8
8
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00, P01
TI00/P00
TO00/P01
ch0
P10 to P17
P20 to P27
P30, P31
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
2
2
P40, P41
P50, P51
(TI04/TO04/P13)
(TI05/TO05/P12)
(TI06/TO06/P11)
ch4
ch5
ch6
ch7
4
4
P60 to P63
P70 to P73
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
P120
WINDOW
WATCHDOG
TIMER
PORT 12
P121 to P124
4
2
PORT 13
PORT 14
P137
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
P146, P147
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
REAL-TIME
CLOCK
RTC1HZ/P30
ANI0/P20 to
ANI7/P27
8
2
SERIAL ARRAY
UNIT0 (4ch)
A/D CONVERTER
KEY RETURN
ANI18/P147, ANI19/P120
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
UART1
CSI00
RxD1/P01
TxD1/P00
KR0/P70 to
KR3/P73
4
SCK00/P10
SI00/P11
RAM
SO00/P12
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
SCK11/P30
SI11/P50
DETECTOR
CSI11
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
SO11/P51
SCL00/P10
SDA00/P11
IIC00
IIC11
RESET CONTROL
ON-CHIP DEBUG
SCL11/P30
SDA11/P50
TOOL0/P40
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SERIAL
INTERFACE IICA0
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
SERIAL ARRAY
UNIT1 (2ch)
BUZZER OUTPUT
RxD2/P14
TxD2/P13
PCLBUZ0/P31,
PCLBUZ1/P15
HIGH-SPEED
ON-CHIP
OSCILLATOR
UART2
LINSEL
2
XT1/P123
CLOCK OUTPUT
CONTROL
XT2/EXCLKS/P124
SCK20/P15
SI20/P14
VOLTAGE
REGULATOR
MULTIPLIER&
DIVIDER,
MULITIPLY-
CSI20
CSI21
REGC
CRC
SO20/P13
SCK21/P70
SI21/P71
ACCUMULATOR
RxD2/P14
INTP0/P137
SO21/P72
DIRECT MEMORY
ACCESS CONTROL
INTP1/P50,
INTP2/P51
2
INTERRUPT
CONTROL
SCL20/P15
SDA20/P14
IIC20
IIC21
INTP3/P30,
INTP4/P31
2
SCL21/P70
SDA21/P71
BCD
ADJUSTMENT
INTP5/P16
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 41 of 196
RL78/G13
1.5.9 48-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
2
8
8
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00, P01
TI00/P00
TO00/P01
ch0
P10 to P17
P20 to P27
P30, P31
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
2
2
P40, P41
P50, P51
(TI04/TO04/P13)
(TI05/TO05/P12)
(TI06/TO06/P11)
ch4
ch5
ch6
ch7
4
6
P60 to P63
P70 to P75
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
P120
PORT 12
WINDOW
WATCHDOG
TIMER
4
3
P121 to P124
P130
P137
PORT 13
PORT 14
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
P140,
P146, P147
REAL-TIME
CLOCK
CODE FLASH MEMORY
DATA FLASH MEMORY
RTC1HZ/P30
RL78
CPU
CORE
ANI0/P20 to
ANI7/P27
8
2
SERIAL ARRAY
UNIT0 (4ch)
ANI18/P147, ANI19/P120
A/D CONVERTER
KEY RETURN
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
UART1
CSI00
RxD1/P01
TxD1/P00
KR0/P70 to
KR5/P75
6
SCK00/P10
SI00/P11
RAM
SO00/P12
SCK01/P75
SI01/P74
POWER ON RESET/
VOLTAGE
POR/LVD
CONTROL
CSI01
CSI11
DETECTOR
SO01/P73
SCK11/P30
SI11/P50
RESET CONTROL
ON-CHIP DEBUG
VDD
V
SS TOOLRxD/P11,
TOOLTxD/P12
SO11/P51
SCL00/P10
SDA00/P11
IIC00
IIC01
IIC11
TOOL0/P40
SCL01/P75
SDA01/P74
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
SCL11/P30
SDA11/P50
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SERIAL
HIGH-SPEED
ON-CHIP
OSCILLATOR
INTERFACE IICA0
XT1/P123
XT2/EXCLKS/P124
SERIAL ARRAY
UNIT1 (2ch)
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P15
VOLTAGE
REGULATOR
REGC
2
RxD2/P14
TxD2/P13
UART2
LINSEL
CLOCK OUTPUT
CONTROL
RxD2/P14
INTP0/P137
SCK20/P15
SI20/P14
MULTIPLIER&
DIVIDER,
MULITIPLY-
CRC
INTP1/P50,
INTP2/P51
CSI20
CSI21
2
SO20/P13
SCK21/P70
SI21/P71
INTP3/P30,
INTP4/P31
ACCUMULATOR
2
INTERRUPT
CONTROL
INTP5/P16
DIRECT MEMORY
ACCESS CONTROL
SO21/P72
INTP6/P140
SCL20/P15
SDA20/P14
IIC20
IIC21
INTP8/P74,
INTP9/P75
2
BCD
ADJUSTMENT
SCL21/P70
SDA21/P71
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 42 of 196
RL78/G13
1.5.10 52-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
4
8
8
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00 to P03
P10 to P17
P20 to P27
P30, P31
TI00/P00
TO00/P01
ch0
TI01/TO01/P16
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
2
2
P40, P41
P50, P51
(TI04/TO04/P13)
(TI05/TO05/P12)
(TI06/TO06/P11)
ch4
ch5
ch6
ch7
4
8
P60 to P63
P70 to P77
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
P120
PORT 12
WINDOW
WATCHDOG
TIMER
4
3
P121 to P124
P130
P137
PORT 13
PORT 14
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
P140,
P146, P147
REAL-TIME
CLOCK
RTC1HZ/P30
ANI0/P20 to
ANI7/P27
8
4
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
A/D CONVERTER
KEY RETURN
SERIAL ARRAY
UNIT0 (4ch)
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
UART1
CSI00
RxD1/P03
TxD1/P02
KR0/P70 to
KR7/P77
8
SCK00/P10
SI00/P11
POWER ON RESET/
VOLTAGE
SO00/P12
SCK01/P75
SI01/P74
POR/LVD
CONTROL
RAM
DETECTOR
CSI01
SO01/P73
SCK11/P30
SI11/P50
RESET CONTROL
ON-CHIP DEBUG
CSI11
IIC00
SO11/P51
SCL00/P10
SDA00/P11
VDD
V
SS TOOLRxD/P11,
TOOLTxD/P12
TOOL0/P40
SCL01/P75
SDA01/P74
SYSTEM
CONTROL
IIC01
IIC11
RESET
X1/P121
X2/EXCLK/P122
SCL11/P30
SDA11/P50
HIGH-SPEED
ON-CHIP
XT1/P123
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
OSCILLATOR
XT2/EXCLKS/P124
SERIAL
INTERFACE IICA0
VOLTAGE
REGULATOR
SERIAL ARRAY
UNIT1 (2ch)
REGC
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P15
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
UART2
LINSEL
RxD2/P14 (RxD2/P76)
INTP0/P137
2
CLOCK OUTPUT
CONTROL
INTP1/P50,
INTP2/P51
2
SCK20/P15
SI20/P14
MULTIPLIER&
DIVIDER,
MULITIPLY-
CSI20
CSI21
INTP3/P30,
INTP4/P31
CRC
2
INTERRUPT
CONTROL
SO20/P13
SCK21/P70
SI21/P71
INTP5/P16
ACCUMULATOR
INTP6/P140
SO21/P72
DIRECT MEMORY
INTP8/P74 to
INTP11/P77
ACCESS CONTROL
SCL20/P15
SDA20/P14
4
IIC20
IIC21
SCL21/P70
SDA21/P71
BCD
ADJUSTMENT
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 43 of 196
RL78/G13
1.5.11 64-pin products
1. OUTLINE
TIMER ARRAY
UNIT (8ch)
7
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00 to P06
TI00/P00
TO00/P01
ch0
8
P10 to P17
TI01/TO01/P16
ch1
ch2
ch3
8
2
P20 to P27
P30, P31
TI02/TO02/P17
(TI02/TO02/P15)
TI03/TO03/P31
(TI03/TO03/P14)
4
6
P40 to P43
P50 to P55
TI04/TO04/P42
(TI04/TO04/P13)
ch4
ch5
ch6
ch7
TI05/TO05/P05
(TI05/TO05/P12)
TI06/TO06/P06
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
4
8
P60 to P63
P70 to P77
(RxD2/P76)
P120
PORT 12
WINDOW
WATCHDOG
TIMER
4
4
P121 to P124
P130
P137
PORT 13
PORT 14
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
P140, P141,
P146, P147
REAL-TIME
CLOCK
RTC1HZ/P30
ANI0/P20 to
ANI7/P27
8
4
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120
SERIAL ARRAY
UNIT0 (4ch)
A/D CONVERTER
KEY RETURN
AVREFP/P20
AVREFM/P21
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
UART1
CSI00
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
RxD1/P03
TxD1/P02
KR0/P70 to
KR7/P77
8
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P75
POWER ON RESET/
VOLTAGE
DETECTOR
POR/LVD
CONTROL
CSI01
CSI10
SI01/P74
SO01/P73
SCK10/P04
SI10/P03
RAM
RESET CONTROL
ON-CHIP DEBUG
SO10/P02
SCK11/P30
SI11/P50
CSI11
TOOL0/P40
SO11/P51
SCL00/P10
SDA00/P11
SYSTEM
CONTROL
IIC00
IIC01
IIC10
IIC11
RESET
X1/P121
X2/EXCLK/P122
V
DD
,
V
SS
,
TOOLRxD/P11,
EVDD0 EVSS0 TOOLTxD/P12
SCL01/P75
SDA01/P74
HIGH-SPEED
ON-CHIP
OSCILLATOR
XT1/P123
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SCL10/P04
SDA10/P03
XT2/EXCLKS/P124
SERIAL
INTERFACE IICA0
VOLTAGE
REGULATOR
SCL11/P30
SDA11/P50
REGC
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
RxD2/P14 (RxD2/P76)
INTP0/P137
2
CLOCK OUTPUT
CONTROL
SERIAL ARRAY
UNIT1 (2ch)
INTP1/P50,
INTP2/P51
2
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
UART2
LINSEL
MULTIPLIER&
DIVIDER,
INTP3/P30,
INTP4/P31
CRC
2
MULITIPLY-
INTERRUPT
CONTROL
INTP5/P16(INTP5/P12)
ACCUMULATOR
SCK20/P15
SI20/P14
INTP6/P140,
INTP7/P141
CSI20
CSI21
2
2
2
DIRECT MEMORY
ACCESS CONTROL
SO20/P13
SCK21/P70
SI21/P71
INTP8/P74,
INTP9/P75
INTP10/P76(INTP10/P52),
INTP11/P77(INTP11/P53)
SO21/P72
BCD
ADJUSTMENT
SCL20/P15
SDA20/P14
IIC20
IIC21
SCL21/P70
SDA21/P71
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 44 of 196
RL78/G13
1.5.12 80-pin products
1. OUTLINE
TIMER ARRAY
UNIT1 (4ch)
TIMER ARRAY
UNIT0 (8ch)
TI00/P00
TO00/P01
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
7
8
8
2
6
6
8
P00 to P06
ch0
ch0
TI10/TO10/P64
TI11/TO11/P65
P10 to P17
P20 to P27
P30, P31
TI01/TO01/P16
ch1
ch2
ch3
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI12/TO12/P66
TI13/TO13/P67
TI03/TO03/P31
(TI03/TO03/P14)
TI04/TO04/P42
(TI04/TO04/P13)
ch4
ch5
ch6
ch7
P40 to P45
P50 to P55
P60 to P67
P70 to P77
TI05/TO05/P05
(TI05/TO05/P12)
TI06/TO06/P06
(TI06/TO06/P11)
TI07/TO07/P41
(TI07/TO07/P10)
RxD2/P14
(RxD2/P76)
8
SERIAL ARRAY
UNIT0 (4ch)
8
4
5
ANI0/P20 to ANI7/P27
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
ANI8/P150 to ANI11/P153
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
UART0
UART1
CSI00
RxD1/P03
TxD1/P02
A/D CONVERTER
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
P100
PORT 10
PORT 11
PORT 12
AVREFP/P20
AVREFM/P21
2
4
P110, P111
CSI01
CSI10
SI01/P44
P120
SO01/P45
P121 to P124
SCK10/P04
SI10/P03
CODE FLASH MEMORY
DATA FLASH MEMORY
P130
P137
RL78
CPU
CORE
SO10/P02
PORT 13
PORT 14
PORT 15
SCK11/P30
SI11/P50
CSI11
P140 to P144,
P146, P147
7
4
SO11/P51
SCL00/P10
SDA00/P11
P150 to P153
IIC00
IIC01
IIC10
IIC11
SCL01/P43
SDA01/P44
KR0/P70 to
KR7/P77
KEY RETURN
8
SCL10/P04
SDA10/P03
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
SCL11/P30
SDA11/P50
POR/LVD
CONTROL
V
DD
,
V
SS
,
TOOLRxD/P11,
SERIAL ARRAY
UNIT1 (4ch)
EVDD0 EVSS0 TOOLTxD/P12
RESET CONTROL
ON-CHIP DEBUG
SDAA0/P61(SDAA0/P13)
SCLA0/P60(SCLA0/P14)
SERIAL
INTERFACE IICA0
UART2
LINSEL
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
TOOL0/P40
SDAA1/P63
SCLA1/P62
SERIAL
INTERFACE IICA1
RxD3/P143
TxD3/P144
UART3
CSI20
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
SCK20/P15
SI20/P14
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
HIGH-SPEED
ON-CHIP
OSCILLATOR
2
SO20/P13
SCK21/P70
SI21/P71
XT1/P123
CLOCK OUTPUT
CONTROL
XT2/EXCLKS/P124
CSI21
CSI30
SO21/P72
MULTIPLIER&
DIVIDER,
MULITIPLY-
CRC
VOLTAGE
REGULATOR
SCK30/P142
SI30/P143
REGC
ACCUMULATOR
SO30/P144
RxD2/P14 (RxD2/P76)
INTP0/P137
SCK31/P54
SI31/P53
DIRECT MEMORY
ACCESS CONTROL
CSI31
INTP1/P50,
INTP2/P51
2
SO31/P52
INTP3/P30,
INTP4/P31
BCD
ADJUSTMENT
SCL20/P15
SDA20/P14
2
IIC20
IIC21
IIC30
IIC31
WINDOW
WATCHDOG
TIMER
INTP5/P16(INTP5/P12)
INTERRUPT
CONTROL
SCL21/P70
SDA21/P71
INTP6/P140,
INTP7/P141
2
2
2
SCL30/P142
SDA30/P143
LOW-SPEED
ON-CHIP
OSCILLATOR
INTP8/P74,
INTP9/P75
12-BIT INTERVAL
TIMER
INTP10/P76(INTP10/P110),
INTP11/P77(INTP11/P111)
SCL31/P54
SDA31/P53
REAL-TIME
CLOCK
RTC1HZ/P30
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 45 of 196
RL78/G13
1.5.13 100-pin products
1. OUTLINE
TIMER ARRAY
UNIT1 (4ch)
TIMER ARRAY
UNIT0 (8ch)
TI00/P00
TO00/P01
7
8
8
2
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00 to P06
ch0
ch0
TI10/TO10/P64
TI11/TO11/P65
TI01/TO01/P16
ch1
ch2
ch3
P10 to P17
P20 to P27
P30, P31
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI12/TO12/P66
TI13/TO13/P67
TI03/TO03/P31
(TI03/TO03/P14)
TI04/TO04/P42
(TI04/TO04/P13)
ch4
ch5
ch6
ch7
8
8
P40 to P47
P50 to P57
TI05/TO05/P46
(TI05/TO05/P12)
TI06/TO06/P102
(TI06/TO06/P11)
TI07/TO07/P145
(TI07/TO07/P10)
RxD2/P14
8
8
P60 to P67
P70 to P77
(RxD2/P76)
SERIAL ARRAY
UNIT0 (4ch)
8
7
5
ANI0/P20 to ANI7/P27
PORT 8
8
P80 to P87
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
ANI8/P150 to ANI14/P156
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100
UART0
UART1
CSI00
RxD1/P03(RxD1/P81)
TxD1/P02(TxD1/P82)
A/D CONVERTER
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
3
2
P100 to P102
P110, P111
PORT 10
PORT 11
PORT 12
AVREFP/P20
AVREFM/P21
CSI01
CSI10
SI01/P44
P120
SO01/P45
4
P121 to P124
SCK10/P04(SCK10/P80)
SI10/P03(SI10/P81)
CODE FLASH MEMORY
DATA FLASH MEMORY
P130
P137
RL78
CPU
CORE
SO10/P02(SO10/P82)
PORT 13
PORT 14
PORT 15
SCK11/P30
SI11/P50
CSI11
8
7
P140 to P147
P150 to P156
SO11/P51
SCL00/P10
SDA00/P11
IIC00
IIC01
IIC10
IIC11
SCL01/P43
SDA01/P44
KR0/P70 to
KR7/P77
KEY RETURN
8
SCL10/P04(SCL10/P80)
SDA10/P03(SDA10/P81)
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
SCL11/P30
SDA11/P50
POR/LVD
CONTROL
V
DD
,
V
SS
,
TOOLRxD/P11,
SERIAL ARRAY
UNIT1 (4ch)
EVDD0, EVSS0, TOOLTxD/P12
EVDD1 EVSS1
RESET CONTROL
ON-CHIP DEBUG
UART2
LINSEL
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
SCLA0/P60(SCLA0/P14)
TOOL0/P40
RxD3/P143
TxD3/P144
SDAA1/P63
SCLA1/P62
UART3
CSI20
SERIAL
INTERFACE IICA1
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
SCK20/P15
SI20/P14
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
HIGH-SPEED
ON-CHIP
OSCILLATOR
SO20/P13
SCK21/P70
SI21/P71
2
XT1/P123
CLOCK OUTPUT
CONTROL
XT2/EXCLKS/P124
CSI21
CSI30
SO21/P72
VOLTAGE
REGULATOR
MULTIPLIER&
DIVIDER,
MULITIPLY-
REGC
SCK30/P142
SI30/P143
CRC
SO30/P144
ACCUMULATOR
RxD2/P14 (RxD2/P76)
INTP0/P137
SCK31/P54
SI31/P53
DIRECT MEMORY
ACCESS CONTROL
CSI31
INTP1/P46(INTP1/P56),
INTP2/P47
2
SO31/P52
INTP3/P30(INTP3/P57),
INTP4/P31(INTP4/P146)
SCL20/P15
SDA20/P14
2
IIC20
IIC21
IIC30
IIC31
BCD
ADJUSTMENT
INTERRUPT
CONTROL
INTP5/P16(INTP5/P12)
SCL21/P70
SDA21/P71
WINDOW
WATCHDOG
TIMER
INTP6/P140(INTP6/P84),
INTP7/P141(INTP7/P85)
2
2
2
SCL30/P142
SDA30/P143
INTP8/P74(INTP8/P86),
INTP9/P75(INTP9/P87)
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
INTP10/P76(INTP10/P110),
INTP11/P77(INTP11/P111)
SCL31/P54
SDA31/P53
REAL-TIME
CLOCK
RTC1HZ/P30
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
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RL78/G13
1.5.14 128-pin products
1. OUTLINE
TIMER ARRAY
UNIT1 (8ch)
TIMER ARRAY
UNIT0 (8ch)
TI00/P00
TO00/P01
8
8
8
8
PORT 0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
P00 to P07
ch0
ch0
TI10/TO10/P64
TI11/TO11/P65
P10 to P17
P20 to P27
P30 to P37
TI01/TO01/P16
ch1
ch2
ch3
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P15)
TI12/TO12/P66
TI13/TO13/P67
TI14/TO14/P103
TI03/TO03/P31
(TI03/TO03/P14)
TI04/TO04/P42
(TI04/TO04/P13)
ch4
ch5
ch6
ch7
ch4
ch5
ch6
ch7
8
8
P40 to P47
P50 to P57
TI05/TO05/P46
(TI05/TO05/P12)
TI15/TO15/P104
TI16/TO16/P105
TI17/TO17/P106
TI06/TO06/P102
(TI06/TO06/P11)
TI07/TO07/P145
(TI07/TO07/P10)
RxD2/P14
8
8
P60 to P67
P70 to P77
(RxD2/P76)
SERIAL ARRAY
UNIT0 (4ch)
PORT 8
PORT 9
8
P80 to P87
RxD0/P11(RxD0/P16)
TxD0/P12(TxD0/P17)
UART0
UART1
CSI00
8
7
ANI0/P20 to ANI7/P27
ANI8/P150 to ANI14/P156
ANI16/P03, ANI17/P02,
ANI18/P147, ANI19/P120,
ANI20/P100, ANI21/37,
ANI22/P36, ANI23/P35,
ANI24/P117, ANI25/P116,
ANI26/P115
RxD1/P03(RxD1/P81)
TxD1/P02(TxD1/P82)
8
7
8
P90 to P97
11
SCK00/P10(SCK00/P55)
SI00/P11(SI00/P16)
SO00/P12(SO00/P17)
SCK01/P43
P100 to P106
P110 to P117
A/D CONVERTER
PORT 10
PORT 11
PORT 12
CSI01
CSI10
AVREFP/P20
AVREFM/P21
SI01/P44
4
4
P120, P125 to P127
P121 to P124
SO01/P45
SCK10/P04(SCK10/P80)
SI10/P03(SI10/P81)
CODE FLASH MEMORY
DATA FLASH MEMORY
P130
P137
RL78
CPU
CORE
SO10/P02(SO10/P82)
PORT 13
PORT 14
PORT 15
SCK11/P95
SI11/P96
CSI11
8
7
P140 to P147
P150 to P156
SO11/P97
SCL00/P10
SDA00/P11
IIC00
IIC01
IIC10
IIC11
SCL01/P43
SDA01/P44
KR0/P70 to
KR7/P77
KEY RETURN
8
SCL10/P04(SCL10/P80)
SDA10/P03(SDA10/P81)
RAM
POWER ON RESET/
VOLTAGE
DETECTOR
SCL11/P95
SDA11/P96
POR/LVD
CONTROL
V
DD
,
V
SS
,
TOOLRxD/P11,
SERIAL ARRAY
UNIT1 (4ch)
EVDD0, EVSS0, TOOLTxD/P12
EVDD1 EVSS1
RESET CONTROL
ON-CHIP DEBUG
UART2
LINSEL
SDAA0/P61(SDAA0/P13)
SERIAL
INTERFACE IICA0
RxD2/P14(RxD2/P76)
TxD2/P13(TxD2/P77)
SCLA0/P60(SCLA0/P14)
TOOL0/P40
SDAA1/P63
SCLA1/P62
RxD3/P143
TxD3/P144
SERIAL
INTERFACE IICA1
UART3
CSI20
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
SCK20/P15
SI20/P14
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P31),
PCLBUZ1/P141
(PCLBUZ1/P55)
HIGH-SPEED
ON-CHIP
OSCILLATOR
SO20/P13
SCK21/P70
SI21/P71
2
XT1/P123
CLOCK OUTPUT
CONTROL
XT2/EXCLKS/P124
CSI21
CSI30
SO21/P72
MULTIPLIER&
DIVIDER,
MULITIPLY-
VOLTAGE
REGULATOR
CRC
SCK30/P142
SI30/P143
REGC
ACCUMULATOR
SO30/P144
RxD2/P14 (RxD2/P76)
INTP0/P137
SCK31/P54
SI31/P53
DIRECT MEMORY
ACCESS CONTROL
CSI31
INTP1/P46 (INTP1/P56),
INTP2/P47
2
SO31/P52
INTP3/P30 (INTP3/P57),
INTP4/P31 (INTP4/P146)
SCL20/P15
SDA20/P14
BCD
ADJUSTMENT
2
IIC20
IIC21
IIC30
IIC31
INTERRUPT
CONTROL
INTP5/P16 (INTP5/P12)
WINDOW
WATCHDOG
TIMER
SCL21/P70
SDA21/P71
INTP6/P140 (INTP6/P84),
INTP7/P141 (INTP7/P85)
2
2
SCL30/P142
SDA30/P143
INTP8/P74 (INTP8/P86),
INTP9/P75 (INTP9/P87)
LOW-SPEED
ON-CHIP
OSCILLATOR
12-BIT INTERVAL
TIMER
INTP10/P76 (INTP10/P110),
INTP11/P77 (INTP11/P111)
SCL31/P54
SDA31/P53
2
REAL-TIME
CLOCK
RTC1HZ/P30
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR). Refer to Figure 4-8 Format of Peripheral I/O Redirection Register
(PIOR) in the RL78/G13 User’s Manual.
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RL78/G13
1.6 Outline of Functions
1. OUTLINE
[20-pin, 24-pin, 25-pin, 30-pin, 32-pin, 36-pin products]
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
20-pin
24-pin
25-pin
30-pin
32-pin
36-pin
Code flash memory (KB)
Data flash memory (KB)
RAM (KB)
16 to 64
16 to 64
16 to 64
16 to 128
16 to 128
16 to 128
4
4
4
4 to 8
4 to 8
4 to 8
2 to 4Note1
2 to 4Note1
2 to 4Note1
2 to 12Note1
2 to 12Note1
2 to 12Note1
Address space
1 MB
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Main system High-speed system
clock
clock
HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
High-speed on-chip
oscillator
Subsystem clock
Low-speed on-chip oscillator
General-purpose registers
15 kHz (TYP.)
(8-bit register 8) 4 banks
Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
Instruction set
I/O port
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
16
13
20
15
21
15
26
21
28
22
32
26
CMOS I/O
(N-ch O.D. I/O (N-ch O.D. I/O (N-ch O.D. I/O (N-ch O.D. I/O (N-ch O.D. I/O (N-ch O.D. I/O
[VDD withstand [VDD withstand [VDD withstand [VDD withstand [VDD withstand [VDD withstand
voltage]: 5)
voltage]: 6)
voltage]: 6)
voltage]: 9)
voltage]: 9)
voltage]: 10)
CMOS input
3
3
3
3
3
3
CMOS output
1
2
N-ch O.D. I/O
2
2
3
3
(withstand voltage: 6 V)
Timer
16-bit timer
8 channels
Watchdog timer
Real-time clock (RTC)
12-bit interval timer (IT)
Timer output
1 channel
1 channelNote 2
1 channel
3 channels
4 channels
4 channels (PWM outputs: 3 Note 3),
8 channels (PWM outputs: 7 Note 3
(PWM outputs: (PWM outputs: 3Note 3
)
Note 4
)
2 Note 3
)
RTC output
Notes 1. The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F100xD, R5F101xD (x = 6 to 8, A to C): Start address FF300H
R5F100xE, R5F101xE (x = 6 to 8, A to C): Start address FEF00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library
for RL78 Family (R20UT2944).
2. Only the constant-period interrupt function when the low-speed on-chip oscillator clock (fIL) is
selected
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RL78/G13
1. OUTLINE
3. The number of PWM outputs varies depending on the setting of channels in use (the number of
masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s
Manual).
4. When setting to PIOR = 1
(2/2)
Item
20-pin
24-pin
25-pin
30-pin
32-pin
36-pin
Clock output/buzzer output
1
1
2
2
2
2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
8/10-bit resolution A/D converter
Serial interface
6 channels
6 channels
6 channels
8 channels
8 channels
8 channels
[20-pin, 24-pin, 25-pin products]
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
[30-pin, 32-pin products]
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel
[36-pin products]
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
I2C bus
1 channel
1 channel
1 channel
1 channel
1 channel
Multiplier and divider/multiply-
accumulator
16 bits 16 bits = 32 bits (Unsigned or signed)
32 bits 32 bits = 32 bits (Unsigned)
16 bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
23
3
24
5
24
5
27
6
27
6
27
6
sources
External
Key interrupt
Reset
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access
Power-on-reset circuit
Voltage detector
Power-on-reset:
Power-down-reset: 1.50 V (TYP.)
1.51 V (TYP.)
Rising edge :
Falling edge :
1.67 V to 4.06 V (14 stages)
1.63 V to 3.98 V (14 stages)
On-chip debug function
Power supply voltage
Provided
VDD = 1.6 to 5.5 V (TA = -40 to +85°C)
DD = 2.4 to 5.5 V (TA = -40 to +105°C)
<R>
V
Operating ambient temperature
TA = 40 to +85°C (A: Consumer applications, D: Industrial applications )
TA = 40 to +105°C (G: Industrial applications)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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RL78/G13
1. OUTLINE
[40-pin, 44-pin, 48-pin, 52-pin, 64-pin products]
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
40-pin
44-pin
48-pin
52-pin
64-pin
Code flash memory (KB)
Data flash memory (KB)
RAM (KB)
16 to 192
16 to 512
16 to 512
32 to 512
32 to 512
4 to 8
2 to 16Note1
1 MB
4 to 8
4 to 8
4 to 8
4 to 8
2 to 32Note1
2 to 32Note1
2 to 32Note1
2 to 32Note1
Address space
Main system High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
clock
clock
High-speed on-chip
oscillator
HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator
General-purpose registers
15 kHz (TYP.)
(8-bit register 8) 4 banks
Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
I/O port
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
36
40
44
48
58
CMOS I/O
28
31
34
38
48
(N-ch O.D. I/O
[VDD withstand
voltage]: 10)
(N-ch O.D. I/O
[VDD withstand
voltage]: 10)
(N-ch O.D. I/O
[VDD withstand
voltage]: 11)
(N-ch O.D. I/O
[VDD withstand
voltage]: 13)
(N-ch O.D. I/O
[VDD withstand
voltage]: 15)
CMOS input
5
3
5
4
5
1
4
5
1
4
5
1
4
CMOS output
N-ch O.D. I/O
(withstand voltage: 6 V)
Timer
16-bit timer
8 channels
1 channel
1 channel
1 channel
Watchdog timer
Real-time clock (RTC)
12-bit interval timer (IT)
Timer output
4 channels (PWM
outputs: 3 Note 2),
5 channels (PWM outputs: 4 Note 2),
8 channels (PWM
Note 3
8 channels (PWM outputs: 7 Note 2
)
outputs: 7Note 2
)
8 channels (PWM
Note 3
outputs: 7 Note 2
)
RTC output
1 channel
1 Hz (subsystem clock: fSUB = 32.768 kHz)
Notes 1. The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F100xD, R5F101xD (x = E to G, J, L): Start address FF300H
R5F100xE, R5F101xE (x = E to G, J, L): Start address FEF00H
R5F100xJ, R5F101xJ (x = F, G, J, L):
R5F100xL, R5F101xL (x = F, G, J, L):
Start address FAF00H
Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library
for RL78 Family (R20UT2944).
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RL78/G13
1. OUTLINE
2. The number of PWM outputs varies depending on the setting of channels in use (the number of
masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s
Manual).
3. When setting to PIOR = 1
(2/2)
Item
40-pin
44-pin
48-pin
52-pin
64-pin
2
2
2
2
2
Clock output/buzzer output
2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
9 channels
10 channels
10 channels
12 channels
12 channels
[40-pin, 44-pin products]
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
[48-pin, 52-pin products]
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
[64-pin products]
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
I2C bus
1 channel
1 channel
1 channel
1 channel
1 channel
16 bits 16 bits = 32 bits (Unsigned or signed)
32 bits 32 bits = 32 bits (Unsigned)
Multiplier and divider/multiply-
accumulator
16 bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored
Internal
External
27
27
7
27
10
6
27
27
interrupt sources
7
12
8
13
8
Key interrupt
Reset
4
4
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access
Power-on-reset circuit
Voltage detector
Power-on-reset: 1.51 V (TYP.)
Power-down-reset: 1.50 V (TYP.)
Rising edge :
Falling edge :
1.67 V to 4.06 V (14 stages)
1.63 V to 3.98 V (14 stages)
On-chip debug function
Power supply voltage
Provided
VDD = 1.6 to 5.5 V (TA = -40 to +85°C)
DD = 2.4 to 5.5 V (TA = -40 to +105°C)
V
TA = 40 to +85°C (A: Consumer applications, D: Industrial applications)
TA = 40 to +105°C (G: Industrial applications)
<R>
Operating ambient temperature
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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Page 51 of 196
RL78/G13
1. OUTLINE
[80-pin, 100-pin, 128-pin products]
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
80-pin
R5F101Mx
100-pin
R5F100Px R5F101Px
128-pin
R5F100Sx R5F101Sx
R5F100Mx
Code flash memory (KB)
Data flash memory (KB)
RAM (KB)
96 to 512
96 to 512
192 to 512
8
8
8
8 to 32 Note 1
8 to 32 Note 1
16 to 32 Note 1
Address space
1 MB
Main system High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
HS (High-speed main) mode: 1 to 20 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
clock
clock
High-speed on-chip
oscillator
HS (High-speed main) mode: 1 to 32 MHz (VDD = 2.7 to 5.5 V),
HS (High-speed main) mode: 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode: 1 to 8 MHz (VDD = 1.8 to 5.5 V),
LV (Low-voltage main) mode: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
XT1 (crystal) oscillation, external subsystem clock input (EXCLKS)
32.768 kHz
Low-speed on-chip oscillator
General-purpose register
15 kHz (TYP.)
(8-bit register 8) 4 banks
Minimum instruction execution time 0.03125 s (High-speed on-chip oscillator: fIH = 32 MHz operation)
0.05 s (High-speed system clock: fMX = 20 MHz operation)
30.5 s (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
I/O port
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.
Total
74
92
120
CMOS I/O
64
82
110
(N-ch O.D. I/O [EVDD withstand (N-ch O.D. I/O [EVDD withstand (N-ch O.D. I/O [EVDD withstand
voltage]: 21)
voltage]: 24)
voltage]: 25)
CMOS input
5
1
4
5
1
4
5
1
4
CMOS output
N-ch O.D. I/O
(withstand voltage: 6
V)
Timer
16-bit timer
12 channels
1 channel
1 channel
1 channel
12 channels
1 channel
1 channel
1 channel
16 channels
1 channel
1 channel
1 channel
Watchdog timer
Real-time clock (RTC)
12-bit interval timer (IT)
Timer output
12 channels
12 channels
(PWM outputs: 10 Note 2
16 channels
(PWM outputs: 14Note 2
)
(PWM outputs: 10 Note 2
1 channel
)
)
RTC output
1 Hz (subsystem clock: fSUB = 32.768 kHz)
Notes 1. The flash library uses RAM in self-programming and rewriting of the data flash memory.
The target products and start address of the RAM areas used by the flash library are shown below.
R5F100xJ, R5F101xJ (x = M, P): Start address FAF00H
R5F100xL, R5F101xL (x = M, P, S): Start address F7F00H
For the RAM areas used by the flash library, see Self RAM list of Flash Self-Programming Library
for RL78 Family (R20UT2944).
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RL78/G13
1. OUTLINE
2. The number of PWM outputs varies depending on the setting of channels in use (the number of
masters and slaves) (see 6.9.3 Operation as multiple PWM output function in the RL78/G13 User’s
Manual).
(2/2)
Item
80-pin
2
100-pin
R5F100Px R5F101Px
128-pin
R5F100Sx R5F101Sx
R5F100Mx
R5F101Mx
Clock output/buzzer output
2
2
2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
17 channels
20 channels
26 channels
[80-pin, 100-pin, 128-pin products]
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel
CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel
I2C bus
2 channels
2 channels
2 channels
Multiplier and divider/multiply-
accumulator
16 bits 16 bits = 32 bits (Unsigned or signed)
32 bits 32 bits = 32 bits (Unsigned)
16 bits 16 bits + 32 bits = 32 bits (Unsigned or signed)
4 channels
DMA controller
Vectored
Internal
External
37
13
8
37
13
8
41
13
8
interrupt sources
Key interrupt
Reset
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note
Internal reset by RAM parity error
Internal reset by illegal-memory access
Power-on-reset circuit
Voltage detector
Power-on-reset: 1.51 V (TYP.)
Power-down-reset: 1.50 V (TYP.)
Rising edge :
Falling edge :
1.67 V to 4.06 V (14 stages)
1.63 V to 3.98 V (14 stages)
On-chip debug function
Power supply voltage
Provided
VDD = 1.6 to 5.5 V (TA = -40 to +85°C)
VDD = 2.4 to 5.5 V (TA = -40 to +105°C)
<R>
Operating ambient temperature
TA = 40 to +85°C (A: Consumer applications, D: Industrial applications )
TA = 40 to +105°C (G: Industrial applications)
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
This chapter describes the following electrical specifications.
Target products A: Consumer applications TA = −40 to +85°C
R5F100xxAxx, R5F101xxAxx
D: Industrial applications TA = −40 to +85°C
R5F100xxDxx, R5F101xxDxx
G: Industrial applications when TA = −40 to +105°C products is used in the range of TA = −40 to
+85°C
R5F100xxGxx
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times of the
flash memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and EVDD1
with VDD, or replace EVSS0 and EVSS1 with VSS.
3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions for
each product.
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RL78/G13
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25C) (1/2)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter
Symbols
Conditions
Ratings
Unit
V
Supply voltage
VDD
0.5 to +6.5
0.5 to +6.5
0.5 to +0.3
EVDD0, EVDD1 EVDD0 = EVDD1
EVSS0, EVSS1 EVSS0 = EVSS1
V
V
REGC pin input voltage VIREGC
REGC
0.3 to +2.8
and 0.3 to VDD +0.3Note 1
V
Input voltage
VI1
P00 to P07, P10 to P17, P30 to P37, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
0.3 to EVDD0 +0.3
and 0.3 to VDD +0.3Note 2
V
VI2
P60 to P63 (N-ch open-drain)
0.3 to +6.5
0.3 to VDD +0.3Note 2
V
V
VI3
P20 to P27, P121 to P124, P137, P150 to P156,
EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P07, P10 to P17, P30 to P37, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to P117, P120,
P125 to P127, P130, P140 to P147
0.3 to EVDD0 +0.3
and 0.3 to VDD +0.3Note 2
V
VO2
P20 to P27, P150 to P156
ANI16 to ANI26
0.3 to VDD +0.3Note 2
V
V
Analog input voltage
VAI1
0.3 to EVDD0 +0.3
and 0.3 to AVREF(+) +0.3Notes 2, 3
VAI2
ANI0 to ANI14
0.3 to VDD +0.3
and 0.3 to AVREF(+) +0.3Notes 2, 3
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2. AVREF (+) : + side reference voltage of the A/D converter.
3.
VSS : Reference voltage
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter Symbols
Output current, high
Conditions
Ratings
Unit
mA
IOH1
Per pin
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P130, P140 to
P147
40
Total of all pins P00 to P04, P07, P32 to P37,
70
mA
mA
170 mA
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to
P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100, P101,
P110 to P117, P146, P147
100
IOH2
Per pin
P20 to P27, P150 to P156
0.5
2
mA
mA
mA
Total of all pins
Per pin
Output current, low
IOL1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P130, P140 to
P147
40
Total of all pins P00 to P04, P07, P32 to P37,
70
mA
mA
170 mA
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to
P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100, P101,
P110 to P117, P146, P147
100
IOL2
Per pin
P20 to P27, P150 to P156
1
5
mA
mA
C
Total of all pins
Operating ambient
temperature
TA
In normal operation mode
40 to +85
In flash memory programming mode
Storage temperature
Tstg
65 to +150
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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RL78/G13
2.2 Oscillator Characteristics
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.2.1 X1, XT1 oscillator characteristics
(TA = 40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V)
Parameter
Resonator
Conditions
2.7 V VDD 5.5 V
2.4 V VDD 2.7 V
1.8 V VDD 2.4 V
1.6 V VDD 1.8 V
MIN.
1.0
1.0
1.0
1.0
32
TYP.
MAX.
20.0
16.0
8.0
Unit
MHz
MHz
MHz
MHz
kHz
X1 clock oscillation
frequency (fX)Note
Ceramic resonator/
crystal resonator
4.0
XT1 clock oscillation
frequency (fX)Note
Crystal resonator
32.768
35
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and
the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator.
2.2.2 On-chip oscillator characteristics
(TA = 40 to +85C, 1.6 V VDD 5.5 V, VSS = 0 V)
Oscillators
Parameters
Conditions
MIN.
1
TYP. MAX.
32
Unit
High-speed on-chip oscillator
clock frequencyNotes 1, 2
fIH
MHz
High-speed on-chip oscillator
clock frequency accuracy
20 to +85 C
40 to 20 C
1.8 V VDD 5.5 V
1.6 V VDD < 1.8 V
1.8 V VDD 5.5 V
1.6 V VDD < 1.8 V
1.0
5.0
1.5
5.5
+1.0
+5.0
%
%
+1.5
%
+5.5
%
Low-speed on-chip oscillator
clock frequency
fIL
15
kHz
Low-speed on-chip oscillator
clock frequency accuracy
15
+15
%
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution
time.
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RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
mA
Output current,
highNote 1
IOH1
Per pin for P00 to P07, P10 to P17,
P30 to P37, P40 to P47, P50 to P57, P64
to P67, P70 to P77, P80 to P87, P90 to
P97, P100 to P106,
1.6 V EVDD0 5.5 V
10.0
Note 2
P110 to P117, P120, P125 to P127,
P130, P140 to P147
Total of P00 to P04, P07, P32 to P37,
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
1.8 V EVDD0 < 2.7 V
1.6 V EVDD0 < 1.8 V
55.0
10.0
5.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
(When duty 70%Note 3
)
2.5
Total of P05, P06, P10 to P17, P30, P31, 4.0 V EVDD0 5.5 V
P50 to P57, P64 to P67, P70 to P77, P80
80.0
19.0
10.0
5.0
2.7 V EVDD0 < 4.0 V
to P87, P90 to P97, P100, P101, P110 to
1.8 V EVDD0 < 2.7 V
P117, P146, P147
(When duty 70% Note 3
)
1.6 V EVDD0 < 1.8 V
Total of all pins
1.6 V EVDD0 5.5 V
135.0
(When duty 70% Note 3
)
Note 4
IOH2
Per pin for P20 to P27, P150 to P156
1.6 V VDD 5.5 V
1.6 V VDD 5.5 V
0.1Note 2 mA
1.5 mA
Total of all pins
(When duty 70% Note 3
)
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
EVDD1, VDD pins to an output pin.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
4. The applied current for the products for industrial application (R5F100xxDxx, R5F101xxDxx,
R5F100xxGxx) is 100 mA.
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and
P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
mA
Output current,
lowNote 1
IOL1
Per pin for P00 to P07, P10 to P17,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
20.0Note 2
P110 to P117, P120, P125 to P127,
P130, P140 to P147
Per pin for P60 to P63
15.0Note 2
70.0
15.0
9.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total of P00 to P04, P07, P32 to
P37,
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
1.8 V EVDD0 < 2.7 V
1.6 V EVDD0 < 1.8 V
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
(When duty 70%Note 3
4.5
)
Total of P05, P06, P10 to P17, P30, 4.0 V EVDD0 5.5 V
P31, P50 to P57, P60 to P67,
80.0
35.0
20.0
10.0
2.7 V EVDD0 < 4.0 V
P70 to P77, P80 to P87, P90 to P97,
1.8 V EVDD0 < 2.7 V
P100, P101, P110 to P117, P146,
1.6 V EVDD0 < 1.8 V
P147
(When duty 70%Note 3
)
Total of all pins
(When duty 70%Note 3
150.0
mA
)
IOL2
Per pin for P20 to P27, P150 to P156
0.4Note 2
5.0
mA
mA
Total of all pins
1.6 V VDD 5.5 V
(When duty 70%Note 3
)
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS0, EVSS1 and VSS pin.
2. However, do not exceed the total current value.
3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
Input voltage,
high
VIH1
P00 to P07, P10 to P17, P30 to P37, Normal input buffer 0.8EVDD0
P40 to P47, P50 to P57, P64 to P67,
EVDD0
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
VIH2
P01, P03, P04, P10, P11,
P13 to P17, P43, P44, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V
TTL input buffer
3.3 V
TTL input buffer
1.6 V
2.2
2.0
1.5
EVDD0
EVDD0
EVDD0
V
V
V
EVDD0
5.5 V
4.0 V
3.3 V
EVDD0
EVDD0
VIH3
VIH4
VIH5
VIL1
P20 to P27, P150 to P156
P60 to P63
0.7VDD
0.7EVDD0
0.8VDD
0
VDD
6.0
V
V
V
V
P121 to P124, P137, EXCLK, EXCLKS, RESET
VDD
Input voltage,
low
P00 to P07, P10 to P17, P30 to P37, Normal input buffer
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
0.2EVDD0
VIL2
P01, P03, P04, P10, P11,
P13 to P17, P43, P44, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V
TTL input buffer
3.3 V
TTL input buffer
1.6 V
0
0
0
0.8
0.5
V
V
V
EVDD0
5.5 V
4.0 V
3.3 V
EVDD0
0.32
EVDD0
VIL3
VIL4
VIL5
P20 to P27, P150 to P156
P60 to P63
0
0
0
0.3VDD
0.3EVDD0
0.2VDD
V
V
V
P121 to P124, P137, EXCLK, EXCLKS, RESET
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55,
P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5)
Items
Symbol
Conditions
P00 to P07, P10 to P17, P30 to
MIN.
TYP.
MAX.
Unit
V
Output voltage,
high
VOH1
4.0 V
EVDD0
5.5 V, EVDD0
P37, P40 to P47, P50 to P57, P64
to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to
P117, P120, P125 to P127, P130,
P140 to P147
I
OH1
=
10.0 mA
1.5
4.0 V
EVDD0
5.5 V, EVDD0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
I
OH1
=
3.0 mA
0.7
2.7 V
EVDD0
5.5 V, EVDD0
I
OH1
=
2.0 mA
0.6
1.8 V
EVDD0
5.5 V, EVDD0
I
OH1
=
1.5 mA
0.5
1.6 V
EVDD0 < 5.5 V, EVDD0
1.0 mA
I
OH1
=
0.5
VOH2
P20 to P27, P150 to P156
1.6 V VDD 5.5 V, VDD 0.5
IOH2 = 100 A
Output voltage,
low
VOL1
P00 to P07, P10 to P17, P30 to
P37, P40 to P47, P50 to P57, P64
to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to
P117, P120, P125 to P127, P130,
P140 to P147
4.0 V
EVDD0
5.5 V,
5.5 V,
5.5 V,
5.5 V,
5.5 V,
1.3
0.7
0.6
0.4
0.4
0.4
0.4
2.0
0.4
0.4
0.4
0.4
I
OL1 = 20 mA
4.0 V
EVDD0
I
OL1 = 8.5 mA
2.7 V
EVDD0
I
OL1 = 3.0 mA
2.7 V
EVDD0
I
OL1 = 1.5 mA
1.8 V
EVDD0
I
OL1 = 0.6 mA
1.6 V
EVDD0 < 5.5 V,
I
OL1 = 0.3 mA
VOL2
P20 to P27, P150 to P156
P60 to P63
1.6 V VDD 5.5 V,
IOL2 = 400 A
VOL3
4.0 V
EVDD0
5.5 V,
5.5 V,
5.5 V,
5.5 V,
I
OL3 = 15.0 mA
4.0 V
EVDD0
I
OL3 = 5.0 mA
2.7 V
EVDD0
I
OL3 = 3.0 mA
1.8 V
EVDD0
I
OL3 = 2.0 mA
1.6 V
EVDD0 < 5.5 V,
I
OL3 = 1.0 mA
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and
P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 61 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
1
Unit
Input leakage
current, high
ILIH1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
VI = EVDD0
A
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P140 to P147
ILIH2
P20 to P27, P137,
VI = VDD
VI = VDD
1
1
A
A
P150 to P156, RESET
ILIH3
P121 to P124
In input port or
external clock
input
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
In resonator
connection
10
A
A
Input leakage
current, low
ILIL1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
VI = EVSS0
1
P125 to P127, P140 to P147
ILIL2
P20 to P27, P137,
VI = VSS
VI = VSS
1
1
A
A
P150 to P156, RESET
ILIL3
P121 to P124
In input port or
external clock
input
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
In resonator
connection
10
A
k
On-chip pll-up
resistance
RU
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
VI = EVSS0, In input port
10
20
100
P125 to P127, P140 to P147
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 62 of 196
RL78/G13
2.3.2 Supply current characteristics
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
(TA = 40 to +85C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) (1/2)
Parameter Symbol
Conditions
fIH = 32 MHzNote 3
MIN.
TYP.
2.1
2.1
4.6
4.6
3.7
3.7
2.7
2.7
1.2
1.2
MAX.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply
IDD1
Operating HS (high-
Basic
operation
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
VDD = 2.0 V
currentNote 1
mode
speed main)
modeNote 5
Normal
operation
7.0
7.0
5.5
5.5
4.0
4.0
1.8
1.8
fIH = 24 MHzNote 3
fIH = 16 MHzNote 3
fIH = 8 MHzNote 3
Normal
operation
Normal
operation
LS (low-
Normal
operation
speed main)
modeNote 5
LV (low-
voltage
fIH = 4 MHzNote 3
Normal
operation
VDD = 3.0 V
VDD = 2.0 V
1.2
1.2
1.7
1.7
mA
mA
main) mode
Note 5
HS (high-
fMX = 20 MHzNote 2
VDD = 5.0 V
,
,
,
,
Normal
operation
Square wave input
3.0
3.2
4.6
4.8
mA
mA
speed main)
Resonator
connection
modeNote 5
fMX = 20 MHzNote 2
VDD = 3.0 V
Normal
operation
Square wave input
3.0
3.2
4.6
4.8
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 5.0 V
Normal
operation
Square wave input
1.9
1.9
2.7
2.7
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 3.0 V
Normal
operation
Square wave input
1.9
1.9
2.7
2.7
mA
Resonator
connection
mA
LS (low-
fMX = 8 MHzNote 2
VDD = 3.0 V
,
Normal
operation
Square wave input
1.1
1.1
1.7
1.7
mA
speed main)
Resonator
connection
mA
modeNote 5
fMX = 8 MHzNote 2
VDD = 2.0 V
,
Normal
operation
Square wave input
1.1
1.1
1.7
1.7
mA
Resonator
connection
mA
Subsystem fSUB = 32.768 kHz Normal
Square wave input
4.1
4.2
4.9
5.0
A
A
Note 4
clock
operation
Resonator
connection
operation
TA = 40C
fSUB = 32.768 kHz Normal
Square wave input
4.1
4.2
4.9
5.0
A
A
Note 4
operation
Resonator
connection
TA = +25C
fSUB = 32.768 kHz Normal
Square wave input
4.2
4.3
5.5
5.6
A
A
Note 4
operation
Resonator
connection
TA = +50C
fSUB = 32.768 kHz Normal
Square wave input
4.3
4.4
6.3
6.4
A
A
Note 4
operation
Resonator
connection
TA = +70C
fSUB = 32.768 kHz Normal
Square wave input
4.6
4.7
7.7
7.8
A
A
Note 4
operation
Resonator
connection
TA = +85C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 63 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-
bit interval timer, and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 64 of 196
RL78/G13
(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
(TA = 40 to +85C, 1.6 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) (2/2)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter Symbol
Conditions
MIN.
TYP.
0.54
0.54
0.44
0.44
0.40
0.40
260
MAX.
1.63
1.63
1.28
1.28
1.00
1.00
530
Unit
mA
mA
mA
mA
mA
mA
A
fIH = 32 MHzNote 4
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
VDD = 2.0 V
HS (high-
Supply
IDD2
Note 2
HALT
mode
speed main)
current
modeNote 7
Note 1
fIH = 24 MHzNote 4
fIH = 16 MHzNote 4
fIH = 8 MHzNote 4
LS (low-
speed main)
modeNote 7
260
530
A
fIH = 4 MHzNote 4
VDD = 3.0 V
VDD = 2.0 V
420
420
640
640
A
A
LV (low-
voltage
main) mode
Note 7
fMX = 20 MHzNote 3
VDD = 5.0 V
,
,
,
,
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
0.28
0.45
0.28
0.45
0.19
0.26
0.19
0.26
95
1.00
1.17
1.00
1.17
0.60
0.67
0.60
0.67
330
mA
mA
mA
mA
mA
mA
mA
mA
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
HS (high-
speed main)
modeNote 7
fMX = 20 MHzNote 3
VDD = 3.0 V
fMX = 10 MHzNote 3
VDD = 5.0 V
fMX = 10 MHzNote 3
VDD = 3.0 V
LS (low-
fMX = 8 MHzNote 3
VDD = 3.0 V
,
speed main)
modeNote 7
145
380
fMX = 8 MHzNote 3
,
95
330
VDD = 2.0 V
145
380
Subsystem fSUB = 32.768 kHzNote 5
0.25
0.44
0.30
0.49
0.37
0.56
0.53
0.72
0.82
1.01
0.18
0.23
0.30
0.46
0.75
0.57
0.76
0.57
0.76
1.17
1.36
1.97
2.16
3.37
3.56
0.50
0.50
1.10
1.90
3.30
clock
TA = 40C
operation
fSUB = 32.768 kHzNote 5
TA = +25C
fSUB = 32.768 kHzNote 5
TA = +50C
fSUB = 32.768 kHzNote 5
TA = +70C
fSUB = 32.768 kHzNote 5
TA = +85C
Note 6
IDD3
STOP
modeNote 8
TA = 40C
TA = +25C
TA = +50C
TA = +70C
TA = +85C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 65 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 66 of 196
RL78/G13
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter Symbol
Conditions
fIH = 32 MHzNote 3
MIN.
TYP.
2.3
2.3
5.2
5.2
4.1
4.1
3.0
3.0
1.3
1.3
MAX.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply
IDD1
Operating HS (high-
Basic
operation
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
VDD = 2.0 V
current
mode
speed main)
Note 1
modeNote 5
Normal
operation
8.5
8.5
6.6
6.6
4.7
4.7
2.1
2.1
fIH = 24 MHzNote 3
fIH = 16 MHzNote 3
fIH = 8 MHzNote 3
Normal
operation
Normal
operation
LS (low-
Normal
operation
speed main)
modeNote 5
LV (low-
voltage
fIH = 4 MHzNote 3
Normal
operation
VDD = 3.0 V
VDD = 2.0 V
1.3
1.3
1.8
1.8
mA
mA
main) mode
Note 5
HS (high-
fMX = 20 MHzNote 2
VDD = 5.0 V
,
Normal
operation
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
3.4
3.6
3.4
3.6
2.1
2.1
2.1
2.1
1.2
1.2
1.2
1.2
4.8
4.9
5.5
5.7
5.5
5.7
3.2
3.2
3.2
3.2
2.0
2.0
2.0
2.0
5.9
6.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
speed main)
modeNote 5
fMX = 20 MHzNote 2
,
,
,
Normal
operation
VDD = 3.0 V
fMX = 10 MHzNote 2
VDD = 5.0 V
fMX = 10 MHzNote 2
Normal
operation
Normal
operation
VDD = 3.0 V
LS (low-
fMX = 8 MHzNote 2
VDD = 3.0 V
,
Normal
operation
speed main)
modeNote 5
fMX = 8 MHzNote 2
,
Normal
operation
VDD = 2.0 V
Subsystem fSUB = 32.768 kHz
clock
operation
Normal
operation
Note 4
A
TA = 40C
fSUB = 32.768 kHz
Normal
operation
Square wave input
4.9
5.0
5.9
6.0
A
A
Note 4
Resonator connection
TA = +25C
fSUB = 32.768 kHz
Normal
operation
Square wave input
5.0
5.1
7.6
7.7
A
A
Note 4
Resonator connection
TA = +50C
fSUB = 32.768 kHz
Normal
operation
Square wave input
5.2
5.3
9.3
9.4
A
A
Note 4
Resonator connection
TA = +70C
fSUB = 32.768 kHz
Normal
operation
Square wave input
5.7
5.8
13.3
13.4
A
A
Note 4
Resonator connection
TA = +85C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 67 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the
MAX. column include the peripheral operation current. However, not including the current flowing into the
A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during
data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit
interval timer and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 68 of 196
RL78/G13
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter Symbol
Conditions
fIH = 32 MHzNote 4
MIN.
TYP.
0.62
0.62
0.50
0.50
0.44
0.44
290
MAX.
1.86
1.86
1.45
1.45
1.11
1.11
620
Unit
mA
mA
mA
mA
mA
mA
A
Supply
current
IDD2
HALT
mode
HS (high-
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
VDD = 2.0 V
Note 2
speed main)
Note 1
modeNote 7
fIH = 24 MHzNote 4
fIH = 16 MHzNote 4
fIH = 8 MHzNote 4
LS (low-
speed main)
290
620
A
modeNote 7
LV (low-
voltage
fIH = 4 MHzNote 4
VDD = 3.0 V
VDD = 2.0 V
440
440
680
680
A
A
main) mode
Note 7
HS (high-
fMX = 20 MHzNote 3
VDD = 5.0 V
,
,
,
,
Square wave input
0.31
0.48
1.08
1.28
mA
mA
speed main)
Resonator
connection
modeNote 7
fMX = 20 MHzNote 3
VDD = 3.0 V
Square wave input
0.31
0.48
1.08
1.28
mA
mA
Resonator
connection
fMX = 10 MHzNote 3
VDD = 5.0 V
Square wave input
0.21
0.28
0.63
0.71
mA
mA
Resonator
connection
fMX = 10 MHzNote 3
VDD = 3.0 V
Square wave input
0.21
0.28
0.63
0.71
mA
mA
Resonator
connection
LS (low-
fMX = 8 MHzNote 3
VDD = 3.0 V
,
Square wave input
110
160
360
420
A
A
speed main)
Resonator
connection
modeNote 7
fMX = 8 MHzNote 3
VDD = 2.0 V
,
Square wave input
110
160
360
420
A
A
Resonator
connection
Subsystem fSUB = 32.768 kHzNote 5
Square wave input
0.28
0.47
0.61
0.80
A
A
clock
TA = 40C
Resonator
connection
operation
fSUB = 32.768 kHzNote 5
Square wave input
0.34
0.53
0.61
0.80
A
A
TA = +25C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.41
0.60
2.30
2.49
A
A
TA = +50C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.64
0.83
4.03
4.22
A
A
TA = +70C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
1.09
1.28
8.04
8.23
A
A
TA = +85C
Resonator
connection
Note 6
IDD3
STOP
TA = 40C
TA = +25C
TA = +50C
TA = +70C
TA = +85C
0.19
0.25
0.32
0.55
1.00
0.52
0.52
2.21
3.94
7.95
A
A
A
A
A
modeNote 8
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 69 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the
MAX. column include the peripheral operation current . However, not including the current flowing into
the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing
during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 70 of 196
RL78/G13
(3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter Symbol
Conditions
fIH = 32 MHzNote 3
MIN.
TYP.
2.6
2.6
6.1
6.1
4.8
4.8
3.5
3.5
1.5
1.5
MAX.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Supply
IDD1
Operating HS (high-
Basic
operation
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
VDD = 2.0 V
currentNote 1
mode
speed main)
modeNote 5
Normal
operation
9.5
9.5
7.4
7.4
5.3
5.3
2.3
2.3
fIH = 24 MHzNote 3
fIH = 16 MHzNote 3
fIH = 8 MHzNote 3
Normal
operation
Normal
operation
LS (low-
Normal
operation
speed main)
modeNote 5
LV (low-
voltage
fIH = 4 MHzNote 3
Normal
operation
VDD = 3.0 V
VDD = 2.0 V
1.5
1.5
2.0
2.0
mA
mA
main) mode
Note 5
HS (high-
fMX = 20 MHzNote 2
VDD = 5.0 V
,
,
,
,
Normal
operation
Square wave input
3.9
4.1
6.1
6.3
mA
mA
speed main)
Resonator
connection
modeNote 5
fMX = 20 MHzNote 2
VDD = 3.0 V
Normal
operation
Square wave input
3.9
4.1
6.1
6.3
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 5.0 V
Normal
operation
Square wave input
2.5
2.5
3.7
3.7
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 3.0 V
Normal
operation
Square wave input
2.5
2.5
3.7
3.7
mA
Resonator
connection
mA
LS (low-
fMX = 8 MHzNote 2
VDD = 3.0 V
,
Normal
operation
Square wave input
1.4
1.4
2.2
2.2
mA
speed main)
Resonator
connection
mA
modeNote 5
fMX = 8 MHzNote 2
VDD = 2.0 V
,
Normal
operation
Square wave input
1.4
1.4
2.2
2.2
mA
Resonator
connection
mA
Subsystem fSUB = 32.768 kHz Normal
Square wave input
5.4
5.5
6.5
6.6
A
A
Note 4
clock
operation
Resonator
connection
operation
TA = 40C
fSUB = 32.768 kHz Normal
Square wave input
5.5
5.6
6.5
6.6
A
A
Note 4
operation
Resonator
connection
TA = +25C
fSUB = 32.768 kHz Normal
Square wave input
5.6
5.7
9.4
9.5
A
A
Note 4
operation
Resonator
connection
TA = +50C
fSUB = 32.768 kHz Normal
Square wave input
5.9
6.0
12.0
12.1
A
A
Note 4
operation
Resonator
connection
TA = +70C
fSUB = 32.768 kHz Normal
Square wave input
6.6
6.7
16.3
16.4
A
A
Note 4
operation
Resonator
connection
TA = +85C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 71 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the
MAX. column include the peripheral operation current. However, not including the current flowing into the
A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during
data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-bit
interval timer, and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V @1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 72 of 196
RL78/G13
(3) 128-pin products, and flash ROM: 384 to 512 KB of 44- to 100-pin products
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter Symbol
Conditions
fIH = 32 MHzNote 4
MIN.
TYP.
0.62
0.62
0.50
0.50
0.44
0.44
290
MAX.
1.89
1.89
1.48
1.48
1.12
1.12
620
Unit
mA
mA
mA
mA
mA
mA
A
Supply
current
IDD2
HALT
mode
HS (high-
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
VDD = 2.0 V
Note 2
speed main)
Note 1
modeNote 7
fIH = 24 MHzNote 4
fIH = 16 MHzNote 4
fIH = 8 MHzNote 4
LS (low-
speed main)
290
620
A
modeNote 7
LV (low-
voltage
fIH = 4 MHzNote 4
VDD = 3.0 V
VDD = 2.0 V
460
460
700
700
A
A
main) mode
Note 7
HS (high-
fMX = 20 MHzNote 3
VDD = 5.0 V
,
,
,
,
Square wave input
0.31
0.48
1.14
1.34
mA
mA
speed main)
Resonator
connection
modeNote 7
fMX = 20 MHzNote 3
VDD = 3.0 V
Square wave input
0.31
0.48
1.14
1.34
mA
mA
Resonator
connection
fMX = 10 MHzNote 3
VDD = 5.0 V
Square wave input
0.21
0.28
0.68
0.76
mA
mA
Resonator
connection
fMX = 10 MHzNote 3
VDD = 3.0 V
Square wave input
0.21
0.28
0.68
0.76
mA
mA
Resonator
connection
LS (low-
fMX = 8 MHzNote 3
VDD = 3.0 V
,
Square wave input
110
160
390
450
A
A
speed main)
Resonator
connection
modeNote 7
fMX = 8 MHzNote 3
VDD = 2.0 V
,
Square wave input
110
160
390
450
A
A
Resonator
connection
Subsystem
clock
operation
fSUB = 32.768 kHzNote 5
Square wave input
0.31
0.50
0.66
0.85
A
A
TA = 40C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.38
0.57
0.66
0.85
A
A
TA = +25C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.47
0.66
3.49
3.68
A
A
TA = +50C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.80
0.99
6.10
6.29
A
A
TA = +70C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
1.52
1.71
10.46
10.65
A
A
TA = +85C
Resonator
connection
Note 6
IDD3
STOP
TA = 40C
TA = +25C
TA = +50C
TA = +70C
TA = +85C
0.19
0.26
0.35
0.68
1.40
0.54
0.54
3.37
5.98
10.34
A
A
A
A
A
modeNote 8
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 73 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the
MAX. column include the peripheral operation current . However, not including the current flowing into
the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing
during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode: 1.8 V VDD 5.5 V @1 MHz to 8 MHz
LV (low-voltage main) mode: 1.6 V VDD 5.5 V@1 MHz to 4 MHz
8. Regarding the value for current to operate the subsystem clock in STOP mode, refer to that in HALT
mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 74 of 196
RL78/G13
(4) Peripheral Functions (Common to all products)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Parameter
Symbol
Conditions
MIN.
TYP.
0.20
MAX.
Unit
Note 1
IFIL
Low-speed on-
chip oscillator
operating
A
current
RTC operating
current
IRTC
0.02
0.02
A
A
Notes 1, 2, 3
Notes 1, 2, 4
12-bit interval
timer operating
current
IIT
Watchdog timer IWDT
fIL = 15 kHz
0.22
A
Notes 1, 2, 5
operating
current
Notes 1, 6
A/D converter
operating
current
IADC
When
Normal mode, AVREFP = VDD = 5.0 V
1.3
0.5
1.7
0.7
mA
mA
conversion at
maximum
speed
Low voltage mode, AVREFP = VDD = 3.0 V
Note 1
A/D converter
reference
voltage current
IADREF
75.0
75.0
A
A
Note 1
Temperature
sensor
ITMPS
operating
current
Notes 1, 7
LVD operating
current
ILVI
0.08
2.50
A
Notes 1, 9
Self-
IFSP
12.20
12.20
mA
programming
operating
current
Notes 1, 8
Note 1
mA
BGO operating
current
IBGO
2.50
SNOOZE
operating
current
ISNOZ
ADC operation
The mode is performedNote 10
0.50
1.20
0.60
1.44
mA
mA
The A/D conversion operations are
performed, Low voltage mode, AVREFP =
VDD = 3.0 V
CSI/UART operation
Notes 1. Current flowing to VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
0.70
0.84
mA
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-
chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation
includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The supply current of the RL78 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when
the watchdog timer is in operation.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 75 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of
IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode.
7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10. For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 76 of 196
RL78/G13
2.4 AC Characteristics
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
s
Instruction cycle (minimum
instruction execution time)
TCY
Main
system
clock (fMAIN)
operation
2.7 V
2.4 V
V
DD
5.5 V 0.03125
1
1
HS (high-
speed main)
mode
V
DD < 2.7 V 0.0625
s
1.8 V
1.6 V
VDD
5.5 V 0.125
1
1
s
s
LS (low-speed
main) mode
VDD
5.5 V
5.5 V
0.25
28.5
LV (low-
voltage main)
mode
Subsystem clock (fSUB)
operation
1.8 V
VDD
30.5
31.3
s
In the self
programming
mode
2.7 V
2.4 V
VDD
5.5 V 0.03125
1
1
s
s
HS (high-
speed main)
mode
V
DD < 2.7 V 0.0625
1.8 V
1.8 V
V
DD
5.5 V 0.125
1
1
s
s
LS (low-speed
main) mode
VDD
5.5 V
0.25
LV (low-
voltage main)
mode
External system clock
frequency
fEX
2.7 V VDD 5.5 V
2.4 V VDD < 2.7 V
1.8 V VDD < 2.4 V
1.6 V VDD < 1.8 V
1.0
1.0
20.0
16.0
8.0
MHz
MHz
MHz
MHz
kHz
ns
1.0
1.0
4.0
fEXS
32
35
External system clock input
high-level width, low-level width
tEXH, tEXL
2.7 V VDD 5.5 V
2.4 V VDD < 2.7 V
1.8 V VDD < 2.4 V
1.6 V VDD < 1.8 V
24
30
ns
60
ns
120
13.7
1/fMCK+10
ns
tEXHS, tEXLS
s
nsNote
TI00 to TI07, TI10 to TI17 input tTIH,
high-level width, low-level width tTIL
TO00 to TO07, TO10 to TO17
output frequency
fTO
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
1.8 V EVDD0 < 2.7 V
1.6 V EVDD0 < 1.8 V
1.8 V EVDD0 5.5 V
1.6 V EVDD0 < 1.8 V
1.6 V EVDD0 5.5 V
16
8
MHz
MHz
MHz
MHz
MHz
MHz
MHz
HS (high-speed
main) mode
4
2
LS (low-speed
main) mode
4
2
LV (low-voltage
main) mode
2
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
HS (high-speed
main) mode
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
1.8 V EVDD0 < 2.7 V
1.6 V EVDD0 < 1.8 V
1.8 V EVDD0 5.5 V
1.6 V EVDD0 < 1.8 V
1.8 V EVDD0 5.5 V
1.6 V EVDD0 < 1.8 V
1.6 V VDD 5.5 V
16
8
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
s
4
2
LS (low-speed
main) mode
4
2
LV (low-voltage
main) mode
4
2
Interrupt input high-level width, tINTH,
low-level width
INTP0
1
1
tINTL
INTP1 to INTP11 1.6 V EVDD0 5.5 V
s
Key interrupt input low-level
width
tKR
KR0 to KR7
1.8 V EVDD0 5.5 V
1.6 V EVDD0 < 1.8 V
250
1
ns
s
RESET low-level width
tRSL
10
s
(Note and Remark are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 77 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Note The following conditions are required for low voltage interface when EVDD0 < VDD
1.8 V EVDD0 < 2.7 V : MIN. 125 ns
1.6 V EVDD0 < 1.8 V : MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
5.5
0
1.0
2.0
2.4
3.0
2.7
4.0
5.0
6.0
Supply voltage VDD [V]
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 78 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
TCY vs VDD (LS (low-speed main) mode)
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.125
0.1
0.01
5.5
0
1.0
2.0
1.8
3.0
4.0
5.0
6.0
Supply voltage VDD [V]
TCY vs VDD (LV (low-voltage main) mode)
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.25
0.1
0.01
5.5
0
1.0
2.0
1.6 1.8
3.0
4.0
5.0
6.0
Supply voltage VDD [V]
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 79 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
AC Timing Test Points
V
V
IH/VOH
IL/VOL
V
IH/VOH
IL/VOL
Test points
V
External System Clock Timing
1/fEX
/
1/fEXS
t
EXL
/
t
t
EXH
/
tEXLS
EXHS
EXCLK/EXCLKS
TI/TO Timing
tTIL
t
TIH
TI00 to TI07, TI10 to TI17
1/fTO
TO00 to TO07, TO10 to TO17
Interrupt Request Input Timing
t
INTL
tINTH
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 80 of 196
RL78/G13
2.5 Peripheral Functions Characteristics
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
AC Timing Test Points
V
IH/VOH
V
IH/VOH
Test points
VIL/VOL
VIL/VOL
2.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rateNote 1
2.4 V EVDD0 5.5 V
fMCK/6
Note 2
fMCK/6
fMCK/6
bps
Theoretical value of the
5.3
1.3
0.6
Mbps
maximum transfer rate
Note 3
fMCK = fCLK
1.8 V EVDD0 5.5 V
fMCK/6
fMCK/6
1.3
fMCK/6
0.6
bps
Note 2
Theoretical value of the
maximum transfer rate
5.3
Mbps
Note 3
fMCK = fCLK
1.7 V EVDD0 5.5 V
fMCK/6
fMCK/6
fMCK/6
0.6
bps
Note 2
Note 2
Theoretical value of the
maximum transfer rate
5.3
1.3
Mbps
Note 3
fMCK = fCLK
1.6 V EVDD0 5.5 V
fMCK/6
fMCK/6
0.6
bps
Note 2
Theoretical value of the
maximum transfer rate
1.3
Mbps
Note 3
fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V EVDD0 < 2.4 V : MAX. 1.3 Mbps
1.6 V EVDD0 < 1.8 V : MAX. 0.6 Mbps
3. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
8 MHz (1.8 V VDD 5.5 V)
4 MHz (1.6 V VDD 5.5 V)
LS (low-speed main) mode:
LV (low-voltage main) mode:
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
UART mode connection diagram (during communication at same potential)
TxDq
RxDq
Rx
Tx
User device
RL78 microcontroller
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only)
(TA = 40 to +85C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle time
tKCY1
tKCY1 2/fCLK 4.0 V EVDD0 5.5 V 62.5
2.7 V EVDD0 5.5 V 83.3
250
250
500
500
ns
ns
ns
SCKp high-/low-level
width
tKH1,
4.0 V EVDD0 5.5 V
tKCY1/2
tKCY1/2
tKCY1/2
tKL1
7
50
50
2.7 V EVDD0 5.5 V
tKCY1/2
tKCY1/2
tKCY1/2
ns
10
50
50
SIp setup time (to SCKp) tSIK1
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
23
33
10
110
110
10
110
110
10
ns
ns
ns
Note 1
SIp hold time (from
tKSI1
SCKp) Note 2
Delay time from SCKp to tKSO1
SOp output Note 3
C = 20 pF Note 4
10
10
10
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM numbers (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed
main) Mode main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
125
MAX.
MIN.
500
MAX.
MIN.
1000
MAX.
SCKp cycle time
tKCY1
tKCY1 4/fCLK 2.7 V EVDD0 5.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
2.4 V EVDD0 5.5
250
500
1000
500
500
1000
1000
1000
1000
V
1.8 V EVDD0 5.5
V
1.7 V EVDD0 5.5
1000
1000
V
1.6 V EVDD0 5.5
V
SCKp high-/low-level tKH1,
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
tKCY1/2
tKCY1/2
tKCY1/2
width
tKL1
12
50
50
tKCY1/2
tKCY1/2
tKCY1/2
18
50
50
tKCY1/2
tKCY1/2
tKCY1/2
38
50
50
tKCY1/2
tKCY1/2
tKCY1/2
50
50
50
tKCY1/2
tKCY1/2
tKCY1/2
100
100
100
tKCY1/2
tKCY1/2
100
100
SIp setup time
tSIK1
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
44
44
110
110
110
110
220
220
19
110
110
110
110
220
220
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
(to SCKp)
Note 1
75
110
220
SIp hold time
(from SCKp) Note 2
tKSI1
19
19
19
Delay time from
SCKp to SOp
output Note 3
tKSO1
1.7 V EVDD0 5.5 V
C = 30 pFNote 4
25
25
25
25
25
1.6 V EVDD0 5.5 V
C = 30 pFNote 4
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0
to 3),
g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (1/2)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed LV (low-voltage Unit
main) Mode main) Mode
MIN. MAX. MIN. MAX.
MIN.
8/fMCK
6/fMCK
8/fMCK
6/fMCK
MAX.
SCKp cycle time
Note 5
tKCY2
4.0 V EVDD0 5.5
20 MHz < fMCK
fMCK 20 MHz
16 MHz < fMCK
fMCK 16 MHz
ns
ns
ns
ns
ns
V
6/fMCK
6/fMCK
2.7 V EVDD0 5.5
V
6/fMCK
6/fMCK
2.4 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
6/fMCK
6/fMCK
and
6/fMCK
and
and 500
500
500
6/fMCK
6/fMCK
and
6/fMCK
and
ns
ns
ns
and 750
750
750
6/fMCK
and
6/fMCK
and
6/fMCK
and
1500
1500
1500
6/fMCK
and
6/fMCK
and
1500
1500
SCKp high-/low-
level width
tKH2,
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
tKCY2/2
tKCY2/2
tKCY2/2
ns
ns
ns
ns
ns
tKL2
7
7
7
tKCY2/2
tKCY2/2
tKCY2/2
8
8
8
tKCY2/2
tKCY2/2
tKCY2/2
18
18
18
tKCY2/2
tKCY2/2
tKCY2/2
66
66
66
tKCY2/2
tKCY2/2
66
66
(Notes, Caution, and Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (2/2)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbo
l
Conditions
HS (high-speed
main) Mode
LS (low-speed main) LV (low-voltage main) Unit
Mode Mode
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SIp setup time
(to SCKp) Note 1
tSIK2
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1/fMCK+2
0
1/fMCK+30
1/fMCK+30
1/fMCK+40
1/fMCK+30
1/fMCK+30
1/fMCK+40
ns
ns
ns
1/fMCK+3
0
1/fMCK+4
0
1.6 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1/fMCK+40
1/fMCK+31
1/fMCK+40
1/fMCK+31
ns
ns
SIp hold time
tKSI2
1/fMCK+3
1
(from SCKp)
Note 2
1.7 V EVDD0 5.5 V
1/fMCK+
250
1/fMCK+
250
1/fMCK+
250
ns
ns
ns
ns
ns
ns
ns
1.6 V EVDD0 5.5 V
C = 30 2.7 V EVDD0 5.5
1/fMCK+
250
1/fMCK+
250
Delay time
tKSO2
2/fMCK+
44
2/fMCK+
110
2/fMCK+
110
from SCKp to
pF Note 4
V
SOp output Note
2.4 V EVDD0 5.5
2/fMCK+
75
2/fMCK+
110
2/fMCK+
110
3
V
1.8 V EVDD0 5.5
2/fMCK+
110
2/fMCK+
110
2/fMCK+
110
V
1.7 V EVDD0 5.5
2/fMCK+
220
2/fMCK+
220
2/fMCK+
220
V
1.6 V EVDD0 5.5
2/fMCK+
220
2/fMCK+
220
V
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode: MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
CSI mode connection diagram (during communication at same potential)
SCKp
SIp
SCK
SO
RL78
microcontroller
User device
SOp
SI
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KCY1, 2
t
KL1, 2
t
KH1, 2
SCKp
t
SIK1, 2
t
KSI1, 2
SIp
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t
KCY1, 2
tKH1, 2
t
KL1, 2
SCKp
t
SIK1, 2
t
KSI1, 2
SIp
Input data
tKSO1, 2
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(5) During communication at same potential (simplified I2C mode) (1/2)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage
main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
Unit
SCLr clock frequency
fSCL
1000
400
400
kHz
kHz
kHz
kHz
kHz
ns
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.7 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.7 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.7 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
Note 1
Note 1
Note 1
400
400
400
Note 1
Note 1
Note 1
300
300
300
Note 1
Note 1
Note 1
250
250
250
Note 1
Note 1
Note 1
250
250
Note 1
Note 1
Hold time when SCLr = “L”
tLOW
475
1150
1550
1850
1150
1150
1550
1850
1850
1150
1150
1550
1850
1850
1150
1150
1550
1850
1850
1150
1150
1550
1850
1850
ns
ns
ns
ns
Hold time when SCLr = “H” tHIGH
475
ns
1150
1550
1850
ns
ns
ns
ns
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(5) During communication at same potential (simplified I2C mode) (2/2)
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage
main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
Unit
Data setup time (reception) tSU:DAT
1/fMCK
1/fMCK
1/fMCK
ns
ns
ns
ns
ns
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
+ 85
+ 145
+ 145
Note2
Note2
Note2
1/fMCK
1/fMCK
1/fMCK
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
+ 145
+ 145
+ 145
Note2
Note2
Note2
1/fMCK
1/fMCK
1/fMCK
1.8 V EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
+ 230
+ 230
+ 230
Note2
Note2
Note2
1/fMCK
1/fMCK
1/fMCK
1.7 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
+ 290
+ 290
+ 290
Note2
Note2
Note2
1/fMCK
1/fMCK
1.6 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
+ 290
+ 290
Note2
Note2
Data hold time
(transmission)
tHD:DAT
0
0
0
0
305
355
405
405
0
0
0
0
0
305
355
405
405
405
0
0
0
0
0
305
355
405
405
405
ns
ns
ns
ns
ns
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
1.8 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
1.8 V EVDD0 < 2.7 V,
Cb = 100 pF, Rb = 5 k
1.7 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
1.6 V EVDD0 < 1.8 V,
Cb = 100 pF, Rb = 5 k
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (When 20- to 52-pin
products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SDAr pin and the normal
output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register h (POMh).
(Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Simplified I2C mode mode connection diagram (during communication at same potential)
V
DD
R
b
SDAr
RL78 microcontroller
SDA
SCL
User device
SCLr
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
t
HIGH
SCLr
SDAr
t
HD:DAT
tSU:DAT
Remarks 1. Rb[]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14),
h: POM number (g = 0, 1, 4, 5, 7 to 9, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m
= 0, 1),
n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol
Conditions
HS (high- LS (low-speed
speed main) main) Mode voltage main)
Mode Mode
MIN. MAX. MIN. MAX. MIN. MAX.
LV (low-
Unit
Transfer
rate
Recep- 4.0 V EVDD0 5.5 V,
fMCK/6
Note 1
fMCK/6
Note 1
fMCK/6
Note 1
bps
tion
2.7 V Vb 4.0 V
Theoretical value
of the maximum
transfer rate
5.3
1.3
0.6
Mbps
Note 4
fMCK = fCLK
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V
fMCK/6
Note 1
fMCK/6
Note 1
fMCK/6
Note 1
bps
Theoretical value
of the maximum
transfer rate
5.3
1.3
0.6
Mbps
Note 4
fMCK = fCLK
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V
fMCK/6
Notes 1 to 3
fMCK/6
Notes 1, 2
fMCK/6
Notes 1, 2
bps
Theoretical value
of the maximum
transfer rate
5.3
1.3
0.6
Mbps
Note 4
fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. Use it with EVDD0Vb.
3. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V EVDD0 < 2.7 V : MAX. 2.6 Mbps
1.8 V EVDD0 < 2.4 V : MAX. 1.3 Mbps
4. The maximum operating frequencies of the CPU/peripheral hardware clock (fCLK) are:
HS (high-speed main) mode:
32 MHz (2.7 V VDD 5.5 V)
16 MHz (2.4 V VDD 5.5 V)
8 MHz (1.8 V VDD 5.5 V)
4 MHz (1.6 V VDD 5.5 V)
LS (low-speed main) mode:
LV (low-voltage main) mode:
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
Remarks 1. Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-
speed main) speed main)
Mode Mode
LS (low-
LV (low-
voltage
Unit
main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
Transfer rate
Transmission 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V
Note
1
Note
1
Note
1
bps
Theoretical
value of the
maximum
2.8
Note 2
2.8
Note 2
2.8
Note 2
Mbps
transfer rate
Cb
= 50 pF, R
b
=
1.4 k , V = 2.7
b
V
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V
Note
3
Note
3
Note
3
bps
Theoretical
value of the
maximum
1.2
Note 4
1.2
Note 4
1.2
Note 4
Mbps
transfer rate
Cb
= 50 pF, R
b
=
2.7 k , V = 2.3
b
V
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V
Notes
5, 6
Notes
5, 6
Notes bps
5, 6
Theoretical
value of the
maximum
0.43
Note 7
0.43
Note 7
0.43 Mbps
Note 7
transfer rate
Cb
= 50 pF, R
b
=
5.5 k , V = 1.6
b
V
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V
1
Maximum transfer rate =
[bps]
2.2
Vb
{Cb × Rb × ln (1
)} × 3
1
2.2
Vb
{Cb × Rb × ln (1
)}
Transfer rate 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.3 V Vb 2.7 V
1
Maximum transfer rate =
[bps]
2.0
Vb
{Cb × Rb × ln (1
)} × 3
1
2.0
Vb
{Cb × Rb × ln (1
)}
Transfer rate 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
5. Use it with EVDD0 Vb.
6. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V
1
Maximum transfer rate =
[bps]
1.5
Vb
{Cb × Rb × ln (1
)} × 3
1
1.5
Vb
{Cb × Rb × ln (1
)}
Transfer rate 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
7. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 6 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
V
b
R
b
TxDq
RxDq
Rx
Tx
User device
RL78 microcontroller
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1. Rb[]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (1/2)
(TA = 40 to +85C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage
main) Mode main) Mode main) Mode
Unit
MIN.
200
MAX.
MIN.
1150
MAX.
MIN.
1150
MAX.
SCKp cycle time tKCY1
tKCY1 2/fCLK 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
ns
Cb = 20 pF, Rb = 1.4
k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
300
1150
1150
ns
Cb = 20 pF, Rb = 2.7
k
SCKp high-level
width
tKH1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
tKCY1/2
tKCY1/2
tKCY1/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
50
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
tKCY1/2
tKCY1/2
tKCY1/2
120
120
120
Cb = 20 pF, Rb = 2.7 k
SCKp low-level
width
tKL1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
tKCY1/2
tKCY1/2
tKCY1/2
7
50
50
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
tKCY1/2
tKCY1/2
tKCY1/2
10
50
50
Cb = 20 pF, Rb = 2.7 k
SIp setup time
(to SCKp)Note 1
tSIK1
tKSI1
tKSO1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
58
121
10
479
479
10
479
479
10
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
SIp hold time
(from SCKp) Note 1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
10
10
10
Cb = 20 pF, Rb = 2.7 k
Delay time from
SCKp to SOp
output Note 1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
60
60
60
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
130
130
130
Cb = 20 pF, Rb = 2.7 k
(Notes, Caution, and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output,
corresponding CSI00 only) (2/2)
(TA = 40 to +85C, 2.7 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
23
MAX.
MIN.
110
MAX.
MIN.
110
MAX.
SIp setup time
tSIK1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
ns
ns
ns
ns
ns
ns
(to SCKp)Note 2
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
33
10
10
110
10
110
10
Cb = 20 pF, Rb = 2.7 k
SIp hold time
(from SCKp) Note 2
tKSI1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
10
10
Cb = 20 pF, Rb = 2.7 k
Delay time from SCKp tKSO1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
10
10
10
10
10
10
to
SOp output Note 2
Cb = 20 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 20 pF, Rb = 2.7 k
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00), m: Unit number (m = 0), n: Channel number (n = 0),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00))
4. This value is valid only when CSI00’s peripheral I/O redirect function is not used.
R01DS0131EJ0330 Rev.3.30
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(1/3)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage Unit
main) Mode
MIN.
300
MAX.
MIN.
1150
MAX.
MIN.
1150
MAX.
SCKp cycle
time
tKCY1
tKCY1 4/fCLK 4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
500
1150
1150
1150
1150
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
1150
1.6 V Vb 2.0 VNote
,
Cb = 30 pF, Rb = 5.5 k
SCKp high-level tKH1
width
4.0 V EVDD0 5.5 V,
tKCY1/2
tKCY1/2
tKCY1/2
2.7 V Vb 4.0 V,
75
75
75
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
tKCY1/2
tKCY1/2
tKCY1/2
170
170
170
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
tKCY1/2
tKCY1/2
tKCY1/2
1.6 V Vb 2.0 VNote
,
458
458
458
Cb = 30 pF, Rb = 5.5 k
SCKp low-level tKL1
width
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
tKCY1/2
tKCY1/2
tKCY1/2
12
50
50
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
tKCY1/2
tKCY1/2
tKCY1/2
18
50
50
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
tKCY1/2
tKCY1/2
tKCY1/2
1.6 V Vb 2.0 VNote
,
50
50
50
Cb = 30 pF, Rb = 5.5 k
Use it with EVDD0 Vb.
Note
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
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Page 97 of 196
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(2/3)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
81
MAX.
MIN.
479
MAX.
MIN.
479
MAX.
SIp setup time
tSIK1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
ns
ns
ns
ns
ns
ns
ns
ns
ns
(to SCKp)Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
177
479
19
479
479
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
479
19
479
19
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
(from SCKp) Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
19
19
19
19
19
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
19
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp tKSO1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
100
195
483
100
195
483
100
195
483
to
SOp output Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
Notes
1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. Use it with EVDD0 Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 98 of 196
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock output)
(3/3)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed
main) Mode
LS (low-speed
main) Mode
LV (low-voltage
main) Mode
Unit
MIN.
44
MAX.
MIN.
110
MAX.
MIN.
110
MAX.
SIp setup time
tSIK1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
ns
ns
ns
ns
ns
ns
ns
ns
ns
(to SCKp)Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
44
110
19
110
110
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
110
19
110
19
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
(from SCKp) Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
19
19
19
19
19
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
19
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
Delay time from SCKp tKSO1
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
25
25
25
25
25
25
25
25
25
to
SOp output Note 1
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
Notes
1. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. Use it with EVDD0 Vb.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (When
20- to 52-pin products)/EVDD tolerance (When 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
R
b
Rb
SCKp
SIp
SCK
SO
User device
RL78
microcontroller
SOp
SI
Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02,
10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
t
KH1
SCKp
t
SIK1
tKSI1
SIp
Input data
t
KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
t
KL1
t
KH1
SCKp
tSIK1
t
KSI1
SIp
Input data
t
KSO1
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10,
12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 101 of 196
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
Parameter
Symbol
Conditions
HS (high-
speed main)
Mode
LS (low-speed LV (low-voltage Unit
main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp cycle timeNote 1
tKCY2
4.0 V
2.7 V
EVDD0
5.5 V, 24 MHz < fMCK
14/
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fMCK
Vb 4.0 V
20 MHz < fMCK 24 MHz 12/
fMCK
8 MHz < fMCK 20 MHz
4 MHz < fMCK 8 MHz
fMCK 4 MHz
10/
fMCK
8/fMCK
6/fMCK
16/
fMCK
10/
10/
fMCK
fMCK
2.7 V
2.3 V
EVDD0 < 4.0 V, 24 MHz < fMCK
2.7 V
20/
fMCK
V
b
20 MHz < fMCK 24 MHz 16/
fMCK
16 MHz < fMCK 20 MHz 14/
fMCK
8 MHz < fMCK 16 MHz 12/
fMCK
4 MHz < fMCK 8 MHz
fMCK 4 MHz
8/fMCK
6/fMCK
16/
fMCK
10/
10/
fMCK
fMCK
1.8 V
EVDD0 < 3.3 V, 24 MHz < fMCK
2.0 VNote
48/
fMCK
1.6 V
2
V
b
20 MHz < fMCK 24 MHz 36/
fMCK
16 MHz < fMCK 20 MHz 32/
fMCK
8 MHz < fMCK 16 MHz 26/
fMCK
4 MHz < fMCK 8 MHz
fMCK 4 MHz
16/
16/
fMCK
fMCK
10/
10/
10/
fMCK
fMCK
fMCK
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 102 of 196
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter
Symbol
Conditions
HS (high-
speed main)
Mode
LS (low-speed LV (low-voltage Unit
main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
SCKp high-/low-level
width
tKH2,
4.0 V EVDD0 5.5 V,
t
KCY2/2
t
KCY2/2
t
KCY2/2
ns
ns
tKL2
2.7 V Vb 4.0 V
12
50
50
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V
tKCY2/2
tKCY2/2
tKCY2/2
18
50
50
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
t
KCY2/2
t
KCY2/2
t
KCY2/2
ns
ns
ns
50
50
50
SIp setup time
(to SCKp) Note 3
tSIK2
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V
1/fMCK
+ 20
1/fMCK
+ 30
1/fMCK
+ 30
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
1/fMCK
+ 30
1/fMCK
+ 30
1/fMCK
+ 30
ns
ns
ns
SIp hold time
(from SCKp) Note 4
tKSI2
1/fMCK +
31
1/fMCK
+ 31
1/fMCK
+ 31
Delay time from
tKSO2
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0
2/fMCK
+ 120
2/fMCK
2/fMCK
SCKp to SOp output
V,
+ 573
+ 573
Note 5
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7
2/fMCK
+ 214
2/fMCK
+ 573
2/fMCK
+ 573
ns
ns
V,
Cb = 30 pF, Rb = 2.7 k
1.8 V EVDD0 < 3.3 V,
2/fMCK
+ 573
2/fMCK
+ 573
2/fMCK
+ 573
1.6 V Vb 2.0 VNote 2
,
Cb = 30 pF, Rb = 5.5 k
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EVDD0 Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the
20- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 103 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
R
b
SCKp
SCK
SO
RL78
User device
microcontroller SIp
SOp
SI
Remarks 1. Rb[]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number, n: Channel number (mn = 00, 01, 02, 10,
12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 104 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KCY2
tKL2
tKH2
SCKp
t
SIK2
t
KSI2
SIp
Input data
t
KSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
t
KL2
tKH2
SCKp
t
SIK2
t
KSI2
SIp
Input data
t
KSO2
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 105 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage
main) Mode main) Mode main) Mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
SCLr clock frequency fSCL
1000
300
300
kHz
kHz
kHz
kHz
kHz
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Note 1
Note 1
Note 1
Cb = 50 pF, Rb = 2.7 k
1000
300
300
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Note 1
Note 1
Note 1
Cb = 50 pF, Rb = 2.7 k
400
300
300
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Note 1
Note 1
Note 1
Cb = 100 pF, Rb = 2.8 k
400
300
300
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Note 1
Note 1
ote 1
Cb = 100 pF, Rb = 2.7 k
300
300
300
1.8 V EVDD0 < 3.3 V,
Note 1
Note 1
Note 1
1.6 V Vb 2.0 VNote 2
,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr tLOW
= “L”
475
475
1550
1550
1550
1550
1550
610
1550
1550
1550
1550
1550
610
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1150
1150
1550
245
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr tHIGH
= “H”
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
200
610
610
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
675
610
610
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
600
610
610
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
610
610
610
ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
,
Cb = 100 pF, Rb = 5.5 k
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 106 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage
main) Mode main) Mode main) Mode
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
1/fMCK
1/fMCK
kHz
kHz
kHz
kHz
kHz
ns
Data setup time
(reception)
tSU:DAT
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK +
135Note 3
+ 190
+ 190
Note 3
Note 3
1/fMCK
1/fMCK
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK +
135Note 3
+ 190
+ 190
Note 3
Note 3
1/fMCK
1/fMCK
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK +
190Note 3
+ 190
+ 190
Note 3
Note 3
1/fMCK
1/fMCK
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK +
190Note 3
+ 190
+ 190
Note 3
Note 3
1/fMCK
1/fMCK
1.8 V EVDD0 < 3.3 V,
1/fMCK +
190Note 3
1.6 V Vb 2.0 VNote 2
,
+ 190
+ 190
Note 3
Note 3
Cb = 100 pF, Rb = 5.5 k
0
0
0
0
0
305
305
355
355
405
0
0
0
0
0
305
305
355
355
405
0
0
0
0
0
305
305
355
355
405
Data hold time
(transmission)
tHD:DAT
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
ns
1.8 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
,
Cb = 100 pF, Rb = 5.5 k
Notes 1. The value must also be equal to or less than fMCK/4.
2. Use it with EVDD0 Vb.
3. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin
products)/EVDD tolerance (for the 64- to 128-pin products)) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 128-
pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 107 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Simplified I2C mode connection diagram (during communication at different potential)
V
b
Vb
R
b
Rb
SDAr
SDA
User device
SCL
RL78
microcontroller
SCLr
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
t
SU:DAT
Remarks 1. Rb[]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12, 13)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 108 of 196
RL78/G13
2.5.2 Serial interface IICA
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(1) I2C standard mode
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX. MIN. MAX.
Standard
mode:
SCLA0 clock frequency
fSCL
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
0
0
0
100
100
100
0
100
100
100
100
0
100
100
100
100
kHz
kHz
kHz
kHz
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
0
0
fCLK 1 MHz
0
0
0
0
Setup time of restart
condition
tSU:STA
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
1.7 V EVDD0 5.5 V
1.6 V EVDD0 5.5 V
4.7
4.7
4.7
4.7
4.7
4.7
4.7
4.0
4.0
4.0
4.0
4.7
4.7
4.7
4.7
4.0
4.0
4.0
4.0
250
250
250
250
0
4.7
4.7
4.7
4.7
4.0
4.0
4.0
4.0
4.7
4.7
4.7
4.7
4.0
4.0
4.0
4.0
250
250
250
250
0
Hold timeNote 1
tHD:STA
4.0
4.0
4.0
Hold time when SCLA0 = tLOW
“L”
4.7
4.7
4.7
Hold time when SCLA0 = tHIGH
“H”
4.0
4.0
4.0
Data setup time
(reception)
tSU:DAT
250
250
250
Data hold time
(transmission)Note 2
tHD:DAT
tSU:STO
tBUF
0
0
0
3.45
3.45
3.45
3.45
3.45
3.45
3.45
3.45
3.45
3.45
3.45
0
0
0
0
0
0
Setup time of stop
condition
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.7
4.7
4.7
4.7
4.0
4.0
4.0
4.0
4.7
4.7
4.7
4.7
Bus-free time
4.7
4.7
4.7
(Notes, Caution and Remark are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 109 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
<R>
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 110 of 196
RL78/G13
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(2) I2C fast mode
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode main) Mode main) Mode
MIN.
0
MAX.
400
MIN.
0
MAX.
400
MIN.
0
MAX.
400
Fast mode:
fCLK 3.5 MHz
SCLA0 clock frequency
fSCL
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
kHz
kHz
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
s
0
400
0
400
0
400
Setup time of restart
condition
tSU:STA
tHD:STA
tLOW
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
1.8 V EVDD0 5.5 V
0.6
0.6
0.6
0.6
1.3
1.3
0.6
0.6
100
100
0
0.6
0.6
0.6
0.6
1.3
1.3
0.6
0.6
100
100
0
0.6
0.6
0.6
0.6
1.3
1.3
0.6
0.6
100
100
0
Hold timeNote 1
Hold time when SCLA0 =
“L”
Hold time when SCLA0 =
“H”
tHIGH
Data setup time
(reception)
tSU:DAT
tHD:DAT
tSU:STO
tBUF
Data hold time
(transmission)Note 2
0.9
0.9
0.9
0.9
0.9
0.9
0
0
0
Setup time of stop
condition
0.6
0.6
1.3
1.3
0.6
0.6
1.3
1.3
0.6
0.6
1.3
1.3
Bus-free time
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
<R>
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Fast mode:
Cb = 320 pF, Rb = 1.1 k
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(3) I2C fast mode plus
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed LS (low-speed LV (low-voltage Unit
main) Mode main) Mode main) Mode
MIN. MAX. MIN. MAX.
MIN.
0
MAX.
1000
Fast mode plus:
SCLA0 clock frequency
fSCL
2.7 V EVDD0 5.5 V
kHz
fCLK 10 MHz
Setup time of restart
condition
tSU:STA
2.7 V EVDD0 5.5 V
0.26
s
Hold timeNote 1
tHD:STA
2.7 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
0.26
0.5
s
s
Hold time when SCLA0 =
“L”
tLOW
Hold time when SCLA0 =
“H”
tHIGH
2.7 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
0.26
50
s
s
s
s
s
Data setup time
(reception)
tSU:DAT
tHD:DAT
tSU:STO
tBUF
Data hold time
(transmission)Note 2
0
0.45
Setup time of stop
condition
0.26
0.5
Bus-free time
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
<R>
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Fast mode plus: Cb = 120 pF, Rb = 1.1 k
IICA serial transfer timing
t
LOW
t
R
SCLAn
SDAAn
t
HD:DAT
t
HIGH
SU:DAT
t
F
tSU:STA
t
HD:STA
t
SU:STO
t
HD:STA
t
t
BUF
Stop
Start
Restart
condition
Stop
condition
condition condition
Remark n = 0, 1
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2.6 Analog Characteristics
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) = AVREFP
Reference voltage (+) = VDD
Reference voltage () = VSS
Refer to 2.6.1 (3).
Reference voltage (+) = VBGR
Reference voltage () = AVREFM
Refer to 2.6.1 (4).
Input channel
Reference voltage () = AVREFM
Refer to 2.6.1 (1).
ANI0 to ANI14
ANI16 to ANI26
Refer to 2.6.1 (2).
Internal reference voltage
Temperature sensor output
voltage
Refer to 2.6.1 (1).
(1) When reference voltage (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature
sensor output voltage
(TA = 40 to +85C, 1.6 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage
() = AVREFM = 0 V)
Parameter
Resolution
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Overall errorNote 1
AINL
10-bit resolution
1.8 V AVREFP 5.5 V
1.2
1.2
3.5
7.0
39
LSB
LSB
s
Note 3
1.6 V AVREFP 5.5 VNote 4
3.6 V VDD 5.5 V
2.7 V VDD 5.5 V
1.8 V VDD 5.5 V
1.6 V VDD 5.5 V
3.6 V VDD 5.5 V
2.7 V VDD 5.5 V
2.4 V VDD 5.5 V
AVREFP = VDD
Conversion time
tCONV
10-bit resolution
Target pin: ANI2 to
ANI14
2.125
3.1875
17
39
s
39
s
57
95
s
10-bit resolution
Target pin: Internal
reference voltage, and
temperature sensor
output voltage
2.375
3.5625
17
39
s
39
s
39
s
(HS (high-speed main)
mode)
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
Integral linearity errorNote 1
EZS
EFS
ILE
10-bit resolution
1.8 V AVREFP 5.5 V
1.6 V AVREFP 5.5 VNote 4
1.8 V AVREFP 5.5 V
1.6 V AVREFP 5.5 VNote 4
1.8 V AVREFP 5.5 V
1.6 V AVREFP 5.5 VNote 4
1.8 V AVREFP 5.5 V
1.6 V AVREFP 5.5 VNote 4
0.25 %FSR
0.50 %FSR
0.25 %FSR
0.50 %FSR
Note 3
AVREFP = VDD
10-bit resolution
Note 3
AVREFP = VDD
10-bit resolution
2.5
5.0
LSB
LSB
LSB
LSB
V
Note 3
AVREFP = VDD
Differential linearity errorNote 1 DLE
10-bit resolution
1.5
Note 3
AVREFP = VDD
2.0
Analog input voltage
VAIN
ANI2 to ANI14
0
AVREFP
Note 5
Internal reference voltage
VBGR
V
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
Note 5
Temperature sensor output voltage
VTMPS25
V
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
(Notes are listed on the next page.)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD
.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD
.
Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD
4. Values when the conversion time is set to 57 s (min.) and 95 s (max.).
.
5. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, 1.6 V AVREFP VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V,
Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V)
Parameter
Resolution
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Overall errorNote 1
AINL
10-bit resolution
1.8 V AVREFP 5.5 V
1.2
1.2
5.0
8.5
LSB
LSB
Notes 3, 4
1.6 V AVREFP 5.5 VNote
EVDD0 = AVREFP = VDD
5
Conversion time
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.7 V VDD 5.5 V
1.8 V VDD 5.5 V
1.6 V VDD 5.5 V
1.8 V AVREFP 5.5 V
2.125
3.1875
17
39
39
s
s
Target ANI pin : ANI16 to
ANI26
39
s
57
95
s
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
EZS
EFS
0.35
0.60
%FSR
%FSR
10-bit resolution
EVDD0 = AVREFP = VDD
Notes 3, 4
1.6 V AVREFP 5.5 VNote
5
10-bit resolution
EVDD0 = AVREFP = VDD
1.8 V AVREFP 5.5 V
0.35
0.60
%FSR
%FSR
Notes 3, 4
1.6 V AVREFP 5.5 VNote
5
Integral linearity errorNote ILE
10-bit resolution
1.8 V AVREFP 5.5 V
3.5
6.0
LSB
LSB
1
Notes 3, 4
1.6 V AVREFP 5.5 VNote
EVDD0 = AVREFP = VDD
5
Differential linearity
errorNote 1
DLE
10-bit resolution
1.8 V AVREFP 5.5 V
2.0
2.5
LSB
LSB
Notes 3, 4
1.6 V AVREFP 5.5 VNote
EVDD0 = AVREFP = VDD
5
Analog input voltage
VAIN
ANI16 to ANI26
0
AVREFP
V
and EVDD0
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD
.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD
.
Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD
4. When AVREFP < EVDD0 VDD, the MAX. values are as follows.
.
.
Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD
.
Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD
.
Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD
5. When the conversion time is set to 57 s (min.) and 95 s (max.).
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM =
0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output
voltage
(TA = 40 to +85C, 1.6 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) = VDD,
Reference voltage () = VSS)
Parameter
Resolution
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Overall errorNote 1
AINL
10-bit resolution
1.8 V VDD 5.5 V
1.2
1.2
7.0
10.5
LSB
LSB
1.6 V VDD 5.5 V
Note 3
Conversion time
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.125
39
39
39
95
39
39
39
s
s
s
s
s
s
s
Target pin: ANI0 to ANI14,
ANI16 to ANI26
2.7 V VDD 5.5 V 3.1875
1.8 V VDD 5.5 V
1.6 V VDD 5.5 V
3.6 V VDD 5.5 V
17
57
Conversion time
tCONV
10-bit resolution
2.375
Target pin: Internal
reference voltage, and
temperature sensor output
voltage (HS (high-speed
main) mode)
2.7 V VDD 5.5 V 3.5625
2.4 V VDD 5.5 V
17
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
Integral linearity errorNote 1
EZS
EFS
ILE
1.8 V VDD 5.5 V
0.60
0.85
%FSR
%FSR
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
1.6 V VDD 5.5 V
Note 3
1.8 V VDD 5.5 V
0.60
0.85
%FSR
%FSR
1.6 V VDD 5.5 V
Note 3
1.8 V VDD 5.5 V
4.0
6.5
LSB
LSB
1.6 V VDD 5.5 V
Note 3
Differential linearity errorNote 1 DLE
1.8 V VDD 5.5 V
2.0
2.5
LSB
LSB
1.6 V VDD 5.5 V
Note 3
Analog input voltage
VAIN
ANI0 to ANI14
0
0
VDD
V
V
V
ANI16 to ANI26
EVDD0
Note 4
Internal reference voltage
VBGR
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
Note 4
Temperature sensor output voltage
VTMPS25
V
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When the conversion time is set to 57 s (min.) and 95 s (max.).
4. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage
() = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26
(TA = 40 to +85C, 2.4 V VDD 5.5 V, 1.6 V EVDD0 = EVDD1 VDD, VSS = EVSS0 = EVSS1 = 0 V, Reference
voltage (+) = VBGR Note 3, Reference voltage () = AVREFM = 0 VNote 4, HS (high-speed main) mode)
Parameter
Symbol
RES
tCONV
EZS
Conditions
MIN.
TYP.
8
MAX.
Unit
bit
Resolution
Conversion time
8-bit resolution
8-bit resolution
8-bit resolution
8-bit resolution
2.4 V VDD 5.5 V
17
39
s
Zero-scale errorNotes 1, 2
Integral linearity errorNote 1
Differential linearity errorNote 1
Analog input voltage
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
0.60
2.0
1.0
%FSR
LSB
LSB
V
ILE
DLE
VAIN
Note 3
0
VBGR
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 2.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage () = VSS, the MAX. values are as follows.
Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM.
Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM.
Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM.
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.6.2 Temperature sensor/internal reference voltage characteristics
(TA = 40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
1.38
TYP.
1.05
1.45
3.6
MAX.
1.5
Unit
V
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C
Internal reference voltage
Temperature coefficient
VBGR
Setting ADS register = 81H
V
FVTMPS
Temperature sensor that depends on the
temperature
mV/C
Operation stabilization wait time
tAMP
5
s
2.6.3 POR circuit characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Detection voltage
Symbol
VPOR
Conditions
Power supply rise time
Power supply fall time
MIN.
1.47
1.46
300
TYP.
1.51
1.50
MAX.
1.55
1.54
Unit
V
VPDR
V
Minimum pulse widthNote
TPW
s
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time
required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is
entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock
operation status control register (CSC).
TPW
Supply voltage (VDD
)
V
POR
VPDR or 0.7 V
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2.6.4 LVD circuit characteristics
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = 40 to +85C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
MIN.
3.98
TYP.
4.06
3.98
3.75
3.67
3.13
3.06
3.02
2.96
2.92
2.86
2.81
2.75
2.71
2.65
2.61
2.55
2.50
2.45
2.09
2.04
1.98
1.94
1.88
1.84
1.77
1.73
1.67
1.63
MAX.
4.14
4.06
3.82
3.74
3.19
3.12
3.08
3.02
2.97
2.91
2.87
2.81
2.76
2.70
2.66
2.60
2.55
2.50
2.13
2.08
2.02
1.98
1.91
1.87
1.81
1.77
1.70
1.66
Unit
V
Detection
voltage
Supply voltage level
VLVD0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
s
s
3.90
3.68
3.60
3.07
3.00
2.96
2.90
2.86
2.80
2.76
2.70
2.66
2.60
2.56
2.50
2.45
2.40
2.05
2.00
1.94
1.90
1.84
1.80
1.74
1.70
1.64
1.60
300
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VLVD8
VLVD9
VLVD10
VLVD11
VLVD12
VLVD13
tLW
Minimum pulse width
Detection delay time
300
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
LVD Detection Voltage of Interrupt & Reset Mode
(TA = 40 to +85C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter Symbol
Conditions
MIN.
1.60
1.74
TYP.
1.63
1.77
MAX.
1.66
1.81
Unit
V
Interrupt and reset VLVDA0
VPOC2, VPOC1, VPOC0 = 0, 0, 0, falling reset voltage
mode
V
VLVDA1
LVIS1, LVIS0 = 1, 0 Rising release reset
voltage
V
V
Falling interrupt voltage
1.70
1.84
1.73
1.88
1.77
1.91
VLVDA2
VLVDA3
LVIS1, LVIS0 = 0, 1 Rising release reset
voltage
V
V
Falling interrupt voltage
1.80
2.86
1.84
2.92
1.87
2.97
LVIS1, LVIS0 = 0, 0 Rising release reset
voltage
V
V
V
Falling interrupt voltage
2.80
1.80
1.94
2.86
1.84
1.98
2.91
1.87
2.02
VLVDB0
VLVDB1
VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage
LVIS1, LVIS0 = 1, 0 Rising release reset
voltage
V
V
Falling interrupt voltage
1.90
2.05
1.94
2.09
1.98
2.13
VLVDB2
VLVDB3
LVIS1, LVIS0 = 0, 1 Rising release reset
voltage
V
V
Falling interrupt voltage
2.00
3.07
2.04
3.13
2.08
3.19
LVIS1, LVIS0 = 0, 0 Rising release reset
voltage
V
V
V
Falling interrupt voltage
3.00
2.40
2.56
3.06
2.45
2.61
3.12
2.50
2.66
VLVDC0
VLVDC1
VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage
LVIS1, LVIS0 = 1, 0 Rising release reset
voltage
V
V
Falling interrupt voltage
2.50
2.66
2.55
2.71
2.60
2.76
VLVDC2
VLVDC3
LVIS1, LVIS0 = 0, 1 Rising release reset
voltage
V
V
Falling interrupt voltage
2.60
3.68
2.65
3.75
2.70
3.82
LVIS1, LVIS0 = 0, 0 Rising release reset
voltage
V
V
V
Falling interrupt voltage
3.60
2.70
2.86
3.67
2.75
2.92
3.74
2.81
2.97
VLVDD0
VLVDD1
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
LVIS1, LVIS0 = 1, 0 Rising release reset
voltage
V
V
Falling interrupt voltage
2.80
2.96
2.86
3.02
2.91
3.08
VLVDD2
LVIS1, LVIS0 = 0, 1 Rising release reset
voltage
V
V
Falling interrupt voltage
2.90
3.98
2.96
4.06
3.02
4.14
VLVDD3
LVIS1, LVIS0 = 0, 0 Rising release reset
voltage
V
Falling interrupt voltage
3.90
3.98
4.06
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.6.5 Power supply voltage rising slope characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
54
Unit
Power supply voltage rising slope
SVDD
V/ms
Caution
Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD
reaches the operating voltage range shown in 2.4 AC Characteristics.
2.7 RAM Data Retention Characteristics
(TA = 40 to +85C, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
VDDDR
1.46Note
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is
generated.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.8 Flash Memory Programming Characteristics
(TA = 40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
1
TYP.
MAX.
32
Unit
CPU/peripheral hardware clock
frequency
fCLK
1.8 V VDD 5.5 V
MHz
Number of code flash rewrites
Notes 1, 2, 3
Cerwr
Retained for 20 years
1,000
Times
TA = 85C
Number of data flash rewrites
Notes 1, 2, 3
Retained for 1 years
1,000,000
TA = 25C
Retained for 5 years
100,000
10,000
TA = 85C
Retained for 20 years
TA = 85C
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library
3. These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
2.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
During serial programming
115,200
1,000,000 bps
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2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85C)
2.10 Timing of Entry to Flash Memory Programming Modes
(TA = 40 to +85C, 1.8 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
tSUINIT
Conditions
MIN.
TYP.
MAX.
100
Unit
ms
Time to complete the
communication for the initial
setting after the external reset is
released
POR and LVD reset must be released before
the external reset is released.
Time to release the external reset tSU
after the TOOL0 pin is set to the
low level
POR and LVD reset must be released before
the external reset is released.
10
1
s
Time to hold the TOOL0 pin at
the low level after the external
reset is released
tHD
POR and LVD reset must be released before
the external reset is released.
ms
(excluding the processing time of
the firmware to control the flash
memory)
<1>
<4>
<2>
<3>
RESET
TOOL0
723 μs + tHD
processing
time
1-byte data for setting mode
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The external reset is released (POR and LVD reset must be released before the
external reset is released.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is
released during this period.
t
SU
:
Time to release the external reset after the TOOL0 pin is set to the low level
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the
processing time of the firmware to control the flash memory)
tHD:
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to
+105C)
This chapter describes the following electrical specifications.
Target products G: Industrial applications TA = 40 to +105°C
R5F100xxGxx
Cautions 1. The RL78 microcontrollers have an on-chip debug function, which is provided for
development and evaluation. Do not use the on-chip debug function in products
designated for mass production, because the guaranteed number of rewritable times of the
flash memory may be exceeded when this function is used, and product reliability therefore
cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the
on-chip debug function is used.
2. With products not provided with an EVDD0, EVDD1, EVSS0, or EVSS1 pin, replace EVDD0 and
EVDD1 with VDD, or replace EVSS0 and EVSS1 with VSS.
3. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions for
each product.
4. Please contact Renesas Electronics sales office for derating of operation under TA = +85C
to +105C. Derating is the systematic reduction of load for the sake of improved reliability.
Remark When RL78/G13 is used in the range of TA = 40 to +85°C, see CHAPTER 2 ELECTRICAL
SPECIFICATIONS (TA = 40 to +85°C).
There are following differences between the products "G: Industrial applications (TA = 40 to +105C)" and the
products “A: Consumer applications, and D: Industrial applications”.
Parameter
Application
A: Consumer applications,
D: Industrial applications
G: Industrial applications
Operating ambient temperature
TA = -40 to +85C
TA = -40 to +105C
Operating mode
HS (high-speed main) mode:
2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
LS (low-speed main) mode:
1.8 V VDD 5.5 V@1 MHz to 8 MHz
LV (low-voltage main) mode:
1.6 V VDD 5.5 V@1 MHz to 4 MHz
1.8 V VDD 5.5 V
HS (high-speed main) mode only:
Operating voltage range
2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
High-speed on-chip oscillator clock
accuracy
2.4 V VDD 5.5 V
1.0%@ TA = -20 to +85C
1.5%@ TA = -40 to -20C
1.6 V VDD < 1.8 V
2.0%@ TA = +85 to +105C
1.0%@ TA = -20 to +85C
1.5%@ TA = -40 to -20C
5.0%@ TA = -20 to +85C
5.5%@ TA = -40 to -20C
UART
Serial array unit
IICA
UART
CSI: fCLK/2 (supporting 16 Mbps), fCLK/4
Simplified I2C communication
Normal mode
CSI: fCLK/4
Simplified I2C communication
Normal mode
Fast mode
Fast mode
Fast mode plus
Voltage detector
Rise detection voltage: 1.67 V to 4.06 V
(14 levels)
Rise detection voltage: 2.61 V to 4.06 V
(8 levels)
Fall detection voltage: 1.63 V to 3.98 V
(14 levels)
Fall detection voltage: 2.55 V to 3.98 V
(8 levels)
(Remark is listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Remark The electrical characteristics of the products G: Industrial applications (TA = -40 to +105C) are different
from those of the products “A: Consumer applications, and D: Industrial applications”. For details, refer to
3.1 to 3.10.
3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25C) (1/2)
Parameter
Symbols
Conditions
Ratings
Unit
V
Supply voltage
VDD
0.5 to +6.5
0.5 to +6.5
0.5 to +0.3
EVDD0, EVDD1 EVDD0 = EVDD1
EVSS0, EVSS1 EVSS0 = EVSS1
V
V
REGC pin input voltage VIREGC
REGC
0.3 to +2.8
and 0.3 to VDD +0.3Note 1
V
Input voltage
VI1
P00 to P07, P10 to P17, P30 to P37, P40 to P47,
P50 to P57, P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
0.3 to EVDD0 +0.3
and 0.3 to VDD +0.3Note 2
V
VI2
P60 to P63 (N-ch open-drain)
0.3 to +6.5
0.3 to VDD +0.3Note 2
V
V
VI3
P20 to P27, P121 to P124, P137, P150 to P156,
EXCLK, EXCLKS, RESET
Output voltage
VO1
P00 to P07, P10 to P17, P30 to P37, P40 to P47,
P50 to P57, P60 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to P117, P120,
P125 to P127, P130, P140 to P147
0.3 to EVDD0 +0.3
and 0.3 to VDD +0.3Note 2
V
VO2
P20 to P27, P150 to P156
ANI16 to ANI26
0.3 to VDD +0.3Note 2
V
V
Analog input voltage
VAI1
0.3 to EVDD0 +0.3
and 0.3 to AVREF(+) +0.3Notes 2, 3
VAI2
ANI0 to ANI14
0.3 to VDD +0.3
and 0.3 to AVREF(+) +0.3Notes 2, 3
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 F). This value regulates the absolute
maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
3. Do not exceed AVREF(+) + 0.3 V in case of A/D conversion target pin.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
2. AVREF (+) : + side reference voltage of the A/D converter.
3.
VSS : Reference voltage
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Absolute Maximum Ratings (TA = 25C) (2/2)
Parameter
Symbols
Conditions
Ratings
Unit
mA
Output current, high
IOH1
Per pin
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P130, P140 to
P147
40
Total of all pins P00 to P04, P07, P32 to P37,
70
mA
mA
170 mA
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to
P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100, P101,
P110 to P117, P146, P147
100
IOH2
Per pin
P20 to P27, P150 to P156
0.5
2
mA
mA
mA
Total of all pins
Per pin
Output current, low
IOL1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P130, P140 to
P147
40
Total of all pins P00 to P04, P07, P32 to P37,
70
mA
mA
170 mA
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to
P145
P05, P06, P10 to P17, P30, P31,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100, P101,
P110 to P117, P146, P147
100
IOL2
Per pin
P20 to P27, P150 to P156
1
mA
mA
C
Total of all pins
5
Operating ambient
temperature
TA
In normal operation mode
40 to +105
In flash memory programming mode
Storage temperature
Tstg
65 to +150
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.2 Oscillator Characteristics
3.2.1 X1, XT1 oscillator characteristics
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V)
Parameter
Resonator
Conditions
2.7 V VDD 5.5 V
2.4 V VDD 2.7 V
MIN.
1.0
1.0
32
TYP.
MAX.
20.0
16.0
35
Unit
MHz
MHz
kHz
X1 clock oscillation
frequency (fX)Note
Ceramic resonator/
crystal resonator
XT1 clock oscillation
frequency (fX)Note
Crystal resonator
32.768
Note Indicates only permissible oscillator frequency ranges. Refer to AC Characteristics for instruction execution
time. Request evaluation by the manufacturer of the oscillator circuit mounted on a board to check the
oscillator characteristics.
Caution Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check
the X1 clock oscillation stabilization time using the oscillation stabilization time counter status
register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and
the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
Remark When using the X1 oscillator and XT1 oscillator, refer to 5.4 System Clock Oscillator.
3.2.2 On-chip oscillator characteristics
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V)
Oscillators
Parameters
Conditions
MIN.
1
TYP. MAX.
32
Unit
High-speed on-chip oscillator
clock frequencyNotes 1, 2
fIH
MHz
High-speed on-chip oscillator
clock frequency accuracy
20 to +85 C
40 to 20 C
+85 to +105 C
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
1.0
1.5
2.0
+1.0
+1.5
%
%
+2.0
%
Low-speed on-chip oscillator
clock frequency
fIL
15
kHz
Low-speed on-chip oscillator
clock frequency accuracy
15
+15
%
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and
bits 0 to 2 of HOCODIV register.
2. This indicates the oscillator characteristics only. Refer to AC Characteristics for instruction execution
time.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.3 DC Characteristics
3.3.1 Pin characteristics
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output current,
highNote 1
IOH1
Per pin for P00 to P07, P10 to P17,
P30 to P37, P40 to P47, P50 to P57, P64
to P67, P70 to P77, P80 to P87, P90 to
P97, P100 to P106,
2.4 V EVDD0 5.5 V
-3.0 Note 2 mA
P110 to P117, P120, P125 to P127,
P130, P140 to P147
Total of P00 to P04, P07, P32 to P37,
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
2.4 V EVDD0 < 2.7 V
-30.0
10.0
5.0
mA
mA
mA
(When duty 70%Note 3
)
Total of P05, P06, P10 to P17, P30, P31, 4.0 V EVDD0 5.5 V
-30.0
19.0
10.0
mA
mA
mA
P50 to P57, P64 to P67, P70 to P77, P80
2.7 V EVDD0 < 4.0 V
to P87, P90 to P97, P100, P101, P110 to
2.4 V EVDD0 < 2.7 V
P117, P146, P147
(When duty 70%Note 3
)
Total of all pins
(When duty 70%Note 3
2.4 V EVDD0 5.5 V
-60.0
mA
)
IOH2
Per pin for P20 to P27, P150 to P156
2,4 V VDD 5.5 V
2.4 V VDD 5.5 V
0.1Note 2 mA
1.5 mA
Total of all pins
(When duty 70%Note 3
)
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD0,
EVDD1, VDD pins to an output pin.
2. Do not exceed the total current value.
3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOH = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and
P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
mA
Output current,
lowNote 1
IOL1
Per pin for P00 to P07, P10 to P17,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
8.5Note 2
P110 to P117, P120, P125 to P127,
P130, P140 to P147
Per pin for P60 to P63
15.0Note 2
40.0
mA
mA
mA
mA
Total of P00 to P04, P07, P32 to
P37,
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
2.4 V EVDD0 < 2.7 V
15.0
P40 to P47, P102 to P106, P120,
P125 to P127, P130, P140 to P145
(When duty 70%Note 3
9.0
)
Total of P05, P06, P10 to P17, P30, 4.0 V EVDD0 5.5 V
40.0
35.0
20.0
mA
mA
mA
P31, P50 to P57, P60 to P67,
2.7 V EVDD0 < 4.0 V
P70 to P77, P80 to P87, P90 to P97,
2,4 V EVDD0 < 2.7 V
P100, P101, P110 to P117, P146,
P147
(When duty 70%Note 3
)
Total of all pins
(When duty 70%Note 3
80.0
mA
)
IOL2
Per pin for P20 to P27, P150 to P156
0.4Note 2
5.0
mA
mA
Total of all pins
2,4 V VDD 5.5 V
(When duty 70%Note 3
)
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS0, EVSS1 and VSS pin.
2. Do not exceed the total current value.
3. Specification under conditions where the duty factor 70%.
The output current value that has changed to the duty factor > 70% the duty ratio can be calculated
with the following expression (when changing the duty factor from 70% to n%).
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 80% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(80 × 0.01) 8.7 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (3/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
Input voltage,
high
VIH1
P00 to P07, P10 to P17, P30 to P37, Normal input buffer 0.8EVDD0
P40 to P47, P50 to P57, P64 to P67,
EVDD0
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
VIH2
P01, P03, P04, P10, P11,
P13 to P17, P43, P44, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V
TTL input buffer
3.3 V
TTL input buffer
2.4 V
2.2
2.0
1.5
EVDD0
EVDD0
EVDD0
V
V
V
EVDD0
5.5 V
4.0 V
3.3 V
EVDD0
EVDD0
VIH3
VIH4
VIH5
VIL1
P20 to P27, P150 to P156
P60 to P63
0.7VDD
0.7EVDD0
0.8VDD
0
VDD
6.0
V
V
V
V
P121 to P124, P137, EXCLK, EXCLKS, RESET
VDD
Input voltage,
low
P00 to P07, P10 to P17, P30 to P37, Normal input buffer
P40 to P47, P50 to P57, P64 to P67,
P70 to P77, P80 to P87, P90 to P97,
P100 to P106, P110 to P117, P120,
P125 to P127, P140 to P147
0.2EVDD0
VIL2
P01, P03, P04, P10, P11,
P13 to P17, P43, P44, P53 to P55,
P80, P81, P142, P143
TTL input buffer
4.0 V
TTL input buffer
3.3 V
TTL input buffer
2.4 V
0
0
0
0.8
0.5
V
V
V
EVDD0
5.5 V
4.0 V
3.3 V
EVDD0
0.32
EVDD0
VIL3
VIL4
VIL5
P20 to P27, P150 to P156
P60 to P63
0
0
0
0.3VDD
0.3EVDD0
0.2VDD
V
V
V
P121 to P124, P137, EXCLK, EXCLKS, RESET
Caution The maximum value of VIH of pins P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55,
P71, P74, P80 to P82, P96, and P142 to P144 is EVDD0, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (4/5)
Items
Symbol
Conditions
P00 to P07, P10 to P17, P30 to
MIN.
TYP.
MAX.
Unit
V
Output voltage,
high
VOH1
4.0 V
EVDD0
5.5 V, EVDD0
P37, P40 to P47, P50 to P57, P64
to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to
P117, P120, P125 to P127, P130,
P140 to P147
I
OH1
=
3.0 mA
0.7
2.7 V
EVDD0
5.5 V, EVDD0
V
V
V
V
V
V
V
V
V
V
V
V
I
OH1
=
2.0 mA
0.6
2.4 V
EVDD0
5.5 V, EVDD0
I
OH1
=
1.5 mA
0.5
VOH2
P20 to P27, P150 to P156
2.4 V VDD 5.5 V, VDD 0.5
IOH2 = 100 A
Output voltage,
low
VOL1
P00 to P07, P10 to P17, P30 to
P37, P40 to P47, P50 to P57, P64
to P67, P70 to P77, P80 to P87,
P90 to P97, P100 to P106, P110 to
P117, P120, P125 to P127, P130,
P140 to P147
4.0 V
EVDD0
5.5 V,
5.5 V,
5.5 V,
5.5 V,
0.7
0.6
0.4
0.4
0.4
2.0
0.4
0.4
0.4
I
OL1 = 8.5 mA
4.0 V
EVDD0
I
OL1 = 3.0 mA
2.7 V
EVDD0
I
OL1 = 1.5 mA
2.4 V
EVDD0
I
OL1 = 0.6 mA
VOL2
P20 to P27, P150 to P156
P60 to P63
2.4 V VDD 5.5 V,
IOL2 = 400 A
VOL3
4.0 V
EVDD0
5.5 V,
5.5 V,
5.5 V,
5.5 V,
I
OL3 = 15.0 mA
4.0 V
EVDD0
I
OL3 = 5.0 mA
2.7 V
EVDD0
I
OL3 = 3.0 mA
2.4 V
EVDD0
I
OL3 = 2.0 mA
Caution P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74, P80 to P82, P96, and
P142 to P144 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 131 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (5/5)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
1
Unit
Input leakage
current, high
ILIH1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
VI = EVDD0
A
P90 to P97, P100 to P106,
P110 to P117, P120,
P125 to P127, P140 to P147
ILIH2
P20 to P27, P137,
VI = VDD
VI = VDD
1
1
A
A
P150 to P156, RESET
ILIH3
P121 to P124
In input port or
external clock
input
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
In resonator
connection
10
A
A
Input leakage
current, low
ILIL1
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
VI = EVSS0
1
P125 to P127, P140 to P147
ILIL2
P20 to P27, P137,
VI = VSS
VI = VSS
1
1
A
A
P150 to P156, RESET
ILIL3
P121 to P124
In input port or
external clock
input
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
In resonator
connection
10
A
k
On-chip pll-up
resistance
RU
P00 to P07, P10 to P17,
P30 to P37, P40 to P47,
P50 to P57, P64 to P67,
P70 to P77, P80 to P87,
P90 to P97, P100 to P106,
P110 to P117, P120,
VI = EVSS0, In input port
10
20
100
P125 to P127, P140 to P147
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 132 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.3.2 Supply current characteristics
(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
(TA = 40 to +105C, 2.4 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) (1/2)
Parameter Symbol
Conditions
fIH = 32 MHzNote 3
MIN.
TYP. MAX.
Unit
mA
mA
Supply
IDD1
Operating HS (high-
Basic
operatio
n
VDD = 5.0 V
VDD = 3.0 V
2.1
2.1
current
mode
speed main)
Note 1
modeNote 5
Normal
operatio
n
VDD = 5.0 V
VDD = 3.0 V
4.6
4.6
7.5
7.5
mA
mA
fIH = 24 MHzNote 3
fIH = 16 MHzNote 3
Normal
operatio
n
VDD = 5.0 V
VDD = 3.0 V
3.7
3.7
5.8
5.8
mA
mA
Normal
operatio
n
VDD = 5.0 V
VDD = 3.0 V
2.7
2.7
4.2
4.2
mA
mA
HS (high-
fMX = 20 MHzNote 2
VDD = 5.0 V
,
,
,
,
Normal
operatio
n
Square wave input
3.0
3.2
4.9
5.0
mA
mA
speed main)
Resonator
connection
modeNote 5
fMX = 20 MHzNote 2
VDD = 3.0 V
Normal
operatio
n
Square wave input
3.0
3.2
4.9
5.0
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 5.0 V
Normal
operatio
n
Square wave input
1.9
1.9
2.9
2.9
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 3.0 V
Normal
operatio
n
Square wave input
1.9
1.9
2.9
2.9
mA
Resonator
connection
mA
Subsystem fSUB = 32.768 kHz Normal
Square wave input
4.1
4.2
4.9
5.0
A
A
Note 4
clock
operatio
n
Resonator
connection
operation
TA = 40C
fSUB = 32.768 kHz Normal
Square wave input
4.1
4.2
4.9
5.0
A
A
Note 4
operatio
Resonator
connection
n
TA = +25C
fSUB = 32.768 kHz Normal
Square wave input
4.2
4.3
5.5
5.6
A
A
Note 4
operatio
Resonator
connection
n
TA = +50C
fSUB = 32.768 kHz Normal
Square wave input
4.3
4.4
6.3
6.4
A
A
Note 4
operatio
Resonator
connection
n
TA = +70C
fSUB = 32.768 kHz Normal
Square wave input
4.6
4.7
7.7
7.8
A
A
Note 4
operation
Resonator
connection
TA = +85C
fSUB = 32.768 kHz Normal
Square wave input
6.9
7.0
19.7
19.8
A
A
Note 4
operation
Resonator
connection
TA = +105C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 133 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the RTC, 12-
bit interval timer, and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 134 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
(TA = 40 to +105C, 2.4 V EVDD0 VDD 5.5 V, VSS = EVSS0 = 0 V) (2/2)
Parameter Symbol
Conditions
MIN.
TYP.
0.54
0.54
0.44
0.44
0.40
0.40
0.28
0.45
0.28
0.45
0.19
0.26
0.19
0.26
0.25
0.44
0.30
0.49
0.37
0.56
0.53
0.72
0.82
1.01
3.01
3.20
0.18
0.23
0.30
0.46
0.75
2.94
MAX.
2.90
2.90
2.30
2.30
1.70
1.70
1.90
2.00
1.90
2.00
1.02
1.10
1.02
1.10
0.57
0.76
0.57
0.76
1.17
1.36
1.97
2.16
3.37
3.56
15.37
15.56
0.50
0.50
1.10
1.90
3.30
15.30
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
fIH = 32 MHzNote 4
VDD = 5.0 V
HS (high-
Supply
IDD2
Note 2
HALT
mode
speed main)
current
Note 1
modeNote 7
VDD = 3.0 V
fIH = 24 MHzNote 4
fIH = 16 MHzNote 4
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
fMX = 20 MHzNote 3
VDD = 5.0 V
,
,
,
,
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
HS (high-
speed main)
modeNote 7
fMX = 20 MHzNote 3
VDD = 3.0 V
fMX = 10 MHzNote 3
VDD = 5.0 V
fMX = 10 MHzNote 3
VDD = 3.0 V
Subsystem fSUB = 32.768 kHzNote 5
clock
TA = 40C
A
operation
fSUB = 32.768 kHzNote 5
A
TA = +25C
fSUB = 32.768 kHzNote 5
TA = +50C
A
A
A
fSUB = 32.768 kHzNote 5
A
TA = +70C
A
fSUB = 32.768 kHzNote 5
TA = +85C
A
A
fSUB = 32.768 kHzNote 5
A
TA = +105C
A
Note 6
IDD3
STOP
modeNote 8
TA = 40C
A
TA = +25C
A
TA = +50C
A
TA = +70C
A
TA = +85C
A
TA = +105C
A
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 135 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 136 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (1/2)
Parameter Symbol
Conditions
fIH = 32 MHzNote 3
MIN.
TYP. MAX.
Unit
mA
mA
Supply
IDD1
Operating HS (high-
Basic
operatio
n
VDD = 5.0 V
VDD = 3.0 V
2.3
2.3
current
mode
speed main)
modeNote 5
Note 1
Normal
operatio
n
VDD = 5.0 V
VDD = 3.0 V
5.2
5.2
9.2
9.2
mA
mA
fIH = 24 MHzNote 3
fIH = 16 MHzNote 3
Normal
operatio
n
VDD = 5.0 V
VDD = 3.0 V
4.1
4.1
7.0
7.0
mA
mA
Normal
operatio
n
VDD = 5.0 V
VDD = 3.0 V
3.0
3.0
5.0
5.0
mA
mA
HS (high-
fMX = 20 MHzNote 2
VDD = 5.0 V
,
,
,
,
Normal
operatio
n
Square wave input
3.4
3.6
5.9
6.0
mA
mA
speed main)
Resonator
connection
modeNote 5
fMX = 20 MHzNote 2
VDD = 3.0 V
Normal
operatio
n
Square wave input
3.4
3.6
5.9
6.0
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 5.0 V
Normal
operatio
n
Square wave input
2.1
2.1
3.5
3.5
mA
Resonator
connection
mA
fMX = 10 MHzNote 2
VDD = 3.0 V
Normal
operatio
n
Square wave input
2.1
2.1
3.5
3.5
mA
Resonator
connection
mA
Subsystem fSUB = 32.768 kHz Normal
Square wave input
4.8
4.9
5.9
6.0
A
A
Note 4
clock
operatio
n
Resonator
connection
operation
TA = 40C
fSUB = 32.768 kHz Normal
Square wave input
4.9
5.0
5.9
6.0
A
A
Note 4
operatio
Resonator
connection
n
TA = +25C
fSUB = 32.768 kHz Normal
Square wave input
5.0
5.1
7.6
7.7
A
A
Note 4
operatio
Resonator
connection
n
TA = +50C
fSUB = 32.768 kHz Normal
Square wave input
5.2
5.3
9.3
9.4
A
A
Note 4
operatio
Resonator
connection
n
TA = +70C
fSUB = 32.768 kHz Normal
Square wave input
5.7
5.8
13.3
13.4
A
A
Note 4
operatio
Resonator
connection
n
TA = +85C
fSUB = 32.768 kHz Normal
Square wave input
10.0
10.0
46.0
46.0
A
A
Note 4
operatio
Resonator
connection
n
TA = +105C
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 137 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the
MAX. column include the peripheral operation current. However, not including the current flowing into the
A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during
data flash rewrite.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When AMPHS1 = 1
(Ultra-low power consumption oscillation). However, not including the current flowing into the 12-bit
interval timer and watchdog timer.
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 138 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(2) Flash ROM: 96 to 256 KB of 30- to 100-pin products
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Parameter Symbol
Conditions
fIH = 32 MHzNote 4
MIN.
TYP.
0.62
0.62
0.50
0.50
0.44
0.44
0.31
0.48
MAX.
3.40
3.40
2.70
2.70
1.90
1.90
2.10
2.20
Unit
mA
mA
mA
mA
mA
mA
mA
mA
Supply
current
IDD2
HALT
mode
HS (high-
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
Square wave input
Note 2
speed main)
Note 1
modeNote 7
fIH = 24 MHzNote 4
fIH = 16 MHzNote 4
HS (high-
fMX = 20 MHzNote 3
VDD = 5.0 V
,
,
,
,
speed main)
Resonator
connection
modeNote 7
fMX = 20 MHzNote 3
VDD = 3.0 V
Square wave input
0.31
0.48
2.10
2.20
mA
mA
Resonator
connection
fMX = 10 MHzNote 3
VDD = 5.0 V
Square wave input
0.21
0.28
1.10
1.20
mA
mA
Resonator
connection
fMX = 10 MHzNote 3
VDD = 3.0 V
Square wave input
0.21
0.28
1.10
1.20
mA
mA
Resonator
connection
Subsystem fSUB = 32.768 kHzNote 5
Square wave input
0.28
0.47
0.61
0.80
A
A
clock
TA = 40C
Resonator
connection
operation
fSUB = 32.768 kHzNote 5
Square wave input
0.34
0.53
0.61
0.80
A
A
TA = +25C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.41
0.60
2.30
2.49
A
A
TA = +50C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
0.64
0.83
4.03
4.22
A
A
TA = +70C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
1.09
1.28
8.04
8.23
A
A
TA = +85C
Resonator
connection
fSUB = 32.768 kHzNote 5
Square wave input
5.50
5.50
41.00
41.00
A
A
TA = +105C
Resonator
connection
Note 6
IDD3
STOP
TA = 40C
TA = +25C
TA = +50C
TA = +70C
TA = +85C
TA = +105C
0.19
0.25
0.32
0.55
1.00
5.00
0.52
0.52
2.21
3.94
7.95
40.00
A
A
A
A
A
A
modeNote 8
(Notes and Remarks are listed on the next page.)
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 139 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Notes 1. Total current flowing into VDD, EVDD0, and EVDD1, including the input leakage current flowing when the
level of the input pin is fixed to VDD, EVDD0, and EVDD1, or VSS, EVSS0, and EVSS1. The values below the
MAX. column include the peripheral operation current. However, not including the current flowing into the
A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during
data flash rewrite.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When high-speed on-chip oscillator and high-speed system clock are stopped. When RTCLPC = 1 and
setting ultra-low current consumption (AMPHS1 = 1). The current flowing into the RTC is included.
However, not including the current flowing into the 12-bit interval timer and watchdog timer.
6. Not including the current flowing into the RTC, 12-bit interval timer, and watchdog timer.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
HS (high-speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 32 MHz
2.4 V VDD 5.5 V@1 MHz to 16 MHz
8. Regarding the value for current operate the subsystem clock in STOP mode, refer to that in HALT mode.
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25C
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 140 of 196
RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(3) Peripheral Functions (Common to all products)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
0.20
MAX.
Unit
Low-speed on-
chip oscillator
operating
IFIL
Note 1
A
current
RTC operating
current
IRTC
0.02
0.02
A
A
Notes 1, 2, 3
12-bit interval
timer operating
current
IIT
Notes 1, 2, 4
Watchdog timer IWDT
fIL = 15 kHz
0.22
A
Notes 1, 2, 5
operating
current
A/D converter
operating
current
IADC
When conversion Normal mode, AVREFP = VDD = 5.0 V
1.3
0.5
1.7
0.7
mA
mA
Notes 1, 6
at maximum
Low voltage mode, AVREFP = VDD = 3.0 V
speed
A/D converter
reference
IADREF
75.0
A
Note 1
voltage current
Temperature
sensor
ITMPS
75.0
A
Note 1
operating
current
LVD operating
current
ILVD
0.08
2.50
A
Notes 1, 7
mA
Self
IFSP
Notes 1, 9
12.20
12.20
programming
operating
current
mA
BGO operating
current
IBGO
Notes 1, 8
2.50
mA
mA
SNOOZE
ISNOZ
Note 1
ADC operation
The mode is performed Note 10
0.50
1.20
1.10
2.04
operating
current
The A/D conversion operations are
performed, Loe voltage mode, AVREFP =
VDD = 3.0 V
mA
CSI/UART operation
0.70
1.54
Notes 1. Current flowing to the VDD.
2. When high speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-
chip oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode.
When the low-speed on-chip oscillator is selected, IFIL should be added. IDD2 subsystem clock operation
includes the operational current of the real-time clock.
4. Current flowing only to the 12-bit interval timer (excluding the operating current of the low-speed on-chip
oscillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the
values of either IDD1 or IDD2, and IIT, when the 12-bit interval timer operates in operation mode or HALT
mode. When the low-speed on-chip oscillator is selected, IFIL should be added.
5. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The supply current of the RL78 is the sum of IDD1, IDD2 or IDD3 and IWDT when the watchdog
timer operates.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
6. Current flowing only to the A/D converter. The supply current of the RL78 microcontrollers is the sum of
IDD1 or IDD2 and IADC when the A/D converter is in operation.
7. Current flowing only to the LVD circuit. The supply current of the RL78 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and ILVD when the LVD circuit is in operation.
8. Current flowing only during data flash rewrite.
9. Current flowing only during self programming.
10.For shift time to the SNOOZE mode, see 18.3.3 SNOOZE mode in the RL78/G13 User’s Manual.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25C
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.4 AC Characteristics
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
s
Instruction cycle (minimum
instruction execution time)
TCY
Main
system
clock (fMAIN)
operation
2.7 V
2.4 V
V
DD
5.5 V 0.03125
1
1
HS (high-speed
main) mode
V
DD < 2.7 V 0.0625
s
Subsystem clock (fSUB)
operation
2.4 V
V
DD
5.5 V
28.5
30.5
31.3
s
In the self
programming
mode
2.7 V
2.4 V
VDD
5.5 V 0.03125
1
1
s
s
HS (high-speed
main) mode
VDD < 2.7 V 0.0625
External system clock frequency
fEX
2.7 V VDD 5.5 V
2.4 V VDD < 2.7 V
1.0
1.0
32
20.0
16.0
35
MHz
MHz
kHz
ns
fEXS
External system clock input high- tEXH, tEXL 2.7 V VDD 5.5 V
24
level width, low-level width
2.4 V VDD < 2.7 V
30
ns
tEXHS,
tEXLS
13.7
s
TI00 to TI07, TI10 to TI17 input
high-level width, low-level width
tTIH,
1/fMCK+10
nsNote
tTIL
TO00 to TO07, TO10 to TO17
output frequency
fTO
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
2.4 V EVDD0 < 2.7 V
4.0 V EVDD0 5.5 V
2.7 V EVDD0 < 4.0 V
2.4 V EVDD0 < 2.7 V
2.4 V VDD 5.5 V
16
8
MHz
MHz
MHz
MHz
MHz
MHz
s
HS (high-speed
main) mode
4
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
HS (high-speed
main) mode
16
8
4
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0
1
1
INTP1 to INTP11
KR0 to KR7
2.4 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
s
Key interrupt input low-level width tKR
RESET low-level width
250
10
ns
tRSL
s
Note The following conditions are required for low voltage interface when EVDD0 < VDD
2.4V EVDD0 < 2.7 V : MIN. 125 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKSmn0, CKSmn1 bits of timer mode register mn (TMRmn).
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Minimum Instruction Execution Time during Main System Clock Operation
TCY vs VDD (HS (high-speed main) mode)
10
1.0
When the high-speed on-chip oscillator clock is selected
During self programming
When high-speed system clock is selected
0.1
0.0625
0.05
0.03125
0.01
5.5
0
1.0
2.0
2.4
3.0
2.7
4.0
5.0
6.0
Supply voltage VDD [V]
AC Timing Test Points
V
V
IH/VOH
IL/VOL
V
IH/VOH
IL/VOL
Test points
V
External System Clock Timing
1/fEX
/
1/fEXS
t
EXL
/
t
t
EXH
/
tEXLS
EXHS
EXCLK/EXCLKS
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
TI/TO Timing
tTIL
tTIH
TI00 to TI07, TI10 to TI17
1/fTO
TO00 to TO07, TO10 to TO17
Interrupt Request Input Timing
t
INTL
tINTH
INTP0 to INTP11
Key Interrupt Input Timing
tKR
KR0 to KR7
RESET Input Timing
tRSL
RESET
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.5 Peripheral Functions Characteristics
AC Timing Test Points
V
IH/VOH
V
IH/VOH
Test points
VIL/VOL
VIL/VOL
3.5.1 Serial array unit
(1) During communication at same potential (UART mode)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
MAX.
fMCK/12Note 2
2.6
Transfer rateNote 1
bps
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V EVDD0 < 2.7 V : MAX. 1.3 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
UART mode connection diagram (during communication at same potential)
TxDq
RxDq
Rx
Tx
User device
RL78 microcontroller
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Remarks 1. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
250
MAX.
SCKp cycle time
tKCY1
tKCY1 4/fCLK 2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500
SCKp high-/low-level width
tKH1,
tKL1
tKCY1/2 24
tKCY1/2 36
tKCY1/2 76
66
SIp setup time (to SCKp)Note 1
tSIK1
66
113
SIp hold time (from SCKp) Note 2 tKSI1
38
Delay time from SCKp to
SOp output Note 3
tKSO1
C = 30 pF Note 4
50
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 0
to 3),
g: PIM and POM numbers (g = 0, 1, 4, 5, 8, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
16/fMCK
MAX.
SCKp cycle timeNote 5
tKCY2
4.0 V EVDD0 5.5
20 MHz < fMCK
fMCK 20 MHz
16 MHz < fMCK
fMCK 16 MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
12/fMCK
2.7 V EVDD0 5.5
16/fMCK
V
12/fMCK
2.4 V EVDD0 5.5 V
16/fMCK
12/fMCK and 1000
tKCY2/2 14
tKCY2/2 16
tKCY2/2 36
1/fMCK+40
1/fMCK+60
1/fMCK+62
SCKp high-/low-level
width
tKH2,
4.0 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
2.7 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
2.4 V EVDD0 5.5 V
tKL2
SIp setup time
(to SCKp) Note 1
tSIK2
SIp hold time
(from SCKp) Note 2
tKSI2
Delay time from
tKSO2
C = 30 pF Note 4
2.7 V EVDD0 5.5
2/fMCK+66
ns
ns
SCKp to SOp output
V
Note 3
2.4 V EVDD0 5.5
2/fMCK+113
V
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
CSI mode connection diagram (during communication at same potential)
SCKp
SIp
SCK
SO
RL78
User device
microcontroller
SOp
SI
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KCY1, 2
t
KL1, 2
t
KH1, 2
SCKp
t
SIK1, 2
t
KSI1, 2
SIp
Input data
tKSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t
KCY1, 2
tKH1, 2
t
KL1, 2
SCKp
t
SIK1, 2
t
KSI1, 2
SIp
Input data
tKSO1, 2
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31)
2. m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(4) During communication at same potential (simplified I2C mode)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
Unit
MIN.
MAX.
SCLr clock frequency
fSCL
400Note1
kHz
kHz
ns
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
2.4 V EVDD 5.5 V,
Cb = 100 pF, Rb = 3 k
2.7 V EVDD0 5.5 V,
Cb = 50 pF, Rb = 2.7 k
2.4 V EVDD0 5.5 V,
Cb = 100 pF, Rb = 3 k
100Note1
Hold time when SCLr = “L”
Hold time when SCLr = “H”
Data setup time (reception)
Data hold time (transmission)
tLOW
1200
4600
1200
4600
ns
tHIGH
ns
ns
tSU:DAT
tHD:DAT
1/fMCK + 220
ns
Note2
1/fMCK + 580
ns
Note2
0
0
770
ns
1420
ns
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin
products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the normal
output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode
register h (POMh).
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Simplified I2C mode mode connection diagram (during communication at same potential)
VDD
R
b
SDAr
RL78 microcontroller
SDA
SCL
User device
SCLr
Simplified I2C mode serial transfer timing (during communication at same potential)
1/fSCL
tLOW
t
HIGH
SCLr
SDAr
t
HD:DAT
tSU:DAT
Remarks 1. Rb[]:Communication line (SDAr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr) load
capacitance
2. r: IIC number (r = 00, 01, 10, 11, 20, 21, 30, 31), g: PIM number (g = 0, 1, 4, 5, 8, 14),
h: POM number (g = 0, 1, 4, 5, 7 to 9, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m
= 0, 1), n: Channel number (n = 0 to 3), mn = 00 to 03, 10 to 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
Unit
MIN.
MAX.
Note 1
Transfer rate
Reception 4.0 V EVDD0 5.5
fMCK/12
2.6
bps
V,
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Mbps
2.7 V Vb 4.0 V
Note 1
2.7 V EVDD0 < 4.0
fMCK/12
2.6
bps
V,
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
Mbps
2.3 V Vb 2.7 V
2.4 V EVDD0 < 3.3
fMCK/12
Notes 1,2
bps
V,
1.6 V Vb 2.0 V
Theoretical value of the
maximum transfer rate
fCLK = 32 MHz, fMCK = fCLK
2.6
Mbps
Notes 1. Transfer rate in the SNOOZE mode is 4800 bps only.
2. The following conditions are required for low voltage interface when EVDD0 < VDD.
2.4 V EVDD0 < 2.7 V : MAX. 1.3 Mbps
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the
20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
Remarks 1. Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13)
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(5) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode Unit
MIN.
MAX.
Transfer rate
Transmission 4.0 V EVDD0 5.5
Note 1
bps
V,
Theoretical value of the
maximum transfer rate
2.6 Note 2
Mbps
2.7 V Vb 4.0 V
C
b
= 50 pF, R
b
= 1.4 k
, V
b
= 2.7
= 2.3
V
2.7 V EVDD0 < 4.0
Note 3
bps
V,
Theoretical value of the
maximum transfer rate
1.2 Note 4
Mbps
2.3 V Vb 2.7 V
Cb
= 50 pF, R
b
= 2.7 k
, V
b
V
2.4 V EVDD0 < 3.3
Note 5
bps
V,
Theoretical value of the
maximum transfer rate
0.43
Note 6
Mbps
1.6 V Vb 2.0 V
Cb
= 50 pF, R
b
= 5.5 k
, V
b
= 1.6
V
Notes 1. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V EVDD0 5.5 V and 2.7 V Vb 4.0 V
1
Maximum transfer rate =
[bps]
2.2
Vb
{Cb × Rb × ln (1
)} × 3
1
2.2
Vb
{Cb × Rb × ln (1
)}
Transfer rate 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
2. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
3. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V EVDD0 < 4.0 V and 2.4 V Vb 2.7 V
1
Maximum transfer rate =
[bps]
2.0
Vb
{Cb × Rb × ln (1
)} × 3
1
2.0
Vb
{Cb × Rb × ln (1
)}
Transfer rate 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
4. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
5. The smaller maximum transfer rate derived by using fMCK/12 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.4 V EVDD0 < 3.3 V and 1.6 V Vb 2.0 V
1
Maximum transfer rate =
[bps]
1.5
Vb
{Cb × Rb × ln (1
)} × 3
1
1.5
Vb
{Cb × Rb × ln (1
)}
Transfer rate 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
* This value is the theoretical value of the relative difference between the transmission and reception sides.
6. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance (for the
20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg). For VIH and VIL,
see the DC characteristics with TTL input buffer selected.
UART mode connection diagram (during communication at different potential)
V
b
R
b
TxDq
RxDq
Rx
Tx
User device
RL78 microcontroller
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Remarks 1. Rb[]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
4. UART2 cannot communicate at different potential when bit 1 (PIOR1) of peripheral I/O redirection
register (PIOR) is 1.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (1/3)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
ns
MIN.
600
MAX.
SCKp cycle time
tKCY1
tKCY1 4/fCLK 4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0
V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7
1000
2300
ns
ns
V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0
V,
Cb = 30 pF, Rb = 5.5 k
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
SCKp high-level width tKH1
tKCY1/2 150
tKCY1/2 340
tKCY1/2 916
tKCY1/2 24
tKCY1/2 36
tKCY1/2 100
ns
ns
ns
ns
ns
ns
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
SCKp low-level width tKL1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the
20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed two pages after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (2/3)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
162
MAX.
SIp setup time
tSIK1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
ns
ns
ns
ns
ns
ns
ns
ns
ns
(to SCKp)Note
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
354
958
38
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
(from SCKp) Note
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
38
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 2.7 k
38
Delay time from SCKp to
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
200
390
966
SOp output Note
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Note When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the
20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the page after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (master mode, SCKp... internal clock
output) (3/3)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
88
MAX.
SIp setup time
tSIK1
4.0 V EVDD 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
ns
ns
ns
ns
ns
ns
ns
ns
ns
(to SCKp)Note
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
88
220
38
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
SIp hold time
tKSI1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
(from SCKp) Note
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
38
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
38
Delay time from SCKp to
tKSO1
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
50
50
50
SOp output Note
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V,
Cb = 30 pF, Rb = 5.5 k
Note When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance (for the
20- to 52-pin products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
R
b
Rb
SCKp
SIp
SCK
SO
RL78
microcontroller
User device
SOp
SI
Remarks 1. Rb[]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number , n: Channel number (mn = 00, 01, 02, 10,
12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00))
4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1
t
KH1
SCKp
t
SIK1
tKSI1
SIp
Input data
t
KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
t
KL1
t
KH1
SCKp
tSIK1
t
KSI1
SIp
Input data
t
KSO1
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 00, 01, 02, 10, 12, 13), n: Channel
number (n = 0, 2), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(7) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock
input)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
MIN.
MAX.
SCKp cycle timeNote 1
tKCY2
4.0 V
V,
EVDD0
5.5
24 MHz < fMCK
28/fMCK
24/fMCK
20/fMCK
16/fMCK
12/fMCK
40/fMCK
32/fMCK
28/fMCK
24/fMCK
16/fMCK
12/fMCK
96/fMCK
72/fMCK
64/fMCK
52/fMCK
32/fMCK
20/fMCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20 MHz < fMCK 24 MHz
8 MHz < fMCK 20 MHz
4 MHz < fMCK 8 MHz
fMCK 4 MHz
2.7 V
Vb 4.0 V
2.7 V
V,
EVDD0 < 4.0
24 MHz < fMCK
20 MHz < fMCK 24 MHz
16 MHz < fMCK 20 MHz
8 MHz < fMCK 16 MHz
4 MHz < fMCK 8 MHz
fMCK 4 MHz
2.3 V
Vb 2.7 V
2.4 V
V,
EVDD0 < 3.3
24 MHz < fMCK
20 MHz < fMCK 24 MHz
16 MHz < fMCK 20 MHz
8 MHz < fMCK 16 MHz
4 MHz < fMCK 8 MHz
fMCK 4 MHz
1.6 V
Vb 2.0 V
SCKp high-/low-level
width
tKH2,
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V
tKCY2/2 24
tKL2
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V
t
KCY2/2 36
ns
ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 VNote 2
t
KCY2/2 100
SIp setup time
tSIK2
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V
1/fMCK + 40
1/fMCK + 40
1/fMCK + 60
1/fMCK + 62
ns
ns
ns
ns
ns
ns
ns
(to SCKp) Note2
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V
SIp hold time
(from SCKp) Note 3
tKSI2
Delay time from SCKp
to SOp output Note 4
tKSO2
4.0 V EVDD0 5.5 V, 2.7 V Vb 4.0 V,
Cb = 30 pF, Rb = 1.4 k
2/fMCK + 240
2/fMCK + 428
2/fMCK + 1146
2.7 V EVDD0 < 4.0 V, 2.3 V Vb 2.7 V,
Cb = 30 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V, 1.6 V Vb 2.0 V
Cb = 30 pF, Rb = 5.5 k
(Notes, Caution and Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 128-pin products)) mode
for the SOp pin by using port input mode register g (PIMg) and port output mode register g
(POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
R
b
SCKp
SIp
SCK
SO
RL78
User device
microcontroller
SOp
SI
Remarks 1. Rb[]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number (m = 0, 1), n: Channel number (n = 00, 01,
02,
10, 12, 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01, 02, 10, 12, 13))
4. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KCY2
tKL2
tKH2
SCKp
t
SIK2
t
KSI2
SIp
Input data
t
KSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
t
KL2
tKH2
SCKp
t
SIK2
t
KSI2
SIp
Input data
t
KSO2
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01, 10, 20, 30, 31), m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12. 13), g: PIM and POM number (g = 0, 1, 4, 5, 8, 14)
2. CSI01 of 48-, 52-, 64-pin products, and CSI11 and CSI21 cannot communicate at different potential.
Use other CSI for communication at different potential.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (1/2)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
Unit
MIN.
MAX.
SCLr clock frequency
fSCL
400Note 1
kHz
kHz
kHz
kHz
kHz
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
400Note 1
100Note 1
100Note 1
100Note 1
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr = “L”
tLOW
1200
1200
4600
4600
4650
620
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
Hold time when SCLr = “H”
tHIGH
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
500
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
2700
2400
1830
ns
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
ns
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
ns
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
(Notes and Caution are listed on the next page, and Remarks are listed on the page after the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main)
Mode
Unit
MIN.
MAX.
Data setup time (reception)
tSU:DAT
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 2
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
1/fMCK + 340
Note 2
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1/fMCK + 760
Note 2
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
1/fMCK + 760
Note 2
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
1/fMCK + 570
Note 2
Data hold time (transmission)
tHD:DAT
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 50 pF, Rb = 2.7 k
0
0
0
0
0
770
770
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 50 pF, Rb = 2.7 k
4.0 V EVDD0 5.5 V,
2.7 V Vb 4.0 V,
Cb = 100 pF, Rb = 2.8 k
1420
1420
1215
2.7 V EVDD0 < 4.0 V,
2.3 V Vb 2.7 V,
Cb = 100 pF, Rb = 2.7 k
2.4 V EVDD0 < 3.3 V,
1.6 V Vb 2.0 V,
Cb = 100 pF, Rb = 5.5 k
Notes 1. The value must also be equal to or less than fMCK/4.
2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin
products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-
pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
Simplified I2C mode connection diagram (during communication at different potential)
V
b
Vb
R
b
Rb
SDAr
SDA
User device
SCL
RL78
microcontroller
SCLr
Simplified I2C mode serial transfer timing (during communication at different potential)
1/fSCL
tLOW
tHIGH
SCLr
SDAr
tHD:DAT
t
SU:DAT
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin
products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the N-ch
open drain output (VDD tolerance (for the 20- to 52-pin products)/EVDD tolerance (for the 64- to 100-
pin products)) mode for the SCLr pin by using port input mode register g (PIMg) and port output
mode register g (POMg). For VIH and VIL, see the DC characteristics with TTL input buffer selected.
Remarks 1. Rb[]:Communication line (SDAr, SCLr) pull-up resistance, Cb[F]: Communication line (SDAr, SCLr)
load capacitance, Vb[V]: Communication line voltage
2. r: IIC number (r = 00, 01, 10, 20, 30, 31), g: PIM, POM number (g = 0, 1, 4, 5, 8, 14)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01, 02, 10, 12, 13)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.5.2 Serial interface IICA
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
HS (high-speed main) Mode
Unit
Standard
Mode
Fast Mode
MIN. MAX. MIN. MAX.
SCLA0 clock frequency
fSCL
Fast mode: fCLK 3.5 MHz
0
0
400
kHz
kHz
s
Standard mode: fCLK 1 MHz
100
Setup time of restart condition
Hold timeNote 1
tSU:STA
tHD:STA
tLOW
4.7
4.0
4.7
4.0
250
0
0.6
0.6
1.3
0.6
100
0
s
Hold time when SCLA0 = “L”
Hold time when SCLA0 = “H”
Data setup time (reception)
Data hold time (transmission)Note 2
Setup time of stop condition
Bus-free time
s
tHIGH
s
tSU:DAT
tHD:DAT
tSU:STO
tBUF
ns
3.45
0.9
s
4.0
4.7
0.6
1.3
s
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
<R>
(acknowledge) timing.
Caution The values in the above table are applied even when bit 2 (PIOR2) in the peripheral I/O redirection
register (PIOR) is 1. At this time, the pin characteristics (IOH1, IOL1, VOH1, VOL1) must satisfy the
values in the redirect destination.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 k
Fast mode:
Cb = 320 pF, Rb = 1.1 k
IICA serial transfer timing
t
LOW
t
R
SCLAn
SDAAn
t
HD:DAT
t
HIGH
SU:DAT
t
F
tSU:STA
t
HD:STA
t
SU:STO
t
HD:STA
t
t
BUF
Stop
Start
Restart
condition
Stop
condition
condition condition
Remark n = 0, 1
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.6 Analog Characteristics
3.6.1 A/D converter characteristics
Classification of A/D converter characteristics
Reference Voltage
Reference voltage (+) = VDD
Reference voltage () = VSS
Refer to 3.6.1 (3).
Reference voltage (+) = AVREFP
Reference voltage (+) = VBGR
Reference voltage () = AVREFM
Refer to 3.6.1 (4).
Input channel
Reference voltage () = AVREFM
Refer to 3.6.1 (1).
ANI0 to ANI14
ANI16 to ANI26
Refer to 3.6.1 (2).
Internal reference voltage
Temperature sensor output
voltage
Refer to 3.6.1 (1).
(1) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI2 to ANI14, internal reference voltage, and temperature
sensor output voltage
(TA = 40 to +105C, 2.4 V AVREFP VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage () = AVREFM = 0 V)
Parameter
Resolution
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Overall errorNote 1
AINL
10-bit resolution
2.4 V AVREFP 5.5 V
1.2
3.5
LSB
Note 3
AVREFP = VDD
Conversion time
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.7 V VDD 5.5 V
2.4 V VDD 5.5 V
2.125
3.1875
17
39
39
39
39
39
39
s
s
s
s
s
s
Target pin: ANI2 to ANI14
10-bit resolution
3.6 V VDD 5.5 V
2.7 V VDD 5.5 V
2.4 V VDD 5.5 V
2.375
3.5625
17
Target pin: Internal reference
voltage, and temperature
sensor output voltage (HS
(high-speed main) mode)
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
EZS
EFS
ILE
0.25
0.25
2.5
%FSR
%FSR
LSB
10-bit resolution
AVREFP = VDD
2.4 V AVREFP 5.5
V
Note 3
10-bit resolution
2.4 V AVREFP 5.5
V
Note 3
AVREFP = VDD
2.4 V AVREFP 5.5
V
Integral linearity error
Note 1
10-bit resolution
Note 3
AVREFP = VDD
2.4 V AVREFP 5.5
V
Differential linearity error DLE
Note 1
10-bit resolution
1.5
LSB
Note 3
AVREFP = VDD
Analog input voltage
VAIN
ANI2 to ANI14
0
AVREFP
V
V
Note 4
Internal reference voltage output
VBGR
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
Note 4
Temperature sensor output voltage
VTMPS25
V
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
(Notes are listed on the next page.)
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Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD
.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD
.
Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD
4. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage () =
AVREFM/ANI1 (ADREFM = 1), target pin : ANI16 to ANI26
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, 2.4 V AVREFP VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V,
Reference voltage (+) = AVREFP, Reference voltage () = AVREFM = 0 V)
Parameter
Resolution
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Overall errorNote 1
AINL
10-bit resolution
2.4 V AVREFP 5.5
1.2
5.0
LSB
Notes 3, 4
EVDD0 AVREFP = VDD
V
Conversion time
tCONV
10-bit resolution
3.6 V VDD 5.5 V
2.7 V VDD 5.5 V
2.4 V VDD 5.5 V
2.125
3.1875
17
39
39
s
s
Target pin : ANI16 to ANI26
39
s
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
EZS
EFS
2.4 V AVREFP 5.5
0.35
%FSR
10-bit resolution
EVDD0 AVREFP = VDD
Notes 3, 4
V
10-bit resolution
EVDD0 AVREFP = VDD
2.4 V AVREFP 5.5
0.35
3.5
2.0
%FSR
LSB
LSB
V
Notes 3, 4
V
Integral linearity errorNote 1 ILE
10-bit resolution
2.4 V AVREFP 5.5
Notes 3, 4
EVDD0 AVREFP = VDD
V
Differential linearity error DLE
Note 1
10-bit resolution
2.4 V AVREFP 5.5
Notes 3, 4
EVDD0 AVREFP = VDD
V
Analog input voltage
VAIN
ANI16 to ANI26
0
AVREFP
and
EVDD0
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. When AVREFP < VDD, the MAX. values are as follows.
Overall error: Add 1.0 LSB to the MAX. value when AVREFP = VDD
.
Zero-scale error/Full-scale error: Add 0.05%FSR to the MAX. value when AVREFP = VDD
.
Integral linearity error/ Differential linearity error: Add 0.5 LSB to the MAX. value when AVREFP = VDD
4. When AVREFP < EVDD0 VDD, the MAX. values are as follows.
.
.
Overall error: Add 4.0 LSB to the MAX. value when AVREFP = VDD
Zero-scale error/Full-scale error: Add 0.20%FSR to the MAX. value when AVREFP = VDD
Integral linearity error/ Differential linearity error: Add 2.0 LSB to the MAX. value when AVREFP = VDD
.
.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(3) When reference voltage (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage () = VSS (ADREFM =
0), target pin : ANI0 to ANI14, ANI16 to ANI26, internal reference voltage, and temperature sensor output
voltage
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =
VDD, Reference voltage () = VSS)
Parameter
Resolution
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Overall errorNote 1
AINL
10-bit resolution
10-bit resolution
2.4 V VDD 5.5 V
3.6 V VDD 5.5 V
1.2
7.0
39
LSB
s
Conversion time
tCONV
2.125
Target pin: ANI0 to ANI14,
ANI16 to ANI26
2.7 V VDD 5.5 V 3.1875
39
s
2.4 V VDD 5.5 V
3.6 V VDD 5.5 V
17
39
s
10-bit resolution
2.375
39
s
Target pin: Internal reference
voltage, and temperature
sensor output voltage (HS
(high-speed main) mode)
2.7 V VDD 5.5 V 3.5625
39
s
2.4 V VDD 5.5 V
17
39
s
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
EZS
EFS
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
0.60
0.60
4.0
%FSR
%FSR
LSB
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
Integral linearity errorNote 1 ILE
Differential linearity error DLE
Note 1
2.0
LSB
Analog input voltage
VAIN
ANI0 to ANI14
0
0
VDD
V
V
V
ANI16 to ANI26
EVDD0
Note 3
Internal reference voltage output
VBGR
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
Note 3
Temperature sensor output voltage
VTMPS25
V
(2.4 V VDD 5.5 V, HS (high-speed main) mode)
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
(4) When reference voltage (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage
() = AVREFM/ANI1 (ADREFM = 1), target pin : ANI0, ANI2 to ANI14, ANI16 to ANI26
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V, Reference voltage (+) =
VBGR Note 3, Reference voltage () = AVREFM Note 4 = 0 V, HS (high-speed main) mode)
Parameter
Symbol
RES
tCONV
EZS
Conditions
MIN.
TYP.
8
MAX.
Unit
bit
Resolution
Conversion time
8-bit resolution
8-bit resolution
8-bit resolution
8-bit resolution
2.4 V VDD 5.5 V
17
39
s
Zero-scale errorNotes 1, 2
Integral linearity errorNote 1
Differential linearity errorNote 1
Analog input voltage
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
2.4 V VDD 5.5 V
0.60
2.0
1.0
%FSR
LSB
LSB
V
ILE
DLE
VAIN
Note 3
0
VBGR
Notes 1. Excludes quantization error (1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. Refer to 3.6.2 Temperature sensor/internal reference voltage characteristics.
4. When reference voltage () = VSS, the MAX. values are as follows.
Zero-scale error: Add 0.35%FSR to the MAX. value when reference voltage () = AVREFM.
Integral linearity error: Add 0.5 LSB to the MAX. value when reference voltage () = AVREFM.
Differential linearity error: Add 0.2 LSB to the MAX. value when reference voltage () = AVREFM.
3.6.2 Temperature sensor/internal reference voltage characteristics
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode)
Parameter
Symbol
Conditions
MIN.
TYP.
1.05
1.45
3.6
MAX.
1.5
Unit
V
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25C
Internal reference voltage
Temperature coefficient
VBGR
Setting ADS register = 81H
1.38
V
FVTMPS
Temperature sensor that depends on the
temperature
mV/C
Operation stabilization wait time
tAMP
5
s
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.6.3 POR circuit characteristics
(TA = 40 to +105C, VSS = 0 V)
Parameter
Symbol
VPOR
Conditions
Power supply rise time
Power supply fall time
MIN.
1.45
1.44
300
TYP.
1.51
1.50
MAX.
1.57
1.56
Unit
V
Detection voltage
VPDR
V
Minimum pulse width
TPW
s
Note Minimum time required for a POR reset when VDD exceeds below VPDR. This is also the minimum time
required for a POR reset from when VDD exceeds below 0.7 V to when VDD exceeds VPOR while STOP mode is
entered or the main system clock is stopped through setting bit 0 (HIOSTOP) and bit 7 (MSTOP) in the clock
operation status control register (CSC).
TPW
Supply voltage (VDD
)
V
POR
VPDR or 0.7 V
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and Interrupt Mode
(TA = 40 to +105C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
MIN.
3.90
TYP.
4.06
3.98
3.75
3.67
3.13
3.06
3.02
2.96
2.92
2.86
2.81
2.75
2.71
2.65
2.61
2.55
MAX.
4.22
4.13
3.90
3.81
3.25
3.18
3.14
3.07
3.03
2.97
2.92
2.86
2.81
2.75
2.71
2.65
Unit
V
Detection
voltage
Supply voltage level
VLVD0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
s
s
3.83
3.60
3.53
3.01
2.94
2.90
2.85
2.81
2.75
2.70
2.64
2.61
2.55
2.51
2.45
300
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
tLW
Minimum pulse width
Detection delay time
300
LVD Detection Voltage of Interrupt & Reset Mode
(TA = 40 to +105C, VPDR VDD 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
2.64
2.81
TYP.
2.75
2.92
MAX.
2.86
3.03
Unit
V
Interrupt and reset VLVDD0
VPOC2, VPOC1, VPOC0 = 0, 1, 1, falling reset voltage
mode
V
VLVDD1
LVIS1, LVIS0 = 1, 0 Rising release reset
voltage
V
V
Falling interrupt voltage
2.75
2.90
2.86
3.02
2.97
3.14
VLVDD2
LVIS1, LVIS0 = 0, 1 Rising release reset
voltage
V
V
Falling interrupt voltage
2.85
3.90
2.96
4.06
3.07
4.22
VLVDD3
LVIS1, LVIS0 = 0, 0 Rising release reset
voltage
V
Falling interrupt voltage
3.83
3.98
4.13
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.6.5 Power supply voltage rising slope characteristics
(TA = 40 to +105C, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
54
Unit
Power supply voltage rising slope
SVDD
V/ms
Caution Make sure to keep the internal reset state by the LVD circuit or an external reset until VDD
reaches the operating voltage range shown in 3.4 AC Characteristics.
3.7 RAM Data Retention Characteristics
(TA = 40 to +105°C, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
VDDDR
1.44Note
Note This depends on the POR detection voltage. For a falling voltage, data in RAM are retained until the voltage
reaches the level that triggers a POR reset but not once it reaches the level at which a POR reset is
generated.
Operation mode
STOP mode
RAM data retention
VDD
VDDDR
STOP instruction execution
Standby release signal
(interrupt request)
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.8 Flash Memory Programming Characteristics
(TA = 40 to +105C, 2.4 V VDD 5.5 V, VSS = 0 V)
Parameter
CPU/peripheral hardware clock
frequency
Symbol
Conditions
2.4 V VDD 5.5 V
MIN.
1
TYP.
MAX.
32
Unit
fCLK
MHz
Number of code flash rewrites
Notes 1,2,3
Cerwr
Retained for 20 years
TA = 85C Note 4
1,000
Times
Number of data flash rewrites
Notes 1,2,3
Retained for 1 years
TA = 25C
1,000,000
Retained for 5 years
TA = 85C Note 4
100,000
10,000
Retained for 20 years
TA = 85C Note 4
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.The retaining years are until next rewrite
after the rewrite.
2. When using flash memory programmer and Renesas Electronics self programming library.
3. These are the characteristics of the flash memory and the results obtained from reliability testing by
Renesas Electronics Corporation.
4. This temperature is the average value at which data are retained.
3.9 Dedicated Flash Memory Programmer Communication (UART)
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Transfer rate
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
During serial programming
115,200
1,000,000 bps
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3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105C)
3.10 Timing of Entry to Flash Memory Programming Modes
(TA = 40 to +105C, 2.4 V EVDD0 = EVDD1 VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
100
Unit
ms
Time to complete the
communication for the initial
setting after the external reset is
released
tSUINIT
POR and LVD reset must be released before
the external reset is released.
Time to release the external reset tSU
after the TOOL0 pin is set to the
low level
POR and LVD reset must be released before
the external reset is released.
10
1
s
Time to hold the TOOL0 pin at the tHD
low level after the external reset is
released
POR and LVD reset must be released before
the external reset is released.
ms
(excluding the processing time of
the firmware to control the flash
memory)
<1>
<4>
<2>
<3>
RESET
TOOL0
723 μs + tHD
processing
time
1-byte data for setting mode
tSU
tSUINIT
<1> The low level is input to the TOOL0 pin.
<2> The external reset is released (POR and LVD reset must be released before the
external reset is released.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark tSUINIT: Communication for the initial setting must be completed within 100 ms after the external reset is
released during this period.
t
SU
:
Time to release the external reset after the TOOL0 pin is set to the low level
Time to hold the TOOL0 pin at the low level after the external reset is released (excluding the
processing time of the firmware to control the flash memory)
tHD:
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4. PACKAGE DRAWINGS
4. PACKAGE DRAWINGS
4.1 20-pin Products
R5F1006AASP, R5F1006CASP, R5F1006DASP, R5F1006EASP
R5F1016AASP, R5F1016CASP, R5F1016DASP, R5F1016EASP
R5F1006ADSP, R5F1006CDSP, R5F1006DDSP, R5F1006EDSP
R5F1016ADSP, R5F1016CDSP, R5F1016DDSP, R5F1016EDSP
R5F1006AGSP, R5F1006CGSP, R5F1006DGSP, R5F1006EGSP
JEITA Package Code
P-LSSOP20-0300-0.65
RENESAS Code
PLSP0020JC-A
Previous Code
MASS (TYP.) [g]
0.12
S20MC-65-5A4-3
20
11
detail of lead end
F
G
T
P
L
U
E
1
10
A
H
I
J
S
N
S
ITEM MILLIMETERS
K
C
A
B
C
6.65 0.15
0.475 MAX.
0.65 (T.P.)
B
M
D
M
+0.08
0.24
D
−0.07
NOTE
E
F
G
H
I
0.1 0.05
1.3 0.1
1.2
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6 0.15
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 178 of 196
RL78/G13
4.2 24-pin Products
4. PACKAGE DRAWINGS
R5F1007AANA, R5F1007CANA, R5F1007DANA, R5F1007EANA
R5F1017AANA, R5F1017CANA, R5F1017DANA, R5F1017EANA
R5F1007ADNA, R5F1007CDNA, R5F1007DDNA, R5F1007EDNA
R5F1017ADNA, R5F1017CDNA, R5F1017DDNA, R5F1017EDNA
R5F1007AGNA, R5F1007CGNA, R5F1007DGNA, R5F1007EGNA
JEITA Package code
RENESAS code
Previous code
MASS(TYP.)[g]
P-HWQFN24-4x4-0.50
PWQN0024KE-A
P24K8-50-CAB-3
0.04
D
18
13
DETAIL OF A PART
12
19
E
A
24
7
A1
c2
6
1
INDEX AREA
A
S
y
S
Dimension in Millimeters
Referance
Symbol
Nom
4.00
4.00
Max
4.05
4.05
0.80
Min
3.95
3.95
D
E
D2
A
Lp
A
EXPOSED DIE PAD
1
6
A1
b
0.00
0.30
0.18
0.25
0.50
0.40
7
24
e
0.30
0.50
0.05
0.05
Lp
x
B
E2
y
ZE
ZD
ZE
c2
0.75
0.75
0.20
2.50
2.50
19
12
0.15
0.25
13
18
D2
E2
e
ZD
M
b
x
S
A B
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 179 of 196
RL78/G13
4.3 25-pin Products
4. PACKAGE DRAWINGS
R5F1008AALA, R5F1008CALA, R5F1008DALA, R5F1008EALA
R5F1018AALA, R5F1018CALA, R5F1018DALA, R5F1018EALA
R5F1008AGLA, R5F1008CGLA, R5F1008DGLA, R5F1008EGLA
JEITA Package Code
P-WFLGA25-3x3-0.50
RENESAS Code
PWLG0025KA-A
Previous Code
MASS (TYP.) [g]
P25FC-50-2N2-2
0.01
M
21x
b
x
S A B
A
ZD
e
ZE
D
w S A
5
4
3
2
1
B
C
2.27
E
INDEX MARK
ED
CB
A
w
S B
INDEX MARK
D
2.27
y1
S
A
S
(UNIT:mm)
ITEM DIMENSIONS
y
S
D
E
3.00 0.10
3.00 0.10
0.20
DETAIL OF C PART
DETAIL OF D PART
w
e
0.50
R0.17 0.05
R0.12 0.05
0.50 0.05
0.365 0.05
0.43 0.05
0.33 0.05
A
0.69 0.07
0.24 0.05
0.05
b
x
y
0.08
y1
ZD
ZE
0.20
0.50
0.50
b
(LAND PAD)
0.34 0.05
(APERTURE OF
SOLDER RESIST)
0.365 0.05
0.50 0.05
0.33 0.05
0.43 0.05
R0.165 0.05
R0.215 0.05
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 180 of 196
RL78/G13
4.4 30-pin Products
4. PACKAGE DRAWINGS
R5F100AAASP, R5F100ACASP, R5F100ADASP, R5F100AEASP, R5F100AFASP, R5F100AGASP
R5F101AAASP, R5F101ACASP, R5F101ADASP, R5F101AEASP, R5F101AFASP, R5F101AGASP
R5F100AADSP, R5F100ACDSP, R5F100ADDSP, R5F100AEDSP, R5F100AFDSP, R5F100AGDSP
R5F101AADSP, R5F101ACDSP, R5F101ADDSP, R5F101AEDSP, R5F101AFDSP, R5F101AGDSP
R5F100AAGSP, R5F100ACGSP, R5F100ADGSP,R5F100AEGSP, R5F100AFGSP, R5F100AGGSP
JEITA Package Code
P-LSSOP30-0300-0.65
RENESAS Code
PLSP0030JB-B
Previous Code
MASS (TYP.) [g]
0.18
S30MC-65-5A4-3
30
16
detail of lead end
F
G
T
P
L
1
15
U
E
A
H
I
J
S
B
C
N
S
ITEM MILLIMETERS
A
B
C
9.85 0.15
0.45 MAX.
0.65 (T.P.)
M
M
D
K
+0.08
0.24
D
−0.07
NOTE
E
F
G
H
I
0.1 0.05
1.3 0.1
1.2
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
8.1 0.2
6.1 0.2
1.0 0.2
0.17 0.03
0.5
J
K
L
M
N
0.13
0.10
+5°
3°
P
−3°
T
0.25
U
0.6 0.15
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 181 of 196
RL78/G13
4.5 32-pin Products
4. PACKAGE DRAWINGS
R5F100BAANA, R5F100BCANA, R5F100BDANA, R5F100BEANA, R5F100BFANA, R5F100BGANA
R5F101BAANA, R5F101BCANA, R5F101BDANA, R5F101BEANA, R5F101BFANA, R5F101BGANA
R5F100BADNA, R5F100BCDNA, R5F100BDDNA, R5F100BEDNA, R5F100BFDNA, R5F100BGDNA
R5F101BADNA, R5F101BCDNA, R5F101BDDNA, R5F101BEDNA, R5F101BFDNA, R5F101BGDNA
R5F100BAGNA, R5F100BCGNA, R5F100BDGNA,R5F100BEGNA, R5F100BFGNA, R5F100BGGNA
JEITA Package code
P-HWQFN32-5x5-0.50
RENESAS code
PWQN0032KB-A
Previous code
MASS (TYP.)[g]
0.06
P32K8-50-3B4-5
D
17
24
DETAIL OF A PART
16
25
E
A
32
9
A1
C2
8
1
INDEX AREA
A
S
y
S
Dimension in Millimeters
Referance
Symbol
Nom
5.00
5.00
Max
5.05
5.05
0.80
Min
4.95
4.95
D
E
D2
A
Lp
EXPOSED DIE PAD
A
1
8
A1
b
0.00
0.18
0.30
0.25
0.50
0.40
9
32
e
0.30
0.15
0.50
0.05
0.05
Lp
x
B
E2
y
ZE
ZD
ZE
c2
0.75
0.75
0.20
3.50
3.50
16
25
0.25
17
24
D2
E2
ZD
e
M
b
x
S
A B
2013 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 182 of 196
RL78/G13
4.6 36-pin Products
4. PACKAGE DRAWINGS
R5F100CAALA, R5F100CCALA, R5F100CDALA, R5F100CEALA, R5F100CFALA, R5F100CGALA
R5F101CAALA, R5F101CCALA, R5F101CDALA, R5F101CEALA, R5F101CFALA, R5F101CGALA
R5F100CAGLA, R5F100CCGLA, R5F100CDGLA, R5F100CEGLA, R5F100CFGLA, R5F100CGGLA
JEITA Package Code
P-WFLGA36-4x4-0.50
RENESAS Code
PWLG0036KA-A
Previous Code
MASS (TYP.) [g]
0.023
P36FC-50-AA4-2
M
32x
b
x
S A B
A
ZD
e
ZE
D
w
S
A
6
5
4
3
2
1
B
2.90
E
C
F
E
D
C
B
A
D
E
INDEX MARK
w S B
2.90
y1
S
S
A
S
y
DETAIL E
R0.17 0.05
DETAIL C
DETAIL D
R0.17 0.05
(UNIT:mm)
ITEM DIMENSIONS
0.70 0.05
0.70 0.05
0.55 0.05
R0.12 0.05
R0.12 0.05 0.55 0.05
D
E
4.00 0.10
4.00 0.10
0.20
0.75
0.55
0.75
0.55
w
e
0.50
A
0.69 0.07
0.24 0.05
0.05
b
φ
b
x
(LAND PAD)
y
0.08
φ
0.34 0.05
y1
ZD
ZE
0.20
0.55
0.75
0.55
0.75
R0.275 0.05
R0.35 0.05
(APERTURE OF
SOLDER RESIST)
0.75
0.75
0.55 0.05
0.70 0.05
0.55 0.05
0.70 0.05
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 183 of 196
RL78/G13
4.7 40-pin Products
4. PACKAGE DRAWINGS
R5F100EAANA, R5F100ECANA, R5F100EDANA, R5F100EEANA, R5F100EFANA, R5F100EGANA, R5F100EHANA
R5F101EAANA, R5F101ECANA, R5F101EDANA, R5F101EEANA, R5F101EFANA, R5F101EGANA, R5F101EHANA
R5F100EADNA, R5F100ECDNA, R5F100EDDNA, R5F100EEDNA, R5F100EFDNA, R5F100EGDNA,
R5F100EHDNA
R5F101EADNA, R5F101ECDNA, R5F101EDDNA, R5F101EEDNA, R5F101EFDNA, R5F101EGDNA,
R5F101EHDNA
R5F100EAGNA, R5F100ECGNA, R5F100EDGNA, R5F100EEGNA, R5F100EFGNA, R5F100EGGNA,
R5F100EHGNA
JEITA Package code
RENESAS code
Previous code
MASS (TYP.) [g]
P-HWQFN40-6x6-0.50
P40K8-50-4B4-5
0.09
PWQN0040KC-A
D
21
30
20
31
DETAIL OF A PART
E
A
40
11
A1
C2
10
1
INDEX AREA
A
S
y
S
Dimension in Millimeters
Referance
Symbol
Nom
6.00
6.00
Max
6.05
6.05
0.80
Min
5.95
5.95
D
E
D2
A
Lp
EXPOSED DIE PAD
A
1
10
A1
b
0.00
11
0.18
0.30
0.25
0.50
0.40
40
e
0.30
0.50
0.05
0.05
Lp
x
B
E2
y
ZD
ZE
c2
0.75
0.75
0.20
4.50
4.50
ZE
20
31
0.15
0.25
30
21
D2
E2
ZD
e
M
b
x
S
A B
2013 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 184 of 196
RL78/G13
4.8 44-pin Products
4. PACKAGE DRAWINGS
R5F100FAAFP, R5F100FCAFP, R5F100FDAFP, R5F100FEAFP, R5F100FFAFP, R5F100FGAFP,
R5F100FHAFP, R5F100FJAFP, R5F100FKAFP, R5F100FLAFP
R5F101FAAFP, R5F101FCAFP, R5F101FDAFP, R5F101FEAFP, R5F101FFAFP, R5F101FGAFP,
R5F101FHAFP, R5F101FJAFP, R5F101FKAFP, R5F101FLAFP
R5F100FADFP, R5F100FCDFP, R5F100FDDFP, R5F100FEDFP, R5F100FFDFP, R5F100FGDFP,
R5F100FHDFP, R5F100FJDFP, R5F100FKDFP, R5F100FLDFP
R5F101FADFP, R5F101FCDFP, R5F101FDDFP, R5F101FEDFP, R5F101FFDFP, R5F101FGDFP,
R5F101FHDFP, R5F101FJDFP, R5F101FKDFP, R5F101FLDFP
R5F100FAGFP, R5F100FCGFP, R5F100FDGFP, R5F100FEGFP, R5F100FFGFP, R5F100FGGFP,
R5F100FHGFP, R5F100FJGFP
JEITA Package Code
P-LQFP44-10x10-0.80
RENESAS Code
PLQP0044GC-A
Previous Code
MASS (TYP.) [g]
0.36
P44GB-80-UES-2
HD
D
detail of lead end
A3
23
22
33
34
c
θ
L
Lp
E
HE
L1
(UNIT:mm)
ITEM DIMENSIONS
12
11
44
D
E
10.00 0.20
10.00 0.20
12.00 0.20
12.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
1
HD
HE
A
ZE
e
ZD
A1
A2
A3
b
M
b
x
S
A
A2
+0.08
0.37
−0.07
+0.055
c
0.145
−0.045
S
L
0.50
Lp
L1
0.60 0.15
1.00 0.20
y
S
A1
+5°
3°
θ
−3°
e
x
0.80
0.20
0.10
1.00
1.00
NOTE
y
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
ZD
ZE
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 185 of 196
RL78/G13
4.9 48-pin Products
4. PACKAGE DRAWINGS
R5F100GAAFB, R5F100GCAFB, R5F100GDAFB, R5F100GEAFB, R5F100GFAFB, R5F100GGAFB,
R5F100GHAFB, R5F100GJAFB, R5F100GKAFB, R5F100GLAFB
R5F101GAAFB, R5F101GCAFB, R5F101GDAFB, R5F101GEAFB, R5F101GFAFB, R5F101GGAFB,
R5F101GHAFB, R5F101GJAFB, R5F101GKAFB, R5F101GLAFB
R5F100GADFB, R5F100GCDFB, R5F100GDDFB, R5F100GEDFB, R5F100GFDFB, R5F100GGDFB,
R5F100GHDFB, R5F100GJDFB, R5F100GKDFB, R5F100GLDFB
R5F101GADFB, R5F101GCDFB, R5F101GDDFB, R5F101GEDFB, R5F101GFDFB, R5F101GGDFB,
R5F101GHDFB, R5F101GJDFB, R5F101GKDFB, R5F101GLDFB
R5F100GAGFB, R5F100GCGFB, R5F100GDGFB, R5F100GEGFB, R5F100GFGFB, R5F100GGGFB,
R5F100GHGFB, R5F100GJGFB
JEITA Package Code
P-LFQFP48-7x7-0.50
RENESAS Code
PLQP0048KF-A
Previous Code
MASS (TYP.) [g]
0.16
P48GA-50-8EU-1
HD
D
detail of lead end
36
25
24
A3
37
c
θ
L
Lp
E
HE
L1
(UNIT:mm)
13
12
48
ITEM DIMENSIONS
1
D
E
7.00 0.20
7.00 0.20
9.00 0.20
9.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
ZE
HD
HE
A
e
ZD
A1
A2
M
S
b
x
A
A3
b
A2
0.22 0.05
+0.055
c
0.145
0.50
−0.045
L
S
Lp
L1
0.60 0.15
1.00 0.20
+5°
3°
θ
−3°
y
S
A1
e
x
0.50
0.08
0.08
0.75
0.75
y
ZD
ZE
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 186 of 196
RL78/G13
4. PACKAGE DRAWINGS
R5F100GAANA, R5F100GCANA, R5F100GDANA, R5F100GEANA, R5F100GFANA, R5F100GGANA,
R5F100GHANA, R5F100GJANA, R5F100GKANA, R5F100GLANA
R5F101GAANA, R5F101GCANA, R5F101GDANA, R5F101GEANA, R5F101GFANA, R5F101GGANA,
R5F101GHANA, R5F101GJANA, R5F101GKANA, R5F101GLANA
R5F100GADNA, R5F100GCDNA, R5F100GDDNA, R5F100GEDNA, R5F100GFDNA, R5F100GGDNA,
R5F100GHDNA, R5F100GJDNA, R5F100GKDNA, R5F100GLDNA
R5F101GADNA, R5F101GCDNA, R5F101GDDNA, R5F101GEDNA, R5F101GFDNA, R5F101GGDNA,
R5F101GHDNA, R5F101GJDNA, R5F101GKDNA, R5F101GLDNA
R5F100GAGNA, R5F100GCGNA, R5F100GDGNA, R5F100GEGNA, R5F100GFGNA, R5F100GGGNA,
R5F100GHGNA, R5F100GJGNA
JEITA Package code
RENESAS code
Previous code
MASS(TYP.)[g]
0.13
48PJN-A
P48K8-50-5B4-6
P-HWQFN48-7x7-0.50
PWQN0048KB-A
D
25
36
24
37
DETAIL OF
A PART
E
A
A1
c2
13
48
12
1
INDEX AREA
A
S
y
S
Dimension in Millimeters
Referance
Symbol
Nom
7.00
7.00
Max
7.05
7.05
0.80
Min
6.95
6.95
D
E
D2
A
Lp
EXPOSED DIE PAD
A
12
1
A1
b
0.00
13
0.30
0.18
0.25
0.50
0.40
48
e
0.30
0.50
0.05
0.05
Lp
x
B
E2
y
ZD
ZE
c2
0.75
0.75
0.20
5.50
5.50
ZE
37
24
0.15
0.25
36
25
D2
E2
ZD
e
M
S A B
b
x
2013 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 187 of 196
RL78/G13
4.10 52-pin Products
4. PACKAGE DRAWINGS
R5F100JCAFA, R5F100JDAFA, R5F100JEAFA, R5F100JFAFA, R5F100JGAFA, R5F100JHAFA, R5F100JJAFA,
R5F100JKAFA, R5F100JLAFA
R5F101JCAFA, R5F101JDAFA, R5F101JEAFA, R5F101JFAFA, R5F101JGAFA, R5F101JHAFA, R5F101JJAFA,
R5F101JKAFA, R5F101JLAFA
R5F100JCDFA, R5F100JDDFA, R5F100JEDFA, R5F100JFDFA, R5F100JGDFA, R5F100JHDFA, R5F100JJDFA,
R5F100JKDFA, R5F100JLDFA
R5F101JCDFA, R5F101JDDFA, R5F101JEDFA, R5F101JFDFA, R5F101JGDFA, R5F101JHDFA, R5F101JJDFA,
R5F101JKDFA, R5F101JLDFA
R5F100JCGFA, R5F100JDGFA, R5F100JEGFA, R5F100JFGFA, R5F100JGGFA, R5F100JHGFA, R5F100JJGFA
JEITA Package Code
RENESAS Code
Previous Code
MASS (TYP.) [g]
0.3
P-LQFP52-10x10-0.65
PLQP0052JA-A
P52GB-65-GBS-1
HD
2
D
39
27
26
detail of lead end
40
c
1
E
HE
L
14
52
1
13
e
(UNIT:mm)
3
b
ITEM
D
DIMENSIONS
M
x
A
10.00 0.10
10.00 0.10
E
A2
HD
HE
A
12.00 0.20
12.00 0.20
1.70 MAX.
0.10 0.05
1.40
A1
A2
y
A1
b
c
0.32 0.05
0.145 0.055
0.50 0.15
NOTE
L
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
0° to 8°
0.65
e
x
y
0.13
0.10
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 188 of 196
RL78/G13
4.11 64-pin Products
4. PACKAGE DRAWINGS
R5F100LCAFA, R5F100LDAFA, R5F100LEAFA, R5F100LFAFA, R5F100LGAFA, R5F100LHAFA, R5F100LJAFA,
R5F100LKAFA, R5F100LLAFA
R5F101LCAFA, R5F101LDAFA, R5F101LEAFA, R5F101LFAFA, R5F101LGAFA, R5F101LHAFA, R5F101LJAFA,
R5F101LKAFA, R5F101LLAFA
R5F100LCDFA, R5F100LDDFA, R5F100LEDFA, R5F100LFDFA, R5F100LGDFA, R5F100LHDFA, R5F100LJDFA,
R5F100LKDFA, R5F100LLDFA
R5F101LCDFA, R5F101LDDFA, R5F101LEDFA, R5F101LFDFA, R5F101LGDFA, R5F101LHDFA, R5F101LJDFA,
R5F101LKDFA, R5F101LLDFA
R5F100LCGFA, R5F100LDGFA, R5F100LEGFA, R5F100LFGFA, R5F100LGGFA, R5F100LHGFA,
R5F100LJGFA
JEITA Package Code
P-LQFP64-12x12-0.65
RENESAS Code
PLQP0064JA-A
Previous Code
MASS (TYP.) [g]
0.51
P64GK-65-UET-2
HD
D
detail of lead end
48
33
49
32
A3
c
θ
L
Lp
E
HE
L1
(UNIT:mm)
ITEM DIMENSIONS
D
E
12.00 0.20
12.00 0.20
14.00 0.20
14.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
17
e
64
HD
HE
A
1
16
ZE
A1
A2
A3
b
ZD
M
S
b
x
+0.08
0.32
A
−0.07
+0.055
c
0.145
A2
−0.045
L
0.50
Lp
L1
0.60 0.15
1.00 0.20
S
+5°
3°
θ
−3°
y
e
x
A1
0.65
S
0.13
y
0.10
ZD
ZE
1.125
1.125
NOTE
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 189 of 196
RL78/G13
4. PACKAGE DRAWINGS
R5F100LCAFB, R5F100LDAFB, R5F100LEAFB, R5F100LFAFB, R5F100LGAFB, R5F100LHAFB, R5F100LJAFB,
R5F100LKAFB, R5F100LLAFB
R5F101LCAFB, R5F101LDAFB, R5F101LEAFB, R5F101LFAFB, R5F101LGAFB, R5F101LHAFB,
R5F101LJAFB, R5F101LKAFB, R5F101LLAFB
R5F100LCDFB, R5F100LDDFB, R5F100LEDFB, R5F100LFDFB, R5F100LGDFB, R5F100LHDFB, R5F100LJDFB,
R5F100LKDFB, R5F100LLDFB
R5F101LCDFB, R5F101LDDFB, R5F101LEDFB, R5F101LFDFB, R5F101LGDFB, R5F101LHDFB,
R5F101LJDFB, R5F101LKDFB, R5F101LLDFB
R5F100LCGFB, R5F100LDGFB, R5F100LEGFB, R5F100LFGFB, R5F100LGGFB, R5F100LHGFB,
R5F100LJGFB
JEITA Package Code
RENESAS Code
PLQP0064KF-A
Previous Code
MASS (TYP.) [g]
0.35
P-LFQFP64-10x10-0.50
P64GB-50-UEU-2
HD
D
detail of lead end
48
33
A3
49
32
c
θ
L
Lp
E
HE
L1
(UNIT:mm)
ITEM DIMENSIONS
17
64
D
E
10.00 0.20
10.00 0.20
12.00 0.20
12.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
1
16
HD
HE
A
ZE
e
A1
A2
ZD
M
S
b
x
A3
b
A
0.22 0.05
+0.055
0.145
A2
c
−0.045
L
0.50
Lp
L1
0.60 0.15
1.00 0.20
S
+5°
3°
θ
−3°
e
x
0.50
0.08
0.08
1.25
1.25
y
S
A1
y
ZD
ZE
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 190 of 196
RL78/G13
4. PACKAGE DRAWINGS
R5F100LCABG, R5F100LDABG, R5F100LEABG, R5F100LFABG, R5F100LGABG, R5F100LHABG,
R5F100LJABG
R5F101LCABG, R5F101LDABG, R5F101LEABG, R5F101LFABG, R5F101LGABG, R5F101LHABG,
R5F101LJABG
R5F100LCGBG, R5F100LDGBG, R5F100LEGBG, R5F100LFGBG, R5F100LGGBG, R5F100LHGBG,
R5F100LJGBG
JEITA Package Code
P-VFBGA64-4x4-0.40
RENESAS Code
PVBG0064LA-A
Previous Code
MASS (TYP.) [g]
0.03
P64F1-40-AA2-2
w
S
A
ZE
A
ZD
D
8
7
6
5
4
3
2
1
B
E
H G F E D C B A
INDEX MARK
INDEX MARK
w
S B
(UNIT:mm)
ITEM DIMENSIONS
A
D
E
4.00 0.10
4.00 0.10
0.15
A2
y1
S
w
A
0.89 0.10
0.20 0.05
0.69
S
A1
A2
e
0.40
0.25 0.05
0.05
b
y
e
S
A1
x
y
0.08
x
M
b
S A B
y1
ZD
ZE
0.20
0.60
0.60
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 191 of 196
RL78/G13
4.12 80-pin Products
4. PACKAGE DRAWINGS
R5F100MFAFA, R5F100MGAFA, R5F100MHAFA, R5F100MJAFA, R5F100MKAFA, R5F100MLAFA
R5F101MFAFA, R5F101MGAFA, R5F101MHAFA, R5F101MJAFA, R5F101MKAFA, R5F101MLAFA
R5F100MFDFA, R5F100MGDFA, R5F100MHDFA, R5F100MJDFA, R5F100MKDFA, R5F100MLDFA
R5F101MFDFA, R5F101MGDFA, R5F101MHDFA, R5F101MJDFA, R5F101MKDFA, R5F101MLDFA
R5F100MFGFA, R5F100MGGFA, R5F100MHGFA, R5F100MJGFA
JEITA Package Code
P-LQFP80-14x14-0.65
RENESAS Code
PLQP0080JB-E
Previous Code
MASS (TYP.) [g]
0.69
P80GC-65-UBT-2
HD
D
detail of lead end
L1
A3
A
c
60
61
41
40
L
Lp
B
E
HE
Dimension in Millimeters
Referance
Symbol
Nom
14.00
14.00
17.20
17.20
Max
14.20
14.20
17.40
Min
13.80
13.80
17.00
D
E
80
1
21
20
HD
HE
17.00
17.40
1.70
0.20
1.45
A
A1
A2
A3
bp
c
ZE
0.05
1.35
0.125
1.40
0.25
e
ZD
M
bp
x
S
AB
0.26
0.10
0.38
0.20
0.32
0.145
0.80
L
A
Lp
0.886
0.736
1.40
0°
1.036
1.80
8°
A2
L1
1.60
3°
S
e
x
y
0.65
0.13
0.10
y
S
A1
0.825
0.825
ZD
ZE
2012 Renesas ElectronicsCorporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 192 of 196
RL78/G13
4. PACKAGE DRAWINGS
R5F100MFAFB, R5F100MGAFB, R5F100MHAFB, R5F100MJAFB, R5F100MKAFB, R5F100MLAFB
R5F101MFAFB, R5F101MGAFB, R5F101MHAFB, R5F101MJAFB, R5F101MKAFB, R5F101MLAFB
R5F100MFDFB, R5F100MGDFB, R5F100MHDFB, R5F100MJDFB, R5F100MKDFB, R5F100MLDFB
R5F101MFDFB, R5F101MGDFB, R5F101MHDFB, R5F101MJDFB, R5F101MKDFB, R5F101MLDFB
R5F100MFGFB, R5F100MGGFB, R5F100MHGFB, R5F100MJGFB
JEITA Package Code
RENESAS Code
PLQP0080KE-A
Previous Code
MASS (TYP.) [g]
0.53
P-LFQFP80-12x12-0.50
P80GK-50-8EU-2
HD
D
detail of lead end
41
40
60
A3
61
c
θ
L
Lp
E
HE
L1
(UNIT:mm)
ITEM DIMENSIONS
D
E
12.00 0.20
12.00 0.20
14.00 0.20
14.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
HD
HE
A
21
20
80
1
A1
A2
ZE
e
A3
b
ZD
0.22 0.05
M
b
x
S
+0.055
0.145
c
−0.045
L
0.50
A
Lp
L1
0.60 0.15
1.00 0.20
A2
+5°
3°
θ
−3°
S
e
x
0.50
0.08
0.08
1.25
1.25
y
y
S
A1
ZD
ZE
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 193 of 196
RL78/G13
4.13 100-pin Products
4. PACKAGE DRAWINGS
R5F100PFAFB, R5F100PGAFB, R5F100PHAFB, R5F100PJAFB, R5F100PKAFB, R5F100PLAFB
R5F101PFAFB, R5F101PGAFB, R5F101PHAFB, R5F101PJAFB, R5F101PKAFB, R5F101PLAFB
R5F100PFDFB, R5F100PGDFB, R5F100PHDFB, R5F100PJDFB, R5F100PKDFB, R5F100PLDFB
R5F101PFDFB, R5F101PGDFB, R5F101PHDFB, R5F101PJDFB, R5F101PKDFB, R5F101PLDFB
R5F100PFGFB, R5F100PGGFB, R5F100PHGFB, R5F100PJGFB
JEITA Package Code
RENESAS Code
PLQP0100KE-A
Previous Code
MASS (TYP.) [g]
0.69
P-LFQFP100-14x14-0.50
P100GC-50-GBR-1
HD
D
detail of lead end
A
L1
A3
75
76
51
50
c
B
L
E
HE
Lp
(UNIT:mm)
ITEM DIMENSIONS
D
E
14.00 0.20
14.00 0.20
16.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
HD
HE
A
26
25
100
1
A1
A2
A3
b
ZE
e
0.05
0.22
+0.055
M
b
x
S
AB
ZD
c
0.145
0.50
0.045
A
L
A2
Lp
L1
0.60 0.15
1.00 0.20
S
+
5°
3°
3°
e
x
0.50
0.08
0.08
1.00
1.00
y
S
A1
y
ZD
ZE
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 194 of 196
RL78/G13
4. PACKAGE DRAWINGS
R5F100PFAFA, R5F100PGAFA, R5F100PHAFA, R5F100PJAFA, R5F100PKAFA, R5F100PLAFA
R5F101PFAFA, R5F101PGAFA, R5F101PHAFA, R5F101PJAFA, R5F101PKAFA, R5F101PLAFA
R5F100PFDFA, R5F100PGDFA, R5F100PHDFA, R5F100PJDFA, R5F100PKDFA, R5F100PLDFA
R5F101PFDFA, R5F101PGDFA, R5F101PHDFA, R5F101PJDFA, R5F101PKDFA, R5F101PLDFA
R5F100PFGFA, R5F100PGGFA, R5F100PHGFA, R5F100PJGFA
JEITA Package Code
RENESAS Code
PLQP0100JC-A
Previous Code
MASS (TYP.) [g]
0.92
P-LQFP100-14x20-0.65
P100GF-65-GBN-1
HD
D
detail of lead end
A
80
81
51
50
A3
c
B
E
HE
L
Lp
L1
100
1
31
30
(UNIT:mm)
ITEM DIMENSIONS
ZE
e
D
E
20.00 0.20
14.00 0.20
22.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
ZD
M
b
x
S
AB
HD
HE
A
A
A1
A2
A3
A2
S
+ 0.08
0.32
b
c
0.07
+ 0.055
0.145
0.045
y
A1
S
L
0.50
Lp
L1
0.60 0.15
1.00 0.20
+
5
3
3
e
x
0.65
0.13
y
0.10
ZD
ZE
0.575
0.825
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 195 of 196
RL78/G13
4.14 128-pin Products
4. PACKAGE DRAWINGS
R5F100SHAFB, R5F100SJAFB, R5F100SKAFB, R5F100SLAFB
R5F101SHAFB, R5F101SJAFB, R5F101SKAFB, R5F101SLAFB
R5F100SHDFB, R5F100SJDFB, R5F100SKDFB, R5F100SLDFB
R5F101SHDFB, R5F101SJDFB, R5F101SKDFB, R5F101SLDFB
JEITA Package Code
RENESAS Code
PLQP0128KD-A
Previous Code
MASS (TYP.) [g]
0.92
P-LFQFP128-14x20-0.50
P128GF-50-GBP-1
HD
D
detail of lead end
A
A3
c
102
103
65
64
B
θ
E
L
HE
Lp
L1
128
1
39
38
(UNIT:mm)
ITEM DIMENSIONS
D
E
20.00 0.20
14.00 0.20
22.00 0.20
16.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
ZE
e
ZD
HD
HE
A
M
b
x
S
AB
A
A1
A2
A3
b
A2
0.05
0.22
S
+0.055
0.145
c
−0.045
L
0.50
y
S
A1
Lp
L1
0.60 0.15
1.00 0.20
+5°
3°
θ
−3°
e
x
0.50
0.08
0.08
0.75
0.75
y
ZD
ZE
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
Page 196 of 196
Revision History
RL78/G13 Data Sheet
Description
Summary
Rev.
1.00
2.00
Date
Page
Feb 29, 2012
Oct 12, 2012
-
First Edition issued
7
Figure 1-1. Part Number, Memory Size, and Package of RL78/G13: Pin count
corrected.
25
1.4 Pin Identification: Description of pins INTP0 to INTP11 corrected.
40, 42, 44 1.6 Outline of Functions: Descriptions of Subsystem clock, Low-speed on-chip
oscillator, and General-purpose register corrected.
41, 43, 45 1.6 Outline of Functions: Lists of Descriptions changed.
59, 63, 67 Descriptions of Note 8 in a table corrected.
68
69
(4) Common to RL78/G13 all products: Descriptions of Notes corrected.
2.4 AC Characteristics: Symbol of external system clock frequency corrected.
2.6.1 A/D converter characteristics: Notes of overall error corrected.
2.6.2 Temperature sensor characteristics: Parameter name corrected.
96 to 98
100
104
2.8 Flash Memory Programming Characteristics: Incorrect descriptions
corrected.
116
120
1
3.10 52-pin products: Package drawings of 52-pin products corrected.
3.12 80-pin products: Package drawings of 80-pin products corrected.
3.00
Aug 02, 2013
Modification of 1.1 Features
3
4 to 15
16 to 32
33
Modification of 1.2 List of Part Numbers
Modification of Table 1-1. List of Ordering Part Numbers, note, and caution
Modification of package type in 1.3.1 to 1.3.14
Modification of description in 1.4 Pin Identification
Modification of caution, table, and note in 1.6 Outline of Functions
Modification of description in table of Absolute Maximum Ratings (TA = 25C)
48, 50, 52
55
57
Modification of table, note, caution, and remark in 2.2.1 X1, XT1 oscillator
characteristics
57
58
59
63
64
Modification of table in 2.2.2 On-chip oscillator characteristics
Modification of note 3 of table (1/5) in 2.3.1 Pin characteristics
Modification of note 3 of table (2/5) in 2.3.1 Pin characteristics
Modification of table in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin
products
65
66
Modification of table in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin products
Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64-
pin products
68
70
72
74
Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100-
pin products
Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to
100-pin products
Modification of notes 1 and 4 in (3) Flash ROM: 384 to 512 KB of 44- to 100-
pin products
Modification of notes 1, 5, and 6 in (3) Flash ROM: 384 to 512 KB of 44- to
100-pin products
75
77
Modification of (4) Peripheral Functions (Common to all products)
Modification of table in 2.4 AC Characteristics
78, 79
Addition of Minimum Instruction Execution Time during Main System Clock
Operation
80
Modification of figures of AC Timing Test Points and External System Clock
Timing
C - 1
Description
Summary
Rev.
Date
Page
3.00
Aug 02, 2013
81
Modification of figure of AC Timing Test Points
81
Modification of description and note 3 in (1) During communication at same
potential (UART mode)
83
Modification of description in (2) During communication at same potential
(CSI mode)
84
Modification of description in (3) During communication at same potential
(CSI mode)
85
Modification of description in (4) During communication at same potential
(CSI mode) (1/2)
86
Modification of description in (4) During communication at same potential
(CSI mode) (2/2)
88
Modification of table in (5) During communication at same potential
(simplified I2C mode) (1/2)
89
Modification of table and caution in (5) During communication at same
potential (simplified I2C mode) (2/2)
91
Modification of table and notes 1 and 4 in (6) Communication at different
potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
92, 93
94
Modification of table and notes 2 to 7 in (6) Communication at different
potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
Modification of remarks 1 to 4 in (6) Communication at different potential (1.8
V, 2.5 V, 3 V) (UART mode) (2/2)
95
Modification of table in (7) Communication at different potential (2.5 V, 3 V)
(CSI mode) (1/2)
96
Modification of table and caution in (7) Communication at different potential
(2.5 V, 3 V) (CSI mode) (2/2)
97
Modification of table in (8) Communication at different potential (1.8 V, 2.5 V,
3 V) (CSI mode) (1/3)
98
Modification of table, note 1, and caution in (8) Communication at different
potential (1.8 V, 2.5 V, 3 V) (CSI mode) (2/3)
99
Modification of table, note 1, and caution in (8) Communication at different
potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3)
100
102
103
106
107
Modification of remarks 3 and 4 in (8) Communication at different potential
(1.8 V, 2.5 V, 3 V) (CSI mode) (3/3)
Modification of table in (9) Communication at different potential (1.8 V, 2.5 V,
3 V) (CSI mode) (1/2)
Modification of table and caution in (9) Communication at different potential
(1.8 V, 2.5 V, 3 V) (CSI mode) (2/2)
Modification of table in (10) Communication at different potential (1.8 V, 2.5
V, 3 V) (simplified I2C mode) (1/2)
Modification of table, note 1, and caution in (10) Communication at different
potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
Addition of (1) I2C standard mode
Addition of (2) I2C fast mode
Addition of (3) I2C fast mode plus
109
111
112
112
113
Modification of IICA serial transfer timing
Addition of table in 2.6.1 A/D converter characteristics
113
114
115
116
117
Modification of description in 2.6.1 (1)
Modification of notes 3 to 5 in 2.6.1 (1)
Modification of description and notes 2, 4, and 5 in 2.6.1 (2)
Modification of description and notes 3 and 4 in 2.6.1 (3)
Modification of description and notes 3 and 4 in 2.6.1 (4)
C - 2
Description
Summary
Rev.
Date
Page
3.00
Aug 02, 2013
118
Modification of table in 2.6.2 Temperature sensor/internal reference voltage
characteristics
118
119
120
120
122
Modification of table and note in 2.6.3 POR circuit characteristics
Modification of table in 2.6.4 LVD circuit characteristics
Modification of table of LVD Detection Voltage of Interrupt & Reset Mode
Renamed to 2.6.5 Power supply voltage rising slope characteristics
Modification of table, figure, and remark in 2.10 Timing Specs for Switching
Flash Memory Programming Modes
123
124
126
Modification of caution 1 and description
Modification of table and remark 3 in Absolute Maximum Ratings (TA = 25°C)
Modification of table, note, caution, and remark in 3.2.1 X1, XT1 oscillator
characteristics
126
127
128
133
Modification of table in 3.2.2 On-chip oscillator characteristics
Modification of note 3 in 3.3.1 Pin characteristics (1/5)
Modification of note 3 in 3.3.1 Pin characteristics (2/5)
Modification of notes 1 and 4 in (1) Flash ROM: 16 to 64 KB of 20- to 64-pin
products (1/2)
135
137
139
Modification of notes 1, 5, and 6 in (1) Flash ROM: 16 to 64 KB of 20- to 64-
pin products (2/2)
Modification of notes 1 and 4 in (2) Flash ROM: 96 to 256 KB of 30- to 100-
pin products (1/2)
Modification of notes 1, 5, and 6 in (2) Flash ROM: 96 to 256 KB of 30- to
100-pin products (2/2)
140
142
143
Modification of (3) Peripheral Functions (Common to all products)
Modification of table in 3.4 AC Characteristics
Addition of Minimum Instruction Execution Time during Main System Clock
Operation
143
143
145
145
Modification of figure of AC Timing Test Points
Modification of figure of External System Clock Timing
Modification of figure of AC Timing Test Points
Modification of description, note 1, and caution in (1) During communication
at same potential (UART mode)
146
147
149
151
Modification of description in (2) During communication at same potential
(CSI mode)
Modification of description in (3) During communication at same potential
(CSI mode)
Modification of table, note 1, and caution in (4) During communication at
same potential (simplified I2C mode)
Modification of table, note 1, and caution in (5) Communication at different
potential (1.8 V, 2.5 V, 3 V) (UART mode) (1/2)
152 to
154
Modification of table, notes 2 to 6, caution, and remarks 1 to 4 in (5)
Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (2/2)
155
Modification of table in (6) Communication at different potential (1.8 V, 2.5 V,
3 V) (CSI mode) (1/3)
156
Modification of table and caution in (6) Communication at different potential
(1.8 V, 2.5 V, 3 V) (CSI mode) (2/3)
157, 158
160, 161
Modification of table, caution, and remarks 3 and 4 in (6) Communication at
different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (3/3)
Modification of table and caution in (7) Communication at different potential
(1.8 V, 2.5 V, 3 V) (CSI mode)
C - 3
Description
Summary
Rev.
Date
Page
3.00
Aug 02, 2013
163
Modification of table in (8) Communication at different potential (1.8 V, 2.5 V,
3 V) (simplified I2C mode) (1/2)
164, 165
Modification of table, note 1, and caution in (8) Communication at different
potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode) (2/2)
166
166
Modification of table in 3.5.2 Serial interface IICA
Modification of IICA serial transfer timing
167
Addition of table in 3.6.1 A/D converter characteristics
Modification of table and notes 3 and 4 in 3.6.1 (1)
167, 168
169
170
171
172
Modification of description in 3.6.1 (2)
Modification of description and note 3 in 3.6.1 (3)
Modification of description and notes 3 and 4 in 3.6.1 (4)
Modification of table and note in 3.6.3 POR circuit characteristics
Modification of table of LVD Detection Voltage of Interrupt & Reset Mode
173
173
Modification from Supply Voltage Rise Time to 3.6.5 Power supply voltage
rising slope characteristics
174
175
Modification of 3.9 Dedicated Flash Memory Programmer Communication
(UART)
Modification of table, figure, and remark in 3.10 Timing Specs for Switching
Flash Memory Programming Modes
3.10
3.30
Nov 15, 2013
Mar 31, 2016
123
125
Caution 4 added.
Note for operating ambient temperature in 3.1 Absolute Maximum Ratings
deleted.
Modification of the position of the index mark in 25-pin plastic WFLGA (3 × 3
mm, 0.50 mm pitch) of 1.3.3 25-pin products
Modification of power supply voltage in 1.6 Outline of Functions [20-pin, 24-
pin, 25-pin, 30-pin, 32-pin, 36-pin products]
Modification of power supply voltage in 1.6 Outline of Functions [40-pin, 44-
pin, 48-pin, 52-pin, 64-pin products]
Modification of power supply voltage in 1.6 Outline of Functions [80-pin, 100-
pin, 128-pin products]
ACK corrected to ACK
ACK corrected to ACK
All trademarks and registered trademarks are the property of their respective owners.
SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United
States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
C - 4
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction.
If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers.
A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or
third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.
5. Renesas Electronics products are classified according to the following two quality grades: "Standard" and "High Quality". The recommended applications for each Renesas Electronics product depends on
the product's quality grade, as indicated below.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic
equipment; and industrial robots etc.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical
implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it
in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses
incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or systems manufactured by you.
8. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
9. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or
regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the
development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
10. It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the
contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics
products.
11. This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Colophon 5.0
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