R5F10RFCAFP [RENESAS]
Integrated LCD controller/driver, True Low Power Platform (as low as 75 μA/MHz, and 0.64 μA for RTC + LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Appli; 集成的LCD控制器/驱动器，真正的低功耗平台（低至75 μA / MHz和0.64 μA的RTC + LVD ） ， 1.6 V至5.5 V工作电压， 8〜 32 KB的闪存， 31 DMIPS在24 MHz ，对于所有LCD基于APPLI
| 型号： | R5F10RFCAFP |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Integrated LCD controller/driver, True Low Power Platform (as low as 75 μA/MHz, and 0.64 μA for RTC + LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Appli |
| 文件： | 总76页 (文件大小：803K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Datasheet
Specifications in this document are tentative and subject to change.
R01DS0157EJ0001
Rev.0.01
RL78/L12
RENESAS MCU
2012.02.20
Integrated LCD controller/driver, True Low Power Platform (as low as 75 µA/MHz, and 0.64 µA for RTC +
LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
1. OUTLINE
1.1 Features
Ultra-Low Power Technology
• 1.6 V to 5.5 V operation from a single supply
• Stop (RAM retained): 0.23 µA, (LVD enabled): 0.31
µA
• Halt (RTC + LVD): 0.64 µA
• Supports snooze
LCD Controller/Driver
• Up to 35 seg x 8 com or 39 seg x 4 com
• Supports capacitor split method, internal voltage
boost method and resistance division method
• Supports waveform types A and B
• Supports LCD contrast adjustment (18 steps)
• Supports LCD blinking
• Operating: 75 µA/MHz
• LCD operating current (Capacitor split method): 0.12
µA
Data Memory Access (DMA) Controller
• Up to 2 fully programmable channels
• Transfer unit: 8- or 16-bit
• LCD operating current (Internal voltage boost
method): 1.0 µA
Multiple Communication Interfaces
• Up to 1 × I2C multi-master
• Up to 2 × CSI/SPI (7-, 8-bit)
• Up to 1 × UART (7-, 8-, 9-bit)
• Up to 1 × LIN
16-bit RL78 CPU Core
• Delivers 31 DMIPS at maximum operating frequency
of 24 MHz
• Instruction Execution: 86% of instructions can be
executed in 1 to 2 clock cycles
• CISC Architecture (Harvard) with 3-stage pipeline
• Multiply Signed & Unsigned: 16 x 16 to 32-bit result in
1 clock cycle
• MAC: 16 x 16 to 32-bit result in 2 clock cycles
• 16-bit barrel shifter for shift & rotate in 1 clock cycle
• 1-wire on-chip debug function
Extended-Function Timers
• Multi-function 16-bit timers: Up to 8 channels
• Real-time clock (RTC): 1 channel (full calendar and
alarm function with watch correction function)
• Interval Timer: 12-bit, 1 channel
• 15 kHz watchdog timer: 1 channel (window function)
Code Flash Memory
• Density: 8 KB to 32 KB
• Block size: 1 KB
• On-chip single voltage flash memory with protection
from block erase/writing
• Self-programming with secure boot swap function
and flash shield window function
Rich Analog
• ADC: Up to 10 channels, 10-bit resolution, 2.1 µs
conversion time
• Supports 1.6 V
• Internal voltage reference (1.45 V)
• On-chip temperature sensor
Safety Features (IEC or UL 60730 compliance)
• Flash memory CRC calculation
• RAM parity error check
• RAM write protection
• SFR write protection
• Illegal memory access detection
• Clock frequency detection
• ADC self-test
Data Flash Memory
• Data flash with background operation
• Data flash size: 2 KB size
• Erase cycles: 1 Million (typ.)
• Erase/programming voltage: 1.8 V to 5.5 V
RAM
• 1 KB and 1.5 KB size options
• Supports operands or instructions
• Back-up retention in all modes
General Purpose I/O
• 5V tolerant, high-current (up to 20 mA per pin)
• Open-Drain, Internal Pull-up support
High-speed On-chip Oscillator
• 24 MHz with +/− 1% accuracy over voltage (1.8 V to
5.5 V) and temperature (−20°C to 85°C) <target>
• Pre-configured settings: 24 MHz, 16 MHz, 12 MHz, 8
MHz, 4 MHz & 1 MHz
Operating Ambient Temperature
• Standard: −40 °C to +85 °C
Package Type and Pin Count
From 7mm x 7mm to 12mm x 12mm
QFP: 32, 44, 48, 52, 64
QFN: 64
Reset and Supply Management
• Power-on reset (POR) monitor/generator
• Low voltage detection (LVD) with 14 setting options
(Interrupt and/or reset function)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 1 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
{ ROM, RAM capacities
Flash
ROM
Data
flash
RAM
RL78/L12
48 pins
32 pins
44 pins
52 pins
64 pins
32 KB
16 KB
8KB
2 KB
2 KB
2 KB
1.5
KBNote
1
R5F10RBC
R5F10RFC
R5F10RGC
R5F10RJC
R5F10RLC
R5F10RBA
R5F10RB8
R5F10RFA
R5F10RF8
R5F10RGA
R5F10RG8
R5F10RJA
R5F10RJ8
R5F10RLA
KBNote
1
−
KBNote
Note
In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data flash
function is used.
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
1.2 Ordering Information
• Flash memory version (lead-free product)
Pin count
32 pins
44 pins
48 pins
Package
Part Number
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
32-pin plastic LQFP (7 × 7)
44-pin plastic LQFP (10 × 10)
48-pin plastic LQFP
(fine pitch) (7 × 7)
52 pins
64 pins
52-pin plastic LQFP (10 × 10)
64-pin plastic WQFN (8 × 8)
64-pin plastic LQFP (fine pitch)
(10 × 10)
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
R5F10RLAANB, R5F10RLCANB
R5F10RLAAFB, R5F10RLCAFB
4-pin plastic LQFP (12 × 12)
R5F10RLAAFA, R5F10RLCAFA
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 2 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3 Pin Configuration (Top View)
1.3.1 32-pin products
• 32-pin plastic LQFP (7 × 7)
24 23 22 21 20 19 18 17
25
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P14/ANI19/SEG32
P30/TI01/TO01/SEG19
16
15
14
13
12
11
10
9
VL4
VL2
VL1
26
27
28
29
30
31
32
P13/ANI18/TI00/SEG31
P12/SO00/TXD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RXD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
1 2 3 4 5 6 7 8
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 3 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3.2 44-pin products
• 44-pin plastic LQFP (10 × 10)
33 32 31 30 29 28 27 26 25 24 23
22
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
34
35
36
37
38
39
40
41
42
43
44
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
21
20
19
18
17
16
15
14
13
12
V
V
V
L4
L2
L1
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/KR0/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/KR1/SEG29/(INTP2)
P10/SCK00/TI07/TO07/KR2/SEG28/(INTP1)
P140/TO00/PCLBUZ0/KR3/SEG27
P141/TI00/PCLBUZ1/SEG26
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
1 2 3 4
5 6 7 8 9 10 11
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 4 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3.3 48-pin products
• 48-pin plastic LQFP (fine pitch) (7 × 7)
36 35 34 33 32 31 30 29 28 27 26 25
24
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
37
38
39
40
41
42
43
44
45
46
47
48
P70/KR0/SEG16
23
22
21
20
19
18
17
16
15
14
13
P32/TI03/TO03/INTP4/KR1/SEG17
P31/INTP3/RTC1HZ/KR2/SEG18
P30/TI01/TO01/KR3/SEG19
P125/VL3
P14/ANI19/SEG32
P13/ANI18/SEG31
VL4
VL2
VL1
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
P10/SCK00/TI07/TO07/SEG28/(INTP1)
P140/TO00/PCLBUZ0/SEG27
P141/TI00/PCLBUZ1/SEG26
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
1 2 3 4
5 6 7 8 9 10 11 12
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 5 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3.4 52-pin products
• 52-pin plastic LQFP (10 × 10)
39 38 37 36 35 34 33 32 31 30 29 28 27
26
25
24
23
22
21
20
19
18
17
16
15
14
40
41
42
43
44
45
46
47
48
49
50
51
52
P71/KR1/SEG15
P21/ANI1/AVREFM
P20/ANI0/AVREFP
P70/KR0/SEG16
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/KR2/SEG18
P30/TI01/TO01/KR3/SEG19
P125/VL3
P145/ANI23/SEG36
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
V
V
V
L4
L2
L1
P14/ANI19/SEG32
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30/(TI02)/(TO02)
P11/SI00/RxD0/TOOLRxD/SEG29/(INTP2)
P10/SCK00/TI07/TO07/SEG28/(INTP1)
P140/TO00/PCLBUZ0/SEG27
P141/TI00/PCLBUZ1/SEG26
P126/CAPL
P127/CAPH
P61/SDAA0/SEG20
P60/SCLA0/SEG21
1
2
3
4
5
6
7
8 9 10 11 12 13
Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 6 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.3.5 64-pin products
• 64-pin plastic WQFN (8 × 8)
exposed die pad
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AVREFM
P20/ANI0/AVREFP
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P74/SEG12
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P73/KR3/SEG13
P130
P72/KR2/SEG14
P147/SEG38
P71/KR1/SEG15
P146/SEG37
P70/KR0/SEG16
P145/ANI23/SEG36
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
V
V
V
L4
L2
L1
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P126/CAPL
P127/CAPH
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
P61/SDAA0/SEG20
P60/SCLA0/SEG21
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD pins and connect the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 7 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
• 64-pin plastic LQFP (fine pitch) (10 × 10)
• 64-pin plastic LQFP (12 × 12)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P21/ANI1/AVREFM
P20/ANI0/AVREFP
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P74/SEG12
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P73/KR3/SEG13
P130
P72/KR2/SEG14
P147/SEG38
P71/KR1/SEG15
P146/SEG37
P70/KR0/SEG16
P145/ANI23/SEG36
P32/TI03/TO03/INTP4/SEG17
P31/INTP3/RTC1HZ/SEG18
P30/TI01/TO01/SEG19
P125/VL3
P144/ANI22/SEG35
P143/ANI21/SEG34
P142/ANI20/SEG33
P14/ANI19/SEG32
V
V
V
L4
L2
L1
P13/ANI18/SEG31
P12/SO00/TxD0/TOOLTxD/SEG30
P11/SI00/RxD0/TOOLRxD/SEG29
P10/SCK00/SEG28
P126/CAPL
P127/CAPH
P140/TO00/PCLBUZ0/SEG27/(INTP6)
P141/TI00/PCLBUZ1/SEG26/(INTP7)
P61/SDAA0/SEG20
P60/SCLA0/SEG21
1
2
3
4
5
6 7 8 9 10 11 12 13 14 15 16
Cautions 1. Make EVSS pin the same potential as VSS pin.
2. Make VDD pin the potential that is higher than EVDD pin.
3. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).
Remarks 1. For pin identification, see 1.4 Pin Identification.
2. When using the microcontroller for an application where the noise generated inside the
microcontroller must be reduced, it is recommended to supply separate powers to the VDD and
EVDD pins and connect the VSS and EVSS pins to separate ground lines.
3. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 8 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.4 Pin Identification
ANI0, ANI1,
P120 to P127:
P130, P137:
Port 12
Port 13
Port 14
ANI16 to ANI23:
AVREFM:
Analog Input
Analog Reference
Voltage Minus
P140 to P147:
PCLBUZ0, PCLBUZ1: Programmable Clock
Output/Buzzer Output
AVREFP:
Analog Reference
Voltage Plus
REGC:
Regulator Capacitance
Reset
CAPH, CAPL:
COM0 to COM7,
COMEXP:
EVDD:
Capacitor for LCD
RESET:
RTC1HZ:
Real-time Clock Correction Clock
(1 Hz) Output
LCD Common Output
Power Supply for Port
Ground for Port
External Clock Input
(Main System Clock)
External Clock Input
(Sub System Clock)
External Interrupt Input
Key Return
RxD0:
Receive Data
EVSS:
SCK00, SCK01:
SCLA0:
Serial Clock Input/Output
Serial Clock Input/Output
Serial Data Input/Output
LCD Segment Output
Serial Data Input
EXCLK:
SDAA0:
EXCLKS:
SEG0 to SEG38:
SI00, SI01:
SO00, SO01:
TI00 to TI07:
TO00 to TO07:
TOOL0:
INTP0 to INTP7:
KR0-KR3:
Serial Data Output
Timer Input
P10 to P17:
P20, P21:
Port 1
Timer Output
Port 2
Data Input/Output for Tool
P30 to P32:
P40 to P43:
P50 to P54:
P60, P61:
Port 3
TOOLRxD, TOOLTxD: Data Input/Output for External Device
Port 4
TxD0:
Transmit Data
Port 5
VDD:
Power Supply
Port 6
VL1 to VL4:
VSS:
LCD Power Supply
P70 to P74:
Port 7
Ground
X1, X2:
XT1, XT2:
Crystal Oscillator (Main System Clock)
Crystal Oscillator (Subsystem Clock)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 9 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.5 Block Diagram
1.5.1 32-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P13
TO00/P140
ch0
PORT 1
PORT 2
PORT 3
PORT 4
8
2
P10 to P17
P20, P21
P30
TI01/TO01/P30
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P12)
INTERVAL
TIMER
2
2
ANI0/P20, ANI1/P21
ch4
ch5
ch6
ch7
P40
ANI18/P13, ANI19/P14
A/D CONVERTER
AVREFP/P20
AVREFM/P21
PORT 6
2
P60, P61
TI07/TO07/P10
WINDOW
WATCHDOG
TIMER
2
2
P126, P127
P121, P122
PORT 12
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 13
PORT 14
P137
P140
REAL-TIME
CLOCK
BUZZER OUTPUT
PCLBUZ0/P140
SERIAL ARRAY
UNIT0 (2ch)
CLOCK OUTPUT
CONTROL
RxD0/P11
TxD0/P12
UART0
RAM
3
KR0/P12 to KR2/P10
KR3/P140
KEY RETURN
SCK00/P10
SI00/P11
CSI00
SO00/P12
POWER ON RESET/
VOLTAGE
SCK01/P15
SI01/P16
SO01/P17
POR/LVD
CONTROL
CSI01
DETECTOR
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
DIRECT MEMORY
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
ACCESS CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
MULTIPLIER&
DIVIDER,
MULITIPLY-
HIGH-SPEED
ON-CHIP
ACCUMULATOR
OSCILLATOR
SEG0, SEG4 to SEG6,
SEG19 to SEG21, 13
SEG27 to SEG32
LCD
CONTROLLER/
DRIVER
VOLTAGE
REGULATOR
REGC
COM0 to COM3, COMEXP
5
VL1, VL2, VL4
CAPH
RAM SPACE
FOR LCD DATA
INTP0/P137
CAPL
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTERRUPT
CONTROL
BCD
ADJUSTMENT
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 10 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.5.2 44-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
PORT 1
PORT 2
PORT 3
PORT 4
8
2
3
P10 to P17
P20, P21
P30 to P32
P40
TI01/TO01/P30
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P12)
INTERVAL
TIMER
TI03/TO03/P32
2
3
2
ANI0/P20, ANI1/P21
ANI17/P120, ANI18/P13,
ANI19/P14
ch4
ch5
ch6
ch7
A/D CONVERTER
ANI20/P142, ANI21/P143
AVREFP/P20
AVREFM/P21
PORT 6
2
P60, P61
TI07/TO07/P10
WINDOW
WATCHDOG
TIMER
4
4
P120, P125 to P127
P121 to P124
PORT 12
PORT 13
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
PORT 14
4
P140 to P143
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
PCLBUZ0/P140,
PCLBUZ1/P141
2
3
SERIAL ARRAY
UNIT0 (2ch)
CLOCK OUTPUT
CONTROL
RxD0/P11
TxD0/P12
UART0
RAM
KR0/P12 to KR2/P10
KR3/P140
KEY RETURN
SCK00/P10
SI00/P11
CSI00
SO00/P12
POWER ON RESET/
VOLTAGE
SCK01/P15
SI01/P16
SO01/P17
POR/LVD
CONTROL
CSI01
DETECTOR
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
DIRECT MEMORY
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
ACCESS CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
MULTIPLIER&
DIVIDER,
MULITIPLY-
HIGH-SPEED
ON-CHIP
XT1/P123
ACCUMULATOR
OSCILLATOR
XT2/EXCLKS/P124
SEG0 to SEG6,
SEG17 to SEG21, 22
SEG25 to SEG34
LCD
CONTROLLER/
DRIVER
VOLTAGE
REGULATOR
REGC
COM0 to COM7, COMEXP
9
VL1 to VL4
CAPH
RAM SPACE
FOR LCD DATA
INTP0/P137
CAPL
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTERRUPT
CONTROL
INTP3/P31,
INTP4/P32
BCD
ADJUSTMENT
2
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 11 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.5.3 48-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
8
2
3
2
P10 to P17
P20, P21
P30 to P32
P40, P41
P50
TI01/TO01/P30
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P12)
INTERVAL
TIMER
TI03/TO03/P32
TI04/TO04/P41
2
4
3
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ch4
ch5
ch6
ch7
A/D CONVERTER
ANI20/P142 to ANI22/P144
AVREFP/P20
AVREFM/P21
2
P60, P61
P70
TI07/TO07/P10
WINDOW
WATCHDOG
TIMER
4
4
P120, P125 to P127
P121 to P124
PORT 12
PORT 13
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
PORT 14
5
2
P140 to P144
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
SERIAL ARRAY
UNIT0 (2ch)
CLOCK OUTPUT
CONTROL
RxD0/P11
TxD0/P12
UART0
RAM
KR0/P70
KEY RETURN
3
KR1/P32 to KR3/P30
SCK00/P10
SI00/P11
CSI00
SO00/P12
POWER ON RESET/
VOLTAGE
SCK01/P15
SI01/P16
SO01/P17
POR/LVD
CONTROL
CSI01
DETECTOR
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
DIRECT MEMORY
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
ACCESS CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
MULTIPLIER&
DIVIDER,
MULITIPLY-
HIGH-SPEED
ON-CHIP
XT1/P123
ACCUMULATOR
OSCILLATOR
XT2/EXCLKS/P124
SEG0 to SEG7,
SEG16 to SEG21, 26
SEG24 to SEG35
LCD
CONTROLLER/
DRIVER
VOLTAGE
REGULATOR
REGC
COM0 to COM7, COMEXP
9
VL1 to VL4
CAPH
RAM SPACE
FOR LCD DATA
INTP0/P137
CAPL
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTERRUPT
CONTROL
INTP3/P31,
INTP4/P32
BCD
ADJUSTMENT
2
INTP5/P50
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 12 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.5.4 52-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
8
2
3
3
2
2
2
P10 to P17
P20, P21
P30 to P32
P40 to P42
P50, P51
P60, P61
P70, P71
TI01/TO01/P30
ch1
ch2
ch3
TI02/TO02/P17
(TI02/TO02/P12)
INTERVAL
TIMER
TI03/TO03/P32
TI04/TO04/P41
TI05/TO05/P42
TI06/TO06/P51
TI07/TO07/P10
2
4
4
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ch4
ch5
ch6
ch7
A/D CONVERTER
ANI20/P142 to ANI23/P145
AVREFP/P20
AVREFM/P21
WINDOW
WATCHDOG
TIMER
4
4
P120, P125 to P127
P121 to P124
PORT 12
PORT 13
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
LOW-SPEED
ON-CHIP
OSCILLATOR
P137
PORT 14
6
2
P140 to P145
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
SERIAL ARRAY
UNIT0 (2ch)
CLOCK OUTPUT
CONTROL
RxD0/P11
TxD0/P12
UART0
RAM
2
2
KR0/P70, KR1/P71
KR2/P31, KR3/P30
KEY RETURN
SCK00/P10
SI00/P11
CSI00
SO00/P12
POWER ON RESET/
VOLTAGE
SCK10/P15
SI10/P16
SO10/P17
POR/LVD
CONTROL
CSI01
DETECTOR
VDD
VSS TOOLRxD/P11,
TOOLTxD/P12
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
DIRECT MEMORY
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
ACCESS CONTROL
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
MULTIPLIER&
DIVIDER,
MULITIPLY-
HIGH-SPEED
ON-CHIP
XT1/P123
ACCUMULATOR
OSCILLATOR
XT2/EXCLKS/P124
SEG0 to SEG8,
SEG15 to SEG21, 30
SEG23 to SEG36
LCD
CONTROLLER/
DRIVER
VOLTAGE
REGULATOR
REGC
COM0 to COM7, COMEXP
9
VL1 to VL4
CAPH
RAM SPACE
FOR LCD DATA
INTP0/P137
CAPL
INTP1/P15(INTP1/P10),
INTP2/P16(INTP2/P11)
2
INTERRUPT
CONTROL
INTP3/P31,
INTP4/P32
BCD
ADJUSTMENT
2
INTP5/P50
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 13 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.5.5 64-pin products
TIMER ARRAY
UNIT0 (8ch)
TI00/P141
TO00/P140
ch0
PORT 1
PORT 2
PORT 3
PORT 4
PORT 5
PORT 6
PORT 7
8
P10 to P17
P20, P21
TI01/TO01/P30
ch1
ch2
ch3
2
3
4
5
2
5
TI02/TO02/P17
(TI02/TO02/P54)
INTERVAL
TIMER
P30 to P32
P40 to P43
P50 to P54
P60, P61
TI03/TO03/P32
TI04/TO04/P41
TI05/TO05/P42
TI06/TO06/P51
TI07/TO07/P53
2
4
4
ANI0/P20, ANI1/P21
ANI16/P41, ANI17/P120,
ANI18/P13, ANI19/P14
ch4
ch5
ch6
ch7
A/D CONVERTER
ANI20/P142 to ANI23/P145
AVREFP/P20
AVREFM/P21
P70 to P74
WINDOW
WATCHDOG
TIMER
4
4
P120, P125 to P127
P121 to P124
PORT 12
PORT 13
CODE FLASH MEMORY
DATA FLASH MEMORY
RL78
CPU
CORE
P130
P137
LOW-SPEED
ON-CHIP
OSCILLATOR
PORT 14
8
2
P140 to P147
REAL-TIME
CLOCK
RTC1HZ/P31
BUZZER OUTPUT
PCLBUZ0/P140
(PCLBUZ0/P50),
PCLBUZ1/P141
SERIAL ARRAY
UNIT0 (2ch)
CLOCK OUTPUT
CONTROL
RxD0/P11
TxD0/P12
UART0
RAM
KR0/P70 to
KR3/P73
4
KEY RETURN
SCK00/P10
SI00/P11
CSI00
SO00/P12
POWER ON RESET/
VOLTAGE
SCK01/P15
SI01/P16
SO01/P17
POR/LVD
CONTROL
CSI01
DETECTOR
VDD,
V
SS,
TOOLRxD/P11,
EVDD EVSS TOOLTxD/P12
RESET CONTROL
ON-CHIP DEBUG
TOOL0/P40
DIRECT MEMORY
ACCESS CONTROL
SDAA0/P61
SCLA0/P60
SERIAL
INTERFACE IICA0
SYSTEM
CONTROL
RESET
X1/P121
X2/EXCLK/P122
MULTIPLIER&
DIVIDER,
MULITIPLY-
HIGH-SPEED
ON-CHIP
XT1/P123
ACCUMULATOR
OSCILLATOR
XT2/EXCLKS/P124
LCD
CONTROLLER/
DRIVER
VOLTAGE
REGULATOR
SEG0 to SEG38 39
REGC
COM0 to COM7, COMEXP
9
V
L1 to VL4
CAPH
CAPL
RAM SPACE
FOR LCD DATA
INTP0/P137
INTP1/P15(INTP1/P53),
INTP2/P16(INTP2/P54)
2
INTERRUPT
CONTROL
INTP3/P31,
INTP4/P32
BCD
ADJUSTMENT
2
INTP5/P50
INTP6/P52(INTP6/P140)
INTP7/P43(INTP7/P141)
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O
redirection register (PIOR)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 14 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
1.6 Outline of Functions
Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR)
is set to 00H.
(1/2)
Item
32-pin
R5F10RBx
8 to 32
2
44-pin
R5F10RFx
8 to 32
2
48-pin
R5F10RGx
8 to 32
2
52-pin
R5F10RJx
8 to 32
2
64-pin
R5F10RLx
16, 32
Code flash memory (KB)
Data flash memory (KB)
RAM (KB)
2
1, 1.5Note 1
1, 1.5Note 1
1, 1.5Note 1
1, 1.5Note 1
1, 1.5Note 1
Memory space
1 MB
Main system High-speed system
X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD =
1.6 to 1.8 V
clock
clock
High-speed on-chip
oscillator clock
High-speed operation: 1 to 24 MHz (VDD = 2.7 to 5.5 V), High-speed operation: 1
to 16 MHz (VDD = 2.4 to 5.5 V), Low-speed operation: 1 to 8 MHz (VDD = 1.8 to 5.5
V), Low-voltage operation: 1 to 4 MHz (VDD = 1.6 to 5.5 V)
Subsystem clock
−
XT1 (crystal) oscillation , external subsystem clock input (EXCLKS)
32.768 kHz (TYP.): VDD = 1.6 to 5.5 V
Low-speed on-chip oscillator clock
Internal oscillation
15 kHz (TYP.): VDD = 1.6 to 5.5 V
General-purpose register
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
Minimum instruction execution time 0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation)
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)
Instruction set
•
•
•
•
Data transfer (8/16 bits)
Adder and subtractor/logical operation (8/16 bits)
Multiplication (8 bits × 8 bits)
Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean
operation), etc.
I/O port
Total
20
15
3
29
22
5
33
26
5
37
30
5
47
39
5
CMOS I/O
CMOS input
CMOS output
−
−
−
−
1
N-ch open-drain I/O
(6 V tolerance)
2
2
2
2
2
Timer
16-bit timer
8 channels
8 channels (with 1 channel remote control output function)
Watchdog timer
Real-time clock (RTC)
Interval timer (IT)
Timer output
1 channel
1 channel
1 channel
4 channels
5 channels
6 channels
8 channels (PWM outputs: 7 Note 2
)
(PWM outputs: (PWM outputs: (PWM outputs:
3 Note 2 4Note 2 5Note 2
)
)
)
RTC output
−
1
•
1 Hz (subsystem clock: fSUB = 32.768 kHz or )
Notes 1. In the case of the 1 KB, and 1.5 KB, this is 630 bytes when the self-programming function and data
flash function is used.
2. The number of outputs varies, depending on the setting.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 15 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
1. OUTLINE
(2/2)
Item
32-pin
44-pin
48-pin
52-pin
64-pin
R5F10RLx
R5F10RBx
R5F10RFx
R5F10RGx
R5F10RJx
Clock output/buzzer output
1
2
• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz
(Main system clock: fMAIN = 20 MHz operation)
• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz,
32.768 kHz
(Subsystem clock: fSUB = 32.768 kHz operation)
8/10-bit resolution A/D converter
Serial interface
4 channels
CSI: 2 channel/UART (LIN-bus supported): 1 channel
1 channel 1 channel 1 channel 1 channel
7 channels
9 channels
10 channels
10 channels
•
I2C bus
1 channel
LCD controller/driver
Internal voltage boosting method, capacitor split method, and external resistance
division
method are switchable.
22 (18) Note 1
26 (22) Note 1
30 (26) Note 1
39 (35) Note 1
Segment signal output
Common signal output
13
4
4 (8) Note 1
Multiplier and
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
divider/multiply-accumulator
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
DMA controller
2 channels
Vectored interrupt Internal
23
4
23
6
23
7
23
7
23
9
sources
External
Key interrupt
Reset
4
•
•
•
•
•
•
•
Reset by RESET pin
Internal reset by watchdog timer
Internal reset by power-on-reset
Internal reset by voltage detector
Internal reset by illegal instruction execution Note 2
Internal reset by RAM parity error
Internal reset by illegal-memory access
Power-on-reset circuit
• Power-on-reset:
1.51 ±0.03 V
• Power-down-reset: 1.50 ±0.03 V
1.63 V to 4.06 V (14 stages)
Provided
Voltage detector
On-chip debug function
Power supply voltage
Operating ambient temperature
VDD = 1.6 to 5.5 V
TA = −40 to +85 °C
Notes 1. The values in parentheses are the number of signal outputs when 8 com is used.
2. The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or
on-chip debug emulator.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 16 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
2.
ELECTRICAL SPECIFICATIONS (TARGET)
Cautions 1. These specifications show target values, which may change after device evaluation.
2. The RL78/L12 have an on-chip debug function, which is provided for development and
evaluation. Do not use the on-chip debug function in products designated for mass
production, because the guaranteed number of rewritable times of the flash memory may be
exceeded when this function is used, and product reliability therefore cannot be guaranteed.
Renesas Electronics is not liable for problems occurring when the on-chip debug function is
used.
3. The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 17 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C) (1/3)
Parameter
Symbols
Conditions
Ratings
Unit
V
Supply voltage
VDD
VDD = EVDD
VDD = EVDD
−0.5 to +6.5
−0.5 to +6.5
−0.5 to +0.3
−0.5 to +0.3
EVDD
VSS
V
V
EVSS
V
REGC pin input voltage VIREGC
REGC
−0.3 to +2.8
and −0.3 to VDD +0.3Note 1
V
Input voltage
VI1
P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127,
−0.3 to EVDD +0.3
and −0.3 to VDD +0.3Note 2
V
P140 to P147
VI2
P60, P61 (N-ch open-drain)
P20, P21, P121 to P124, P137, EXCLK,
EXCLKS, RESET
−0.3 to +6.5
−0.3 to VDD +0.3Note 2
V
V
VI3
Output voltage
VO1
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P60, P61, P70 to P74, P120,
P125 to P127, P130, P140 to P147
P20, P21
−0.3 to EVDD +0.3
V
and −0.3 to VDD +0.3Note 2
VO2
−0.3 to VDD +0.3
V
V
Analog input voltage
VAI1
ANI16 to ANI23
−0.3 to EVDD +0.3
and −0.3 to AVREFP +0.3Note 2
VAI2
ANI0, ANI1
−0.3 to VDD +0.3
and −0.3 to AVREFP +0.3Note 2
V
Notes 1. Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). This value regulates the
absolute maximum rating of the REGC pin. Do not use this pin with voltage applied to it.
2. Must be 6.5 V or lower.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 18 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
Absolute Maximum Ratings (TA = 25°C) (2/3)
Parameter
LCD voltage
Symbols
Conditions
Ratings
Unit
V
VLI1
VL1 input voltageNote 1
VL2 input voltageNote 1
VL3 input voltageNote 1
VL4 input voltageNote 1
−0.3 to +VLI2
Note 2
VLI2
VLI1 to VLI3
V
VLI3
VLI2 to VLI4
VLI3Note 3 to +6.5
−0.3 to +6.5
−0.3 to +VLO2
V
VLI4
V
VLI5
CAPL, CAPH input voltageNote 1
V
VLO1
VLO2
VLO3
VLO4
VLO5
VLO6
VL1 output voltage
V
Note 4
VL2 output voltage
VLO1 to VLO3
V
VL3 output voltage
VLO2 to VLO4
VLO3Note 5 to +6.5
−0.3 to +6.5
V
VL4 output voltage
V
CAPL, CAPH output voltage
V
COM0 to COM7, External
SEG0 to SEG38, resistance
When other than
a memory-type
−0.3 to VDD +0.3Note 6
V
COMEXP
division method liquid crystal
output voltage
waveform is
used
When a
−0.3 to VLI4 +0.3Note 6
V
memory-type
liquid crystal
waveform is
used
Capacitor split method
Internal voltage boosting method
−0.3 to VDD +0.3Note 6
−0.3 to VLI4 +0.3Note 6
V
V
Notes 1. This value only indicates the absolute maximum ratings when applying voltage to the VL1, VL2,
VL3, and VL4 pins; it does not mean that applying voltage to these pins is recommended.
When using the internal voltage boosting method or capacitance split method, connect these
pins to VSS via a capacitor (0.47 μ F ± 30%) and connect a capacitor (0.47 μ F ± 30%)
between the CAPL and CAPH pins.
2. This is VLI4 in 32-pin products or when the 1/3 bias method is used.
3. This is VLI2 in 32-pin products or when the 1/3 bias method is used. It is VLI1 when the 1/2 bias
method is used. It is -0.3 in static mode.
4. This is VLO4 in 32-pin products or when the 1/3 bias method is used.
5. This is VLO2 in 32-pin products or when the 1/3 bias method is used. It is VLO1 when the 1/2 bias
method is used. It is -0.3 in static mode.
6. Must be 6.5 V or lower.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 19 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
Absolute Maximum Ratings (TA = 25°C) (3/3)
Parameter
Symbols
Conditions
Ratings
Unit
mA
Output current, high
IOH1
Per pin
P10 to P17, P30 to P32, P40 to
P43, P50 to P54, P70 to P74,
P120, P125 to P127, P130, P140
to P147
−40
Total of all pins
P10 to P14, P40 to P43, P120,
P130, P140 to P147
−70
mA
mA
−170 mA
P15 to P17, P30 to P32, P50 to
P54, P70 to P74, P125-P127
−100
IOH2
Per pin
P20, P21
−0.5
−1
mA
mA
mA
Total of all pins
Per pin
Output current, low
IOL1
P10 to P17, P30 to P32, P40 to
P43, P50 to P54, P60, P61, P70
to P74, P120, P125 to P127,
P130, P140 to P147
40
Total of all pins
170 mA
P10 to P14, P40 to P43, P120,
P130, P140 to P147
70
mA
mA
P15 to P17, P30 to P32, P50 to
P54, P60, P61, P70 to P74, P125
to P127
100
IOL2
Per pin
P20, P21
1
2
mA
mA
°C
Total of all pins
Operating ambient
temperature
TA
In normal operation mode
−40 to +85
In flash memory programming mode
Storage temperature
Tstg
−65 to +150
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 20 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.2 Oscillator Characteristics
2.2.1 Main system clock oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Resonator
Recommended
Circuit
Parameter
Conditions
MIN.
TYP. MAX.
Unit
Ceramic resonator
X1 clock oscillation
frequency (fX)Note
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
1.6 V ≤ VDD <1.8 V
1.0
1.0
1.0
20.0
8.0
MHz
MHz
MHz
V
SS X1
C1
X2
Rd
4.0
C2
Crystal resonator
X1 clock oscillation
frequency (fX)Note
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
1.6 V ≤ VDD <1.8 V
1.0
1.0
1.0
20.0
8.0
MHz
MHz
MHz
V
SS X1
C1
X2
Rd
4.0
C2
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the
above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release,
check the X1 clock oscillation stabilization time using the oscillation stabilization time
counter status register (OSTC) by the user. Determine the oscillation stabilization time of the
OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently
evaluating the oscillation stabilization time with the resonator to be used.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 21 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.2.2 On-chip oscillator characteristics
(TA = −20 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
Parameters
Conditions
1.8 V ≤ VDD < 5.5 V 24 MHz selected
16 MHz selected
MIN.
TYP. MAX.
Unit
High-speed
fIH
23.76 24.00 24.24 MHz
15.84 16.00 16.16 MHz
22.80 24.00 25.20 MHz
11.40 16.00 16.80 MHz
on-chip oscillator
clock frequency
1.6 V ≤ VDD <1.8 V 24 MHz selected
16 MHz selected
Note
Note This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution
time.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
Parameters
Conditions
1.8 V ≤ VDD < 5.5 V 24 MHz selected
16 MHz selected
MIN.
TYP. MAX.
Unit
High-speed
fIH
23.64 24.00 24.36 MHz
15.76 16.00 16.24 MHz
22.68 24.00 25.32 MHz
15.12 16.00 16.88 MHz
on-chip oscillator
clock frequency
1.6 V ≤ VDD <1.8 V 24 MHz selected
16 MHz selected
Note
Note This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution
time.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Oscillators
Parameters
Conditions
MIN.
TYP. MAX.
15 17.25
Unit
kHz
Low-speed on-chip fIL
oscillator clock
frequency
12.75
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 22 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.2.3 Subsystem clock oscillator characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Resonator
Recommended
Circuit
Items
Conditions
MIN.
32
TYP. MAX.
Unit
kHz
Crystal resonator
XT1 clock oscillation
frequency (fXT)Note
32.768
35
VSS XT2 XT1
Rd
C3
C4
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the XT1 oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as VSS.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption,
and is more prone to malfunction due to noise than the X1 oscillator. Particular care is
therefore required with the wiring method when the XT1 clock is used.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 23 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.3 DC Characteristics
2.3.1 Pin characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
mA
Output current,
highNote 1
IOH1
Per pin for P10 to P17, P30 to P32, P40 to P43, P50 to P54,
P70 to P74, P120, P125 to P127, P130, P140 to P147
−10.0
Note 3
Total of P10 to P14, P40 to P43, P120,
P130, P140 to P147
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
−40.0
−8.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
(When duty = 70%Note 2
)
−4.0
−2.0
Total of P15 to P17, P30 to P32,
−60.0
−15.0
−8.0
P50 to P54, P70 to P74, P125 to P127
(When duty = 70%Note 2
)
−4.0
Total of all pins
−100.0
(When duty = 70%Note 2
P20, P21 Per pin
)
IOH2
−0.1Note 3 mA
−1.5 mA
Total of all pins
1.6 V ≤ VDD ≤ 5.5 V
(When duty = 70%Note 2
)
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from the EVDD
pin to an output pin.
2. Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
3. Do not exceed the total current value.
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 24 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
mA
Output current,
lowNote 1
IOL1
Per pin for P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120, P125 to P127, P130,
P140 to P147
20.0
Note 3
Per pin for P60, P61
15.0Note 3
70.0
15.0
9.0
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Total of P10 to P14, P40 to P43,
P120, P130, P140 to P147
(When duty = 70%Note 2
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
)
4.5
Total of P15 to P17, P30 to P32,
P50 to P54, P60, P61, P70 to P74,
P125 to P127
(When duty = 70%Note 2
80.0
35.0
20.0
10.0
150.0
)
Total of all pins
(When duty = 70%Note 2
)
IOL2
P20, P21 Per pin for
0.4Note 3
5.0
mA
mA
Total of all pins
(When duty = 70%Note 2
1.6 V ≤ VDD ≤ 5.5 V
)
Notes 1. Value of current at which the device operation is guaranteed even if the current flows from an output
pin to the EVSS and VSS pin.
2. Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following
expression (when changing the duty factor from 70% to n%).
•
Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor.
A current higher than the absolute maximum rating must not flow into one pin.
3. Do not exceed the total current value.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of
the port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 25 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
Input voltage,
high
VIH1
P10 to P17, P30 to P32, P40 to P43, Normal input buffer 0.8EVDD
P50 to P54, P70 to P74, P120,
EVDD
P125 to P127, P140 to P147
VIH2
P10, P11, P15, P16
TTL input buffer
4.0 V 5.5 V
TTL input buffer
3.3 V 4.0 V
TTL input buffer
1.6 V 3.3 V
2.2
2.0
EVDD
EVDD
EVDD
V
V
V
≤
EVDD ≤
≤
EVDD <
1.50
≤
EVDD <
VIH3
VIH4
VIH5
VIL1
P20, P21
P60, P61
0.7VDD
0.7EVDD
0.8VDD
0
VDD
6.0
V
V
V
V
P121 to P124, P137, EXCLK, EXCLKS, RESET
VDD
Input voltage,
low
P10 to P17, P30 to P32, P40 to P43, Normal input buffer
P50 to P54, P70 to P74, P120,
0.2EVDD
P125 to P127, P140 to P147
VIL2
P10, P11, P15, P16
TTL input buffer
4.0 V 5.5 V
TTL input buffer
3.3 V 4.0 V
TTL input buffer
1.6 V 3.3 V
0
0
0
0.8
0.5
V
V
V
≤
EVDD ≤
≤
EVDD <
0.32
≤
EVDD <
VIL3
VIL4
VIL5
P20, P21
P60, P61
0
0
0
0.3VDD
0.3EVDD
0.2VDD
V
V
V
P121 to P124, P137, EXCLK, EXCLKS, RESET
Cautions The maximum value of VIH of P10, P12, P15, P17 is VDD, even in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 26 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
Output voltage,
high
VOH1
P10 to P17, P30 to P32, P40 to P43, 4.0 V
≤
EVDD
EVDD
EVDD
EVDD
≤
≤
≤
≤
5.5 V, T.B.D.
P50 to P54, P70 to P74, P120,
T.B.D.
4.0 V
T.B.D.
P125 to P127, P130, P140 to P147
≤
5.5 V, T.B.D.
5.5 V, T.B.D.
5.5 V, T.B.D.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2.7 V
≤
T.B.D.
1.8 V
≤
T.B.D.
1.6 V
≤ EVDD < 5.5 V, T.B.D.
T.B.D.
VOH2
P20, P21
1.6 V ≤ VDD ≤ 5.5 V,
T.B.D
T.B.D.
Output voltage,
low
VOL1
P10 to P17, P30 to P32, P40 to P43, 4.0 V
≤
EVDD
EVDD
EVDD
EVDD
EVDD
≤
≤
≤
≤
≤
5.5 V,
5.5 V,
5.5 V,
5.5 V,
5.5 V,
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
P50 to P54, P70 to P74, P120,
T.B.D.
4.0 V
T.B.D.
P125 to P127, P130, P140 to P147
≤
2.7 V
≤
T.B.D.
2.7 V
≤
T.B.D.
1.8 V
≤
T.B.D.
1.6 V
≤ EVDD < 5.5 V,
T.B.D.
VOL2
P20, P21
P60, P61
1.6 V ≤ VDD ≤ 5.5 V,
T.B.D.
VOL3
4.0 V
≤
EVDD
EVDD
EVDD
EVDD
≤
≤
≤
≤
5.5 V,
5.5 V,
5.5 V,
5.5 V,
T.B.D.
4.0 V
≤
T.B.D.
2.7 V
≤
T.B.D.
1.8 V
≤
T.B.D.
1.6 V
≤ EVDD < 5.5 V,
T.B.D.
Caution P10, P12, P15, P17 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 27 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
1
Unit
Input leakage
current, high
ILIH1
P10 to P17, P30 to P32,
VI = EVDD
μA
P40 to P43, P50 to P54, P60,
P61, P70 to P74, P120,
P125 to P127, P140 to P147
ILIH2
P20, P21, P137, RESET
VI = VDD
VI = VDD
1
1
μA
μA
ILIH3
P121 to P124
In input port or
external clock
input
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
In resonator
connection
10
μA
μA
Input leakage
current, low
ILIL1
P10 to P17, P30 to P32,
P40 to P43, P50 to P54, P60,
P61, P70 to P74, P120,
VI = EVSS
−1
P125 to P127, P140 to P147
ILIL2
P20, P21, P137, RESET
VI = VSS
VI = VSS
−1
−1
μA
μA
ILIL3
P121 to P124
In input port or
external clock
input
(X1, X2, XT1, XT2, EXCLK,
EXCLKS)
In resonator
connection
−10
μA
kΩ
On-chip pll-up
resistance
RU
P10 to P17, P30 to P32,
P40 to P43, P50 to P54,
P70 to P74, P120,
VI = EVSS, In input port
10
20
100
P125 to P127, P140 to P147
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 28 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.3.2 Supply current characteristics
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
(1/2)
Parameter Symbol
Conditions
fIH = 24 MHzNote 3
MIN.
TYP.
1.8
1.8
3.7
3.7
2.7
2.7
1.2
1.2
1.2
1.2
3.0
3.2
3.0
3.2
1.9
1.9
1.9
1.9
1.1
1.1
1.1
1.1
4.1
4.2
4.1
4.2
4.2
4.3
4.2
4.3
4.8
4.9
MAX.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
Note 1
IDD1
Supply
current
Operating High-speed
mode
Basic
operation
VDD = 5.0 V
operationNote 5
VDD = 3.0 V
Normal
operation
VDD = 5.0 V
VDD = 3.0 V
fIH = 16 MHzNote 3
fIH = 8 MHzNote 3
fIH = 4 MHzNote 3
Normal
operation
VDD = 5.0 V
VDD = 3.0 V
Low-speed
Normal
operation
VDD = 3.0 V
operationNote 5
VDD = 2.0 V
Low-voltage
operationNote 5
Normal
operation
VDD = 3.0 V
VDD = 2.0 V
High-speed
fMX = 20 MHzNote 2
VDD = 5.0 V
,
Normal
operation
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
operationNote 5
fMX = 20 MHzNote 2
,
,
,
Normal
operation
VDD = 3.0 V
fMX = 10 MHzNote 2
VDD = 5.0 V
fMX = 10 MHzNote 2
Normal
operation
Normal
operation
VDD = 3.0 V
Low-speed
fMX = 8 MHzNote 2
VDD = 3.0 V
,
Normal
operation
operationNote 5
fMX = 8 MHzNote 2
,
Normal
operation
VDD = 2.0 V
Subsystem
clock
operation
f
SUB = 32.768 kHz Note 4 Normal
operation
T = −40°C
A
μA
f
SUB = 32.768 kHz Note 4 Normal
μA
operation
T = +25°C
SUB = 32.768 kHz Note 4 Normal
A
μA
f
μA
operation
T = +50°C
SUB = 32.768 kHz Note 4 Normal
A
μA
f
μA
operation
T = +70°C
SUB = 32.768 kHz Note 4 Normal
A
μA
f
μA
operation
T = +85°C
A
μA
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 29 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current (except for back ground operation (BGO)). However, not including the current flowing
into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. When high-speed on-chip oscillator and subsystem clock are stopped.
3. When high-speed system clock and subsystem clock are stopped.
4. When high-speed on-chip oscillator and high-speed system clock are stopped. When real-time clock
and watchdog timer are stopped. When AMPHS1 = 1 (Ultra-low power consumption oscillation).
5. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
High speed operation: VDD = 2.4 V to 5.5 V@1 MHz to 24 MHz
Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation, temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 30 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
(2/2)
Parameter Symbol
Conditions
fIH = 24 MHzNote 4
MIN.
TYP.
0.44
0.44
0.40
0.40
260
MAX.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
Unit
mA
mA
mA
mA
μA
μA
μA
μA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
μA
Supply
IDD2
HALT
mode
High-speed
VDD = 5.0 V
Note 2
current
operationNote 7
VDD = 3.0 V
Note 1
fIH = 16 MHzNote 4
fIH = 8 MHzNote 4
VDD = 5.0 V
VDD = 3.0 V
Low-speed
VDD = 3.0 V
operationNote 7
VDD = 2.0 V
260
Low-voltage fIH = 4 MHzNote 4
operation
VDD = 3.0 V
420
VDD = 2.0 V
420
High-speed
fMX = 20 MHzNote 3
,
,
,
,
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
Square wave input
Resonator connection
0.28
0.45
0.28
0.45
0.19
0.26
0.19
0.26
95
operationNote 7
VDD = 5.0 V
fMX = 20 MHzNote 3
VDD = 3.0 V
fMX = 10 MHzNote 3
VDD = 5.0 V
fMX = 10 MHzNote 3
VDD = 3.0 V
fMX = 8 MHzNote 3
Low-speed
,
operationNote 7
VDD = 3.0 V
145
fMX = 8 MHzNote 3
VDD = 2.0 V
fSUB = 32.768 kHzNote 5
,
95
145
Subsystem
clock
operation
0.32
0.51
0.37
0.56
0.40
0.59
0.43
0.62
1.04
1.23
0.18
0.23
0.26
0.29
0.90
TA = −40C
fSUB = 32.768 kHzNote 5
TA = +25°C
fSUB = 32.768 kHzNote 5
TA = +50°C
fSUB = 32.768 kHzNote 5
TA = +70°C
fSUB = 32.768 kHzNote 5
TA = +85°C
Note 6
IDD3
STOP
mode
TA = −40°C
TA = +25°C
TA = +50°C
TA = +70°C
TA = +85°C
(Notes and Remarks are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 31 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Notes 1. Total current flowing into VDD and EVDD, including the input leakage current flowing when the level of the
input pin is fixed to VDD, EVDD or VSS, EVSS. The values below the MAX. column include the peripheral
operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port,
and on-chip pull-up/pull-down resistors.
2. During HALT instruction execution by flash memory.
3. When high-speed on-chip oscillator and subsystem clock are stopped.
4. When high-speed system clock and subsystem clock are stopped.
5. When operating real-time clock (RTC) and setting ultra-low current consumption (AMPHS1 = 1). When
high-speed on-chip oscillator and high-speed system clock are stopped. When watchdog timer is
stopped.
6. When high-speed on-chip oscillator, high-speed system clock, and subsystem clock are stopped. When
watchdog timer is stopped.
7. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
below.
High speed operation: VDD = 2.4 V to 5.5 V@1 MHz to 24 MHz
Low speed operation: VDD = 1.8 V to 5.5 V@1 MHz to 8 MHz
Low voltage operation: VDD = 1.6 V to 5.5 V@1 MHz to 4 MHz
Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system
clock frequency)
2. fIH: High-speed on-chip oscillator clock frequency
3. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
4. Except subsystem clock operation and STOP mode, temperature condition of the TYP. value is TA =
25°C
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 32 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
0.02
0.02
0.22
MAX.
Unit
Notes 1, 2
RTC operating
current
IRTC
fSUB = 32.768 kHz
fIL = 15 kHz
Real-time clock operation
Interval timer operation
μA
Notes 2, 3
Watchdog timer IWDT
operating
μA
current
Note 4
A/D converter
operating
current
IADC
Normal mode, AVREFP = VDD = 5.0 V
1.3
0.5
1.7
0.7
mA
mA
Low voltage mode, AVREFP = VDD = 3.0 V
Temperature
sensor
ITMPS
75
μA
operating
current
Note 5
LVD operating
current
ILVI
0.08
2.50
μA
Note 6
mA
BGO operating
current
IBGO
12.20
LCD operating
current
ILCD1
VDD = 5.0 V
VDD = 3.0 V
VDD = 3.0 V
T.B.D. T.B.D.
μA
μA
μA
External resistance LCD clock = 128 Hz
division method
Notes 7, 8
Note7
ILCD2
1.0
T.B.D.
T.B.D.
Internal voltage
boosting method
LCD clock = 128 Hz
Note7
ILCD3
0.12
Capacitor split
method
LCD clock = 128 Hz
Notes 1. Current flowing only to the real-time clock (excluding the operating current of the XT1 oscillator). The
TYP. value of the current value of the RL78/L12 is the sum of the TYP. values of either IDD1 or IDD2, and
IRTC, when the real-time clock operates in operation mode or HALT mode. The IDD1 and IDD2 MAX.
values also include the real-time clock operating current. However, IDD2 subsystem clock operation
includes the operational current of the real-time clock.
2. When high-speed on-chip oscillator and high-speed system clock are stopped.
3. Current flowing only to the watchdog timer (including the operating current of the low-speed on-chip
oscillator). The current value of the RL78/L12 is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB
when the watchdog timer operates in STOP mode.
4. Current flowing only to the A/D converter. The current value of the RL78/L12 is the sum of IDD1 or IDD2
and IADC when the A/D converter operates in an operation mode or the HALT mode.
5. Current flowing only to the LVD circuit. The current value of the RL78/L12 is the sum of IDD1, IDD2 or
IDD3 and ILVI when the LVD circuit operates in the Operating, HALT or STOP mode.
6. Current flowing only when the BGO operates. The current value of the RL78/L12 is the sum of IDD1 or
IDD2 and IBGO when the BGO operates in an operation mode.
7. Current flowing only to the LCD controller/driver (VDD pin). The current value of the RL78/L12
microcontrollers is the sum of the LCD operating current (ILCD1, ILCD2 or ILCD3) to the supply current (IDD1,
or IDD2) when the LCD controller/driver operates in an operation mode or HALT mode. Not including the
current that flows through the LCD panel.
8. Not including the current that flows through the LCD divider resistor.
Remarks 1. fIL: Low-speed on-chip oscillator clock frequency
2. fSUB: Subsystem clock frequency (XT1 clock oscillation frequency)
3. fCLK: CPU/peripheral hardware clock frequency
4. Temperature condition of the TYP. value is TA = 25°C
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 33 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.4 AC Characteristics
2.4.1 Basic operation
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
TCY
Conditions
MIN.
TYP.
MAX.
1
Unit
Instruction cycle (minimum
instruction execution time)
Main
system
clock (fMAIN)
operation
High-speed 2.7 V
main mode
≤
V
DD
≤
5.5 V 0.04167
μs
2.4 V
≤
≤
V
DD < 2.7 V 0.0625
1
1
μs
μs
Low voltage 1.6 V
main mode
VDD
≤
≤
≤
≤
5.5 V 0.25
5.5 V 0.125
5.5 V 28.5
5.5 V 0.04167
Low-speed 1.8 V
main mode
≤
≤
VDD
1
μs
μs
Subsystem clock (fSUB)
operation
1.8 V
VDD
30.5
31.3
In the self
High-speed 2.7 V
programming main mode
mode
≤
≤
VDD
1
1
μs
μs
2.4 V
VDD < 2.7 V 0.0625
Low voltage 1.8 V
main mode
≤
≤
V
DD
≤
≤
5.5 V 0.25
5.5 V 0.125
1
1
μs
μs
Low-speed 1.8 V
main mode
VDD
External main system clock
frequency
fEX
2.7 V ≤ VDD ≤ 5.5 V
1.0
1.0
1.0
32
20.0
8.0
4.0
35
MHz
MHz
MHz
kHz
ns
1.8 V ≤ VDD < 2.7 V
1.6 V ≤ VDD < 1.8 V
fEXS
External main system clock input tEXH, tEXL
high-level width, low-level width
2.7 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD < 2.7 V
1.6 V ≤ VDD < 1.8 V
24
60
120
ns
ns
tEXHS, tEXLS
13.7
μs
TI00 to TI07 input high-level
width, low-level width
tTIH,
tTIL
1/fMCK+10
nsNote
TO00 to TO07 output frequency
fTO
High-speed main 4.0 V ≤ EVDD ≤ 5.5 V
12
8
MHz
MHz
MHz
MHz
MHz
mode
2.7 V ≤ EVDD < 4.0 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
4
2
Low voltage main 1.6 V ≤ EVDD ≤ 5.5 V
mode
2
Low-speed main
mode
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD < 1.8 V
4
2
MHz
MHz
PCLBUZ0, PCLBUZ1 output
frequency
fPCL
High-speed main 4.0 V ≤ EVDD ≤ 5.5 V
16
8
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
μs
mode
2.7 V ≤ EVDD < 4.0 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
4
2
Low voltage main 1.8 V ≤ EVDD ≤ 5.5 V
4
mode
1.6 V ≤ EVDD < 1.8 V
2
Low-speed main
mode
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD < 1.8 V
1.6 V ≤ VDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD < 1.8 V
4
2
Interrupt input high-level width,
low-level width
tINTH,
tINTL
INTP0
1
1
INTP1 to INTP7
KR0 to KR3
μs
Key interrupt input low-level width tKR
250
1
ns
μs
RESET low-level width
tRSL
10
μs
(Note and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 34 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
Note The following conditions are required for low voltage interface when EVDD<VDD
1.8 V ≤ EVDD < 2.7 V : MIN. 125 ns
1.6 V ≤ EVDD < 1.8 V : MIN. 250 ns
Remark fMCK: Timer array unit operation clock frequency
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n =
0 to 7))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 35 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.5 Peripheral Functions Characteristics
2.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
fMCK/6Note 2
4.0
Unit
bps
Transfer rateNote 1
Theoretical value of the
maximum transfer rate
fCLK=24MHz, fMCK= fCLK
Mbps
UART mode connection diagram (during communication at same potential)
TxDq
RxDq
Rx
Tx
User's device
RL78/L12
UART mode bit width (during communication at same potential) (reference)
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
TxDq
RxDq
Notes 1. Transfer rate in the SNOOZE mode is max. 9600 bps, min. 4800 bps.
2. The following conditions are required for low voltage interface when EVDD<VDD.
2.4 V ≤ EVDD < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD < 1.8 V : MAX. 0.6 Mbps
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. q: UART number (q = 0), g: PIM and POM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 36 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(2) During communication at same potential (CSI mode) (master mode (fMCK/2, fMCK/4), SCKp... internal
clock output)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
MIN.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKp cycle time
tKCY1
167Note 1
250Note 1
500Note 1
1000Note 1
tKCY1/2 − 12
tKCY1/2 − 18
tKCY1/2 − 38
tKCY1/2 − 50
SCKp high-/low-level width
tKH1,
tKL1
tKCY1/2 −
100
SIp setup time (to SCKp↑)Note 2
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD ≤ 5.5 V
2.4 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
44
44
ns
ns
ns
ns
ns
ns
ns
75
110
220
19
SIp hold time (from SCKp↑) Note 3
tKSI1
Delay time from SCKp↓ to
SOp output Note 4
tKSO1
C = 30 pFNote 5
25
Notes 1. For CSI00, set a cycle of 2/fCLK or longer. For other than CSI00, set a cycle of 4/fCLK or longer.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp pin and
SCKp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM numbers (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 37 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
8/fMCK
6/fMCK
8/fMCK
6/fMCK
8/fMCK
6/fMCK
6/fMCK
tKCY2/2
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
SCKp cycle time Note 5
tKCY2
4.0 V ≤ EVDD ≤ 20 MHz < fMCK
5.5 V
fMCK ≤ 20 MHz
2.7 V ≤ EVDD < 16 MHz < fMCK
4.0 V
fMCK ≤ 16 MHz
1.8 V ≤ EVDD < 16 MHz < fMCK
2.7 V
fMCK ≤ 16 MHz
1.6 V ≤ EVDD < 1.8 V
1.6 V ≤ EVDD ≤ 5.5 V
SCKp high-/low-level width
tKH2,
tKL2
SIp setup time
tSIK2
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD < 2.7 V
1.6 V ≤ EVDD < 1.8 V
1/fMCK+20
1/fMCK+30
1/fMCK+40
1/fMCK+31
1/fMCK+31
ns
ns
ns
ns
ns
ns
(to SCKp↑) Note 1
SIp hold time
(from SCKp↑) Note 2
tKSI2
1/fMCK+
250
Delay time from SCKp↓ to
SOp output Note 3
tKSO2
C = 30 pF Note 4 4.0 V ≤ EVDD ≤ 5.5 V
2.7 V ≤ EVDD < 4.0 V
2/fMCK+44
2/fMCK+44
2/fMCK+75
2/fMCK+110
ns
ns
ns
ns
ns
2.4 V ≤ EVDD < 2.7 V
1.8 V ≤ EVDD < 2.4 V
1.6 V ≤ EVDD < 1.8 V
2/fMCK+
220
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp
pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1. p: CSI number (p = 00, 01), m: Unit number (m = 0),
n: Channel number (n = 0, 1), g: PIM number (g = 1)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01))
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 38 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
CSI mode connection diagram (during communication at same potential)
SCKp
SIp
SCK
SO
User's device
RL78/L12
SOp
SI
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KCY1, 2
t
KL1, 2
t
KH1, 2
SCKp
t
SIK1, 2
t
KSI1, 2
SIp
Input data
t
KSO1, 2
Output data
SOp
CSI mode serial transfer timing (during communication at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1, 2
tKH1, 2
tKL1, 2
SCKp
tSIK1, 2
tKSI1, 2
SIp
Input data
tKSO1, 2
Output data
SOp
Remarks 1. p: CSI number (p = 00, 01)
2. m: Unit number, n: Channel number (mn = 00, 01)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 39 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
bps
Transfer rate
reception 4.0 V ≤ EVDD ≤ 5.5 V,
fMCK/6Note 1
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the
maximum transfer rate
4.0
Mbps
fCLK = 24 MHz, fMCK = fCLK
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK/6Note 1
bps
Theoretical value of the
maximum transfer rate
4.0
Mbps
fCLK = 24 MHz, fMCK = fCLK
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
fMCK/6
Notes 1 to 3
bps
Theoretical value of the
maximum transfer rate
1.3
Mbps
fCLK = 8 MHz, fMCK = fCLK
Notes 1. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
2. Use it with EVDD≥Vb.
3. The following conditions are required for low voltage interface when EVDD<VDD.
2.4 V ≤ EVDD < 2.7 V : MAX. 2.6 Mbps
1.8 V ≤ EVDD < 2.4 V : MAX. 1.3 Mbps
1.6 V ≤ EVDD < 1.8 V : MAX. 0.6 Mbps
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1. Vb[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ V
b
≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ V
b
b
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 40 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(4) Communication at different potential (2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP. MAX.
Unit
bps
Transfer rate
transmission 4.0 V ≤ EVDD ≤ 5.5 V,
Notes
1, 2
2.8 Note 3
2.7 V ≤ Vb ≤ 4.0 V
Theoretical value of the
maximum transfer rate
Mbps
Cb
= 50 pF, R
b
= 1.4 k
Ω
, V = 2.7 V
b
2.7 V ≤ EVDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
Notes
2, 4
bps
Theoretical value of the
maximum transfer rate
1.2 Note 5
Mbps
Cb
= 50 pF, R
b
= 2.7 k
Ω
, V = 2.3 V
b
1.8 V ≤ EVDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Notes
2, 6, 7
bps
Theoretical value of the
maximum transfer rate
0.43
Notes 8
Mbps
Cb
= 50 pF, R
b
= 5.5 k
Ω
, V = 1.6 V
b
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 4.0 V ≤ EVDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate =
[bps]
2.2
Vb
{−Cb × Rb × ln (1 −
)} × 3
1
2.2
Vb
− {−Cb × Rb × ln (1−
)}
Transfer rate × 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
*
This value is the theoretical value of the relative difference between the transmission and reception sides.
2. Transfer rate in the SNOOZE mode : MAX. 9600 bps, MIN. 4800 bps
3. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer.
4. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ EVDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
[bps]
2.0
Vb
{−Cb × Rb × ln (1 −
)} × 3
1
2.0
Vb
− {−Cb × Rb × ln (1 −
)}
Transfer rate × 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
*
This value is the theoretical value of the relative difference between the transmission and reception sides.
5. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 4 above to calculate the maximum transfer rate under conditions of the customer.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 41 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Notes 6. Use it with EVDD ≥ Vb.
7. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 1.8 V ≤ EVDD < 3.3 V and 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate =
[bps]
1.5
Vb
{−Cb × Rb × ln (1 −
)} × 3
1
1.5
Vb
− {−Cb × Rb × ln (1 −
)}
Transfer rate × 2
Baud rate error (theoretical value) =
× 100 [%]
1
(
) × Number of transferred bits
Transfer rate
*
This value is the theoretical value of the relative difference between the transmission and reception sides.
8. This value as an example is calculated when the conditions described in the “Conditions” column are
met. Refer to Note 7 above to calculate the maximum transfer rate under conditions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
2. q: UART number (q = 0, 1), g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in UART mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ V
b
≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
b
b
UART mode connection diagram (during communication at different potential)
Vb
Rb
TxDq
RxDq
Rx
Tx
RL78/L12
User's device
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 42 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
UART mode bit width (during communication at different potential) (reference)
1/Transfer rate
Low-bit width
High-bit width
Baud rate error tolerance
TxDq
1/Transfer rate
High-/Low-bit width
Baud rate error tolerance
RxDq
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode
for the TxDq pin by using port input mode register g (PIMg) and port output mode register g
(POMg).
Remarks 1. Rb[Ω]:Communication line (TxDq) pull-up resistance, Vb[V]: Communication line voltage
2. q: UART number (q = 0), g: PIM and POM number (g = 1)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 43 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(5) Communication at different potential (2.5 V, 3 V) (fMCK/2) (CSI mode) (master mode, SCKp... internal clock
output)
(TA = −40 to +85°C, 2.7 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
ns
SCKp cycle time
tKCY1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 200 Note 1
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 300Note 1
Cb = 20 pF, Rb = 2.7 kΩ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKp high-level width
SCKp low-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 50
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 −
120
Cb = 20 pF, Rb = 2.7 kΩ
tKL1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 7
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 10
Cb = 20 pF, Rb = 2.7 kΩ
SIp setup time
tSIK1
tKSI1
tKSO1
tSIK1
tKSI1
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
58
121
10
(to SCKp↑)Note 2
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↑) Note 2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10
Delay time from SCKp↓ to
SOp output Note 2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
60
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
130
SIp setup time
(to SCKp↓)Note 3
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
23
33
10
10
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
SIp hold time
(from SCKp↓) Note 3
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
Delay time from SCKp↑ to
SOp output Note 3
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10
10
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 44 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
Rb
R
b
SCKp
SIp
SCK
SO
User's device
RL78/L12
SOp
SI
Notes 1. The value must also be 2/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
3. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ V
b
≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ V
b
b
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ V
4. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00, 01)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 45 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(6) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
ns
SCKp cycle time
tKCY1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, 300 Note
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, 500Note
ns
ns
ns
ns
ns
ns
ns
ns
Cb = 30 pF, Rb = 2.7 kΩ
2.7 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, 1150Note
Cb = 30 pF, Rb = 5.5 kΩ
SCKp high-level width
tKH1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 75
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 −
170
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 −
458
Cb = 30 pF, Rb = 5.5 kΩ
SCKp low-level width
tKL1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V, tKCY1/2 − 12
Cb = 30 pF, Rb = 1.4 kΩ
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V, tKCY1/2 − 18
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V, tKCY1/2 − 50
Cb = 30 pF, Rb = 5.5 kΩ
Note The value must also be 4/fCLK or more.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
2. Use it with EVDD ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1), g: PIM and POM
number (g = 1)
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ V
b
≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ V
b
b
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 46 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(6) Communication at different potential (2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock
output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
81
TYP.
MAX.
Unit
ns
SIp setup time
tSIK1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
(to SCKp↑)Note 1
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
177
479
19
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp hold time
tKSI1
tKSO1
tSIK1
tKSI1
tKSO1
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
(from SCKp↑) Note 1
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
19
Delay time from SCKp↓ to
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
100
195
483
SOp output Note 1
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
SIp setup time
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
44
44
(to SCKp↓)Note 2
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
110
19
SIp hold time
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
(from SCKp↓) Note 2
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
19
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
19
Delay time from SCKp↑ to
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
25
25
25
SOp output Note 2
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 47 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
CSI mode connection diagram (during communication at different potential)
<Master>
Vb
Vb
Rb
R
b
SCKp
SIp
SCK
SO
User's device
RL78/L12
SOp
SI
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Cautions 1. Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance)
mode for the SOp pin and SCKp pin by using port input mode register g (PIMg) and port
output mode register g (POMg).
2. Use it with EVDD ≥ Vb.
Remarks 1. Rb[Ω]:Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp)
load capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ V
b
≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ V
b
b
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 48 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
t
KL1
t
KH1
SCKp
t
SIK1
t
KSI1
SIp
Input data
t
KSO1
SOp
Output data
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
t
KL1
t
KH1
SCKp
t
SIK1
t
KSI1
SIp
Input data
t
KSO1
Output data
SOp
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 49 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(7) Communication at different potential (2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCKp cycle timeNote 1
tKCY2
4.0 V
2.7 V
≤
≤
EVDD
≤
5.5 V, 20 MHz < fMCK ≤ 24 MHz
12/fMCK
10/fMCK
8/fMCK
Vb ≤ 4.0 V
8 MHz < fMCK ≤ 20 MHz
4 MHz < fMCK ≤ 8 MHz
fMCK ≤ 4 MHz
6/fMCK
2.7 V
2.3 V
≤
≤
EVDD < 4.0 V, 20 MHz < fMCK ≤ 24 MHz
16/fMCK
14/fMCK
12/fMCK
8/fMCK
Vb ≤ 2.7 V
16 MHz < fMCK ≤ 20 MHz
8 MHz < fMCK ≤ 16 MHz
4 MHz < fMCK ≤ 8 MHz
fMCK ≤ 4 MHz
6/fMCK
1.8 V
1.6 V
≤
≤
EVDD < 3.3 V, 20 MHz < fMCK ≤ 24 MHz
36/fMCK
32/fMCK
26/fMCK
16/fMCK
10/fMCK
V ≤
2.0 VNote2
b
16 MHz < fMCK ≤ 20 MHz
8 MHz < fMCK ≤ 16 MHz
4 MHz < fMCK ≤ 8 MHz
fMCK ≤ 4 MHz
SCKp high-/low-level
widthNote 2
tKH2,
tKL2
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
t
KCY2/2 −
12
t
KCY2/2 −
ns
ns
18
t
KCY2/2 −
50
SIp setup time
tSIK2
2.7 V ≤ VDD < 5.5 V
1.8 V ≤ Vb ≤ 3.3 V
1/fMCK + 20
1/fMCK + 30
1/fMCK + 31
ns
ns
ns
(to SCKp↑) Note 3
SIp hold time
(from SCKp↑) Note 4
tKSI2
Delay time from SCKp↓ to tKSO2
SOp output Notes 2, 5
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK +
120
ns
ns
ns
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK +
214
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK +
573
(Note, Caution and Remark are listed on the next page.)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 50 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
CSI mode connection diagram (during communication at different potential)
<Slave>
Vb
Rb
SCKp
SIp
SCK
SO
User's device
RL78/L12
SOp
SI
Notes 1. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
2. Use it with EVDD ≥ Vb.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remarks 1. Rb[Ω]:Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load
capacitance, Vb[V]: Communication line voltage
2. p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00, 01))
4. VIH and VIL below are observation points for the AC characteristics of the serial array unit when
communicating at different potentials in CSI mode.
4.0 V ≤ EVDD ≤ 5.5 V, 2.7 V ≤ V
b
≤ 4.0 V: VIH = 2.2 V, VIL = 0.8 V
≤ 2.7 V: VIH = 2.0 V, VIL = 0.5 V
≤ 2.0 V: VIH = 1.50 V, VIL = 0.32 V
2.7 V ≤ EVDD < 4.0 V, 2.3 V ≤ V
b
b
1.8 V ≤ EVDD < 3.3 V, 1.6 V ≤ V
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 51 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
t
KCY2
t
KL2
t
KH2
SCKp
tSIK2
t
KSI2
SIp
Input data
t
KSO2
Output data
SOp
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
t
KCY2
t
KL2
t
KH2
SCKp
tSIK2
t
KSI2
SIp
Input data
t
KSO2
Output data
SOp
Caution Select the TTL input buffer for the SIp pin and SCKp pin and the N-ch open drain output (VDD
tolerance) mode for the SOp pin by using port input mode register g (PIMg) and port output mode
register g (POMg).
Remark p: CSI number (p = 00, 01), m: Unit number (m = 0), n: Channel number (n = 0, 1),
g: PIM and POM number (g = 1)
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 52 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.5.2 Serial interface IICA
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
Standard
Mode
Fast Mode
Fast Mode
Plus
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Fast mode plus:
SCLA0 clock frequency
fSCL
2.7 V ≤ EVDD ≤ 5.5 V
1.8 V ≤ EVDD ≤ 5.5 V
1.6 V ≤ EVDD ≤ 5.5 V
0
1000 kHz
fCLK ≥ 10 MHz
Fast mode:
0
400
kHz
fCLK ≥ 3.5 MHz
Normal mode:
fCLK ≥ 1 MHz
0
100
kHz
Setup time of restart conditionNote 1
Hold time
tSU:STA
tHD:STA
tLOW
4.7
4.0
4.7
4.0
250
0
0.6
0.6
1.3
0.6
100
0
0.26
0.26
0.5
μs
μs
μs
μs
ns
μs
μs
μs
Hold time when SCLA0 = “L”
Hold time when SCLA0 = “H”
Data setup time (reception)
Data hold time (transmission)Note 2
Setup time of stop condition
Bus-free time
tHIGH
0.26
50
tSU:DAT
tHD:DAT
tSU:STO
tBUF
3.45
0.9
0
4.0
4.7
0.6
1.3
0.26
0.5
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line
pull-up resistor) at that time in each mode are as follows.
Standard mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode:
Cb = 320 pF, Rb = 1.1 kΩ
Fast mode plus: Cb = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
tLOW
SCL0
SDA0
tHD:DAT
t
HIGH
SU:DAT
t
SU:STA
t
HD:STA
tSU:STO
tHD:STA
t
tLOW
Stop
Start
Restart
condition
Stop
condition
condition condition
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 53 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.5.3 On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
1 M
Unit
bps
Transfer rate
115.2 k
2.6 Analog Characteristics
2.6.1 A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), target
ANI pin : ANI16 to ANI23 (supply ANI pin to EVDD)
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = AVREFP, Reference
voltage (−) = AVREFM)
Parameter
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Resolution
Overall errorNotes 1, 2
AINL
10-bit resolution
AVREFP = VDD
1.8 V ≤ VDD ≤ 5.5 V
1.2
1.2
±5.0
±8.5
39
LSB
LSB
μs
1.6 V ≤ VDD ≤ 5.5 V
3.6 V ≤ VDD ≤ 5.5 V
Conversion time
tCONV
10-bit resolution
AVREFP = VDD
2.125
2.7 V ≤ VDD ≤ 5.5 V 3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
17
57
39
μs
95
μs
Zero-scale errorNotes 1, 2
EZS
EFS
ILE
±0.35
±0.60
±0.35
±0.60
±3.5
±6.0
±2.0
±2.5
VDD
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
10-bit resolution
AVREFP = VDD
Full-scale errorNotes 1, 2
10-bit resolution
AVREFP = VDD
Integral linearity errorNote 1
Differential linearity errorNote 1
10-bit resolution
AVREFP = VDD
DLE
10-bit resolution
AVREFP = VDD
Reference voltage (+)
Analog input voltage
AVREFP
VAIN
1.6
0
AVREFP
V
and EVDD
Note3
VBGR
2.4 V ≤ VDD ≤ 5.5 V
1.38
1.45
1.5
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. HS (high-speed main) mode only
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 54 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(2) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = VSS (ADREFM = 0), target ANI pin : ANI0,
ANI1, ANI16 to ANI23
(TA = −40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VDD, Reference
voltage (−) = VSS)
Parameter
Symbol
RES
Conditions
MIN.
8
TYP.
MAX.
10
Unit
bit
Resolution
Overall errorNotes 1, 2
AINL
10-bit resolution
10-bit resolution
1.8 V ≤ VDD ≤ 5.5 V
1.2
1.2
±7.0
±10.5
39
LSB
LSB
μs
1.6 V ≤ VDD ≤ 5.5 V
3.6 V ≤ VDD ≤ 5.5 V
Conversion time
tCONV
2.125
2.7 V ≤ VDD ≤ 5.5 V 3.1875
39
μs
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
1.8 V ≤ VDD ≤ 5.5 V
1.6 V ≤ VDD ≤ 5.5 V
17
57
39
μs
95
μs
Zero-scale errorNotes 1, 2
Full-scale errorNotes 1, 2
EZS
EFS
ILE
±0.60
±0.85
±0.60
±0.85
±4.0
±6.5
±2.0
±2.5
VDD
%FSR
%FSR
%FSR
%FSR
LSB
LSB
LSB
LSB
V
10-bit resolution
10-bit resolution
10-bit resolution
10-bit resolution
Integral linearity errorNote 1
Differential linearity errorNote 1
Analog input voltage
DLE
VAIN
ANI0, ANI1
0
0
ANI16 to ANI23
2.4 V ≤ VDD ≤ 5.5 V
EVDD
1.5
V
Note3
VBGR
1.38
1.45
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
3. HS (high-speed main) mode only
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 55 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(3) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (−) = AVREFM/ANI1
(ADREFM = 1), target ANI pin : ANI0, ANI16 to ANI23
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V, Reference voltage (+) = VBGR, Reference
voltage (−) = AVREFM = 0 V) (HS (high-speed main) mode only)
Parameter
Symbol
RES
Conditions
MIN.
TYP.
8
MAX.
Unit
bit
Resolution
Conversion time
tCONV
EZS
8-bit resolution
8-bit resolution
8-bit resolution
8-bit resolution
2.4 V ≤ VDD ≤ 5.5 V
17
39
±0.60
±2.0
±1.0
1.5
μs
Zero-scale errorNotes 1, 2
Integral linearity errorNote 1
Differential linearity errorNote 1
Reference voltage (+)
Reference voltage (−)
Analog input voltage
2.4 V ≤ VDD ≤ 5.5 V
2.4 V ≤ VDD ≤ 5.5 V
2.4 V ≤ VDD ≤ 5.5 V
%FSR
LSB
LSB
V
ILE
DLE
VBGR
AVREFM
VAIN
1.38
0
1.45
VSS
V
VBGR
V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale value.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 56 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.6.2 Temperature sensor characteristics
(TA = −40 to +85°C, 2.4 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V) (HS (high-speed main) mode only)
Parameter
Symbol
Conditions
MIN.
TYP.
1.05
1.45
−3.6
MAX.
Unit
V
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H, TA = +25°C
Reference output voltage
Temperature coefficient
VCONST
FVTMPS
Setting ADS register = 81H
1.38
1.5
V
Temperature sensor that depends on the
temperature
mV/C
Operation stabilization wait time
tAMP
5
μs
2.6.3 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Detection voltage
Symbol
VPOR
Conditions
Power supply rise time
Power supply fall time
MIN.
1.48
1.47
300
TYP.
1.51
1.50
MAX.
1.54
1.53
Unit
V
VPDR
V
Minimum pulse width
Detection delay time
TPW
μs
μs
350
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 57 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.6.4 LVD circuit characteristics
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
Power supply rise time
MIN.
3.98
3.90
3.68
3.60
3.07
3.00
2.96
2.90
2.86
2.80
2.76
2.70
2.66
2.60
2.56
2.50
2.45
2.40
2.05
2.00
1.94
1.90
1.84
1.80
1.74
1.70
1.64
1.60
300
TYP.
4.06
3.98
3.75
3.67
3.13
3.06
3.02
2.96
2.92
2.86
2.81
2.75
2.71
2.65
2.61
2.55
2.50
2.45
2.09
2.04
1.98
1.94
1.88
1.84
1.77
1.73
1.67
1.63
MAX.
4.14
4.06
3.82
3.74
3.19
3.12
3.08
3.02
2.97
2.91
2.87
2.81
2.76
2.70
2.66
2.60
2.55
2.50
2.13
2.08
2.02
1.98
1.91
1.87
1.81
1.77
1.70
1.66
Unit
V
Detection
voltage
Supply voltage level
VLVI0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
μs
μs
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
Power supply rise time
Power supply fall time
VLVI1
VLVI2
VLVI3
VLVI4
VLVI5
VLVI6
VLVI7
VLVI8
VLVI9
VLVI10
VLVI11
VLVI12
VLVI13
Minimum pulse width
Detection delay time
tLW
tLD
300
Remark VLVI(n − 1) > VLVIn: n = 1 to 13
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 58 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
LVD Detection Voltage of Interrupt & Reset Mode
(TA = −40 to +85°C, VPDR ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
1.60
1.74
1.70
1.84
1.80
2.86
2.80
1.80
1.94
1.90
2.05
2.00
3.07
3.00
2.40
2.56
2.50
2.66
2.60
3.68
3.60
2.70
2.86
2.80
2.96
2.90
3.98
3.90
TYP.
1.63
1.77
1.73
1.88
1.84
2.92
2.86
1.84
1.98
1.94
2.09
2.04
3.13
3.06
2.45
2.61
2.55
2.71
2.65
3.75
3.67
2.75
2.92
2.86
3.02
2.96
4.06
3.98
MAX.
1.66
1.81
1.77
1.91
1.87
2.97
2.91
1.87
2.02
1.98
2.13
2.08
3.19
3.12
2.50
2.66
2.60
2.76
2.70
3.82
3.74
2.81
2.97
2.91
3.08
3.02
4.14
4.06
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Interrupt and reset VLVI13
VPOC0, VPOC1, VPOC2 = 0, 0, 0, falling reset voltage: 1.6 V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
mode
VLVI12
(+0.1 V)
Falling interrupt voltage
VLVI11
VLVI4
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
VLVI11
VLVI10
VPOC0, VPOC1, VPOC2 = 0, 0, 1, falling reset voltage: 1.8 V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
VLVI9
VLVI2
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
VLVI8
VLVI7
VPOC0, VPOC1, VPOC2 = 0, 1, 0, falling reset voltage: 2.4 V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
VLVI6
VLVI1
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
VLVI5
VLVI4
VPOC0, VPOC1, VPOC2 = 0, 1, 1, falling reset voltage: 2.7 V
LVIS0, LVIS1 = 1, 0 Rising release reset voltage
(+0.1 V)
Falling interrupt voltage
VLVI3
LVIS0, LVIS1 = 0, 1 Rising release reset voltage
(+0.2 V)
Falling interrupt voltage
VLVI0
LVIS0, LVIS1 = 0, 0 Rising release reset voltage
(+1.2 V)
Falling interrupt voltage
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 59 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.6.5 Supply voltage rise time
(TA = −40 to +85°C, VSS = 0 V)
Parameter
Symbol
tPUP1
Conditions
MIN.
TYP.
MAX.
3.2
Unit
ms
Maximum timeto rise to
1.6 V (VDD (MIN.))Note
When RESET input is not used
(VDD: 0 V → 1.6 V)
Note Make sure to raise the power supply in a shorter time than this.
Supply Voltage Rise Time Timing
• When RESET pin input is not used
Supply voltage
(VDD
)
1.6 V
0 V
Time
POR internal
signal
tPUP1
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 60 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.7 LCD Characteristics
2.7.1 Resistance division method
(1) Static display mode
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
2.0
TYP.
TYP.
TYP.
MAX.
VDD
40
Unit
V
LCD drive voltage
VL4
LCD output resistorNote
(Common)
LCD output resistorNote
(Segment)
RODC
IO = ±5 μA
IO = ±1 μA
kΩ
ROCS
200
kΩ
(2) 1/2 bias method, 1/4 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
2.7
MAX.
VDD
40
Unit
V
LCD drive voltage
VL4
LCD output resistorNote
(Common)
LCD output resistorNote
(Segment)
RODC
IO = ±5 μA
IO = ±1 μA
kΩ
ROCS
200
kΩ
(3) 1/3 bias method
(TA = −40 to +85°C, VL4 (MIN.) ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
2.5
MAX.
Unit
V
Note2
LCD drive voltage
VL4
VDD
LCD output resistorNote1
(Common)
LCD output resistorNote1
(Segment)
RODC
IO = ±5 μA
IO = ±1 μA
40
kΩ
ROCS
200
kΩ
Notes 1. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
2. 5.5 V (MAX) when driving a memory-type liquid crystal (the MLCDEN bit of the MLCD register = 1).
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 61 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.7.2 Internal voltage boosting method
(1) 1/3 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
C1 to C4Note 1
= 0.47 μFNote 2
MIN.
TYP.
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
2 VL1
MAX.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
2 VL1
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD output voltage variation range VL1
VLCD = 02H
VLCD = 03H
VLCD = 04H
VLCD = 05H
VLCD = 06H
VLCD = 07H
VLCD = 08H
VLCD = 09H
VLCD = 0AH
VLCD = 0BH
VLCD = 0CH
VLCD = 0DH
VLCD = 0EH
VLCD = 0FH
VLCD = 10H
VLCD = 11H
VLCD = 12H
VLCD = 13H
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
Doubler output voltage
Tripler output voltage
VL2
VL3
C1 to C4Note 1 = 0.47 μF
2 VL1
−0.1
C1 to C4Note 1 = 0.47 μF
3 VL1
3 VL1
3 VL1
V
−0.15
Reference voltage setup timeNote 2
Voltage boost wait timeNote 3
tVWAIT1
tVWAIT2
5
ms
ms
ms
kΩ
kΩ
C1 to C4Note 1 = 0.47 μF
VDD > VL4
500
T.B.D.
LCD output resistorNote 4 (Common)
LCD output resistorNote 4 (Segment) ROCS
RODC
IO = ±5 μA
40
IO = ±1 μA
200
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register
(or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of
the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts
(VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON
= 1).
4. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 62 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
(2) 1/4 bias method
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter
Symbol
Conditions
C1 to C5Note 1
= 0.47 μFNote 2
MIN.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
2 VL1−0.08
3 VL1−0.12
4 VL1−0.16
5
TYP.
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
2 VL1
3 VL1
4 VL1
MAX.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
T.B.D.
2 VL1
Unit
V
LCD output voltage variation range VL1
VLCD = 02H
VLCD = 03H
VLCD = 04H
VLCD = 05H
VLCD = 06H
VLCD = 07H
VLCD = 08H
VLCD = 09H
VLCD = 0AH
VLCD = 0BH
VLCD = 0CH
VLCD = 0DH
VLCD = 0EH
VLCD = 0FH
VLCD = 10H
VLCD = 11H
VLCD = 12H
VLCD = 13H
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Doubler output voltage
VL2
C1 to C5Note 1 = 0.47 μF
C1 to C5Note 1 = 0.47 μF
C1 to C5Note 1 = 0.47 μF
V
Tripler output voltage
VL3
3 VL1
V
Quadruply output voltage
Reference voltage setup timeNote 2
Voltage boost wait timeNote 3
VL4
4 VL1
V
tVWAIT1
tVWAIT2
ms
ms
C1 to C5Note 1 = 0.47 μF
500
VDD > VL4
IO = ±5 μA
IO = ±1 μA
T.B.D.
ms
kΩ
kΩ
LCD output resistorNote 4 (Common) RODC
LCD output resistorNote 4 (Segment) ROCS
40
200
Notes 1. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL3 and GND
C5: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = C5 = 0.47 pF±30 %
2. This is the time required to wait from when the reference voltage is specified by using the VLCD register
(or when the internal voltage boosting method is selected [by setting the MDSET1 and MDSET0 bits of
the LCDM0 register to 01B] if the default value reference voltage is used) until voltage boosting starts
(VLCON = 1).
3. This is the wait time from when voltage boosting is started (VLCON = 1) until display is enabled (LCDON
= 1).
4. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 63 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.7.3 Capacitor split method
(1) 1/3 bias method
(TA = −40 to +85°C, 2.2 V ≤ VDD = EVDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
C1 to C4 = 0.47 μ FNote 3
MIN.
TYP.
VDD
MAX.
Unit
V
VL4 voltage
VL2 voltage
VL4
VL2
C1 to C4 = 0.47 μ FNote 3
2/3 VL4
2/3 VL4
2/3 VL4
+0.1
V
−0.1
VL1 voltage
VL1
C1 to C4 = 0.47 μ FNote 3
1/3 VL4
1/3 VL4
1/3 VL4
+0.1
V
−0.1
Capacitor split wait timeNote 1
tVWAIT
100
ms
LCD output resistorNote 2
(Common)
LCD output resistorNote 2
(Segment)
RODC
40
kΩ
IO = ±5 μA
IO = ±1 μA
ROCS
200
kΩ
Notes 1. This is the wait time from when voltage bucking is started (VLCON = 1) until display is enabled (LCDON
= 1).
2. The output resistor is a resistor connected between one of the VL1, VL2, VL3, VL4 and VSS pins, and either
of the SEG and COM pins.
3. This is a capacitor that is connected between voltage pins used to drive the LCD.
C1: A capacitor connected between CAPH and CAPL
C2: A capacitor connected between VL1 and GND
C3: A capacitor connected between VL2 and GND
C4: A capacitor connected between VL4 and GND
C1 = C2 = C3 = C4 = 0.47 pF±30 %
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 64 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
5.5
Unit
V
Data retention supply voltage
VDDDR
1.47Note
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a
POR reset is effected, but data is not retained when a POR reset is effected.
Operation mode
STOP mode
Data retention mode
V
DD
V
DDDR
STOP instruction execution
Standby release signal
(interrupt request)
2.9 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Parameter
Symbol
Conditions
MIN.
1
TYP.
MAX.
24
Unit
CPU/peripheral hardware clock
frequency
fCLK
1.8 V ≤ VDD ≤ 5.5 V
MHz
Number of code flash rewrites
Cerwr
1 erase + 1 write after Retained for 20 years 1,000
the erase is regarded (Self/serial
Times
as 1 rewrite.
programming)Note
The retaining years
are until next rewrite
after the rewrite.
Number of data flash rewrites
Retained for 1 years
(Self/serial
programming)Note
1,000,000
Retained for 5 years 100,000
(Self/serial
programming)Note
Note When using flash memory programmer and Renesas Electronics self programming library
Remark When updating data multiple times, use the flash memory as one for updating data.
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 65 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Caution The pins mounted depend on the product. Refer to 1.3.1 32-pin products to 1.3.5 64-pin
products.
2.10 Timing Specs for Switching Modes
Parameter
Symbol
tSUINIT
Conditions
MIN.
TYP.
MAX.
100
Unit
ms
How long from when a pin reset
ends until the initial communication
settings are specified
POR and LVD reset must end before the pin
reset ends.
How long from when the TOOL0
pin is placed at the low level until a
pin reset ends
tSU
POR and LVD reset must end before the pin
reset ends.
10
1
μ s
How long the TOOL0 pin must be
kept at the low level after a reset
ends
tHD
POR and LVD reset must end before the pin
reset ends.
ms
<1>
<2>
<3>
<4>
RESET
tHD+
software
processing
time
TOOL0
t
SUINIT
t
SU
<1> The low level is input to the TOOL0 pin.
<2> The pins reset ends (POR and LVD reset must end before the pin reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete
the baud rate setting.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the external and internal resets end.
tSU:
tHD:
How long from when the TOOL0 pin is placed at the low level until a pin reset ends
How long to keep the TOOL0 pin at the low level from when the external and internal resets end
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 66 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
3. PACKAGE DRAWINGS
3.1 32-pin products
R5F10RB8AFP, R5F10RBAAFP, R5F10RBCAFP
32-PIN PLASTIC LQFP(7x7)
HD
2D
17
16
24
25
detail of lead end
1
c
E
HE
θ
L
32
9
8
e
1
(UNIT:mm)
ITEM DIMENSIONS
3
M
b
x
D
E
7.00 0.10
7.00 0.10
9.00 0.20
9.00 0.20
1.70 MAX.
0.10 0.10
1.40
A
A2
HD
HE
A
A1
A2
b
0.37 0.05
y
A1
c
0.145 0.055
0.50 0.20
0° to 8°
L
NOTE
θ
e
x
y
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
0.80
0.20
0.10
P32GA-80-GBT
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 67 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
3.2 44-pin products
R5F10RF8AFP, R5F10RFAAFP, R5F10RFCAFP
44-PIN PLASTIC LQFP(10x10)
HD
D
detail of lead end
A3
c
23
22
33
34
θ
L
Lp
E
HE
L1
12
11
44
(UNIT:mm)
1
ITEM DIMENSIONS
D
E
10.00 0.20
10.00 0.20
12.00 0.20
12.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
ZE
HD
HE
A
e
ZD
M
b
x
S
A
A1
A2
A3
b
A2
+0.08
0.37
−0.07
S
+0.055
c
0.145
−0.045
L
0.50
y
Lp
L1
0.60 0.15
1.00 0.20
S
A1
+5°
3°
θ
−3°
e
x
0.80
0.20
0.10
1.00
NOTE
Each lead centerline is located within 0.20 mm of
its true position at maximum material condition.
y
ZD
ZE
1.00
P44GB-80-UES-1
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 68 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
3.3 48-pin products
R5F10RG8AFB, R5F10RGAAFB, R5F10RGCAFB
48-PIN PLASTIC LQFP (FINE PITCH)(7x7)
HD
D
detail of lead end
36
25
A3
c
37
24
θ
L
Lp
E
HE
L1
13
48
12
1
(UNIT:mm)
ITEM DIMENSIONS
ZE
D
E
7.00 0.20
7.00 0.20
9.00 0.20
9.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
e
ZD
HD
HE
A
M
b
x
S
A
A1
A2
A2
A3
b
0.22 0.05
+0.055
S
c
0.145
0.50
−0.045
L
Lp
L1
0.60 0.15
1.00 0.20
y
S
A1
+5°
3°
θ
−3°
e
x
0.50
0.08
0.08
0.75
NOTE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
y
ZD
ZE
0.75
P48GA-50-8EU
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 69 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
3.4 52-pin products
R5F10RJ8AFA, R5F10RJAAFA, R5F10RJCAFA
52-PIN PLASTIC LQFP (10x10)
HD
2
D
39
27
detail of lead end
40
26
c
1
E
HE
θ
L
14
e
52
1
13
(UNIT:mm)
3
b
ITEM DIMENSIONS
M
x
A
D
E
10.00 0.10
10.00 0.10
12.00 0.20
12.00 0.20
1.70 MAX.
0.10 0.05
1.40
A2
HD
HE
A
A1
A2
b
y
A1
0.32 0.05
c
0.145 0.055
NOTE
L
0.50 0.15
0° to 8°
0.65
1.Dimensions “ 1” and “ 2” do not include mold flash.
2.Dimension “ 3” does not include trim offset.
θ
e
x
y
0.13
0.10
P52GB-65-GBS
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 70 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
3.5 64-pin products
R5F10RLAAFA, R5F10RLCAFA
64-PIN PLASTIC LQFP(12x12)
HD
D
detail of lead end
48
49
33
32
A3
c
θ
L
Lp
E
HE
L1
(UNIT:mm)
ITEM DIMENSIONS
17
e
64
1
D
E
12.00 0.20
12.00 0.20
14.00 0.20
14.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
16
HD
HE
A
ZE
ZD
A1
A2
A3
b
M
b
x
S
A
A2
+0.08
0.32
−0.07
+0.055
c
0.145
−0.045
S
L
0.50
Lp
L1
0.60 0.15
1.00 0.20
y
A1
S
+5°
3°
θ
−3°
e
x
0.65
0.13
0.10
1.125
NOTE
y
Each lead centerline is located within 0.13 mm of
its true position at maximum material condition.
ZD
ZE
1.125
P64GK-65-UET-1
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 71 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
R5F10RLAAFB, R5F10RLCAFB
64-PIN PLASTIC LQFP(FINE PITCH)(10x10)
HD
D
detail of lead end
48
33
A3
c
49
32
θ
L
Lp
E
HE
L1
(UNIT:mm)
17
64
ITEM DIMENSIONS
1
16
D
E
10.00 0.20
10.00 0.20
12.00 0.20
12.00 0.20
1.60 MAX.
0.10 0.05
1.40 0.05
0.25
HD
HE
A
ZE
e
ZD
A1
A2
M
b
x
S
A
A3
b
A2
0.22 0.05
+0.055
0.145
c
−0.045
L
0.50
S
Lp
L1
0.60 0.15
1.00 0.20
+5°
3°
θ
y
−3°
S
A1
e
x
0.50
0.08
0.08
1.25
y
NOTE
ZD
ZE
Each lead centerline is located within 0.08 mm of
its true position at maximum material condition.
1.25
P64GB-50-UEU-1
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 72 of 73
Preliminary document
Under development
Specifications in this document are tentative and subject to change.
RL78/L12
3. PACKAGE DRAWINGS
R5F10RLAANB, R5F10RLCANB
64-PIN PLASTICWQFN(8x8)
D
DETAIL OF A PART
E
A
S
A
S
y
S
A
D2
(UNIT:mm)
EXPOSED DIE PAD
ITEM DIMENSIONS
D
E
A
b
8.00 0.05
8.00 0.05
0.75 0.05
1
16
64
17
0.05
0.20
0.40
e
Lp
x
B
0.40 0.10
0.05
E2
y
0.05
P64K8-40-9B5
D2
E2
32
49
ITEM
MIN NOM MAX MIN NOM MAX
EXPOSED
DIE PAD
VARIATIONS
33
48
A
6.45 6.50 6.55 6.45 6.50 6.55
Lp
e
M
b
x
S A B
R01DS0157EJ0001 Rev.0.01
2012.02.20
Page 73 of 73
Revision History
RL78/L12 Data Sheet
Description
Summary
Rev.
0.01
Date
Page
Feb 20, 2012
-
First Edition issued
All trademarks and registered trademarks are the property of their respective owners.
C - 1
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work benches and floors should be grounded. The operator should be grounded using a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers.
A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device and according to related specifications governing the device.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard":
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific":
Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to
redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult,
please evaluate the safety of the final products or system manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics
products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes
no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/" for the latest and detailed information.
Renesas Electronics America Inc.
2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A.
Tel: +1-408-588-6000, Fax: +1-408-588-6130
Renesas Electronics Canada Limited
1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada
Tel: +1-905-898-5441, Fax: +1-905-898-3220
Renesas Electronics Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K
Tel: +44-1628-585-100, Fax: +44-1628-585-900
Renesas Electronics Europe GmbH
Arcadiastrasse 10, 40472 Düsseldorf, Germany
Tel: +49-211-65030, Fax: +49-211-6503-1327
Renesas Electronics (China) Co., Ltd.
7th Floor, Quantum Plaza, No.27 ZhiChunLu Haidian District, Beijing 100083, P.R.China
Tel: +86-10-8235-1155, Fax: +86-10-8235-7679
Renesas Electronics (Shanghai) Co., Ltd.
Unit 204, 205, AZIA Center, No.1233 Lujiazui Ring Rd., Pudong District, Shanghai 200120, China
Tel: +86-21-5877-1818, Fax: +86-21-6887-7858 / -7898
Renesas Electronics Hong Kong Limited
Unit 1601-1613, 16/F., Tower 2, Grand Century Place, 193 Prince Edward Road West, Mongkok, Kowloon, Hong Kong
Tel: +852-2886-9318, Fax: +852 2886-9022/9044
Renesas Electronics Taiwan Co., Ltd.
13F, No. 363, Fu Shing North Road, Taipei, Taiwan
Tel: +886-2-8175-9600, Fax: +886 2-8175-9670
Renesas Electronics Singapore Pte. Ltd.
1 harbourFront Avenue, #06-10, keppel Bay Tower, Singapore 098632
Tel: +65-6213-0200, Fax: +65-6278-8001
Renesas Electronics Malaysia Sdn.Bhd.
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: +60-3-7955-9390, Fax: +60-3-7955-9510
Renesas Electronics Korea Co., Ltd.
11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea
Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2012 Renesas Electronics Corporation. All rights reserved.
Colophon 1.1
相关型号：
R5F10RG8AFB
Integrated LCD controller/driver, True Low Power Platform (as low as 75 μA/MHz, and 0.64 μA for RTC + LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Appli
RENESAS
R5F10RGAAFB
Integrated LCD controller/driver, True Low Power Platform (as low as 75 μA/MHz, and 0.64 μA for RTC + LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Appli
RENESAS
R5F10RGCAFB
Integrated LCD controller/driver, True Low Power Platform (as low as 75 μA/MHz, and 0.64 μA for RTC + LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Appli
RENESAS
©2020 ICPDF网 联系我们和版权申明